1 /*! 2 \file gd32e50x_rcu.h 3 \brief definitions for the RCU 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50X 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2020-09-20, V1.1.1, firmware for GD32E50x 8 \version 2021-03-23, V1.2.0, firmware for GD32E50x 9 */ 10 11 /* 12 Copyright (c) 2021, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E50X_RCU_H 39 #define GD32E50X_RCU_H 40 41 #include "gd32e50x.h" 42 43 /* RCU definitions */ 44 #define RCU RCU_BASE 45 46 /* registers definitions */ 47 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)) 48 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */ 49 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration register 0 */ 50 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt register */ 51 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 52 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 53 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ 54 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 55 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 56 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 57 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock register */ 58 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration register 1 */ 59 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltage register */ 60 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock control register */ 61 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock interrupt register */ 62 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset register */ 63 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable register */ 64 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration register 2 */ 65 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset register */ 66 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable register */ 67 #elif defined(GD32E50X_CL) || defined(GD32E508) 68 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */ 69 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration register 0 */ 70 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt register */ 71 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 72 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 73 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */ 74 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 75 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 76 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 77 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock register */ 78 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ 79 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration register 1 */ 80 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltage register */ 81 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock control register */ 82 #define RCU_ADDCFG REG32(RCU + 0x000000C4U) /*!< Additional clock configuration register */ 83 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock interrupt register */ 84 #define RCU_PLLSSCTL REG32(RCU + 0x000000D0U) /*!< PLL clock spread spectrum control register */ 85 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration register 2 */ 86 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset register */ 87 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable register */ 88 #elif defined(GD32EPRT) 89 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */ 90 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration register 0 */ 91 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt register */ 92 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 93 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 94 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */ 95 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 96 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 97 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 98 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock register */ 99 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ 100 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration register 1 */ 101 #define RCU_DSV REG32(RCU + 0x00000034U) /*!< deep-sleep mode voltage register */ 102 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< Additional clock control register */ 103 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< Additional clock interrupt register */ 104 #define RCU_PLLSSCTL REG32(RCU + 0x000000D0U) /*!< PLL clock spread spectrum control register */ 105 #define RCU_CFG2 REG32(RCU + 0x000000D4U) /*!< clock configuration register 2 */ 106 #define RCU_ADDAPB1RST REG32(RCU + 0x000000E0U) /*!< APB1 additional reset register */ 107 #define RCU_ADDAPB1EN REG32(RCU + 0x000000E4U) /*!< APB1 additional enable register */ 108 #endif /* GD32E50X_HD and GD32E50X_XD */ 109 110 /* bits definitions */ 111 /* RCU_CTL */ 112 #if defined(GD32E50X_HD) || defined(GD32E50X_XD) 113 #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 114 #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 115 #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 116 #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 117 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 118 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 119 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 120 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 121 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 122 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 123 #elif defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 124 #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 125 #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 126 #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 127 #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 128 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 129 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 130 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 131 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 132 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 133 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 134 #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ 135 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ 136 #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ 137 #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ 138 #endif /* GD32E50X_HD and GD32E50X_XD*/ 139 140 /* RCU_CFG0 */ 141 #if defined(GD32E50X_HD) || defined(GD32E50X_XD) 142 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 143 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 144 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 145 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 146 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 147 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ 148 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 149 #define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ 150 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 151 #define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ 152 #define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ 153 #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ 154 #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ 155 #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ 156 #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ 157 #elif defined(GD32E50X_CL) || defined(GD32E508) 158 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 159 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 160 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 161 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 162 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 163 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ 164 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 165 #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ 166 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 167 #define RCU_CFG0_USBHSPSC BITS(22,23) /*!< USBHS clock prescaler selection */ 168 #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ 169 #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ 170 #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ 171 #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ 172 #define RCU_CFG0_USBHSPSC_2 BIT(31) /*!< bit 2 of USBHSPSC */ 173 #elif defined(GD32EPRT) 174 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 175 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 176 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 177 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 178 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 179 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ 180 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 181 #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ 182 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 183 #define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ 184 #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ 185 #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ 186 #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ 187 #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ 188 #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ 189 #endif /* GD32E50X_HD and GD32E50X_XD */ 190 191 /* RCU_INT */ 192 #if defined(GD32E50X_HD) || defined(GD32E50X_XD) 193 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 194 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 195 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 196 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 197 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 198 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 199 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 200 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 201 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 202 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 203 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 204 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ 205 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ 206 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ 207 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ 208 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 209 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 210 #elif defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 211 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 212 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 213 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 214 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 215 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 216 #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ 217 #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ 218 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 219 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 220 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 221 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 222 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 223 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 224 #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ 225 #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ 226 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ 227 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 228 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ 229 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 230 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 231 #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ 232 #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ 233 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 234 #endif /* GD32E50X_HD and GD32E50X_XD */ 235 236 /* RCU_APB2RST */ 237 #define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ 238 #define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ 239 #define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ 240 #define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ 241 #define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ 242 #define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ 243 #define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ 244 #define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ 245 #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ 246 #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ 247 #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ 248 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 249 #define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ 250 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 251 #if defined(GD32E50X_XD) || defined(GD32E50X_HD) || defined(GD32EPRT) 252 #define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ 253 #endif /* GD32E50X_XD and GD32E50X_HDand GD32EPRT */ 254 #ifndef GD32EPRT 255 #define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ 256 #define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ 257 #define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ 258 #endif /* GD32EPRT*/ 259 #define RCU_APB2RST_USART5RST BIT(28) /*!< USART5 reset */ 260 #ifndef GD32EPRT 261 #define RCU_APB2RST_SHRTIMERRST BIT(29) /*!< HPTIME reset */ 262 #endif /* GD32EPRT */ 263 #if defined(GD32E50X_CL) || defined(GD32E508) 264 #define RCU_APB2RST_CMPRST BIT(31) /*!< CMP reset */ 265 #endif /* GD32E50X_CL and GD32E508 */ 266 267 /* RCU_APB1RST */ 268 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ 269 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ 270 #define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ 271 #define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ 272 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ 273 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ 274 #ifndef GD32EPRT 275 #define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ 276 #define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ 277 #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ 278 #endif /* GD32EPRT */ 279 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ 280 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 281 #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ 282 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 283 #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ 284 #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ 285 #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ 286 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 287 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 288 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 289 #define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ 290 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 291 #define RCU_APB1RST_I2C2RST BIT(24) /*!< I2C2 reset */ 292 #ifndef GD32EPRT 293 #define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ 294 #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ 295 #endif /* GD32EPRT */ 296 #define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ 297 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ 298 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 299 300 /* RCU_AHBEN */ 301 #define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ 302 #define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ 303 #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ 304 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ 305 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 306 #define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ 307 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)) 308 #define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ 309 #elif defined(GD32E50X_CL) || defined(GD32E508) 310 #define RCU_AHBEN_USBHSEN BIT(12) /*!< USBHS clock enable */ 311 #define RCU_AHBEN_ULPIEN BIT(13) /*!< ULPI clock enable */ 312 #define RCU_AHBEN_TMUEN BIT(30) /*!< TMU clock enable */ 313 #endif /* GD32E50X_HD and GD32E50X_XD */ 314 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 315 #define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ 316 #define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ 317 #define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ 318 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 319 #define RCU_AHBEN_SQPIEN BIT(31) /*!< SQPI clock enable */ 320 321 /* RCU_APB2EN */ 322 #define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ 323 #define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ 324 #define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ 325 #define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ 326 #define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ 327 #define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ 328 #define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ 329 #define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ 330 #define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ 331 #define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ 332 #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ 333 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 334 #define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ 335 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 336 #if defined(GD32E50X_XD) || defined(GD32E50X_HD) || defined(GD32EPRT) 337 #define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ 338 #endif /* GD32E50X_XD and GD32E50X_HDand GD32EPRT */ 339 #ifndef GD32EPRT 340 #define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ 341 #define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ 342 #define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ 343 #endif /* GD32EPRT */ 344 #define RCU_APB2EN_USART5EN BIT(28) /*!< USART5 clock enable */ 345 #ifndef GD32EPRT 346 #define RCU_APB2EN_SHRTIMEREN BIT(29) /*!< SHRTIMER clock enable */ 347 #endif /* GD32EPRT */ 348 #if defined(GD32E50X_CL) || defined(GD32E508) 349 #define RCU_APB2EN_CMPEN BIT(31) /*!< CMP clock enable */ 350 #endif /* GD32E50X_CL and GD32E508 */ 351 352 /* RCU_APB1EN */ 353 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ 354 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ 355 #define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ 356 #define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ 357 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ 358 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ 359 #ifndef GD32EPRT 360 #define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ 361 #define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ 362 #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ 363 #endif /* GD32EPRT */ 364 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ 365 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 366 #define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ 367 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 368 #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ 369 #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ 370 #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ 371 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 372 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 373 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 374 #define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ 375 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 376 #define RCU_APB1EN_I2C2EN BIT(24) /*!< I2C2 clock enable */ 377 #ifndef GD32EPRT 378 #define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ 379 #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ 380 #endif /* GD32EPRT */ 381 #define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ 382 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ 383 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 384 385 /* RCU_BDCTL */ 386 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 387 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ 388 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 389 #define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ 390 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 391 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 392 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 393 394 /* RCU_RSTSCK */ 395 #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ 396 #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ 397 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 398 #define RCU_RSTSCK_BORRSTF BIT(25) /*!< BOR reset flag */ 399 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 400 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 401 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 402 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 403 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 404 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 405 406 #if defined(GD32E50X_CL) || defined(GD32E508) 407 /* RCU_AHBRST */ 408 #define RCU_AHBRST_USBHSRST BIT(12) /*!< USBHS reset */ 409 #define RCU_AHBRST_TMURST BIT(30) /*!< TMU reset */ 410 #endif /* GD32E50X_CL and GD32E508 */ 411 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 412 #define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ 413 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 414 #define RCU_AHBRST_SQPIRST BIT(31) /*!< SQPI reset */ 415 416 /* RCU_CFG1 */ 417 #define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ 418 #define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ 419 #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ 420 #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ 421 #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ 422 #if defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 423 #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ 424 #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ 425 #define RCU_CFG1_PLL2MF_5 BIT(28) /*!< bit 6 of PLL2MF */ 426 #define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ 427 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 428 #ifndef GD32EPRT 429 #define RCU_CFG1_SHRTIMERSEL BIT(19) /*!< SHRTIMER clock source selection */ 430 #endif /* GD32EPRT */ 431 #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ 432 #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ 433 434 /* RCU_DSV */ 435 #define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ 436 437 /* RCU_ADDCTL */ 438 #define RCU_ADDCTL_CK48MSEL BITS(0,1) /*!< 48MHz clock selection */ 439 #if defined(GD32E50X_CL) || defined(GD32E508) 440 #define RCU_ADDCTL_USBHSSEL BIT(2) /*!< USBHS clock selection */ 441 #define RCU_ADDCTL_USBHSDV BITS(3,5) /*!< USBHS clock divider factor */ 442 #define RCU_ADDCTL_USBSWEN BIT(6) /*!< USB clock source selection enable */ 443 #define RCU_ADDCTL_PLLUSBEN BIT(14) /*!< PLLUSB enable */ 444 #define RCU_ADDCTL_PLLUSBSTB BIT(15) /*!< PLLUSB clock stabilization flag */ 445 #endif /* GD32E50X_CL and GD32E508 */ 446 #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ 447 #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ 448 #define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ 449 450 /* RCU_ADDCFG */ 451 #if defined(GD32E50X_CL) || defined(GD32E508) 452 #define RCU_ADDCFG_PLLUSBPREDV BITS(0,3) /*!< PLLUSBPREDV division factor */ 453 #define RCU_ADDCFG_PLLUSBPRESEL BIT(16) /*!< PLLUSB clock source preselection */ 454 #define RCU_ADDCFG_PLLUSBPREDVSEL BIT(17) /*!< PLLUSBPREDV input Clock Source Selection */ 455 #define RCU_ADDCFG_PLLUSBMF BITS(18,24) /*!< The PLLUSB clock multiplication factor */ 456 #endif /* GD32E50X_CL and GD32E508 */ 457 458 /* RCU_ADDINT */ 459 #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ 460 #define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ 461 #define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 462 #if defined(GD32E50X_CL) || defined(GD32E508) 463 #define RCU_ADDINT_PLLUSBSTBIF BIT(7) /*!< PLLUSB stabilization interrupt flag */ 464 #define RCU_ADDINT_PLLUSBSTBIE BIT(15) /*!< PLLUSB stabilization interrupt enable */ 465 #define RCU_ADDINT_PLLUSBSTBIC BIT(23) /*!< PLLUSB stabilization interrupt clear */ 466 #endif /* GD32E50X_CL and GD32E508 */ 467 468 /* RCU_PLLSSCTL */ 469 #define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation 470 profile amplitude and frequency. the following criteria 471 must be met: MODSTEP*MODCNT=215-1 */ 472 #define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation 473 profile amplitude and frequency. the following criteria 474 must be met: MODSTEP*MODCNT=215-1 */ 475 #define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ 476 #define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ 477 478 /* RCU_CFG2 */ 479 #define RCU_CFG2_USART5SEL BITS(0,1) /*!< USART5 Clock Source Selection */ 480 #define RCU_CFG2_I2C2SEL BITS(4,5) /*!< I2C2 Clock Source Selection */ 481 482 /* RCU_ADDAPB1RST */ 483 #define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ 484 #if defined(GD32E50X_CL) || defined(GD32E508) 485 #define RCU_ADDAPB1RST_CAN2RST BIT(31) /*!< CAN2 reset */ 486 #endif /* GD32E50X_CL and GD32E508 */ 487 488 /* RCU_ADDAPB1EN */ 489 #define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ 490 #if defined(GD32E50X_CL) || defined(GD32E508) 491 #define RCU_ADDAPB1EN_CAN2EN BIT(31) /*!< CAN2 clock enable */ 492 #endif /* GD32E50X_CL and GD32E508 */ 493 494 /* constants definitions */ 495 /* define the peripheral clock enable bit position and its register index offset */ 496 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 497 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) 498 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 499 500 /* register offset */ 501 /* peripherals enable */ 502 #define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ 503 #define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ 504 #define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ 505 #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ 506 507 /* peripherals reset */ 508 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ 509 #define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ 510 #define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ 511 #define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ 512 #define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ 513 514 /* clock control */ 515 #define CTL_REG_OFFSET 0x00U /*!< control register offset */ 516 #define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ 517 #define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ 518 #define PLLSSCTL_REG_OFFSET 0xD0U /*!<PLL clock spread spectrum control register offset */ 519 520 /* clock stabilization and stuck interrupt */ 521 #define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ 522 #define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ 523 524 /* configuration register */ 525 #define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ 526 #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ 527 #define ADDCFG_REG_OFFSET 0xC4U /*!< Additional clock configuration register offset */ 528 529 /* peripheral clock enable */ 530 typedef enum 531 { 532 /* AHB peripherals */ 533 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ 534 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ 535 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ 536 RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ 537 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)) 538 RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ 539 #elif defined(GD32E50X_CL) || defined(GD32E508) 540 RCU_USBHS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBHS clock */ 541 RCU_ULPI = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 13U), /*!< ULPI clock */ 542 RCU_TMU = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 30U), /*!< TMU clock */ 543 #endif /* GD32E50X_HD and GD32E50X_XD */ 544 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 545 RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ 546 RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ 547 RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ 548 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 549 RCU_SQPI = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 31U), /*!< SQPI clock */ 550 551 /* APB1 peripherals */ 552 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 553 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 554 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ 555 RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ 556 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 557 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 558 #ifndef GD32EPRT 559 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ 560 RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ 561 RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ 562 #endif /* GD32EPRT */ 563 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 564 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 565 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ 566 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 567 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ 568 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ 569 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ 570 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 571 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 572 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 573 RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ 574 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 575 RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 24U), /*!< I2C2 clock */ 576 #ifndef GD32EPRT 577 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ 578 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ 579 #endif /* GD32EPRT */ 580 RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ 581 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 582 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 583 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ 584 RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ 585 #if defined(GD32E50X_CL) || defined(GD32E508) 586 RCU_CAN2 = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< CAN2 clock */ 587 #endif /* GD32E50X_CL and GD32E508 */ 588 589 /* APB2 peripherals */ 590 RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ 591 RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ 592 RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ 593 RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ 594 RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ 595 RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ 596 RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ 597 RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ 598 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ 599 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ 600 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ 601 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 602 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ 603 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ 604 #ifndef GD32E50X_CL 605 RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ 606 #endif /* GD32E50X_CL */ 607 #ifndef GD32EPRT 608 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ 609 RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ 610 RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ 611 #endif /* GD32EPRT */ 612 #ifndef GD32EPRT 613 RCU_SHRTIMER = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 29U), /*!< SHRTIMER clock */ 614 #endif /* GD32EPRT */ 615 RCU_USART5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 28U), /*!< USART5 clock */ 616 #if defined(GD32E50X_CL) || defined(GD32E508) 617 RCU_CMP = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 31U), /*!< CMP clock */ 618 #endif /* GD32E50X_CL and GD32E508 */ 619 }rcu_periph_enum; 620 621 /* peripheral clock enable when sleep mode*/ 622 typedef enum 623 { 624 /* AHB peripherals */ 625 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock when sleep mode */ 626 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock when sleep mode */ 627 }rcu_periph_sleep_enum; 628 629 /* peripherals reset */ 630 typedef enum 631 { 632 /* AHB peripherals */ 633 #if defined(GD32E50X_CL) || defined(GD32E508) 634 RCU_USBHSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBHS clock reset */ 635 RCU_TMURST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 30U), /*!< TMU clock reset */ 636 #endif /* GD32E50X_CL and GD32E508 */ 637 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 638 RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ 639 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 640 RCU_SQPIRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 31U), /*!< SQPI clock reset */ 641 642 /* APB1 peripherals */ 643 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ 644 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ 645 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ 646 RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ 647 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ 648 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ 649 #ifndef GD32EPRT 650 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ 651 RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ 652 RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ 653 #endif /* GD32EPRT */ 654 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ 655 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ 656 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ 657 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ 658 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ 659 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ 660 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ 661 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ 662 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ 663 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 664 RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ 665 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 666 RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 24U), /*!< I2C2 clock reset */ 667 #ifndef GD32EPRT 668 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ 669 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ 670 #endif /* GD32EPRT */ 671 RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ 672 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ 673 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ 674 RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ 675 #if defined(GD32E50X_CL) || defined(GD32E508) 676 RCU_CAN2RST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U), /*!< CAN2 clock reset */ 677 #endif /* GD32E50X_CL and GD32E508 */ 678 679 /* APB2 peripherals */ 680 RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ 681 RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ 682 RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ 683 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ 684 RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ 685 RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ 686 RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ 687 RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ 688 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ 689 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ 690 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ 691 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ 692 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ 693 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ 694 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 695 RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ 696 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 697 #ifndef GD32EPRT 698 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ 699 RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ 700 RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ 701 #endif /* GD32EPRT */ 702 RCU_USART5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 28U), /*!< USART5 clock reset */ 703 #ifndef GD32EPRT 704 RCU_SHRTIMERRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 29U), /*!< HPTIEMR clock reset */ 705 #endif /* GD32EPRT */ 706 #if defined(GD32E50X_CL) || defined(GD32E508) 707 RCU_CMPRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 31U), /*!< CMP clock reset */ 708 #endif /* GD32E50X_CL and GD32E508 */ 709 }rcu_periph_reset_enum; 710 711 /* clock stabilization and peripheral reset flags */ 712 typedef enum 713 { 714 /* clock stabilization flags */ 715 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ 716 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ 717 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ 718 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 719 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ 720 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ 721 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 722 #if defined(GD32E50X_CL) || defined(GD32E508) 723 RCU_FLAG_PLLUSBSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 15U), /*!< PLLUSB stabilization flags */ 724 #endif /* GD32E50X_CL and GD32E508 */ 725 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ 726 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ 727 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ 728 /* reset source flags */ 729 RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< BOR reset flag */ 730 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ 731 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ 732 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ 733 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ 734 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ 735 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ 736 737 }rcu_flag_enum; 738 739 /* clock stabilization and ckm interrupt flags */ 740 typedef enum 741 { 742 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ 743 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 744 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ 745 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 746 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 747 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 748 RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ 749 RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ 750 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 751 #if defined(GD32E50X_CL) || defined(GD32E508) 752 RCU_INT_FLAG_PLLUSBSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 7U), /*!< PLLUSB stabilization interrupt flag */ 753 #endif /* GD32E50X_CL and GD32E508 */ 754 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ 755 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ 756 757 }rcu_int_flag_enum; 758 759 /* clock stabilization and stuck interrupt flags clear */ 760 typedef enum 761 { 762 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ 763 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ 764 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ 765 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ 766 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ 767 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 768 RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ 769 RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ 770 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 771 #if defined(GD32E50X_CL) || defined(GD32E508) 772 RCU_INT_FLAG_PLLUSBSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 23U), /*!< PLLUSB stabilization interrupt flags clear */ 773 #endif /* GD32E50X_CL and GD32E508 */ 774 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ 775 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 776 }rcu_int_flag_clear_enum; 777 778 /* clock stabilization interrupt enable or disable */ 779 typedef enum 780 { 781 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ 782 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ 783 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ 784 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ 785 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ 786 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 787 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ 788 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ 789 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 790 #if (defined(GD32E50X_CL) || defined(GD32E508)) 791 RCU_INT_PLLUSBSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 15U), /*!< PLLUSB stabilization interrupt */ 792 #endif /* GD32E50X_CL and GD32E508 */ 793 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ 794 }rcu_int_enum; 795 796 /* oscillator types */ 797 typedef enum 798 { 799 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 800 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 801 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ 802 RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ 803 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ 804 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ 805 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 806 RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ 807 RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ 808 #endif /* GD32E50X_CL and GD32EPRT and GD32E508*/ 809 #if defined(GD32E50X_CL) || defined(GD32E508) 810 RCU_PLLUSB_CK = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 14U), /*!< PLLUSB */ 811 #endif /* GD32E50X_CL and GD32E508 */ 812 }rcu_osci_type_enum; 813 814 /* rcu clock frequency */ 815 typedef enum 816 { 817 CK_SYS = 0, /*!< system clock */ 818 CK_AHB, /*!< AHB clock */ 819 CK_APB1, /*!< APB1 clock */ 820 CK_APB2, /*!< APB2 clock */ 821 CK_USART /*!< USART5 clock */ 822 }rcu_clock_freq_enum; 823 824 /* RCU_CFG0 register bit define */ 825 /* system clock source select */ 826 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 827 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ 828 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 829 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 830 831 /* system clock source select status */ 832 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 833 #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ 834 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 835 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ 836 837 /* AHB prescaler selection */ 838 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 839 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 840 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 841 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 842 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 843 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 844 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 845 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 846 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 847 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 848 849 /* APB1 prescaler selection */ 850 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 851 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 852 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 853 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 854 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 855 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 856 857 /* APB2 prescaler selection */ 858 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) 859 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 860 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 861 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 862 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 863 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 864 865 /* ADC prescaler select */ 866 #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ 867 #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ 868 #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ 869 #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ 870 #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ 871 #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ 872 #define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ 873 #define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ 874 #define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ 875 #define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ 876 877 /* PLL clock source selection */ 878 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ 879 #define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ 880 881 /* PLL clock multiplication factor */ 882 #define PLLMF_4 RCU_CFG0_PLLMF_4 /*!< bit 4 of PLLMF */ 883 #define PLLMF_5 RCU_CFG0_PLLMF_5 /*!< bit 5 of PLLMF */ 884 #define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /*!< bit 4 and 5 of PLLMF */ 885 886 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) 887 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ 888 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ 889 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ 890 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ 891 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ 892 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ 893 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ 894 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ 895 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ 896 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ 897 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ 898 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ 899 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ 900 #if defined(GD32E50X_HD) || defined(GD32E50X_XD) 901 #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ 902 #elif defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 903 #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ 904 #endif /* GD32E50X_HD and GD32E50X_XD */ 905 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ 906 #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ 907 #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ 908 #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ 909 #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ 910 #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ 911 #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ 912 #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ 913 #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ 914 #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ 915 #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ 916 #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ 917 #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ 918 #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ 919 #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ 920 #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ 921 #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ 922 #define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ 923 #define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ 924 #define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ 925 #define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ 926 #define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ 927 #define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ 928 #define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ 929 #define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ 930 #define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ 931 #define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ 932 #define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ 933 #define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ 934 #define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ 935 #define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ 936 #define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ 937 #define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ 938 #define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ 939 #define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ 940 #define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ 941 #define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ 942 #define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ 943 #define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ 944 #define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ 945 #define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ 946 #define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ 947 #define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ 948 #define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ 949 #define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ 950 #define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ 951 #define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ 952 #define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ 953 #define RCU_PLL_MUL64 (PLLMF_4_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 64 */ 954 955 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32EPRT)) 956 #define USBPSC_2 RCU_CFG0_USBDPSC_2 957 #elif defined(GD32E50X_CL) || defined(GD32E508) 958 #define USBPSC_2 RCU_CFG0_USBHSPSC_2 959 #endif /* GD32E50X_HD and GD32E50X_XD and GD32EPRT */ 960 961 /* USBD/USBHS prescaler select */ 962 #define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) 963 #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBHS prescaler select CK_PLL/1.5 */ 964 #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBHS prescaler select CK_PLL/1 */ 965 #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBHS prescaler select CK_PLL/2.5 */ 966 #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBHS prescaler select CK_PLL/2 */ 967 #define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBHS prescaler select CK_PLL/3 */ 968 #define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBHS prescaler select CK_PLL/3.5 */ 969 #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBHS prescaler select CK_PLL/4 */ 970 971 /* CKOUT0 Clock source selection */ 972 #define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 973 #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ 974 #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ 975 #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ 976 #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ 977 #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ 978 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 979 #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ 980 #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ 981 #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ 982 #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ 983 #define RCU_CKOUT0SRC_CKIRC48M CFG0_CKOUT0SEL(12) /*!< CK_IRC48M clock selected */ 984 #define RCU_CKOUT0SRC_CKIRC48M_DIV8 CFG0_CKOUT0SEL(13) /*!< CK_IRC48M/8 clock selected */ 985 #endif /* GD32E50X_CL and GD32EPRT and GD32E508*/ 986 #if defined(GD32E50X_CL) || defined(GD32E508) 987 #define RCU_CKOUT0SRC_CKPLLUSB_DIV32 CFG0_CKOUT0SEL(14) /*!< CK_PLLUSB/32 clock selected */ 988 #endif /* GD32E50X_CL and GD32E508 */ 989 990 /* LXTAL drive capability */ 991 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) 992 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ 993 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ 994 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ 995 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ 996 997 /* RTC clock entry selection */ 998 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 999 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 1000 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ 1001 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ 1002 #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ 1003 1004 /* PREDV0 division factor */ 1005 #define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 1006 #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ 1007 #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ 1008 #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ 1009 #define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ 1010 #define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ 1011 #define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ 1012 #define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ 1013 #define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ 1014 #define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ 1015 #define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ 1016 #define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ 1017 #define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ 1018 #define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ 1019 #define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ 1020 #define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ 1021 #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ 1022 1023 /* PREDV1 division factor */ 1024 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 1025 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ 1026 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ 1027 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ 1028 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ 1029 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ 1030 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ 1031 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ 1032 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ 1033 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ 1034 #define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ 1035 #define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ 1036 #define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ 1037 #define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ 1038 #define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ 1039 #define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ 1040 #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ 1041 1042 /* PLL1 clock multiplication factor */ 1043 #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) 1044 #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ 1045 #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ 1046 #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ 1047 #define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ 1048 #define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ 1049 #define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ 1050 #define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ 1051 #define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ 1052 #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ 1053 1054 /* PLL2 clock multiplication factor */ 1055 #define PLL2MF_4 RCU_CFG1_PLL2MF_4 /*!< bit 4 of PLL2MF */ 1056 #define PLL2MF_5 RCU_CFG1_PLL2MF_5 /*!< bit 5 of PLL2MF */ 1057 #define PLL2MF_4_5 (PLL2MF_4 | PLL2MF_5) /*!< bit 4 and 5 of PLL2MF */ 1058 1059 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) 1060 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ 1061 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ 1062 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ 1063 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ 1064 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ 1065 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ 1066 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ 1067 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ 1068 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ 1069 #define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ 1070 #define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ 1071 #define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ 1072 #define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ 1073 #define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ 1074 #define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ 1075 #define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ 1076 #define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ 1077 #define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ 1078 #define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ 1079 #define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ 1080 #define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ 1081 #define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ 1082 #define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ 1083 #define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ 1084 #define RCU_PLL2_MUL34 (PLL2MF_5 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 34 */ 1085 #define RCU_PLL2_MUL35 (PLL2MF_5 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 35 */ 1086 #define RCU_PLL2_MUL36 (PLL2MF_5 | CFG1_PLL2MF(2)) /*!< PLL2 source clock multiply by 36 */ 1087 #define RCU_PLL2_MUL37 (PLL2MF_5 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 37 */ 1088 #define RCU_PLL2_MUL38 (PLL2MF_5 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 38 */ 1089 #define RCU_PLL2_MUL39 (PLL2MF_5 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 39 */ 1090 #define RCU_PLL2_MUL41 (PLL2MF_5 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 41 */ 1091 #define RCU_PLL2_MUL42 (PLL2MF_5 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 42 */ 1092 #define RCU_PLL2_MUL43 (PLL2MF_5 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 43 */ 1093 #define RCU_PLL2_MUL44 (PLL2MF_5 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 44 */ 1094 #define RCU_PLL2_MUL45 (PLL2MF_5 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 45 */ 1095 #define RCU_PLL2_MUL46 (PLL2MF_5 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 46 */ 1096 #define RCU_PLL2_MUL47 (PLL2MF_5 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 47 */ 1097 #define RCU_PLL2_MUL48 (PLL2MF_5 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 48 */ 1098 #define RCU_PLL2_MUL49 (PLL2MF_5 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 49 */ 1099 #define RCU_PLL2_MUL50 (PLL2MF_4_5 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 50 */ 1100 #define RCU_PLL2_MUL51 (PLL2MF_4_5 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 51 */ 1101 #define RCU_PLL2_MUL52 (PLL2MF_4_5 | CFG1_PLL2MF(2)) /*!< PLL2 source clock multiply by 52 */ 1102 #define RCU_PLL2_MUL53 (PLL2MF_4_5 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 53 */ 1103 #define RCU_PLL2_MUL54 (PLL2MF_4_5 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 54 */ 1104 #define RCU_PLL2_MUL55 (PLL2MF_4_5 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 55 */ 1105 #define RCU_PLL2_MUL56 (PLL2MF_4_5 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 56*/ 1106 #define RCU_PLL2_MUL57 (PLL2MF_4_5 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 57 */ 1107 #define RCU_PLL2_MUL58 (PLL2MF_4_5 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 58 */ 1108 #define RCU_PLL2_MUL59 (PLL2MF_4_5 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 59 */ 1109 #define RCU_PLL2_MUL60 (PLL2MF_4_5 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 60 */ 1110 #define RCU_PLL2_MUL61 (PLL2MF_4_5 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 61 */ 1111 #define RCU_PLL2_MUL62 (PLL2MF_4_5 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 62 */ 1112 #define RCU_PLL2_MUL63 (PLL2MF_4_5 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 63 */ 1113 #define RCU_PLL2_MUL64 (PLL2MF_4_5 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 64 */ 1114 #define RCU_PLL2_MUL80 (PLL2MF_4_5 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 80 */ 1115 1116 #if (defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508)) 1117 /* PREDV0 input clock source selection */ 1118 #define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ 1119 #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ 1120 1121 /* I2S1 clock source selection */ 1122 #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ 1123 #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ 1124 1125 /* I2S2 clock source selection */ 1126 #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ 1127 #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ 1128 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 1129 1130 /* SHRTIMER clock source selection */ 1131 #ifndef GD32EPRT 1132 #define RCU_SHRTIMERSRC_CKAPB2 ((uint32_t)0x00000000U) /*!< APB2 clock selected as SHRTIMER source clock */ 1133 #define RCU_SHRTIMERSRC_CKSYS RCU_CFG1_SHRTIMERSEL /*!< system clock selected as SHRTIMER source clock */ 1134 #endif /* GD32EPRT */ 1135 1136 /* PLL input clock source selection */ 1137 #define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ 1138 #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ 1139 1140 /* deep-sleep mode voltage */ 1141 #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 1142 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ 1143 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ 1144 #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ 1145 #define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ 1146 1147 /* USB 48MHz clock selection */ 1148 #define ADDCTL_CK48MSEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 1149 #define RCU_CK48MSRC_CKPLL ADDCTL_CK48MSEL(0) /*!< select select CK_PLL as CK48M clock source */ 1150 #define RCU_CK48MSRC_IRC48M ADDCTL_CK48MSEL(1) /*!< select select CK_IRC48M as CK48M clock source */ 1151 #define RCU_CK48MSRC_CKPLLUSB ADDCTL_CK48MSEL(2) /*!< select CK_PLLUSB clock as CK48M clock source */ 1152 #define RCU_CK48MSRC_CKPLL2 ADDCTL_CK48MSEL(3) /*!< select CK_PLL2 clock as CK48M clock source */ 1153 1154 #if defined(GD32E50X_CL) || defined(GD32E508) 1155 /* USBHSSEL clock source selection */ 1156 #define RCU_USBHSSRC_48M ((uint32_t)0x00000000U) /*!< 48M clock selected as USBHS source clock */ 1157 #define RCU_CK48MSRC_60M RCU_ADDCTL_USBHSSEL /*!< 60M clock selected as USBHS source clock */ 1158 1159 /* USBHSDV division factor */ 1160 #define ADDCTL_USBHSDV(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) 1161 #define RCU_USBHSDV_DIV2 ADDCTL_USBHSDV(0) /*!< USBHSDV input source clock divided by 2 */ 1162 #define RCU_USBHSDV_DIV4 ADDCTL_USBHSDV(1) /*!< USBHSDV input source clock divided by 4 */ 1163 #define RCU_USBHSDV_DIV6 ADDCTL_USBHSDV(2) /*!< USBHSDV input source clock divided by 6 */ 1164 #define RCU_USBHSDV_DIV8 ADDCTL_USBHSDV(3) /*!< USBHSDV input source clock divided by 8 */ 1165 #define RCU_USBHSDV_DIV10 ADDCTL_USBHSDV(4) /*!< USBHSDV input source clock divided by 10 */ 1166 #define RCU_USBHSDV_DIV12 ADDCTL_USBHSDV(5) /*!< USBHSDV input source clock divided by 12 */ 1167 #define RCU_USBHSDV_DIV14 ADDCTL_USBHSDV(6) /*!< USBHSDV input source clock divided by 14 */ 1168 #define RCU_USBHSDV_DIV16 ADDCTL_USBHSDV(7) /*!< USBHSDV input source clock divided by 16 */ 1169 1170 /* PLLUSBPREDV division factor */ 1171 #define ADDCFG_PLLUSBPREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 1172 #define RCU_PLLUSBPREDV_DIV1 ADDCFG_PLLUSBPREDV(1) /*!< PLLUSBPREDV input source clock divided by 1 */ 1173 #define RCU_PLLUSBPREDV_DIV2 ADDCFG_PLLUSBPREDV(2) /*!< PLLUSBPREDV input source clock divided by 2 */ 1174 #define RCU_PLLUSBPREDV_DIV3 ADDCFG_PLLUSBPREDV(3) /*!< PLLUSBPREDV input source clock divided by 3 */ 1175 #define RCU_PLLUSBPREDV_DIV4 ADDCFG_PLLUSBPREDV(4) /*!< PLLUSBPREDV input source clock divided by 4 */ 1176 #define RCU_PLLUSBPREDV_DIV5 ADDCFG_PLLUSBPREDV(5) /*!< PLLUSBPREDV input source clock divided by 5 */ 1177 #define RCU_PLLUSBPREDV_DIV6 ADDCFG_PLLUSBPREDV(6) /*!< PLLUSBPREDV input source clock divided by 6 */ 1178 #define RCU_PLLUSBPREDV_DIV7 ADDCFG_PLLUSBPREDV(7) /*!< PLLUSBPREDV input source clock divided by 7 */ 1179 #define RCU_PLLUSBPREDV_DIV8 ADDCFG_PLLUSBPREDV(8) /*!< PLLUSBPREDV input source clock divided by 8 */ 1180 #define RCU_PLLUSBPREDV_DIV9 ADDCFG_PLLUSBPREDV(9) /*!< PLLUSBPREDV input source clock divided by 9 */ 1181 #define RCU_PLLUSBPREDV_DIV10 ADDCFG_PLLUSBPREDV(10) /*!< PLLUSBPREDV input source clock divided by 10 */ 1182 #define RCU_PLLUSBPREDV_DIV11 ADDCFG_PLLUSBPREDV(11) /*!< PLLUSBPREDV input source clock divided by 11 */ 1183 #define RCU_PLLUSBPREDV_DIV12 ADDCFG_PLLUSBPREDV(12) /*!< PLLUSBPREDV input source clock divided by 12 */ 1184 #define RCU_PLLUSBPREDV_DIV13 ADDCFG_PLLUSBPREDV(13) /*!< PLLUSBPREDV input source clock divided by 13 */ 1185 #define RCU_PLLUSBPREDV_DIV14 ADDCFG_PLLUSBPREDV(14) /*!< PLLUSBPREDV input source clock divided by 14 */ 1186 #define RCU_PLLUSBPREDV_DIV15 ADDCFG_PLLUSBPREDV(15) /*!< PLLUSBPREDV input source clock divided by 15 */ 1187 1188 /* PLLUSB clock source selection */ 1189 #define RCU_PLLUSBPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLLUSB source clock */ 1190 #define RCU_PLLUSBPRESRC_IRC48M RCU_ADDCFG_PLLUSBPRESEL /*!< IRC48M clock selected as PLLUSB source clock */ 1191 1192 /* PLLUSBPREDVSEL clock source selection */ 1193 #define RCU_PLLUSBPREDVSRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PLLUSBPREDV input source clock */ 1194 #define RCU_PLLUSBPREDVSRC_CKPLL1 RCU_ADDCFG_PLLUSBPREDVSEL /*!< CK_PLL1 selected as PLLUSBPREDV input source clock */ 1195 1196 /* PLLUSB clock multiplication factor */ 1197 #define ADDCFG_PLLUSBMF(regval) (BITS(18,24) & ((uint32_t)(regval) << 18)) 1198 #define RCU_PLLUSB_MUL16 ADDCFG_PLLUSBMF(16) /*!< PLLUSB source clock multiply by 16 */ 1199 #define RCU_PLLUSB_MUL17 ADDCFG_PLLUSBMF(17) /*!< PLLUSB source clock multiply by 17 */ 1200 #define RCU_PLLUSB_MUL18 ADDCFG_PLLUSBMF(18) /*!< PLLUSB source clock multiply by 18 */ 1201 #define RCU_PLLUSB_MUL19 ADDCFG_PLLUSBMF(19) /*!< PLLUSB source clock multiply by 19 */ 1202 #define RCU_PLLUSB_MUL20 ADDCFG_PLLUSBMF(20) /*!< PLLUSB source clock multiply by 20 */ 1203 #define RCU_PLLUSB_MUL21 ADDCFG_PLLUSBMF(21) /*!< PLLUSB source clock multiply by 21 */ 1204 #define RCU_PLLUSB_MUL22 ADDCFG_PLLUSBMF(22) /*!< PLLUSB source clock multiply by 22 */ 1205 #define RCU_PLLUSB_MUL23 ADDCFG_PLLUSBMF(23) /*!< PLLUSB source clock multiply by 23 */ 1206 #define RCU_PLLUSB_MUL24 ADDCFG_PLLUSBMF(24) /*!< PLLUSB source clock multiply by 24 */ 1207 #define RCU_PLLUSB_MUL25 ADDCFG_PLLUSBMF(25) /*!< PLLUSB source clock multiply by 25 */ 1208 #define RCU_PLLUSB_MUL26 ADDCFG_PLLUSBMF(26) /*!< PLLUSB source clock multiply by 26 */ 1209 #define RCU_PLLUSB_MUL27 ADDCFG_PLLUSBMF(27) /*!< PLLUSB source clock multiply by 27 */ 1210 #define RCU_PLLUSB_MUL28 ADDCFG_PLLUSBMF(28) /*!< PLLUSB source clock multiply by 28 */ 1211 #define RCU_PLLUSB_MUL29 ADDCFG_PLLUSBMF(29) /*!< PLLUSB source clock multiply by 29 */ 1212 #define RCU_PLLUSB_MUL30 ADDCFG_PLLUSBMF(30) /*!< PLLUSB source clock multiply by 30 */ 1213 #define RCU_PLLUSB_MUL31 ADDCFG_PLLUSBMF(31) /*!< PLLUSB source clock multiply by 31 */ 1214 #define RCU_PLLUSB_MUL32 ADDCFG_PLLUSBMF(32) /*!< PLLUSB source clock multiply by 32 */ 1215 #define RCU_PLLUSB_MUL33 ADDCFG_PLLUSBMF(33) /*!< PLLUSB source clock multiply by 33 */ 1216 #define RCU_PLLUSB_MUL34 ADDCFG_PLLUSBMF(34) /*!< PLLUSB source clock multiply by 34 */ 1217 #define RCU_PLLUSB_MUL35 ADDCFG_PLLUSBMF(35) /*!< PLLUSB source clock multiply by 35 */ 1218 #define RCU_PLLUSB_MUL36 ADDCFG_PLLUSBMF(36) /*!< PLLUSB source clock multiply by 36 */ 1219 #define RCU_PLLUSB_MUL37 ADDCFG_PLLUSBMF(37) /*!< PLLUSB source clock multiply by 37 */ 1220 #define RCU_PLLUSB_MUL38 ADDCFG_PLLUSBMF(38) /*!< PLLUSB source clock multiply by 38 */ 1221 #define RCU_PLLUSB_MUL39 ADDCFG_PLLUSBMF(39) /*!< PLLUSB source clock multiply by 39 */ 1222 #define RCU_PLLUSB_MUL40 ADDCFG_PLLUSBMF(40) /*!< PLLUSB source clock multiply by 40 */ 1223 #define RCU_PLLUSB_MUL41 ADDCFG_PLLUSBMF(41) /*!< PLLUSB source clock multiply by 41 */ 1224 #define RCU_PLLUSB_MUL42 ADDCFG_PLLUSBMF(42) /*!< PLLUSB source clock multiply by 42 */ 1225 #define RCU_PLLUSB_MUL43 ADDCFG_PLLUSBMF(43) /*!< PLLUSB source clock multiply by 43 */ 1226 #define RCU_PLLUSB_MUL44 ADDCFG_PLLUSBMF(44) /*!< PLLUSB source clock multiply by 44 */ 1227 #define RCU_PLLUSB_MUL45 ADDCFG_PLLUSBMF(45) /*!< PLLUSB source clock multiply by 45 */ 1228 #define RCU_PLLUSB_MUL46 ADDCFG_PLLUSBMF(46) /*!< PLLUSB source clock multiply by 46 */ 1229 #define RCU_PLLUSB_MUL47 ADDCFG_PLLUSBMF(47) /*!< PLLUSB source clock multiply by 47 */ 1230 #define RCU_PLLUSB_MUL48 ADDCFG_PLLUSBMF(48) /*!< PLLUSB source clock multiply by 48 */ 1231 #define RCU_PLLUSB_MUL49 ADDCFG_PLLUSBMF(49) /*!< PLLUSB source clock multiply by 49 */ 1232 #define RCU_PLLUSB_MUL50 ADDCFG_PLLUSBMF(50) /*!< PLLUSB source clock multiply by 50 */ 1233 #define RCU_PLLUSB_MUL51 ADDCFG_PLLUSBMF(51) /*!< PLLUSB source clock multiply by 51 */ 1234 #define RCU_PLLUSB_MUL52 ADDCFG_PLLUSBMF(52) /*!< PLLUSB source clock multiply by 52 */ 1235 #define RCU_PLLUSB_MUL53 ADDCFG_PLLUSBMF(53) /*!< PLLUSB source clock multiply by 53 */ 1236 #define RCU_PLLUSB_MUL54 ADDCFG_PLLUSBMF(54) /*!< PLLUSB source clock multiply by 54 */ 1237 #define RCU_PLLUSB_MUL55 ADDCFG_PLLUSBMF(55) /*!< PLLUSB source clock multiply by 55 */ 1238 #define RCU_PLLUSB_MUL56 ADDCFG_PLLUSBMF(56) /*!< PLLUSB source clock multiply by 56 */ 1239 #define RCU_PLLUSB_MUL57 ADDCFG_PLLUSBMF(57) /*!< PLLUSB source clock multiply by 57 */ 1240 #define RCU_PLLUSB_MUL58 ADDCFG_PLLUSBMF(58) /*!< PLLUSB source clock multiply by 58 */ 1241 #define RCU_PLLUSB_MUL59 ADDCFG_PLLUSBMF(59) /*!< PLLUSB source clock multiply by 59 */ 1242 #define RCU_PLLUSB_MUL60 ADDCFG_PLLUSBMF(60) /*!< PLLUSB source clock multiply by 60 */ 1243 #define RCU_PLLUSB_MUL61 ADDCFG_PLLUSBMF(61) /*!< PLLUSB source clock multiply by 61 */ 1244 #define RCU_PLLUSB_MUL62 ADDCFG_PLLUSBMF(62) /*!< PLLUSB source clock multiply by 62 */ 1245 #define RCU_PLLUSB_MUL63 ADDCFG_PLLUSBMF(63) /*!< PLLUSB source clock multiply by 63 */ 1246 #define RCU_PLLUSB_MUL64 ADDCFG_PLLUSBMF(64) /*!< PLLUSB source clock multiply by 64 */ 1247 #define RCU_PLLUSB_MUL65 ADDCFG_PLLUSBMF(65) /*!< PLLUSB source clock multiply by 65 */ 1248 #define RCU_PLLUSB_MUL66 ADDCFG_PLLUSBMF(66) /*!< PLLUSB source clock multiply by 66 */ 1249 #define RCU_PLLUSB_MUL67 ADDCFG_PLLUSBMF(67) /*!< PLLUSB source clock multiply by 67 */ 1250 #define RCU_PLLUSB_MUL68 ADDCFG_PLLUSBMF(68) /*!< PLLUSB source clock multiply by 68 */ 1251 #define RCU_PLLUSB_MUL69 ADDCFG_PLLUSBMF(69) /*!< PLLUSB source clock multiply by 69 */ 1252 #define RCU_PLLUSB_MUL70 ADDCFG_PLLUSBMF(70) /*!< PLLUSB source clock multiply by 70 */ 1253 #define RCU_PLLUSB_MUL71 ADDCFG_PLLUSBMF(71) /*!< PLLUSB source clock multiply by 71 */ 1254 #define RCU_PLLUSB_MUL72 ADDCFG_PLLUSBMF(72) /*!< PLLUSB source clock multiply by 72 */ 1255 #define RCU_PLLUSB_MUL73 ADDCFG_PLLUSBMF(73) /*!< PLLUSB source clock multiply by 73 */ 1256 #define RCU_PLLUSB_MUL74 ADDCFG_PLLUSBMF(74) /*!< PLLUSB source clock multiply by 74 */ 1257 #define RCU_PLLUSB_MUL75 ADDCFG_PLLUSBMF(75) /*!< PLLUSB source clock multiply by 75 */ 1258 #define RCU_PLLUSB_MUL76 ADDCFG_PLLUSBMF(76) /*!< PLLUSB source clock multiply by 76 */ 1259 #define RCU_PLLUSB_MUL77 ADDCFG_PLLUSBMF(77) /*!< PLLUSB source clock multiply by 77 */ 1260 #define RCU_PLLUSB_MUL78 ADDCFG_PLLUSBMF(78) /*!< PLLUSB source clock multiply by 78 */ 1261 #define RCU_PLLUSB_MUL79 ADDCFG_PLLUSBMF(79) /*!< PLLUSB source clock multiply by 79 */ 1262 #define RCU_PLLUSB_MUL80 ADDCFG_PLLUSBMF(80) /*!< PLLUSB source clock multiply by 80 */ 1263 #define RCU_PLLUSB_MUL81 ADDCFG_PLLUSBMF(81) /*!< PLLUSB source clock multiply by 81 */ 1264 #define RCU_PLLUSB_MUL82 ADDCFG_PLLUSBMF(82) /*!< PLLUSB source clock multiply by 82 */ 1265 #define RCU_PLLUSB_MUL83 ADDCFG_PLLUSBMF(83) /*!< PLLUSB source clock multiply by 83 */ 1266 #define RCU_PLLUSB_MUL84 ADDCFG_PLLUSBMF(84) /*!< PLLUSB source clock multiply by 84 */ 1267 #define RCU_PLLUSB_MUL85 ADDCFG_PLLUSBMF(85) /*!< PLLUSB source clock multiply by 85 */ 1268 #define RCU_PLLUSB_MUL86 ADDCFG_PLLUSBMF(86) /*!< PLLUSB source clock multiply by 86 */ 1269 #define RCU_PLLUSB_MUL87 ADDCFG_PLLUSBMF(87) /*!< PLLUSB source clock multiply by 87 */ 1270 #define RCU_PLLUSB_MUL88 ADDCFG_PLLUSBMF(88) /*!< PLLUSB source clock multiply by 88 */ 1271 #define RCU_PLLUSB_MUL89 ADDCFG_PLLUSBMF(89) /*!< PLLUSB source clock multiply by 89 */ 1272 #define RCU_PLLUSB_MUL90 ADDCFG_PLLUSBMF(90) /*!< PLLUSB source clock multiply by 90 */ 1273 #define RCU_PLLUSB_MUL91 ADDCFG_PLLUSBMF(91) /*!< PLLUSB source clock multiply by 91 */ 1274 #define RCU_PLLUSB_MUL92 ADDCFG_PLLUSBMF(92) /*!< PLLUSB source clock multiply by 92 */ 1275 #define RCU_PLLUSB_MUL93 ADDCFG_PLLUSBMF(93) /*!< PLLUSB source clock multiply by 93 */ 1276 #define RCU_PLLUSB_MUL94 ADDCFG_PLLUSBMF(94) /*!< PLLUSB source clock multiply by 94 */ 1277 #define RCU_PLLUSB_MUL95 ADDCFG_PLLUSBMF(95) /*!< PLLUSB source clock multiply by 95 */ 1278 #define RCU_PLLUSB_MUL96 ADDCFG_PLLUSBMF(96) /*!< PLLUSB source clock multiply by 96 */ 1279 #define RCU_PLLUSB_MUL97 ADDCFG_PLLUSBMF(97) /*!< PLLUSB source clock multiply by 97 */ 1280 #define RCU_PLLUSB_MUL98 ADDCFG_PLLUSBMF(98) /*!< PLLUSB source clock multiply by 98 */ 1281 #define RCU_PLLUSB_MUL99 ADDCFG_PLLUSBMF(99) /*!< PLLUSB source clock multiply by 99 */ 1282 #define RCU_PLLUSB_MUL100 ADDCFG_PLLUSBMF(100) /*!< PLLUSB source clock multiply by 100 */ 1283 #define RCU_PLLUSB_MUL101 ADDCFG_PLLUSBMF(101) /*!< PLLUSB source clock multiply by 101 */ 1284 #define RCU_PLLUSB_MUL102 ADDCFG_PLLUSBMF(102) /*!< PLLUSB source clock multiply by 102 */ 1285 #define RCU_PLLUSB_MUL103 ADDCFG_PLLUSBMF(103) /*!< PLLUSB source clock multiply by 103 */ 1286 #define RCU_PLLUSB_MUL104 ADDCFG_PLLUSBMF(104) /*!< PLLUSB source clock multiply by 104 */ 1287 #define RCU_PLLUSB_MUL105 ADDCFG_PLLUSBMF(105) /*!< PLLUSB source clock multiply by 105 */ 1288 #define RCU_PLLUSB_MUL106 ADDCFG_PLLUSBMF(106) /*!< PLLUSB source clock multiply by 106 */ 1289 #define RCU_PLLUSB_MUL107 ADDCFG_PLLUSBMF(107) /*!< PLLUSB source clock multiply by 107 */ 1290 #define RCU_PLLUSB_MUL108 ADDCFG_PLLUSBMF(108) /*!< PLLUSB source clock multiply by 108 */ 1291 #define RCU_PLLUSB_MUL109 ADDCFG_PLLUSBMF(109) /*!< PLLUSB source clock multiply by 109 */ 1292 #define RCU_PLLUSB_MUL110 ADDCFG_PLLUSBMF(110) /*!< PLLUSB source clock multiply by 110 */ 1293 #define RCU_PLLUSB_MUL111 ADDCFG_PLLUSBMF(111) /*!< PLLUSB source clock multiply by 111 */ 1294 #define RCU_PLLUSB_MUL112 ADDCFG_PLLUSBMF(112) /*!< PLLUSB source clock multiply by 112 */ 1295 #define RCU_PLLUSB_MUL113 ADDCFG_PLLUSBMF(113) /*!< PLLUSB source clock multiply by 113 */ 1296 #define RCU_PLLUSB_MUL114 ADDCFG_PLLUSBMF(114) /*!< PLLUSB source clock multiply by 114 */ 1297 #define RCU_PLLUSB_MUL115 ADDCFG_PLLUSBMF(115) /*!< PLLUSB source clock multiply by 115 */ 1298 #define RCU_PLLUSB_MUL116 ADDCFG_PLLUSBMF(116) /*!< PLLUSB source clock multiply by 116 */ 1299 #define RCU_PLLUSB_MUL117 ADDCFG_PLLUSBMF(117) /*!< PLLUSB source clock multiply by 117 */ 1300 #define RCU_PLLUSB_MUL118 ADDCFG_PLLUSBMF(118) /*!< PLLUSB source clock multiply by 118 */ 1301 #define RCU_PLLUSB_MUL119 ADDCFG_PLLUSBMF(119) /*!< PLLUSB source clock multiply by 119 */ 1302 #define RCU_PLLUSB_MUL120 ADDCFG_PLLUSBMF(120) /*!< PLLUSB source clock multiply by 120 */ 1303 #define RCU_PLLUSB_MUL121 ADDCFG_PLLUSBMF(121) /*!< PLLUSB source clock multiply by 121 */ 1304 #define RCU_PLLUSB_MUL122 ADDCFG_PLLUSBMF(122) /*!< PLLUSB source clock multiply by 122 */ 1305 #define RCU_PLLUSB_MUL123 ADDCFG_PLLUSBMF(123) /*!< PLLUSB source clock multiply by 123 */ 1306 #define RCU_PLLUSB_MUL124 ADDCFG_PLLUSBMF(124) /*!< PLLUSB source clock multiply by 124 */ 1307 #define RCU_PLLUSB_MUL125 ADDCFG_PLLUSBMF(125) /*!< PLLUSB source clock multiply by 125 */ 1308 #define RCU_PLLUSB_MUL126 ADDCFG_PLLUSBMF(126) /*!< PLLUSB source clock multiply by 126 */ 1309 #define RCU_PLLUSB_MUL127 ADDCFG_PLLUSBMF(127) /*!< PLLUSB source clock multiply by 127 */ 1310 #endif /* GD32E50X_CL and GD32E508 */ 1311 1312 /* USART5 clock source selection */ 1313 #define CFG2_USART5SRC(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 1314 #define RCU_USART5SRC_CKAPB2 CFG2_USART5SRC(0) /*!< CK_APB2 selected as USART5 source clock */ 1315 #define RCU_USART5SRC_CKSYS CFG2_USART5SRC(1) /*!< CK_SYS selected as USART5 source clock */ 1316 #define RCU_USART5SRC_LXTAL CFG2_USART5SRC(2) /*!< CK_LXTAL selected as USART5 source clock */ 1317 #define RCU_USART5SRC_IRC8M CFG2_USART5SRC(3) /*!< CK_IRC8M selected as USART5 source clock */ 1318 1319 /* I2C2 clock source selection */ 1320 #define CFG2_I2C2SRC(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 1321 #define RCU_I2C2SRC_CKAPB1 CFG2_I2C2SRC(0) /*!< APB1 clock selected as I2C2 source clock */ 1322 #define RCU_I2C2SRC_CKSYS CFG2_I2C2SRC(1) /*!< System clock selected as I2C2 source clock */ 1323 #define RCU_I2C2SRCSRC_CKIRC8M CFG2_I2C2SRC(2) /*!< CK_IRC8M clock selected as I2C2 source clock */ 1324 1325 /* function declarations */ 1326 /* deinitialize the RCU */ 1327 void rcu_deinit(void); 1328 /* enable the peripherals clock */ 1329 void rcu_periph_clock_enable(rcu_periph_enum periph); 1330 /* disable the peripherals clock */ 1331 void rcu_periph_clock_disable(rcu_periph_enum periph); 1332 /* enable the peripherals clock when sleep mode */ 1333 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 1334 /* disable the peripherals clock when sleep mode */ 1335 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 1336 /* reset the peripherals */ 1337 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 1338 /* disable reset the peripheral */ 1339 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 1340 /* reset the BKP domain */ 1341 void rcu_bkp_reset_enable(void); 1342 /* disable the BKP domain reset */ 1343 void rcu_bkp_reset_disable(void); 1344 1345 /* configure the system clock source */ 1346 void rcu_system_clock_source_config(uint32_t ck_sys); 1347 /* get the system clock source */ 1348 uint32_t rcu_system_clock_source_get(void); 1349 /* configure the AHB prescaler selection */ 1350 void rcu_ahb_clock_config(uint32_t ck_ahb); 1351 /* configure the APB1 prescaler selection */ 1352 void rcu_apb1_clock_config(uint32_t ck_apb1); 1353 /* configure the APB2 prescaler selection */ 1354 void rcu_apb2_clock_config(uint32_t ck_apb2); 1355 /* configure the CK_OUT0 clock source and divider */ 1356 void rcu_ckout0_config(uint32_t ckout0_src); 1357 /* configure the PLL clock source selection and PLL multiply factor */ 1358 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 1359 /* configure the PLL clock source preselection */ 1360 void rcu_pllpresel_config(uint32_t pll_presel); 1361 #if defined(GD32E50X_HD) || defined(GD32E50X_XD) 1362 /* configure the PREDV0 division factor and clock source */ 1363 void rcu_predv0_config(uint32_t predv0_div); 1364 #elif defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 1365 /* configure the PREDV0 division factor and clock source */ 1366 void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); 1367 /* configure the PREDV1 division factor */ 1368 void rcu_predv1_config(uint32_t predv1_div); 1369 /* configure the PLL1 clock */ 1370 void rcu_pll1_config(uint32_t pll_mul); 1371 /* configure the PLL2 clock */ 1372 void rcu_pll2_config(uint32_t pll_mul); 1373 #endif /* GD32E50X_HD and GD32E50X_XD */ 1374 #if defined(GD32E50X_CL) || defined(GD32E508) 1375 /* configure the PLLUSB clock source preselection */ 1376 void rcu_pllusbpresel_config(uint32_t pllusb_presel); 1377 /* configure the PLLUSBPREDV division factor and clock source */ 1378 void rcu_pllusbpredv_config(uint32_t pllusbpredv_source, uint32_t pllusbpredv_div); 1379 /* configure the PLLUSB clock */ 1380 void rcu_pllusb_config(uint32_t pllusb_mul); 1381 #endif /* GD32E50X_CL and GD32E508 */ 1382 1383 /* configure the ADC division factor */ 1384 void rcu_adc_clock_config(uint32_t adc_psc); 1385 /* configure the USBD/USBHS prescaler factor */ 1386 void rcu_usb_clock_config(uint32_t usb_psc); 1387 /* configure the RTC clock source selection */ 1388 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 1389 #ifndef GD32EPRT 1390 /* configure the SHRTIMER clock source selection */ 1391 void rcu_shrtimer_clock_config(uint32_t shrtimer_clock_source); 1392 #endif /* GD32EPRT */ 1393 /* configure the usart5 clock source selection */ 1394 void rcu_usart5_clock_config(uint32_t usart5_clock_source); 1395 /* configure the I2C2 clock source selection */ 1396 void rcu_i2c2_clock_config(uint32_t i2c2_clock_source); 1397 /* configure the CK48M clock selection */ 1398 void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); 1399 #if defined(GD32E50X_CL) || defined(GD32EPRT) || defined(GD32E508) 1400 /* configure the I2S1 clock source selection */ 1401 void rcu_i2s1_clock_config(uint32_t i2s_clock_source); 1402 /* configure the I2S2 clock source selection */ 1403 void rcu_i2s2_clock_config(uint32_t i2s_clock_source); 1404 #endif /* GD32E50X_CL and GD32EPRT and GD32E508 */ 1405 #if defined(GD32E50X_CL) || defined(GD32E508) 1406 /* configure the USBHSSEL source clock selection */ 1407 void rcu_usbhssel_config(uint32_t usbhssel_clock_source); 1408 /* configure the USBHSDV division factor */ 1409 void rcu_usbdv_config(uint32_t usbhs_dv); 1410 #endif /* GD32E50X_CL and GD32E508 */ 1411 1412 /* get the clock stabilization and periphral reset flags */ 1413 FlagStatus rcu_flag_get(rcu_flag_enum flag); 1414 /* clear the reset flag */ 1415 void rcu_all_reset_flag_clear(void); 1416 /* get the clock stabilization interrupt and ckm flags */ 1417 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 1418 /* clear the interrupt flags */ 1419 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); 1420 /* enable the stabilization interrupt */ 1421 void rcu_interrupt_enable(rcu_int_enum interrupt); 1422 /* disable the stabilization interrupt */ 1423 void rcu_interrupt_disable(rcu_int_enum interrupt); 1424 1425 /* configure the LXTAL drive capability */ 1426 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 1427 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ 1428 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 1429 /* turn on the oscillator */ 1430 void rcu_osci_on(rcu_osci_type_enum osci); 1431 /* turn off the oscillator */ 1432 void rcu_osci_off(rcu_osci_type_enum osci); 1433 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 1434 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 1435 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 1436 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 1437 /* enable the HXTAL clock monitor */ 1438 void rcu_hxtal_clock_monitor_enable(void); 1439 /* disable the HXTAL clock monitor */ 1440 void rcu_hxtal_clock_monitor_disable(void); 1441 1442 /* set the IRC8M adjust value */ 1443 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); 1444 1445 /* set the deep sleep mode voltage */ 1446 void rcu_deepsleep_voltage_set(uint32_t dsvol); 1447 1448 /* get the system clock, bus and peripheral clock frequency */ 1449 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 1450 1451 #endif /* GD32E50X_RCU_H */ 1452
