1 /* 2 * Copyright (c) 2022, Teslabs Engineering S.L. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_ 7 #define SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_ 8 9 #include <zephyr/sys/util_macro.h> 10 11 /* RCU */ 12 #define RCU_CFG0_OFFSET 0x08U 13 #define RCU_AHB1EN_OFFSET 0x30U 14 #define RCU_AHB2EN_OFFSET 0x34U 15 #define RCU_AHB3EN_OFFSET 0x38U 16 #define RCU_APB1EN_OFFSET 0x40U 17 #define RCU_APB2EN_OFFSET 0x44U 18 #define RCU_CFG1_OFFSET 0x8CU 19 #define RCU_ADDAPB1EN_OFFSET 0xE4U 20 21 #define RCU_CFG0_AHBPSC_POS 4U 22 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS) 23 #define RCU_CFG0_APB1PSC_POS 10U 24 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS) 25 #define RCU_CFG0_APB2PSC_POS 13U 26 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS) 27 28 #define RCU_CFG1_TIMERSEL_POS 24U 29 #define RCU_CFG1_TIMERSEL_MSK (BIT_MASK(1) << RCU_CFG1_TIMERSEL_POS) 30 31 #endif /* SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_ */ 32
