| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/ |
| D | fsl_sentinel.c | 28 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/upower/ |
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/upower/ |
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/upower/ |
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/upower/ |
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/upower/ |
| D | upmu.h | 326 MU_RCR_tag RCR; // RCR Register member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_MU.h | 94 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_ENET.h | 90 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_MU.h | 94 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm4.h | 10779 __IO uint32_t RCR; /**< DAC Reset Control Register, offset: 0x24 */ member
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| D | K32L3A60_cm0plus.h | 10071 __IO uint32_t RCR; /**< DAC Reset Control Register, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/ |
| D | MK64F12.h | 9725 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/ |
| D | MK63F12.h | 9712 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/ |
| D | MKV58F24.h | 11967 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/ |
| D | MK65F18.h | 11354 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/ |
| D | MK66F18.h | 11354 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/ |
| D | MCXA156.h | 23619 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/ |
| D | MCXA154.h | 23619 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/ |
| D | MCXA155.h | 23619 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 8459 …__IO uint32_t RCR; /**< Receive Control Register, offset: 0x84… member
9893 …__IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 16099 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
47647 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
62606 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
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| D | MIMX9352_ca55.h | 19001 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ member
50521 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
65478 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/ |
| D | MCXN947_cm33_core1.h | 32190 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
47521 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/ |
| D | MCXN946_cm33_core0.h | 32190 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
47521 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
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| D | MCXN946_cm33_core1.h | 32190 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
47521 __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ member
|
