1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_RCC_EX_H 21 #define STM32N6xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported constants --------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 40 * @{ 41 */ 42 43 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 44 * @{ 45 */ 46 #define RCC_PERIPHCLK_ADC (0x0000000000000001UL) 47 #define RCC_PERIPHCLK_ADF1 (0x0000000000000002UL) 48 #define RCC_PERIPHCLK_CKPER (0x0000000000000004UL) 49 #define RCC_PERIPHCLK_CSI (0x0000000000000008UL) 50 #define RCC_PERIPHCLK_DCMIPP (0x0000000000000010UL) 51 #define RCC_PERIPHCLK_ETH1 (0x0000000000000020UL) 52 #define RCC_PERIPHCLK_ETH1PHY (0x0000000000000040UL) 53 #define RCC_PERIPHCLK_ETH1RX (0x0000000000000080UL) 54 #define RCC_PERIPHCLK_ETH1TX (0x0000000000000100UL) 55 #define RCC_PERIPHCLK_ETH1PTP (0x0000000000000200UL) 56 #define RCC_PERIPHCLK_FDCAN (0x0000000000000400UL) 57 #define RCC_PERIPHCLK_FMC (0x0000000000000800UL) 58 #define RCC_PERIPHCLK_I2C1 (0x0000000000001000UL) 59 #define RCC_PERIPHCLK_I2C2 (0x0000000000002000UL) 60 #define RCC_PERIPHCLK_I2C3 (0x0000000000004000UL) 61 #define RCC_PERIPHCLK_I2C4 (0x0000000000008000UL) 62 #define RCC_PERIPHCLK_I3C1 (0x0000000000010000UL) 63 #define RCC_PERIPHCLK_I3C2 (0x0000000000020000UL) 64 #define RCC_PERIPHCLK_LPTIM1 (0x0000000000040000UL) 65 #define RCC_PERIPHCLK_LPTIM2 (0x0000000000080000UL) 66 #define RCC_PERIPHCLK_LPTIM3 (0x0000000000100000UL) 67 #define RCC_PERIPHCLK_LPTIM4 (0x0000000000200000UL) 68 #define RCC_PERIPHCLK_LPTIM5 (0x0000000000400000UL) 69 #define RCC_PERIPHCLK_LPUART1 (0x0000000000800000UL) 70 #define RCC_PERIPHCLK_LTDC (0x0000000001000000UL) 71 #define RCC_PERIPHCLK_MDF1 (0x0000000002000000UL) 72 #define RCC_PERIPHCLK_PSSI (0x0000000004000000UL) 73 #define RCC_PERIPHCLK_RTC (0x0000000008000000UL) 74 #define RCC_PERIPHCLK_SAI1 (0x0000000010000000UL) 75 #define RCC_PERIPHCLK_SAI2 (0x0000000020000000UL) 76 #define RCC_PERIPHCLK_SDMMC1 (0x0000000040000000UL) 77 #define RCC_PERIPHCLK_SDMMC2 (0x0000000080000000UL) 78 #define RCC_PERIPHCLK_SPDIFRX1 (0x0000000100000000UL) 79 #define RCC_PERIPHCLK_SPI1 (0x0000000200000000UL) 80 #define RCC_PERIPHCLK_SPI2 (0x0000000400000000UL) 81 #define RCC_PERIPHCLK_SPI3 (0x0000000800000000UL) 82 #define RCC_PERIPHCLK_SPI4 (0x0000001000000000UL) 83 #define RCC_PERIPHCLK_SPI5 (0x0000002000000000UL) 84 #define RCC_PERIPHCLK_SPI6 (0x0000004000000000UL) 85 #define RCC_PERIPHCLK_TIM (0x0000008000000000UL) 86 #define RCC_PERIPHCLK_USART1 (0x0000010000000000UL) 87 #define RCC_PERIPHCLK_USART2 (0x0000020000000000UL) 88 #define RCC_PERIPHCLK_USART3 (0x0000040000000000UL) 89 #define RCC_PERIPHCLK_UART4 (0x0000080000000000UL) 90 #define RCC_PERIPHCLK_UART5 (0x0000100000000000UL) 91 #define RCC_PERIPHCLK_USART6 (0x0000200000000000UL) 92 #define RCC_PERIPHCLK_UART7 (0x0000400000000000UL) 93 #define RCC_PERIPHCLK_UART8 (0x0000800000000000UL) 94 #define RCC_PERIPHCLK_UART9 (0x0001000000000000UL) 95 #define RCC_PERIPHCLK_USART10 (0x0002000000000000UL) 96 #define RCC_PERIPHCLK_USBPHY1 (0x0004000000000000UL) 97 #define RCC_PERIPHCLK_USBOTGHS1 (0x0008000000000000UL) 98 #define RCC_PERIPHCLK_USBPHY2 (0x0010000000000000UL) 99 #define RCC_PERIPHCLK_USBOTGHS2 (0x0020000000000000UL) 100 #define RCC_PERIPHCLK_XSPI1 (0x0040000000000000UL) 101 #define RCC_PERIPHCLK_XSPI2 (0x0080000000000000UL) 102 #define RCC_PERIPHCLK_XSPI3 (0x0100000000000000UL) 103 /** 104 * @} 105 */ 106 107 108 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 109 * @{ 110 */ 111 #define RCC_ADCCLKSOURCE_HCLK LL_RCC_ADC_CLKSOURCE_HCLK 112 #define RCC_ADCCLKSOURCE_CLKP LL_RCC_ADC_CLKSOURCE_CLKP 113 #define RCC_ADCCLKSOURCE_IC7 LL_RCC_ADC_CLKSOURCE_IC7 114 #define RCC_ADCCLKSOURCE_IC8 LL_RCC_ADC_CLKSOURCE_IC8 115 #define RCC_ADCCLKSOURCE_MSI LL_RCC_ADC_CLKSOURCE_MSI 116 #define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI 117 #define RCC_ADCCLKSOURCE_PIN LL_RCC_ADC_CLKSOURCE_I2S_CKIN 118 #define RCC_ADCCLKSOURCE_TIMG LL_RCC_ADC_CLKSOURCE_TIMG 119 /** 120 * @} 121 */ 122 123 /** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source 124 * @{ 125 */ 126 #define RCC_ADF1CLKSOURCE_HCLK LL_RCC_ADF1_CLKSOURCE_HCLK 127 #define RCC_ADF1CLKSOURCE_CLKP LL_RCC_ADF1_CLKSOURCE_CLKP 128 #define RCC_ADF1CLKSOURCE_IC7 LL_RCC_ADF1_CLKSOURCE_IC7 129 #define RCC_ADF1CLKSOURCE_IC8 LL_RCC_ADF1_CLKSOURCE_IC8 130 #define RCC_ADF1CLKSOURCE_MSI LL_RCC_ADF1_CLKSOURCE_MSI 131 #define RCC_ADF1CLKSOURCE_HSI LL_RCC_ADF1_CLKSOURCE_HSI 132 #define RCC_ADF1CLKSOURCE_PIN LL_RCC_ADF1_CLKSOURCE_I2S_CKIN 133 #define RCC_ADF1CLKSOURCE_TIMG LL_RCC_ADF1_CLKSOURCE_TIMG 134 /** 135 * @} 136 */ 137 138 /** @defgroup RCCEx_CLKP_Clock_Source CLKP Clock Source 139 * @{ 140 */ 141 #define RCC_CLKPCLKSOURCE_HSI LL_RCC_CLKP_CLKSOURCE_HSI 142 #define RCC_CLKPCLKSOURCE_MSI LL_RCC_CLKP_CLKSOURCE_MSI 143 #define RCC_CLKPCLKSOURCE_HSE LL_RCC_CLKP_CLKSOURCE_HSE 144 #define RCC_CLKPCLKSOURCE_IC5 LL_RCC_CLKP_CLKSOURCE_IC5 145 #define RCC_CLKPCLKSOURCE_IC10 LL_RCC_CLKP_CLKSOURCE_IC10 146 #define RCC_CLKPCLKSOURCE_IC15 LL_RCC_CLKP_CLKSOURCE_IC15 147 #define RCC_CLKPCLKSOURCE_IC19 LL_RCC_CLKP_CLKSOURCE_IC19 148 #define RCC_CLKPCLKSOURCE_IC20 LL_RCC_CLKP_CLKSOURCE_IC20 149 /** 150 * @} 151 */ 152 153 /** @defgroup RCCEx_DCMIPP_Clock_Source DCMIPP Clock Source 154 * @{ 155 */ 156 #define RCC_DCMIPPCLKSOURCE_PCLK5 LL_RCC_DCMIPP_CLKSOURCE_PCLK5 157 #define RCC_DCMIPPCLKSOURCE_CLKP LL_RCC_DCMIPP_CLKSOURCE_CLKP 158 #define RCC_DCMIPPCLKSOURCE_IC17 LL_RCC_DCMIPP_CLKSOURCE_IC17 159 #define RCC_DCMIPPCLKSOURCE_HSI LL_RCC_DCMIPP_CLKSOURCE_HSI 160 /** 161 * @} 162 */ 163 164 /** @defgroup RCCEx_ETH1_Clock_Source ETH1 Clock Source 165 * @{ 166 */ 167 #define RCC_ETH1CLKSOURCE_HCLK LL_RCC_ETH1_CLKSOURCE_HCLK 168 #define RCC_ETH1CLKSOURCE_CLKP LL_RCC_ETH1_CLKSOURCE_CLKP 169 #define RCC_ETH1CLKSOURCE_IC12 LL_RCC_ETH1_CLKSOURCE_IC12 170 #define RCC_ETH1CLKSOURCE_HSE LL_RCC_ETH1_CLKSOURCE_HSE 171 /** 172 * @} 173 */ 174 175 /** @defgroup RCCEx_ETH1_PHY_Interface ETH1 PHY Interface 176 * @{ 177 */ 178 #define RCC_ETH1PHYIF_MII LL_RCC_ETH1PHY_IF_MII 179 #define RCC_ETH1PHYIF_RGMII LL_RCC_ETH1PHY_IF_RGMII 180 #define RCC_ETH1PHYIF_RMII LL_RCC_ETH1PHY_IF_RMII 181 /** 182 * @} 183 */ 184 185 /** @defgroup RCCEx_ETH1_RX_Clock_Source ETH1 RX Clock Source 186 * @{ 187 */ 188 #define RCC_ETH1RXCLKSOURCE_EXT LL_RCC_ETH1REFRX_CLKSOURCE_EXT 189 #define RCC_ETH1RXCLKSOURCE_INT LL_RCC_ETH1REFRX_CLKSOURCE_INT 190 /** 191 * @} 192 */ 193 194 /** @defgroup RCCEx_ETH1_TX_Clock_Source ETH1 TX Clock Source 195 * @{ 196 */ 197 #define RCC_ETH1TXCLKSOURCE_EXT LL_RCC_ETH1REFTX_CLKSOURCE_EXT 198 #define RCC_ETH1TXCLKSOURCE_INT LL_RCC_ETH1REFTX_CLKSOURCE_INT 199 /** 200 * @} 201 */ 202 203 /** @defgroup RCCEx_ETH1_PTP_Clock_Source ETH1 PTP Clock Source 204 * @{ 205 */ 206 #define RCC_ETH1PTPCLKSOURCE_HCLK LL_RCC_ETH1PTP_CLKSOURCE_HCLK 207 #define RCC_ETH1PTPCLKSOURCE_CLKP LL_RCC_ETH1PTP_CLKSOURCE_CLKP 208 #define RCC_ETH1PTPCLKSOURCE_IC13 LL_RCC_ETH1PTP_CLKSOURCE_IC13 209 #define RCC_ETH1PTPCLKSOURCE_HSE LL_RCC_ETH1PTP_CLKSOURCE_HSE 210 /** 211 * @} 212 */ 213 214 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 215 * @{ 216 */ 217 #define RCC_FDCANCLKSOURCE_PCLK1 LL_RCC_FDCAN_CLKSOURCE_PCLK1 218 #define RCC_FDCANCLKSOURCE_CLKP LL_RCC_FDCAN_CLKSOURCE_CLKP 219 #define RCC_FDCANCLKSOURCE_IC19 LL_RCC_FDCAN_CLKSOURCE_IC19 220 #define RCC_FDCANCLKSOURCE_HSE LL_RCC_FDCAN_CLKSOURCE_HSE 221 /** 222 * @} 223 */ 224 225 /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source 226 * @{ 227 */ 228 #define RCC_FMCCLKSOURCE_HCLK LL_RCC_FMC_CLKSOURCE_HCLK 229 #define RCC_FMCCLKSOURCE_CLKP LL_RCC_FMC_CLKSOURCE_CLKP 230 #define RCC_FMCCLKSOURCE_IC3 LL_RCC_FMC_CLKSOURCE_IC3 231 #define RCC_FMCCLKSOURCE_IC4 LL_RCC_FMC_CLKSOURCE_IC4 232 /** 233 * @} 234 */ 235 236 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 237 * @{ 238 */ 239 #define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 240 #define RCC_I2C1CLKSOURCE_CLKP LL_RCC_I2C1_CLKSOURCE_CLKP 241 #define RCC_I2C1CLKSOURCE_IC10 LL_RCC_I2C1_CLKSOURCE_IC10 242 #define RCC_I2C1CLKSOURCE_IC15 LL_RCC_I2C1_CLKSOURCE_IC15 243 #define RCC_I2C1CLKSOURCE_MSI LL_RCC_I2C1_CLKSOURCE_MSI 244 #define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI 245 /** 246 * @} 247 */ 248 249 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 250 * @{ 251 */ 252 #define RCC_I2C2CLKSOURCE_PCLK1 LL_RCC_I2C2_CLKSOURCE_PCLK1 253 #define RCC_I2C2CLKSOURCE_CLKP LL_RCC_I2C2_CLKSOURCE_CLKP 254 #define RCC_I2C2CLKSOURCE_IC10 LL_RCC_I2C2_CLKSOURCE_IC10 255 #define RCC_I2C2CLKSOURCE_IC15 LL_RCC_I2C2_CLKSOURCE_IC15 256 #define RCC_I2C2CLKSOURCE_MSI LL_RCC_I2C2_CLKSOURCE_MSI 257 #define RCC_I2C2CLKSOURCE_HSI LL_RCC_I2C2_CLKSOURCE_HSI 258 /** 259 * @} 260 */ 261 262 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 263 * @{ 264 */ 265 #define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 266 #define RCC_I2C3CLKSOURCE_CLKP LL_RCC_I2C3_CLKSOURCE_CLKP 267 #define RCC_I2C3CLKSOURCE_IC10 LL_RCC_I2C3_CLKSOURCE_IC10 268 #define RCC_I2C3CLKSOURCE_IC15 LL_RCC_I2C3_CLKSOURCE_IC15 269 #define RCC_I2C3CLKSOURCE_MSI LL_RCC_I2C3_CLKSOURCE_MSI 270 #define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI 271 /** 272 * @} 273 */ 274 275 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 276 * @{ 277 */ 278 #define RCC_I2C4CLKSOURCE_PCLK1 LL_RCC_I2C4_CLKSOURCE_PCLK1 279 #define RCC_I2C4CLKSOURCE_CLKP LL_RCC_I2C4_CLKSOURCE_CLKP 280 #define RCC_I2C4CLKSOURCE_IC10 LL_RCC_I2C4_CLKSOURCE_IC10 281 #define RCC_I2C4CLKSOURCE_IC15 LL_RCC_I2C4_CLKSOURCE_IC15 282 #define RCC_I2C4CLKSOURCE_MSI LL_RCC_I2C4_CLKSOURCE_MSI 283 #define RCC_I2C4CLKSOURCE_HSI LL_RCC_I2C4_CLKSOURCE_HSI 284 /** 285 * @} 286 */ 287 288 /** @defgroup RCCEx_I3C1_Clock_Source I3C1 Clock Source 289 * @{ 290 */ 291 #define RCC_I3C1CLKSOURCE_PCLK1 LL_RCC_I3C1_CLKSOURCE_PCLK1 292 #define RCC_I3C1CLKSOURCE_CLKP LL_RCC_I3C1_CLKSOURCE_CLKP 293 #define RCC_I3C1CLKSOURCE_IC10 LL_RCC_I3C1_CLKSOURCE_IC10 294 #define RCC_I3C1CLKSOURCE_IC15 LL_RCC_I3C1_CLKSOURCE_IC15 295 #define RCC_I3C1CLKSOURCE_MSI LL_RCC_I3C1_CLKSOURCE_MSI 296 #define RCC_I3C1CLKSOURCE_HSI LL_RCC_I3C1_CLKSOURCE_HSI 297 /** 298 * @} 299 */ 300 301 /** @defgroup RCCEx_I3C2_Clock_Source I3C2 Clock Source 302 * @{ 303 */ 304 #define RCC_I3C2CLKSOURCE_PCLK1 LL_RCC_I3C2_CLKSOURCE_PCLK1 305 #define RCC_I3C2CLKSOURCE_CLKP LL_RCC_I3C2_CLKSOURCE_CLKP 306 #define RCC_I3C2CLKSOURCE_IC10 LL_RCC_I3C2_CLKSOURCE_IC10 307 #define RCC_I3C2CLKSOURCE_IC15 LL_RCC_I3C2_CLKSOURCE_IC15 308 #define RCC_I3C2CLKSOURCE_MSI LL_RCC_I3C2_CLKSOURCE_MSI 309 #define RCC_I3C2CLKSOURCE_HSI LL_RCC_I3C2_CLKSOURCE_HSI 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 315 * @{ 316 */ 317 #define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 318 #define RCC_LPTIM1CLKSOURCE_CLKP LL_RCC_LPTIM1_CLKSOURCE_CLKP 319 #define RCC_LPTIM1CLKSOURCE_IC15 LL_RCC_LPTIM1_CLKSOURCE_IC15 320 #define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE 321 #define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI 322 #define RCC_LPTIM1CLKSOURCE_TIMG LL_RCC_LPTIM1_CLKSOURCE_TIMG 323 /** 324 * @} 325 */ 326 327 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 328 * @{ 329 */ 330 #define RCC_LPTIM2CLKSOURCE_PCLK4 LL_RCC_LPTIM2_CLKSOURCE_PCLK4 331 #define RCC_LPTIM2CLKSOURCE_CLKP LL_RCC_LPTIM2_CLKSOURCE_CLKP 332 #define RCC_LPTIM2CLKSOURCE_IC15 LL_RCC_LPTIM2_CLKSOURCE_IC15 333 #define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE 334 #define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI 335 #define RCC_LPTIM2CLKSOURCE_TIMG LL_RCC_LPTIM2_CLKSOURCE_TIMG 336 /** 337 * @} 338 */ 339 340 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 341 * @{ 342 */ 343 #define RCC_LPTIM3CLKSOURCE_PCLK4 LL_RCC_LPTIM3_CLKSOURCE_PCLK4 344 #define RCC_LPTIM3CLKSOURCE_CLKP LL_RCC_LPTIM3_CLKSOURCE_CLKP 345 #define RCC_LPTIM3CLKSOURCE_IC15 LL_RCC_LPTIM3_CLKSOURCE_IC15 346 #define RCC_LPTIM3CLKSOURCE_LSE LL_RCC_LPTIM3_CLKSOURCE_LSE 347 #define RCC_LPTIM3CLKSOURCE_LSI LL_RCC_LPTIM3_CLKSOURCE_LSI 348 #define RCC_LPTIM3CLKSOURCE_TIMG LL_RCC_LPTIM3_CLKSOURCE_TIMG 349 /** 350 * @} 351 */ 352 353 /** @defgroup RCCEx_LPTIM4_Clock_Source LPTIM4 Clock Source 354 * @{ 355 */ 356 #define RCC_LPTIM4CLKSOURCE_PCLK4 LL_RCC_LPTIM4_CLKSOURCE_PCLK4 357 #define RCC_LPTIM4CLKSOURCE_CLKP LL_RCC_LPTIM4_CLKSOURCE_CLKP 358 #define RCC_LPTIM4CLKSOURCE_IC15 LL_RCC_LPTIM4_CLKSOURCE_IC15 359 #define RCC_LPTIM4CLKSOURCE_LSE LL_RCC_LPTIM4_CLKSOURCE_LSE 360 #define RCC_LPTIM4CLKSOURCE_LSI LL_RCC_LPTIM4_CLKSOURCE_LSI 361 #define RCC_LPTIM4CLKSOURCE_TIMG LL_RCC_LPTIM4_CLKSOURCE_TIMG 362 /** 363 * @} 364 */ 365 366 /** @defgroup RCCEx_LPTIM5_Clock_Source LPTIM5 Clock Source 367 * @{ 368 */ 369 #define RCC_LPTIM5CLKSOURCE_PCLK4 LL_RCC_LPTIM5_CLKSOURCE_PCLK4 370 #define RCC_LPTIM5CLKSOURCE_CLKP LL_RCC_LPTIM5_CLKSOURCE_CLKP 371 #define RCC_LPTIM5CLKSOURCE_IC15 LL_RCC_LPTIM5_CLKSOURCE_IC15 372 #define RCC_LPTIM5CLKSOURCE_LSE LL_RCC_LPTIM5_CLKSOURCE_LSE 373 #define RCC_LPTIM5CLKSOURCE_LSI LL_RCC_LPTIM5_CLKSOURCE_LSI 374 #define RCC_LPTIM5CLKSOURCE_TIMG LL_RCC_LPTIM5_CLKSOURCE_TIMG 375 /** 376 * @} 377 */ 378 379 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 380 * @{ 381 */ 382 #define RCC_LPUART1CLKSOURCE_PCLK4 LL_RCC_LPUART1_CLKSOURCE_PCLK4 383 #define RCC_LPUART1CLKSOURCE_CLKP LL_RCC_LPUART1_CLKSOURCE_CLKP 384 #define RCC_LPUART1CLKSOURCE_IC9 LL_RCC_LPUART1_CLKSOURCE_IC9 385 #define RCC_LPUART1CLKSOURCE_IC14 LL_RCC_LPUART1_CLKSOURCE_IC14 386 #define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE 387 #define RCC_LPUART1CLKSOURCE_MSI LL_RCC_LPUART1_CLKSOURCE_MSI 388 #define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI 389 /** 390 * @} 391 */ 392 393 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 394 * @{ 395 */ 396 #define RCC_LTDCCLKSOURCE_PCLK5 LL_RCC_LTDC_CLKSOURCE_PCLK5 397 #define RCC_LTDCCLKSOURCE_CLKP LL_RCC_LTDC_CLKSOURCE_CLKP 398 #define RCC_LTDCCLKSOURCE_IC16 LL_RCC_LTDC_CLKSOURCE_IC16 399 #define RCC_LTDCCLKSOURCE_HSI LL_RCC_LTDC_CLKSOURCE_HSI 400 /** 401 * @} 402 */ 403 404 /** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source 405 * @{ 406 */ 407 #define RCC_MDF1CLKSOURCE_HCLK LL_RCC_MDF1_CLKSOURCE_HCLK 408 #define RCC_MDF1CLKSOURCE_CLKP LL_RCC_MDF1_CLKSOURCE_CLKP 409 #define RCC_MDF1CLKSOURCE_IC7 LL_RCC_MDF1_CLKSOURCE_IC7 410 #define RCC_MDF1CLKSOURCE_IC8 LL_RCC_MDF1_CLKSOURCE_IC8 411 #define RCC_MDF1CLKSOURCE_MSI LL_RCC_MDF1_CLKSOURCE_MSI 412 #define RCC_MDF1CLKSOURCE_HSI LL_RCC_MDF1_CLKSOURCE_HSI 413 #define RCC_MDF1CLKSOURCE_PIN LL_RCC_MDF1_CLKSOURCE_I2S_CKIN 414 #define RCC_MDF1CLKSOURCE_TIMG LL_RCC_MDF1_CLKSOURCE_TIMG 415 /** 416 * @} 417 */ 418 419 /** @defgroup RCCEx_PSSI_Clock_Source PSSI Clock Source 420 * @{ 421 */ 422 #define RCC_PSSICLKSOURCE_HCLK LL_RCC_PSSI_CLKSOURCE_HCLK 423 #define RCC_PSSICLKSOURCE_CLKP LL_RCC_PSSI_CLKSOURCE_CLKP 424 #define RCC_PSSICLKSOURCE_IC20 LL_RCC_PSSI_CLKSOURCE_IC20 425 #define RCC_PSSICLKSOURCE_HSI LL_RCC_PSSI_CLKSOURCE_HSI 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 431 * @{ 432 */ 433 #define RCC_SAI1CLKSOURCE_PCLK2 LL_RCC_SAI1_CLKSOURCE_PCLK2 434 #define RCC_SAI1CLKSOURCE_CLKP LL_RCC_SAI1_CLKSOURCE_CLKP 435 #define RCC_SAI1CLKSOURCE_IC7 LL_RCC_SAI1_CLKSOURCE_IC7 436 #define RCC_SAI1CLKSOURCE_IC8 LL_RCC_SAI1_CLKSOURCE_IC8 437 #define RCC_SAI1CLKSOURCE_MSI LL_RCC_SAI1_CLKSOURCE_MSI 438 #define RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI 439 #define RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_I2S_CKIN 440 #define RCC_SAI1CLKSOURCE_SPDIFRX1 LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 441 /** 442 * @} 443 */ 444 445 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 446 * @{ 447 */ 448 #define RCC_SAI2CLKSOURCE_PCLK2 LL_RCC_SAI2_CLKSOURCE_PCLK2 449 #define RCC_SAI2CLKSOURCE_CLKP LL_RCC_SAI2_CLKSOURCE_CLKP 450 #define RCC_SAI2CLKSOURCE_IC7 LL_RCC_SAI2_CLKSOURCE_IC7 451 #define RCC_SAI2CLKSOURCE_IC8 LL_RCC_SAI2_CLKSOURCE_IC8 452 #define RCC_SAI2CLKSOURCE_MSI LL_RCC_SAI2_CLKSOURCE_MSI 453 #define RCC_SAI2CLKSOURCE_HSI LL_RCC_SAI2_CLKSOURCE_HSI 454 #define RCC_SAI2CLKSOURCE_PIN LL_RCC_SAI2_CLKSOURCE_I2S_CKIN 455 #define RCC_SAI2CLKSOURCE_SPDIFRX1 LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 456 /** 457 * @} 458 */ 459 460 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 461 * @{ 462 */ 463 #define RCC_SDMMC1CLKSOURCE_HCLK LL_RCC_SDMMC1_CLKSOURCE_HCLK 464 #define RCC_SDMMC1CLKSOURCE_CLKP LL_RCC_SDMMC1_CLKSOURCE_CLKP 465 #define RCC_SDMMC1CLKSOURCE_IC4 LL_RCC_SDMMC1_CLKSOURCE_IC4 466 #define RCC_SDMMC1CLKSOURCE_IC5 LL_RCC_SDMMC1_CLKSOURCE_IC5 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCCEx_SDMMC2_Clock_Source SDMMC2 Clock Source 472 * @{ 473 */ 474 #define RCC_SDMMC2CLKSOURCE_HCLK LL_RCC_SDMMC2_CLKSOURCE_HCLK 475 #define RCC_SDMMC2CLKSOURCE_CLKP LL_RCC_SDMMC2_CLKSOURCE_CLKP 476 #define RCC_SDMMC2CLKSOURCE_IC4 LL_RCC_SDMMC2_CLKSOURCE_IC4 477 #define RCC_SDMMC2CLKSOURCE_IC5 LL_RCC_SDMMC2_CLKSOURCE_IC5 478 /** 479 * @} 480 */ 481 482 /** @defgroup RCCEx_SPDIFRX1_Clock_Source SPDIFRX1 Clock Source 483 * @{ 484 */ 485 #define RCC_SPDIFRX1CLKSOURCE_PCLK1 LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 486 #define RCC_SPDIFRX1CLKSOURCE_CLKP LL_RCC_SPDIFRX1_CLKSOURCE_CLKP 487 #define RCC_SPDIFRX1CLKSOURCE_IC7 LL_RCC_SPDIFRX1_CLKSOURCE_IC7 488 #define RCC_SPDIFRX1CLKSOURCE_IC8 LL_RCC_SPDIFRX1_CLKSOURCE_IC8 489 #define RCC_SPDIFRX1CLKSOURCE_MSI LL_RCC_SPDIFRX1_CLKSOURCE_MSI 490 #define RCC_SPDIFRX1CLKSOURCE_HSI LL_RCC_SPDIFRX1_CLKSOURCE_HSI 491 #define RCC_SPDIFRX1CLKSOURCE_PIN LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN 492 /** 493 * @} 494 */ 495 496 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 497 * @{ 498 */ 499 #define RCC_SPI1CLKSOURCE_PCLK2 LL_RCC_SPI1_CLKSOURCE_PCLK2 500 #define RCC_SPI1CLKSOURCE_CLKP LL_RCC_SPI1_CLKSOURCE_CLKP 501 #define RCC_SPI1CLKSOURCE_IC8 LL_RCC_SPI1_CLKSOURCE_IC8 502 #define RCC_SPI1CLKSOURCE_IC9 LL_RCC_SPI1_CLKSOURCE_IC9 503 #define RCC_SPI1CLKSOURCE_MSI LL_RCC_SPI1_CLKSOURCE_MSI 504 #define RCC_SPI1CLKSOURCE_HSI LL_RCC_SPI1_CLKSOURCE_HSI 505 #define RCC_SPI1CLKSOURCE_PIN LL_RCC_SPI1_CLKSOURCE_I2S_CKIN 506 /** 507 * @} 508 */ 509 510 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 511 * @{ 512 */ 513 #define RCC_SPI2CLKSOURCE_PCLK1 LL_RCC_SPI2_CLKSOURCE_PCLK1 514 #define RCC_SPI2CLKSOURCE_CLKP LL_RCC_SPI2_CLKSOURCE_CLKP 515 #define RCC_SPI2CLKSOURCE_IC8 LL_RCC_SPI2_CLKSOURCE_IC8 516 #define RCC_SPI2CLKSOURCE_IC9 LL_RCC_SPI2_CLKSOURCE_IC9 517 #define RCC_SPI2CLKSOURCE_MSI LL_RCC_SPI2_CLKSOURCE_MSI 518 #define RCC_SPI2CLKSOURCE_HSI LL_RCC_SPI2_CLKSOURCE_HSI 519 #define RCC_SPI2CLKSOURCE_PIN LL_RCC_SPI2_CLKSOURCE_I2S_CKIN 520 /** 521 * @} 522 */ 523 524 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 525 * @{ 526 */ 527 #define RCC_SPI3CLKSOURCE_PCLK1 LL_RCC_SPI3_CLKSOURCE_PCLK1 528 #define RCC_SPI3CLKSOURCE_CLKP LL_RCC_SPI3_CLKSOURCE_CLKP 529 #define RCC_SPI3CLKSOURCE_IC8 LL_RCC_SPI3_CLKSOURCE_IC8 530 #define RCC_SPI3CLKSOURCE_IC9 LL_RCC_SPI3_CLKSOURCE_IC9 531 #define RCC_SPI3CLKSOURCE_MSI LL_RCC_SPI3_CLKSOURCE_MSI 532 #define RCC_SPI3CLKSOURCE_HSI LL_RCC_SPI3_CLKSOURCE_HSI 533 #define RCC_SPI3CLKSOURCE_PIN LL_RCC_SPI3_CLKSOURCE_I2S_CKIN 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 539 * @{ 540 */ 541 #define RCC_SPI4CLKSOURCE_PCLK2 LL_RCC_SPI4_CLKSOURCE_PCLK2 542 #define RCC_SPI4CLKSOURCE_CLKP LL_RCC_SPI4_CLKSOURCE_CLKP 543 #define RCC_SPI4CLKSOURCE_IC9 LL_RCC_SPI4_CLKSOURCE_IC9 544 #define RCC_SPI4CLKSOURCE_IC14 LL_RCC_SPI4_CLKSOURCE_IC14 545 #define RCC_SPI4CLKSOURCE_MSI LL_RCC_SPI4_CLKSOURCE_MSI 546 #define RCC_SPI4CLKSOURCE_HSI LL_RCC_SPI4_CLKSOURCE_HSI 547 #define RCC_SPI4CLKSOURCE_HSE LL_RCC_SPI4_CLKSOURCE_HSE 548 /** 549 * @} 550 */ 551 552 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 553 * @{ 554 */ 555 #define RCC_SPI5CLKSOURCE_PCLK2 LL_RCC_SPI5_CLKSOURCE_PCLK2 556 #define RCC_SPI5CLKSOURCE_CLKP LL_RCC_SPI5_CLKSOURCE_CLKP 557 #define RCC_SPI5CLKSOURCE_IC9 LL_RCC_SPI5_CLKSOURCE_IC9 558 #define RCC_SPI5CLKSOURCE_IC14 LL_RCC_SPI5_CLKSOURCE_IC14 559 #define RCC_SPI5CLKSOURCE_MSI LL_RCC_SPI5_CLKSOURCE_MSI 560 #define RCC_SPI5CLKSOURCE_HSI LL_RCC_SPI5_CLKSOURCE_HSI 561 #define RCC_SPI5CLKSOURCE_HSE LL_RCC_SPI5_CLKSOURCE_HSE 562 /** 563 * @} 564 */ 565 566 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 567 * @{ 568 */ 569 #define RCC_SPI6CLKSOURCE_PCLK4 LL_RCC_SPI6_CLKSOURCE_PCLK4 570 #define RCC_SPI6CLKSOURCE_CLKP LL_RCC_SPI6_CLKSOURCE_CLKP 571 #define RCC_SPI6CLKSOURCE_IC8 LL_RCC_SPI6_CLKSOURCE_IC8 572 #define RCC_SPI6CLKSOURCE_IC9 LL_RCC_SPI6_CLKSOURCE_IC9 573 #define RCC_SPI6CLKSOURCE_MSI LL_RCC_SPI6_CLKSOURCE_MSI 574 #define RCC_SPI6CLKSOURCE_HSI LL_RCC_SPI6_CLKSOURCE_HSI 575 #define RCC_SPI6CLKSOURCE_PIN LL_RCC_SPI6_CLKSOURCE_I2S_CKIN 576 /** 577 * @} 578 */ 579 580 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 581 * @{ 582 */ 583 #define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 584 #define RCC_USART1CLKSOURCE_CLKP LL_RCC_USART1_CLKSOURCE_CLKP 585 #define RCC_USART1CLKSOURCE_IC9 LL_RCC_USART1_CLKSOURCE_IC9 586 #define RCC_USART1CLKSOURCE_IC14 LL_RCC_USART1_CLKSOURCE_IC14 587 #define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE 588 #define RCC_USART1CLKSOURCE_MSI LL_RCC_USART1_CLKSOURCE_MSI 589 #define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 595 * @{ 596 */ 597 #define RCC_USART2CLKSOURCE_PCLK1 LL_RCC_USART2_CLKSOURCE_PCLK1 598 #define RCC_USART2CLKSOURCE_CLKP LL_RCC_USART2_CLKSOURCE_CLKP 599 #define RCC_USART2CLKSOURCE_IC9 LL_RCC_USART2_CLKSOURCE_IC9 600 #define RCC_USART2CLKSOURCE_IC14 LL_RCC_USART2_CLKSOURCE_IC14 601 #define RCC_USART2CLKSOURCE_LSE LL_RCC_USART2_CLKSOURCE_LSE 602 #define RCC_USART2CLKSOURCE_MSI LL_RCC_USART2_CLKSOURCE_MSI 603 #define RCC_USART2CLKSOURCE_HSI LL_RCC_USART2_CLKSOURCE_HSI 604 /** 605 * @} 606 */ 607 608 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 609 * @{ 610 */ 611 #define RCC_USART3CLKSOURCE_PCLK1 LL_RCC_USART3_CLKSOURCE_PCLK1 612 #define RCC_USART3CLKSOURCE_CLKP LL_RCC_USART3_CLKSOURCE_CLKP 613 #define RCC_USART3CLKSOURCE_IC9 LL_RCC_USART3_CLKSOURCE_IC9 614 #define RCC_USART3CLKSOURCE_IC14 LL_RCC_USART3_CLKSOURCE_IC14 615 #define RCC_USART3CLKSOURCE_LSE LL_RCC_USART3_CLKSOURCE_LSE 616 #define RCC_USART3CLKSOURCE_MSI LL_RCC_USART3_CLKSOURCE_MSI 617 #define RCC_USART3CLKSOURCE_HSI LL_RCC_USART3_CLKSOURCE_HSI 618 /** 619 * @} 620 */ 621 622 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 623 * @{ 624 */ 625 #define RCC_UART4CLKSOURCE_PCLK1 LL_RCC_UART4_CLKSOURCE_PCLK1 626 #define RCC_UART4CLKSOURCE_CLKP LL_RCC_UART4_CLKSOURCE_CLKP 627 #define RCC_UART4CLKSOURCE_IC9 LL_RCC_UART4_CLKSOURCE_IC9 628 #define RCC_UART4CLKSOURCE_IC14 LL_RCC_UART4_CLKSOURCE_IC14 629 #define RCC_UART4CLKSOURCE_LSE LL_RCC_UART4_CLKSOURCE_LSE 630 #define RCC_UART4CLKSOURCE_MSI LL_RCC_UART4_CLKSOURCE_MSI 631 #define RCC_UART4CLKSOURCE_HSI LL_RCC_UART4_CLKSOURCE_HSI 632 /** 633 * @} 634 */ 635 636 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 637 * @{ 638 */ 639 #define RCC_UART5CLKSOURCE_PCLK1 LL_RCC_UART5_CLKSOURCE_PCLK1 640 #define RCC_UART5CLKSOURCE_CLKP LL_RCC_UART5_CLKSOURCE_CLKP 641 #define RCC_UART5CLKSOURCE_IC9 LL_RCC_UART5_CLKSOURCE_IC9 642 #define RCC_UART5CLKSOURCE_IC14 LL_RCC_UART5_CLKSOURCE_IC14 643 #define RCC_UART5CLKSOURCE_LSE LL_RCC_UART5_CLKSOURCE_LSE 644 #define RCC_UART5CLKSOURCE_MSI LL_RCC_UART5_CLKSOURCE_MSI 645 #define RCC_UART5CLKSOURCE_HSI LL_RCC_UART5_CLKSOURCE_HSI 646 /** 647 * @} 648 */ 649 650 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 651 * @{ 652 */ 653 #define RCC_USART6CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK2 654 #define RCC_USART6CLKSOURCE_CLKP LL_RCC_USART6_CLKSOURCE_CLKP 655 #define RCC_USART6CLKSOURCE_IC9 LL_RCC_USART6_CLKSOURCE_IC9 656 #define RCC_USART6CLKSOURCE_IC14 LL_RCC_USART6_CLKSOURCE_IC14 657 #define RCC_USART6CLKSOURCE_LSE LL_RCC_USART6_CLKSOURCE_LSE 658 #define RCC_USART6CLKSOURCE_MSI LL_RCC_USART6_CLKSOURCE_MSI 659 #define RCC_USART6CLKSOURCE_HSI LL_RCC_USART6_CLKSOURCE_HSI 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCCEx_UART7_Clock_Source UART7 Clock Source 665 * @{ 666 */ 667 #define RCC_UART7CLKSOURCE_PCLK1 LL_RCC_UART7_CLKSOURCE_PCLK1 668 #define RCC_UART7CLKSOURCE_CLKP LL_RCC_UART7_CLKSOURCE_CLKP 669 #define RCC_UART7CLKSOURCE_IC9 LL_RCC_UART7_CLKSOURCE_IC9 670 #define RCC_UART7CLKSOURCE_IC14 LL_RCC_UART7_CLKSOURCE_IC14 671 #define RCC_UART7CLKSOURCE_LSE LL_RCC_UART7_CLKSOURCE_LSE 672 #define RCC_UART7CLKSOURCE_MSI LL_RCC_UART7_CLKSOURCE_MSI 673 #define RCC_UART7CLKSOURCE_HSI LL_RCC_UART7_CLKSOURCE_HSI 674 /** 675 * @} 676 */ 677 678 /** @defgroup RCCEx_UART8_Clock_Source UART8 Clock Source 679 * @{ 680 */ 681 #define RCC_UART8CLKSOURCE_PCLK1 LL_RCC_UART8_CLKSOURCE_PCLK1 682 #define RCC_UART8CLKSOURCE_CLKP LL_RCC_UART8_CLKSOURCE_CLKP 683 #define RCC_UART8CLKSOURCE_IC9 LL_RCC_UART8_CLKSOURCE_IC9 684 #define RCC_UART8CLKSOURCE_IC14 LL_RCC_UART8_CLKSOURCE_IC14 685 #define RCC_UART8CLKSOURCE_LSE LL_RCC_UART8_CLKSOURCE_LSE 686 #define RCC_UART8CLKSOURCE_MSI LL_RCC_UART8_CLKSOURCE_MSI 687 #define RCC_UART8CLKSOURCE_HSI LL_RCC_UART8_CLKSOURCE_HSI 688 /** 689 * @} 690 */ 691 692 /** @defgroup RCCEx_UART9_Clock_Source UART9 Clock Source 693 * @{ 694 */ 695 #define RCC_UART9CLKSOURCE_PCLK2 LL_RCC_UART9_CLKSOURCE_PCLK2 696 #define RCC_UART9CLKSOURCE_CLKP LL_RCC_UART9_CLKSOURCE_CLKP 697 #define RCC_UART9CLKSOURCE_IC9 LL_RCC_UART9_CLKSOURCE_IC9 698 #define RCC_UART9CLKSOURCE_IC14 LL_RCC_UART9_CLKSOURCE_IC14 699 #define RCC_UART9CLKSOURCE_LSE LL_RCC_UART9_CLKSOURCE_LSE 700 #define RCC_UART9CLKSOURCE_MSI LL_RCC_UART9_CLKSOURCE_MSI 701 #define RCC_UART9CLKSOURCE_HSI LL_RCC_UART9_CLKSOURCE_HSI 702 /** 703 * @} 704 */ 705 706 /** @defgroup RCCEx_USART10_Clock_Source USART10 Clock Source 707 * @{ 708 */ 709 #define RCC_USART10CLKSOURCE_PCLK2 LL_RCC_USART10_CLKSOURCE_PCLK2 710 #define RCC_USART10CLKSOURCE_CLKP LL_RCC_USART10_CLKSOURCE_CLKP 711 #define RCC_USART10CLKSOURCE_IC9 LL_RCC_USART10_CLKSOURCE_IC9 712 #define RCC_USART10CLKSOURCE_IC14 LL_RCC_USART10_CLKSOURCE_IC14 713 #define RCC_USART10CLKSOURCE_LSE LL_RCC_USART10_CLKSOURCE_LSE 714 #define RCC_USART10CLKSOURCE_MSI LL_RCC_USART10_CLKSOURCE_MSI 715 #define RCC_USART10CLKSOURCE_HSI LL_RCC_USART10_CLKSOURCE_HSI 716 /** 717 * @} 718 */ 719 720 /** @defgroup RCCEx_USBPHY1_Clock_Source USBPHY1 Clock Source 721 * @{ 722 */ 723 #define RCC_USBPHY1REFCLKSOURCE_OTGPHY1 LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 724 #define RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC 725 #define RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) 726 /** 727 * @} 728 */ 729 730 /** @defgroup RCCEx_USBPHY2_Clock_Source USBPHY2 Clock Source 731 * @{ 732 */ 733 #define RCC_USBPHY2REFCLKSOURCE_OTGPHY2 LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 734 #define RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC 735 #define RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) 736 /** 737 * @} 738 */ 739 740 /** @defgroup RCCEx_USB_OTGHS1_Clock_Source USB OTGHS1 Clock Source 741 * @{ 742 */ 743 #define RCC_USBOTGHS1CLKSOURCE_HSE_DIV2 LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 744 #define RCC_USBOTGHS1CLKSOURCE_CLKP LL_RCC_OTGPHY1_CLKSOURCE_CLKP 745 #define RCC_USBOTGHS1CLKSOURCE_IC15 LL_RCC_OTGPHY1_CLKSOURCE_IC15 746 #define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC 747 #define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) 748 /** 749 * @} 750 */ 751 752 /** @defgroup RCCEx_USB_OTGHS2_Clock_Source USB OTGHS2 Clock Source 753 * @{ 754 */ 755 #define RCC_USBOTGHS2CLKSOURCE_HSE_DIV2 LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 756 #define RCC_USBOTGHS2CLKSOURCE_CLKP LL_RCC_OTGPHY2_CLKSOURCE_CLKP 757 #define RCC_USBOTGHS2CLKSOURCE_IC15 LL_RCC_OTGPHY2_CLKSOURCE_IC15 758 #define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC 759 #define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) 760 /** 761 * @} 762 */ 763 764 /** @defgroup RCCEx_XSPI1_Clock_Source XSPI1 Clock Source 765 * @{ 766 */ 767 #define RCC_XSPI1CLKSOURCE_HCLK LL_RCC_XSPI1_CLKSOURCE_HCLK 768 #define RCC_XSPI1CLKSOURCE_CLKP LL_RCC_XSPI1_CLKSOURCE_CLKP 769 #define RCC_XSPI1CLKSOURCE_IC3 LL_RCC_XSPI1_CLKSOURCE_IC3 770 #define RCC_XSPI1CLKSOURCE_IC4 LL_RCC_XSPI1_CLKSOURCE_IC4 771 /** 772 * @} 773 */ 774 775 /** @defgroup RCCEx_XSPI2_Clock_Source XSPI2 Clock Source 776 * @{ 777 */ 778 #define RCC_XSPI2CLKSOURCE_HCLK LL_RCC_XSPI2_CLKSOURCE_HCLK 779 #define RCC_XSPI2CLKSOURCE_CLKP LL_RCC_XSPI2_CLKSOURCE_CLKP 780 #define RCC_XSPI2CLKSOURCE_IC3 LL_RCC_XSPI2_CLKSOURCE_IC3 781 #define RCC_XSPI2CLKSOURCE_IC4 LL_RCC_XSPI2_CLKSOURCE_IC4 782 /** 783 * @} 784 */ 785 786 /** @defgroup RCCEx_XSPI3_Clock_Source XSPI3 Clock Source 787 * @{ 788 */ 789 #define RCC_XSPI3CLKSOURCE_HCLK LL_RCC_XSPI3_CLKSOURCE_HCLK 790 #define RCC_XSPI3CLKSOURCE_CLKP LL_RCC_XSPI3_CLKSOURCE_CLKP 791 #define RCC_XSPI3CLKSOURCE_IC3 LL_RCC_XSPI3_CLKSOURCE_IC3 792 #define RCC_XSPI3CLKSOURCE_IC4 LL_RCC_XSPI3_CLKSOURCE_IC4 793 /** 794 * @} 795 */ 796 797 798 /** @defgroup RCCEx_TIM_Prescaler_Selection TIM Prescaler Selection 799 * @{ 800 */ 801 #define RCC_TIMPRES_DIV1 LL_RCC_TIM_PRESCALER_1 /*!< Timers clocks prescaler divide by 1 */ 802 #define RCC_TIMPRES_DIV2 LL_RCC_TIM_PRESCALER_2 /*!< Timers clocks prescaler divide by 2 */ 803 #define RCC_TIMPRES_DIV4 LL_RCC_TIM_PRESCALER_4 /*!< Timers clocks prescaler divide by 4 */ 804 #define RCC_TIMPRES_DIV8 LL_RCC_TIM_PRESCALER_8 /*!< Timers clocks prescaler divide by 8 */ 805 /** 806 * @} 807 */ 808 809 /** @defgroup RCCEx_PERIPH_FREQUENCY Peripheral clock frequency 810 * @{ 811 */ 812 #define RCC_PERIPH_FREQUENCY_NO LL_RCC_PERIPH_FREQUENCY_NO /*!< No clock enabled for the peripheral */ 813 #define RCC_PERIPH_FREQUENCY_NA LL_RCC_PERIPH_FREQUENCY_NA /*!< Frequency cannot be provided as external clock */ 814 /** 815 * @} 816 */ 817 818 /** @defgroup RCCEx_IC_Selection_Max Maximum IC Selection 819 * @{ 820 */ 821 #define RCC_IC_MAX_NUMBER 20U 822 /** 823 * @} 824 */ 825 826 /** @defgroup RCCEx_IC_Selection IC Selection 827 * @{ 828 */ 829 #define RCC_IC1 0U /*!< IC1 source is PLL1 output by default */ 830 #define RCC_IC2 1U /*!< IC2 source is PLL1 output by default */ 831 #define RCC_IC3 2U /*!< IC3 source is PLL1 output by default */ 832 #define RCC_IC4 3U /*!< IC4 source is PLL1 output by default */ 833 #define RCC_IC5 4U /*!< IC5 source is PLL1 output by default */ 834 #define RCC_IC6 5U /*!< IC6 source is PLL1 output by default */ 835 #define RCC_IC7 6U /*!< IC7 source is PLL2 output by default */ 836 #define RCC_IC8 7U /*!< IC8 source is PLL2 output by default */ 837 #define RCC_IC9 8U /*!< IC9 source is PLL2 output by default */ 838 #define RCC_IC10 9U /*!< IC10 source is PLL2 output by default */ 839 #define RCC_IC11 10U /*!< IC11 source is PLL1 output by default */ 840 #define RCC_IC12 11U /*!< IC12 source is PLL3 output by default */ 841 #define RCC_IC13 12U /*!< IC13 source is PLL3 output by default */ 842 #define RCC_IC14 13U /*!< IC14 source is PLL3 output by default */ 843 #define RCC_IC15 14U /*!< IC15 source is PLL3 output by default */ 844 #define RCC_IC16 15U /*!< IC16 source is PLL4 output by default */ 845 #define RCC_IC17 16U /*!< IC17 source is PLL4 output by default */ 846 #define RCC_IC18 17U /*!< IC18 source is PLL4 output by default */ 847 #define RCC_IC19 18U /*!< IC19 source is PLL4 output by default */ 848 #define RCC_IC20 19U /*!< IC20 source is PLL4 output by default */ 849 /** 850 * @} 851 */ 852 853 /** @defgroup RCCEx_EXTI_LINE_LSECSS LSE CSS external interrupt line 854 * @{ 855 */ 856 #define RCC_EXTI_LINE_LSECSS EXTI_IMR3_IM65 /*!< LSE CSS failure interrupt connected to direct EXTI line 65 (Tamper) */ 857 /** 858 * @} 859 */ 860 861 /** @defgroup RCC_PLL_Selection PLL selection 862 * @{ 863 */ 864 #define RCC_PLL1 0U 865 #define RCC_PLL2 1U 866 #define RCC_PLL3 2U 867 #define RCC_PLL4 3U 868 /** 869 * @} 870 */ 871 872 /** @defgroup RCC_PLL_SSCGSpread_Mode PLL SSCG spread mode selection 873 * @{ 874 */ 875 #define RCC_PLL_SSCG_CENTER 0U /*!< PLL SSCG center spread modulation */ 876 #define RCC_PLL_SSCG_DOWN 1U /*!< PLL SSCG down spread modulation */ 877 /** 878 * @} 879 */ 880 881 /** 882 * @} 883 */ 884 885 886 /* Exported types ------------------------------------------------------------*/ 887 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 888 * @{ 889 */ 890 891 /** 892 * @brief RCC extended clocks structure definition 893 */ 894 typedef struct 895 { 896 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 897 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 898 899 RCC_ICInitTypeDef ICSelection[RCC_IC_MAX_NUMBER]; /*!< ICx structure parameters. 900 This parameter shall be used when ICx is selected as kernel clock source 901 for some peripherals */ 902 903 uint32_t FmcClockSelection; /*!< Specifies FMC clock source. 904 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 905 906 uint32_t Xspi1ClockSelection; /*!< Specifies XSPI1 clock source. 907 This parameter can be a value of @ref RCCEx_XSPI1_Clock_Source */ 908 909 uint32_t Xspi2ClockSelection; /*!< Specifies XSPI2 clock source. 910 This parameter can be a value of @ref RCCEx_XSPI2_Clock_Source */ 911 912 uint32_t Xspi3ClockSelection; /*!< Specifies XSPI3 clock source. 913 This parameter can be a value of @ref RCCEx_XSPI3_Clock_Source */ 914 915 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source. 916 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 917 918 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 919 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 920 921 uint32_t AdcDivider; /*!< Specifies ADC clock divider. 922 This parameter can be a value between 1 to 256 */ 923 924 uint32_t Adf1ClockSelection; /*!< Specifies ADF1 Clock clock source. 925 This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ 926 927 uint32_t DcmippClockSelection; /*!< Specifies DCMIPP clock source. 928 This parameter can be a value of @ref RCCEx_DCMIPP_Clock_Source */ 929 930 uint32_t Eth1ClockSelection; /*!< Specifies ETH1 clock source. 931 This parameter can be a value of @ref RCCEx_ETH1_Clock_Source */ 932 933 uint32_t Eth1PhyInterfaceSelection; /*!< Specifies ETH1 PHY interface. 934 This parameter can be a value of @ref RCCEx_ETH1_PHY_Interface */ 935 936 uint32_t Eth1RxClockSelection; /*!< Specifies ETH1 RX clock source. 937 This parameter can be a value of @ref RCCEx_ETH1_RX_Clock_Source */ 938 939 uint32_t Eth1TxClockSelection; /*!< Specifies ETH1 TX clock source. 940 This parameter can be a value of @ref RCCEx_ETH1_TX_Clock_Source */ 941 942 uint32_t Eth1PtpClockSelection; /*!< Specifies ETH1 PTP clock source. 943 This parameter can be a value of @ref RCCEx_ETH1_PTP_Clock_Source */ 944 945 uint32_t Eth1PtpDivider; /*!< Specifies ETH1 PTP clock divider. 946 This parameter can be a value between 1 to 16 */ 947 948 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. 949 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 950 951 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 952 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 953 954 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 955 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 956 957 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 958 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 959 960 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 961 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 962 963 uint32_t I3c1ClockSelection; /*!< Specifies I3C1 clock source. 964 This parameter can be a value of @ref RCCEx_I3C1_Clock_Source */ 965 966 uint32_t I3c2ClockSelection; /*!< Specifies I3C2 clock source. 967 This parameter can be a value of @ref RCCEx_I3C2_Clock_Source */ 968 969 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 970 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 971 972 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 973 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 974 975 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 976 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 977 978 uint32_t Lptim4ClockSelection; /*!< Specifies LPTIM4 clock source. 979 This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source */ 980 981 uint32_t Lptim5ClockSelection; /*!< Specifies LPTIM5 clock source. 982 This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source */ 983 984 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 985 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 986 987 uint32_t LtdcClockSelection; /*!< Specifies LPUART1 clock source. 988 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 989 990 uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 Clock clock source. 991 This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ 992 993 uint32_t PssiClockSelection; /*!< Specifies PSSI clock source. 994 This parameter can be a value of @ref RCCEx_PSSI_Clock_Source */ 995 996 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 997 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 998 999 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 1000 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 1001 1002 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source. 1003 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 1004 1005 uint32_t Sdmmc2ClockSelection; /*!< Specifies SDMMC2 clock source. 1006 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ 1007 1008 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source. 1009 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 1010 1011 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source. 1012 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 1013 1014 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source. 1015 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 1016 1017 uint32_t Spi4ClockSelection; /*!< Specifies SPI4 clock source. 1018 This parameter can be a value of @ref RCCEx_SPI4_Clock_Source */ 1019 1020 uint32_t Spi5ClockSelection; /*!< Specifies SPI5 clock source. 1021 This parameter can be a value of @ref RCCEx_SPI5_Clock_Source */ 1022 1023 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source. 1024 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 1025 1026 uint32_t Spdifrx1ClockSelection; /*!< Specifies SPDIFRX1 Clock clock source. 1027 This parameter can be a value of @ref RCCEx_SPDIFRX1_Clock_Source */ 1028 1029 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 1030 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 1031 1032 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 1033 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 1034 1035 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 1036 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 1037 1038 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 1039 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 1040 1041 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 1042 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 1043 1044 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. 1045 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 1046 1047 uint32_t Uart7ClockSelection; /*!< Specifies UART7 clock source. 1048 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ 1049 1050 uint32_t Uart8ClockSelection; /*!< Specifies UART8 clock source. 1051 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ 1052 1053 uint32_t Uart9ClockSelection; /*!< Specifies UART9 clock source. 1054 This parameter can be a value of @ref RCCEx_UART9_Clock_Source */ 1055 1056 uint32_t Usart10ClockSelection; /*!< Specifies USART10 clock source. 1057 This parameter can be a value of @ref RCCEx_USART10_Clock_Source */ 1058 1059 uint32_t UsbPhy1ClockSelection; /*!< Specifies USBPHY1 clock source. 1060 This parameter can be a value of @ref RCCEx_USBPHY1_Clock_Source */ 1061 1062 uint32_t UsbOtgHs1ClockSelection; /*!< Specifies USB OTG HS1 clock source. 1063 This parameter can be a value of @ref RCCEx_USB_OTGHS1_Clock_Source */ 1064 1065 uint32_t UsbPhy2ClockSelection; /*!< Specifies USBPHY2 clock source. 1066 This parameter can be a value of @ref RCCEx_USBPHY2_Clock_Source */ 1067 1068 uint32_t UsbOtgHs2ClockSelection; /*!< Specifies USB OTG HS2 clock source. 1069 This parameter can be a value of @ref RCCEx_USB_OTGHS2_Clock_Source */ 1070 1071 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source. 1072 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 1073 1074 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 1075 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 1076 } RCC_PeriphCLKInitTypeDef; 1077 1078 /** 1079 * @brief RCC Extended PLL configuration structure definition 1080 * (allow to configure the PLL in SSCG mode) 1081 */ 1082 typedef struct 1083 { 1084 uint32_t PLLModDiv; /*!< Modulation division frequency. 1085 This parameter must be a number between Min_Data = 0 and Max_Data = 0xF */ 1086 uint32_t PLLModSpreadDepth; /*!< Modulation spread spectrum depth. 1087 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1F */ 1088 uint32_t PLLModSpreadMode; /*!< Modulation spread spectrum mode. 1089 This parameter must be a value of @ref RCC_PLL_SSCGSpread_Mode */ 1090 } RCC_PLLSSCGInitTypeDef; 1091 /** 1092 * @} 1093 */ 1094 1095 /* Exported macros -----------------------------------------------------------*/ 1096 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1097 * @{ 1098 */ 1099 1100 /** 1101 * @brief Macro to configure the PLL1 SSCG Spread Depth 1102 * @note This configuration cannot be requested when the PLL1 has been enabled. 1103 * 1104 * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. 1105 * It should be a value between 0 and 0x1F. 1106 * @retval None 1107 */ 1108 #define __HAL_RCC_PLL1_MODSPR_CONFIG(__PLLMODSPR__) \ 1109 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL1CFGR3_PLL1MODSPR_Pos) 1110 1111 /** 1112 * @brief Macro to configure the PLL1 SSCG Spread Mode 1113 * @note This configuration cannot be requested when the PLL1 has been enabled. 1114 * 1115 * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. 1116 * It should be a value of @ref RCC_PLL_SSCGSpread_Mode 1117 * @retval None 1118 */ 1119 #define __HAL_RCC_PLL1_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ 1120 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) 1121 1122 1123 /** 1124 * @brief Macro to configure the PLL2 SSCG Spread Depth 1125 * @note This configuration cannot be requested when the PLL2 has been enabled. 1126 * 1127 * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. 1128 * It should be a value between 0 and 0x1F. 1129 * @retval None 1130 */ 1131 #define __HAL_RCC_PLL2_MODSPR_CONFIG(__PLLMODSPR__) \ 1132 MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL2CFGR3_PLL2MODSPR_Pos) 1133 1134 /** 1135 * @brief Macro to configure the PLL2 SSCG Spread Mode 1136 * @note This configuration cannot be requested when the PLL2 has been enabled. 1137 * 1138 * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. 1139 * It should be a value of @ref RCC_PLL_SSCGSpread_Mode 1140 * @retval None 1141 */ 1142 #define __HAL_RCC_PLL2_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ 1143 MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) 1144 1145 1146 /** 1147 * @brief Macro to configure the PLL3 SSCG Spread Depth 1148 * @note This configuration cannot be requested when the PLL3 has been enabled. 1149 * 1150 * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. 1151 * It should be a value between 0 and 0x1F. 1152 * @retval None 1153 */ 1154 #define __HAL_RCC_PLL3_MODSPR_CONFIG(__PLLMODSPR__) \ 1155 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL3CFGR3_PLL3MODSPR_Pos) 1156 1157 /** 1158 * @brief Macro to configure the PLL3 SSCG Spread Mode 1159 * @note This configuration cannot be requested when the PLL3 has been enabled. 1160 * 1161 * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. 1162 * It should be a value of @ref RCC_PLL_SSCGSpread_Mode 1163 * @retval None 1164 */ 1165 #define __HAL_RCC_PLL3_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ 1166 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) 1167 1168 1169 /** 1170 * @brief Macro to configure the PLL4 SSCG Spread Depth 1171 * @note This configuration cannot be requested when the PLL4 has been enabled. 1172 * 1173 * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. 1174 * It should be a value between 0 and 0x1F. 1175 * @retval None 1176 */ 1177 #define __HAL_RCC_PLL4_MODSPR_CONFIG(__PLLMODSPR__) \ 1178 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL4CFGR3_PLL4MODSPR_Pos) 1179 1180 /** 1181 * @brief Macro to configure the PLL4 SSCG Spread Mode 1182 * @note This configuration cannot be requested when the PLL4 has been enabled. 1183 * 1184 * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. 1185 * It should be a value of @ref RCC_PLL_SSCGSpread_Mode 1186 * @retval None 1187 */ 1188 #define __HAL_RCC_PLL4_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ 1189 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) 1190 1191 1192 /** @brief Macro to configure the ADC clock 1193 * @param __ADC_CLKSOURCE__ specifies the ADC clock source. 1194 * This parameter can be one of the following values: 1195 * @arg RCC_ADCCLKSOURCE_HCLK HCLK Clock selected as ADC clock 1196 * @arg RCC_ADCCLKSOURCE_CLKP CLKP selected as ADC clock 1197 * @arg RCC_ADCCLKSOURCE_IC7 IC7 selected as ADC clock 1198 * @arg RCC_ADCCLKSOURCE_IC8 IC8 selected as ADC clock 1199 * @arg RCC_ADCCLKSOURCE_MSI MSI selected as ADC clock 1200 * @arg RCC_ADCCLKSOURCE_HSI HSI selected as ADC clock 1201 * @arg RCC_ADCCLKSOURCE_PIN External I2S_CKIN selected as ADC clock 1202 * @arg RCC_ADCCLKSOURCE_TIMG TIMG selected as ADC clock 1203 */ 1204 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 1205 LL_RCC_SetADCClockSource((__ADC_CLKSOURCE__)) 1206 1207 /** @brief Macro to get the ADC clock source. 1208 * @retval The clock source can be one of the following values: 1209 * @arg RCC_ADCCLKSOURCE_HCLK HCLK Clock selected as ADC clock 1210 * @arg RCC_ADCCLKSOURCE_CLKP CLKP selected as ADC clock 1211 * @arg RCC_ADCCLKSOURCE_IC7 IC7 selected as ADC clock 1212 * @arg RCC_ADCCLKSOURCE_IC8 IC8 selected as ADC clock 1213 * @arg RCC_ADCCLKSOURCE_MSI MSI selected as ADC clock 1214 * @arg RCC_ADCCLKSOURCE_HSI HSI selected as ADC clock 1215 * @arg RCC_ADCCLKSOURCE_PIN External I2S_CKIN selected as ADC clock 1216 * @arg RCC_ADCCLKSOURCE_TIMG TIMG selected as ADC clock 1217 */ 1218 #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) 1219 1220 /** @brief Macro to configure the ADC clock divider. 1221 * @param __ADC_DIVIDER__ specifies clock divider for ADC. 1222 * This parameter can be a value between 1 and 256. 1223 */ 1224 #define __HAL_RCC_ADC_DIVIDER_CONFIG(__ADC_DIVIDER__) LL_RCC_SetADCPrescaler((__ADC_DIVIDER__) - 1U) 1225 1226 /** @brief Macro to get the ADC clock divider. 1227 * @retval The divider can be a value between 1 and 256. 1228 */ 1229 #define __HAL_RCC_GET_ADC_DIVIDER() (LL_RCC_GetADCPrescaler() + 1U) 1230 1231 /** @brief Macro to configure the ADF1 clock 1232 * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. 1233 * This parameter can be one of the following values: 1234 * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 1235 * @arg RCC_ADF1CLKSOURCE_CLKP CLKP selected as ADF1 clock 1236 * @arg RCC_ADF1CLKSOURCE_IC7 IC7 selected as ADF1 clock 1237 * @arg RCC_ADF1CLKSOURCE_IC8 IC8 selected as ADF1 clock 1238 * @arg RCC_ADF1CLKSOURCE_MSI MSI selected as ADF1 clock 1239 * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock 1240 * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock 1241 * @arg RCC_ADF1CLKSOURCE_TIMG TIMG selected as ADF1 clock 1242 */ 1243 #define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ 1244 LL_RCC_SetADFClockSource((__ADF1_CLKSOURCE__)) 1245 1246 /** @brief Macro to get the ADF1 clock source. 1247 * @retval The clock source can be one of the following values: 1248 * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 1249 * @arg RCC_ADF1CLKSOURCE_CLKP CLKP selected as ADF1 clock 1250 * @arg RCC_ADF1CLKSOURCE_IC7 IC7 selected as ADF1 clock 1251 * @arg RCC_ADF1CLKSOURCE_IC8 IC8 selected as ADF1 clock 1252 * @arg RCC_ADF1CLKSOURCE_MSI MSI selected as ADF1 clock 1253 * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock 1254 * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock 1255 * @arg RCC_ADF1CLKSOURCE_TIMG TIMG selected as ADF1 clock 1256 */ 1257 #define __HAL_RCC_GET_ADF1_SOURCE() LL_RCC_GetADFClockSource(LL_RCC_ADF1_CLKSOURCE) 1258 1259 /** @brief Macro to configure the CLKP clock for peripheral 1260 * @param __CLKP_CLKSOURCE__ specifies the clock for peripheral 1261 * This parameter can be one of the following values: 1262 * @arg RCC_CLKPCLKSOURCE_HSI HSI selected as CLKP clock 1263 * @arg RCC_CLKPCLKSOURCE_MSI MSI selected as CLKP clock 1264 * @arg RCC_CLKPCLKSOURCE_HSE HSE selected as CLKP clock 1265 * @arg RCC_CLKPCLKSOURCE_IC5 IC5 selected as CLKP clock 1266 * @arg RCC_CLKPCLKSOURCE_IC10 IC10 selected as CLKP clock 1267 * @arg RCC_CLKPCLKSOURCE_IC15 IC15 selected as CLKP clock 1268 * @arg RCC_CLKPCLKSOURCE_IC19 IC19 selected as CLKP clock 1269 * @arg RCC_CLKPCLKSOURCE_IC20 IC20 selected as CLKP clock 1270 */ 1271 #define __HAL_RCC_CLKP_CONFIG(__CLKP_CLKSOURCE__) \ 1272 LL_RCC_SetCLKPClockSource((__CLKP_CLKSOURCE__)) 1273 1274 /** @brief Macro to get the Oscillator clock for peripheral source. 1275 * @retval The clock source can be one of the following values: 1276 * @arg RCC_CLKPCLKSOURCE_HSI HSI selected as CLKP clock 1277 * @arg RCC_CLKPCLKSOURCE_MSI MSI selected as CLKP clock 1278 * @arg RCC_CLKPCLKSOURCE_HSE HSE selected as CLKP clock 1279 * @arg RCC_CLKPCLKSOURCE_IC5 IC5 selected as CLKP clock 1280 * @arg RCC_CLKPCLKSOURCE_IC10 IC10 selected as CLKP clock 1281 * @arg RCC_CLKPCLKSOURCE_IC15 IC15 selected as CLKP clock 1282 * @arg RCC_CLKPCLKSOURCE_IC19 IC19 selected as CLKP clock 1283 * @arg RCC_CLKPCLKSOURCE_IC20 IC20 selected as CLKP clock 1284 */ 1285 #define __HAL_RCC_GET_CLKP_SOURCE() LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE) 1286 1287 /** @brief Macro to configure the DCMIPP clock source. 1288 * 1289 * @param __DCMIPP_CLKSOURCE__ specifies the DCMIPP clock source. 1290 * @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock 1291 * @arg RCC_DCMIPPCLKSOURCE_CLKP CLKP selected as DCMIPP clock 1292 * @arg RCC_DCMIPPCLKSOURCE_IC17 IC17 selected as DCMIPP clock 1293 * @arg RCC_DCMIPPCLKSOURCE_HSI HSI selected as DCMIPP clock 1294 */ 1295 #define __HAL_RCC_DCMIPP_CONFIG(__DCMIPP_CLKSOURCE__) \ 1296 LL_RCC_SetDCMIPPClockSource((__DCMIPP_CLKSOURCE__)) 1297 1298 /** @brief Macro to get the DCMIPP clock source. 1299 * @retval The clock source can be one of the following values: 1300 * @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock 1301 * @arg RCC_DCMIPPCLKSOURCE_CLKP CLKP selected as DCMIPP clock 1302 * @arg RCC_DCMIPPCLKSOURCE_IC17 IC17 elected as DCMIPP clock 1303 * @arg RCC_DCMIPPCLKSOURCE_HSI HSI selected as DCMIPP clock 1304 */ 1305 #define __HAL_RCC_GET_DCMIPP_SOURCE() LL_RCC_GetDCMIPPClockSource(LL_RCC_DCMIPP_CLKSOURCE) 1306 1307 /** @brief Macro to configure the ETH1 kernel clock source. 1308 * @param __ETH1_CLKSOURCE__ specifies clock source for ETH1 1309 * This parameter can be one of the following values: 1310 * @arg RCC_ETH1CLKSOURCE_HCLK HCLK selected as ETH1 clock 1311 * @arg RCC_ETH1CLKSOURCE_CLKP CLKP selected as ETH1 clock 1312 * @arg RCC_ETH1CLKSOURCE_IC12 IC12 selected as ETH1 clock 1313 * @arg RCC_ETH1CLKSOURCE_HSE HSE selected as ETH1 clock 1314 */ 1315 #define __HAL_RCC_ETH1_CONFIG(__ETH1_CLKSOURCE__) \ 1316 LL_RCC_SetETHClockSource(__ETH1_CLKSOURCE__) 1317 1318 /** @brief Macro to get the ETH1 kernel clock source. 1319 * @retval The clock source can be one of the following values: 1320 * @arg RCC_ETH1CLKSOURCE_HCLK HCLK selected as ETH1 clock 1321 * @arg RCC_ETH1CLKSOURCE_CLKP CLKP selected as ETH1 clock 1322 * @arg RCC_ETH1CLKSOURCE_IC12 IC12 selected as ETH1 clock 1323 * @arg RCC_ETH1CLKSOURCE_HSE HSE selected as ETH1 clock 1324 */ 1325 #define __HAL_RCC_GET_ETH1_SOURCE() LL_RCC_GetETHClockSource(LL_RCC_ETH1_CLKSOURCE) 1326 1327 /** @brief Macro to configure the ETH1 PHY interface. 1328 * @note This configuration must be done while ETH1 is under reset, 1329 * and before enabling the ETH1 clocks 1330 * @param __ETH1PHY_IF__ specifies interface for ETH1 PHY 1331 * This parameter can be one of the following values: 1332 * @arg RCC_ETH1PHYIF_MII MII selected as ETH1 PHY interface 1333 * @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface 1334 * @arg RCC_ETH1PHYIF_RMII RMII selected as ETH1 PHY interface 1335 */ 1336 #define __HAL_RCC_ETH1PHY_CONFIG(__ETH1PHY_IF__) \ 1337 LL_RCC_SetETHPHYInterface(__ETH1PHY_IF__) 1338 1339 /** @brief Macro to get the ETH PHY clock source. 1340 * @retval The clock source can be one of the following values: 1341 * @arg RCC_ETH1PHYIF_MII MII selected as ETH1 PHY interface 1342 * @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface 1343 * @arg RCC_ETH1PHYIF_RMII RMII selected as ETH1 PHY interface 1344 */ 1345 #define __HAL_RCC_GET_ETH1PHY_INTERFACE() LL_RCC_GetETHPHYInterface(LL_RCC_ETH1PHY_IF) 1346 1347 /** @brief Macro to configure the ETH1 reference Rx clock source. 1348 * @param __ETH1RX_CLKSOURCE__ specifies clock source for ETH1 reference Rx 1349 * This parameter can be one of the following values: 1350 * @arg RCC_ETH1RXCLKSOURCE_EXT External clock selected as ETH1 reference Rx clock 1351 * @arg RCC_ETH1RXCLKSOURCE_INT Internal kernel selected as ETH1 reference Rx clock 1352 */ 1353 #define __HAL_RCC_ETH1RX_CONFIG(__ETH1RX_CLKSOURCE__) \ 1354 LL_RCC_SetETHREFRXClockSource(__ETH1RX_CLKSOURCE__) 1355 1356 /** @brief Macro to get the ETH1 reference Rx clock source. 1357 * @retval The clock source can be one of the following values: 1358 * @arg RCC_ETH1RXCLKSOURCE_EXT External clock selected as ETH1 reference Rx clock 1359 * @arg RCC_ETH1RXCLKSOURCE_INT Internal kernel selected as ETH1 reference Rx clock 1360 */ 1361 #define __HAL_RCC_GET_ETH1RX_SOURCE() LL_RCC_GetETHREFRXClockSource(LL_RCC_ETH1REFRX_CLKSOURCE) 1362 1363 /** @brief Macro to configure the ETH1 reference Tx RGMII 125MHz clock source. 1364 * @param __ETH1TX_CLKSOURCE__ specifies clock source for ETH1 reference Tx 1365 * This parameter can be one of the following values: 1366 * @arg RCC_ETH1TXCLKSOURCE_EXT External clock selected as ETH1 reference Tx clock 1367 * @arg RCC_ETH1TXCLKSOURCE_INT Internal kernel selected as ETH1 reference Tx clock 1368 */ 1369 #define __HAL_RCC_ETH1TX_CONFIG(__ETH1TX_CLKSOURCE__) \ 1370 LL_RCC_SetETHREFTXClockSource(__ETH1TX_CLKSOURCE__) 1371 1372 /** @brief Macro to get the ETH1 reference Tx RGMII 125MHz clock source. 1373 * @retval The clock source can be one of the following values: 1374 * @arg RCC_ETH1TXCLKSOURCE_EXT External clock selected as ETH1 reference Tx clock 1375 * @arg RCC_ETH1TXCLKSOURCE_INT Internal kernel selected as ETH1 reference Tx clock 1376 */ 1377 #define __HAL_RCC_GET_ETH1TX_SOURCE() LL_RCC_GetETHREFTXClockSource(LL_RCC_ETH1REFTX_CLKSOURCE) 1378 1379 /** @brief Macro to configure the ETH1 PTP clock source. 1380 * @param __ETH1PTP_CLKSOURCE__ specifies clock source for ETH1 PTP 1381 * This parameter can be one of the following values: 1382 * @arg RCC_ETH1PTPCLKSOURCE_HCLK HCLK selected as ETH1 PTP clock 1383 * @arg RCC_ETH1PTPCLKSOURCE_CLKP CLKP selected as ETH1 PTP clock 1384 * @arg RCC_ETH1PTPCLKSOURCE_IC13 IC13 selected as ETH1 PTP clock 1385 * @arg RCC_ETH1PTPCLKSOURCE_HSE HSE selected as ETH1 PTP clock 1386 */ 1387 #define __HAL_RCC_ETH1PTP_CONFIG(__ETH1PTP_CLKSOURCE__) \ 1388 LL_RCC_SetETHPTPClockSource(__ETH1PTP_CLKSOURCE__) 1389 1390 /** @brief Macro to get the ETH1 PTP clock source. 1391 * @retval The clock source can be one of the following values: 1392 * @arg RCC_ETH1PTPCLKSOURCE_HCLK HCLK selected as ETH1 PTP clock 1393 * @arg RCC_ETH1PTPCLKSOURCE_CLKP CLKP selected as ETH1 PTP clock 1394 * @arg RCC_ETH1PTPCLKSOURCE_IC13 IC13 selected as ETH1 PTP clock 1395 * @arg RCC_ETH1PTPCLKSOURCE_HSE HSE selected as ETH1 PTP clock 1396 */ 1397 #define __HAL_RCC_GET_ETH1PTP_SOURCE() LL_RCC_GetETHPTPClockSource(LL_RCC_ETH1PTP_CLKSOURCE) 1398 1399 /** @brief Macro to configure the ETH1 PTP divider. 1400 * @param __ETH1PTP_DIVIDER__ specifies clock divider for ETH1 PTP 1401 * This parameter can be a value between 1 and 16. 1402 */ 1403 #define __HAL_RCC_ETH1PTP_DIVIDER_CONFIG(__ETH1PTP_DIVIDER__) \ 1404 LL_RCC_SetETH1PTPDivider(((__ETH1PTP_DIVIDER__) - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos) 1405 1406 /** @brief Macro to get the ETH1 PTP divider. 1407 * @retval The divider can be a value between 1 and 16. 1408 */ 1409 #define __HAL_RCC_GET_ETH1PTP_DIVIDER() \ 1410 ((LL_RCC_GetETH1PTPDivider() >> RCC_CCIPR2_ETH1PTPDIV_Pos) + 1U) 1411 1412 /** @brief Macro to configure the FDCAN kernel clock source. 1413 * @param __FDCAN_CLKSOURCE__ specifies clock source for FDCAN kernel 1414 * This parameter can be one of the following values: 1415 * @arg RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as FDCAN kernel clock (default) 1416 * @arg RCC_FDCANCLKSOURCE_CLKP CLKP selected as FDCAN kernel clock 1417 * @arg RCC_FDCANCLKSOURCE_IC19 IC19 selected as FDCAN kernel clock 1418 * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1419 */ 1420 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1421 LL_RCC_SetFDCANClockSource((__FDCAN_CLKSOURCE__)) 1422 1423 /** @brief Macro to get the FDCAN kernel clock source. 1424 * @retval The clock source can be one of the following values: 1425 * @arg RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as FDCAN kernel clock (default) 1426 * @arg RCC_FDCANCLKSOURCE_CLKP CLKP selected as FDCAN kernel clock 1427 * @arg RCC_FDCANCLKSOURCE_IC19 IC19 selected as FDCAN kernel clock 1428 * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1429 */ 1430 #define __HAL_RCC_GET_FDCAN_SOURCE() LL_RCC_GetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE) 1431 1432 /** @brief Macro to configure the FMC clock source. 1433 * 1434 * @param __FMC_CLKSOURCE__ specifies the FMC clock source. 1435 * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock 1436 * @arg RCC_FMCCLKSOURCE_CLKP CLKP Clock selected as FMC clock 1437 * @arg RCC_FMCCLKSOURCE_IC3 IC3 Clock selected as FMC clock 1438 * @arg RCC_FMCCLKSOURCE_IC4 IC4 selected as FMC clock 1439 */ 1440 #define __HAL_RCC_FMC_CONFIG(__FMC_CLKSOURCE__) \ 1441 LL_RCC_SetFMCClockSource((__FMC_CLKSOURCE__)) 1442 1443 /** @brief Macro to get the FMC clock source. 1444 * @retval The clock source can be one of the following values: 1445 * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock 1446 * @arg RCC_FMCCLKSOURCE_CLKP CLKP Clock selected as FMC clock 1447 * @arg RCC_FMCCLKSOURCE_IC3 IC3 Clock selected as FMC clock 1448 * @arg RCC_FMCCLKSOURCE_IC4 IC4 selected as FMC clock 1449 */ 1450 #define __HAL_RCC_GET_FMC_SOURCE() LL_RCC_GetFMCClockSource(LL_RCC_FMC_CLKSOURCE) 1451 1452 /** @brief Macro to configure the I2C1 clock source. 1453 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1454 * This parameter can be one of the following values: 1455 * @arg RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1456 * @arg RCC_I2C1CLKSOURCE_CLKP CKLP selected as I2C1 clock 1457 * @arg RCC_I2C1CLKSOURCE_IC10 IC10 selected as I2C1 clock 1458 * @arg RCC_I2C1CLKSOURCE_IC15 IC15 selected as I2C1 clock 1459 * @arg RCC_I2C1CLKSOURCE_MSI MSI selected as I2C1 clock 1460 * @arg RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1461 */ 1462 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1463 LL_RCC_SetI2CClockSource((__I2C1_CLKSOURCE__)) 1464 1465 /** @brief Macro to get the I2C1 clock source. 1466 * @retval The clock source can be one of the following values: 1467 * @arg RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1468 * @arg RCC_I2C1CLKSOURCE_CLKP CKLP selected as I2C1 clock 1469 * @arg RCC_I2C1CLKSOURCE_IC10 IC10 selected as I2C1 clock 1470 * @arg RCC_I2C1CLKSOURCE_IC15 IC15 selected as I2C1 clock 1471 * @arg RCC_I2C1CLKSOURCE_MSI MSI selected as I2C1 clock 1472 * @arg RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1473 */ 1474 #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) 1475 1476 /** @brief Macro to configure the I2C2 clock source. 1477 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1478 * This parameter can be one of the following values: 1479 * @arg RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1480 * @arg RCC_I2C2CLKSOURCE_CLKP CKLP selected as I2C2 clock 1481 * @arg RCC_I2C2CLKSOURCE_IC10 IC10 selected as I2C2 clock 1482 * @arg RCC_I2C2CLKSOURCE_IC15 IC15 selected as I2C2 clock 1483 * @arg RCC_I2C2CLKSOURCE_MSI MSI selected as I2C2 clock 1484 * @arg RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1485 */ 1486 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1487 LL_RCC_SetI2CClockSource((__I2C2_CLKSOURCE__)) 1488 1489 /** @brief Macro to get the I2C2 clock source. 1490 * @retval The clock source can be one of the following values: 1491 * @arg RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1492 * @arg RCC_I2C2CLKSOURCE_CLKP CKLP selected as I2C2 clock 1493 * @arg RCC_I2C2CLKSOURCE_IC10 IC10 selected as I2C2 clock 1494 * @arg RCC_I2C2CLKSOURCE_IC15 IC15 selected as I2C2 clock 1495 * @arg RCC_I2C2CLKSOURCE_MSI MSI selected as I2C2 clock 1496 * @arg RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1497 */ 1498 #define __HAL_RCC_GET_I2C2_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE) 1499 1500 /** @brief Macro to configure the I2C3 clock source. 1501 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1502 * This parameter can be one of the following values: 1503 * @arg RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1504 * @arg RCC_I2C3CLKSOURCE_CLKP CKLP selected as I2C3 clock 1505 * @arg RCC_I2C3CLKSOURCE_IC10 IC10 selected as I2C3 clock 1506 * @arg RCC_I2C3CLKSOURCE_IC15 IC15 selected as I2C3 clock 1507 * @arg RCC_I2C3CLKSOURCE_MSI MSI selected as I2C3 clock 1508 * @arg RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1509 */ 1510 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1511 LL_RCC_SetI2CClockSource((__I2C3_CLKSOURCE__)) 1512 1513 /** @brief Macro to get the I2C3 clock source. 1514 * @retval The clock source can be one of the following values: 1515 * @arg RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1516 * @arg RCC_I2C3CLKSOURCE_CLKP CKLP selected as I2C3 clock 1517 * @arg RCC_I2C3CLKSOURCE_IC10 IC10 selected as I2C3 clock 1518 * @arg RCC_I2C3CLKSOURCE_IC15 IC15 selected as I2C3 clock 1519 * @arg RCC_I2C3CLKSOURCE_MSI MSI selected as I2C3 clock 1520 * @arg RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1521 */ 1522 #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) 1523 1524 /** @brief Macro to configure the I2C4 clock source. 1525 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1526 * This parameter can be one of the following values: 1527 * @arg RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1528 * @arg RCC_I2C4CLKSOURCE_CLKP CKLP selected as I2C4 clock 1529 * @arg RCC_I2C4CLKSOURCE_IC10 IC10 selected as I2C4 clock 1530 * @arg RCC_I2C4CLKSOURCE_IC15 IC15 selected as I2C4 clock 1531 * @arg RCC_I2C4CLKSOURCE_MSI MSI selected as I2C4 clock 1532 * @arg RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1533 */ 1534 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1535 LL_RCC_SetI2CClockSource((__I2C4_CLKSOURCE__)) 1536 1537 /** @brief Macro to get the I2C4 clock source. 1538 * @retval The clock source can be one of the following values: 1539 * @arg RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1540 * @arg RCC_I2C4CLKSOURCE_CLKP CKLP selected as I2C4 clock 1541 * @arg RCC_I2C4CLKSOURCE_IC10 IC10 selected as I2C4 clock 1542 * @arg RCC_I2C4CLKSOURCE_IC15 IC15 selected as I2C4 clock 1543 * @arg RCC_I2C4CLKSOURCE_MSI MSI selected as I2C4 clock 1544 * @arg RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1545 */ 1546 #define __HAL_RCC_GET_I2C4_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C4_CLKSOURCE) 1547 1548 /** @brief Macro to configure the I3C1 clock source. 1549 * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. 1550 * This parameter can be one of the following values: 1551 * @arg RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 1552 * @arg RCC_I3C1CLKSOURCE_CLKP CKLP selected as I3C1 clock 1553 * @arg RCC_I3C1CLKSOURCE_IC10 IC10 selected as I3C1 clock 1554 * @arg RCC_I3C1CLKSOURCE_IC15 IC15 selected as I3C1 clock 1555 * @arg RCC_I3C1CLKSOURCE_MSI MSI selected as I3C1 clock 1556 * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 1557 */ 1558 #define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ 1559 LL_RCC_SetI3CClockSource((__I3C1_CLKSOURCE__)) 1560 1561 /** @brief Macro to get the I3C1 clock source. 1562 * @retval The clock source can be one of the following values: 1563 * @arg RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 1564 * @arg RCC_I3C1CLKSOURCE_CLKP CKLP selected as I3C1 clock 1565 * @arg RCC_I3C1CLKSOURCE_IC10 IC10 selected as I3C1 clock 1566 * @arg RCC_I3C1CLKSOURCE_IC15 IC15 selected as I3C1 clock 1567 * @arg RCC_I3C1CLKSOURCE_MSI MSI selected as I3C1 clock 1568 * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 1569 */ 1570 #define __HAL_RCC_GET_I3C1_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C1_CLKSOURCE) 1571 1572 /** @brief Macro to configure the I3C2 clock source. 1573 * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. 1574 * This parameter can be one of the following values: 1575 * @arg RCC_I3C2CLKSOURCE_PCLK1 PCLK1 selected as I3C2 clock 1576 * @arg RCC_I3C2CLKSOURCE_CLKP CKLP selected as I3C2 clock 1577 * @arg RCC_I3C2CLKSOURCE_IC10 IC10 selected as I3C2 clock 1578 * @arg RCC_I3C2CLKSOURCE_IC15 IC15 selected as I3C2 clock 1579 * @arg RCC_I3C2CLKSOURCE_MSI MSI selected as I3C2 clock 1580 * @arg RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 1581 */ 1582 #define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ 1583 LL_RCC_SetI3CClockSource((__I3C2_CLKSOURCE__)) 1584 1585 /** @brief Macro to get the I3C2 clock source. 1586 * @retval The clock source can be one of the following values: 1587 * @arg RCC_I3C2CLKSOURCE_PCLK1 PCLK1 selected as I3C2 clock 1588 * @arg RCC_I3C2CLKSOURCE_CLKP CKLP selected as I3C2 clock 1589 * @arg RCC_I3C2CLKSOURCE_IC10 IC10 selected as I3C2 clock 1590 * @arg RCC_I3C2CLKSOURCE_IC15 IC15 selected as I3C2 clock 1591 * @arg RCC_I3C2CLKSOURCE_MSI MSI selected as I3C2 clock 1592 * @arg RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 1593 */ 1594 #define __HAL_RCC_GET_I3C2_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C2_CLKSOURCE) 1595 1596 /** @brief Macro to configure the LPTIM1 clock source. 1597 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1598 * This parameter can be one of the following values: 1599 * @arg RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 clock selected as LPTIM1 clock 1600 * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP clock selected as LPTIM1 clock 1601 * @arg RCC_LPTIM1CLKSOURCE_IC15 IC15 clock selected as LPTIM1 clock 1602 * @arg RCC_LPTIM1CLKSOURCE_LSE LSE clock selected as LPTIM1 clock 1603 * @arg RCC_LPTIM1CLKSOURCE_LSI LSI clock selected as LPTIM1 clock 1604 * @arg RCC_LPTIM1CLKSOURCE_TIMG TIMG clock selected as LPTIM1 clock 1605 */ 1606 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1607 LL_RCC_SetLPTIMClockSource((__LPTIM1_CLKSOURCE__)) 1608 1609 /** @brief Macro to get the LPTIM1 clock source. 1610 * @retval The clock source can be one of the following values: 1611 * @arg RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 clock selected as LPTIM1 clock 1612 * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP clock selected as LPTIM1 clock 1613 * @arg RCC_LPTIM1CLKSOURCE_IC15 IC15 clock selected as LPTIM1 clock 1614 * @arg RCC_LPTIM1CLKSOURCE_LSE LSE clock selected as LPTIM1 clock 1615 * @arg RCC_LPTIM1CLKSOURCE_LSI LSI clock selected as LPTIM1 clock 1616 * @arg RCC_LPTIM1CLKSOURCE_TIMG TIMG clock selected as LPTIM1 clock 1617 */ 1618 #define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE) 1619 1620 /** @brief Macro to configure the LPTIM2 clock source. 1621 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1622 * This parameter can be one of the following values: 1623 * @arg RCC_LPTIM2CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM2 clock 1624 * @arg RCC_LPTIM2CLKSOURCE_CLKP CLKP clock selected as LPTIM2 clock 1625 * @arg RCC_LPTIM2CLKSOURCE_IC15 IC15 clock selected as LPTIM2 clock 1626 * @arg RCC_LPTIM2CLKSOURCE_LSE LSE clock selected as LPTIM2 clock 1627 * @arg RCC_LPTIM2CLKSOURCE_LSI LSI clock selected as LPTIM2 clock 1628 * @arg RCC_LPTIM2CLKSOURCE_TIMG TIMG clock selected as LPTIM2 clock 1629 */ 1630 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1631 LL_RCC_SetLPTIMClockSource((__LPTIM2_CLKSOURCE__)) 1632 1633 /** @brief Macro to get the LPTIM2 clock source. 1634 * @retval The clock source can be one of the following values: 1635 * @arg RCC_LPTIM2CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM2 clock 1636 * @arg RCC_LPTIM2CLKSOURCE_CLKP CLKP clock selected as LPTIM2 clock 1637 * @arg RCC_LPTIM2CLKSOURCE_IC15 IC15 clock selected as LPTIM2 clock 1638 * @arg RCC_LPTIM2CLKSOURCE_LSE LSE clock selected as LPTIM2 clock 1639 * @arg RCC_LPTIM2CLKSOURCE_LSI LSI clock selected as LPTIM2 clock 1640 * @arg RCC_LPTIM2CLKSOURCE_TIMG TIMG clock selected as LPTIM2 clock 1641 */ 1642 #define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE) 1643 1644 /** @brief Macro to configure the LPTIM3 clock source. 1645 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 1646 * This parameter can be one of the following values: 1647 * @arg RCC_LPTIM3CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM3 clock 1648 * @arg RCC_LPTIM3CLKSOURCE_CLKP CLKP clock selected as LPTIM3 clock 1649 * @arg RCC_LPTIM3CLKSOURCE_IC15 IC15 clock selected as LPTIM3 clock 1650 * @arg RCC_LPTIM3CLKSOURCE_LSE LSE clock selected as LPTIM3 clock 1651 * @arg RCC_LPTIM3CLKSOURCE_LSI LSI clock selected as LPTIM3 clock 1652 * @arg RCC_LPTIM3CLKSOURCE_TIMG TIMG clock selected as LPTIM3 clock 1653 */ 1654 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 1655 LL_RCC_SetLPTIMClockSource((__LPTIM3_CLKSOURCE__)) 1656 1657 /** @brief Macro to get the LPTIM3 clock source. 1658 * @retval The clock source can be one of the following values: 1659 * @arg RCC_LPTIM3CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM3 clock 1660 * @arg RCC_LPTIM3CLKSOURCE_CLKP CLKP clock selected as LPTIM3 clock 1661 * @arg RCC_LPTIM3CLKSOURCE_IC15 IC15 clock selected as LPTIM3 clock 1662 * @arg RCC_LPTIM3CLKSOURCE_LSE LSE clock selected as LPTIM3 clock 1663 * @arg RCC_LPTIM3CLKSOURCE_LSI LSI clock selected as LPTIM3 clock 1664 * @arg RCC_LPTIM3CLKSOURCE_TIMG TIMG clock selected as LPTIM3 clock 1665 */ 1666 #define __HAL_RCC_GET_LPTIM3_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE) 1667 1668 /** @brief Macro to configure the LPTIM4 clock source. 1669 * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. 1670 * This parameter can be one of the following values: 1671 * @arg RCC_LPTIM4CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM4 clock 1672 * @arg RCC_LPTIM4CLKSOURCE_CLKP CLKP clock selected as LPTIM4 clock 1673 * @arg RCC_LPTIM4CLKSOURCE_IC15 IC15 clock selected as LPTIM4 clock 1674 * @arg RCC_LPTIM4CLKSOURCE_LSE LSE clock selected as LPTIM4 clock 1675 * @arg RCC_LPTIM4CLKSOURCE_LSI LSI clock selected as LPTIM4 clock 1676 * @arg RCC_LPTIM4CLKSOURCE_TIMG TIMG clock selected as LPTIM4 clock 1677 */ 1678 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ 1679 LL_RCC_SetLPTIMClockSource((__LPTIM4_CLKSOURCE__)) 1680 1681 /** @brief Macro to get the LPTIM4 clock source. 1682 * @retval The clock source can be one of the following values: 1683 * @arg RCC_LPTIM4CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM4 clock 1684 * @arg RCC_LPTIM4CLKSOURCE_CLKP CLKP clock selected as LPTIM4 clock 1685 * @arg RCC_LPTIM4CLKSOURCE_IC15 IC15 clock selected as LPTIM4 clock 1686 * @arg RCC_LPTIM4CLKSOURCE_LSE LSE clock selected as LPTIM4 clock 1687 * @arg RCC_LPTIM4CLKSOURCE_LSI LSI clock selected as LPTIM4 clock 1688 * @arg RCC_LPTIM4CLKSOURCE_TIMG TIMG clock selected as LPTIM4 clock 1689 */ 1690 #define __HAL_RCC_GET_LPTIM4_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM4_CLKSOURCE) 1691 1692 /** @brief Macro to configure the LPTIM5 clock source. 1693 * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. 1694 * This parameter can be one of the following values: 1695 * @arg RCC_LPTIM5CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM5 clock 1696 * @arg RCC_LPTIM5CLKSOURCE_CLKP CLKP clock selected as LPTIM5 clock 1697 * @arg RCC_LPTIM5CLKSOURCE_IC15 IC15 clock selected as LPTIM5 clock 1698 * @arg RCC_LPTIM5CLKSOURCE_LSE LSE clock selected as LPTIM5 clock 1699 * @arg RCC_LPTIM5CLKSOURCE_LSI LSI clock selected as LPTIM5 clock 1700 * @arg RCC_LPTIM5CLKSOURCE_TIMG TIMG clock selected as LPTIM5 clock 1701 */ 1702 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ 1703 LL_RCC_SetLPTIMClockSource((__LPTIM5_CLKSOURCE__)) 1704 1705 /** @brief Macro to get the LPTIM5 clock source. 1706 * @retval The clock source can be one of the following values: 1707 * @arg RCC_LPTIM5CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM5 clock 1708 * @arg RCC_LPTIM5CLKSOURCE_CLKP CLKP clock selected as LPTIM5 clock 1709 * @arg RCC_LPTIM5CLKSOURCE_IC15 IC15 clock selected as LPTIM5 clock 1710 * @arg RCC_LPTIM5CLKSOURCE_LSE LSE clock selected as LPTIM5 clock 1711 * @arg RCC_LPTIM5CLKSOURCE_LSI LSI clock selected as LPTIM5 clock 1712 * @arg RCC_LPTIM5CLKSOURCE_TIMG TIMG clock selected as LPTIM5 clock 1713 */ 1714 #define __HAL_RCC_GET_LPTIM5_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM5_CLKSOURCE) 1715 1716 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1717 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1718 * This parameter can be one of the following values: 1719 * @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock 1720 * @arg RCC_LPUART1CLKSOURCE_CLKP CLKP selected as LPUART1 clock 1721 * @arg RCC_LPUART1CLKSOURCE_IC9 IC9 selected as LPUART1 clock 1722 * @arg RCC_LPUART1CLKSOURCE_IC14 IC14 selected as LPUART1 clock 1723 * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1724 * @arg RCC_LPUART1CLKSOURCE_MSI MSI selected as LPUART1 clock 1725 * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1726 */ 1727 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1728 LL_RCC_SetLPUARTClockSource((__LPUART1_CLKSOURCE__)) 1729 1730 /** @brief Macro to get the LPUART1 clock source. 1731 * @retval The clock source can be one of the following values: 1732 * @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock 1733 * @arg RCC_LPUART1CLKSOURCE_CLKP CLKP selected as LPUART1 clock 1734 * @arg RCC_LPUART1CLKSOURCE_IC9 IC9 selected as LPUART1 clock 1735 * @arg RCC_LPUART1CLKSOURCE_IC14 IC14 selected as LPUART1 clock 1736 * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1737 * @arg RCC_LPUART1CLKSOURCE_MSI MSI selected as LPUART1 clock 1738 * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1739 */ 1740 #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) 1741 1742 /** @brief Macro to configure the LTDC clock (LTDCCLK). 1743 * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. 1744 * This parameter can be one of the following values: 1745 * @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock 1746 * @arg RCC_LTDCCLKSOURCE_CLKP CLKP selected as LTDC clock 1747 * @arg RCC_LTDCCLKSOURCE_IC16 IC14 selected as LTDC clock 1748 * @arg RCC_LTDCCLKSOURCE_HSI HSI selected as LTDC clock 1749 */ 1750 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 1751 LL_RCC_SetLTDCClockSource((__LTDC_CLKSOURCE__)) 1752 1753 /** @brief Macro to get the LTDC clock source. 1754 * @retval The clock source can be one of the following values: 1755 * @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock 1756 * @arg RCC_LTDCCLKSOURCE_CLKP CLKP selected as LTDC clock 1757 * @arg RCC_LTDCCLKSOURCE_IC16 IC14 selected as LTDC clock 1758 * @arg RCC_LTDCCLKSOURCE_HSI HSI selected as LTDC clock 1759 */ 1760 #define __HAL_RCC_GET_LTDC_SOURCE() LL_RCC_GetLTDCClockSource(LL_RCC_LTDC_CLKSOURCE) 1761 1762 /** @brief Macro to configure the MDF1 clock 1763 * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. 1764 * This parameter can be one of the following values: 1765 * @arg RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock 1766 * @arg RCC_MDF1CLKSOURCE_CLKP CLKP selected as MDF1 clock 1767 * @arg RCC_MDF1CLKSOURCE_IC7 IC7 selected as MDF1 clock 1768 * @arg RCC_MDF1CLKSOURCE_IC8 IC8 selected as MDF1 clock 1769 * @arg RCC_MDF1CLKSOURCE_MSI MSI selected as MDF1 clock 1770 * @arg RCC_MDF1CLKSOURCE_HSI HSI selected as MDF1 clock 1771 * @arg RCC_MDF1CLKSOURCE_PIN External I2S_CKIN selected as MDF1 clock 1772 * @arg RCC_MDF1CLKSOURCE_TIMG TIMG selected as MDF1 clock 1773 */ 1774 #define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ 1775 LL_RCC_SetMDFClockSource((__MDF1_CLKSOURCE__)) 1776 1777 /** @brief Macro to get the MDF1 clock source. 1778 * @retval The clock source can be one of the following values: 1779 * @arg RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock 1780 * @arg RCC_MDF1CLKSOURCE_CLKP CLKP selected as MDF1 clock 1781 * @arg RCC_MDF1CLKSOURCE_IC7 IC7 selected as MDF1 clock 1782 * @arg RCC_MDF1CLKSOURCE_IC8 IC8 selected as MDF1 clock 1783 * @arg RCC_MDF1CLKSOURCE_MSI MSI selected as MDF1 clock 1784 * @arg RCC_MDF1CLKSOURCE_HSI HSI selected as MDF1 clock 1785 * @arg RCC_MDF1CLKSOURCE_PIN External I2S_CKIN selected as MDF1 clock 1786 * @arg RCC_MDF1CLKSOURCE_TIMG TIMG selected as MDF1 clock 1787 */ 1788 #define __HAL_RCC_GET_MDF1_SOURCE() LL_RCC_GetMDFClockSource(LL_RCC_MDF1_CLKSOURCE) 1789 1790 /** 1791 * @brief Macro to configure the PSSI clock source. 1792 * @param __PSSI_CLKSOURCE__ defines the PSSI clock source. 1793 * This parameter can be one of the following values: 1794 * @arg RCC_PSSICLKSOURCE_HCLK HCLK selected as PSSI clock 1795 * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock CLKP selected as PSSI clock 1796 * @arg RCC_PSSICLKSOURCE_IC20 IC20 selected as PSSI clock 1797 * @arg RCC_PSSICLKSOURCE_HSI HSI selected as PSSI clock 1798 * @retval None 1799 */ 1800 #define __HAL_RCC_PSSI_CONFIG(__PSSI_CLKSOURCE__) \ 1801 LL_RCC_SetPSSIClockSource((__PSSI_CLKSOURCE__)) 1802 1803 /** @brief Macro to get the PSSI clock source. 1804 * @retval The clock source can be one of the following values: 1805 * @arg RCC_PSSICLKSOURCE_HCLK HCLK selected as PSSI clock 1806 * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock CLKP selected as PSSI clock 1807 * @arg RCC_PSSICLKSOURCE_IC20 IC20 selected as PSSI clock 1808 * @arg RCC_PSSICLKSOURCE_HSI HSI selected as PSSI clock 1809 */ 1810 #define __HAL_RCC_GET_PSSI_SOURCE() LL_RCC_GetPSSIClockSource(LL_RCC_PSSI_CLKSOURCE) 1811 1812 /** 1813 * @brief Macro to configure the SAI1 clock source. 1814 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. 1815 * This parameter can be one of the following values: 1816 * @arg RCC_SAI1CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI1 clock 1817 * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI1 clock 1818 * @arg RCC_SAI1CLKSOURCE_IC7 IC7 selected as SAI1 clock 1819 * @arg RCC_SAI1CLKSOURCE_IC8 IC8 selected as SAI1 clock 1820 * @arg RCC_SAI1CLKSOURCE_MSI MSI selected as SAI1 clock 1821 * @arg RCC_SAI1CLKSOURCE_HSI HSI selected as SAI1 clock 1822 * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock 1823 * @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock 1824 * @retval None 1825 */ 1826 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \ 1827 LL_RCC_SetSAIClockSource((__SAI1_CLKSOURCE__)) 1828 1829 /** @brief Macro to get the SAI1 clock source. 1830 * @retval The clock source can be one of the following values: 1831 * @arg RCC_SAI1CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI1 clock 1832 * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI1 clock 1833 * @arg RCC_SAI1CLKSOURCE_IC7 IC7 selected as SAI1 clock 1834 * @arg RCC_SAI1CLKSOURCE_IC8 IC8 selected as SAI1 clock 1835 * @arg RCC_SAI1CLKSOURCE_MSI MSI selected as SAI1 clock 1836 * @arg RCC_SAI1CLKSOURCE_HSI HSI selected as SAI1 clock 1837 * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock 1838 * @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock 1839 */ 1840 #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) 1841 1842 /** 1843 * @brief Macro to configure the SAI2 clock source. 1844 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. 1845 * This parameter can be one of the following values: 1846 * @arg RCC_SAI2CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI2 clock 1847 * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI2 clock 1848 * @arg RCC_SAI2CLKSOURCE_IC7 IC7 selected as SAI2 clock 1849 * @arg RCC_SAI2CLKSOURCE_IC8 IC8 selected as SAI2 clock 1850 * @arg RCC_SAI2CLKSOURCE_MSI MSI selected as SAI2 clock 1851 * @arg RCC_SAI2CLKSOURCE_HSI HSI selected as SAI2 clock 1852 * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock 1853 * @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock 1854 * @retval None 1855 */ 1856 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) \ 1857 LL_RCC_SetSAIClockSource((__SAI2_CLKSOURCE__)) 1858 1859 /** @brief Macro to get the SAI2 clock source. 1860 * @retval The clock source can be one of the following values: 1861 * @arg RCC_SAI2CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI2 clock 1862 * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI2 clock 1863 * @arg RCC_SAI2CLKSOURCE_IC7 IC7 selected as SAI2 clock 1864 * @arg RCC_SAI2CLKSOURCE_IC8 IC8 selected as SAI2 clock 1865 * @arg RCC_SAI2CLKSOURCE_MSI MSI selected as SAI2 clock 1866 * @arg RCC_SAI2CLKSOURCE_HSI HSI selected as SAI2 clock 1867 * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock 1868 * @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock 1869 */ 1870 #define __HAL_RCC_GET_SAI2_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI2_CLKSOURCE) 1871 1872 /** @brief Macro to configure the SDMMC1 kernel clock source. 1873 * @param __SDMMC1_CLKSOURCE__ specifies clock source for SDMMC1 1874 * This parameter can be one of the following values: 1875 * @arg RCC_SDMMC1CLKSOURCE_HCLK HCLK Clock selected as SDMMC1 kernel clock 1876 * @arg RCC_SDMMC1CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC1 kernel clock 1877 * @arg RCC_SDMMC1CLKSOURCE_IC4 IC4 selected as SDMMC1 kernel clock 1878 * @arg RCC_SDMMC1CLKSOURCE_IC5 IC5 selected as SDMMC1 kernel clock 1879 */ 1880 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1881 LL_RCC_SetSDMMCClockSource((__SDMMC1_CLKSOURCE__)) 1882 1883 /** @brief Macro to get the SDMMC1 kernel clock source. 1884 * @retval The clock source can be one of the following values: 1885 * @arg RCC_SDMMC1CLKSOURCE_HCLK HCLK Clock selected as SDMMC1 kernel clock 1886 * @arg RCC_SDMMC1CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC1 kernel clock 1887 * @arg RCC_SDMMC1CLKSOURCE_IC4 IC4 selected as SDMMC1 kernel clock 1888 * @arg RCC_SDMMC1CLKSOURCE_IC5 IC5 selected as SDMMC1 kernel clock 1889 */ 1890 #define __HAL_RCC_GET_SDMMC1_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC1_CLKSOURCE) 1891 1892 /** @brief Macro to configure the SDMMC2 kernel clock source. 1893 * @param __SDMMC2_CLKSOURCE__ specifies clock source for SDMMC2 1894 * This parameter can be one of the following values: 1895 * @arg RCC_SDMMC2CLKSOURCE_HCLK HCLK Clock selected as SDMMC2 kernel clock 1896 * @arg RCC_SDMMC2CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC2 kernel clock 1897 * @arg RCC_SDMMC2CLKSOURCE_IC4 IC4 selected as SDMMC2 kernel clock 1898 * @arg RCC_SDMMC2CLKSOURCE_IC5 IC5 selected as SDMMC2 kernel clock 1899 */ 1900 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ 1901 LL_RCC_SetSDMMCClockSource((__SDMMC2_CLKSOURCE__)) 1902 1903 /** @brief Macro to get the SDMMC2 kernel clock source. 1904 * @retval The clock source can be one of the following values: 1905 * @arg RCC_SDMMC2CLKSOURCE_HCLK HCLK Clock selected as SDMMC2 kernel clock 1906 * @arg RCC_SDMMC2CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC2 kernel clock 1907 * @arg RCC_SDMMC2CLKSOURCE_IC4 IC4 selected as SDMMC2 kernel clock 1908 * @arg RCC_SDMMC2CLKSOURCE_IC5 IC5 selected as SDMMC2 kernel clock 1909 */ 1910 #define __HAL_RCC_GET_SDMMC2_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC2_CLKSOURCE) 1911 1912 /** 1913 * @brief Macro to Configure the SPDIFRX1 clock source. 1914 * @param __SPDIFRX_CLKSOURCE__ defines the SPDIFRX1 clock source. 1915 * This parameter can be one of the following values: 1916 * @arg RCC_SPDIFRX1CLKSOURCE_PCLK1 PCLK1 Clock selected as SPDIFRX1 clock 1917 * @arg RCC_SPDIFRX1CLKSOURCE_CLKP Peripheral clock CLKP selected as SPDIFRX1 clock 1918 * @arg RCC_SPDIFRX1CLKSOURCE_IC7 IC7 selected as SPDIFRX1 clock 1919 * @arg RCC_SPDIFRX1CLKSOURCE_IC8 IC8 selected as SPDIFRX1 clock 1920 * @arg RCC_SPDIFRX1CLKSOURCE_MSI MSI selected as SPDIFRX1 clock 1921 * @arg RCC_SPDIFRX1CLKSOURCE_HSI HSI selected as SPDIFRX1 clock 1922 * @arg RCC_SPDIFRX1CLKSOURCE_PIN External I2S_CKIN selected as SPDIFRX1 clock 1923 * @retval None 1924 */ 1925 #define __HAL_RCC_SPDIFRX1_CONFIG(__SPDIFRX_CLKSOURCE__ ) \ 1926 LL_RCC_SetSPDIFRXClockSource((__SPDIFRX_CLKSOURCE__)) 1927 1928 /** 1929 * @brief Macro to get the SPDIFRX1 clock source. 1930 * @retval The clock source can be one of the following values: 1931 * @arg RCC_SPDIFRX1CLKSOURCE_PCLK1 PCLK1 Clock selected as SPDIFRX1 clock 1932 * @arg RCC_SPDIFRX1CLKSOURCE_CLKP Peripheral clock CLKP selected as SPDIFRX1 clock 1933 * @arg RCC_SPDIFRX1CLKSOURCE_IC7 IC7 selected as SPDIFRX1 clock 1934 * @arg RCC_SPDIFRX1CLKSOURCE_IC8 IC8 selected as SPDIFRX1 clock 1935 * @arg RCC_SPDIFRX1CLKSOURCE_MSI MSI selected as SPDIFRX1 clock 1936 * @arg RCC_SPDIFRX1CLKSOURCE_HSI HSI selected as SPDIFRX1 clock 1937 * @arg RCC_SPDIFRX1CLKSOURCE_PIN External I2S_CKIN selected as SPDIFRX1 clock 1938 * @retval None 1939 */ 1940 #define __HAL_RCC_GET_SPDIFRX1_SOURCE() LL_RCC_GetSPDIFRXClockSource(LL_RCC_SPDIFRX1_CLKSOURCE) 1941 1942 /** 1943 * @brief Macro to configure the SPI1 clock source. 1944 * @param __SPI1_CLKSOURCE__ defines the SPI1 clock source. 1945 * This parameter can be one of the following values: 1946 * @arg RCC_SPI1CLKSOURCE_PCLK2 PCLK2 selected as SPI1 clock 1947 * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI1 clock 1948 * @arg RCC_SPI1CLKSOURCE_IC8 IC8 selected as SPI1 clock 1949 * @arg RCC_SPI1CLKSOURCE_IC9 IC9 selected as SPI1 clock 1950 * @arg RCC_SPI1CLKSOURCE_MSI MSI selected as SPI1 clock 1951 * @arg RCC_SPI1CLKSOURCE_HSI HSI selected as SPI1 clock 1952 * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock 1953 * @retval None 1954 */ 1955 #define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__ ) \ 1956 LL_RCC_SetSPIClockSource((__SPI1_CLKSOURCE__)) 1957 1958 /** @brief Macro to get the SPI1 clock source. 1959 * @retval The clock source can be one of the following values: 1960 * @arg RCC_SPI1CLKSOURCE_PCLK2 PCLK2 selected as SPI1 clock 1961 * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI1 clock 1962 * @arg RCC_SPI1CLKSOURCE_IC8 IC8 selected as SPI1 clock 1963 * @arg RCC_SPI1CLKSOURCE_IC9 IC9 selected as SPI1 clock 1964 * @arg RCC_SPI1CLKSOURCE_MSI MSI selected as SPI1 clock 1965 * @arg RCC_SPI1CLKSOURCE_HSI HSI selected as SPI1 clock 1966 * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock 1967 */ 1968 #define __HAL_RCC_GET_SPI1_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI1_CLKSOURCE) 1969 1970 /** 1971 * @brief Macro to configure the SPI2 clock source. 1972 * @param __SPI2_CLKSOURCE__ defines the SPI2 clock source. 1973 * This parameter can be one of the following values: 1974 * @arg RCC_SPI2CLKSOURCE_PCLK1 PCLK1 selected as SPI2 clock 1975 * @arg RCC_SPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI2 clock 1976 * @arg RCC_SPI2CLKSOURCE_IC8 IC8 selected as SPI2 clock 1977 * @arg RCC_SPI2CLKSOURCE_IC9 IC9 selected as SPI2 clock 1978 * @arg RCC_SPI2CLKSOURCE_MSI MSI selected as SPI2 clock 1979 * @arg RCC_SPI2CLKSOURCE_HSI HSI selected as SPI2 clock 1980 * @arg RCC_SPI2CLKSOURCE_PIN External I2S_CKIN selected as SPI2 clock 1981 * @retval None 1982 */ 1983 #define __HAL_RCC_SPI2_CONFIG(__SPI2_CLKSOURCE__ ) \ 1984 LL_RCC_SetSPIClockSource((__SPI2_CLKSOURCE__)) 1985 1986 /** @brief Macro to get the SPI2 clock source. 1987 * @retval The clock source can be one of the following values: 1988 * @arg RCC_SPI2CLKSOURCE_PCLK1 PCLK1 selected as SPI2 clock 1989 * @arg RCC_SPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI2 clock 1990 * @arg RCC_SPI2CLKSOURCE_IC8 IC8 selected as SPI2 clock 1991 * @arg RCC_SPI2CLKSOURCE_IC9 IC9 selected as SPI2 clock 1992 * @arg RCC_SPI2CLKSOURCE_MSI MSI selected as SPI2 clock 1993 * @arg RCC_SPI2CLKSOURCE_HSI HSI selected as SPI2 clock 1994 * @arg RCC_SPI2CLKSOURCE_PIN External I2S_CKIN selected as SPI2 clock 1995 */ 1996 #define __HAL_RCC_GET_SPI2_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI2_CLKSOURCE) 1997 1998 /** 1999 * @brief Macro to configure the SPI3 clock source. 2000 * @param __SPI3_CLKSOURCE__ defines the SPI3 clock source. 2001 * This parameter can be one of the following values: 2002 * @arg RCC_SPI3CLKSOURCE_PCLK1 PCLK1 selected as SPI3 clock 2003 * @arg RCC_SPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI3 clock 2004 * @arg RCC_SPI3CLKSOURCE_IC8 IC8 selected as SPI3 clock 2005 * @arg RCC_SPI3CLKSOURCE_IC9 IC9 selected as SPI3 clock 2006 * @arg RCC_SPI3CLKSOURCE_MSI MSI selected as SPI3 clock 2007 * @arg RCC_SPI3CLKSOURCE_HSI HSI selected as SPI3 clock 2008 * @arg RCC_SPI3CLKSOURCE_PIN External I2S_CKIN selected as SPI3 clock 2009 * @retval None 2010 */ 2011 #define __HAL_RCC_SPI3_CONFIG(__SPI3_CLKSOURCE__ ) \ 2012 LL_RCC_SetSPIClockSource((__SPI3_CLKSOURCE__)) 2013 2014 /** @brief Macro to get the SPI3 clock source. 2015 * @retval The clock source can be one of the following values: 2016 * @arg RCC_SPI3CLKSOURCE_PCLK1 PCLK1 selected as SPI3 clock 2017 * @arg RCC_SPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI3 clock 2018 * @arg RCC_SPI3CLKSOURCE_IC8 IC8 selected as SPI3 clock 2019 * @arg RCC_SPI3CLKSOURCE_IC9 IC9 selected as SPI3 clock 2020 * @arg RCC_SPI3CLKSOURCE_MSI MSI selected as SPI3 clock 2021 * @arg RCC_SPI3CLKSOURCE_HSI HSI selected as SPI3 clock 2022 * @arg RCC_SPI3CLKSOURCE_PIN External I2S_CKIN selected as SPI3 clock 2023 */ 2024 #define __HAL_RCC_GET_SPI3_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI3_CLKSOURCE) 2025 2026 /** 2027 * @brief Macro to configure the SPI4 clock source. 2028 * @param __SPI4_CLKSOURCE__ defines the SPI4 clock source. 2029 * This parameter can be one of the following values: 2030 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 selected as SPI4 clock 2031 * @arg RCC_SPI4CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI4 clock 2032 * @arg RCC_SPI4CLKSOURCE_IC8 IC8 selected as SPI4 clock 2033 * @arg RCC_SPI4CLKSOURCE_IC9 IC9 selected as SPI4 clock 2034 * @arg RCC_SPI4CLKSOURCE_MSI MSI selected as SPI4 clock 2035 * @arg RCC_SPI4CLKSOURCE_HSI HSI selected as SPI4 clock 2036 * @arg RCC_SPI4CLKSOURCE_PIN External I2S_CKIN selected as SPI4 clock 2037 * @retval None 2038 */ 2039 #define __HAL_RCC_SPI4_CONFIG(__SPI4_CLKSOURCE__ ) \ 2040 LL_RCC_SetSPIClockSource((__SPI4_CLKSOURCE__)) 2041 2042 /** @brief Macro to get the SPI4 clock source. 2043 * @retval The clock source can be one of the following values: 2044 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 selected as SPI4 clock 2045 * @arg RCC_SPI4CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI4 clock 2046 * @arg RCC_SPI4CLKSOURCE_IC8 IC8 selected as SPI4 clock 2047 * @arg RCC_SPI4CLKSOURCE_IC9 IC9 selected as SPI4 clock 2048 * @arg RCC_SPI4CLKSOURCE_MSI MSI selected as SPI4 clock 2049 * @arg RCC_SPI4CLKSOURCE_HSI HSI selected as SPI4 clock 2050 * @arg RCC_SPI4CLKSOURCE_PIN External I2S_CKIN selected as SPI4 clock 2051 */ 2052 #define __HAL_RCC_GET_SPI4_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI4_CLKSOURCE) 2053 2054 /** 2055 * @brief Macro to configure the SPI5 clock source. 2056 * @param __SPI5_CLKSOURCE__ defines the SPI5 clock source. 2057 * This parameter can be one of the following values: 2058 * @arg RCC_SPI5CLKSOURCE_PCLK2 PCLK2 selected as SPI5 clock 2059 * @arg RCC_SPI5CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI5 clock 2060 * @arg RCC_SPI5CLKSOURCE_IC8 IC8 selected as SPI5 clock 2061 * @arg RCC_SPI5CLKSOURCE_IC9 IC9 selected as SPI5 clock 2062 * @arg RCC_SPI5CLKSOURCE_MSI MSI selected as SPI5 clock 2063 * @arg RCC_SPI5CLKSOURCE_HSI HSI selected as SPI5 clock 2064 * @arg RCC_SPI5CLKSOURCE_PIN External I2S_CKIN selected as SPI5 clock 2065 * @retval None 2066 */ 2067 #define __HAL_RCC_SPI5_CONFIG(__SPI5_CLKSOURCE__ ) \ 2068 LL_RCC_SetSPIClockSource((__SPI5_CLKSOURCE__)) 2069 2070 /** @brief Macro to get the SPI5 clock source. 2071 * @retval The clock source can be one of the following values: 2072 * @arg RCC_SPI5CLKSOURCE_PCLK2 PCLK2 selected as SPI5 clock 2073 * @arg RCC_SPI5CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI5 clock 2074 * @arg RCC_SPI5CLKSOURCE_IC8 IC8 selected as SPI5 clock 2075 * @arg RCC_SPI5CLKSOURCE_IC9 IC9 selected as SPI5 clock 2076 * @arg RCC_SPI5CLKSOURCE_MSI MSI selected as SPI5 clock 2077 * @arg RCC_SPI5CLKSOURCE_HSI HSI selected as SPI5 clock 2078 * @arg RCC_SPI5CLKSOURCE_PIN External I2S_CKIN selected as SPI5 clock 2079 */ 2080 #define __HAL_RCC_GET_SPI5_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI5_CLKSOURCE) 2081 2082 /** 2083 * @brief Macro to configure the SPI6 clock source. 2084 * @param __SPI6_CLKSOURCE__ defines the SPI6 clock source. 2085 * This parameter can be one of the following values: 2086 * @arg RCC_SPI6CLKSOURCE_PCLK4 PCLK4 selected as SPI6 clock 2087 * @arg RCC_SPI6CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI6 clock 2088 * @arg RCC_SPI6CLKSOURCE_IC8 IC8 selected as SPI6 clock 2089 * @arg RCC_SPI6CLKSOURCE_IC9 IC9 selected as SPI6 clock 2090 * @arg RCC_SPI6CLKSOURCE_MSI MSI selected as SPI6 clock 2091 * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock 2092 * @arg RCC_SPI6CLKSOURCE_PIN External I2S_CKIN selected as SPI6 clock 2093 * @retval None 2094 */ 2095 #define __HAL_RCC_SPI6_CONFIG(__SPI6_CLKSOURCE__ ) \ 2096 LL_RCC_SetSPIClockSource((__SPI6_CLKSOURCE__)) 2097 2098 /** @brief Macro to get the SPI6 clock source. 2099 * @retval The clock source can be one of the following values: 2100 * @arg RCC_SPI6CLKSOURCE_PCLK4 PCLK4 selected as SPI6 clock 2101 * @arg RCC_SPI6CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI6 clock 2102 * @arg RCC_SPI6CLKSOURCE_IC8 IC8 selected as SPI6 clock 2103 * @arg RCC_SPI6CLKSOURCE_IC9 IC9 selected as SPI6 clock 2104 * @arg RCC_SPI6CLKSOURCE_MSI MSI selected as SPI6 clock 2105 * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock 2106 * @arg RCC_SPI6CLKSOURCE_PIN External I2S_CKIN selected as SPI6 clock 2107 */ 2108 #define __HAL_RCC_GET_SPI6_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI6_CLKSOURCE) 2109 2110 /** @brief Macro to configure the USART1 clock source. 2111 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 2112 * This parameter can be one of the following values: 2113 * @arg RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2114 * @arg RCC_USART1CLKSOURCE_CLKP Peripheral clock CKLP selected as USART1 clock 2115 * @arg RCC_USART1CLKSOURCE_IC9 IC9 selected as USART1 clock 2116 * @arg RCC_USART1CLKSOURCE_IC14 IC14 selected as USART1 clock 2117 * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2118 * @arg RCC_USART1CLKSOURCE_MSI MSI selected as USART1 clock 2119 * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2120 */ 2121 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 2122 LL_RCC_SetUSARTClockSource((__USART1_CLKSOURCE__)) 2123 2124 /** @brief Macro to get the USART1 clock source. 2125 * @retval The clock source can be one of the following values: 2126 * @arg RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2127 * @arg RCC_USART1CLKSOURCE_CLKP Peripheral clock CKLP selected as USART1 clock 2128 * @arg RCC_USART1CLKSOURCE_IC9 IC9 selected as USART1 clock 2129 * @arg RCC_USART1CLKSOURCE_IC14 IC14 selected as USART1 clock 2130 * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2131 * @arg RCC_USART1CLKSOURCE_MSI MSI selected as USART1 clock 2132 * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2133 */ 2134 #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) 2135 2136 /** @brief Macro to configure the USART2 clock source. 2137 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 2138 * This parameter can be one of the following values: 2139 * @arg RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 2140 * @arg RCC_USART2CLKSOURCE_CLKP Peripheral clock CKLP selected as USART2 clock 2141 * @arg RCC_USART2CLKSOURCE_IC9 IC9 selected as USART2 clock 2142 * @arg RCC_USART2CLKSOURCE_IC14 IC14 selected as USART2 clock 2143 * @arg RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2144 * @arg RCC_USART2CLKSOURCE_MSI MSI selected as USART2 clock 2145 * @arg RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2146 */ 2147 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 2148 LL_RCC_SetUSARTClockSource((__USART2_CLKSOURCE__)) 2149 2150 /** @brief Macro to get the USART2 clock source. 2151 * @retval The clock source can be one of the following values: 2152 * @arg RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 2153 * @arg RCC_USART2CLKSOURCE_CLKP Peripheral clock CKLP selected as USART2 clock 2154 * @arg RCC_USART2CLKSOURCE_IC9 IC9 selected as USART2 clock 2155 * @arg RCC_USART2CLKSOURCE_IC14 IC14 selected as USART2 clock 2156 * @arg RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2157 * @arg RCC_USART2CLKSOURCE_MSI MSI selected as USART2 clock 2158 * @arg RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2159 */ 2160 #define __HAL_RCC_GET_USART2_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE) 2161 2162 /** @brief Macro to configure the USART3 clock source. 2163 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 2164 * This parameter can be one of the following values: 2165 * @arg RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 2166 * @arg RCC_USART3CLKSOURCE_CLKP Peripheral clock CKLP selected as USART3 clock 2167 * @arg RCC_USART3CLKSOURCE_IC9 IC9 selected as USART3 clock 2168 * @arg RCC_USART3CLKSOURCE_IC14 IC14 selected as USART3 clock 2169 * @arg RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2170 * @arg RCC_USART3CLKSOURCE_MSI MSI selected as USART3 clock 2171 * @arg RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2172 */ 2173 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 2174 LL_RCC_SetUSARTClockSource((__USART3_CLKSOURCE__)) 2175 2176 /** @brief Macro to get the USART3 clock source. 2177 * @retval The clock source can be one of the following values: 2178 * @arg RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 2179 * @arg RCC_USART3CLKSOURCE_CLKP Peripheral clock CKLP selected as USART3 clock 2180 * @arg RCC_USART3CLKSOURCE_IC9 IC9 selected as USART3 clock 2181 * @arg RCC_USART3CLKSOURCE_IC14 IC14 selected as USART3 clock 2182 * @arg RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2183 * @arg RCC_USART3CLKSOURCE_MSI MSI selected as USART3 clock 2184 * @arg RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2185 */ 2186 #define __HAL_RCC_GET_USART3_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART3_CLKSOURCE) 2187 2188 /** @brief Macro to configure the UART4 clock source. 2189 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 2190 * This parameter can be one of the following values: 2191 * @arg RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2192 * @arg RCC_UART4CLKSOURCE_CLKP Peripheral clock CKLP selected as UART4 clock 2193 * @arg RCC_UART4CLKSOURCE_IC9 IC9 selected as UART4 clock 2194 * @arg RCC_UART4CLKSOURCE_IC14 IC14 selected as UART4 clock 2195 * @arg RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2196 * @arg RCC_UART4CLKSOURCE_MSI MSI selected as UART4 clock 2197 * @arg RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2198 */ 2199 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 2200 LL_RCC_SetUSARTClockSource((__UART4_CLKSOURCE__)) 2201 2202 /** @brief Macro to get the UART4 clock source. 2203 * @retval The clock source can be one of the following values: 2204 * @arg RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2205 * @arg RCC_UART4CLKSOURCE_CLKP Peripheral clock CKLP selected as UART4 clock 2206 * @arg RCC_UART4CLKSOURCE_IC9 IC9 selected as UART4 clock 2207 * @arg RCC_UART4CLKSOURCE_IC14 IC14 selected as UART4 clock 2208 * @arg RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2209 * @arg RCC_UART4CLKSOURCE_MSI MSI selected as UART4 clock 2210 * @arg RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2211 */ 2212 #define __HAL_RCC_GET_UART4_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART4_CLKSOURCE) 2213 2214 /** @brief Macro to configure the UART5 clock source. 2215 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 2216 * This parameter can be one of the following values: 2217 * @arg RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2218 * @arg RCC_UART5CLKSOURCE_CLKP Peripheral clock CKLP selected as UART5 clock 2219 * @arg RCC_UART5CLKSOURCE_IC9 IC9 selected as UART5 clock 2220 * @arg RCC_UART5CLKSOURCE_IC14 IC14 selected as UART5 clock 2221 * @arg RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2222 * @arg RCC_UART5CLKSOURCE_MSI MSI selected as UART5 clock 2223 * @arg RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2224 */ 2225 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 2226 LL_RCC_SetUSARTClockSource((__UART5_CLKSOURCE__)) 2227 2228 /** @brief Macro to get the UART5 clock source. 2229 * @retval The clock source can be one of the following values: 2230 * @arg RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2231 * @arg RCC_UART5CLKSOURCE_CLKP Peripheral clock CKLP selected as UART5 clock 2232 * @arg RCC_UART5CLKSOURCE_IC9 IC9 selected as UART5 clock 2233 * @arg RCC_UART5CLKSOURCE_IC14 IC14 selected as UART5 clock 2234 * @arg RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2235 * @arg RCC_UART5CLKSOURCE_MSI MSI selected as UART5 clock 2236 * @arg RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2237 */ 2238 #define __HAL_RCC_GET_UART5_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART5_CLKSOURCE) 2239 2240 /** @brief Macro to configure the USART6 clock source. 2241 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 2242 * This parameter can be one of the following values: 2243 * @arg RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock 2244 * @arg RCC_USART6CLKSOURCE_CLKP Peripheral clock CKLP selected as USART6 clock 2245 * @arg RCC_USART6CLKSOURCE_IC9 IC9 selected as USART6 clock 2246 * @arg RCC_USART6CLKSOURCE_IC14 IC14 selected as USART6 clock 2247 * @arg RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2248 * @arg RCC_USART6CLKSOURCE_MSI MSI selected as USART6 clock 2249 * @arg RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2250 */ 2251 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 2252 LL_RCC_SetUSARTClockSource((__USART6_CLKSOURCE__)) 2253 2254 /** @brief Macro to get the USART6 clock source. 2255 * @retval The clock source can be one of the following values: 2256 * @arg RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock 2257 * @arg RCC_USART6CLKSOURCE_CLKP Peripheral clock CKLP selected as USART6 clock 2258 * @arg RCC_USART6CLKSOURCE_IC9 IC9 selected as USART6 clock 2259 * @arg RCC_USART6CLKSOURCE_IC14 IC14 selected as USART6 clock 2260 * @arg RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2261 * @arg RCC_USART6CLKSOURCE_MSI MSI selected as USART6 clock 2262 * @arg RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2263 */ 2264 #define __HAL_RCC_GET_USART6_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART6_CLKSOURCE) 2265 2266 /** @brief Macro to configure the UART7 clock source. 2267 * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. 2268 * This parameter can be one of the following values: 2269 * @arg RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2270 * @arg RCC_UART7CLKSOURCE_CLKP Peripheral clock CKLP selected as UART7 clock 2271 * @arg RCC_UART7CLKSOURCE_IC9 IC9 selected as UART7 clock 2272 * @arg RCC_UART7CLKSOURCE_IC14 IC14 selected as UART7 clock 2273 * @arg RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2274 * @arg RCC_UART7CLKSOURCE_MSI MSI selected as UART7 clock 2275 * @arg RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2276 */ 2277 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ 2278 LL_RCC_SetUSARTClockSource((__UART7_CLKSOURCE__)) 2279 2280 /** @brief Macro to get the UART7 clock source. 2281 * @retval The clock source can be one of the following values: 2282 * @arg RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2283 * @arg RCC_UART7CLKSOURCE_CLKP Peripheral clock CKLP selected as UART7 clock 2284 * @arg RCC_UART7CLKSOURCE_IC9 IC9 selected as UART7 clock 2285 * @arg RCC_UART7CLKSOURCE_IC14 IC14 selected as UART7 clock 2286 * @arg RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2287 * @arg RCC_UART7CLKSOURCE_MSI MSI selected as UART7 clock 2288 * @arg RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2289 */ 2290 #define __HAL_RCC_GET_UART7_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART7_CLKSOURCE) 2291 2292 /** @brief Macro to configure the UART8 clock source. 2293 * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. 2294 * This parameter can be one of the following values: 2295 * @arg RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2296 * @arg RCC_UART8CLKSOURCE_CLKP Peripheral clock CKLP selected as UART8 clock 2297 * @arg RCC_UART8CLKSOURCE_IC9 IC9 selected as UART8 clock 2298 * @arg RCC_UART8CLKSOURCE_IC14 IC14 selected as UART8 clock 2299 * @arg RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2300 * @arg RCC_UART8CLKSOURCE_MSI MSI selected as UART8 clock 2301 * @arg RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2302 */ 2303 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ 2304 LL_RCC_SetUSARTClockSource((__UART8_CLKSOURCE__)) 2305 2306 /** @brief Macro to get the UART8 clock source. 2307 * @retval The clock source can be one of the following values: 2308 * @arg RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2309 * @arg RCC_UART8CLKSOURCE_CLKP Peripheral clock CKLP selected as UART8 clock 2310 * @arg RCC_UART8CLKSOURCE_IC9 IC9 selected as UART8 clock 2311 * @arg RCC_UART8CLKSOURCE_IC14 IC14 selected as UART8 clock 2312 * @arg RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2313 * @arg RCC_UART8CLKSOURCE_MSI MSI selected as UART8 clock 2314 * @arg RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2315 */ 2316 #define __HAL_RCC_GET_UART8_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART8_CLKSOURCE) 2317 2318 /** @brief Macro to configure the UART9 clock source. 2319 * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. 2320 * This parameter can be one of the following values: 2321 * @arg RCC_UART9CLKSOURCE_PCLK2 PCLK2 selected as UART9 clock 2322 * @arg RCC_UART9CLKSOURCE_CLKP Peripheral clock CKLP selected as UART9 clock 2323 * @arg RCC_UART9CLKSOURCE_IC9 IC9 selected as UART9 clock 2324 * @arg RCC_UART9CLKSOURCE_IC14 IC14 selected as UART9 clock 2325 * @arg RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2326 * @arg RCC_UART9CLKSOURCE_MSI MSI selected as UART9 clock 2327 * @arg RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2328 */ 2329 #define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ 2330 LL_RCC_SetUSARTClockSource((__UART9_CLKSOURCE__)) 2331 2332 /** @brief Macro to get the UART9 clock source. 2333 * @retval The clock source can be one of the following values: 2334 * @arg RCC_UART9CLKSOURCE_PCLK2 PCLK2 selected as UART9 clock 2335 * @arg RCC_UART9CLKSOURCE_CLKP Peripheral clock CKLP selected as UART9 clock 2336 * @arg RCC_UART9CLKSOURCE_IC9 IC9 selected as UART9 clock 2337 * @arg RCC_UART9CLKSOURCE_IC14 IC14 selected as UART9 clock 2338 * @arg RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2339 * @arg RCC_UART9CLKSOURCE_MSI MSI selected as UART9 clock 2340 * @arg RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2341 */ 2342 #define __HAL_RCC_GET_UART9_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART9_CLKSOURCE) 2343 2344 /** @brief Macro to configure the USART10 clock source. 2345 * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. 2346 * This parameter can be one of the following values: 2347 * @arg RCC_USART10CLKSOURCE_PCLK2 PCLK2 selected as USART10 clock 2348 * @arg RCC_USART10CLKSOURCE_CLKP Peripheral clock CKLP selected as USART10 clock 2349 * @arg RCC_USART10CLKSOURCE_IC9 IC9 selected as USART10 clock 2350 * @arg RCC_USART10CLKSOURCE_IC14 IC14 selected as USART10 clock 2351 * @arg RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2352 * @arg RCC_USART10CLKSOURCE_MSI MSI selected as USART10 clock 2353 * @arg RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2354 */ 2355 #define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ 2356 LL_RCC_SetUSARTClockSource((__USART10_CLKSOURCE__)) 2357 2358 /** @brief Macro to get the USART10 clock source. 2359 * @retval The clock source can be one of the following values: 2360 * @arg RCC_USART10CLKSOURCE_PCLK2 PCLK2 selected as USART10 clock 2361 * @arg RCC_USART10CLKSOURCE_CLKP Peripheral clock CKLP selected as USART10 clock 2362 * @arg RCC_USART10CLKSOURCE_IC9 IC9 selected as USART10 clock 2363 * @arg RCC_USART10CLKSOURCE_IC14 IC14 selected as USART10 clock 2364 * @arg RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2365 * @arg RCC_USART10CLKSOURCE_MSI MSI selected as USART10 clock 2366 * @arg RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2367 */ 2368 #define __HAL_RCC_GET_USART10_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART10_CLKSOURCE) 2369 2370 /** @brief Macro to configure the XSPI1 clock source. 2371 * 2372 * @param __XSPI1_CLKSOURCE__ specifies the XSPI1 clock source. 2373 * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK selected as XSPI1 clock 2374 * @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock 2375 * @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock 2376 * @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock 2377 */ 2378 #define __HAL_RCC_XSPI1_CONFIG(__XSPI1_CLKSOURCE__) \ 2379 LL_RCC_SetXSPIClockSource((__XSPI1_CLKSOURCE__)) 2380 2381 /** @brief Macro to get the XSPI1 clock source. 2382 * @retval The clock source can be one of the following values: 2383 * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK selected as XSPI1 clock 2384 * @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock 2385 * @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock 2386 * @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock 2387 */ 2388 #define __HAL_RCC_GET_XSPI1_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE) 2389 2390 /** @brief Macro to configure the XSPI2 clock source. 2391 * 2392 * @param __XSPI2_CLKSOURCE__ specifies the XSPI2 clock source. 2393 * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK selected as XSPI2 clock 2394 * @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock 2395 * @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock 2396 * @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock 2397 */ 2398 #define __HAL_RCC_XSPI2_CONFIG(__XSPI2_CLKSOURCE__) \ 2399 LL_RCC_SetXSPIClockSource((__XSPI2_CLKSOURCE__)) 2400 2401 /** @brief Macro to get the XSPI2 clock source. 2402 * @retval The clock source can be one of the following values: 2403 * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK selected as XSPI2 clock 2404 * @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock 2405 * @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock 2406 * @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock 2407 */ 2408 #define __HAL_RCC_GET_XSPI2_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI2_CLKSOURCE) 2409 2410 /** @brief Macro to configure the XSPI3 clock source. 2411 * 2412 * @param __XSPI3_CLKSOURCE__ specifies the XSPI3 clock source. 2413 * @arg RCC_XSPI3CLKSOURCE_HCLK HCLK selected as XSPI3 clock 2414 * @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock 2415 * @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock 2416 * @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock 2417 */ 2418 #define __HAL_RCC_XSPI3_CONFIG(__XSPI3_CLKSOURCE__) \ 2419 LL_RCC_SetXSPIClockSource((__XSPI3_CLKSOURCE__)) 2420 2421 /** @brief Macro to get the XSPI3 clock source. 2422 * @retval The clock source can be one of the following values: 2423 * @arg RCC_XSPI3CLKSOURCE_HCLK HCLK selected as XSPI3 clock 2424 * @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock 2425 * @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock 2426 * @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock 2427 */ 2428 #define __HAL_RCC_GET_XSPI3_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI3_CLKSOURCE) 2429 2430 /** @brief Macro to configure the Timers clocks prescaler 2431 * @param __PRESC__ specifies the Timers clocks prescaler selection 2432 * This parameter can be one of the following values: 2433 * @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1 2434 * @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2 2435 * @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4 2436 * @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8 2437 */ 2438 #define __HAL_RCC_TIMCLKPRESCALER_CONFIG(__PRESC__) LL_RCC_SetTIMPrescaler((__PRESC__)) 2439 2440 /** @brief Macro to get the Timers clocks prescaler. 2441 * @retval Timers clocks prescaler can be one of the following values: 2442 * @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1 2443 * @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2 2444 * @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4 2445 * @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8 2446 */ 2447 #define __HAL_RCC_GET_TIMCLKPRESCALER() LL_RCC_GetTIMPrescaler() 2448 2449 /** @brief Macro to configure the USBPHY1 clock. 2450 * @param __USBPHY1_CLKSOURCE__ specifies the USBPHY1 clock source. 2451 * This parameter can be one of the following values: 2452 * @arg RCC_USBPHY1REFCLKSOURCE_OTGPHY1 USB OTGPHY1 kernel clock selected as USBPHY1 clock 2453 * @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY1 clock 2454 * @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock 2455 */ 2456 #define __HAL_RCC_USBPHY1_CONFIG(__USBPHY1_CLKSOURCE__) \ 2457 do \ 2458 { \ 2459 LL_RCC_SetOTGPHYCKREFClockSource((__USBPHY1_CLKSOURCE__) & 0x7FFFFFFFUL); \ 2460 if(((__USBPHY1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ 2461 else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ 2462 } while (0) 2463 2464 2465 /** @brief Macro to get the USBPHY1 clock source. 2466 * @retval The clock source can be one of the following values: 2467 * @arg RCC_USBPHY1REFCLKSOURCE_OTGPHY1 USB OTGPHY1 kernel clock selected as USBPHY1 clock 2468 * @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY1 clock 2469 * @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock 2470 */ 2471 #define __HAL_RCC_GET_USBPHY1_SOURCE() \ 2472 (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY1CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) 2473 2474 /** @brief Macro to configure the USBPHY2 clock. 2475 * @param __USBPHY2_CLKSOURCE__ specifies the USBPHY2 clock source. 2476 * This parameter can be one of the following values: 2477 * @arg RCC_USBPHY2REFCLKSOURCE_OTGPHY2 USB OTGPHY2 kernel clock selected as USBPHY2 clock 2478 * @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY2 clock 2479 * @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock 2480 */ 2481 #define __HAL_RCC_USBPHY2_CONFIG(__USBPHY2_CLKSOURCE__) \ 2482 do \ 2483 { \ 2484 LL_RCC_SetOTGPHYCKREFClockSource((__USBPHY2_CLKSOURCE__) & 0x7FFFFFFFUL); \ 2485 if(((__USBPHY2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ 2486 else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ 2487 } while (0) 2488 2489 /** @brief Macro to get the USBPHY2 clock source. 2490 * @retval The clock source can be one of the following values: 2491 * @arg RCC_USBPHY2REFCLKSOURCE_OTGPHY2 USB OTGPHY2 kernel clock selected as USBPHY2 clock 2492 * @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY2 clock 2493 * @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock 2494 */ 2495 #define __HAL_RCC_GET_USBPHY2_SOURCE() \ 2496 (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY2CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) 2497 2498 /** @brief Macro to configure the USB OTGHS1 clock. 2499 * @param __USBOTGHS1_CLKSOURCE__ specifies the USB OTGHS1 clock source. 2500 * This parameter can be one of the following values: 2501 * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHS1 clock 2502 * @arg RCC_USBOTGHS1CLKSOURCE_CLKP Peripheral clock CKLP selected as USBOTGHS1 clock 2503 * @arg RCC_USBOTGHS1CLKSOURCE_IC15 IC15 selected as USBOTGHS1 clock 2504 * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS1 clock 2505 */ 2506 #define __HAL_RCC_USBOTGHS1_CONFIG(__USBOTGHS1_CLKSOURCE__) \ 2507 do \ 2508 { \ 2509 LL_RCC_SetOTGPHYClockSource((__USBOTGHS1_CLKSOURCE__) & 0x7FFFFFFFUL); \ 2510 if(((__USBOTGHS1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ 2511 else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ 2512 } while (0) 2513 2514 /** @brief Macro to get the USB OTGHS1 clock source. 2515 * @retval The clock source can be one of the following values: 2516 * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHS1 clock 2517 * @arg RCC_USBOTGHS1CLKSOURCE_CLKP Peripheral clock CKLP selected as USBOTGHS1 clock 2518 * @arg RCC_USBOTGHS1CLKSOURCE_IC15 IC15 selected as USBOTGHS1 clock 2519 * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS1 clock 2520 */ 2521 #define __HAL_RCC_GET_USBOTGHS1_SOURCE() \ 2522 (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY1_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) 2523 2524 /** @brief Macro to configure the USB OTGHS2 clock. 2525 * @param __USBOTGHS2_CLKSOURCE__ specifies the USB OTGHS2 clock source. 2526 * This parameter can be one of the following values: 2527 * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHS2 clock 2528 * @arg RCC_USBOTGHS2CLKSOURCE_CLKP Peripheral clock CKLP selected as USBOTGHS2 clock 2529 * @arg RCC_USBOTGHS2CLKSOURCE_IC15 IC15 selected as USBOTGHS2 clock 2530 * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS2 clock 2531 */ 2532 #define __HAL_RCC_USBOTGHS2_CONFIG(__USBOTGHS2_CLKSOURCE__) \ 2533 do \ 2534 { \ 2535 LL_RCC_SetOTGPHYClockSource((__USBOTGHS2_CLKSOURCE__) & 0x7FFFFFFFUL); \ 2536 if(((__USBOTGHS2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ 2537 else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ 2538 } while (0) 2539 2540 /** @brief Macro to get the USB OTGHS2 clock source. 2541 * @retval The clock source can be one of the following values: 2542 * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBOTGHS2 clock 2543 * @arg RCC_USBOTGHS2CLKSOURCE_CLKP Peripheral clock CKLP selected as USBOTGHS2 clock 2544 * @arg RCC_USBOTGHS2C LKSOURCE_IC15 IC15 selected as USBOTGHS2 clock 2545 * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS2 clock 2546 */ 2547 #define __HAL_RCC_GET_USBOTGHS2_SOURCE() \ 2548 (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY2_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) 2549 2550 /** 2551 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 2552 * @retval None 2553 */ 2554 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS) 2555 2556 /** 2557 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 2558 * @retval None 2559 */ 2560 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS) 2561 2562 /** 2563 * @brief Enable the RCC LSE CSS Event Line. 2564 * @retval None. 2565 */ 2566 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS) 2567 2568 /** 2569 * @brief Disable the RCC LSE CSS Event Line. 2570 * @retval None. 2571 */ 2572 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS) 2573 2574 /** 2575 * @} 2576 */ 2577 2578 2579 /* Exported functions --------------------------------------------------------*/ 2580 /** @addtogroup RCCEx_Exported_Functions 2581 * @{ 2582 */ 2583 2584 /** @addtogroup RCCEx_Exported_Functions_Group1 2585 * @{ 2586 */ 2587 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2588 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2589 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 2590 uint32_t HAL_RCCEx_GetPLL1CLKFreq(void); 2591 uint32_t HAL_RCCEx_GetPLL2CLKFreq(void); 2592 uint32_t HAL_RCCEx_GetPLL3CLKFreq(void); 2593 uint32_t HAL_RCCEx_GetPLL4CLKFreq(void); 2594 /** 2595 * @} 2596 */ 2597 2598 /** @addtogroup RCCEx_Exported_Functions_Group2 2599 * @{ 2600 */ 2601 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 2602 void HAL_RCCEx_EnableLSECSS(void); 2603 void HAL_RCCEx_DisableLSECSS(void); 2604 void HAL_RCCEx_EnableLSECSS_IT(void); 2605 void HAL_RCCEx_DisableLSECSS_IT(void); 2606 void HAL_RCCEx_ReArmLSECSS(void); 2607 void HAL_RCCEx_LSECSS_IRQHandler(void); 2608 void HAL_RCCEx_LSECSS_Callback(void); 2609 HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit, 2610 const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit); 2611 2612 /** 2613 * @} 2614 */ 2615 2616 /** 2617 * @} 2618 */ 2619 2620 /* Private macros ------------------------------------------------------------*/ 2621 /** @addtogroup RCCEx_Private_Macros 2622 * @{ 2623 */ 2624 2625 /** @defgroup RCCEx_IS_RCC_Definitions Private macros to check input parameters 2626 * @{ 2627 */ 2628 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2629 ((((__SELECTION__) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ 2630 (((__SELECTION__) & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) || \ 2631 (((__SELECTION__) & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) || \ 2632 (((__SELECTION__) & RCC_PERIPHCLK_XSPI3) == RCC_PERIPHCLK_XSPI3) || \ 2633 (((__SELECTION__) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ 2634 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2635 (((__SELECTION__) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) || \ 2636 (((__SELECTION__) & RCC_PERIPHCLK_CSI) == RCC_PERIPHCLK_CSI) || \ 2637 (((__SELECTION__) & RCC_PERIPHCLK_DCMIPP) == RCC_PERIPHCLK_DCMIPP) || \ 2638 (((__SELECTION__) & RCC_PERIPHCLK_ETH1) == RCC_PERIPHCLK_ETH1) || \ 2639 (((__SELECTION__) & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) || \ 2640 (((__SELECTION__) & RCC_PERIPHCLK_ETH1RX) == RCC_PERIPHCLK_ETH1RX) || \ 2641 (((__SELECTION__) & RCC_PERIPHCLK_ETH1TX) == RCC_PERIPHCLK_ETH1TX) || \ 2642 (((__SELECTION__) & RCC_PERIPHCLK_ETH1PTP) == RCC_PERIPHCLK_ETH1PTP) || \ 2643 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 2644 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2645 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2646 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2647 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2648 (((__SELECTION__) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1) || \ 2649 (((__SELECTION__) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2) || \ 2650 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2651 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2652 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ 2653 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4) || \ 2654 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5) || \ 2655 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2656 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 2657 (((__SELECTION__) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) || \ 2658 (((__SELECTION__) & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) || \ 2659 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2660 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2661 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2662 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 2663 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ 2664 (((__SELECTION__) & RCC_PERIPHCLK_SPDIFRX1) == RCC_PERIPHCLK_SPDIFRX1) || \ 2665 (((__SELECTION__) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ 2666 (((__SELECTION__) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) || \ 2667 (((__SELECTION__) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) || \ 2668 (((__SELECTION__) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4) || \ 2669 (((__SELECTION__) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5) || \ 2670 (((__SELECTION__) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ 2671 (((__SELECTION__) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 2672 (((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2673 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2674 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2675 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2676 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2677 (((__SELECTION__) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 2678 (((__SELECTION__) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 2679 (((__SELECTION__) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 2680 (((__SELECTION__) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9) || \ 2681 (((__SELECTION__) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10) || \ 2682 (((__SELECTION__) & RCC_PERIPHCLK_USBPHY1) == RCC_PERIPHCLK_USBPHY1) || \ 2683 (((__SELECTION__) & RCC_PERIPHCLK_USBPHY2) == RCC_PERIPHCLK_USBPHY2) || \ 2684 (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS1) == RCC_PERIPHCLK_USBOTGHS1) || \ 2685 (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS2) == RCC_PERIPHCLK_USBOTGHS2)) 2686 2687 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2688 (((__SOURCE__) == RCC_ADCCLKSOURCE_HCLK) || \ 2689 ((__SOURCE__) == RCC_ADCCLKSOURCE_CLKP) || \ 2690 ((__SOURCE__) == RCC_ADCCLKSOURCE_IC7) || \ 2691 ((__SOURCE__) == RCC_ADCCLKSOURCE_IC8) || \ 2692 ((__SOURCE__) == RCC_ADCCLKSOURCE_MSI) || \ 2693 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ 2694 ((__SOURCE__) == RCC_ADCCLKSOURCE_PIN) || \ 2695 ((__SOURCE__) == RCC_ADCCLKSOURCE_TIMG)) 2696 2697 #define IS_RCC_ADCDIVIDER(__VALUE__) \ 2698 ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U)) 2699 2700 #define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ 2701 (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ 2702 ((__SOURCE__) == RCC_ADF1CLKSOURCE_CLKP) || \ 2703 ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC7) || \ 2704 ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC8) || \ 2705 ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSI) || \ 2706 ((__SOURCE__) == RCC_ADF1CLKSOURCE_HSI) || \ 2707 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ 2708 ((__SOURCE__) == RCC_ADF1CLKSOURCE_TIMG)) 2709 2710 #define IS_RCC_CKPERCLKSOURCE(__SOURCE__) \ 2711 (((__SOURCE__) == RCC_CLKPCLKSOURCE_HSI) || \ 2712 ((__SOURCE__) == RCC_CLKPCLKSOURCE_MSI) || \ 2713 ((__SOURCE__) == RCC_CLKPCLKSOURCE_HSE) || \ 2714 ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC19) || \ 2715 ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC5) || \ 2716 ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC10) || \ 2717 ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC15) || \ 2718 ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC20)) 2719 2720 #define IS_RCC_DCMIPPCLKSOURCE(__SOURCE__) \ 2721 (((__SOURCE__) == RCC_DCMIPPCLKSOURCE_PCLK5) || \ 2722 ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_CLKP) || \ 2723 ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_IC17) || \ 2724 ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_HSI)) 2725 2726 #define IS_RCC_ETH1CLKSOURCE(__SOURCE__) \ 2727 (((__SOURCE__) == RCC_ETH1CLKSOURCE_HCLK) || \ 2728 ((__SOURCE__) == RCC_ETH1CLKSOURCE_CLKP) || \ 2729 ((__SOURCE__) == RCC_ETH1CLKSOURCE_IC12) || \ 2730 ((__SOURCE__) == RCC_ETH1CLKSOURCE_HSE)) 2731 2732 #define IS_RCC_ETH1PHYIF(__SOURCE__) \ 2733 (((__SOURCE__) == RCC_ETH1PHYIF_MII) || \ 2734 ((__SOURCE__) == RCC_ETH1PHYIF_RGMII) || \ 2735 ((__SOURCE__) == RCC_ETH1PHYIF_RMII)) 2736 2737 #define IS_RCC_ETH1RXCLKSOURCE(__SOURCE__) \ 2738 (((__SOURCE__) == RCC_ETH1RXCLKSOURCE_EXT) || \ 2739 ((__SOURCE__) == RCC_ETH1RXCLKSOURCE_INT)) 2740 2741 #define IS_RCC_ETH1TXCLKSOURCE(__SOURCE__) \ 2742 (((__SOURCE__) == RCC_ETH1TXCLKSOURCE_EXT) || \ 2743 ((__SOURCE__) == RCC_ETH1TXCLKSOURCE_INT)) 2744 2745 #define IS_RCC_ETH1PTPCLKSOURCE(__SOURCE__) \ 2746 (((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HCLK) || \ 2747 ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_CLKP) || \ 2748 ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_IC13) || \ 2749 ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HSE)) 2750 2751 #define IS_RCC_ETH1PTPDIVIDER(__VALUE__) \ 2752 ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2753 2754 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 2755 (((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1) || \ 2756 ((__SOURCE__) == RCC_FDCANCLKSOURCE_CLKP) || \ 2757 ((__SOURCE__) == RCC_FDCANCLKSOURCE_IC19) || \ 2758 ((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)) 2759 2760 #define IS_RCC_FMCCLKSOURCE(__SOURCE__) \ 2761 (((__SOURCE__) == RCC_FMCCLKSOURCE_HCLK) || \ 2762 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP) || \ 2763 ((__SOURCE__) == RCC_FMCCLKSOURCE_IC3) || \ 2764 ((__SOURCE__) == RCC_FMCCLKSOURCE_IC4)) 2765 2766 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 2767 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 2768 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CLKP) || \ 2769 ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC10) || \ 2770 ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC15) || \ 2771 ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSI) || \ 2772 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 2773 2774 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 2775 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 2776 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CLKP) || \ 2777 ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC10) || \ 2778 ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC15) || \ 2779 ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSI) || \ 2780 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 2781 2782 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 2783 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 2784 ((__SOURCE__) == RCC_I2C3CLKSOURCE_CLKP) || \ 2785 ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC10) || \ 2786 ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC15) || \ 2787 ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSI) || \ 2788 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 2789 2790 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 2791 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 2792 ((__SOURCE__) == RCC_I2C4CLKSOURCE_CLKP) || \ 2793 ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC10) || \ 2794 ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC15) || \ 2795 ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSI) || \ 2796 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 2797 2798 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 2799 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 2800 ((__SOURCE__) == RCC_I3C1CLKSOURCE_CLKP) || \ 2801 ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC10) || \ 2802 ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC15) || \ 2803 ((__SOURCE__) == RCC_I3C1CLKSOURCE_MSI) || \ 2804 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 2805 2806 #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ 2807 (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK1) || \ 2808 ((__SOURCE__) == RCC_I3C2CLKSOURCE_CLKP) || \ 2809 ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC10) || \ 2810 ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC15) || \ 2811 ((__SOURCE__) == RCC_I3C2CLKSOURCE_MSI) || \ 2812 ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) 2813 2814 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 2815 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 2816 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP) || \ 2817 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_IC15) || \ 2818 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 2819 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 2820 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_TIMG)) 2821 2822 #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ 2823 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK4) || \ 2824 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP) || \ 2825 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_IC15) || \ 2826 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 2827 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 2828 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_TIMG)) 2829 2830 #define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) \ 2831 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK4) || \ 2832 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP) || \ 2833 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_IC15) || \ 2834 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ 2835 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 2836 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_TIMG)) 2837 2838 #define IS_RCC_LPTIM4CLKSOURCE(__SOURCE__) \ 2839 (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK4) || \ 2840 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP) || \ 2841 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_IC15) || \ 2842 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ 2843 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ 2844 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_TIMG)) 2845 2846 #define IS_RCC_LPTIM5CLKSOURCE(__SOURCE__) \ 2847 (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK4) || \ 2848 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP) || \ 2849 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_IC15) || \ 2850 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ 2851 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ 2852 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_TIMG)) 2853 2854 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 2855 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK4) || \ 2856 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CLKP) || \ 2857 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC9) || \ 2858 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC14) || \ 2859 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 2860 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSI) || \ 2861 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 2862 2863 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 2864 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PCLK5) || \ 2865 ((__SOURCE__) == RCC_LTDCCLKSOURCE_CLKP) || \ 2866 ((__SOURCE__) == RCC_LTDCCLKSOURCE_IC16) || \ 2867 ((__SOURCE__) == RCC_LTDCCLKSOURCE_HSI)) 2868 2869 #define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \ 2870 (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \ 2871 ((__SOURCE__) == RCC_MDF1CLKSOURCE_CLKP) || \ 2872 ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC7) || \ 2873 ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC8) || \ 2874 ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSI) || \ 2875 ((__SOURCE__) == RCC_MDF1CLKSOURCE_HSI) || \ 2876 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \ 2877 ((__SOURCE__) == RCC_MDF1CLKSOURCE_TIMG)) 2878 2879 #define IS_RCC_PSSICLKSOURCE(__SOURCE__) \ 2880 (((__SOURCE__) == RCC_PSSICLKSOURCE_HCLK) || \ 2881 ((__SOURCE__) == RCC_PSSICLKSOURCE_CLKP) || \ 2882 ((__SOURCE__) == RCC_PSSICLKSOURCE_IC20) || \ 2883 ((__SOURCE__) == RCC_PSSICLKSOURCE_HSI)) 2884 2885 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 2886 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PCLK2) || \ 2887 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 2888 ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC7) || \ 2889 ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC8) || \ 2890 ((__SOURCE__) == RCC_SAI1CLKSOURCE_MSI) || \ 2891 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ 2892 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 2893 ((__SOURCE__) == RCC_SAI1CLKSOURCE_SPDIFRX1)) 2894 2895 #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ 2896 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PCLK2) || \ 2897 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 2898 ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC7) || \ 2899 ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC8) || \ 2900 ((__SOURCE__) == RCC_SAI2CLKSOURCE_MSI) || \ 2901 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI) || \ 2902 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 2903 ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIFRX1)) 2904 2905 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2906 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HCLK) || \ 2907 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_CLKP) || \ 2908 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC4) || \ 2909 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC5)) 2910 2911 #define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ 2912 (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_HCLK) || \ 2913 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_CLKP) || \ 2914 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC4) || \ 2915 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC5)) 2916 2917 #define IS_RCC_SPDIFRX1CLKSOURCE(__SOURCE__) \ 2918 (((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PCLK1) || \ 2919 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_CLKP) || \ 2920 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC7) || \ 2921 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC8) || \ 2922 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_MSI) || \ 2923 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_HSI) || \ 2924 ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PIN)) 2925 2926 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 2927 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ 2928 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ 2929 ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC8) || \ 2930 ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC9) || \ 2931 ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSI) || \ 2932 ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI) || \ 2933 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) 2934 2935 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 2936 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \ 2937 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ 2938 ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC8) || \ 2939 ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC9) || \ 2940 ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSI) || \ 2941 ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI) || \ 2942 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) 2943 2944 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 2945 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK1) || \ 2946 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ 2947 ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC8) || \ 2948 ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC9) || \ 2949 ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSI) || \ 2950 ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI) || \ 2951 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) 2952 2953 #define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ 2954 (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ 2955 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CLKP) || \ 2956 ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC9) || \ 2957 ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC14) || \ 2958 ((__SOURCE__) == RCC_SPI4CLKSOURCE_MSI) || \ 2959 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 2960 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 2961 2962 #define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ 2963 (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK2) || \ 2964 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CLKP) || \ 2965 ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC9) || \ 2966 ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC14) || \ 2967 ((__SOURCE__) == RCC_SPI5CLKSOURCE_MSI) || \ 2968 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 2969 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 2970 2971 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 2972 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK4) || \ 2973 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CLKP) || \ 2974 ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC8) || \ 2975 ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC9) || \ 2976 ((__SOURCE__) == RCC_SPI6CLKSOURCE_MSI) || \ 2977 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 2978 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) 2979 2980 #define IS_RCC_TIMPRES(__VALUE__) \ 2981 (((__VALUE__) == RCC_TIMPRES_DIV1) || \ 2982 ((__VALUE__) == RCC_TIMPRES_DIV2) || \ 2983 ((__VALUE__) == RCC_TIMPRES_DIV4) || \ 2984 ((__VALUE__) == RCC_TIMPRES_DIV8)) 2985 2986 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 2987 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 2988 ((__SOURCE__) == RCC_USART1CLKSOURCE_CLKP) || \ 2989 ((__SOURCE__) == RCC_USART1CLKSOURCE_IC9) || \ 2990 ((__SOURCE__) == RCC_USART1CLKSOURCE_IC14) || \ 2991 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 2992 ((__SOURCE__) == RCC_USART1CLKSOURCE_MSI) || \ 2993 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 2994 2995 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 2996 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 2997 ((__SOURCE__) == RCC_USART2CLKSOURCE_CLKP) || \ 2998 ((__SOURCE__) == RCC_USART2CLKSOURCE_IC9) || \ 2999 ((__SOURCE__) == RCC_USART2CLKSOURCE_IC14) || \ 3000 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 3001 ((__SOURCE__) == RCC_USART2CLKSOURCE_MSI) || \ 3002 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 3003 3004 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3005 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3006 ((__SOURCE__) == RCC_USART3CLKSOURCE_CLKP) || \ 3007 ((__SOURCE__) == RCC_USART3CLKSOURCE_IC9) || \ 3008 ((__SOURCE__) == RCC_USART3CLKSOURCE_IC14) || \ 3009 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 3010 ((__SOURCE__) == RCC_USART3CLKSOURCE_MSI) || \ 3011 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 3012 3013 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 3014 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 3015 ((__SOURCE__) == RCC_UART4CLKSOURCE_CLKP) || \ 3016 ((__SOURCE__) == RCC_UART4CLKSOURCE_IC9) || \ 3017 ((__SOURCE__) == RCC_UART4CLKSOURCE_IC14) || \ 3018 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 3019 ((__SOURCE__) == RCC_UART4CLKSOURCE_MSI) || \ 3020 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 3021 3022 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 3023 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 3024 ((__SOURCE__) == RCC_UART5CLKSOURCE_CLKP) || \ 3025 ((__SOURCE__) == RCC_UART5CLKSOURCE_IC9) || \ 3026 ((__SOURCE__) == RCC_UART5CLKSOURCE_IC14) || \ 3027 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 3028 ((__SOURCE__) == RCC_UART5CLKSOURCE_MSI) || \ 3029 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 3030 3031 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ 3032 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK2) || \ 3033 ((__SOURCE__) == RCC_USART6CLKSOURCE_CLKP) || \ 3034 ((__SOURCE__) == RCC_USART6CLKSOURCE_IC9) || \ 3035 ((__SOURCE__) == RCC_USART6CLKSOURCE_IC14) || \ 3036 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE) || \ 3037 ((__SOURCE__) == RCC_USART6CLKSOURCE_MSI) || \ 3038 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI)) 3039 3040 #define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ 3041 (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ 3042 ((__SOURCE__) == RCC_UART7CLKSOURCE_CLKP) || \ 3043 ((__SOURCE__) == RCC_UART7CLKSOURCE_IC9) || \ 3044 ((__SOURCE__) == RCC_UART7CLKSOURCE_IC14) || \ 3045 ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE) || \ 3046 ((__SOURCE__) == RCC_UART7CLKSOURCE_MSI) || \ 3047 ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI)) 3048 3049 #define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ 3050 (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ 3051 ((__SOURCE__) == RCC_UART8CLKSOURCE_CLKP) || \ 3052 ((__SOURCE__) == RCC_UART8CLKSOURCE_IC9) || \ 3053 ((__SOURCE__) == RCC_UART8CLKSOURCE_IC14) || \ 3054 ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE) || \ 3055 ((__SOURCE__) == RCC_UART8CLKSOURCE_MSI) || \ 3056 ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI)) 3057 3058 #define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ 3059 (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK2) || \ 3060 ((__SOURCE__) == RCC_UART9CLKSOURCE_CLKP) || \ 3061 ((__SOURCE__) == RCC_UART9CLKSOURCE_IC9) || \ 3062 ((__SOURCE__) == RCC_UART9CLKSOURCE_IC14) || \ 3063 ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE) || \ 3064 ((__SOURCE__) == RCC_UART9CLKSOURCE_MSI) || \ 3065 ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI)) 3066 3067 #define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ 3068 (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK2) || \ 3069 ((__SOURCE__) == RCC_USART10CLKSOURCE_CLKP) || \ 3070 ((__SOURCE__) == RCC_USART10CLKSOURCE_IC9) || \ 3071 ((__SOURCE__) == RCC_USART10CLKSOURCE_IC14) || \ 3072 ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE) || \ 3073 ((__SOURCE__) == RCC_USART10CLKSOURCE_MSI) || \ 3074 ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI)) 3075 3076 #define IS_RCC_USBPHY1CLKSOURCE(__SOURCE__) \ 3077 (((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_OTGPHY1) || \ 3078 ((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT) || \ 3079 ((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2)) 3080 3081 #define IS_RCC_USBPHY2CLKSOURCE(__SOURCE__) \ 3082 (((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_OTGPHY2) || \ 3083 ((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT) || \ 3084 ((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2)) 3085 3086 #define IS_RCC_USBOTGHS1CLKSOURCE(__SOURCE__) \ 3087 (((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIV2) || \ 3088 ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_CLKP) || \ 3089 ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_IC15) || \ 3090 ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT) || \ 3091 ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2)) 3092 3093 #define IS_RCC_USBOTGHS2CLKSOURCE(__SOURCE__) \ 3094 (((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIV2) || \ 3095 ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_CLKP) || \ 3096 ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_IC15) || \ 3097 ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT) || \ 3098 ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2)) 3099 3100 #define IS_RCC_XSPI1CLKSOURCE(__SOURCE__) \ 3101 (((__SOURCE__) == RCC_XSPI1CLKSOURCE_HCLK) || \ 3102 ((__SOURCE__) == RCC_XSPI1CLKSOURCE_CLKP) || \ 3103 ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC3) || \ 3104 ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC4)) 3105 3106 #define IS_RCC_XSPI2CLKSOURCE(__SOURCE__) \ 3107 (((__SOURCE__) == RCC_XSPI2CLKSOURCE_HCLK) || \ 3108 ((__SOURCE__) == RCC_XSPI2CLKSOURCE_CLKP) || \ 3109 ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC3) || \ 3110 ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC4)) 3111 3112 #define IS_RCC_XSPI3CLKSOURCE(__SOURCE__) \ 3113 (((__SOURCE__) == RCC_XSPI3CLKSOURCE_HCLK) || \ 3114 ((__SOURCE__) == RCC_XSPI3CLKSOURCE_CLKP) || \ 3115 ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC3) || \ 3116 ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC4)) 3117 3118 /** 3119 * @} 3120 */ 3121 3122 /** 3123 * @} 3124 */ 3125 3126 /** 3127 * @} 3128 */ 3129 3130 /** 3131 * @} 3132 */ 3133 3134 #ifdef __cplusplus 3135 } 3136 #endif 3137 3138 #endif /* STM32N6xx_HAL_RCC_EX_H */ 3139
