1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32U0xx_HAL_RCC_EX_H 20 #define __STM32U0xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32u0xx_hal_def.h" 28 29 /** @addtogroup STM32U0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL Clocks structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLL_P_Frequency; 49 uint32_t PLL_Q_Frequency; 50 uint32_t PLL_R_Frequency; 51 } PLL_ClocksTypeDef; 52 53 /** 54 * @brief RCC extended clocks structure definition 55 */ 56 typedef struct 57 { 58 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 59 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 60 61 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 62 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 63 64 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 65 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 66 #if defined (LPUART3) 67 uint32_t Lpuart3ClockSelection; /*!< Specifies LPUART1 clock source. 68 This parameter can be a value of @ref RCCEx_LPUART3_Clock_Source */ 69 #endif /* LPUART3 */ 70 uint32_t Lpuart2ClockSelection; /*!< Specifies LPUART2 clock source. 71 This parameter can be a value of @ref RCCEx_LPUART2_Clock_Source */ 72 73 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART3 clock source. 74 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 75 76 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 77 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 78 79 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 80 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 81 82 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 83 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 84 85 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 86 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 87 #if defined (LPTIM3) 88 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 89 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 90 #endif /* LPTIM3 */ 91 uint32_t Tim1ClockSelection; /*!< Specifies TIM1 clock source. 92 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 93 94 uint32_t Tim15ClockSelection; /*!< Specifies TIM15 clock source. 95 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 96 #if defined(USB_DRD_FS) 97 uint32_t UsbClockSelection; /*!< Specifies USB clock source. 98 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 99 #endif /* USB_DRD_FS */ 100 uint32_t RngClockSelection; /*!< Specifies RNG clock source. 101 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 102 103 uint32_t AdcClockSelection; /*!< Specifies ADC clock source. 104 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 105 106 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 107 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 108 } RCC_PeriphCLKInitTypeDef; 109 110 #if defined (CRS) 111 /** 112 * @brief RCC_CRS Init structure definition 113 */ 114 typedef struct 115 { 116 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 117 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 118 119 uint32_t Source; /*!< Specifies the SYNC signal source. 120 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 121 122 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 123 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 124 125 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 126 event. It can be calculated in using macro 127 @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 128 This parameter must be a number between 0 and 0xFFFF or a value of 129 @ref RCCEx_CRS_ReloadValueDefault .*/ 130 131 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 132 This parameter must be a number between 0 and 0xFF or a value of 133 @ref RCCEx_CRS_ErrorLimitDefault */ 134 135 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 136 This parameter must be a number between 0 and 0x3F or a value of 137 @ref RCCEx_CRS_HSI48CalibrationDefault */ 138 139 } RCC_CRSInitTypeDef; 140 141 /** 142 * @brief RCC_CRS Synchronization structure definition 143 */ 144 typedef struct 145 { 146 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 147 This parameter must be a number between 0 and 0xFFFF */ 148 149 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in RC48 oscillator smooth trimming. 150 This parameter must be a number between 0 and 0x3F */ 151 152 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 153 value latched in the time of the last SYNC event. 154 This parameter must be a number between 0 and 0xFFFF */ 155 156 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 157 frequency error counter latched in the time of the last SYNC event. 158 It shows whether the actual frequency is below or above the target. 159 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection */ 160 161 } RCC_CRSSynchroInfoTypeDef; 162 163 #endif /* CRS */ 164 /** 165 * @} 166 */ 167 168 /* Exported constants --------------------------------------------------------*/ 169 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 170 * @{ 171 */ 172 173 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 174 * @{ 175 */ 176 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */ 177 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 178 /** 179 * @} 180 */ 181 182 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 183 * @{ 184 */ 185 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) 186 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) 187 #if defined (LPUART3) 188 #define RCC_PERIPHCLK_LPUART3 ((uint32_t)0x00000004U) 189 #endif /* LPUART3 */ 190 #define RCC_PERIPHCLK_LPUART2 ((uint32_t)0x00000008U) 191 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000010U) 192 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020U) 193 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000040U) 194 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U) 195 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000100U) 196 #if defined (LPTIM3) 197 #define RCC_PERIPHCLK_LPTIM3 ((uint32_t)0x00000200U) 198 #endif /* LPTIM3 */ 199 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00000400U) 200 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00000800U) 201 #if defined(USB_DRD_FS) 202 #define RCC_PERIPHCLK_USB ((uint32_t)0x00001000U) 203 #endif /* USB_DRD_FS */ 204 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00002000U) 205 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U) 206 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00008000U) 207 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00010000U) 208 #define RCC_PERIPHCLK_USART4 ((uint32_t)0x00020000U) 209 210 /** 211 * @} 212 */ 213 214 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 215 * @{ 216 */ 217 #define RCC_USART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 218 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 219 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 220 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 221 /** 222 * @} 223 */ 224 225 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 226 * @{ 227 */ 228 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 229 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 230 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 231 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 232 /** 233 * @} 234 */ 235 236 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 237 * @{ 238 */ 239 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 240 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 241 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 242 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 243 /** 244 * @} 245 */ 246 247 /** @defgroup RCCEx_LPUART2_Clock_Source LPUART2 Clock Source 248 * @{ 249 */ 250 #define RCC_LPUART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 251 #define RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0 252 #define RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1 253 #define RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1) 254 /** 255 * @} 256 */ 257 258 #if defined (LPUART3) 259 /** @defgroup RCCEx_LPUART3_Clock_Source LPUART3 Clock Source 260 * @{ 261 */ 262 #define RCC_LPUART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 263 #define RCC_LPUART3CLKSOURCE_SYSCLK RCC_CCIPR_LPUART3SEL_0 264 #define RCC_LPUART3CLKSOURCE_HSI RCC_CCIPR_LPUART3SEL_1 265 #define RCC_LPUART3CLKSOURCE_LSE (RCC_CCIPR_LPUART3SEL_0 | RCC_CCIPR_LPUART3SEL_1) 266 /** 267 * @} 268 */ 269 #endif /* LPUART3 */ 270 271 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 272 * @{ 273 */ 274 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 275 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 276 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 277 /** 278 * @} 279 */ 280 281 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 282 * @{ 283 */ 284 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 285 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 286 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 287 /** 288 * @} 289 */ 290 291 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 292 * @{ 293 */ 294 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 295 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 296 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 297 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1) 298 /** 299 * @} 300 */ 301 302 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 303 * @{ 304 */ 305 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 306 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 307 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 308 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL_0 | RCC_CCIPR_LPTIM2SEL_1) 309 /** 310 * @} 311 */ 312 313 #if defined (LPTIM3) 314 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 315 * @{ 316 */ 317 #define RCC_LPTIM3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 318 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR_LPTIM3SEL_0 319 #define RCC_LPTIM3CLKSOURCE_HSI RCC_CCIPR_LPTIM3SEL_1 320 #define RCC_LPTIM3CLKSOURCE_LSE (RCC_CCIPR_LPTIM3SEL_0 | RCC_CCIPR_LPTIM3SEL_1) 321 /** 322 * @} 323 */ 324 #endif /* LPTIM3 */ 325 326 /** @defgroup RCCEx_TIM1_Clock_Source TIM1 Clock Source 327 * @{ 328 */ 329 #define RCC_TIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 330 #define RCC_TIM1CLKSOURCE_PLLQ RCC_CCIPR_TIM1SEL 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCCEx_TIM15_Clock_Source TIM15 Clock Source 336 * @{ 337 */ 338 #define RCC_TIM15CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 339 #define RCC_TIM15CLKSOURCE_PLLQ RCC_CCIPR_TIM15SEL 340 /** 341 * @} 342 */ 343 #if defined(USB_DRD_FS) 344 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 345 * @{ 346 */ 347 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U) 348 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL_0 349 #define RCC_USBCLKSOURCE_PLLQ RCC_CCIPR_CLK48SEL_1 350 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_CLK48SEL 351 /** 352 * @} 353 */ 354 #endif /* USB_DRD_FS */ 355 356 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 357 * @{ 358 */ 359 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U) 360 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL_0 361 #define RCC_RNGCLKSOURCE_PLLQ RCC_CCIPR_CLK48SEL_1 362 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_CLK48SEL 363 /** 364 * @} 365 */ 366 /** @defgroup RCCEx_ADC_Clock_Source ADC1 Clock Source 367 * @{ 368 */ 369 #define RCC_ADCCLKSOURCE_SYSCLK ((uint32_t)0x00000000U) 370 #define RCC_ADCCLKSOURCE_PLLP RCC_CCIPR_ADCSEL_0 371 #define RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 372 /** 373 * @} 374 */ 375 376 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 377 * @{ 378 */ 379 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM27 /*!< External interrupt line 27 connected to the LSE CSS EXTI Line */ 380 /** 381 * @} 382 */ 383 384 #if defined(CRS) 385 386 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 387 * @{ 388 */ 389 #define RCC_CRS_NONE 0x00000000U 390 #define RCC_CRS_TIMEOUT 0x00000001U 391 #define RCC_CRS_SYNCOK 0x00000002U 392 #define RCC_CRS_SYNCWARN 0x00000004U 393 #define RCC_CRS_SYNCERR 0x00000008U 394 #define RCC_CRS_SYNCMISS 0x00000010U 395 #define RCC_CRS_TRIMOVF 0x00000020U 396 /** 397 * @} 398 */ 399 400 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 401 * @{ 402 */ 403 #define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ 404 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 405 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 406 /** 407 * @} 408 */ 409 410 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 411 * @{ 412 */ 413 #define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ 414 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 415 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 416 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 417 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 418 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 419 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 420 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 426 * @{ 427 */ 428 #define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ 429 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 435 * @{ 436 */ 437 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 438 to a target frequency of 48 MHz and a synchronization 439 signal frequency of 1 kHz (SOF signal from USB). */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 445 * @{ 446 */ 447 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 453 * @{ 454 */ 455 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle 456 of the trimming interval. The trimming step is specified in 457 the product datasheet. A higher TRIM value corresponds 458 to a higher output frequency */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 464 * @{ 465 */ 466 #define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ 467 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 473 * @{ 474 */ 475 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 476 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 477 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 478 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 479 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 480 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 481 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 487 * @{ 488 */ 489 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 490 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 491 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 492 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 493 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 494 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 495 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 496 /** 497 * @} 498 */ 499 500 #endif /* CRS */ 501 502 /** 503 * @} 504 */ 505 506 /* Exported macros -----------------------------------------------------------*/ 507 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 508 * @{ 509 */ 510 511 /** @brief Macro to configure the USART1 clock (USART1CLK). 512 * 513 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 514 * This parameter can be one of the following values: 515 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK selected as USART1 clock 516 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 517 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 518 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 519 * @retval None 520 */ 521 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 522 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 523 524 /** @brief Macro to get the USART1 clock source. 525 * @retval The clock source can be one of the following values: 526 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK selected as USART1 clock 527 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 528 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 529 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 530 */ 531 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 532 533 /** @brief Macro to configure the USART2 clock (USART2CLK). 534 * 535 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 536 * This parameter can be one of the following values: 537 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK selected as USART2 clock 538 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 539 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 540 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 541 * @retval None 542 */ 543 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 544 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 545 546 /** @brief Macro to get the USART2 clock source. 547 * @retval The clock source can be one of the following values: 548 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK selected as USART2 clock 549 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 550 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 551 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 552 */ 553 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) 554 555 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 556 * 557 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 558 * This parameter can be one of the following values: 559 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK selected as LPUART1 clock 560 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 561 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 562 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 563 * @retval None 564 */ 565 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 566 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 567 568 /** @brief Macro to get the LPUART1 clock source. 569 * @retval The clock source can be one of the following values: 570 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK selected as LPUART1 clock 571 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 572 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 573 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 574 */ 575 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) 576 577 /** @brief Macro to configure the LPUART2 clock (LPUART2CLK). 578 * 579 * @param __LPUART2_CLKSOURCE__ specifies the LPUART2 clock source. 580 * This parameter can be one of the following values: 581 * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK selected as LPUART2 clock 582 * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock 583 * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock 584 * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock 585 * @retval None 586 */ 587 #define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \ 588 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) 589 590 /** @brief Macro to get the LPUART2 clock source. 591 * @retval The clock source can be one of the following values: 592 * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK selected as LPUART2 clock 593 * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock 594 * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock 595 * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock 596 */ 597 #define __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL))) 598 599 #if defined (LPUART3) 600 /** @brief Macro to configure the LPUART3 clock (LPUART3CLK). 601 * 602 * @param __LPUART3_CLKSOURCE__ specifies the LPUART3 clock source. 603 * This parameter can be one of the following values: 604 * @arg @ref RCC_LPUART3CLKSOURCE_PCLK1 PCLK selected as LPUART3 clock 605 * @arg @ref RCC_LPUART3CLKSOURCE_HSI HSI selected as LPUART3 clock 606 * @arg @ref RCC_LPUART3CLKSOURCE_SYSCLK System Clock selected as LPUART3 clock 607 * @arg @ref RCC_LPUART3CLKSOURCE_LSE LSE selected as LPUART3 clock 608 * @retval None 609 */ 610 #define __HAL_RCC_LPUART3_CONFIG(__LPUART3_CLKSOURCE__) \ 611 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART3SEL, (uint32_t)(__LPUART3_CLKSOURCE__)) 612 613 /** @brief Macro to get the LPUART3 clock source. 614 * @retval The clock source can be one of the following values: 615 * @arg @ref RCC_LPUART3CLKSOURCE_PCLK1 PCLK selected as LPUART3 clock 616 * @arg @ref RCC_LPUART3CLKSOURCE_HSI HSI selected as LPUART3 clock 617 * @arg @ref RCC_LPUART3CLKSOURCE_SYSCLK System Clock selected as LPUART3 clock 618 * @arg @ref RCC_LPUART3CLKSOURCE_LSE LSE selected as LPUART3 clock 619 */ 620 #define __HAL_RCC_GET_LPUART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART3SEL))) 621 #endif /* LPUART3 */ 622 623 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 624 * 625 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 626 * This parameter can be one of the following values: 627 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK selected as I2C1 clock 628 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 629 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 630 * @retval None 631 */ 632 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 633 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 634 635 /** @brief Macro to get the I2C1 clock source. 636 * @retval The clock source can be one of the following values: 637 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK selected as I2C1 clock 638 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 639 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 640 */ 641 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 642 643 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 644 * 645 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 646 * This parameter can be one of the following values: 647 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK selected as I2C3 clock 648 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 649 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 650 * @retval None 651 */ 652 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 654 655 /** @brief Macro to get the I2C3 clock source. 656 * @retval The clock source can be one of the following values: 657 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK selected as I2C3 clock 658 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 659 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 660 */ 661 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) 662 663 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 664 * 665 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 666 * This parameter can be one of the following values: 667 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock 668 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 669 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 670 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 671 * @retval None 672 */ 673 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 674 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 675 676 /** @brief Macro to get the LPTIM1 clock source. 677 * @retval The clock source can be one of the following values: 678 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 679 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 680 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 681 */ 682 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) 683 684 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 685 * 686 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 687 * This parameter can be one of the following values: 688 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 689 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 690 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 691 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 692 * @retval None 693 */ 694 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 695 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 696 697 /** @brief Macro to get the LPTIM2 clock source. 698 * @retval The clock source can be one of the following values: 699 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 700 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 701 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 702 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 703 */ 704 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) 705 706 #if defined (LPTIM3) 707 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 708 * 709 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 710 * This parameter can be one of the following values: 711 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock 712 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 713 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 714 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 715 * @retval None 716 */ 717 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 718 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 719 720 /** @brief Macro to get the LPTIM3 clock source. 721 * @retval The clock source can be one of the following values: 722 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock 723 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 724 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 725 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 726 */ 727 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM3SEL))) 728 #endif /* LPTIM3 */ 729 730 #if defined(USB_DRD_FS) 731 /** @brief Macro to configure the CLK48 source (CLK48CLK). 732 * 733 * @param __USB_SOURCE__: specifies the CLK48 clock source. 734 * This parameter can be one of the following values: 735 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB source 736 * @arg RCC_USBCLKSOURCE_PLLQ : PLL selected as USB source 737 * @arg RCC_USBCLKSOURCE_MSIS : MSIS selected as USB source 738 */ 739 #define __HAL_RCC_USB_CONFIG(__USB_SOURCE__) \ 740 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_SOURCE__)) 741 742 /** @brief macro to get the USB source. 743 * @retval The clock source can be one of the following values: 744 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 used as USB source 745 * @arg RCC_USBCLKSOURCE_PLLQ : PLL used as USB source 746 * @arg RCC_USBCLKSOURCE_MSIS : MSIS used as USB source 747 */ 748 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 749 #endif /* USB_DRD_FS */ 750 751 /** @brief Macro to configure the RNG source (CLK48CLK). 752 * 753 * @param __RNG_SOURCE__: specifies the CLK48 clock source. 754 * This parameter can be one of the following values: 755 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as USB source 756 * @arg RCC_RNGCLKSOURCE_PLLQ : PLL selected as USB source 757 * @arg RCC_RNGCLKSOURCE_MSIS : MSIS selected as USB source 758 */ 759 #define __HAL_RCC_RNG_CONFIG(__RNG_SOURCE__) \ 760 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_SOURCE__)) 761 762 /** @brief macro to get the RNG source. 763 * @retval The clock source can be one of the following values: 764 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 used as USB source 765 * @arg RCC_RNGCLKSOURCE_PLLQ : PLL used as USB source 766 * @arg RCC_RNGCLKSOURCE_MSIS : MSIS used as USB source 767 */ 768 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 769 770 /** @brief macro to configure the ADC clock source. 771 * @retval The clock source can be one of the following values: 772 * @arg RCC_ADCCLKSOURCE_SYSCLK : SYSCLK Clock selected as ADC1 clock 773 * @arg RCC_ADCCLKSOURCE_PLLP : PLLP Clock selected as ADC1 clock 774 * @arg RCC_ADCCLKSOURCE_HSI : HSI Clock selected as ADC1 clock 775 */ 776 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 777 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 778 779 /** @brief macro to get the ADC clock source. 780 * @retval The clock source can be one of the following values: 781 * @arg RCC_ADCCLKSOURCE_SYSCLK : SYSCLK Clock selected as ADC clock 782 * @arg RCC_ADCCLKSOURCE_PLLP : PLLP Clock selected as ADC clock 783 * @arg RCC_ADCCLKSOURCE_HSI : HSI Clock selected as ADC clock 784 */ 785 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) 786 787 /** @brief macro to configure the TIM1 clock source. 788 * @retval The clock source can be one of the following values: 789 * @arg RCC_TIM1CLKSOURCE_PCLK : PCLK Clock used as TIM1 clock 790 * @arg RCC_TIM1CLKSOURCE_PLLQ : PLLQ clock used as TIM1 clock 791 */ 792 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ 793 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1CLKSource__)) 794 795 /** @brief macro to get the TIM1 clock source. 796 * @retval The clock source can be one of the following values: 797 * @arg RCC_TIM1CLKSOURCE_PCLK1 : PCLK Clock used as TIM1 clock 798 * @arg RCC_TIM1CLKSOURCE_PLLQ : PLLQ clock used as TIM1 clock 799 */ 800 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL))) 801 802 /** @brief macro to configure the TIM15 clock source. 803 * @retval The clock source can be one of the following values: 804 * @arg RCC_TIM15CLKSOURCE_PCLK1 : PCLK Clock used as TIM15 clock 805 * @arg RCC_TIM15CLKSOURCE_PLLQ : PLLQ clock used as TIM15 clock 806 */ 807 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ 808 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM15CLKSource__)) 809 810 /** @brief macro to get the TIM15 clock source. 811 * @retval The clock source can be one of the following values: 812 * @arg RCC_TIM15CLKSOURCE_PCLK1 : PCLK Clock used as TIM15 clock 813 * @arg RCC_TIM15CLKSOURCE_PLLQ : PLLQ clock used as TIM15 clock 814 */ 815 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL))) 816 817 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 818 * @brief macros to manage the specified RCC Flags and interrupts. 819 * @{ 820 */ 821 822 /** 823 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 824 * @retval None 825 */ 826 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 827 828 /** 829 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 830 * @retval None 831 */ 832 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 833 834 /** 835 * @brief Enable the RCC LSE CSS Event Line. 836 * @retval None. 837 */ 838 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 839 840 /** 841 * @brief Disable the RCC LSE CSS Event Line. 842 * @retval None. 843 */ 844 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 845 846 /** 847 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 848 * @retval None. 849 */ 850 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 851 852 /** 853 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 854 * @retval None. 855 */ 856 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 857 858 859 /** 860 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 861 * @retval None. 862 */ 863 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 864 865 /** 866 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 867 * @retval None. 868 */ 869 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 870 871 /** 872 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 873 * @retval None. 874 */ 875 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 876 do { \ 877 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 878 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 879 } while(0) 880 881 /** 882 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 883 * @retval None. 884 */ 885 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 886 do { \ 887 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 888 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 889 } while(0) 890 891 /** 892 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 893 * @retval EXTI RCC LSE CSS Line Status. 894 */ 895 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 896 897 /** 898 * @brief Clear the RCC LSE CSS EXTI flag. 899 * @retval None. 900 */ 901 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 902 903 /** 904 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 905 * @retval None. 906 */ 907 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 908 909 #if defined(CRS) 910 911 /** 912 * @brief Enable the specified CRS interrupts. 913 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 914 * This parameter can be any combination of the following values: 915 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 916 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 917 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 918 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 919 * @retval None 920 */ 921 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 922 923 /** 924 * @brief Disable the specified CRS interrupts. 925 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 926 * This parameter can be any combination of the following values: 927 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 928 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 929 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 930 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 931 * @retval None 932 */ 933 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 934 935 /** @brief Check whether the CRS interrupt has occurred or not. 936 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 937 * This parameter can be one of the following values: 938 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 939 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 940 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 941 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 942 * @retval The new state of __INTERRUPT__ (SET or RESET). 943 */ 944 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 945 946 /** @brief Clear the CRS interrupt pending bits 947 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 948 * This parameter can be any combination of the following values: 949 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 950 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 951 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 952 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 953 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 954 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 955 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 956 */ 957 /* CRS IT Error Mask */ 958 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 959 960 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 961 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 962 { \ 963 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 964 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 965 } \ 966 else \ 967 { \ 968 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 969 } \ 970 } while(0) 971 972 /** 973 * @brief Check whether the specified CRS flag is set or not. 974 * @param __FLAG__ specifies the flag to check. 975 * This parameter can be one of the following values: 976 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 977 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 978 * @arg @ref RCC_CRS_FLAG_ERR Error 979 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 980 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 981 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 982 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 983 * @retval The new state of _FLAG_ (TRUE or FALSE). 984 */ 985 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 986 987 /** 988 * @brief Clear the CRS specified FLAG. 989 * @param __FLAG__ specifies the flag to clear. 990 * This parameter can be one of the following values: 991 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 992 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 993 * @arg @ref RCC_CRS_FLAG_ERR Error 994 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 995 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 996 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 997 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 998 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and 999 consequently RCC_CRS_FLAG_ERR 1000 * @retval None 1001 */ 1002 1003 /* CRS Flag Error Mask */ 1004 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 1005 1006 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1007 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1008 { \ 1009 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 1010 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1011 } \ 1012 else \ 1013 { \ 1014 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1015 } \ 1016 } while(0) 1017 1018 #endif /* CRS */ 1019 1020 /** 1021 * @} 1022 */ 1023 1024 #if defined(CRS) 1025 1026 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1027 * @{ 1028 */ 1029 /** 1030 * @brief Enable the oscillator clock for frequency error counter. 1031 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1032 * @retval None 1033 */ 1034 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1035 1036 /** 1037 * @brief Disable the oscillator clock for frequency error counter. 1038 * @retval None 1039 */ 1040 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1041 1042 /** 1043 * @brief Enable the automatic hardware adjustment of TRIM bits. 1044 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1045 * @retval None 1046 */ 1047 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1048 1049 /** 1050 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1051 * @retval None 1052 */ 1053 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1054 1055 /** 1056 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1057 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1058 * of the synchronization source after prescaling. It is then decreased by one in order to 1059 * reach the expected synchronization on the zero value. The formula is the following: 1060 * RELOAD = (fTARGET / fSYNC) -1 1061 * @param __FTARGET__ Target frequency (value in Hz) 1062 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1063 * @retval None 1064 */ 1065 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1066 1067 /** 1068 * @} 1069 */ 1070 1071 #endif /* CRS */ 1072 1073 /* Exported functions --------------------------------------------------------*/ 1074 /** @addtogroup RCCEx_Exported_Functions 1075 * @{ 1076 */ 1077 1078 /** @addtogroup RCCEx_Exported_Functions_Group1 1079 * @{ 1080 */ 1081 1082 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1083 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1084 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1085 void HAL_RCCEx_GetPLLClockFreq(PLL_ClocksTypeDef *PLL_Clocks); 1086 1087 /** 1088 * @} 1089 */ 1090 1091 /** @addtogroup RCCEx_Exported_Functions_Group2 1092 * @{ 1093 */ 1094 1095 HAL_StatusTypeDef HAL_RCCEx_EnablePLL(RCC_PLLInitTypeDef *PLLInit); 1096 HAL_StatusTypeDef HAL_RCCEx_DisablePLL(void); 1097 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1098 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 1099 void HAL_RCCEx_EnableLSECSS(void); 1100 void HAL_RCCEx_DisableLSECSS(void); 1101 void HAL_RCCEx_EnableLSECSS_IT(void); 1102 void HAL_RCCEx_LSECSS_IRQHandler(void); 1103 void HAL_RCCEx_LSECSS_Callback(void); 1104 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1105 void HAL_RCCEx_DisableLSCO(void); 1106 void HAL_RCCEx_EnableMSIPLLMode(void); 1107 void HAL_RCCEx_DisableMSIPLLMode(void); 1108 1109 /** 1110 * @} 1111 */ 1112 1113 #if defined(CRS) 1114 1115 /** @addtogroup RCCEx_Exported_Functions_Group3 1116 * @{ 1117 */ 1118 1119 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit); 1120 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1121 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1122 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1123 void HAL_RCCEx_CRS_IRQHandler(void); 1124 void HAL_RCCEx_CRS_SyncOkCallback(void); 1125 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1126 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1127 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1128 1129 /** 1130 * @} 1131 */ 1132 1133 #endif /* CRS */ 1134 1135 /** 1136 * @} 1137 */ 1138 1139 /* Private macros ------------------------------------------------------------*/ 1140 /** @addtogroup RCCEx_Private_Macros 1141 * @{ 1142 */ 1143 1144 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1145 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1146 #if (defined (LPUART3) || defined (LPTIM3) || defined (USB_DRD_FS)) 1147 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 1148 RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USART4 | \ 1149 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_LPUART2 | \ 1150 RCC_PERIPHCLK_LPUART3 | RCC_PERIPHCLK_I2C1 | \ 1151 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ 1152 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 | \ 1153 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_TIM15 | \ 1154 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RNG | \ 1155 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ADC) 1156 #else 1157 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 1158 RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USART4 | \ 1159 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_LPUART2 | \ 1160 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ 1161 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 1162 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_TIM15 | \ 1163 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ 1164 RCC_PERIPHCLK_ADC) 1165 #endif /* LPUART3 | LPTIM3 | USB_DRD_FS */ 1166 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != (0x00U)) && \ 1167 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == (0x00U))) 1168 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1169 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ 1170 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1171 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 1172 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 1173 1174 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1175 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1176 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1177 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 1178 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 1179 1180 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1181 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 1182 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 1183 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 1184 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)) 1185 1186 #define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \ 1187 (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ 1188 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ 1189 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI) || \ 1190 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE)) 1191 #if defined (LPUART3) 1192 #define IS_RCC_LPUART3CLKSOURCE(__SOURCE__) \ 1193 (((__SOURCE__) == RCC_LPUART3CLKSOURCE_PCLK1) || \ 1194 ((__SOURCE__) == RCC_LPUART3CLKSOURCE_SYSCLK) || \ 1195 ((__SOURCE__) == RCC_LPUART3CLKSOURCE_HSI) || \ 1196 ((__SOURCE__) == RCC_LPUART3CLKSOURCE_LSE)) 1197 #endif /* LPUART3 */ 1198 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 1199 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 1200 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ 1201 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 1202 1203 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 1204 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 1205 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ 1206 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 1207 1208 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 1209 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 1210 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK) || \ 1211 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 1212 1213 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1214 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 1215 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 1216 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1217 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 1218 1219 #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ 1220 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ 1221 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 1222 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 1223 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 1224 #if defined (LPTIM3) 1225 #define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) \ 1226 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ 1227 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 1228 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ 1229 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) 1230 #endif /* LPTIM3 */ 1231 #define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \ 1232 (((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1) || \ 1233 ((__SOURCE__) == RCC_TIM1CLKSOURCE_PLLQ)) 1234 #if defined (USB_DRD_FS) 1235 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1236 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ 1237 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI) || \ 1238 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLQ) || \ 1239 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 1240 #endif /* USB_DRD_FS */ 1241 #if defined(RCC_RNGCLKSOURCE_HSI48) 1242 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1243 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 1244 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 1245 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLQ) || \ 1246 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)) 1247 #else 1248 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1249 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 1250 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 1251 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLQ)) 1252 #endif /* RCC_CRRCR_HSI48ON */ 1253 #define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \ 1254 (((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1) || \ 1255 ((__SOURCE__) == RCC_TIM15CLKSOURCE_PLLQ)) 1256 1257 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 1258 (((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)|| \ 1259 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLP) || \ 1260 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) 1261 1262 #if defined(CRS) 1263 1264 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 1265 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1266 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 1267 1268 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1269 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1270 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1271 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1272 1273 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1274 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1275 1276 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 1277 1278 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 1279 1280 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 1281 1282 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1283 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1284 1285 #endif /* CRS */ 1286 1287 /** 1288 * @} 1289 */ 1290 1291 /** 1292 * @} 1293 */ 1294 1295 /** 1296 * @} 1297 */ 1298 1299 /** 1300 * @} 1301 */ 1302 1303 #ifdef __cplusplus 1304 } 1305 #endif 1306 1307 #endif /* __STM32U0xx_HAL_RCC_EX_H */ 1308
