1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_RCC_EX_H 21 #define __STM32H5xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief PLL2 Clock structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. 49 This parameter must be a value of @ref RCC_PLL2_Clock_Source */ 50 51 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 52 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 53 54 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 55 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 56 57 uint32_t PLL2P; /*!< PLL2P: Division factor for peripheral clock. 58 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 59 60 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 61 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 62 63 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 65 odd division factors are not allowed */ 66 67 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 68 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 69 70 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 71 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 72 73 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 74 PLL2 VCO It should be a value between 0 and 8191 */ 75 76 uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. 77 This parameter must be a value or a combination of @ref RCC_PLL2_Clock_Output */ 78 } RCC_PLL2InitTypeDef; 79 80 81 #if defined(RCC_CR_PLL3ON) 82 /** 83 * @brief PLL3 Clock structure definition 84 */ 85 typedef struct 86 { 87 uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. 88 This parameter must be a value of @ref RCC_PLL3_Clock_Source */ 89 90 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 91 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 92 93 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 94 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 95 96 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 97 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 98 99 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 100 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 101 102 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 103 This parameter must be a number between Min_Data = 1 and Max_Data = 128 104 odd division factors are not allowed */ 105 106 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 107 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 108 109 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 110 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 111 112 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 113 PLL3 VCO It should be a value between 0 and 8191 */ 114 115 uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. 116 This parameter must be a value or a combination of @ref RCC_PLL3_Clock_Output */ 117 } RCC_PLL3InitTypeDef; 118 #endif /* RCC_CR_PLL3ON */ 119 120 /** 121 * @brief RCC PLL1 Clocks structure definition 122 */ 123 typedef struct 124 { 125 uint32_t PLL1_P_Frequency; 126 uint32_t PLL1_Q_Frequency; 127 uint32_t PLL1_R_Frequency; 128 } PLL1_ClocksTypeDef; 129 130 /** 131 * @brief RCC PLL2 Clocks structure definition 132 */ 133 typedef struct 134 { 135 uint32_t PLL2_P_Frequency; 136 uint32_t PLL2_Q_Frequency; 137 uint32_t PLL2_R_Frequency; 138 } PLL2_ClocksTypeDef; 139 140 #if defined(RCC_CR_PLL3ON) 141 /** 142 * @brief RCC PLL3 Clocks structure definition 143 */ 144 typedef struct 145 { 146 uint32_t PLL3_P_Frequency; 147 uint32_t PLL3_Q_Frequency; 148 uint32_t PLL3_R_Frequency; 149 } PLL3_ClocksTypeDef; 150 #endif /* RCC_CR_PLL3ON */ 151 152 153 /** 154 * @brief RCC extended clocks structure definition 155 */ 156 typedef struct 157 { 158 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 159 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 160 161 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 162 This parameter will be used only when PLL2 is selected as kernel clock Source 163 for some peripherals */ 164 165 #if defined(RCC_CR_PLL3ON) 166 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 167 This parameter will be used only when PLL2 is selected as kernel clock Source 168 for some peripherals */ 169 #endif /* RCC_CR_PLL3ON */ 170 171 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 172 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 173 174 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 175 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 176 177 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 178 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 179 180 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 181 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 182 183 #if defined(UART4) 184 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 185 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 186 #endif /* UART4 */ 187 188 #if defined(UART5) 189 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 190 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 191 #endif /* UART5 */ 192 193 #if defined(USART6) 194 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. 195 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 196 #endif /* USART6 */ 197 198 #if defined(UART7) 199 uint32_t Uart7ClockSelection; /*!< Specifies UART7 clock source. 200 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ 201 #endif /* UART7 */ 202 203 #if defined(UART8) 204 uint32_t Uart8ClockSelection; /*!< Specifies UART8 clock source. 205 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ 206 #endif /* UART8 */ 207 208 #if defined(UART9) 209 uint32_t Uart9ClockSelection; /*!< Specifies UART9 clock source. 210 This parameter can be a value of @ref RCCEx_UART9_Clock_Source */ 211 #endif /* UART9 */ 212 213 #if defined(USART10) 214 uint32_t Usart10ClockSelection; /*!< Specifies USART10 clock source. 215 This parameter can be a value of @ref RCCEx_USART10_Clock_Source */ 216 #endif /* USART10 */ 217 218 #if defined(USART11) 219 uint32_t Usart11ClockSelection; /*!< Specifies USART11 clock source. 220 This parameter can be a value of @ref RCCEx_USART11_Clock_Source */ 221 #endif /* USART11 */ 222 223 #if defined(UART12) 224 uint32_t Uart12ClockSelection; /*!< Specifies UART12 clock source. 225 This parameter can be a value of @ref RCCEx_UART12_Clock_Source */ 226 #endif /* UART12 */ 227 228 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 229 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 230 231 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 232 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 233 234 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 235 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 236 237 #if defined(I2C3) 238 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 239 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 240 #endif /* I2C3 */ 241 242 #if defined(I2C4) 243 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 244 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 245 #endif /* I2C4 */ 246 247 uint32_t I3c1ClockSelection; /*!< Specifies I3C1 clock source. 248 This parameter can be a value of @ref RCCEx_I3C1_Clock_Source */ 249 250 #if defined(I3C2) 251 uint32_t I3c2ClockSelection; /*!< Specifies I3C2 clock source. 252 This parameter can be a value of @ref RCCEx_I3C2_Clock_Source */ 253 #endif /* I3C2*/ 254 255 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 256 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 257 258 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 259 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 260 261 #if defined(LPTIM3) 262 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 263 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 264 #endif /* LPTIM3 */ 265 266 #if defined(LPTIM4) 267 uint32_t Lptim4ClockSelection; /*!< Specifies LPTIM4 clock source. 268 This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source */ 269 #endif /* LPTIM4 */ 270 271 #if defined(LPTIM5) 272 uint32_t Lptim5ClockSelection; /*!< Specifies LPTIM5 clock source. 273 This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source */ 274 #endif /* LPTIM5 */ 275 276 #if defined(LPTIM6) 277 uint32_t Lptim6ClockSelection; /*!< Specifies LPTIM6 clock source. 278 This parameter can be a value of @ref RCCEx_LPTIM6_Clock_Source */ 279 #endif /* LPTIM6 */ 280 281 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. 282 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 283 #if defined(SAI1) 284 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 285 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 286 #endif /* SAI1*/ 287 288 #if defined(SAI2) 289 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 290 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 291 #endif /* SAI2*/ 292 293 uint32_t RngClockSelection; /*!< Specifies RNG clock source. 294 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 295 296 #if defined(SDMMC1) 297 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source. 298 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 299 #endif /* SDMMC1 */ 300 301 #if defined(SDMMC2) 302 uint32_t Sdmmc2ClockSelection; /*!< Specifies SDMMC2 clock source. 303 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ 304 #endif /* SDMMC2 */ 305 306 uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC2 and DAC interface clock source. 307 This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ 308 309 uint32_t DacLowPowerClockSelection; /*!< Specifies DAC low-power clock source used in Sample and hold mode. 310 This parameter can be a value of @ref RCCEx_DAC_Low_Power_Clock_Source */ 311 312 #if defined(OCTOSPI1) 313 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 314 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 315 #endif /* OCTOSPI1 */ 316 317 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source. 318 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 319 320 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source. 321 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 322 323 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source. 324 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 325 326 #if defined(SPI4) 327 uint32_t Spi4ClockSelection; /*!< Specifies SPI4 clock source. 328 This parameter can be a value of @ref RCCEx_SPI4_Clock_Source */ 329 #endif /* SPI4 */ 330 331 #if defined(SPI5) 332 uint32_t Spi5ClockSelection; /*!< Specifies SPI5 clock source. 333 This parameter can be a value of @ref RCCEx_SPI5_Clock_Source */ 334 #endif /* SPI5 */ 335 336 #if defined(SPI6) 337 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source. 338 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 339 #endif /* SPI6 */ 340 341 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 342 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 343 344 #if defined(CEC) 345 uint32_t CecClockSelection; /*!< Specifies CEC clock source. 346 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 347 #endif /* CEC */ 348 349 #if defined(USB_DRD_FS) 350 uint32_t UsbClockSelection; /*!< Specifies USB clock source. 351 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 352 #endif /* USB_DRD_FS */ 353 354 uint32_t TimPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 355 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 356 } RCC_PeriphCLKInitTypeDef; 357 358 #if defined(CRS) 359 360 /** 361 * @brief RCC_CRS Init structure definition 362 */ 363 typedef struct 364 { 365 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 366 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 367 368 uint32_t Source; /*!< Specifies the SYNC signal source. 369 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 370 371 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 372 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 373 374 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 375 event. It can be calculated in using macro 376 __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 377 This parameter must be a number between 0 and 0xFFFF or a value of 378 @ref RCCEx_CRS_ReloadValueDefault .*/ 379 380 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 381 This parameter must be a number between 0 and 0xFF or a value of 382 @ref RCCEx_CRS_ErrorLimitDefault */ 383 384 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 385 This parameter must be a number between 0 and 0x7F or a value of 386 @ref RCCEx_CRS_HSI48CalibrationDefault */ 387 388 } RCC_CRSInitTypeDef; 389 390 /** 391 * @brief RCC_CRS Synchronization structure definition 392 */ 393 typedef struct 394 { 395 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 396 This parameter must be a number between 0 and 0xFFFF */ 397 398 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 399 This parameter must be a number between 0 and 0x3F */ 400 401 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 402 value latched in the time of the last SYNC event. 403 This parameter must be a number between 0 and 0xFFFF */ 404 405 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 406 frequency error counter latched in the time of the last SYNC event. 407 It shows whether the actual frequency is below or above the target. 408 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection */ 409 410 } RCC_CRSSynchroInfoTypeDef; 411 412 #endif /* CRS */ 413 /** 414 * @} 415 */ 416 417 418 /* Exported constants --------------------------------------------------------*/ 419 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 420 * @{ 421 */ 422 423 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Microcontroller Clock Output Source 424 * @{ 425 */ 426 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed microcontroller clock output */ 427 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed microcontroller clock output */ 428 /** 429 * @} 430 */ 431 432 #if defined(PWR_USBSCR_OTGHSEN) 433 /** @defgroup OTGHS_CLK48_VALUE OTG_HS output clock 434 * @{ 435 */ 436 #define OTGHS_CLK48_VALUE 48000000U /*!< Value of the OTGHS_CLK48 in Hz*/ 437 /** 438 * @} 439 */ 440 #endif /* PWR_USBSCR_OTGHSEN */ 441 442 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 443 * @{ 444 */ 445 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) 446 #define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) 447 #define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) 448 #if defined(UART4) 449 #define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) 450 #endif /* UART4 */ 451 #if defined(UART5) 452 #define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) 453 #endif /* UART5 */ 454 #if defined(USART6) 455 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x00000020U) 456 #endif /* USART6 */ 457 #if defined(UART7) 458 #define RCC_PERIPHCLK_UART7 ((uint64_t)0x00000040U) 459 #endif /* UART7 */ 460 #if defined(UART8) 461 #define RCC_PERIPHCLK_UART8 ((uint64_t)0x00000080U) 462 #endif /* UART8 */ 463 #if defined(UART9) 464 #define RCC_PERIPHCLK_UART9 ((uint64_t)0x00000100U) 465 #endif /* UART9 */ 466 #if defined(USART10) 467 #define RCC_PERIPHCLK_USART10 ((uint64_t)0x00000200U) 468 #endif /* USART10 */ 469 #if defined(USART11) 470 #define RCC_PERIPHCLK_USART11 ((uint64_t)0x00000400U) 471 #endif /* USART11 */ 472 #if defined(UART12) 473 #define RCC_PERIPHCLK_UART12 ((uint64_t)0x00000800U) 474 #endif /* UART12 */ 475 #define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00001000U) 476 #define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00002000U) 477 #define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00004000U) 478 #if defined(I2C3) 479 #define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00008000U) 480 #endif /* I2C3 */ 481 #define RCC_PERIPHCLK_I3C1 ((uint64_t)0x00010000U) 482 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00020000U) 483 #define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00040000U) 484 #if defined(SAI1) 485 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00080000U) 486 #endif /* SAI1 */ 487 #if defined(SAI2) 488 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00100000U) 489 #endif /* SAI2 */ 490 #define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00200000U) 491 #define RCC_PERIPHCLK_ADC RCC_PERIPHCLK_ADCDAC 492 #define RCC_PERIPHCLK_DAC RCC_PERIPHCLK_ADCDAC 493 #if defined(SDMMC1) 494 #define RCC_PERIPHCLK_SDMMC1 ((uint64_t)0x00400000U) 495 #endif /* SDMMC1 */ 496 #if defined(SDMMC2) 497 #define RCC_PERIPHCLK_SDMMC2 ((uint64_t)0x00800000U) 498 #endif /* SDMMC2 */ 499 #define RCC_PERIPHCLK_CKPER ((uint64_t)0x01000000U) 500 #define RCC_PERIPHCLK_RTC ((uint64_t)0x02000000U) 501 #define RCC_PERIPHCLK_RNG ((uint64_t)0x04000000U) 502 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x08000000U) 503 #define RCC_PERIPHCLK_SPI2 ((uint64_t)0x10000000U) 504 #define RCC_PERIPHCLK_SPI3 ((uint64_t)0x20000000U) 505 #if defined(SPI4) 506 #define RCC_PERIPHCLK_SPI4 ((uint64_t)0x40000000U) 507 #endif /* SPI4 */ 508 #if defined(SPI5) 509 #define RCC_PERIPHCLK_SPI5 ((uint64_t)0x80000000U) 510 #endif /* SPI5 */ 511 #if defined(SPI6) 512 #define RCC_PERIPHCLK_SPI6 ((uint64_t)0x100000000U) 513 #endif /* SPI6 */ 514 #if defined(OCTOSPI1) 515 #define RCC_PERIPHCLK_OSPI ((uint64_t)0x200000000U) 516 #endif /* OCTOSPI1 */ 517 #define RCC_PERIPHCLK_FDCAN ((uint64_t)0x400000000U) 518 #if defined(CEC) 519 #define RCC_PERIPHCLK_CEC ((uint64_t)0x800000000U) 520 #endif /* CEC */ 521 #if defined(USB_DRD_FS) 522 #define RCC_PERIPHCLK_USB ((uint64_t)0x1000000000U) 523 #endif /* USB_DRD_FS */ 524 #if defined(LPTIM3) 525 #define RCC_PERIPHCLK_LPTIM3 ((uint64_t)0x2000000000U) 526 #endif /* LPTIM3 */ 527 #if defined(LPTIM4) 528 #define RCC_PERIPHCLK_LPTIM4 ((uint64_t)0x4000000000U) 529 #endif /* LPTIM4 */ 530 #if defined(LPTIM5) 531 #define RCC_PERIPHCLK_LPTIM5 ((uint64_t)0x8000000000U) 532 #endif /* LPTIM5 */ 533 #if defined(LPTIM6) 534 #define RCC_PERIPHCLK_LPTIM6 ((uint64_t)0x10000000000U) 535 #endif /* LPTIM6 */ 536 #define RCC_PERIPHCLK_DAC_LP ((uint64_t)0x20000000000U) 537 #if defined(I2C4) 538 #define RCC_PERIPHCLK_I2C4 ((uint64_t)0x40000000000U) 539 #endif /* I2C4 */ 540 #define RCC_PERIPHCLK_TIM ((uint64_t)0x80000000000U) 541 #if defined(I3C2) 542 #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) 543 #endif /* I3C2 */ 544 545 /** 546 * @} 547 */ 548 549 550 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 551 * @{ 552 */ 553 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN 554 #define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN 555 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN 556 /** 557 * @} 558 */ 559 560 #if defined(RCC_CR_PLL3ON) 561 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 562 * @{ 563 */ 564 #define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN 565 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN 566 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN 567 /** 568 * @} 569 */ 570 #endif /* RCC_CR_PLL3ON */ 571 572 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 573 * @{ 574 */ 575 #define RCC_PLL2_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 576 #define RCC_PLL2_VCIRANGE_1 RCC_PLL2CFGR_PLL2RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 577 #define RCC_PLL2_VCIRANGE_2 RCC_PLL2CFGR_PLL2RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 578 #define RCC_PLL2_VCIRANGE_3 (RCC_PLL2CFGR_PLL2RGE_0 | RCC_PLL2CFGR_PLL2RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 584 * @{ 585 */ 586 #define RCC_PLL2_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 587 #define RCC_PLL2_VCORANGE_MEDIUM RCC_PLL2CFGR_PLL2VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 588 589 /** 590 * @} 591 */ 592 593 /** @defgroup RCC_PLL2_Clock_Source RCC PLL2 Clock Source 594 * @{ 595 */ 596 #define RCC_PLL2_SOURCE_NONE (0x00000000U) 597 #define RCC_PLL2_SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 598 #define RCC_PLL2_SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 599 #define RCC_PLL2_SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) 600 /** 601 * @} 602 */ 603 604 #if defined(RCC_CR_PLL3ON) 605 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 606 * @{ 607 */ 608 #define RCC_PLL3_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 609 #define RCC_PLL3_VCIRANGE_1 RCC_PLL3CFGR_PLL3RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 610 #define RCC_PLL3_VCIRANGE_2 RCC_PLL3CFGR_PLL3RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 611 #define RCC_PLL3_VCIRANGE_3 (RCC_PLL3CFGR_PLL3RGE_0 | RCC_PLL3CFGR_PLL3RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 617 * @{ 618 */ 619 #define RCC_PLL3_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 620 #define RCC_PLL3_VCORANGE_MEDIUM RCC_PLL3CFGR_PLL3VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 621 /** 622 * @} 623 */ 624 625 /** @defgroup RCC_PLL3_Clock_Source RCC PLL3 Clock Source 626 * @{ 627 */ 628 #define RCC_PLL3_SOURCE_NONE (0x00000000U) 629 #define RCC_PLL3_SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 630 #define RCC_PLL3_SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 631 #define RCC_PLL3_SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) 632 /** 633 * @} 634 */ 635 #endif /* RCC_CR_PLL3ON */ 636 637 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 638 * @{ 639 */ 640 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 641 #define RCC_USART1CLKSOURCE_PLL2Q RCC_CCIPR1_USART1SEL_0 642 #if defined(RCC_CR_PLL3ON) 643 #define RCC_USART1CLKSOURCE_PLL3Q RCC_CCIPR1_USART1SEL_1 644 #endif /* RCC_CR_PLL3ON */ 645 #define RCC_USART1CLKSOURCE_HSI (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 646 #define RCC_USART1CLKSOURCE_CSI RCC_CCIPR1_USART1SEL_2 647 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_2) 648 /** 649 * @} 650 */ 651 652 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 653 * @{ 654 */ 655 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 656 #define RCC_USART2CLKSOURCE_PLL2Q RCC_CCIPR1_USART2SEL_0 657 #if defined(RCC_CR_PLL3ON) 658 #define RCC_USART2CLKSOURCE_PLL3Q RCC_CCIPR1_USART2SEL_1 659 #endif /* RCC_CR_PLL3ON */ 660 #define RCC_USART2CLKSOURCE_HSI (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 661 #define RCC_USART2CLKSOURCE_CSI RCC_CCIPR1_USART2SEL_2 662 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_2) 663 /** 664 * @} 665 */ 666 667 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 668 * @{ 669 */ 670 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 671 #define RCC_USART3CLKSOURCE_PLL2Q RCC_CCIPR1_USART3SEL_0 672 #if defined(RCC_CR_PLL3ON) 673 #define RCC_USART3CLKSOURCE_PLL3Q RCC_CCIPR1_USART3SEL_1 674 #endif /* RCC_CR_PLL3ON */ 675 #define RCC_USART3CLKSOURCE_HSI (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) 676 #define RCC_USART3CLKSOURCE_CSI RCC_CCIPR1_USART3SEL_2 677 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_2) 678 /** 679 * @} 680 */ 681 682 #if defined(UART4) 683 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 684 * @{ 685 */ 686 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 687 #define RCC_UART4CLKSOURCE_PLL2Q RCC_CCIPR1_UART4SEL_0 688 #define RCC_UART4CLKSOURCE_PLL3Q RCC_CCIPR1_UART4SEL_1 689 #define RCC_UART4CLKSOURCE_HSI (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) 690 #define RCC_UART4CLKSOURCE_CSI RCC_CCIPR1_UART4SEL_2 691 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_2) 692 /** 693 * @} 694 */ 695 #endif /* UART4 */ 696 697 #if defined(UART5) 698 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 699 * @{ 700 */ 701 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 702 #define RCC_UART5CLKSOURCE_PLL2Q RCC_CCIPR1_UART5SEL_0 703 #define RCC_UART5CLKSOURCE_PLL3Q RCC_CCIPR1_UART5SEL_1 704 #define RCC_UART5CLKSOURCE_HSI (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) 705 #define RCC_UART5CLKSOURCE_CSI RCC_CCIPR1_UART5SEL_2 706 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_2) 707 /** 708 * @} 709 */ 710 #endif /* UART5 */ 711 712 #if defined(USART6) 713 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 714 * @{ 715 */ 716 #define RCC_USART6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 717 #define RCC_USART6CLKSOURCE_PLL2Q RCC_CCIPR1_USART6SEL_0 718 #define RCC_USART6CLKSOURCE_PLL3Q RCC_CCIPR1_USART6SEL_1 719 #define RCC_USART6CLKSOURCE_HSI (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_1) 720 #define RCC_USART6CLKSOURCE_CSI RCC_CCIPR1_USART6SEL_2 721 #define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_2) 722 /** 723 * @} 724 */ 725 #endif /* USART6 */ 726 727 #if defined(UART7) 728 /** @defgroup RCCEx_UART7_Clock_Source UART7 Clock Source 729 * @{ 730 */ 731 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 732 #define RCC_UART7CLKSOURCE_PLL2Q RCC_CCIPR1_UART7SEL_0 733 #define RCC_UART7CLKSOURCE_PLL3Q RCC_CCIPR1_UART7SEL_1 734 #define RCC_UART7CLKSOURCE_HSI (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_1) 735 #define RCC_UART7CLKSOURCE_CSI RCC_CCIPR1_UART7SEL_2 736 #define RCC_UART7CLKSOURCE_LSE (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_2) 737 /** 738 * @} 739 */ 740 #endif /* UART7 */ 741 742 #if defined(UART8) 743 /** @defgroup RCCEx_UART8_Clock_Source UART8 Clock Source 744 * @{ 745 */ 746 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 747 #define RCC_UART8CLKSOURCE_PLL2Q RCC_CCIPR1_UART8SEL_0 748 #define RCC_UART8CLKSOURCE_PLL3Q RCC_CCIPR1_UART8SEL_1 749 #define RCC_UART8CLKSOURCE_HSI (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_1) 750 #define RCC_UART8CLKSOURCE_CSI RCC_CCIPR1_UART8SEL_2 751 #define RCC_UART8CLKSOURCE_LSE (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_2) 752 /** 753 * @} 754 */ 755 #endif /* UART8 */ 756 757 #if defined(UART9) 758 /** @defgroup RCCEx_UART9_Clock_Source UART9 Clock Source 759 * @{ 760 */ 761 #define RCC_UART9CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 762 #define RCC_UART9CLKSOURCE_PLL2Q RCC_CCIPR1_UART9SEL_0 763 #define RCC_UART9CLKSOURCE_PLL3Q RCC_CCIPR1_UART9SEL_1 764 #define RCC_UART9CLKSOURCE_HSI (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_1) 765 #define RCC_UART9CLKSOURCE_CSI RCC_CCIPR1_UART9SEL_2 766 #define RCC_UART9CLKSOURCE_LSE (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_2) 767 /** 768 * @} 769 */ 770 #endif /* UART9 */ 771 772 #if defined(USART10) 773 /** @defgroup RCCEx_USART10_Clock_Source USART10 Clock Source 774 * @{ 775 */ 776 #define RCC_USART10CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 777 #define RCC_USART10CLKSOURCE_PLL2Q RCC_CCIPR1_USART10SEL_0 778 #define RCC_USART10CLKSOURCE_PLL3Q RCC_CCIPR1_USART10SEL_1 779 #define RCC_USART10CLKSOURCE_HSI (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_1) 780 #define RCC_USART10CLKSOURCE_CSI RCC_CCIPR1_USART10SEL_2 781 #define RCC_USART10CLKSOURCE_LSE (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_2) 782 /** 783 * @} 784 */ 785 #endif /* USART10 */ 786 787 #if defined(USART11) 788 /** @defgroup RCCEx_USART11_Clock_Source USART11 Clock Source 789 * @{ 790 */ 791 #define RCC_USART11CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 792 #define RCC_USART11CLKSOURCE_PLL2Q RCC_CCIPR2_USART11SEL_0 793 #define RCC_USART11CLKSOURCE_PLL3Q RCC_CCIPR2_USART11SEL_1 794 #define RCC_USART11CLKSOURCE_HSI (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_1) 795 #define RCC_USART11CLKSOURCE_CSI RCC_CCIPR2_USART11SEL_2 796 #define RCC_USART11CLKSOURCE_LSE (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_2) 797 /** 798 * @} 799 */ 800 #endif /* USART11 */ 801 802 #if defined(UART12) 803 /** @defgroup RCCEx_UART12_Clock_Source UART12 Clock Source 804 * @{ 805 */ 806 #define RCC_UART12CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 807 #define RCC_UART12CLKSOURCE_PLL2Q RCC_CCIPR2_UART12SEL_0 808 #define RCC_UART12CLKSOURCE_PLL3Q RCC_CCIPR2_UART12SEL_1 809 #define RCC_UART12CLKSOURCE_HSI (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_1) 810 #define RCC_UART12CLKSOURCE_CSI RCC_CCIPR2_UART12SEL_2 811 #define RCC_UART12CLKSOURCE_LSE (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_2) 812 /** 813 * @} 814 */ 815 #endif /* UART12 */ 816 817 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 818 * @{ 819 */ 820 #define RCC_LPUART1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 821 #define RCC_LPUART1CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 822 #if defined(RCC_CR_PLL3ON) 823 #define RCC_LPUART1CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 824 #endif /* RCC_CR_PLL3ON */ 825 #define RCC_LPUART1CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 826 #define RCC_LPUART1CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 827 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) 828 829 /** 830 * @} 831 */ 832 833 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 834 * @{ 835 */ 836 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 837 #if defined(RCC_CR_PLL3ON) 838 #define RCC_I2C1CLKSOURCE_PLL3R RCC_CCIPR4_I2C1SEL_0 839 #else 840 #define RCC_I2C1CLKSOURCE_PLL2R RCC_CCIPR4_I2C1SEL_0 841 #endif /* RCC_CR_PLL3ON */ 842 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR4_I2C1SEL_1 843 #define RCC_I2C1CLKSOURCE_CSI (RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0) 844 /** 845 * @} 846 */ 847 848 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 849 * @{ 850 */ 851 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 852 #if defined(RCC_CR_PLL3ON) 853 #define RCC_I2C2CLKSOURCE_PLL3R RCC_CCIPR4_I2C2SEL_0 854 #else 855 #define RCC_I2C2CLKSOURCE_PLL2R RCC_CCIPR4_I2C2SEL_0 856 #endif /* RCC_CR_PLL3ON */ 857 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR4_I2C2SEL_1 858 #define RCC_I2C2CLKSOURCE_CSI (RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0) 859 /** 860 * @} 861 */ 862 863 #if defined(I2C3) 864 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 865 * @{ 866 */ 867 #define RCC_I2C3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 868 #define RCC_I2C3CLKSOURCE_PLL3R RCC_CCIPR4_I2C3SEL_0 869 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR4_I2C3SEL_1 870 #define RCC_I2C3CLKSOURCE_CSI (RCC_CCIPR4_I2C3SEL_0 | RCC_CCIPR4_I2C3SEL_1) 871 /** 872 * @} 873 */ 874 #endif /* I2C3 */ 875 876 #if defined(I2C4) 877 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 878 * @{ 879 */ 880 #define RCC_I2C4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 881 #define RCC_I2C4CLKSOURCE_PLL3R RCC_CCIPR4_I2C4SEL_0 882 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR4_I2C4SEL_1 883 #define RCC_I2C4CLKSOURCE_CSI (RCC_CCIPR4_I2C4SEL_0 | RCC_CCIPR4_I2C4SEL_1) 884 /** 885 * @} 886 */ 887 #endif /* I2C4 */ 888 889 /** @defgroup RCCEx_I3C1_Clock_Source I3C1 Clock Source 890 * @{ 891 */ 892 #define RCC_I3C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 893 #if defined(RCC_CR_PLL3ON) 894 #define RCC_I3C1CLKSOURCE_PLL3R RCC_CCIPR4_I3C1SEL_0 895 #else 896 #define RCC_I3C1CLKSOURCE_PLL2R RCC_CCIPR4_I3C1SEL_0 897 #endif /* RCC_CR_PLL3ON */ 898 #define RCC_I3C1CLKSOURCE_HSI RCC_CCIPR4_I3C1SEL_1 899 /** 900 * @} 901 */ 902 903 #if defined(I3C2) 904 /** @defgroup RCCEx_I3C2_Clock_Source I3C2 Clock Source 905 * @{ 906 */ 907 #define RCC_I3C2CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 908 #if defined(RCC_CR_PLL3ON) 909 #define RCC_I3C2CLKSOURCE_PLL3R RCC_CCIPR4_I3C2SEL_0 910 #else 911 #define RCC_I3C2CLKSOURCE_PLL2R RCC_CCIPR4_I3C2SEL_0 912 #endif /* RCC_CR_PLL3ON */ 913 #define RCC_I3C2CLKSOURCE_HSI RCC_CCIPR4_I3C2SEL_1 914 /** 915 * @} 916 */ 917 #endif /* I3C2 */ 918 919 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 920 * @{ 921 */ 922 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) 923 #define RCC_RNGCLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 924 #define RCC_RNGCLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 925 #define RCC_RNGCLKSOURCE_LSI (RCC_CCIPR5_RNGSEL_0 | RCC_CCIPR5_RNGSEL_1) 926 /** 927 * @} 928 */ 929 930 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 931 * @{ 932 */ 933 #define RCC_SPI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 934 #define RCC_SPI1CLKSOURCE_PLL2P RCC_CCIPR3_SPI1SEL_0 935 #if defined(RCC_CR_PLL3ON) 936 #define RCC_SPI1CLKSOURCE_PLL3P RCC_CCIPR3_SPI1SEL_1 937 #endif /* RCC_CR_PLL3ON */ 938 #define RCC_SPI1CLKSOURCE_PIN (RCC_CCIPR3_SPI1SEL_0 | RCC_CCIPR3_SPI1SEL_1) 939 #define RCC_SPI1CLKSOURCE_CLKP RCC_CCIPR3_SPI1SEL_2 940 /** 941 * @} 942 */ 943 944 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 945 * @{ 946 */ 947 #define RCC_SPI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 948 #define RCC_SPI2CLKSOURCE_PLL2P RCC_CCIPR3_SPI2SEL_0 949 #if defined(RCC_CR_PLL3ON) 950 #define RCC_SPI2CLKSOURCE_PLL3P RCC_CCIPR3_SPI2SEL_1 951 #endif /* RCC_CR_PLL3ON */ 952 #define RCC_SPI2CLKSOURCE_PIN (RCC_CCIPR3_SPI2SEL_0 | RCC_CCIPR3_SPI2SEL_1) 953 #define RCC_SPI2CLKSOURCE_CLKP RCC_CCIPR3_SPI2SEL_2 954 /** 955 * @} 956 */ 957 958 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 959 * @{ 960 */ 961 #define RCC_SPI3CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 962 #define RCC_SPI3CLKSOURCE_PLL2P RCC_CCIPR3_SPI3SEL_0 963 #if defined(RCC_CR_PLL3ON) 964 #define RCC_SPI3CLKSOURCE_PLL3P RCC_CCIPR3_SPI3SEL_1 965 #endif /* RCC_CR_PLL3ON */ 966 #define RCC_SPI3CLKSOURCE_PIN (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) 967 #define RCC_SPI3CLKSOURCE_CLKP RCC_CCIPR3_SPI3SEL_2 968 /** 969 * @} 970 */ 971 972 #if defined(SPI4) 973 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 974 * @{ 975 */ 976 #define RCC_SPI4CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 977 #define RCC_SPI4CLKSOURCE_PLL2Q RCC_CCIPR3_SPI4SEL_0 978 #define RCC_SPI4CLKSOURCE_PLL3Q RCC_CCIPR3_SPI4SEL_1 979 #define RCC_SPI4CLKSOURCE_HSI (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_1) 980 #define RCC_SPI4CLKSOURCE_CSI RCC_CCIPR3_SPI4SEL_2 981 #define RCC_SPI4CLKSOURCE_HSE (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_2) 982 /** 983 * @} 984 */ 985 #endif /* SPI4 */ 986 987 #if defined(SPI5) 988 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 989 * @{ 990 */ 991 #define RCC_SPI5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 992 #define RCC_SPI5CLKSOURCE_PLL2Q RCC_CCIPR3_SPI5SEL_0 993 #define RCC_SPI5CLKSOURCE_PLL3Q RCC_CCIPR3_SPI5SEL_1 994 #define RCC_SPI5CLKSOURCE_HSI (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_1) 995 #define RCC_SPI5CLKSOURCE_CSI RCC_CCIPR3_SPI5SEL_2 996 #define RCC_SPI5CLKSOURCE_HSE (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_2) 997 /** 998 * @} 999 */ 1000 #endif /* SPI5 */ 1001 1002 #if defined(SPI6) 1003 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 1004 * @{ 1005 */ 1006 #define RCC_SPI6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 1007 #define RCC_SPI6CLKSOURCE_PLL2Q RCC_CCIPR3_SPI6SEL_0 1008 #define RCC_SPI6CLKSOURCE_PLL3Q RCC_CCIPR3_SPI6SEL_1 1009 #define RCC_SPI6CLKSOURCE_HSI (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_1) 1010 #define RCC_SPI6CLKSOURCE_CSI RCC_CCIPR3_SPI6SEL_2 1011 #define RCC_SPI6CLKSOURCE_HSE (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_2) 1012 /** 1013 * @} 1014 */ 1015 #endif /* SPI6 */ 1016 1017 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 1018 * @{ 1019 */ 1020 #define RCC_LPTIM1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1021 #define RCC_LPTIM1CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM1SEL_0 1022 #if defined(RCC_CR_PLL3ON) 1023 #define RCC_LPTIM1CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM1SEL_1 1024 #endif /* RCC_CR_PLL3ON */ 1025 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) 1026 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL_2 1027 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) 1028 /** 1029 * @} 1030 */ 1031 1032 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 1033 * @{ 1034 */ 1035 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 1036 #define RCC_LPTIM2CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM2SEL_0 1037 #if defined(RCC_CR_PLL3ON) 1038 #define RCC_LPTIM2CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM2SEL_1 1039 #endif /* RCC_CR_PLL3ON */ 1040 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) 1041 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR2_LPTIM2SEL_2 1042 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) 1043 /** 1044 * @} 1045 */ 1046 1047 #if defined(LPTIM3) 1048 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 1049 * @{ 1050 */ 1051 #define RCC_LPTIM3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1052 #define RCC_LPTIM3CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM3SEL_0 1053 #define RCC_LPTIM3CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM3SEL_1 1054 #define RCC_LPTIM3CLKSOURCE_LSE (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) 1055 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR2_LPTIM3SEL_2 1056 #define RCC_LPTIM3CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) 1057 /** 1058 * @} 1059 */ 1060 #endif /* LPTIM3 */ 1061 1062 #if defined(LPTIM4) 1063 /** @defgroup RCCEx_LPTIM4_Clock_Source LPTIM4 Clock Source 1064 * @{ 1065 */ 1066 #define RCC_LPTIM4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1067 #define RCC_LPTIM4CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM4SEL_0 1068 #define RCC_LPTIM4CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM4SEL_1 1069 #define RCC_LPTIM4CLKSOURCE_LSE (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) 1070 #define RCC_LPTIM4CLKSOURCE_LSI RCC_CCIPR2_LPTIM4SEL_2 1071 #define RCC_LPTIM4CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) 1072 /** 1073 * @} 1074 */ 1075 #endif /* LPTIM4 */ 1076 1077 #if defined(LPTIM5) 1078 /** @defgroup RCCEx_LPTIM5_Clock_Source LPTIM5 Clock Source 1079 * @{ 1080 */ 1081 #define RCC_LPTIM5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1082 #define RCC_LPTIM5CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM5SEL_0 1083 #define RCC_LPTIM5CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM5SEL_1 1084 #define RCC_LPTIM5CLKSOURCE_LSE (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) 1085 #define RCC_LPTIM5CLKSOURCE_LSI RCC_CCIPR2_LPTIM5SEL_2 1086 #define RCC_LPTIM5CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) 1087 /** 1088 * @} 1089 */ 1090 #endif /* LPTIM5 */ 1091 1092 #if defined(LPTIM6) 1093 /** @defgroup RCCEx_LPTIM6_Clock_Source LPTIM6 Clock Source 1094 * @{ 1095 */ 1096 #define RCC_LPTIM6CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1097 #define RCC_LPTIM6CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM6SEL_0 1098 #define RCC_LPTIM6CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM6SEL_1 1099 #define RCC_LPTIM6CLKSOURCE_LSE (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) 1100 #define RCC_LPTIM6CLKSOURCE_LSI RCC_CCIPR2_LPTIM6SEL_2 1101 #define RCC_LPTIM6CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) 1102 /** 1103 * @} 1104 */ 1105 #endif /* LPTIM6 */ 1106 1107 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 1108 * @{ 1109 */ 1110 #define RCC_FDCANCLKSOURCE_HSE ((uint32_t)0x00000000U) 1111 #define RCC_FDCANCLKSOURCE_PLL1Q RCC_CCIPR5_FDCANSEL_0 1112 #define RCC_FDCANCLKSOURCE_PLL2Q RCC_CCIPR5_FDCANSEL_1 1113 /** 1114 * @} 1115 */ 1116 1117 /** @defgroup RCCEx_ADCDAC_Clock_Source ADCDAC Kernel Clock Source 1118 * @{ 1119 */ 1120 #define RCC_ADCDACCLKSOURCE_HCLK ((uint32_t)0x00000000U) 1121 #define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 1122 #define RCC_ADCDACCLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 1123 #define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_1 | RCC_CCIPR5_ADCDACSEL_0) 1124 #define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 1125 #define RCC_ADCDACCLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_2 | RCC_CCIPR5_ADCDACSEL_0) 1126 1127 /** 1128 * @} 1129 */ 1130 1131 /** @defgroup RCCEx_DAC_Low_Power_Clock_Source DAC Low Power Kernel Clock Source 1132 * @{ 1133 */ 1134 #define RCC_DACLPCLKSOURCE_LSE ((uint32_t)0x00000000U) 1135 #define RCC_DACLPCLKSOURCE_LSI RCC_CCIPR5_DACSEL 1136 /** 1137 * @} 1138 */ 1139 1140 #if defined(SAI1) 1141 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 1142 * @{ 1143 */ 1144 #define RCC_SAI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1145 #define RCC_SAI1CLKSOURCE_PLL2P RCC_CCIPR5_SAI1SEL_0 1146 #define RCC_SAI1CLKSOURCE_PLL3P RCC_CCIPR5_SAI1SEL_1 1147 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) 1148 #define RCC_SAI1CLKSOURCE_CLKP RCC_CCIPR5_SAI1SEL_2 1149 /** 1150 * @} 1151 */ 1152 #endif /* SAI1 */ 1153 1154 #if defined(SAI2) 1155 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 1156 * @{ 1157 */ 1158 #define RCC_SAI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1159 #define RCC_SAI2CLKSOURCE_PLL2P RCC_CCIPR5_SAI2SEL_0 1160 #define RCC_SAI2CLKSOURCE_PLL3P RCC_CCIPR5_SAI2SEL_1 1161 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) 1162 #define RCC_SAI2CLKSOURCE_CLKP RCC_CCIPR5_SAI2SEL_2 1163 /** 1164 * @} 1165 */ 1166 #endif /* SAI2 */ 1167 1168 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1169 * @{ 1170 */ 1171 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1172 #define RCC_CLKPSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 1173 #define RCC_CLKPSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 1174 /** 1175 * @} 1176 */ 1177 1178 #if defined(SDMMC1) 1179 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 1180 * @{ 1181 */ 1182 #define RCC_SDMMC1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1183 #define RCC_SDMMC1CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC1SEL 1184 /** 1185 * @} 1186 */ 1187 #endif /* SDMMC1 */ 1188 1189 #if defined(SDMMC2) 1190 /** @defgroup RCCEx_SDMMC2_Clock_Source SDMMC2 Clock Source 1191 * @{ 1192 */ 1193 #define RCC_SDMMC2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1194 #define RCC_SDMMC2CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC2SEL 1195 /** 1196 * @} 1197 */ 1198 #endif /* SDMMC2 */ 1199 1200 #if defined(OCTOSPI1) 1201 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 1202 * @{ 1203 */ 1204 #define RCC_OSPICLKSOURCE_HCLK ((uint32_t)0x00000000U) 1205 #define RCC_OSPICLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 1206 #define RCC_OSPICLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 1207 #define RCC_OSPICLKSOURCE_CLKP (RCC_CCIPR4_OCTOSPISEL_0 | RCC_CCIPR4_OCTOSPISEL_1) 1208 /** 1209 * @} 1210 */ 1211 #endif /* OCTOSPI1 */ 1212 1213 #if defined(CEC) 1214 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 1215 * @{ 1216 */ 1217 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) 1218 #define RCC_CECCLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 1219 #define RCC_CECCLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 1220 /** 1221 * @} 1222 */ 1223 #endif /* CEC */ 1224 1225 #if defined(USB_DRD_FS) 1226 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 1227 * @{ 1228 */ 1229 #define RCC_USBCLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 1230 #if defined(RCC_CR_PLL3ON) 1231 #define RCC_USBCLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 1232 #else 1233 #define RCC_USBCLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 1234 #endif /* RCC_CR_PLL3ON */ 1235 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR4_USBSEL 1236 /** 1237 * @} 1238 */ 1239 #endif /* USB_DRD_FS */ 1240 1241 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1242 * @{ 1243 */ 1244 #define RCC_TIMPRES_DEACTIVATED (0x00000000U) 1245 #define RCC_TIMPRES_ACTIVATED RCC_CFGR1_TIMPRE 1246 1247 /** 1248 * @} 1249 */ 1250 1251 #if defined(CRS) 1252 1253 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1254 * @{ 1255 */ 1256 #define RCC_CRS_NONE ((uint32_t)0x00000000U) 1257 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) 1258 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) 1259 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) 1260 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) 1261 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) 1262 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) 1263 /** 1264 * @} 1265 */ 1266 1267 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1268 * @{ 1269 */ 1270 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ 1271 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1272 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 1273 /** 1274 * @} 1275 */ 1276 1277 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1278 * @{ 1279 */ 1280 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ 1281 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1282 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1283 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1284 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1285 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1286 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1287 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1288 /** 1289 * @} 1290 */ 1291 1292 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1293 * @{ 1294 */ 1295 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ 1296 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1297 /** 1298 * @} 1299 */ 1300 1301 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1302 * @{ 1303 */ 1304 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1305 to a target frequency of 48 MHz and a synchronization 1306 signal frequency of 1 kHz (SOF signal from USB). */ 1307 /** 1308 * @} 1309 */ 1310 1311 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1312 * @{ 1313 */ 1314 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ 1315 /** 1316 * @} 1317 */ 1318 1319 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1320 * @{ 1321 */ 1322 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the 1323 middle of the trimming interval. The trimming step 1324 is around 67 kHz between two consecutive TRIM 1325 steps. A higher TRIM value corresponds to a higher 1326 output frequency */ 1327 /** 1328 * @} 1329 */ 1330 1331 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1332 * @{ 1333 */ 1334 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1335 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1336 /** 1337 * @} 1338 */ 1339 1340 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1341 * @{ 1342 */ 1343 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1344 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1345 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1346 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1347 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1348 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1349 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1355 * @{ 1356 */ 1357 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1358 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1359 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1360 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1361 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1362 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1363 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1364 /** 1365 * @} 1366 */ 1367 1368 #endif /* CRS */ 1369 1370 /** 1371 * @} 1372 */ 1373 1374 /* Exported macros -----------------------------------------------------------*/ 1375 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1376 * @{ 1377 */ 1378 1379 /** @brief Macros to enable or disable the HSI and CSI divided clock for Timers 12, 15 and LPTimer2 input capture. 1380 * @note HSI and CSI clocks without division are available when TIMIC is enabled 1381 * @retval None 1382 */ 1383 #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ 1384 #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ 1385 1386 1387 /** @brief Macro to configure the PLL2 clock source. 1388 * @note This function must be used only when all PLL2 is disabled. 1389 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1390 * This parameter can be one of the following values: 1391 * @arg RCC_PLL2_SOURCE_NONE: No oscillator clock selected as PLL2 clock entry 1392 * @arg RCC_PLL2_SOURCE_CSI: CSI oscillator clock selected as PLL2 clock entry 1393 * @arg RCC_PLL2_SOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry 1394 * @arg RCC_PLL2_SOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry 1395 * 1396 */ 1397 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, \ 1398 (__PLL2SOURCE__)) 1399 1400 /** @brief Macro to get the oscillator used as PLL2 clock source. 1401 * @retval The oscillator used as PLL2 clock source. The returned value can be one 1402 * of the following: 1403 * - RCC_PLL2_SOURCE_NONE: No oscillator is used as PLL clock source. 1404 * - RCC_PLL2_SOURCE_CSI: CSI oscillator is used as PLL clock source. 1405 * - RCC_PLL2_SOURCE_HSI: HSI oscillator is used as PLL clock source. 1406 * - RCC_PLL2_SOURCE_HSE: HSE oscillator is used as PLL clock source. 1407 */ 1408 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) 1409 1410 /** 1411 * @brief Macro to configures the PLL2 source, multiplication and division factors. 1412 * @note This function must be used only when PLL2 is disabled. 1413 * 1414 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1415 * This parameter can be one of the following values: 1416 * @arg @ref RCC_PLL2_SOURCE_NONE No clock selected as PLL2 clock entry 1417 * @arg @ref RCC_PLL2_SOURCE_CSI CSI oscillator clock selected as PLL2 clock entry 1418 * @arg @ref RCC_PLL2_SOURCE_HSI HSI oscillator clock selected as PLL2 clock entry 1419 * @arg @ref RCC_PLL2_SOURCE_HSE HSE oscillator clock selected as PLL2 clock entry 1420 * 1421 * @param __PLL2M__ specifies the division factor of PLL2 input clock. 1422 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1423 * 1424 * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock 1425 * This parameter must be a number between 4 and 512. 1426 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1427 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1428 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1429 * 1430 * @param __PLL2P__: specifies the division factor for peripheral kernel clocks 1431 * This parameter must be a number between 1 and 128 1432 * 1433 * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks 1434 * This parameter must be a number between 1 and 128 1435 * 1436 * @param __PLL2R__: specifies the division factor for peripheral kernel clocks 1437 * This parameter must be a number between 1 and 128 1438 * 1439 * @retval None 1440 */ 1441 #define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ 1442 do{ \ 1443 MODIFY_REG(RCC->PLL2CFGR, (RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M), \ 1444 ((__PLL2SOURCE__) << RCC_PLL2CFGR_PLL2SRC_Pos) | ((__PLL2M__) << RCC_PLL2CFGR_PLL2M_Pos)); \ 1445 WRITE_REG(RCC->PLL2DIVR , ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | \ 1446 ((((__PLL2P__) - 1U) << RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) | \ 1447 ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR_PLL2Q_Pos) & RCC_PLL2DIVR_PLL2Q) | \ 1448 ((((__PLL2R__) - 1U) << RCC_PLL2DIVR_PLL2R_Pos) & RCC_PLL2DIVR_PLL2R))); \ 1449 } while(0) 1450 /** 1451 * @brief Macro to configure the PLL2 clock multiplication factor N. 1452 * 1453 * @note This function must be used only when the PLL2 is disabled. 1454 * @note PLL2 clock source is independent from the main PLL and is configured through 1455 * __HAL_RCC_PLL2_CONFIG() macro. 1456 * 1457 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock. 1458 * This parameter must be a number between 4 and 512. 1459 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1460 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1461 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1462 * 1463 * @retval None 1464 */ 1465 #define __HAL_RCC_PLL2_MULN_CONFIG(__PLL2N__) \ 1466 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos) 1467 1468 /** @brief Macro to configure the PLL2 input clock division factor M. 1469 * 1470 * @note This function must be used only when the PLL2 is disabled. 1471 * @note PLL2 clock source is independent from the main PLL and is configured through 1472 * __HAL_RCC_PLL2_CONFIG() macro. 1473 * 1474 * @param __PLL2M__ specifies the division factor for PLL2 clock. 1475 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1476 * In order to save power when PLL2 is not used, the value of PLL2M must be set to 0. 1477 * 1478 * @retval None 1479 */ 1480 #define __HAL_RCC_PLL2_DIVM_CONFIG(__PLL2M__) \ 1481 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos) 1482 1483 /** @brief Macro to configure the PLL2 clock division factor P. 1484 * 1485 * @note This function must be used only when the PLL2 is disabled. 1486 * @note PLL2 clock source is independent from the main PLL and is configured through 1487 * __HAL_RCC_PLL2_CONFIG() macro. 1488 * 1489 * @param __PLL2P__ specifies the division factor for PLL2 output P clock. 1490 * This parameter must be a number in the range (1 to 128). 1491 * Use to set PLL2 output P clock frequency = f(PLL2) / PLL2P 1492 * 1493 * @retval None 1494 */ 1495 #define __HAL_RCC_PLL2_DIVP_CONFIG(__PLL2P__) \ 1496 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, ((__PLL2P__) - 1U) << RCC_PLL2DIVR_P2_Pos) 1497 1498 /** @brief Macro to configure the PLL2 clock division factor Q. 1499 * 1500 * @note This function must be used only when the PLL2 is disabled. 1501 * @note PLL2 clock source is independent from the main PLL and is configured through 1502 * __HAL_RCC_PLL2_CONFIG() macro. 1503 * 1504 * @param __PLL2Q__ specifies the division factor for PLL2 output Q clock. 1505 * This parameter must be a number in the range (1 to 128). 1506 * Use to set PLL2 output Q clock frequency = f(PLL2) / PLL2Q 1507 * 1508 * @retval None 1509 */ 1510 #define __HAL_RCC_PLL2_DIVQ_CONFIG(__PLL2Q__) \ 1511 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, ((__PLL2Q__) - 1U) << RCC_PLL2DIVR_Q2_Pos) 1512 1513 /** @brief Macro to configure the PLL2 clock division factor R. 1514 * 1515 * @note This function must be used only when the PLL2 is disabled. 1516 * @note PLL2 clock source is independent from the main PLL and is configured through 1517 * __HAL_RCC_PLL2_CONFIG() macro. 1518 * 1519 * @param __PLL2R__ specifies the division factor for PLL2 output R clock. 1520 * This parameter must be a number in the range (1 to 128). 1521 * Use to set PLL2 output R clock frequency = f(PLL2) / PLL2R 1522 * 1523 * @retval None 1524 */ 1525 #define __HAL_RCC_PLL2_DIVR_CONFIG(__PLL2R__) \ 1526 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, ((__PLL2R__) - 1U) << RCC_PLL2DIVR_R2_Pos) 1527 1528 /** @brief Macros to enable or disable the PLL2. 1529 * @note After enabling PLL2, the application software should wait on 1530 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1531 * be used as kernel clock source. 1532 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1533 * @retval None 1534 */ 1535 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1536 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1537 1538 /** 1539 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1540 * @note Enabling/disabling those clocks can be done at any time without the need to stop the PLL2, 1541 * This is mainly used to save Power. 1542 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1543 * This parameter can be one or a combination of the following values: 1544 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1545 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1546 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1547 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1548 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1549 * @retval None 1550 */ 1551 #define __HAL_RCC_PLL2_CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1552 #define __HAL_RCC_PLL2_CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1553 1554 /** 1555 * @brief Macro to get the PLL2 clock output enable status. 1556 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1557 * This parameter can be one or a combination of the following values: 1558 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1559 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1560 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1561 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1562 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1563 * @retval SET / RESET 1564 */ 1565 #define __HAL_RCC_GET_PLL2_CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1566 1567 /** 1568 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1569 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL2 1570 * @retval None 1571 */ 1572 #define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1573 #define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1574 1575 /** 1576 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1577 * 1578 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1579 * 1580 * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1581 * It should be a value between 0 and 8191 1582 * @note Warning: the software has to set correctly these bits to insure that the VCO 1583 * output frequency is between its valid frequency range, which is: 1584 * 192 to 836 MHz if PLL2VCOSEL = 0 1585 * 150 to 420 MHz if PLL2VCOSEL = 1. 1586 * 1587 * @retval None 1588 */ 1589 #define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, \ 1590 (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) 1591 1592 /** @brief Macro to select the PLL2 reference frequency range. 1593 * @param __PLL2VCIRange__: specifies the PLL2 input frequency range 1594 * This parameter can be one of the following values: 1595 * @arg RCC_PLL2_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1596 * @arg RCC_PLL2_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1597 * @arg RCC_PLL2_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1598 * @arg RCC_PLL2_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1599 * @retval None 1600 */ 1601 #define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ 1602 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) 1603 1604 /** @brief Macro to select the PLL2 reference frequency range. 1605 * @param __RCC_PLL2VCORange__: specifies the PLL2 output frequency range 1606 * This parameter can be one of the following values: 1607 * @arg RCC_PLL2_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 1608 * @arg RCC_PLL2_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 1609 * 1610 * @retval None 1611 */ 1612 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1613 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1614 1615 #if defined(RCC_CR_PLL3ON) 1616 /** @brief Macro to configure the PLL3 clock source. 1617 * @note This function must be used only when all PLL3 is disabled. 1618 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1619 * This parameter can be one of the following values: 1620 * @arg RCC_PLL3_SOURCE_NONE: No oscillator clock selected as PLL3 clock entry 1621 * @arg RCC_PLL3_SOURCE_CSI: CSI oscillator clock selected as PLL3 clock entry 1622 * @arg RCC_PLL3_SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 1623 * @arg RCC_PLL3_SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 1624 * 1625 */ 1626 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ 1627 (__PLL3SOURCE__)) 1628 1629 /** @brief Macro to get the oscillator used as PLL3 clock source. 1630 * @retval The oscillator used as PLL3 clock source. The returned value can be one 1631 * of the following: 1632 * - RCC_PLL3_SOURCE_NONE: No oscillator is used as PLL3 clock source. 1633 * - RCC_PLL3_SOURCE_CSI: CSI oscillator is used as PLL3 clock source. 1634 * - RCC_PLL3_SOURCE_HSI: HSI oscillator is used as PLL3 clock source. 1635 * - RCC_PLL3_SOURCE_HSE: HSE oscillator is used as PLL3 clock source. 1636 */ 1637 #define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) 1638 1639 /** 1640 * @brief Macro to configures the PLL3 source, multiplication and division factors. 1641 * @note This function must be used only when PLL3 is disabled. 1642 * 1643 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1644 * This parameter can be one of the following values: 1645 * @arg @ref RCC_PLL3_SOURCE_NONE No clock selected as PLL3 clock entry 1646 * @arg @ref RCC_PLL3_SOURCE_CSI CSI oscillator clock selected as PLL3 clock entry 1647 * @arg @ref RCC_PLL3_SOURCE_HSI HSI oscillator clock selected as PLL3 clock entry 1648 * @arg @ref RCC_PLL3_SOURCE_HSE HSE oscillator clock selected as PLL3 clock entry 1649 * 1650 * @param __PLL3M__ specifies the division factor of PLL3 input clock. 1651 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1652 * 1653 * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock 1654 * This parameter must be a number between 4 and 512. 1655 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1656 * output frequency is between 150 and 420 MHz (when in medium VCO range) 1657 * or between 192 and 836 MHZ (when in wide VCO range) 1658 * 1659 * @param __PLL3P__: specifies the division factor for peripheral kernel clocks 1660 * This parameter must be a number between 1 and 128 1661 * 1662 * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks 1663 * This parameter must be a number between 1 and 128 1664 * 1665 * @param __PLL3R__: specifies the division factor for peripheral kernel clocks 1666 * This parameter must be a number between 1 and 128 1667 * 1668 * @retval None 1669 */ 1670 #define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ 1671 do{\ 1672 MODIFY_REG(RCC->PLL3CFGR, (RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M), \ 1673 ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos) | ((__PLL3M__) << RCC_PLL3CFGR_PLL3M_Pos)); \ 1674 WRITE_REG(RCC->PLL3DIVR , ( (((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | \ 1675 ((((__PLL3P__) - 1U) << RCC_PLL3DIVR_PLL3P_Pos) & RCC_PLL3DIVR_PLL3P) | \ 1676 ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR_PLL3Q_Pos) & RCC_PLL3DIVR_PLL3Q) | \ 1677 ((((__PLL3R__) - 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ 1678 } while(0) 1679 1680 /** 1681 * @brief Macro to configure the PLL3 clock multiplication factor N. 1682 * 1683 * @note This function must be used only when the PLL3 is disabled. 1684 * @note PLL3 clock source is independent from the main PLL and is configured through 1685 * __HAL_RCC_PLL3_CONFIG() macro. 1686 * 1687 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock. 1688 * This parameter must be a number between 8 and 86. 1689 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1690 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1691 * PLL3 clock frequency = f(PLL3) multiplied by PLL3N 1692 * 1693 * @retval None 1694 */ 1695 #define __HAL_RCC_PLL3_MULN_CONFIG(__PLL3N__) \ 1696 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, ((__PLL3N__) - 1U) << RCC_PLL3DIVR_N3_Pos) 1697 1698 /** @brief Macro to configure the PLL3 input clock division factor M. 1699 * 1700 * @note This function must be used only when the PLL3 is disabled. 1701 * @note PLL3 clock source is independent from the main PLL and is configured through 1702 * __HAL_RCC_PLL3_CONFIG() macro. 1703 * 1704 * @param __PLL3M__ specifies the division factor for PLL3 clock. 1705 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1706 * In order to save power when PLL3 is not used, the value of PLL3M must be set to 0. 1707 * 1708 * @retval None 1709 */ 1710 #define __HAL_RCC_PLL3_DIVM_CONFIG(__PLL3M__) \ 1711 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_DIVM3, (__PLL3M__) << RCC_PLL3CFGR_DIVM3_Pos) 1712 1713 /** @brief Macro to configure the PLL3 clock division factor P. 1714 * 1715 * @note This function must be used only when the PLL3 is disabled. 1716 * @note PLL3 clock source is independent from the main PLL and is configured through 1717 * __HAL_RCC_PLL3_CONFIG() macro. 1718 * 1719 * @param __PLL3P__ specifies the division factor for PLL3 output P clock. 1720 * This parameter must be a number in the range (1 to 128). 1721 * Use to set PLL3 output P clock frequency = f(PLL3) / PLL3P 1722 * 1723 * @retval None 1724 */ 1725 #define __HAL_RCC_PLL3_DIVP_CONFIG(__PLL3P__) \ 1726 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, ((__PLL3P__) - 1U) << RCC_PLL3DIVR_P3_Pos) 1727 1728 /** @brief Macro to configure the PLL3 clock division factor Q. 1729 * 1730 * @note This function must be used only when the PLL3 is disabled. 1731 * @note PLL3 clock source is independent from the main PLL and is configured through 1732 * __HAL_RCC_PLL3_CONFIG() macro. 1733 * 1734 * @param __PLL3Q__ specifies the division factor for PLL3 output Q clock. 1735 * This parameter must be a number in the range (1 to 128). 1736 * Use to set PLL3 output Q clock frequency = f(PLL3) / PLL3Q 1737 * 1738 * @retval None 1739 */ 1740 #define __HAL_RCC_PLL3_DIVQ_CONFIG(__PLL3Q__) \ 1741 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, ((__PLL3Q__) - 1U) << RCC_PLL3DIVR_Q3_Pos) 1742 1743 /** @brief Macro to configure the PLL3 clock division factor R. 1744 * 1745 * @note This function must be used only when the PLL3 is disabled. 1746 * @note PLL3 clock source is independent from the main PLL and is configured through 1747 * __HAL_RCC_PLL3_CONFIG() macro. 1748 * 1749 * @param __PLL3R__ specifies the division factor for PLL3 output R clock. 1750 * This parameter must be a number in the range (1 to 128). 1751 * Use to set PLL3 output R clock frequency = f(PLL3) / PLL3R 1752 * 1753 * @retval None 1754 */ 1755 #define __HAL_RCC_PLL3_DIVR_CONFIG(__PLL3R__) \ 1756 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, ((__PLL3R__) - 1U) << RCC_PLL3DIVR_R3_Pos) 1757 1758 /** 1759 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1760 * 1761 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1762 * 1763 * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1764 * It should be a value between 0 and 8191 1765 * @note Warning: the software has to set correctly these bits to insure that the VCO 1766 * output frequency is between its valid frequency range, which is: 1767 * 192 to 836 MHz if PLL3VCOSEL = 0 1768 * 150 to 420 MHz if PLL3VCOSEL = 1. 1769 * 1770 * @retval None 1771 */ 1772 #define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ 1773 (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) 1774 1775 /** @brief Macro to select the PLL3 reference frequency range. 1776 * @param __PLL3VCIRange__: specifies the PLL3 input frequency range 1777 * This parameter can be one of the following values: 1778 * @arg RCC_PLL3_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1779 * @arg RCC_PLL3_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1780 * @arg RCC_PLL3_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1781 * @arg RCC_PLL3_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1782 * 1783 * @retval None 1784 */ 1785 #define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ 1786 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) 1787 1788 /** @brief Macro to select the PLL3 reference frequency range. 1789 * @param __RCC_PLL3VCORange__: specifies the PLL3 input frequency range 1790 * This parameter can be one of the following values: 1791 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz 1792 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 1793 * 1794 * @retval None 1795 */ 1796 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 1797 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 1798 1799 /** 1800 * @brief Macros to enable or disable the PLL3. 1801 * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1802 * @retval None 1803 */ 1804 1805 /** @brief Macros to enable or disable the main PLL3. 1806 * @note After enabling PLL3, the application software should wait on 1807 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1808 * be used as kernel clock source. 1809 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1810 */ 1811 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1812 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1813 1814 /** 1815 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1816 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL3 1817 * @retval None 1818 */ 1819 #define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1820 #define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1821 1822 /** 1823 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1824 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, 1825 * This is mainly used to save Power. 1826 * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted 1827 * This parameter can be one of the following values: 1828 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1829 * high-quality audio performance on SAI and SPI/I2S interfaces. 1830 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1831 * and USB peripherals. 1832 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1833 * 1834 * @retval None 1835 */ 1836 #define __HAL_RCC_PLL3_CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1837 #define __HAL_RCC_PLL3_CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1838 1839 /** 1840 * @brief Macro to get clock output enable status (PLL3_SAI2). 1841 * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be output. 1842 * This parameter can be one or a combination of the following values: 1843 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1844 * high-quality audio performance on SAI and SPI/I2S interfaces. 1845 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1846 * and USB peripherals. 1847 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1848 * 1849 * @retval SET / RESET 1850 */ 1851 #define __HAL_RCC_GET_PLL3_CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1852 #endif /* RCC_CR_PLL3ON */ 1853 1854 /** @brief Macro to configure the ADC and DAC kernel clock source. 1855 * @param __ADCDAC_CLKSOURCE__ specifies the ADC and DAC kernel clock source. 1856 * This parameter can be one of the following values: 1857 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB bus clock selected as ADC and DAC kernel clock 1858 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock selected as ADC and DAC kernel clock 1859 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock selected as ADC and DAC kernel clock 1860 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE clock selected as ADC and DAC kernel clock 1861 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI clock selected as ADC and DAC kernel clock 1862 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI clock selected as ADC and DAC kernel clock 1863 * @retval None 1864 */ 1865 #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ 1866 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) 1867 1868 /** @brief Macro to get the ADC and DAC kernel clock source. 1869 * @retval The clock source can be one of the following values: 1870 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB Bus clock used as ADC and DAC kernel clock 1871 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock used as ADC and DAC kernel clock 1872 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock used as ADC and DAC kernel clock 1873 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE oscillator used as ADC and DAC kernel clock 1874 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI oscillator used as ADC and DAC kernel clock 1875 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI oscillator used as ADC and DAC kernel clock 1876 */ 1877 #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL))) 1878 1879 /** @brief Macro to configure the DAC kernel clock source in low-power mode. 1880 * @param __DACLPCLKSOURCE__ specifies the DAC kernel clock source in low-power mode. 1881 * This parameter can be one of the following values: 1882 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator selected as DAC kernel clock in low-power mode 1883 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator selected as DAC kernel clock in low-power mode 1884 * @retval None 1885 */ 1886 #define __HAL_RCC_DAC_LP_CONFIG(__DACLPCLKSOURCE__) \ 1887 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, (uint32_t)(__DACLPCLKSOURCE__)) 1888 1889 /** @brief Macro to get the DAC kernel clock source in low-power mode. 1890 * @retval The clock source can be one of the following values: 1891 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator used as DAC kernel clock in low-power mode 1892 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator used as DAC kernel clock in low-power mode 1893 */ 1894 #define __HAL_RCC_GET_DAC_LP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_DACSEL))) 1895 1896 /** @brief Macro to configure the FDCAN kernel clock (FDCANCLK). 1897 * 1898 * @param __FDCAN_CLKSOURCE__ specifies the FDCAN kernel clock source. 1899 * This parameter can be one of the following values: 1900 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock 1901 * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock 1902 * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock 1903 * @retval None 1904 */ 1905 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1906 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 1907 1908 /** @brief Macro to get the FDCAN clock source. 1909 * @retval The clock source can be one of the following values: 1910 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock 1911 * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock 1912 * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock 1913 */ 1914 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL))) 1915 1916 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1917 * 1918 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1919 * This parameter can be one of the following values: 1920 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1921 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1922 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1923 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1924 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1925 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1926 * @retval None 1927 * 1928 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1929 */ 1930 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1931 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1932 1933 /** @brief Macro to get the LPTIM1 clock source. 1934 * @retval The clock source can be one of the following values: 1935 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1936 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1937 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1938 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1939 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1940 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1941 * 1942 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1943 */ 1944 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) 1945 1946 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1947 * 1948 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1949 * This parameter can be one of the following values: 1950 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1951 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1952 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1953 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1954 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1955 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 1956 * @retval None 1957 * 1958 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1959 */ 1960 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1961 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1962 1963 /** @brief Macro to get the LPTIM2 clock source. 1964 * @retval The clock source can be one of the following values: 1965 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1966 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1967 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1968 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1969 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1970 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 1971 * 1972 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1973 */ 1974 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL))) 1975 1976 #if defined(LPTIM3) 1977 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 1978 * 1979 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 1980 * This parameter can be one of the following values: 1981 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 1982 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 1983 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 1984 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1985 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1986 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 1987 * @retval None 1988 */ 1989 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 1990 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 1991 1992 /** @brief Macro to get the LPTIM3 clock source. 1993 * @retval The clock source can be one of the following values: 1994 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 1995 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 1996 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 1997 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1998 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1999 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 2000 */ 2001 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL))) 2002 #endif /* LPTIM3 */ 2003 2004 #if defined(LPTIM4) 2005 /** @brief Macro to configure the LPTIM4 clock (LPTIM4CLK). 2006 * 2007 * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. 2008 * This parameter can be one of the following values: 2009 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 2010 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 2011 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 2012 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 2013 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 2014 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 2015 * @retval None 2016 */ 2017 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ 2018 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL, (uint32_t)(__LPTIM4_CLKSOURCE__)) 2019 2020 /** @brief Macro to get the LPTIM4 clock source. 2021 * @retval The clock source can be one of the following values: 2022 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 2023 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 2024 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 2025 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 2026 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 2027 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 2028 */ 2029 #define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL))) 2030 #endif /* LPTIM4 */ 2031 2032 #if defined(LPTIM5) 2033 /** @brief Macro to configure the LPTIM5 clock (LPTIM5CLK). 2034 * 2035 * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. 2036 * This parameter can be one of the following values: 2037 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2038 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2039 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2040 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2041 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2042 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2043 * @retval None 2044 */ 2045 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ 2046 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL, (uint32_t)(__LPTIM5_CLKSOURCE__)) 2047 2048 /** @brief Macro to get the LPTIM5 clock source. 2049 * @retval The clock source can be one of the following values: 2050 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2051 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2052 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2053 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2054 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2055 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2056 */ 2057 #define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL))) 2058 #endif /* LPTIM5 */ 2059 2060 #if defined(LPTIM6) 2061 /** @brief Macro to configure the LPTIM6 clock (LPTIM6CLK). 2062 * 2063 * @param __LPTIM6_CLKSOURCE__ specifies the LPTIM6 clock source. 2064 * This parameter can be one of the following values: 2065 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2066 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2067 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2068 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2069 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2070 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2071 * @retval None 2072 */ 2073 #define __HAL_RCC_LPTIM6_CONFIG(__LPTIM6_CLKSOURCE__) \ 2074 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL, (uint32_t)(__LPTIM6_CLKSOURCE__)) 2075 2076 /** @brief Macro to get the LPTIM6 clock source. 2077 * @retval The clock source can be one of the following values: 2078 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2079 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2080 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2081 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2082 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2083 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2084 */ 2085 #define __HAL_RCC_GET_LPTIM6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL))) 2086 #endif /* LPTIM6 */ 2087 2088 /** @brief macro to configure the SPI1 clock source. 2089 * @retval The clock source can be one of the following values: 2090 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2091 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2092 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2093 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2094 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2095 * 2096 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2097 */ 2098 #define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ 2099 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) 2100 2101 /** @brief macro to get the SPI1 clock source. 2102 * @retval The clock source can be one of the following values: 2103 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2104 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2105 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2106 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2107 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2108 * 2109 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2110 */ 2111 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) 2112 2113 /** @brief macro to configure the SPI2 clock source. 2114 * @retval The clock source can be one of the following values: 2115 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2116 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2117 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2118 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2119 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2120 * 2121 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2122 */ 2123 #define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ 2124 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) 2125 2126 /** @brief macro to get the SPI2 clock source. 2127 * @retval The clock source can be one of the following values: 2128 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2129 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2130 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2131 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2132 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2133 * 2134 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2135 */ 2136 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL))) 2137 2138 /** @brief macro to configure the SPI3 clock source. 2139 * @retval The clock source can be one of the following values: 2140 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2141 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2142 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2143 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2144 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2145 * 2146 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2147 */ 2148 #define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ 2149 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) 2150 2151 /** @brief macro to get the SPI3 clock source. 2152 * @retval The clock source can be one of the following values: 2153 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2154 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2155 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2156 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2157 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2158 * 2159 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2160 */ 2161 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) 2162 2163 #if defined(SPI4) 2164 /** @brief macro to configure the SPI4 clock source. 2165 * @retval The clock source can be one of the following values: 2166 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2167 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2168 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2169 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2170 * @arg RCC_SPI4CLKSOURCE_CSI CSI Clock used as SPI4 clock 2171 * @arg RCC_SPI4CLKSOURCE_HSE HSE Clock used as SPI4 clock 2172 */ 2173 #define __HAL_RCC_SPI4_CONFIG(__SPI4CLKSource__) \ 2174 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL, (uint32_t)(__SPI4CLKSource__)) 2175 2176 /** @brief macro to get the SPI4 clock source. 2177 * @retval The clock source can be one of the following values: 2178 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2179 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2180 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2181 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2182 * @arg RCC_SPI4CLKSOURCE_CSI CSI used as SPI4 clock 2183 * @arg RCC_SPI4CLKSOURCE_HSE HSE used as SPI4 clock 2184 */ 2185 #define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL))) 2186 #endif /* SPI4 */ 2187 2188 #if defined(SPI5) 2189 /** @brief macro to configure the SPI5 clock source. 2190 * @retval The clock source can be one of the following values: 2191 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2192 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2193 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2194 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2195 * @arg RCC_SPI5CLKSOURCE_CSI CSI Clock used as SPI5 clock 2196 * @arg RCC_SPI5CLKSOURCE_HSE HSE Clock used as SPI5 clock 2197 */ 2198 #define __HAL_RCC_SPI5_CONFIG(__SPI5CLKSource__) \ 2199 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL, (uint32_t)(__SPI5CLKSource__)) 2200 2201 /** @brief macro to get the SPI5 clock source. 2202 * @retval The clock source can be one of the following values: 2203 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2204 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2205 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2206 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2207 * @arg RCC_SPI5CLKSOURCE_CSI CSI used as SPI5 clock 2208 * @arg RCC_SPI5CLKSOURCE_HSE HSE used as SPI5 clock 2209 */ 2210 #define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL))) 2211 #endif /* SPI5 */ 2212 2213 #if defined(SPI6) 2214 /** @brief macro to configure the SPI6 clock source. 2215 * @retval The clock source can be one of the following values: 2216 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2217 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2218 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2219 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2220 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2221 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2222 */ 2223 #define __HAL_RCC_SPI6_CONFIG(__SPI6CLKSource__) \ 2224 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL, (uint32_t)(__SPI6CLKSource__)) 2225 2226 /** @brief macro to get the SPI6 clock source. 2227 * @retval The clock source can be one of the following values: 2228 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2229 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2230 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2231 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2232 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2233 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2234 */ 2235 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL))) 2236 #endif /* SPI6 */ 2237 2238 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 2239 * 2240 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 2241 * This parameter can be one of the following values: 2242 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2243 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2244 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2245 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2246 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2247 * @retval None 2248 * 2249 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2250 * (**) : For stm32h503xx family line. 2251 */ 2252 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 2253 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 2254 2255 /** @brief Macro to get the I2C1 clock source. 2256 * @retval The clock source can be one of the following values: 2257 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2258 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2259 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2260 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2261 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2262 * 2263 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2264 * (**) : For stm32h503xx family line. 2265 */ 2266 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL))) 2267 2268 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 2269 * 2270 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 2271 * This parameter can be one of the following values: 2272 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2273 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2274 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2275 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2276 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2277 * @retval None 2278 * 2279 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2280 * (**) : For stm32h503xx family line. 2281 */ 2282 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 2283 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 2284 2285 /** @brief Macro to get the I2C2 clock source. 2286 * @retval The clock source can be one of the following values: 2287 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2288 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2289 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2290 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2291 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2292 * 2293 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2294 * (**) : For stm32h503xx family line. 2295 */ 2296 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL))) 2297 2298 #if defined(I2C3) 2299 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 2300 * 2301 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 2302 * This parameter can be one of the following values: 2303 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2304 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2305 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2306 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2307 * @retval None 2308 */ 2309 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 2310 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 2311 2312 /** @brief Macro to get the I2C3 clock source. 2313 * @retval The clock source can be one of the following values: 2314 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2315 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2316 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2317 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2318 */ 2319 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL))) 2320 #endif /* I2C3 */ 2321 2322 #if defined(I2C4) 2323 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 2324 * 2325 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 2326 * This parameter can be one of the following values: 2327 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2328 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2329 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2330 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2331 * @retval None 2332 */ 2333 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 2334 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 2335 2336 /** @brief Macro to get the I2C4 clock source. 2337 * @retval The clock source can be one of the following values: 2338 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2339 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2340 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2341 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2342 */ 2343 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL))) 2344 #endif /* I2C4 */ 2345 2346 /** @brief Macro to configure the I3C1 clock (I3C1CLK). 2347 * 2348 * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. 2349 * This parameter can be one of the following values: 2350 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2351 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2352 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2353 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2354 * @retval None 2355 * 2356 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2357 * (**) : For stm32h503xx family line. 2358 */ 2359 #define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ 2360 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) 2361 2362 /** @brief Macro to get the I3C1 clock source. 2363 * @retval The clock source can be one of the following values: 2364 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2365 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2366 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2367 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2368 * 2369 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2370 * (**) : For stm32h503xx family line. 2371 */ 2372 #define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL))) 2373 2374 #if defined(I3C2) 2375 /** @brief Macro to configure the I3C2 clock (I3C2CLK). 2376 * 2377 * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. 2378 * This parameter can be one of the following values: 2379 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2380 * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) 2381 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2382 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2383 * 2384 * @retval None 2385 * 2386 * (*) : Not available for all stm32h5xxxx family lines. 2387 */ 2388 #define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ 2389 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__)) 2390 2391 /** @brief Macro to get the I3C2 clock source. 2392 * @retval The clock source can be one of the following values: 2393 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2394 * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) 2395 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2396 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2397 * 2398 * (*) : Not available for all stm32h5xxxx family lines. 2399 */ 2400 #define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL))) 2401 #endif /* I3C2 */ 2402 2403 /** @brief Macro to configure the USART1 clock (USART1CLK). 2404 * 2405 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 2406 * This parameter can be one of the following values: 2407 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2408 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2409 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2410 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2411 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2412 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2413 * @retval None 2414 * 2415 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2416 */ 2417 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 2418 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 2419 2420 /** @brief Macro to get the USART1 clock source. 2421 * @retval The clock source can be one of the following values: 2422 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2423 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2424 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2425 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2426 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2427 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2428 * 2429 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2430 */ 2431 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 2432 2433 /** @brief Macro to configure the USART2 clock (USART2CLK). 2434 * 2435 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 2436 * This parameter can be one of the following values: 2437 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2438 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2439 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2440 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2441 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2442 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2443 * @retval None 2444 * 2445 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2446 */ 2447 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 2448 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 2449 2450 /** @brief Macro to get the USART2 clock source. 2451 * @retval The clock source can be one of the following values: 2452 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2453 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2454 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2455 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2456 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2457 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2458 * 2459 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2460 */ 2461 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 2462 2463 /** @brief Macro to configure the USART3 clock (USART3CLK). 2464 * 2465 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 2466 * This parameter can be one of the following values: 2467 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2468 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2469 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2470 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2471 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2472 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2473 * @retval None 2474 * 2475 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2476 */ 2477 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 2478 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 2479 2480 /** @brief Macro to get the USART3 clock source. 2481 * @retval The clock source can be one of the following values: 2482 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2483 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2484 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2485 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2486 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2487 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2488 * 2489 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2490 */ 2491 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 2492 2493 #if defined(UART4) 2494 /** @brief Macro to configure the UART4 clock (UART4CLK). 2495 * 2496 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 2497 * This parameter can be one of the following values: 2498 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2499 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2500 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2501 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2502 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2503 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2504 * @retval None 2505 */ 2506 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 2507 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 2508 2509 /** @brief Macro to get the UART4 clock source. 2510 * @retval The clock source can be one of the following values: 2511 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2512 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2513 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2514 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2515 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2516 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2517 */ 2518 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 2519 #endif /* UART4 */ 2520 2521 #if defined(UART5) 2522 /** @brief Macro to configure the UART5 clock (UART5CLK). 2523 * 2524 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 2525 * This parameter can be one of the following values: 2526 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2527 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2528 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2529 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2530 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2531 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2532 * @retval None 2533 */ 2534 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 2535 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 2536 2537 /** @brief Macro to get the UART5 clock source. 2538 * @retval The clock source can be one of the following values: 2539 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2540 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2541 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2542 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2543 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2544 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2545 */ 2546 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 2547 #endif /* UART5 */ 2548 2549 #if defined(USART6) 2550 /** @brief Macro to configure the USART6 clock (USART6CLK). 2551 * 2552 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 2553 * This parameter can be one of the following values: 2554 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK2 selected as USART6 clock 2555 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2556 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2557 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2558 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2559 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2560 * @retval None 2561 */ 2562 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 2563 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 2564 2565 /** @brief Macro to get the USART6 clock source. 2566 * @retval The clock source can be one of the following values: 2567 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock 2568 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2569 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2570 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2571 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2572 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2573 */ 2574 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART6SEL))) 2575 #endif /* USART6 */ 2576 2577 #if defined(UART7) 2578 /** @brief Macro to configure the UART7 clock (UART7CLK). 2579 * 2580 * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. 2581 * This parameter can be one of the following values: 2582 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2583 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2584 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2585 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2586 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2587 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2588 * @retval None 2589 */ 2590 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ 2591 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) 2592 2593 /** @brief Macro to get the UART7 clock source. 2594 * @retval The clock source can be one of the following values: 2595 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2596 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2597 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2598 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2599 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2600 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2601 */ 2602 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART7SEL))) 2603 #endif /* UART5 */ 2604 2605 #if defined(UART8) 2606 /** @brief Macro to configure the UART8 clock (UART8CLK). 2607 * 2608 * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. 2609 * This parameter can be one of the following values: 2610 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2611 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2612 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2613 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2614 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2615 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2616 * @retval None 2617 */ 2618 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ 2619 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) 2620 2621 /** @brief Macro to get the UART8 clock source. 2622 * @retval The clock source can be one of the following values: 2623 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2624 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2625 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2626 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2627 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2628 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2629 */ 2630 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART8SEL))) 2631 #endif /* UART8 */ 2632 2633 #if defined(UART9) 2634 /** @brief Macro to configure the UART9 clock (UART9CLK). 2635 * 2636 * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. 2637 * This parameter can be one of the following values: 2638 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2639 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2640 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2641 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2642 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2643 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2644 * @retval None 2645 */ 2646 #define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ 2647 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART9SEL, (uint32_t)(__UART9_CLKSOURCE__)) 2648 2649 /** @brief Macro to get the UART9 clock source. 2650 * @retval The clock source can be one of the following values: 2651 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2652 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2653 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2654 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2655 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2656 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2657 */ 2658 #define __HAL_RCC_GET_UART9_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART9SEL))) 2659 #endif /* UART9 */ 2660 2661 #if defined(USART10) 2662 /** @brief Macro to configure the USART10 clock (USART10CLK). 2663 * 2664 * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. 2665 * This parameter can be one of the following values: 2666 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2667 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2668 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2669 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2670 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2671 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2672 * @retval None 2673 */ 2674 #define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ 2675 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART10SEL, (uint32_t)(__USART10_CLKSOURCE__)) 2676 2677 /** @brief Macro to get the USART10 clock source. 2678 * @retval The clock source can be one of the following values: 2679 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2680 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2681 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2682 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2683 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2684 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2685 */ 2686 #define __HAL_RCC_GET_USART10_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART10SEL))) 2687 #endif /* USART10 */ 2688 2689 #if defined(USART11) 2690 /** @brief Macro to configure the USART11 clock (USART11CLK). 2691 * 2692 * @param __USART11_CLKSOURCE__ specifies the USART11 clock source. 2693 * This parameter can be one of the following values: 2694 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2695 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2696 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2697 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2698 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2699 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2700 * @retval None 2701 */ 2702 #define __HAL_RCC_USART11_CONFIG(__USART11_CLKSOURCE__) \ 2703 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART11SEL, (uint32_t)(__USART11_CLKSOURCE__)) 2704 2705 /** @brief Macro to get the USART11 clock source. 2706 * @retval The clock source can be one of the following values: 2707 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2708 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2709 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2710 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2711 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2712 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2713 */ 2714 #define __HAL_RCC_GET_USART11_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART11SEL))) 2715 #endif /* USART11 */ 2716 2717 #if defined(UART12) 2718 /** @brief Macro to configure the UART12 clock (UART12CLK). 2719 * 2720 * @param __UART12_CLKSOURCE__ specifies the UART12 clock source. 2721 * This parameter can be one of the following values: 2722 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2723 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2724 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2725 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2726 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2727 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2728 * @retval None 2729 */ 2730 #define __HAL_RCC_UART12_CONFIG(__UART12_CLKSOURCE__) \ 2731 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART12SEL, (uint32_t)(__UART12_CLKSOURCE__)) 2732 2733 /** @brief Macro to get the UART12 clock source. 2734 * @retval The clock source can be one of the following values: 2735 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2736 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2737 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2738 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2739 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2740 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2741 */ 2742 #define __HAL_RCC_GET_UART12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART12SEL))) 2743 #endif /* UART12 */ 2744 2745 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 2746 * 2747 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 2748 * This parameter can be one of the following values: 2749 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2750 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2751 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2752 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2753 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2754 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2755 * 2756 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2757 * @retval None 2758 */ 2759 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 2760 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 2761 2762 /** @brief Macro to get the LPUART1 clock source. 2763 * @retval The clock source can be one of the following values: 2764 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2765 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2766 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2767 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2768 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2769 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2770 * 2771 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2772 */ 2773 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) 2774 2775 #if defined(OCTOSPI1) 2776 /** @brief Macro to configure the OctoSPI clock. 2777 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 2778 * This parameter can be one of the following values: 2779 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2780 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2781 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2782 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2783 * @retval None 2784 */ 2785 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 2786 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 2787 2788 /** @brief Macro to get the OctoSPI clock source. 2789 * @retval The clock source can be one of the following values: 2790 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2791 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2792 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2793 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2794 */ 2795 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL))) 2796 #endif /* OCTOSPI1 */ 2797 2798 #if defined(SDMMC1) 2799 /** @brief Macro to configure the SDMMC1 clock (SDMMCCLK). 2800 * 2801 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. 2802 * This parameter can be one of the following values: 2803 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2804 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2805 */ 2806 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 2807 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) 2808 2809 /** @brief macro to get the SDMMC1 clock source. 2810 * @retval The clock source can be one of the following values: 2811 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2812 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2813 */ 2814 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL))) 2815 #endif /* SDMMC1 */ 2816 2817 #if defined(SDMMC2) 2818 /** @brief Macro to configure the SDMMC2 clock (SDMMCCLK). 2819 * 2820 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. 2821 * This parameter can be one of the following values: 2822 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2823 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2824 */ 2825 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ 2826 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) 2827 2828 /** @brief macro to get the SDMMC2 clock source. 2829 * @retval The clock source can be one of the following values: 2830 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2831 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2832 */ 2833 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL))) 2834 #endif /*SDMMC2*/ 2835 2836 /** @brief macro to configure the RNG clock (RNGCLK). 2837 * 2838 * @param __RNGCLKSource__: specifies the RNG clock source. 2839 * This parameter can be one of the following values: 2840 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2841 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2842 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2843 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2844 */ 2845 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 2846 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, (uint32_t)(__RNGCLKSource__)) 2847 2848 /** @brief macro to get the RNG clock source. 2849 * @retval The clock source can be one of the following values: 2850 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2851 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2852 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2853 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2854 */ 2855 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_RNGSEL))) 2856 2857 #if defined(SAI1) 2858 /** 2859 * @brief Macro to configure the SAI1 clock source. 2860 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. 2861 * This parameter can be one of the following values: 2862 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2863 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2Pselected as SAI1 clock 2864 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2865 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2866 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2867 * @retval None 2868 */ 2869 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 2870 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 2871 2872 /** @brief Macro to get the SAI1 clock source. 2873 * @retval The clock source can be one of the following values: 2874 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2875 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2P selected as SAI1 clock 2876 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2877 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2878 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2879 */ 2880 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL))) 2881 #endif /* SAI1 */ 2882 2883 #if defined(SAI2) 2884 /** 2885 * @brief Macro to configure the SAI2 clock source. 2886 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. 2887 * This parameter can be one of the following values: 2888 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2889 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2890 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2891 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2892 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2893 * @retval None 2894 */ 2895 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 2896 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 2897 2898 /** @brief Macro to get the SAI2 clock source. 2899 * @retval The clock source can be one of the following values: 2900 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2901 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2902 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2903 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2904 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2905 */ 2906 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL))) 2907 #endif /* SAI2 */ 2908 2909 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 2910 * @param __CLKPSource__ specifies Oscillator clock for peripheral 2911 * This parameter can be one of the following values: 2912 * @arg RCC_CLKPSOURCE_HSI HSI oscillator selected as clock for peripheral 2913 * @arg RCC_CLKPSOURCE_CSI CSI oscillator selected as clock for peripheral 2914 * @arg RCC_CLKPSOURCE_HSE HSE oscillator selected as clock for peripheral 2915 */ 2916 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 2917 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, (uint32_t)(__CLKPSource__)) 2918 2919 /** @brief Macro to get the oscillator clock for peripheral clock source. 2920 * @retval The clock source can be one of the following values: 2921 * @arg RCC_CLKPSOURCE_HSI HSI selected Oscillator clock for peripheral 2922 * @arg RCC_CLKPSOURCE_CSI CSI selected Oscillator clock for peripheral 2923 * @arg RCC_CLKPSOURCE_HSE HSE selected Oscillator clock for peripheral 2924 */ 2925 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL))) 2926 2927 #if defined(CEC) 2928 /** @brief Macro to configure the CEC clock (CECCLK) 2929 * @param __CECCLKSource__ specifies the CEC clock source. 2930 * This parameter can be one of the following values: 2931 * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 2932 * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock 2933 * @arg RCC_CECCLKSOURCE_CSI_DIV122 CSI Divided by 122 selected as CEC clock 2934 */ 2935 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 2936 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, (uint32_t)(__CECCLKSource__)) 2937 2938 /** @brief Macro to get the CEC clock source. 2939 * @retval The clock source can be one of the following values: 2940 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 2941 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 2942 * @arg RCC_CECCLKSOURCE_CSI_DIV122: CSI Divided by 122 selected as CEC clock 2943 */ 2944 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL))) 2945 #endif /* CEC */ 2946 2947 #if defined(USB_DRD_FS) 2948 /** @brief Macro to configure the USB clock (USBCLK). 2949 * @param __USBCLKSource__ specifies the USB clock source. 2950 * This parameter can be one of the following values: 2951 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2952 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2953 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2954 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2955 * 2956 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2957 * (**) : For stm32h503xx family line. 2958 */ 2959 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 2960 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, (uint32_t)(__USBCLKSource__)) 2961 2962 /** @brief Macro to get the USB clock source. 2963 * @retval The clock source can be one of the following values: 2964 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2965 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2966 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2967 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2968 * 2969 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2970 * (**) : For stm32h503xx family line. 2971 */ 2972 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL))) 2973 #endif /* USB_DRD_FS */ 2974 2975 /** @brief Macro to configure the Timers clocks prescalers 2976 * @param __PRESC__ specifies the Timers clocks prescalers selection 2977 * This parameter can be one of the following values: 2978 * @arg RCC_TIMPRES_DEACTIVATED: The Timers kernels clocks prescaler is 2979 * equal to rcc_hclk1 if PPREx is corresponding to division by 1 or 2, 2980 * else it is equal to 2 x Frcc_pclkx (default after reset) 2981 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 2982 * equal to rcc_hclk1 if PPREx is corresponding to division by 1, 2 or 4, 2983 * else it is equal to 4 x Frcc_pclkx 2984 */ 2985 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR1 &= ~(RCC_CFGR1_TIMPRE);\ 2986 RCC->CFGR1 |= (__PRESC__); \ 2987 }while(0) 2988 2989 #if defined(CRS) 2990 2991 /** 2992 * @brief Enable the specified CRS interrupts. 2993 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2994 * This parameter can be any combination of the following values: 2995 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2996 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2997 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2998 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2999 * @retval None 3000 */ 3001 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 3002 3003 /** 3004 * @brief Disable the specified CRS interrupts. 3005 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 3006 * This parameter can be any combination of the following values: 3007 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3008 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3009 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3010 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3011 * @retval None 3012 */ 3013 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 3014 3015 /** @brief Check whether the CRS interrupt has occurred or not. 3016 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 3017 * This parameter can be one of the following values: 3018 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3019 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3020 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3021 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3022 * @retval The new state of __INTERRUPT__ (0 or 1). 3023 */ 3024 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) 3025 3026 /** @brief Clear the CRS interrupt pending bits 3027 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3028 * This parameter can be any combination of the following values: 3029 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3030 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3031 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3032 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3033 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 3034 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 3035 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 3036 */ 3037 /* CRS IT Error Mask */ 3038 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ 3039 RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 3040 3041 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 3042 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 3043 { \ 3044 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3045 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 3046 } \ 3047 else \ 3048 { \ 3049 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 3050 } \ 3051 } while(0) 3052 3053 /** 3054 * @brief Check whether the specified CRS flag is set or not. 3055 * @param __FLAG__ specifies the flag to check. 3056 * This parameter can be one of the following values: 3057 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3058 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3059 * @arg @ref RCC_CRS_FLAG_ERR Error 3060 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3061 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3062 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3063 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3064 * @retval The new state of _FLAG_ (TRUE or FALSE). 3065 */ 3066 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 3067 3068 /** 3069 * @brief Clear the CRS specified FLAG. 3070 * @param __FLAG__ specifies the flag to clear. 3071 * This parameter can be any combination of the following values: 3072 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3073 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3074 * @arg @ref RCC_CRS_FLAG_ERR Error 3075 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3076 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3077 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3078 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3079 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS 3080 and consequently RCC_CRS_FLAG_ERR 3081 * @retval None 3082 */ 3083 3084 /* CRS Flag Error Mask */ 3085 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ 3086 RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 3087 3088 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 3089 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 3090 { \ 3091 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3092 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 3093 } \ 3094 else \ 3095 { \ 3096 WRITE_REG(CRS->ICR, (__FLAG__)); \ 3097 } \ 3098 } while(0) 3099 3100 /** 3101 * @} 3102 */ 3103 3104 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 3105 * @{ 3106 */ 3107 /** 3108 * @brief Enable the oscillator clock for frequency error counter. 3109 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 3110 * @retval None 3111 */ 3112 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 3113 3114 /** 3115 * @brief Disable the oscillator clock for frequency error counter. 3116 * @retval None 3117 */ 3118 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 3119 3120 /** 3121 * @brief Enable the automatic hardware adjustment of TRIM bits. 3122 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 3123 * @retval None 3124 */ 3125 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3126 3127 /** 3128 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 3129 * @retval None 3130 */ 3131 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3132 3133 /** 3134 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 3135 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 3136 * of the synchronization source after prescaling. It is then decreased by one in order to 3137 * reach the expected synchronization on the zero value. The formula is the following: 3138 * RELOAD = (fTARGET / fSYNC) -1 3139 * @param __FTARGET__ Target frequency (value in Hz) 3140 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 3141 * @retval None 3142 */ 3143 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 3144 3145 3146 /** 3147 * @} 3148 */ 3149 3150 #endif /* CRS */ 3151 3152 /* Private constants ---------------------------------------------------------*/ 3153 /** @addtogroup RCCEx_Private_Constants 3154 * @{ 3155 */ 3156 /* Define used for IS_RCC_* macros below */ 3157 #if defined(SDMMC2) 3158 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3159 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3160 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3161 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3162 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3163 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3164 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3165 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3166 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3167 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3168 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ 3169 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 3170 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \ 3171 RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \ 3172 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3173 #elif defined(UART7) 3174 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3175 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3176 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3177 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3178 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3179 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3180 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3181 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3182 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3183 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3184 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ 3185 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ 3186 RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | \ 3187 RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | \ 3188 RCC_PERIPHCLK_CKPER) 3189 #elif defined(USART6) 3190 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3191 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3192 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3193 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \ 3194 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3195 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3196 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ 3197 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ 3198 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ 3199 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3200 #else 3201 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3202 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3203 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \ 3204 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ 3205 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ 3206 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ 3207 RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3208 #endif /*FDCAN2 && SDMMC2 */ 3209 /** 3210 * @} 3211 */ 3212 3213 /* Private macros ------------------------------------------------------------*/ 3214 /** @addtogroup RCCEx_Private_Macros 3215 * @{ 3216 */ 3217 3218 #define IS_RCC_PLL2_SOURCE(SOURCE) (((SOURCE) == RCC_PLL2_SOURCE_CSI) || \ 3219 ((SOURCE) == RCC_PLL2_SOURCE_HSI) || \ 3220 ((SOURCE) == RCC_PLL2_SOURCE_HSE)) 3221 3222 #define IS_RCC_PLL2_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3223 #define IS_RCC_PLL2_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3224 #define IS_RCC_PLL2_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3225 #define IS_RCC_PLL2_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3226 #define IS_RCC_PLL2_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3227 3228 #define IS_RCC_PLL2_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3229 3230 #define IS_RCC_PLL2_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCIRANGE_0) || \ 3231 ((VALUE) == RCC_PLL2_VCIRANGE_1) || \ 3232 ((VALUE) == RCC_PLL2_VCIRANGE_2) || \ 3233 ((VALUE) == RCC_PLL2_VCIRANGE_3)) 3234 3235 #define IS_RCC_PLL2_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCORANGE_WIDE) || ((VALUE) == RCC_PLL2_VCORANGE_MEDIUM)) 3236 3237 #define IS_RCC_PLL2_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3238 3239 #if defined(RCC_CR_PLL3ON) 3240 #define IS_RCC_PLL3_SOURCE(SOURCE) (((SOURCE) == RCC_PLL3_SOURCE_CSI) || \ 3241 ((SOURCE) == RCC_PLL3_SOURCE_HSI) || \ 3242 ((SOURCE) == RCC_PLL3_SOURCE_HSE)) 3243 3244 #define IS_RCC_PLL3_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCIRANGE_0) || \ 3245 ((VALUE) == RCC_PLL3_VCIRANGE_1) || \ 3246 ((VALUE) == RCC_PLL3_VCIRANGE_2) || \ 3247 ((VALUE) == RCC_PLL3_VCIRANGE_3)) 3248 3249 #define IS_RCC_PLL3_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3250 #define IS_RCC_PLL3_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3251 #define IS_RCC_PLL3_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3252 #define IS_RCC_PLL3_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3253 #define IS_RCC_PLL3_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3254 3255 #define IS_RCC_PLL3_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3256 3257 #define IS_RCC_PLL3_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCORANGE_WIDE) || ((VALUE) == RCC_PLL3_VCORANGE_MEDIUM)) 3258 3259 #define IS_RCC_PLL3_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3260 3261 #endif /* RCC_CR_PLL3ON */ 3262 3263 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 3264 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 3265 3266 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 3267 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 3268 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 3269 3270 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != ((uint64_t)0x00)) && \ 3271 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == ((uint64_t)0x00))) 3272 #if defined(RCC_CR_PLL3ON) 3273 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3274 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3275 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3276 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ 3277 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3278 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3279 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3280 3281 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3282 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3283 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3284 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL3Q) || \ 3285 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3286 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3287 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3288 3289 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3290 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3291 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3292 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL3Q) || \ 3293 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3294 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3295 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3296 3297 #else 3298 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3299 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3300 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3301 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3302 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3303 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3304 3305 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3306 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3307 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3308 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3309 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3310 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3311 3312 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3313 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3314 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3315 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3316 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3317 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3318 3319 #endif /* RCC_CR_PLL3ON */ 3320 3321 #if defined(UART4) 3322 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 3323 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 3324 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL2Q) || \ 3325 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL3Q) || \ 3326 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ 3327 ((__SOURCE__) == RCC_UART4CLKSOURCE_CSI) || \ 3328 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) 3329 #endif /* UART4 */ 3330 3331 #if defined(UART5) 3332 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 3333 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 3334 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL2Q) || \ 3335 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL3Q) || \ 3336 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ 3337 ((__SOURCE__) == RCC_UART5CLKSOURCE_CSI) || \ 3338 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) 3339 #endif /* UART5 */ 3340 3341 #if defined(USART6) 3342 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ 3343 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ 3344 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL2Q) || \ 3345 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL3Q) || \ 3346 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ 3347 ((__SOURCE__) == RCC_USART6CLKSOURCE_CSI) || \ 3348 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) 3349 #endif /* USART6 */ 3350 3351 #if defined(UART7) 3352 #define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ 3353 (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ 3354 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL2Q) || \ 3355 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL3Q) || \ 3356 ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI) || \ 3357 ((__SOURCE__) == RCC_UART7CLKSOURCE_CSI) || \ 3358 ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)) 3359 #endif /* UART7 */ 3360 3361 #if defined(UART8) 3362 #define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ 3363 (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ 3364 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL2Q) || \ 3365 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL3Q) || \ 3366 ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI) || \ 3367 ((__SOURCE__) == RCC_UART8CLKSOURCE_CSI) || \ 3368 ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)) 3369 #endif /* UART8 */ 3370 3371 #if defined(UART9) 3372 #define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ 3373 (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK1) || \ 3374 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL2Q) || \ 3375 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL3Q) || \ 3376 ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI) || \ 3377 ((__SOURCE__) == RCC_UART9CLKSOURCE_CSI) || \ 3378 ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE)) 3379 #endif /* UART9 */ 3380 3381 #if defined(USART10) 3382 #define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ 3383 (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK1) || \ 3384 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL2Q) || \ 3385 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL3Q) || \ 3386 ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI) || \ 3387 ((__SOURCE__) == RCC_USART10CLKSOURCE_CSI) || \ 3388 ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE)) 3389 #endif /* USART10 */ 3390 3391 #if defined(USART11) 3392 #define IS_RCC_USART11CLKSOURCE(__SOURCE__) \ 3393 (((__SOURCE__) == RCC_USART11CLKSOURCE_PCLK1) || \ 3394 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL2Q) || \ 3395 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL3Q) || \ 3396 ((__SOURCE__) == RCC_USART11CLKSOURCE_HSI) || \ 3397 ((__SOURCE__) == RCC_USART11CLKSOURCE_CSI) || \ 3398 ((__SOURCE__) == RCC_USART11CLKSOURCE_LSE)) 3399 #endif /* USART11 */ 3400 3401 #if defined(UART12) 3402 #define IS_RCC_UART12CLKSOURCE(__SOURCE__) \ 3403 (((__SOURCE__) == RCC_UART12CLKSOURCE_PCLK1) || \ 3404 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL2Q) || \ 3405 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL3Q) || \ 3406 ((__SOURCE__) == RCC_UART12CLKSOURCE_HSI) || \ 3407 ((__SOURCE__) == RCC_UART12CLKSOURCE_CSI) || \ 3408 ((__SOURCE__) == RCC_UART12CLKSOURCE_LSE)) 3409 #endif /* UART12 */ 3410 3411 #if defined(RCC_CR_PLL3ON) 3412 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3413 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3414 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3415 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ 3416 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3417 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3418 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3419 3420 #else 3421 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3422 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3423 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3424 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3425 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3426 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3427 3428 #endif /* RCC_CR_PLL3ON */ 3429 3430 #if defined(RCC_CR_PLL3ON) 3431 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3432 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3433 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL3R) || \ 3434 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3435 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3436 3437 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3438 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3439 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL3R) || \ 3440 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3441 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3442 3443 #else 3444 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3445 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3446 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL2R) || \ 3447 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3448 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3449 3450 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3451 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3452 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL2R) || \ 3453 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3454 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3455 3456 #endif /* RCC_CR_PLL3ON */ 3457 3458 3459 #if defined(I2C3) 3460 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 3461 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ 3462 ((__SOURCE__) == RCC_I2C3CLKSOURCE_PLL3R) || \ 3463 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ 3464 ((__SOURCE__) == RCC_I2C3CLKSOURCE_CSI)) 3465 #endif /* I2C3 */ 3466 3467 #if defined(I2C4) 3468 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 3469 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK3) || \ 3470 ((__SOURCE__) == RCC_I2C4CLKSOURCE_PLL3R) || \ 3471 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI ) || \ 3472 ((__SOURCE__) == RCC_I2C4CLKSOURCE_CSI)) 3473 #endif /* I2C4 */ 3474 3475 #if defined(RCC_CR_PLL3ON) 3476 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3477 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3478 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ 3479 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3480 3481 #else 3482 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3483 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3484 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL2R) || \ 3485 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3486 3487 #endif /* RCC_CR_PLL3ON */ 3488 3489 #if defined(I3C2) 3490 #if defined(RCC_CR_PLL3ON) 3491 #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ 3492 (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ 3493 ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ 3494 ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) 3495 #else 3496 #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ 3497 (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ 3498 ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ 3499 ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) 3500 #endif /* PLL3 */ 3501 #endif /* I3C2 */ 3502 3503 #if defined(SAI1) 3504 #define IS_RCC_SAI1CLK(__SOURCE__) \ 3505 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q)|| \ 3506 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P)|| \ 3507 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P)|| \ 3508 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 3509 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP)) 3510 3511 #endif /* SAI1 */ 3512 3513 #if defined(SAI2) 3514 #define IS_RCC_SAI2CLK(__SOURCE__) \ 3515 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q)|| \ 3516 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P)|| \ 3517 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P)|| \ 3518 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 3519 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP)) 3520 #endif /* SAI2 */ 3521 3522 #if defined(RCC_CR_PLL3ON) 3523 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3524 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3525 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3526 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ 3527 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3528 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3529 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3530 3531 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3532 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3533 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3534 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL3R) || \ 3535 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3536 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3537 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3538 3539 #else 3540 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3541 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3542 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3543 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3544 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3545 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3546 3547 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3548 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3549 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3550 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3551 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3552 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3553 3554 #endif /* RCC_CR_PLL3ON */ 3555 3556 #if defined(LPTIM3) 3557 #define IS_RCC_LPTIM3CLK(__SOURCE__) \ 3558 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK3) || \ 3559 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL2P) || \ 3560 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL3R) || \ 3561 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ 3562 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 3563 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP)) 3564 3565 #endif /* LPTIM3 */ 3566 3567 #if defined(LPTIM4) 3568 #define IS_RCC_LPTIM4CLK(__SOURCE__) \ 3569 (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK3) || \ 3570 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL2P) || \ 3571 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL3R) || \ 3572 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ 3573 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ 3574 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP)) 3575 3576 #endif /* LPTIM4 */ 3577 3578 #if defined(LPTIM5) 3579 #define IS_RCC_LPTIM5CLK(__SOURCE__) \ 3580 (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK3) || \ 3581 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL2P) || \ 3582 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL3R) || \ 3583 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ 3584 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ 3585 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP)) 3586 #endif /* LPTIM5 */ 3587 3588 #if defined(LPTIM6) 3589 #define IS_RCC_LPTIM6CLK(__SOURCE__) \ 3590 (((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PCLK3) || \ 3591 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL2P) || \ 3592 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL3R) || \ 3593 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSE) || \ 3594 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSI) || \ 3595 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_CLKP)) 3596 #endif /* LPTIM6 */ 3597 3598 #define IS_RCC_FDCANCLK(__SOURCE__) \ 3599 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 3600 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL1Q) || \ 3601 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2Q)) 3602 3603 #if defined(SDMMC1) 3604 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 3605 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL1Q) || \ 3606 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL2R)) 3607 #endif /* SDMMC1 */ 3608 3609 #if defined(SDMMC2) 3610 #define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ 3611 (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL1Q) || \ 3612 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL2R)) 3613 #endif /*SDMMC2*/ 3614 3615 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 3616 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 3617 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q) || \ 3618 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ 3619 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)) 3620 3621 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ 3622 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ 3623 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ 3624 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2R) || \ 3625 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ 3626 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ 3627 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_CSI)) 3628 3629 #define IS_RCC_DACLPCLKSOURCE(__SOURCE__) \ 3630 (((__SOURCE__) == RCC_DACLPCLKSOURCE_LSI) || \ 3631 ((__SOURCE__) == RCC_DACLPCLKSOURCE_LSE)) 3632 3633 #if defined(OCTOSPI1) 3634 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 3635 (((__SOURCE__) == RCC_OSPICLKSOURCE_HCLK) || \ 3636 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1Q) || \ 3637 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2R) || \ 3638 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 3639 #endif /* OCTOSPI1 */ 3640 3641 #if defined(RCC_CR_PLL3ON) 3642 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3643 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3644 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3645 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ 3646 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3647 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3648 3649 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3650 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3651 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3652 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3P) || \ 3653 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3654 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3655 3656 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3657 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3658 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3659 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3P) || \ 3660 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3661 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3662 #else 3663 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3664 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3665 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3666 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3667 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3668 3669 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3670 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3671 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3672 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3673 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3674 3675 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3676 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3677 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3678 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3679 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3680 3681 #endif /* RCC_CR_PLL3ON */ 3682 3683 #if defined(SPI4) 3684 #define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ 3685 (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ 3686 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2Q) || \ 3687 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3Q) || \ 3688 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 3689 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 3690 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 3691 #endif /* SPI4 */ 3692 3693 #if defined(SPI5) 3694 #define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ 3695 (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK3) || \ 3696 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2Q) || \ 3697 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3Q) || \ 3698 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 3699 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 3700 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 3701 #endif /* SPI5 */ 3702 3703 #if defined(SPI6) 3704 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 3705 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK2) || \ 3706 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ 3707 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ 3708 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 3709 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 3710 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 3711 #endif /* SPI6 */ 3712 3713 #if defined(USB_DRD_FS) 3714 #if defined(RCC_CR_PLL3ON) 3715 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3716 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3717 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL3Q) || \ 3718 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3719 #else 3720 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3721 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3722 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \ 3723 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3724 #endif /* RCC_CR_PLL3ON */ 3725 #endif /* USB_DRD_FS */ 3726 3727 #if defined(CEC) 3728 #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ 3729 (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ 3730 ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ 3731 ((__SOURCE__) == RCC_CECCLKSOURCE_CSI_DIV122)) 3732 #endif /*CEC*/ 3733 3734 #define IS_RCC_TIMPRES(VALUE) \ 3735 (((VALUE) == RCC_TIMPRES_DEACTIVATED) || \ 3736 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 3737 3738 #if defined(CRS) 3739 3740 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 3741 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3742 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 3743 3744 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3745 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3746 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3747 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3748 3749 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3750 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3751 3752 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3753 3754 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3755 3756 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 3757 3758 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3759 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3760 3761 #endif /* CRS */ 3762 3763 /** 3764 * @} 3765 */ 3766 3767 /* Exported functions --------------------------------------------------------*/ 3768 /** @addtogroup RCCEx_Exported_Functions 3769 * @{ 3770 */ 3771 3772 /** @addtogroup RCCEx_Exported_Functions_Group1 3773 * @{ 3774 */ 3775 3776 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3777 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3778 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 3779 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks); 3780 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks); 3781 #if defined(RCC_CR_PLL3ON) 3782 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks); 3783 #endif /* RCC_CR_PLL3ON */ 3784 /** 3785 * @} 3786 */ 3787 3788 /** @addtogroup RCCEx_Exported_Functions_Group2 3789 * @{ 3790 */ 3791 3792 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init); 3793 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 3794 #if defined(RCC_CR_PLL3ON) 3795 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init); 3796 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); 3797 #endif /* RCC_CR_PLL3ON */ 3798 3799 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 3800 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 3801 void HAL_RCCEx_EnableLSECSS(void); 3802 void HAL_RCCEx_DisableLSECSS(void); 3803 void HAL_RCCEx_LSECSS_IRQHandler(void); 3804 void HAL_RCCEx_LSECSS_Callback(void); 3805 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 3806 void HAL_RCCEx_DisableLSCO(void); 3807 /** 3808 * @} 3809 */ 3810 3811 #if defined(CRS) 3812 3813 /** @addtogroup RCCEx_Exported_Functions_Group3 3814 * @{ 3815 */ 3816 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); 3817 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 3818 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 3819 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 3820 void HAL_RCCEx_CRS_IRQHandler(void); 3821 void HAL_RCCEx_CRS_SyncOkCallback(void); 3822 void HAL_RCCEx_CRS_SyncWarnCallback(void); 3823 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 3824 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 3825 /** 3826 * @} 3827 */ 3828 3829 #endif /* CRS */ 3830 3831 /** 3832 * @} 3833 */ 3834 3835 /** 3836 * @} 3837 */ 3838 3839 /** 3840 * @} 3841 */ 3842 3843 #ifdef __cplusplus 3844 } 3845 #endif 3846 3847 #endif /* __STM32H5xx_HAL_RCC_EX_H */ 3848
