1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F4xx_HAL_RCC_EX_H 20 #define __STM32F4xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f4xx_hal_def.h" 28 29 /** @addtogroup STM32F4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 50 and Max_Data = 432 58 except for STM32F411xE devices where the Min_Data = 192 */ 59 60 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 61 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 62 63 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 64 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 65 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 66 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 67 defined(STM32F413xx) || defined(STM32F423xx) 68 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 69 This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx 70 and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 71 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 72 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 73 }RCC_PLLInitTypeDef; 74 75 #if defined(STM32F446xx) 76 /** 77 * @brief PLLI2S Clock structure definition 78 */ 79 typedef struct 80 { 81 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 82 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 83 84 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 85 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 86 87 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. 88 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ 89 90 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 91 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 92 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 93 94 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 95 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 96 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 97 }RCC_PLLI2SInitTypeDef; 98 99 /** 100 * @brief PLLSAI Clock structure definition 101 */ 102 typedef struct 103 { 104 uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. 105 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 106 107 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 108 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 109 110 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. 111 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 112 113 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. 114 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 116 }RCC_PLLSAIInitTypeDef; 117 118 /** 119 * @brief RCC extended clocks structure definition 120 */ 121 typedef struct 122 { 123 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 124 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 125 126 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 127 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 128 129 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 130 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 131 132 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 133 This parameter must be a number between Min_Data = 1 and Max_Data = 32 134 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 135 136 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 137 This parameter must be a number between Min_Data = 1 and Max_Data = 32 138 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 139 140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. 141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 142 143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. 144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 145 146 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 147 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 148 149 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 150 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 151 152 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 153 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 154 155 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 156 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 157 158 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. 159 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 160 161 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 162 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 163 164 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. 165 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 166 167 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 168 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 169 170 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 171 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 172 }RCC_PeriphCLKInitTypeDef; 173 #endif /* STM32F446xx */ 174 175 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 176 /** 177 * @brief RCC extended clocks structure definition 178 */ 179 typedef struct 180 { 181 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 182 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 183 184 uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. 185 This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ 186 187 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 188 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 189 190 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 191 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 192 193 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 194 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 195 196 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 197 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 198 }RCC_PeriphCLKInitTypeDef; 199 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 200 201 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 202 /** 203 * @brief PLLI2S Clock structure definition 204 */ 205 typedef struct 206 { 207 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 208 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 209 210 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 211 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 212 213 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 214 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 215 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 216 217 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 218 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 219 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 220 }RCC_PLLI2SInitTypeDef; 221 222 /** 223 * @brief RCC extended clocks structure definition 224 */ 225 typedef struct 226 { 227 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 228 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 229 230 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 231 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 232 233 #if defined(STM32F413xx) || defined(STM32F423xx) 234 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. 235 This parameter must be a number between Min_Data = 1 and Max_Data = 32 236 This parameter will be used only when PLL is selected as Clock Source SAI */ 237 238 uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. 239 This parameter must be a number between Min_Data = 1 and Max_Data = 32 240 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 241 #endif /* STM32F413xx || STM32F423xx */ 242 243 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 244 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 245 246 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 247 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 248 249 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 250 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 251 252 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 253 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 254 255 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 256 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 257 258 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 259 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 260 261 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. 262 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 263 264 uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. 265 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 266 267 #if defined(STM32F413xx) || defined(STM32F423xx) 268 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. 269 This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ 270 271 uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. 272 This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ 273 274 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 275 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 276 277 uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection 278 This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ 279 280 uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection 281 This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ 282 #endif /* STM32F413xx || STM32F423xx */ 283 284 uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. 285 This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ 286 287 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 288 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 289 }RCC_PeriphCLKInitTypeDef; 290 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 291 292 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 293 294 /** 295 * @brief PLLI2S Clock structure definition 296 */ 297 typedef struct 298 { 299 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 300 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 301 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 302 303 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 304 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 305 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 306 307 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 308 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 309 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 310 }RCC_PLLI2SInitTypeDef; 311 312 /** 313 * @brief PLLSAI Clock structure definition 314 */ 315 typedef struct 316 { 317 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 318 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 319 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 320 #if defined(STM32F469xx) || defined(STM32F479xx) 321 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. 322 This parameter is only available in STM32F469xx/STM32F479xx devices. 323 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 324 #endif /* STM32F469xx || STM32F479xx */ 325 326 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 327 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 328 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 329 330 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 331 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 332 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 333 334 }RCC_PLLSAIInitTypeDef; 335 336 /** 337 * @brief RCC extended clocks structure definition 338 */ 339 typedef struct 340 { 341 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 342 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 343 344 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 345 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 346 347 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 348 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 349 350 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 351 This parameter must be a number between Min_Data = 1 and Max_Data = 32 352 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 353 354 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 355 This parameter must be a number between Min_Data = 1 and Max_Data = 32 356 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 357 358 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 359 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 360 361 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 362 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 363 364 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 365 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 366 #if defined(STM32F469xx) || defined(STM32F479xx) 367 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 368 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 369 370 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 371 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 372 #endif /* STM32F469xx || STM32F479xx */ 373 }RCC_PeriphCLKInitTypeDef; 374 375 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 376 377 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 378 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 379 /** 380 * @brief PLLI2S Clock structure definition 381 */ 382 typedef struct 383 { 384 #if defined(STM32F411xE) 385 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. 386 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ 387 #endif /* STM32F411xE */ 388 389 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 390 This parameter must be a number between Min_Data = 50 and Max_Data = 432 391 Except for STM32F411xE devices where the Min_Data = 192. 392 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 393 394 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 395 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 396 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 397 398 }RCC_PLLI2SInitTypeDef; 399 400 /** 401 * @brief RCC extended clocks structure definition 402 */ 403 typedef struct 404 { 405 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 406 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 407 408 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 409 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 410 411 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 412 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 413 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 414 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 415 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 416 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 417 }RCC_PeriphCLKInitTypeDef; 418 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 419 /** 420 * @} 421 */ 422 423 /* Exported constants --------------------------------------------------------*/ 424 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 425 * @{ 426 */ 427 428 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 429 * @{ 430 */ 431 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ 432 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 433 defined(STM32F413xx) || defined(STM32F423xx) 434 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 435 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 436 #define RCC_PERIPHCLK_TIM 0x00000004U 437 #define RCC_PERIPHCLK_RTC 0x00000008U 438 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U 439 #define RCC_PERIPHCLK_CLK48 0x00000020U 440 #define RCC_PERIPHCLK_SDIO 0x00000040U 441 #define RCC_PERIPHCLK_PLLI2S 0x00000080U 442 #define RCC_PERIPHCLK_DFSDM1 0x00000100U 443 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U 444 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ 445 #if defined(STM32F413xx) || defined(STM32F423xx) 446 #define RCC_PERIPHCLK_DFSDM2 0x00000400U 447 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U 448 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 449 #define RCC_PERIPHCLK_SAIA 0x00002000U 450 #define RCC_PERIPHCLK_SAIB 0x00004000U 451 #endif /* STM32F413xx || STM32F423xx */ 452 /*----------------------------------------------------------------------------*/ 453 454 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ 455 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 456 #define RCC_PERIPHCLK_I2S 0x00000001U 457 #define RCC_PERIPHCLK_TIM 0x00000002U 458 #define RCC_PERIPHCLK_RTC 0x00000004U 459 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U 460 #define RCC_PERIPHCLK_LPTIM1 0x00000010U 461 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 462 /*----------------------------------------------------------------------------*/ 463 464 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ 465 #if defined(STM32F446xx) 466 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 467 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 468 #define RCC_PERIPHCLK_SAI1 0x00000004U 469 #define RCC_PERIPHCLK_SAI2 0x00000008U 470 #define RCC_PERIPHCLK_TIM 0x00000010U 471 #define RCC_PERIPHCLK_RTC 0x00000020U 472 #define RCC_PERIPHCLK_CEC 0x00000040U 473 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U 474 #define RCC_PERIPHCLK_CLK48 0x00000100U 475 #define RCC_PERIPHCLK_SDIO 0x00000200U 476 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U 477 #define RCC_PERIPHCLK_PLLI2S 0x00000800U 478 #endif /* STM32F446xx */ 479 /*-----------------------------------------------------------------------------*/ 480 481 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ 482 #if defined(STM32F469xx) || defined(STM32F479xx) 483 #define RCC_PERIPHCLK_I2S 0x00000001U 484 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 485 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 486 #define RCC_PERIPHCLK_LTDC 0x00000008U 487 #define RCC_PERIPHCLK_TIM 0x00000010U 488 #define RCC_PERIPHCLK_RTC 0x00000020U 489 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 490 #define RCC_PERIPHCLK_CLK48 0x00000080U 491 #define RCC_PERIPHCLK_SDIO 0x00000100U 492 #endif /* STM32F469xx || STM32F479xx */ 493 /*----------------------------------------------------------------------------*/ 494 495 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ 496 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 497 #define RCC_PERIPHCLK_I2S 0x00000001U 498 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 499 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 500 #define RCC_PERIPHCLK_LTDC 0x00000008U 501 #define RCC_PERIPHCLK_TIM 0x00000010U 502 #define RCC_PERIPHCLK_RTC 0x00000020U 503 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 504 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 505 /*----------------------------------------------------------------------------*/ 506 507 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ 508 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ 509 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 510 #define RCC_PERIPHCLK_I2S 0x00000001U 511 #define RCC_PERIPHCLK_RTC 0x00000002U 512 #define RCC_PERIPHCLK_PLLI2S 0x00000004U 513 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 514 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 515 #define RCC_PERIPHCLK_TIM 0x00000008U 516 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 517 /*----------------------------------------------------------------------------*/ 518 /** 519 * @} 520 */ 521 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 522 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 523 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ 524 defined(STM32F479xx) 525 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 526 * @{ 527 */ 528 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U 529 #define RCC_I2SCLKSOURCE_EXT 0x00000001U 530 /** 531 * @} 532 */ 533 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 534 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 535 536 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR 537 * @{ 538 */ 539 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 540 defined(STM32F469xx) || defined(STM32F479xx) 541 #define RCC_PLLSAIDIVR_2 0x00000000U 542 #define RCC_PLLSAIDIVR_4 0x00010000U 543 #define RCC_PLLSAIDIVR_8 0x00020000U 544 #define RCC_PLLSAIDIVR_16 0x00030000U 545 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 546 /** 547 * @} 548 */ 549 550 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider 551 * @{ 552 */ 553 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 554 defined(STM32F412Rx) || defined(STM32F412Cx) 555 #define RCC_PLLI2SP_DIV2 0x00000002U 556 #define RCC_PLLI2SP_DIV4 0x00000004U 557 #define RCC_PLLI2SP_DIV6 0x00000006U 558 #define RCC_PLLI2SP_DIV8 0x00000008U 559 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider 565 * @{ 566 */ 567 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 568 #define RCC_PLLSAIP_DIV2 0x00000002U 569 #define RCC_PLLSAIP_DIV4 0x00000004U 570 #define RCC_PLLSAIP_DIV6 0x00000006U 571 #define RCC_PLLSAIP_DIV8 0x00000008U 572 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ 573 /** 574 * @} 575 */ 576 577 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 578 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source 579 * @{ 580 */ 581 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U 582 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U 583 #define RCC_SAIACLKSOURCE_EXT 0x00200000U 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source 589 * @{ 590 */ 591 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U 592 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U 593 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U 594 /** 595 * @} 596 */ 597 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 598 599 #if defined(STM32F469xx) || defined(STM32F479xx) 600 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 601 * @{ 602 */ 603 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 604 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) 605 /** 606 * @} 607 */ 608 609 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 610 * @{ 611 */ 612 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 613 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) 614 /** 615 * @} 616 */ 617 618 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 619 * @{ 620 */ 621 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 622 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) 623 /** 624 * @} 625 */ 626 #endif /* STM32F469xx || STM32F479xx */ 627 628 #if defined(STM32F446xx) 629 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 630 * @{ 631 */ 632 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U 633 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 634 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 635 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) 636 /** 637 * @} 638 */ 639 640 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source 641 * @{ 642 */ 643 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U 644 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) 645 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) 646 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) 647 /** 648 * @} 649 */ 650 651 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 652 * @{ 653 */ 654 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 655 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 656 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 657 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 658 /** 659 * @} 660 */ 661 662 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 663 * @{ 664 */ 665 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 666 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 667 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 668 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 669 /** 670 * @} 671 */ 672 673 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 674 * @{ 675 */ 676 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 677 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 678 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 679 /** 680 * @} 681 */ 682 683 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 684 * @{ 685 */ 686 #define RCC_CECCLKSOURCE_HSI 0x00000000U 687 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) 688 /** 689 * @} 690 */ 691 692 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 693 * @{ 694 */ 695 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 696 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 697 /** 698 * @} 699 */ 700 701 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 702 * @{ 703 */ 704 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 705 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 706 /** 707 * @} 708 */ 709 710 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source 711 * @{ 712 */ 713 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U 714 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) 715 /** 716 * @} 717 */ 718 719 #endif /* STM32F446xx */ 720 721 #if defined(STM32F413xx) || defined(STM32F423xx) 722 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source 723 * @{ 724 */ 725 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U 726 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 727 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 728 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 729 /** 730 * @} 731 */ 732 733 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source 734 * @{ 735 */ 736 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U 737 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 738 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 739 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 740 /** 741 * @} 742 */ 743 744 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 745 * @{ 746 */ 747 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 748 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 749 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 750 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 751 /** 752 * @} 753 */ 754 755 756 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source 757 * @{ 758 */ 759 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U 760 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 761 /** 762 * @} 763 */ 764 765 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source 766 * @{ 767 */ 768 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U 769 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 770 /** 771 * @} 772 */ 773 774 #endif /* STM32F413xx || STM32F423xx */ 775 776 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 777 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source 778 * @{ 779 */ 780 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U 781 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) 782 /** 783 * @} 784 */ 785 786 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source 787 * @{ 788 */ 789 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U 790 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 791 /** 792 * @} 793 */ 794 795 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source 796 * @{ 797 */ 798 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 799 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 800 /** 801 * @} 802 */ 803 804 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 805 * @{ 806 */ 807 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 808 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 809 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 810 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 811 /** 812 * @} 813 */ 814 815 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 816 * @{ 817 */ 818 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 819 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 820 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 821 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 822 /** 823 * @} 824 */ 825 826 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 827 * @{ 828 */ 829 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 830 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 831 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 832 /** 833 * @} 834 */ 835 836 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 837 * @{ 838 */ 839 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 840 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 841 /** 842 * @} 843 */ 844 845 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 846 * @{ 847 */ 848 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 849 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 850 /** 851 * @} 852 */ 853 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 854 855 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 856 857 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 858 * @{ 859 */ 860 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U 861 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 862 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 863 /** 864 * @} 865 */ 866 867 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 868 * @{ 869 */ 870 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 871 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 872 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 873 /** 874 * @} 875 */ 876 877 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 878 * @{ 879 */ 880 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 881 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 882 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 883 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 884 /** 885 * @} 886 */ 887 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 888 889 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 890 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 891 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 892 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 893 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 894 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 895 * @{ 896 */ 897 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 898 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 899 /** 900 * @} 901 */ 902 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ 903 STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 904 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 905 906 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 907 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 908 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 909 defined(STM32F423xx) 910 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection 911 * @{ 912 */ 913 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 914 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 915 /** 916 * @} 917 */ 918 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ 919 STM32F412Rx || STM32F412Cx */ 920 921 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 922 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 923 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 924 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 925 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 926 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 927 * @{ 928 */ 929 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 930 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 931 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 932 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 933 /** 934 * @} 935 */ 936 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 937 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 938 STM32F412Rx || STM32F413xx | STM32F423xx */ 939 940 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 941 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 942 * @{ 943 */ 944 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 945 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 946 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 947 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 948 /** 949 * @} 950 */ 951 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 952 953 /** 954 * @} 955 */ 956 957 /* Exported macro ------------------------------------------------------------*/ 958 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 959 * @{ 960 */ 961 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ 962 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 963 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 964 * @brief Enables or disables the AHB1 peripheral clock. 965 * @note After reset, the peripheral clock (used for registers read/write access) 966 * is disabled and the application software has to enable this clock before 967 * using it. 968 * @{ 969 */ 970 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 971 __IO uint32_t tmpreg = 0x00U; \ 972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 973 /* Delay after an RCC peripheral clock enabling */ \ 974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 975 UNUSED(tmpreg); \ 976 } while(0U) 977 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 978 __IO uint32_t tmpreg = 0x00U; \ 979 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 980 /* Delay after an RCC peripheral clock enabling */ \ 981 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 982 UNUSED(tmpreg); \ 983 } while(0U) 984 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 985 __IO uint32_t tmpreg = 0x00U; \ 986 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 987 /* Delay after an RCC peripheral clock enabling */ \ 988 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 989 UNUSED(tmpreg); \ 990 } while(0U) 991 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 992 __IO uint32_t tmpreg = 0x00U; \ 993 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 994 /* Delay after an RCC peripheral clock enabling */ \ 995 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 996 UNUSED(tmpreg); \ 997 } while(0U) 998 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 999 __IO uint32_t tmpreg = 0x00U; \ 1000 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1001 /* Delay after an RCC peripheral clock enabling */ \ 1002 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1003 UNUSED(tmpreg); \ 1004 } while(0U) 1005 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 1006 __IO uint32_t tmpreg = 0x00U; \ 1007 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1008 /* Delay after an RCC peripheral clock enabling */ \ 1009 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1010 UNUSED(tmpreg); \ 1011 } while(0U) 1012 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1013 __IO uint32_t tmpreg = 0x00U; \ 1014 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1015 /* Delay after an RCC peripheral clock enabling */ \ 1016 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1017 UNUSED(tmpreg); \ 1018 } while(0U) 1019 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg = 0x00U; \ 1021 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1024 UNUSED(tmpreg); \ 1025 } while(0U) 1026 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 1027 __IO uint32_t tmpreg = 0x00U; \ 1028 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1029 /* Delay after an RCC peripheral clock enabling */ \ 1030 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1031 UNUSED(tmpreg); \ 1032 } while(0U) 1033 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 1034 __IO uint32_t tmpreg = 0x00U; \ 1035 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1036 /* Delay after an RCC peripheral clock enabling */ \ 1037 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1038 UNUSED(tmpreg); \ 1039 } while(0U) 1040 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 1041 __IO uint32_t tmpreg = 0x00U; \ 1042 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1043 /* Delay after an RCC peripheral clock enabling */ \ 1044 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1045 UNUSED(tmpreg); \ 1046 } while(0U) 1047 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 1048 __IO uint32_t tmpreg = 0x00U; \ 1049 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1050 /* Delay after an RCC peripheral clock enabling */ \ 1051 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1052 UNUSED(tmpreg); \ 1053 } while(0U) 1054 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 1055 __IO uint32_t tmpreg = 0x00U; \ 1056 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1057 /* Delay after an RCC peripheral clock enabling */ \ 1058 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1059 UNUSED(tmpreg); \ 1060 } while(0U) 1061 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 1062 __IO uint32_t tmpreg = 0x00U; \ 1063 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1064 /* Delay after an RCC peripheral clock enabling */ \ 1065 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1066 UNUSED(tmpreg); \ 1067 } while(0U) 1068 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 1069 __IO uint32_t tmpreg = 0x00U; \ 1070 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1071 /* Delay after an RCC peripheral clock enabling */ \ 1072 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1073 UNUSED(tmpreg); \ 1074 } while(0U) 1075 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 1076 __IO uint32_t tmpreg = 0x00U; \ 1077 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1078 /* Delay after an RCC peripheral clock enabling */ \ 1079 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1080 UNUSED(tmpreg); \ 1081 } while(0U) 1082 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 1083 __IO uint32_t tmpreg = 0x00U; \ 1084 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1085 /* Delay after an RCC peripheral clock enabling */ \ 1086 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1087 UNUSED(tmpreg); \ 1088 } while(0U) 1089 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 1090 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 1091 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 1092 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 1093 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 1094 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 1095 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 1096 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 1097 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 1098 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 1099 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 1100 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 1101 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 1102 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 1103 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 1104 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 1105 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 1106 1107 /** 1108 * @brief Enable ETHERNET clock. 1109 */ 1110 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 1111 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 1112 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 1113 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 1114 } while(0U) 1115 /** 1116 * @brief Disable ETHERNET clock. 1117 */ 1118 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 1119 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 1120 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 1121 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 1122 } while(0U) 1123 /** 1124 * @} 1125 */ 1126 1127 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 1128 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1129 * @note After reset, the peripheral clock (used for registers read/write access) 1130 * is disabled and the application software has to enable this clock before 1131 * using it. 1132 * @{ 1133 */ 1134 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 1135 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 1136 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 1137 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 1138 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 1139 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 1140 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 1141 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 1142 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 1143 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 1144 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 1145 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 1146 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 1147 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 1148 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 1149 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 1150 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 1151 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 1152 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 1153 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 1154 1155 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 1156 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 1157 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 1158 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 1159 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 1160 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 1161 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 1162 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 1163 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 1164 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 1165 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 1166 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 1167 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 1168 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 1169 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 1170 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 1171 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 1172 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 1173 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 1174 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 1175 /** 1176 * @} 1177 */ 1178 1179 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1180 * @brief Enable or disable the AHB2 peripheral clock. 1181 * @note After reset, the peripheral clock (used for registers read/write access) 1182 * is disabled and the application software has to enable this clock before 1183 * using it. 1184 * @{ 1185 */ 1186 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 1187 __IO uint32_t tmpreg = 0x00U; \ 1188 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1189 /* Delay after an RCC peripheral clock enabling */ \ 1190 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1191 UNUSED(tmpreg); \ 1192 } while(0U) 1193 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 1194 1195 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1196 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 1197 __IO uint32_t tmpreg = 0x00U; \ 1198 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1199 /* Delay after an RCC peripheral clock enabling */ \ 1200 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1201 UNUSED(tmpreg); \ 1202 } while(0U) 1203 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1204 __IO uint32_t tmpreg = 0x00U; \ 1205 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1206 /* Delay after an RCC peripheral clock enabling */ \ 1207 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1208 UNUSED(tmpreg); \ 1209 } while(0U) 1210 1211 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 1212 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 1213 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1214 1215 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 1216 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 1217 }while(0U) 1218 1219 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 1220 1221 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1222 __IO uint32_t tmpreg = 0x00U; \ 1223 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1224 /* Delay after an RCC peripheral clock enabling */ \ 1225 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1226 UNUSED(tmpreg); \ 1227 } while(0U) 1228 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 1229 /** 1230 * @} 1231 */ 1232 1233 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 1234 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1235 * @note After reset, the peripheral clock (used for registers read/write access) 1236 * is disabled and the application software has to enable this clock before 1237 * using it. 1238 * @{ 1239 */ 1240 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 1241 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 1242 1243 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1244 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 1245 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 1246 1247 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 1248 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 1249 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1250 1251 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 1252 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 1253 1254 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 1255 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 1256 /** 1257 * @} 1258 */ 1259 1260 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1261 * @brief Enables or disables the AHB3 peripheral clock. 1262 * @note After reset, the peripheral clock (used for registers read/write access) 1263 * is disabled and the application software has to enable this clock before 1264 * using it. 1265 * @{ 1266 */ 1267 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1268 __IO uint32_t tmpreg = 0x00U; \ 1269 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1270 /* Delay after an RCC peripheral clock enabling */ \ 1271 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1272 UNUSED(tmpreg); \ 1273 } while(0U) 1274 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 1275 #if defined(STM32F469xx) || defined(STM32F479xx) 1276 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 1277 __IO uint32_t tmpreg = 0x00U; \ 1278 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1279 /* Delay after an RCC peripheral clock enabling */ \ 1280 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1281 UNUSED(tmpreg); \ 1282 } while(0U) 1283 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 1284 #endif /* STM32F469xx || STM32F479xx */ 1285 /** 1286 * @} 1287 */ 1288 1289 1290 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 1291 * @brief Get the enable or disable status of the AHB3 peripheral clock. 1292 * @note After reset, the peripheral clock (used for registers read/write access) 1293 * is disabled and the application software has to enable this clock before 1294 * using it. 1295 * @{ 1296 */ 1297 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 1298 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 1299 #if defined(STM32F469xx) || defined(STM32F479xx) 1300 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 1301 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 1302 #endif /* STM32F469xx || STM32F479xx */ 1303 /** 1304 * @} 1305 */ 1306 1307 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1308 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 1309 * @note After reset, the peripheral clock (used for registers read/write access) 1310 * is disabled and the application software has to enable this clock before 1311 * using it. 1312 * @{ 1313 */ 1314 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1315 __IO uint32_t tmpreg = 0x00U; \ 1316 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1317 /* Delay after an RCC peripheral clock enabling */ \ 1318 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1319 UNUSED(tmpreg); \ 1320 } while(0U) 1321 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1322 __IO uint32_t tmpreg = 0x00U; \ 1323 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1324 /* Delay after an RCC peripheral clock enabling */ \ 1325 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1326 UNUSED(tmpreg); \ 1327 } while(0U) 1328 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1329 __IO uint32_t tmpreg = 0x00U; \ 1330 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1331 /* Delay after an RCC peripheral clock enabling */ \ 1332 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1333 UNUSED(tmpreg); \ 1334 } while(0U) 1335 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1336 __IO uint32_t tmpreg = 0x00U; \ 1337 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1338 /* Delay after an RCC peripheral clock enabling */ \ 1339 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1340 UNUSED(tmpreg); \ 1341 } while(0U) 1342 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1343 __IO uint32_t tmpreg = 0x00U; \ 1344 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1345 /* Delay after an RCC peripheral clock enabling */ \ 1346 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1347 UNUSED(tmpreg); \ 1348 } while(0U) 1349 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1350 __IO uint32_t tmpreg = 0x00U; \ 1351 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1352 /* Delay after an RCC peripheral clock enabling */ \ 1353 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1354 UNUSED(tmpreg); \ 1355 } while(0U) 1356 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1357 __IO uint32_t tmpreg = 0x00U; \ 1358 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1359 /* Delay after an RCC peripheral clock enabling */ \ 1360 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1361 UNUSED(tmpreg); \ 1362 } while(0U) 1363 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1364 __IO uint32_t tmpreg = 0x00U; \ 1365 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1366 /* Delay after an RCC peripheral clock enabling */ \ 1367 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1368 UNUSED(tmpreg); \ 1369 } while(0U) 1370 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1371 __IO uint32_t tmpreg = 0x00U; \ 1372 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1373 /* Delay after an RCC peripheral clock enabling */ \ 1374 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1375 UNUSED(tmpreg); \ 1376 } while(0U) 1377 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1378 __IO uint32_t tmpreg = 0x00U; \ 1379 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1380 /* Delay after an RCC peripheral clock enabling */ \ 1381 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1382 UNUSED(tmpreg); \ 1383 } while(0U) 1384 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1385 __IO uint32_t tmpreg = 0x00U; \ 1386 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1387 /* Delay after an RCC peripheral clock enabling */ \ 1388 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1389 UNUSED(tmpreg); \ 1390 } while(0U) 1391 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 1392 __IO uint32_t tmpreg = 0x00U; \ 1393 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1394 /* Delay after an RCC peripheral clock enabling */ \ 1395 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1396 UNUSED(tmpreg); \ 1397 } while(0U) 1398 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1399 __IO uint32_t tmpreg = 0x00U; \ 1400 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1401 /* Delay after an RCC peripheral clock enabling */ \ 1402 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1403 UNUSED(tmpreg); \ 1404 } while(0U) 1405 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1406 __IO uint32_t tmpreg = 0x00U; \ 1407 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1408 /* Delay after an RCC peripheral clock enabling */ \ 1409 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1410 UNUSED(tmpreg); \ 1411 } while(0U) 1412 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1413 __IO uint32_t tmpreg = 0x00U; \ 1414 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1415 /* Delay after an RCC peripheral clock enabling */ \ 1416 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1417 UNUSED(tmpreg); \ 1418 } while(0U) 1419 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1420 __IO uint32_t tmpreg = 0x00U; \ 1421 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1422 /* Delay after an RCC peripheral clock enabling */ \ 1423 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1424 UNUSED(tmpreg); \ 1425 } while(0U) 1426 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1427 __IO uint32_t tmpreg = 0x00U; \ 1428 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1429 /* Delay after an RCC peripheral clock enabling */ \ 1430 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1431 UNUSED(tmpreg); \ 1432 } while(0U) 1433 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1434 __IO uint32_t tmpreg = 0x00U; \ 1435 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1436 /* Delay after an RCC peripheral clock enabling */ \ 1437 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1438 UNUSED(tmpreg); \ 1439 } while(0U) 1440 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1441 __IO uint32_t tmpreg = 0x00U; \ 1442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1443 /* Delay after an RCC peripheral clock enabling */ \ 1444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1445 UNUSED(tmpreg); \ 1446 } while(0U) 1447 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 1448 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 1449 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 1450 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1451 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 1452 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 1453 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 1454 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1455 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1456 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1457 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 1458 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1459 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1460 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 1461 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1462 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 1463 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 1464 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 1465 /** 1466 * @} 1467 */ 1468 1469 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1470 * @brief Get the enable or disable status of the APB1 peripheral clock. 1471 * @note After reset, the peripheral clock (used for registers read/write access) 1472 * is disabled and the application software has to enable this clock before 1473 * using it. 1474 * @{ 1475 */ 1476 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1477 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 1478 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1479 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1480 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 1481 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1482 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1483 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1484 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1485 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1486 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1487 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1488 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1489 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1490 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1491 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1492 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 1493 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 1494 1495 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1496 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 1497 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1498 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1499 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 1500 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1501 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1502 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1503 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1504 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1505 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1506 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1507 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1508 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1509 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1510 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1511 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 1512 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 1513 /** 1514 * @} 1515 */ 1516 1517 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1518 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1519 * @note After reset, the peripheral clock (used for registers read/write access) 1520 * is disabled and the application software has to enable this clock before 1521 * using it. 1522 * @{ 1523 */ 1524 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1525 __IO uint32_t tmpreg = 0x00U; \ 1526 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1527 /* Delay after an RCC peripheral clock enabling */ \ 1528 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1529 UNUSED(tmpreg); \ 1530 } while(0U) 1531 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1532 __IO uint32_t tmpreg = 0x00U; \ 1533 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1534 /* Delay after an RCC peripheral clock enabling */ \ 1535 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1536 UNUSED(tmpreg); \ 1537 } while(0U) 1538 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1539 __IO uint32_t tmpreg = 0x00U; \ 1540 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1541 /* Delay after an RCC peripheral clock enabling */ \ 1542 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1543 UNUSED(tmpreg); \ 1544 } while(0U) 1545 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1546 __IO uint32_t tmpreg = 0x00U; \ 1547 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1548 /* Delay after an RCC peripheral clock enabling */ \ 1549 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1550 UNUSED(tmpreg); \ 1551 } while(0U) 1552 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1553 __IO uint32_t tmpreg = 0x00U; \ 1554 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1555 /* Delay after an RCC peripheral clock enabling */ \ 1556 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1557 UNUSED(tmpreg); \ 1558 } while(0U) 1559 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1560 __IO uint32_t tmpreg = 0x00U; \ 1561 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1562 /* Delay after an RCC peripheral clock enabling */ \ 1563 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1564 UNUSED(tmpreg); \ 1565 } while(0U) 1566 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 1567 __IO uint32_t tmpreg = 0x00U; \ 1568 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1569 /* Delay after an RCC peripheral clock enabling */ \ 1570 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1571 UNUSED(tmpreg); \ 1572 } while(0U) 1573 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1574 __IO uint32_t tmpreg = 0x00U; \ 1575 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1576 /* Delay after an RCC peripheral clock enabling */ \ 1577 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1578 UNUSED(tmpreg); \ 1579 } while(0U) 1580 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1581 __IO uint32_t tmpreg = 0x00U; \ 1582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1583 /* Delay after an RCC peripheral clock enabling */ \ 1584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1585 UNUSED(tmpreg); \ 1586 } while(0U) 1587 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 1588 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 1589 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1590 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1591 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1592 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1593 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 1594 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 1595 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 1596 1597 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1598 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1599 __IO uint32_t tmpreg = 0x00U; \ 1600 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1601 /* Delay after an RCC peripheral clock enabling */ \ 1602 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1603 UNUSED(tmpreg); \ 1604 } while(0U) 1605 1606 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 1607 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1608 1609 #if defined(STM32F469xx) || defined(STM32F479xx) 1610 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1611 __IO uint32_t tmpreg = 0x00U; \ 1612 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1613 /* Delay after an RCC peripheral clock enabling */ \ 1614 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1615 UNUSED(tmpreg); \ 1616 } while(0U) 1617 1618 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 1619 #endif /* STM32F469xx || STM32F479xx */ 1620 /** 1621 * @} 1622 */ 1623 1624 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1625 * @brief Get the enable or disable status of the APB2 peripheral clock. 1626 * @note After reset, the peripheral clock (used for registers read/write access) 1627 * is disabled and the application software has to enable this clock before 1628 * using it. 1629 * @{ 1630 */ 1631 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1632 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1633 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1634 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 1635 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 1636 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 1637 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 1638 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 1639 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) 1640 1641 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 1642 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 1643 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) 1644 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1645 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1646 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1647 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 1648 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 1649 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 1650 1651 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1652 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 1653 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 1654 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1655 1656 #if defined(STM32F469xx) || defined(STM32F479xx) 1657 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 1658 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 1659 #endif /* STM32F469xx || STM32F479xx */ 1660 /** 1661 * @} 1662 */ 1663 1664 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 1665 * @brief Force or release AHB1 peripheral reset. 1666 * @{ 1667 */ 1668 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 1669 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 1670 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 1671 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 1672 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 1673 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 1674 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 1675 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 1676 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 1677 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 1678 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 1679 1680 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 1681 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 1682 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 1683 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 1684 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 1685 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 1686 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 1687 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 1688 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 1689 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 1690 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 1691 /** 1692 * @} 1693 */ 1694 1695 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 1696 * @brief Force or release AHB2 peripheral reset. 1697 * @{ 1698 */ 1699 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 1700 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 1701 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 1702 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 1703 1704 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 1705 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 1706 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 1707 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 1708 1709 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1710 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 1711 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 1712 1713 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 1714 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 1715 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1716 /** 1717 * @} 1718 */ 1719 1720 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 1721 * @brief Force or release AHB3 peripheral reset. 1722 * @{ 1723 */ 1724 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 1725 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 1726 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 1727 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 1728 1729 #if defined(STM32F469xx) || defined(STM32F479xx) 1730 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 1731 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 1732 #endif /* STM32F469xx || STM32F479xx */ 1733 /** 1734 * @} 1735 */ 1736 1737 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 1738 * @brief Force or release APB1 peripheral reset. 1739 * @{ 1740 */ 1741 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1742 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1743 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1744 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1745 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1746 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1747 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1748 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1749 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1750 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1751 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1752 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 1753 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 1754 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1755 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 1756 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1757 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1758 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 1759 1760 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1761 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 1762 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1763 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1764 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 1765 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1766 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1767 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1768 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1769 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1770 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1771 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1772 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1773 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1774 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1775 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1776 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 1777 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 1778 /** 1779 * @} 1780 */ 1781 1782 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 1783 * @brief Force or release APB2 peripheral reset. 1784 * @{ 1785 */ 1786 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1787 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 1788 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 1789 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 1790 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 1791 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 1792 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1793 1794 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 1795 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 1796 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1797 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1798 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 1799 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 1800 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 1801 1802 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1803 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 1804 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 1805 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 1806 1807 #if defined(STM32F469xx) || defined(STM32F479xx) 1808 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 1809 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 1810 #endif /* STM32F469xx || STM32F479xx */ 1811 /** 1812 * @} 1813 */ 1814 1815 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 1816 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1817 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1818 * power consumption. 1819 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1820 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1821 * @{ 1822 */ 1823 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 1824 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 1825 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 1826 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 1827 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 1828 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 1829 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 1830 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 1831 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 1832 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 1833 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 1834 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 1835 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 1836 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 1837 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) 1838 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 1839 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 1840 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 1841 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 1842 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 1843 1844 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 1845 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 1846 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 1847 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 1848 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 1849 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 1850 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 1851 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 1852 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 1853 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 1854 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 1855 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 1856 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 1857 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 1858 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 1859 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 1860 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 1861 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 1862 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 1863 /** 1864 * @} 1865 */ 1866 1867 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 1868 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1869 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1870 * power consumption. 1871 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1872 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1873 * @{ 1874 */ 1875 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 1876 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 1877 1878 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 1879 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 1880 1881 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 1882 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 1883 1884 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1885 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 1886 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 1887 1888 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 1889 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 1890 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1891 /** 1892 * @} 1893 */ 1894 1895 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 1896 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 1897 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1898 * power consumption. 1899 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1900 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1901 * @{ 1902 */ 1903 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 1904 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 1905 1906 #if defined(STM32F469xx) || defined(STM32F479xx) 1907 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 1908 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 1909 #endif /* STM32F469xx || STM32F479xx */ 1910 /** 1911 * @} 1912 */ 1913 1914 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 1915 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1916 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1917 * power consumption. 1918 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1919 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1920 * @{ 1921 */ 1922 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 1923 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 1924 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 1925 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 1926 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 1927 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 1928 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 1929 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 1930 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 1931 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 1932 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 1933 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 1934 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 1935 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 1936 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 1937 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 1938 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 1939 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 1940 1941 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 1942 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 1943 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 1944 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 1945 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 1946 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 1947 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 1948 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 1949 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 1950 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 1951 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 1952 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 1953 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 1954 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 1955 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 1956 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 1957 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 1958 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 1959 /** 1960 * @} 1961 */ 1962 1963 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 1964 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1965 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1966 * power consumption. 1967 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1968 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1969 * @{ 1970 */ 1971 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 1972 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 1973 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 1974 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 1975 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 1976 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 1977 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 1978 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 1979 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 1980 1981 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 1982 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 1983 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 1984 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 1985 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 1986 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 1987 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 1988 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 1989 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 1990 1991 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1992 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 1993 1994 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 1995 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1996 1997 #if defined(STM32F469xx) || defined(STM32F479xx) 1998 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 1999 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 2000 #endif /* STM32F469xx || STM32F479xx */ 2001 /** 2002 * @} 2003 */ 2004 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 2005 /*----------------------------------------------------------------------------*/ 2006 2007 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ 2008 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 2009 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2010 * @brief Enables or disables the AHB1 peripheral clock. 2011 * @note After reset, the peripheral clock (used for registers read/write access) 2012 * is disabled and the application software has to enable this clock before 2013 * using it. 2014 * @{ 2015 */ 2016 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 2017 __IO uint32_t tmpreg = 0x00U; \ 2018 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2019 /* Delay after an RCC peripheral clock enabling */ \ 2020 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2021 UNUSED(tmpreg); \ 2022 } while(0U) 2023 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2024 __IO uint32_t tmpreg = 0x00U; \ 2025 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2026 /* Delay after an RCC peripheral clock enabling */ \ 2027 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2028 UNUSED(tmpreg); \ 2029 } while(0U) 2030 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2031 __IO uint32_t tmpreg = 0x00U; \ 2032 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2033 /* Delay after an RCC peripheral clock enabling */ \ 2034 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2035 UNUSED(tmpreg); \ 2036 } while(0U) 2037 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2038 __IO uint32_t tmpreg = 0x00U; \ 2039 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2040 /* Delay after an RCC peripheral clock enabling */ \ 2041 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2042 UNUSED(tmpreg); \ 2043 } while(0U) 2044 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2045 __IO uint32_t tmpreg = 0x00U; \ 2046 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2047 /* Delay after an RCC peripheral clock enabling */ \ 2048 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2049 UNUSED(tmpreg); \ 2050 } while(0U) 2051 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 2052 __IO uint32_t tmpreg = 0x00U; \ 2053 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2054 /* Delay after an RCC peripheral clock enabling */ \ 2055 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2056 UNUSED(tmpreg); \ 2057 } while(0U) 2058 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 2059 __IO uint32_t tmpreg = 0x00U; \ 2060 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2061 /* Delay after an RCC peripheral clock enabling */ \ 2062 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2063 UNUSED(tmpreg); \ 2064 } while(0U) 2065 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 2066 __IO uint32_t tmpreg = 0x00U; \ 2067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2068 /* Delay after an RCC peripheral clock enabling */ \ 2069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2070 UNUSED(tmpreg); \ 2071 } while(0U) 2072 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 2073 __IO uint32_t tmpreg = 0x00U; \ 2074 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2075 /* Delay after an RCC peripheral clock enabling */ \ 2076 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2077 UNUSED(tmpreg); \ 2078 } while(0U) 2079 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 2080 __IO uint32_t tmpreg = 0x00U; \ 2081 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2082 /* Delay after an RCC peripheral clock enabling */ \ 2083 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2084 UNUSED(tmpreg); \ 2085 } while(0U) 2086 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2087 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2088 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 2089 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 2090 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 2091 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 2092 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 2093 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 2094 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2095 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2096 #if defined(STM32F407xx)|| defined(STM32F417xx) 2097 /** 2098 * @brief Enable ETHERNET clock. 2099 */ 2100 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 2101 __IO uint32_t tmpreg = 0x00U; \ 2102 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2103 /* Delay after an RCC peripheral clock enabling */ \ 2104 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2105 UNUSED(tmpreg); \ 2106 } while(0U) 2107 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 2108 __IO uint32_t tmpreg = 0x00U; \ 2109 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2110 /* Delay after an RCC peripheral clock enabling */ \ 2111 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2112 UNUSED(tmpreg); \ 2113 } while(0U) 2114 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 2115 __IO uint32_t tmpreg = 0x00U; \ 2116 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2117 /* Delay after an RCC peripheral clock enabling */ \ 2118 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2119 UNUSED(tmpreg); \ 2120 } while(0U) 2121 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 2122 __IO uint32_t tmpreg = 0x00U; \ 2123 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2124 /* Delay after an RCC peripheral clock enabling */ \ 2125 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2126 UNUSED(tmpreg); \ 2127 } while(0U) 2128 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 2129 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 2130 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 2131 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 2132 } while(0U) 2133 2134 /** 2135 * @brief Disable ETHERNET clock. 2136 */ 2137 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 2138 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 2139 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 2140 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 2141 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 2142 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 2143 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 2144 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 2145 } while(0U) 2146 #endif /* STM32F407xx || STM32F417xx */ 2147 /** 2148 * @} 2149 */ 2150 2151 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2152 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2153 * @note After reset, the peripheral clock (used for registers read/write access) 2154 * is disabled and the application software has to enable this clock before 2155 * using it. 2156 * @{ 2157 */ 2158 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 2159 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2160 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2161 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2162 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2163 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 2164 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 2165 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 2166 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 2167 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 2168 2169 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2170 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2171 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 2172 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 2173 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 2174 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 2175 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) 2176 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 2177 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2178 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2179 #if defined(STM32F407xx)|| defined(STM32F417xx) 2180 /** 2181 * @brief Enable ETHERNET clock. 2182 */ 2183 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 2184 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 2185 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 2186 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 2187 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 2188 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 2189 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 2190 /** 2191 * @brief Disable ETHERNET clock. 2192 */ 2193 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 2194 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 2195 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 2196 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 2197 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 2198 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 2199 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 2200 #endif /* STM32F407xx || STM32F417xx */ 2201 /** 2202 * @} 2203 */ 2204 2205 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2206 * @brief Enable or disable the AHB2 peripheral clock. 2207 * @note After reset, the peripheral clock (used for registers read/write access) 2208 * is disabled and the application software has to enable this clock before 2209 * using it. 2210 * @{ 2211 */ 2212 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2213 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2214 }while(0U) 2215 2216 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2217 2218 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 2219 __IO uint32_t tmpreg = 0x00U; \ 2220 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2221 /* Delay after an RCC peripheral clock enabling */ \ 2222 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2223 UNUSED(tmpreg); \ 2224 } while(0U) 2225 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 2226 2227 #if defined(STM32F407xx)|| defined(STM32F417xx) 2228 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 2229 __IO uint32_t tmpreg = 0x00U; \ 2230 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2231 /* Delay after an RCC peripheral clock enabling */ \ 2232 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2233 UNUSED(tmpreg); \ 2234 } while(0U) 2235 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 2236 #endif /* STM32F407xx || STM32F417xx */ 2237 2238 #if defined(STM32F415xx) || defined(STM32F417xx) 2239 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 2240 __IO uint32_t tmpreg = 0x00U; \ 2241 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2242 /* Delay after an RCC peripheral clock enabling */ \ 2243 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2244 UNUSED(tmpreg); \ 2245 } while(0U) 2246 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 2247 __IO uint32_t tmpreg = 0x00U; \ 2248 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2249 /* Delay after an RCC peripheral clock enabling */ \ 2250 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2251 UNUSED(tmpreg); \ 2252 } while(0U) 2253 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 2254 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 2255 #endif /* STM32F415xx || STM32F417xx */ 2256 /** 2257 * @} 2258 */ 2259 2260 2261 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2262 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2263 * @note After reset, the peripheral clock (used for registers read/write access) 2264 * is disabled and the application software has to enable this clock before 2265 * using it. 2266 * @{ 2267 */ 2268 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2269 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 2270 2271 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 2272 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 2273 2274 #if defined(STM32F407xx)|| defined(STM32F417xx) 2275 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 2276 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 2277 #endif /* STM32F407xx || STM32F417xx */ 2278 2279 #if defined(STM32F415xx) || defined(STM32F417xx) 2280 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 2281 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 2282 2283 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 2284 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 2285 #endif /* STM32F415xx || STM32F417xx */ 2286 /** 2287 * @} 2288 */ 2289 2290 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 2291 * @brief Enables or disables the AHB3 peripheral clock. 2292 * @note After reset, the peripheral clock (used for registers read/write access) 2293 * is disabled and the application software has to enable this clock before 2294 * using it. 2295 * @{ 2296 */ 2297 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 2298 __IO uint32_t tmpreg = 0x00U; \ 2299 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2300 /* Delay after an RCC peripheral clock enabling */ \ 2301 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2302 UNUSED(tmpreg); \ 2303 } while(0U) 2304 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 2305 /** 2306 * @} 2307 */ 2308 2309 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 2310 * @brief Get the enable or disable status of the AHB3 peripheral clock. 2311 * @note After reset, the peripheral clock (used for registers read/write access) 2312 * is disabled and the application software has to enable this clock before 2313 * using it. 2314 * @{ 2315 */ 2316 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 2317 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 2318 /** 2319 * @} 2320 */ 2321 2322 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 2323 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2324 * @note After reset, the peripheral clock (used for registers read/write access) 2325 * is disabled and the application software has to enable this clock before 2326 * using it. 2327 * @{ 2328 */ 2329 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 2330 __IO uint32_t tmpreg = 0x00U; \ 2331 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2332 /* Delay after an RCC peripheral clock enabling */ \ 2333 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2334 UNUSED(tmpreg); \ 2335 } while(0U) 2336 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 2337 __IO uint32_t tmpreg = 0x00U; \ 2338 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2339 /* Delay after an RCC peripheral clock enabling */ \ 2340 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2341 UNUSED(tmpreg); \ 2342 } while(0U) 2343 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 2344 __IO uint32_t tmpreg = 0x00U; \ 2345 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2346 /* Delay after an RCC peripheral clock enabling */ \ 2347 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2348 UNUSED(tmpreg); \ 2349 } while(0U) 2350 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 2351 __IO uint32_t tmpreg = 0x00U; \ 2352 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2353 /* Delay after an RCC peripheral clock enabling */ \ 2354 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2355 UNUSED(tmpreg); \ 2356 } while(0U) 2357 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 2358 __IO uint32_t tmpreg = 0x00U; \ 2359 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2360 /* Delay after an RCC peripheral clock enabling */ \ 2361 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2362 UNUSED(tmpreg); \ 2363 } while(0U) 2364 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 2365 __IO uint32_t tmpreg = 0x00U; \ 2366 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2367 /* Delay after an RCC peripheral clock enabling */ \ 2368 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2369 UNUSED(tmpreg); \ 2370 } while(0U) 2371 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 2372 __IO uint32_t tmpreg = 0x00U; \ 2373 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2374 /* Delay after an RCC peripheral clock enabling */ \ 2375 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2376 UNUSED(tmpreg); \ 2377 } while(0U) 2378 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 2379 __IO uint32_t tmpreg = 0x00U; \ 2380 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2381 /* Delay after an RCC peripheral clock enabling */ \ 2382 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2383 UNUSED(tmpreg); \ 2384 } while(0U) 2385 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 2386 __IO uint32_t tmpreg = 0x00U; \ 2387 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2388 /* Delay after an RCC peripheral clock enabling */ \ 2389 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2390 UNUSED(tmpreg); \ 2391 } while(0U) 2392 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 2393 __IO uint32_t tmpreg = 0x00U; \ 2394 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2395 /* Delay after an RCC peripheral clock enabling */ \ 2396 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2397 UNUSED(tmpreg); \ 2398 } while(0U) 2399 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 2400 __IO uint32_t tmpreg = 0x00U; \ 2401 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2402 /* Delay after an RCC peripheral clock enabling */ \ 2403 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2404 UNUSED(tmpreg); \ 2405 } while(0U) 2406 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 2407 __IO uint32_t tmpreg = 0x00U; \ 2408 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2409 /* Delay after an RCC peripheral clock enabling */ \ 2410 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2411 UNUSED(tmpreg); \ 2412 } while(0U) 2413 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2414 __IO uint32_t tmpreg = 0x00U; \ 2415 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2416 /* Delay after an RCC peripheral clock enabling */ \ 2417 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2418 UNUSED(tmpreg); \ 2419 } while(0U) 2420 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2421 __IO uint32_t tmpreg = 0x00U; \ 2422 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2423 /* Delay after an RCC peripheral clock enabling */ \ 2424 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2425 UNUSED(tmpreg); \ 2426 } while(0U) 2427 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2428 __IO uint32_t tmpreg = 0x00U; \ 2429 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2430 /* Delay after an RCC peripheral clock enabling */ \ 2431 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2432 UNUSED(tmpreg); \ 2433 } while(0U) 2434 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 2435 __IO uint32_t tmpreg = 0x00U; \ 2436 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2437 /* Delay after an RCC peripheral clock enabling */ \ 2438 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2439 UNUSED(tmpreg); \ 2440 } while(0U) 2441 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 2442 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2443 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 2444 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2445 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 2446 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 2447 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 2448 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 2449 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 2450 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 2451 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 2452 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 2453 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 2454 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 2455 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 2456 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 2457 /** 2458 * @} 2459 */ 2460 2461 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 2462 * @brief Get the enable or disable status of the APB1 peripheral clock. 2463 * @note After reset, the peripheral clock (used for registers read/write access) 2464 * is disabled and the application software has to enable this clock before 2465 * using it. 2466 * @{ 2467 */ 2468 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 2469 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2470 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 2471 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2472 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 2473 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 2474 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 2475 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 2476 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 2477 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 2478 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 2479 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 2480 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 2481 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 2482 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 2483 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 2484 2485 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 2486 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2487 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 2488 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2489 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 2490 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 2491 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 2492 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 2493 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 2494 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 2495 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 2496 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 2497 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 2498 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 2499 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 2500 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 2501 /** 2502 * @} 2503 */ 2504 2505 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 2506 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 2507 * @note After reset, the peripheral clock (used for registers read/write access) 2508 * is disabled and the application software has to enable this clock before 2509 * using it. 2510 * @{ 2511 */ 2512 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 2513 __IO uint32_t tmpreg = 0x00U; \ 2514 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2515 /* Delay after an RCC peripheral clock enabling */ \ 2516 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2517 UNUSED(tmpreg); \ 2518 } while(0U) 2519 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 2520 __IO uint32_t tmpreg = 0x00U; \ 2521 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2522 /* Delay after an RCC peripheral clock enabling */ \ 2523 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2524 UNUSED(tmpreg); \ 2525 } while(0U) 2526 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 2527 __IO uint32_t tmpreg = 0x00U; \ 2528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2529 /* Delay after an RCC peripheral clock enabling */ \ 2530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2531 UNUSED(tmpreg); \ 2532 } while(0U) 2533 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 2534 __IO uint32_t tmpreg = 0x00U; \ 2535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2536 /* Delay after an RCC peripheral clock enabling */ \ 2537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2538 UNUSED(tmpreg); \ 2539 } while(0U) 2540 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 2541 __IO uint32_t tmpreg = 0x00U; \ 2542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2543 /* Delay after an RCC peripheral clock enabling */ \ 2544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2545 UNUSED(tmpreg); \ 2546 } while(0U) 2547 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 2548 __IO uint32_t tmpreg = 0x00U; \ 2549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2550 /* Delay after an RCC peripheral clock enabling */ \ 2551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2552 UNUSED(tmpreg); \ 2553 } while(0U) 2554 2555 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 2556 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 2557 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 2558 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 2559 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 2560 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 2561 /** 2562 * @} 2563 */ 2564 2565 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 2566 * @brief Get the enable or disable status of the APB2 peripheral clock. 2567 * @note After reset, the peripheral clock (used for registers read/write access) 2568 * is disabled and the application software has to enable this clock before 2569 * using it. 2570 * @{ 2571 */ 2572 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 2573 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 2574 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 2575 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 2576 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 2577 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 2578 2579 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 2580 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 2581 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 2582 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 2583 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 2584 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 2585 /** 2586 * @} 2587 */ 2588 2589 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 2590 * @brief Force or release AHB1 peripheral reset. 2591 * @{ 2592 */ 2593 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 2594 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 2595 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 2596 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 2597 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 2598 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 2599 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 2600 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 2601 2602 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 2603 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 2604 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 2605 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 2606 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 2607 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 2608 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 2609 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 2610 /** 2611 * @} 2612 */ 2613 2614 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 2615 * @brief Force or release AHB2 peripheral reset. 2616 * @{ 2617 */ 2618 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 2619 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 2620 2621 #if defined(STM32F407xx)|| defined(STM32F417xx) 2622 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 2623 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 2624 #endif /* STM32F407xx || STM32F417xx */ 2625 2626 #if defined(STM32F415xx) || defined(STM32F417xx) 2627 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 2628 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 2629 2630 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 2631 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 2632 #endif /* STM32F415xx || STM32F417xx */ 2633 2634 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 2635 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 2636 2637 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 2638 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 2639 /** 2640 * @} 2641 */ 2642 2643 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 2644 * @brief Force or release AHB3 peripheral reset. 2645 * @{ 2646 */ 2647 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 2648 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 2649 2650 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 2651 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 2652 /** 2653 * @} 2654 */ 2655 2656 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 2657 * @brief Force or release APB1 peripheral reset. 2658 * @{ 2659 */ 2660 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 2661 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 2662 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 2663 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 2664 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 2665 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 2666 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 2667 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 2668 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 2669 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 2670 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 2671 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 2672 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2673 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 2674 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2675 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 2676 2677 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 2678 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2679 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 2680 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2681 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 2682 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 2683 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 2684 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 2685 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 2686 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 2687 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 2688 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 2689 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 2690 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 2691 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 2692 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 2693 /** 2694 * @} 2695 */ 2696 2697 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 2698 * @brief Force or release APB2 peripheral reset. 2699 * @{ 2700 */ 2701 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 2702 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 2703 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 2704 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 2705 2706 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 2707 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 2708 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 2709 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 2710 /** 2711 * @} 2712 */ 2713 2714 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 2715 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2716 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2717 * power consumption. 2718 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2719 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2720 * @{ 2721 */ 2722 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 2723 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 2724 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 2725 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 2726 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 2727 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 2728 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 2729 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 2730 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 2731 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 2732 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 2733 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 2734 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 2735 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 2736 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 2737 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 2738 2739 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 2740 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 2741 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 2742 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 2743 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 2744 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 2745 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 2746 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 2747 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 2748 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 2749 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 2750 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 2751 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 2752 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 2753 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 2754 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 2755 /** 2756 * @} 2757 */ 2758 2759 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 2760 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2761 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2762 * power consumption. 2763 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 2764 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2765 * @{ 2766 */ 2767 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 2768 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 2769 2770 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 2771 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 2772 2773 #if defined(STM32F407xx)|| defined(STM32F417xx) 2774 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 2775 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 2776 #endif /* STM32F407xx || STM32F417xx */ 2777 2778 #if defined(STM32F415xx) || defined(STM32F417xx) 2779 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 2780 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 2781 2782 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 2783 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 2784 #endif /* STM32F415xx || STM32F417xx */ 2785 /** 2786 * @} 2787 */ 2788 2789 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 2790 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2791 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2792 * power consumption. 2793 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2794 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2795 * @{ 2796 */ 2797 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 2798 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 2799 /** 2800 * @} 2801 */ 2802 2803 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 2804 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2805 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2806 * power consumption. 2807 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2808 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2809 * @{ 2810 */ 2811 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 2812 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 2813 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 2814 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 2815 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 2816 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 2817 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 2818 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 2819 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 2820 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 2821 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 2822 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 2823 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 2824 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 2825 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 2826 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 2827 2828 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 2829 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 2830 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 2831 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 2832 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 2833 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 2834 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 2835 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 2836 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 2837 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 2838 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 2839 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 2840 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 2841 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 2842 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 2843 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 2844 /** 2845 * @} 2846 */ 2847 2848 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 2849 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2850 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2851 * power consumption. 2852 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2853 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2854 * @{ 2855 */ 2856 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 2857 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 2858 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 2859 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 2860 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 2861 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 2862 2863 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 2864 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 2865 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 2866 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 2867 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 2868 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 2869 /** 2870 * @} 2871 */ 2872 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 2873 /*----------------------------------------------------------------------------*/ 2874 2875 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/ 2876 #if defined(STM32F401xC) || defined(STM32F401xE) 2877 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2878 * @brief Enable or disable the AHB1 peripheral clock. 2879 * @note After reset, the peripheral clock (used for registers read/write access) 2880 * is disabled and the application software has to enable this clock before 2881 * using it. 2882 * @{ 2883 */ 2884 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2885 __IO uint32_t tmpreg = 0x00U; \ 2886 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2887 /* Delay after an RCC peripheral clock enabling */ \ 2888 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2889 UNUSED(tmpreg); \ 2890 } while(0U) 2891 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2892 __IO uint32_t tmpreg = 0x00U; \ 2893 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2894 /* Delay after an RCC peripheral clock enabling */ \ 2895 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2896 UNUSED(tmpreg); \ 2897 } while(0U) 2898 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2899 __IO uint32_t tmpreg = 0x00U; \ 2900 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2901 /* Delay after an RCC peripheral clock enabling */ \ 2902 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2903 UNUSED(tmpreg); \ 2904 } while(0U) 2905 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2906 __IO uint32_t tmpreg = 0x00U; \ 2907 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2908 /* Delay after an RCC peripheral clock enabling */ \ 2909 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2910 UNUSED(tmpreg); \ 2911 } while(0U) 2912 2913 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2914 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2915 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2916 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2917 /** 2918 * @} 2919 */ 2920 2921 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2922 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2923 * @note After reset, the peripheral clock (used for registers read/write access) 2924 * is disabled and the application software has to enable this clock before 2925 * using it. 2926 * @{ 2927 */ 2928 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2929 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2930 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2931 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2932 2933 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2934 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2935 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2936 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2937 /** 2938 * @} 2939 */ 2940 2941 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2942 * @brief Enable or disable the AHB2 peripheral clock. 2943 * @note After reset, the peripheral clock (used for registers read/write access) 2944 * is disabled and the application software has to enable this clock before 2945 * using it. 2946 * @{ 2947 */ 2948 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2949 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2950 }while(0U) 2951 2952 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2953 /** 2954 * @} 2955 */ 2956 2957 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2958 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2959 * @note After reset, the peripheral clock (used for registers read/write access) 2960 * is disabled and the application software has to enable this clock before 2961 * using it. 2962 * @{ 2963 */ 2964 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2965 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 2966 /** 2967 * @} 2968 */ 2969 2970 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 2971 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2972 * @note After reset, the peripheral clock (used for registers read/write access) 2973 * is disabled and the application software has to enable this clock before 2974 * using it. 2975 * @{ 2976 */ 2977 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 2978 __IO uint32_t tmpreg = 0x00U; \ 2979 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2980 /* Delay after an RCC peripheral clock enabling */ \ 2981 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2982 UNUSED(tmpreg); \ 2983 } while(0U) 2984 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2985 __IO uint32_t tmpreg = 0x00U; \ 2986 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2987 /* Delay after an RCC peripheral clock enabling */ \ 2988 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2989 UNUSED(tmpreg); \ 2990 } while(0U) 2991 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2992 __IO uint32_t tmpreg = 0x00U; \ 2993 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2994 /* Delay after an RCC peripheral clock enabling */ \ 2995 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2996 UNUSED(tmpreg); \ 2997 } while(0U) 2998 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2999 __IO uint32_t tmpreg = 0x00U; \ 3000 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3001 /* Delay after an RCC peripheral clock enabling */ \ 3002 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3003 UNUSED(tmpreg); \ 3004 } while(0U) 3005 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3006 __IO uint32_t tmpreg = 0x00U; \ 3007 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3008 /* Delay after an RCC peripheral clock enabling */ \ 3009 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3010 UNUSED(tmpreg); \ 3011 } while(0U) 3012 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3013 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3014 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3015 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3016 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3017 /** 3018 * @} 3019 */ 3020 3021 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3022 * @brief Get the enable or disable status of the APB1 peripheral clock. 3023 * @note After reset, the peripheral clock (used for registers read/write access) 3024 * is disabled and the application software has to enable this clock before 3025 * using it. 3026 * @{ 3027 */ 3028 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3029 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3030 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3031 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3032 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3033 3034 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3035 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3036 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3037 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3038 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3039 /** 3040 * @} 3041 */ 3042 3043 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3044 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3045 * @note After reset, the peripheral clock (used for registers read/write access) 3046 * is disabled and the application software has to enable this clock before 3047 * using it. 3048 * @{ 3049 */ 3050 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3051 __IO uint32_t tmpreg = 0x00U; \ 3052 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3053 /* Delay after an RCC peripheral clock enabling */ \ 3054 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3055 UNUSED(tmpreg); \ 3056 } while(0U) 3057 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3058 __IO uint32_t tmpreg = 0x00U; \ 3059 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3060 /* Delay after an RCC peripheral clock enabling */ \ 3061 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3062 UNUSED(tmpreg); \ 3063 } while(0U) 3064 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3065 __IO uint32_t tmpreg = 0x00U; \ 3066 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3067 /* Delay after an RCC peripheral clock enabling */ \ 3068 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3069 UNUSED(tmpreg); \ 3070 } while(0U) 3071 3072 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3073 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3074 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3075 /** 3076 * @} 3077 */ 3078 3079 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3080 * @brief Get the enable or disable status of the APB2 peripheral clock. 3081 * @note After reset, the peripheral clock (used for registers read/write access) 3082 * is disabled and the application software has to enable this clock before 3083 * using it. 3084 * @{ 3085 */ 3086 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3087 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3088 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3089 3090 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3091 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3092 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3093 /** 3094 * @} 3095 */ 3096 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3097 * @brief Force or release AHB1 peripheral reset. 3098 * @{ 3099 */ 3100 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 3101 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3102 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3103 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3104 3105 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 3106 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3107 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3108 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3109 /** 3110 * @} 3111 */ 3112 3113 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3114 * @brief Force or release AHB2 peripheral reset. 3115 * @{ 3116 */ 3117 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 3118 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3119 3120 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3121 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3122 /** 3123 * @} 3124 */ 3125 3126 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3127 * @brief Force or release APB1 peripheral reset. 3128 * @{ 3129 */ 3130 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 3131 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3132 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3133 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3134 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3135 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3136 3137 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 3138 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3139 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3140 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3141 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3142 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3143 /** 3144 * @} 3145 */ 3146 3147 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3148 * @brief Force or release APB2 peripheral reset. 3149 * @{ 3150 */ 3151 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 3152 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3153 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3154 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3155 3156 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 3157 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3158 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3159 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3160 /** 3161 * @} 3162 */ 3163 3164 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3165 * @brief Force or release AHB3 peripheral reset. 3166 * @{ 3167 */ 3168 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3169 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3170 /** 3171 * @} 3172 */ 3173 3174 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3175 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3176 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3177 * power consumption. 3178 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3179 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3180 * @{ 3181 */ 3182 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3183 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3184 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3185 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3186 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3187 3188 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3189 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3190 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3191 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3192 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3193 /** 3194 * @} 3195 */ 3196 3197 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3198 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3199 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3200 * power consumption. 3201 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3202 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3203 * @{ 3204 */ 3205 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3206 3207 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3208 /** 3209 * @} 3210 */ 3211 3212 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3213 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3214 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3215 * power consumption. 3216 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3217 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3218 * @{ 3219 */ 3220 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3221 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3222 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3223 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3224 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3225 3226 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3227 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3228 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3229 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3230 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3231 /** 3232 * @} 3233 */ 3234 3235 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3236 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3237 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3238 * power consumption. 3239 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3240 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3241 * @{ 3242 */ 3243 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3244 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3245 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3246 3247 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3248 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3249 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3250 /** 3251 * @} 3252 */ 3253 #endif /* STM32F401xC || STM32F401xE*/ 3254 /*----------------------------------------------------------------------------*/ 3255 3256 /*-------------------------------- STM32F410xx -------------------------------*/ 3257 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 3258 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3259 * @brief Enables or disables the AHB1 peripheral clock. 3260 * @note After reset, the peripheral clock (used for registers read/write access) 3261 * is disabled and the application software has to enable this clock before 3262 * using it. 3263 * @{ 3264 */ 3265 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3266 __IO uint32_t tmpreg = 0x00U; \ 3267 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3268 /* Delay after an RCC peripheral clock enabling */ \ 3269 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3270 UNUSED(tmpreg); \ 3271 } while(0U) 3272 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 3273 __IO uint32_t tmpreg = 0x00U; \ 3274 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3275 /* Delay after an RCC peripheral clock enabling */ \ 3276 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3277 UNUSED(tmpreg); \ 3278 } while(0U) 3279 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3280 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) 3281 /** 3282 * @} 3283 */ 3284 3285 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3286 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3287 * @note After reset, the peripheral clock (used for registers read/write access) 3288 * is disabled and the application software has to enable this clock before 3289 * using it. 3290 * @{ 3291 */ 3292 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3293 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) 3294 3295 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3296 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 3297 /** 3298 * @} 3299 */ 3300 3301 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3302 * @brief Enable or disable the High Speed APB (APB1) peripheral clock. 3303 * @{ 3304 */ 3305 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 3306 __IO uint32_t tmpreg = 0x00U; \ 3307 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3308 /* Delay after an RCC peripheral clock enabling */ \ 3309 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3310 UNUSED(tmpreg); \ 3311 } while(0U) 3312 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 3313 __IO uint32_t tmpreg = 0x00U; \ 3314 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3315 /* Delay after an RCC peripheral clock enabling */ \ 3316 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3317 UNUSED(tmpreg); \ 3318 } while(0U) 3319 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 3320 __IO uint32_t tmpreg = 0x00U; \ 3321 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3322 /* Delay after an RCC peripheral clock enabling */ \ 3323 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3324 UNUSED(tmpreg); \ 3325 } while(0U) 3326 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 3327 __IO uint32_t tmpreg = 0x00U; \ 3328 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3329 /* Delay after an RCC peripheral clock enabling */ \ 3330 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3331 UNUSED(tmpreg); \ 3332 } while(0U) 3333 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 3334 __IO uint32_t tmpreg = 0x00U; \ 3335 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3336 /* Delay after an RCC peripheral clock enabling */ \ 3337 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3338 UNUSED(tmpreg); \ 3339 } while(0U) 3340 3341 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 3342 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 3343 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 3344 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 3345 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 3346 /** 3347 * @} 3348 */ 3349 3350 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3351 * @brief Get the enable or disable status of the APB1 peripheral clock. 3352 * @note After reset, the peripheral clock (used for registers read/write access) 3353 * is disabled and the application software has to enable this clock before 3354 * using it. 3355 * @{ 3356 */ 3357 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 3358 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 3359 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 3360 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 3361 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 3362 3363 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 3364 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 3365 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 3366 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 3367 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 3368 /** 3369 * @} 3370 */ 3371 3372 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3373 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3374 * @{ 3375 */ 3376 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3377 __IO uint32_t tmpreg = 0x00U; \ 3378 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3379 /* Delay after an RCC peripheral clock enabling */ \ 3380 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3381 UNUSED(tmpreg); \ 3382 } while(0U) 3383 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 3384 __IO uint32_t tmpreg = 0x00U; \ 3385 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3386 /* Delay after an RCC peripheral clock enabling */ \ 3387 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3388 UNUSED(tmpreg); \ 3389 } while(0U) 3390 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3391 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 3392 /** 3393 * @} 3394 */ 3395 3396 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3397 * @brief Get the enable or disable status of the APB2 peripheral clock. 3398 * @note After reset, the peripheral clock (used for registers read/write access) 3399 * is disabled and the application software has to enable this clock before 3400 * using it. 3401 * @{ 3402 */ 3403 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3404 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 3405 3406 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3407 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 3408 /** 3409 * @} 3410 */ 3411 3412 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3413 * @brief Force or release AHB1 peripheral reset. 3414 * @{ 3415 */ 3416 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3417 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) 3418 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3419 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) 3420 /** 3421 * @} 3422 */ 3423 3424 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3425 * @brief Force or release AHB2 peripheral reset. 3426 * @{ 3427 */ 3428 #define __HAL_RCC_AHB2_FORCE_RESET() 3429 #define __HAL_RCC_AHB2_RELEASE_RESET() 3430 /** 3431 * @} 3432 */ 3433 3434 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3435 * @brief Force or release AHB3 peripheral reset. 3436 * @{ 3437 */ 3438 #define __HAL_RCC_AHB3_FORCE_RESET() 3439 #define __HAL_RCC_AHB3_RELEASE_RESET() 3440 /** 3441 * @} 3442 */ 3443 3444 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3445 * @brief Force or release APB1 peripheral reset. 3446 * @{ 3447 */ 3448 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 3449 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 3450 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 3451 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 3452 3453 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 3454 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 3455 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 3456 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 3457 /** 3458 * @} 3459 */ 3460 3461 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3462 * @brief Force or release APB2 peripheral reset. 3463 * @{ 3464 */ 3465 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3466 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3467 /** 3468 * @} 3469 */ 3470 3471 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3472 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3473 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3474 * power consumption. 3475 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3476 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3477 * @{ 3478 */ 3479 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) 3480 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3481 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3482 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3483 3484 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) 3485 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3486 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3487 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3488 /** 3489 * @} 3490 */ 3491 3492 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3493 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3494 * @{ 3495 */ 3496 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 3497 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 3498 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 3499 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 3500 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 3501 3502 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 3503 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 3504 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 3505 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 3506 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 3507 /** 3508 * @} 3509 */ 3510 3511 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3512 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3513 * @{ 3514 */ 3515 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3516 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 3517 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3518 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 3519 /** 3520 * @} 3521 */ 3522 3523 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 3524 /*----------------------------------------------------------------------------*/ 3525 3526 /*-------------------------------- STM32F411xx -------------------------------*/ 3527 #if defined(STM32F411xE) 3528 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3529 * @brief Enables or disables the AHB1 peripheral clock. 3530 * @note After reset, the peripheral clock (used for registers read/write access) 3531 * is disabled and the application software has to enable this clock before 3532 * using it. 3533 * @{ 3534 */ 3535 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3536 __IO uint32_t tmpreg = 0x00U; \ 3537 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3538 /* Delay after an RCC peripheral clock enabling */ \ 3539 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3540 UNUSED(tmpreg); \ 3541 } while(0U) 3542 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3543 __IO uint32_t tmpreg = 0x00U; \ 3544 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3545 /* Delay after an RCC peripheral clock enabling */ \ 3546 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3547 UNUSED(tmpreg); \ 3548 } while(0U) 3549 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3550 __IO uint32_t tmpreg = 0x00U; \ 3551 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3552 /* Delay after an RCC peripheral clock enabling */ \ 3553 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3554 UNUSED(tmpreg); \ 3555 } while(0U) 3556 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3557 __IO uint32_t tmpreg = 0x00U; \ 3558 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3559 /* Delay after an RCC peripheral clock enabling */ \ 3560 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3561 UNUSED(tmpreg); \ 3562 } while(0U) 3563 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 3564 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 3565 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 3566 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3567 /** 3568 * @} 3569 */ 3570 3571 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3572 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3573 * @note After reset, the peripheral clock (used for registers read/write access) 3574 * is disabled and the application software has to enable this clock before 3575 * using it. 3576 * @{ 3577 */ 3578 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 3579 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 3580 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 3581 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3582 3583 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 3584 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 3585 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 3586 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3587 /** 3588 * @} 3589 */ 3590 3591 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 3592 * @brief Enable or disable the AHB2 peripheral clock. 3593 * @note After reset, the peripheral clock (used for registers read/write access) 3594 * is disabled and the application software has to enable this clock before 3595 * using it. 3596 * @{ 3597 */ 3598 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 3599 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 3600 }while(0U) 3601 3602 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 3603 /** 3604 * @} 3605 */ 3606 3607 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 3608 * @brief Get the enable or disable status of the AHB2 peripheral clock. 3609 * @note After reset, the peripheral clock (used for registers read/write access) 3610 * is disabled and the application software has to enable this clock before 3611 * using it. 3612 * @{ 3613 */ 3614 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 3615 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 3616 /** 3617 * @} 3618 */ 3619 3620 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3621 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 3622 * @note After reset, the peripheral clock (used for registers read/write access) 3623 * is disabled and the application software has to enable this clock before 3624 * using it. 3625 * @{ 3626 */ 3627 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 3628 __IO uint32_t tmpreg = 0x00U; \ 3629 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3630 /* Delay after an RCC peripheral clock enabling */ \ 3631 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3632 UNUSED(tmpreg); \ 3633 } while(0U) 3634 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 3635 __IO uint32_t tmpreg = 0x00U; \ 3636 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3637 /* Delay after an RCC peripheral clock enabling */ \ 3638 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3639 UNUSED(tmpreg); \ 3640 } while(0U) 3641 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 3642 __IO uint32_t tmpreg = 0x00U; \ 3643 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3644 /* Delay after an RCC peripheral clock enabling */ \ 3645 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3646 UNUSED(tmpreg); \ 3647 } while(0U) 3648 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 3649 __IO uint32_t tmpreg = 0x00U; \ 3650 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3651 /* Delay after an RCC peripheral clock enabling */ \ 3652 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3653 UNUSED(tmpreg); \ 3654 } while(0U) 3655 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3656 __IO uint32_t tmpreg = 0x00U; \ 3657 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3658 /* Delay after an RCC peripheral clock enabling */ \ 3659 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3660 UNUSED(tmpreg); \ 3661 } while(0U) 3662 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3663 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3664 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3665 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3666 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3667 /** 3668 * @} 3669 */ 3670 3671 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3672 * @brief Get the enable or disable status of the APB1 peripheral clock. 3673 * @note After reset, the peripheral clock (used for registers read/write access) 3674 * is disabled and the application software has to enable this clock before 3675 * using it. 3676 * @{ 3677 */ 3678 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3679 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3680 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3681 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3682 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3683 3684 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3685 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3686 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3687 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3688 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3689 /** 3690 * @} 3691 */ 3692 3693 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3694 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3695 * @{ 3696 */ 3697 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3698 __IO uint32_t tmpreg = 0x00U; \ 3699 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3700 /* Delay after an RCC peripheral clock enabling */ \ 3701 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3702 UNUSED(tmpreg); \ 3703 } while(0U) 3704 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3705 __IO uint32_t tmpreg = 0x00U; \ 3706 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3707 /* Delay after an RCC peripheral clock enabling */ \ 3708 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3709 UNUSED(tmpreg); \ 3710 } while(0U) 3711 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3712 __IO uint32_t tmpreg = 0x00U; \ 3713 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3714 /* Delay after an RCC peripheral clock enabling */ \ 3715 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3716 UNUSED(tmpreg); \ 3717 } while(0U) 3718 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3719 __IO uint32_t tmpreg = 0x00U; \ 3720 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3721 /* Delay after an RCC peripheral clock enabling */ \ 3722 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3723 UNUSED(tmpreg); \ 3724 } while(0U) 3725 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3726 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3727 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3728 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3729 /** 3730 * @} 3731 */ 3732 3733 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3734 * @brief Get the enable or disable status of the APB2 peripheral clock. 3735 * @note After reset, the peripheral clock (used for registers read/write access) 3736 * is disabled and the application software has to enable this clock before 3737 * using it. 3738 * @{ 3739 */ 3740 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3741 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3742 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3743 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3744 3745 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3746 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3747 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3748 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3749 /** 3750 * @} 3751 */ 3752 3753 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3754 * @brief Force or release AHB1 peripheral reset. 3755 * @{ 3756 */ 3757 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3758 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3759 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3760 3761 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3762 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3763 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3764 /** 3765 * @} 3766 */ 3767 3768 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3769 * @brief Force or release AHB2 peripheral reset. 3770 * @{ 3771 */ 3772 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 3773 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3774 3775 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3776 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3777 /** 3778 * @} 3779 */ 3780 3781 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3782 * @brief Force or release AHB3 peripheral reset. 3783 * @{ 3784 */ 3785 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3786 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3787 /** 3788 * @} 3789 */ 3790 3791 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3792 * @brief Force or release APB1 peripheral reset. 3793 * @{ 3794 */ 3795 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3796 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3797 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3798 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3799 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3800 3801 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3802 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3803 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3804 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3805 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3806 /** 3807 * @} 3808 */ 3809 3810 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3811 * @brief Force or release APB2 peripheral reset. 3812 * @{ 3813 */ 3814 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3815 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3816 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3817 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3818 3819 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3820 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3821 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3822 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3823 /** 3824 * @} 3825 */ 3826 3827 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3828 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3829 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3830 * power consumption. 3831 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3832 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3833 * @{ 3834 */ 3835 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3836 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3837 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3838 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3839 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3840 3841 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3842 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3843 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3844 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3845 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3846 /** 3847 * @} 3848 */ 3849 3850 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3851 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3852 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3853 * power consumption. 3854 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3855 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3856 * @{ 3857 */ 3858 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3859 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3860 /** 3861 * @} 3862 */ 3863 3864 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3865 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3866 * @{ 3867 */ 3868 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3869 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3870 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3871 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3872 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3873 3874 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3875 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3876 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3877 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3878 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3879 /** 3880 * @} 3881 */ 3882 3883 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3884 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3885 * @{ 3886 */ 3887 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3888 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3889 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3890 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3891 3892 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3893 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3894 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3895 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3896 /** 3897 * @} 3898 */ 3899 #endif /* STM32F411xE */ 3900 /*----------------------------------------------------------------------------*/ 3901 3902 /*---------------------------------- STM32F446xx -----------------------------*/ 3903 #if defined(STM32F446xx) 3904 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3905 * @brief Enables or disables the AHB1 peripheral clock. 3906 * @note After reset, the peripheral clock (used for registers read/write access) 3907 * is disabled and the application software has to enable this clock before 3908 * using it. 3909 * @{ 3910 */ 3911 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 3912 __IO uint32_t tmpreg = 0x00U; \ 3913 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3914 /* Delay after an RCC peripheral clock enabling */ \ 3915 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3916 UNUSED(tmpreg); \ 3917 } while(0U) 3918 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3919 __IO uint32_t tmpreg = 0x00U; \ 3920 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3921 /* Delay after an RCC peripheral clock enabling */ \ 3922 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3923 UNUSED(tmpreg); \ 3924 } while(0U) 3925 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3926 __IO uint32_t tmpreg = 0x00U; \ 3927 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3928 /* Delay after an RCC peripheral clock enabling */ \ 3929 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3930 UNUSED(tmpreg); \ 3931 } while(0U) 3932 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3933 __IO uint32_t tmpreg = 0x00U; \ 3934 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3935 /* Delay after an RCC peripheral clock enabling */ \ 3936 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3937 UNUSED(tmpreg); \ 3938 } while(0U) 3939 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3940 __IO uint32_t tmpreg = 0x00U; \ 3941 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3942 /* Delay after an RCC peripheral clock enabling */ \ 3943 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3944 UNUSED(tmpreg); \ 3945 } while(0U) 3946 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 3947 __IO uint32_t tmpreg = 0x00U; \ 3948 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 3949 /* Delay after an RCC peripheral clock enabling */ \ 3950 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 3951 UNUSED(tmpreg); \ 3952 } while(0U) 3953 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 3954 __IO uint32_t tmpreg = 0x00U; \ 3955 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 3956 /* Delay after an RCC peripheral clock enabling */ \ 3957 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 3958 UNUSED(tmpreg); \ 3959 } while(0U) 3960 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 3961 __IO uint32_t tmpreg = 0x00U; \ 3962 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 3963 /* Delay after an RCC peripheral clock enabling */ \ 3964 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 3965 UNUSED(tmpreg); \ 3966 } while(0U) 3967 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 3968 __IO uint32_t tmpreg = 0x00U; \ 3969 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 3970 /* Delay after an RCC peripheral clock enabling */ \ 3971 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 3972 UNUSED(tmpreg); \ 3973 } while(0U) 3974 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 3975 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 3976 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 3977 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 3978 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 3979 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 3980 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 3981 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 3982 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3983 /** 3984 * @} 3985 */ 3986 3987 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3988 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3989 * @note After reset, the peripheral clock (used for registers read/write access) 3990 * is disabled and the application software has to enable this clock before 3991 * using it. 3992 * @{ 3993 */ 3994 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 3995 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 3996 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 3997 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 3998 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 3999 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 4000 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 4001 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) 4002 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4003 4004 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4005 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4006 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4007 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4008 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 4009 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 4010 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 4011 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 4012 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4013 /** 4014 * @} 4015 */ 4016 4017 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4018 * @brief Enable or disable the AHB2 peripheral clock. 4019 * @note After reset, the peripheral clock (used for registers read/write access) 4020 * is disabled and the application software has to enable this clock before 4021 * using it. 4022 * @{ 4023 */ 4024 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 4025 __IO uint32_t tmpreg = 0x00U; \ 4026 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4027 /* Delay after an RCC peripheral clock enabling */ \ 4028 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4029 UNUSED(tmpreg); \ 4030 } while(0U) 4031 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 4032 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4033 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4034 }while(0U) 4035 4036 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4037 4038 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4039 __IO uint32_t tmpreg = 0x00U; \ 4040 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4041 /* Delay after an RCC peripheral clock enabling */ \ 4042 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4043 UNUSED(tmpreg); \ 4044 } while(0U) 4045 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4046 /** 4047 * @} 4048 */ 4049 4050 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4051 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4052 * @note After reset, the peripheral clock (used for registers read/write access) 4053 * is disabled and the application software has to enable this clock before 4054 * using it. 4055 * @{ 4056 */ 4057 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 4058 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 4059 4060 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4061 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4062 4063 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4064 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4065 /** 4066 * @} 4067 */ 4068 4069 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4070 * @brief Enables or disables the AHB3 peripheral clock. 4071 * @note After reset, the peripheral clock (used for registers read/write access) 4072 * is disabled and the application software has to enable this clock before 4073 * using it. 4074 * @{ 4075 */ 4076 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 4077 __IO uint32_t tmpreg = 0x00U; \ 4078 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4079 /* Delay after an RCC peripheral clock enabling */ \ 4080 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4081 UNUSED(tmpreg); \ 4082 } while(0U) 4083 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4084 __IO uint32_t tmpreg = 0x00U; \ 4085 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4086 /* Delay after an RCC peripheral clock enabling */ \ 4087 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4088 UNUSED(tmpreg); \ 4089 } while(0U) 4090 4091 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 4092 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4093 /** 4094 * @} 4095 */ 4096 4097 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4098 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4099 * @note After reset, the peripheral clock (used for registers read/write access) 4100 * is disabled and the application software has to enable this clock before 4101 * using it. 4102 * @{ 4103 */ 4104 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 4105 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4106 4107 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 4108 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4109 /** 4110 * @} 4111 */ 4112 4113 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4114 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4115 * @note After reset, the peripheral clock (used for registers read/write access) 4116 * is disabled and the application software has to enable this clock before 4117 * using it. 4118 * @{ 4119 */ 4120 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4121 __IO uint32_t tmpreg = 0x00U; \ 4122 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4123 /* Delay after an RCC peripheral clock enabling */ \ 4124 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4125 UNUSED(tmpreg); \ 4126 } while(0U) 4127 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4128 __IO uint32_t tmpreg = 0x00U; \ 4129 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4130 /* Delay after an RCC peripheral clock enabling */ \ 4131 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4132 UNUSED(tmpreg); \ 4133 } while(0U) 4134 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4135 __IO uint32_t tmpreg = 0x00U; \ 4136 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4137 /* Delay after an RCC peripheral clock enabling */ \ 4138 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4139 UNUSED(tmpreg); \ 4140 } while(0U) 4141 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4142 __IO uint32_t tmpreg = 0x00U; \ 4143 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4144 /* Delay after an RCC peripheral clock enabling */ \ 4145 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4146 UNUSED(tmpreg); \ 4147 } while(0U) 4148 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 4149 __IO uint32_t tmpreg = 0x00U; \ 4150 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4151 /* Delay after an RCC peripheral clock enabling */ \ 4152 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4153 UNUSED(tmpreg); \ 4154 } while(0U) 4155 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 4156 __IO uint32_t tmpreg = 0x00U; \ 4157 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4158 /* Delay after an RCC peripheral clock enabling */ \ 4159 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4160 UNUSED(tmpreg); \ 4161 } while(0U) 4162 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 4163 __IO uint32_t tmpreg = 0x00U; \ 4164 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4165 /* Delay after an RCC peripheral clock enabling */ \ 4166 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4167 UNUSED(tmpreg); \ 4168 } while(0U) 4169 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 4170 __IO uint32_t tmpreg = 0x00U; \ 4171 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4172 /* Delay after an RCC peripheral clock enabling */ \ 4173 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4174 UNUSED(tmpreg); \ 4175 } while(0U) 4176 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 4177 __IO uint32_t tmpreg = 0x00U; \ 4178 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4179 /* Delay after an RCC peripheral clock enabling */ \ 4180 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4181 UNUSED(tmpreg); \ 4182 } while(0U) 4183 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 4184 __IO uint32_t tmpreg = 0x00U; \ 4185 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4186 /* Delay after an RCC peripheral clock enabling */ \ 4187 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4188 UNUSED(tmpreg); \ 4189 } while(0U) 4190 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 4191 __IO uint32_t tmpreg = 0x00U; \ 4192 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4193 /* Delay after an RCC peripheral clock enabling */ \ 4194 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4195 UNUSED(tmpreg); \ 4196 } while(0U) 4197 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 4198 __IO uint32_t tmpreg = 0x00U; \ 4199 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4200 /* Delay after an RCC peripheral clock enabling */ \ 4201 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4202 UNUSED(tmpreg); \ 4203 } while(0U) 4204 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 4205 __IO uint32_t tmpreg = 0x00U; \ 4206 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4207 /* Delay after an RCC peripheral clock enabling */ \ 4208 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4209 UNUSED(tmpreg); \ 4210 } while(0U) 4211 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 4212 __IO uint32_t tmpreg = 0x00U; \ 4213 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4214 /* Delay after an RCC peripheral clock enabling */ \ 4215 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4216 UNUSED(tmpreg); \ 4217 } while(0U) 4218 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 4219 __IO uint32_t tmpreg = 0x00U; \ 4220 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4221 /* Delay after an RCC peripheral clock enabling */ \ 4222 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4223 UNUSED(tmpreg); \ 4224 } while(0U) 4225 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 4226 __IO uint32_t tmpreg = 0x00U; \ 4227 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4228 /* Delay after an RCC peripheral clock enabling */ \ 4229 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4230 UNUSED(tmpreg); \ 4231 } while(0U) 4232 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 4233 __IO uint32_t tmpreg = 0x00U; \ 4234 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4235 /* Delay after an RCC peripheral clock enabling */ \ 4236 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4237 UNUSED(tmpreg); \ 4238 } while(0U) 4239 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 4240 __IO uint32_t tmpreg = 0x00U; \ 4241 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4242 /* Delay after an RCC peripheral clock enabling */ \ 4243 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4244 UNUSED(tmpreg); \ 4245 } while(0U) 4246 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 4247 __IO uint32_t tmpreg = 0x00U; \ 4248 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4249 /* Delay after an RCC peripheral clock enabling */ \ 4250 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4251 UNUSED(tmpreg); \ 4252 } while(0U) 4253 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 4254 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 4255 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 4256 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 4257 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 4258 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 4259 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 4260 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 4261 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 4262 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 4263 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 4264 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 4265 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 4266 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 4267 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 4268 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 4269 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 4270 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 4271 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 4272 /** 4273 * @} 4274 */ 4275 4276 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 4277 * @brief Get the enable or disable status of the APB1 peripheral clock. 4278 * @note After reset, the peripheral clock (used for registers read/write access) 4279 * is disabled and the application software has to enable this clock before 4280 * using it. 4281 * @{ 4282 */ 4283 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 4284 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 4285 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 4286 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 4287 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 4288 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 4289 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 4290 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 4291 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 4292 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 4293 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 4294 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 4295 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 4296 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 4297 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 4298 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 4299 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 4300 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 4301 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 4302 4303 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 4304 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 4305 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 4306 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 4307 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 4308 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 4309 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 4310 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 4311 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 4312 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 4313 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 4314 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 4315 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 4316 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 4317 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 4318 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 4319 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 4320 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 4321 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 4322 /** 4323 * @} 4324 */ 4325 4326 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 4327 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 4328 * @note After reset, the peripheral clock (used for registers read/write access) 4329 * is disabled and the application software has to enable this clock before 4330 * using it. 4331 * @{ 4332 */ 4333 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 4334 __IO uint32_t tmpreg = 0x00U; \ 4335 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4336 /* Delay after an RCC peripheral clock enabling */ \ 4337 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4338 UNUSED(tmpreg); \ 4339 } while(0U) 4340 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 4341 __IO uint32_t tmpreg = 0x00U; \ 4342 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4343 /* Delay after an RCC peripheral clock enabling */ \ 4344 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4345 UNUSED(tmpreg); \ 4346 } while(0U) 4347 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 4348 __IO uint32_t tmpreg = 0x00U; \ 4349 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4350 /* Delay after an RCC peripheral clock enabling */ \ 4351 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4352 UNUSED(tmpreg); \ 4353 } while(0U) 4354 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 4355 __IO uint32_t tmpreg = 0x00U; \ 4356 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4357 /* Delay after an RCC peripheral clock enabling */ \ 4358 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4359 UNUSED(tmpreg); \ 4360 } while(0U) 4361 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 4362 __IO uint32_t tmpreg = 0x00U; \ 4363 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4364 /* Delay after an RCC peripheral clock enabling */ \ 4365 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4366 UNUSED(tmpreg); \ 4367 } while(0U) 4368 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 4369 __IO uint32_t tmpreg = 0x00U; \ 4370 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4371 /* Delay after an RCC peripheral clock enabling */ \ 4372 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4373 UNUSED(tmpreg); \ 4374 } while(0U) 4375 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 4376 __IO uint32_t tmpreg = 0x00U; \ 4377 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4378 /* Delay after an RCC peripheral clock enabling */ \ 4379 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4380 UNUSED(tmpreg); \ 4381 } while(0U) 4382 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 4383 __IO uint32_t tmpreg = 0x00U; \ 4384 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4385 /* Delay after an RCC peripheral clock enabling */ \ 4386 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4387 UNUSED(tmpreg); \ 4388 } while(0U) 4389 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 4390 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 4391 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 4392 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 4393 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 4394 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 4395 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 4396 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 4397 /** 4398 * @} 4399 */ 4400 4401 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 4402 * @brief Get the enable or disable status of the APB2 peripheral clock. 4403 * @note After reset, the peripheral clock (used for registers read/write access) 4404 * is disabled and the application software has to enable this clock before 4405 * using it. 4406 * @{ 4407 */ 4408 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 4409 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 4410 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 4411 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 4412 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 4413 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 4414 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 4415 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 4416 4417 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 4418 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 4419 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 4420 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 4421 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 4422 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 4423 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 4424 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 4425 /** 4426 * @} 4427 */ 4428 4429 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 4430 * @brief Force or release AHB1 peripheral reset. 4431 * @{ 4432 */ 4433 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 4434 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 4435 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 4436 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 4437 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 4438 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 4439 4440 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 4441 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 4442 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 4443 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 4444 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 4445 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 4446 /** 4447 * @} 4448 */ 4449 4450 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 4451 * @brief Force or release AHB2 peripheral reset. 4452 * @{ 4453 */ 4454 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 4455 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 4456 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 4457 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 4458 4459 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 4460 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 4461 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 4462 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 4463 /** 4464 * @} 4465 */ 4466 4467 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 4468 * @brief Force or release AHB3 peripheral reset. 4469 * @{ 4470 */ 4471 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 4472 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 4473 4474 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 4475 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 4476 4477 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 4478 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 4479 /** 4480 * @} 4481 */ 4482 4483 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 4484 * @brief Force or release APB1 peripheral reset. 4485 * @{ 4486 */ 4487 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 4488 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 4489 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 4490 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 4491 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 4492 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 4493 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 4494 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 4495 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 4496 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 4497 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 4498 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 4499 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 4500 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 4501 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 4502 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 4503 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 4504 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 4505 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 4506 4507 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 4508 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 4509 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 4510 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 4511 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 4512 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 4513 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 4514 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 4515 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 4516 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 4517 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 4518 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 4519 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 4520 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 4521 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 4522 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 4523 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 4524 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 4525 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 4526 /** 4527 * @} 4528 */ 4529 4530 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 4531 * @brief Force or release APB2 peripheral reset. 4532 * @{ 4533 */ 4534 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 4535 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 4536 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 4537 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 4538 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 4539 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 4540 4541 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 4542 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 4543 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 4544 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 4545 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 4546 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 4547 /** 4548 * @} 4549 */ 4550 4551 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 4552 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 4553 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4554 * power consumption. 4555 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4556 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4557 * @{ 4558 */ 4559 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 4560 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 4561 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 4562 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 4563 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 4564 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 4565 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 4566 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 4567 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 4568 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 4569 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 4570 4571 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 4572 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 4573 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 4574 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 4575 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 4576 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 4577 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 4578 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 4579 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 4580 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 4581 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 4582 /** 4583 * @} 4584 */ 4585 4586 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 4587 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 4588 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4589 * power consumption. 4590 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 4591 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4592 * @{ 4593 */ 4594 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 4595 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 4596 4597 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 4598 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 4599 4600 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 4601 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 4602 /** 4603 * @} 4604 */ 4605 4606 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 4607 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 4608 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4609 * power consumption. 4610 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4611 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4612 * @{ 4613 */ 4614 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 4615 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 4616 4617 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 4618 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 4619 /** 4620 * @} 4621 */ 4622 4623 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 4624 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 4625 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4626 * power consumption. 4627 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4628 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4629 * @{ 4630 */ 4631 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 4632 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 4633 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 4634 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 4635 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 4636 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 4637 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 4638 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 4639 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 4640 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 4641 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 4642 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 4643 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 4644 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 4645 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 4646 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 4647 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 4648 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 4649 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 4650 4651 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 4652 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 4653 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 4654 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 4655 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 4656 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 4657 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 4658 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 4659 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 4660 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 4661 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 4662 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 4663 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 4664 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 4665 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 4666 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 4667 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 4668 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 4669 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 4670 /** 4671 * @} 4672 */ 4673 4674 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 4675 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 4676 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4677 * power consumption. 4678 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4679 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4680 * @{ 4681 */ 4682 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 4683 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 4684 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 4685 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 4686 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 4687 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 4688 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 4689 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 4690 4691 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 4692 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 4693 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 4694 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 4695 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 4696 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 4697 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 4698 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 4699 /** 4700 * @} 4701 */ 4702 4703 #endif /* STM32F446xx */ 4704 /*----------------------------------------------------------------------------*/ 4705 4706 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ 4707 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 4708 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 4709 * @brief Enables or disables the AHB1 peripheral clock. 4710 * @note After reset, the peripheral clock (used for registers read/write access) 4711 * is disabled and the application software has to enable this clock before 4712 * using it. 4713 * @{ 4714 */ 4715 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4716 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 4717 __IO uint32_t tmpreg = 0x00U; \ 4718 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4719 /* Delay after an RCC peripheral clock enabling */ \ 4720 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4721 UNUSED(tmpreg); \ 4722 } while(0U) 4723 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4724 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4725 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 4726 __IO uint32_t tmpreg = 0x00U; \ 4727 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4728 /* Delay after an RCC peripheral clock enabling */ \ 4729 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4730 UNUSED(tmpreg); \ 4731 } while(0U) 4732 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4733 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4734 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 4735 __IO uint32_t tmpreg = 0x00U; \ 4736 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4737 /* Delay after an RCC peripheral clock enabling */ \ 4738 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4739 UNUSED(tmpreg); \ 4740 } while(0U) 4741 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 4742 __IO uint32_t tmpreg = 0x00U; \ 4743 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4744 /* Delay after an RCC peripheral clock enabling */ \ 4745 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4746 UNUSED(tmpreg); \ 4747 } while(0U) 4748 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4749 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 4750 __IO uint32_t tmpreg = 0x00U; \ 4751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4752 /* Delay after an RCC peripheral clock enabling */ \ 4753 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4754 UNUSED(tmpreg); \ 4755 } while(0U) 4756 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4757 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 4758 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4759 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4760 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 4761 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4762 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4763 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 4764 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 4765 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4766 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 4767 /** 4768 * @} 4769 */ 4770 4771 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 4772 * @brief Get the enable or disable status of the AHB1 peripheral clock. 4773 * @note After reset, the peripheral clock (used for registers read/write access) 4774 * is disabled and the application software has to enable this clock before 4775 * using it. 4776 * @{ 4777 */ 4778 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4779 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 4780 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4781 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4782 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 4783 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4784 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4785 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 4786 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 4787 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4788 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4789 4790 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4791 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4792 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4793 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4794 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4795 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4796 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4797 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4798 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4799 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4800 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4801 /** 4802 * @} 4803 */ 4804 4805 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4806 * @brief Enable or disable the AHB2 peripheral clock. 4807 * @note After reset, the peripheral clock (used for registers read/write access) 4808 * is disabled and the application software has to enable this clock before 4809 * using it. 4810 * @{ 4811 */ 4812 #if defined(STM32F423xx) 4813 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 4814 __IO uint32_t tmpreg = 0x00U; \ 4815 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4816 /* Delay after an RCC peripheral clock enabling */ \ 4817 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4818 UNUSED(tmpreg); \ 4819 } while(0U) 4820 4821 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 4822 #endif /* STM32F423xx */ 4823 4824 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4825 __IO uint32_t tmpreg = 0x00U; \ 4826 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4827 /* Delay after an RCC peripheral clock enabling */ \ 4828 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4829 UNUSED(tmpreg); \ 4830 } while(0U) 4831 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4832 4833 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4834 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4835 }while(0U) 4836 4837 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4838 /** 4839 * @} 4840 */ 4841 4842 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4843 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4844 * @note After reset, the peripheral clock (used for registers read/write access) 4845 * is disabled and the application software has to enable this clock before 4846 * using it. 4847 * @{ 4848 */ 4849 #if defined(STM32F423xx) 4850 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 4851 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 4852 #endif /* STM32F423xx */ 4853 4854 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4855 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4856 4857 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4858 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4859 /** 4860 * @} 4861 */ 4862 4863 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4864 * @brief Enables or disables the AHB3 peripheral clock. 4865 * @note After reset, the peripheral clock (used for registers read/write access) 4866 * is disabled and the application software has to enable this clock before 4867 * using it. 4868 * @{ 4869 */ 4870 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4871 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 4872 __IO uint32_t tmpreg = 0x00U; \ 4873 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4874 /* Delay after an RCC peripheral clock enabling */ \ 4875 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4876 UNUSED(tmpreg); \ 4877 } while(0U) 4878 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4879 __IO uint32_t tmpreg = 0x00U; \ 4880 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4881 /* Delay after an RCC peripheral clock enabling */ \ 4882 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4883 UNUSED(tmpreg); \ 4884 } while(0U) 4885 4886 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 4887 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4888 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4889 /** 4890 * @} 4891 */ 4892 4893 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4894 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4895 * @note After reset, the peripheral clock (used for registers read/write access) 4896 * is disabled and the application software has to enable this clock before 4897 * using it. 4898 * @{ 4899 */ 4900 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4901 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 4902 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4903 4904 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 4905 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4906 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4907 4908 /** 4909 * @} 4910 */ 4911 4912 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4913 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4914 * @note After reset, the peripheral clock (used for registers read/write access) 4915 * is disabled and the application software has to enable this clock before 4916 * using it. 4917 * @{ 4918 */ 4919 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4920 __IO uint32_t tmpreg = 0x00U; \ 4921 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4922 /* Delay after an RCC peripheral clock enabling */ \ 4923 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4924 UNUSED(tmpreg); \ 4925 } while(0U) 4926 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4927 __IO uint32_t tmpreg = 0x00U; \ 4928 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4929 /* Delay after an RCC peripheral clock enabling */ \ 4930 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4931 UNUSED(tmpreg); \ 4932 } while(0U) 4933 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4934 __IO uint32_t tmpreg = 0x00U; \ 4935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4936 /* Delay after an RCC peripheral clock enabling */ \ 4937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4938 UNUSED(tmpreg); \ 4939 } while(0U) 4940 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4941 __IO uint32_t tmpreg = 0x00U; \ 4942 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4943 /* Delay after an RCC peripheral clock enabling */ \ 4944 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4945 UNUSED(tmpreg); \ 4946 } while(0U) 4947 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 4948 __IO uint32_t tmpreg = 0x00U; \ 4949 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4950 /* Delay after an RCC peripheral clock enabling */ \ 4951 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4952 UNUSED(tmpreg); \ 4953 } while(0U) 4954 #if defined(STM32F413xx) || defined(STM32F423xx) 4955 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 4956 __IO uint32_t tmpreg = 0x00U; \ 4957 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 4958 /* Delay after an RCC peripheral clock enabling */ \ 4959 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 4960 UNUSED(tmpreg); \ 4961 } while(0U) 4962 #endif /* STM32F413xx || STM32F423xx */ 4963 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 4964 __IO uint32_t tmpreg = 0x00U; \ 4965 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 4966 /* Delay after an RCC peripheral clock enabling */ \ 4967 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 4968 UNUSED(tmpreg); \ 4969 } while(0U) 4970 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 4971 __IO uint32_t tmpreg = 0x00U; \ 4972 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4973 /* Delay after an RCC peripheral clock enabling */ \ 4974 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4975 UNUSED(tmpreg); \ 4976 } while(0U) 4977 4978 #if defined(STM32F413xx) || defined(STM32F423xx) 4979 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 4980 __IO uint32_t tmpreg = 0x00U; \ 4981 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4982 /* Delay after an RCC peripheral clock enabling */ \ 4983 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4984 UNUSED(tmpreg); \ 4985 } while(0U) 4986 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 4987 __IO uint32_t tmpreg = 0x00U; \ 4988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4989 /* Delay after an RCC peripheral clock enabling */ \ 4990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4991 UNUSED(tmpreg); \ 4992 } while(0U) 4993 #endif /* STM32F413xx || STM32F423xx */ 4994 4995 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 4996 __IO uint32_t tmpreg = 0x00U; \ 4997 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4998 /* Delay after an RCC peripheral clock enabling */ \ 4999 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 5000 UNUSED(tmpreg); \ 5001 } while(0U) 5002 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 5003 __IO uint32_t tmpreg = 0x00U; \ 5004 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5005 /* Delay after an RCC peripheral clock enabling */ \ 5006 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5007 UNUSED(tmpreg); \ 5008 } while(0U) 5009 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 5010 __IO uint32_t tmpreg = 0x00U; \ 5011 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5012 /* Delay after an RCC peripheral clock enabling */ \ 5013 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5014 UNUSED(tmpreg); \ 5015 } while(0U) 5016 #if defined(STM32F413xx) || defined(STM32F423xx) 5017 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 5018 __IO uint32_t tmpreg = 0x00U; \ 5019 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5020 /* Delay after an RCC peripheral clock enabling */ \ 5021 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5022 UNUSED(tmpreg); \ 5023 } while(0U) 5024 #endif /* STM32F413xx || STM32F423xx */ 5025 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 5026 __IO uint32_t tmpreg = 0x00U; \ 5027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5028 /* Delay after an RCC peripheral clock enabling */ \ 5029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5030 UNUSED(tmpreg); \ 5031 } while(0U) 5032 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 5033 __IO uint32_t tmpreg = 0x00U; \ 5034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5035 /* Delay after an RCC peripheral clock enabling */ \ 5036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5037 UNUSED(tmpreg); \ 5038 } while(0U) 5039 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 5040 __IO uint32_t tmpreg = 0x00U; \ 5041 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5042 /* Delay after an RCC peripheral clock enabling */ \ 5043 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5044 UNUSED(tmpreg); \ 5045 } while(0U) 5046 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 5047 __IO uint32_t tmpreg = 0x00U; \ 5048 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5049 /* Delay after an RCC peripheral clock enabling */ \ 5050 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5051 UNUSED(tmpreg); \ 5052 } while(0U) 5053 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 5054 __IO uint32_t tmpreg = 0x00U; \ 5055 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5056 /* Delay after an RCC peripheral clock enabling */ \ 5057 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5058 UNUSED(tmpreg); \ 5059 } while(0U) 5060 #if defined(STM32F413xx) || defined(STM32F423xx) 5061 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 5062 __IO uint32_t tmpreg = 0x00U; \ 5063 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5064 /* Delay after an RCC peripheral clock enabling */ \ 5065 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5066 UNUSED(tmpreg); \ 5067 } while(0U) 5068 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 5069 __IO uint32_t tmpreg = 0x00U; \ 5070 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5071 /* Delay after an RCC peripheral clock enabling */ \ 5072 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5073 UNUSED(tmpreg); \ 5074 } while(0U) 5075 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 5076 __IO uint32_t tmpreg = 0x00U; \ 5077 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5078 /* Delay after an RCC peripheral clock enabling */ \ 5079 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5080 UNUSED(tmpreg); \ 5081 } while(0U) 5082 #endif /* STM32F413xx || STM32F423xx */ 5083 5084 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 5085 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 5086 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 5087 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 5088 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 5089 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 5090 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 5091 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 5092 #if defined(STM32F413xx) || defined(STM32F423xx) 5093 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 5094 #endif /* STM32F413xx || STM32F423xx */ 5095 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 5096 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 5097 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 5098 #if defined(STM32F413xx) || defined(STM32F423xx) 5099 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 5100 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 5101 #endif /* STM32F413xx || STM32F423xx */ 5102 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 5103 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 5104 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 5105 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 5106 #if defined(STM32F413xx) || defined(STM32F423xx) 5107 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 5108 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 5109 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 5110 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 5111 #endif /* STM32F413xx || STM32F423xx */ 5112 5113 /** 5114 * @} 5115 */ 5116 5117 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 5118 * @brief Get the enable or disable status of the APB1 peripheral clock. 5119 * @note After reset, the peripheral clock (used for registers read/write access) 5120 * is disabled and the application software has to enable this clock before 5121 * using it. 5122 * @{ 5123 */ 5124 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 5125 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 5126 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 5127 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 5128 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 5129 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 5130 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 5131 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 5132 #if defined(STM32F413xx) || defined(STM32F423xx) 5133 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 5134 #endif /* STM32F413xx || STM32F423xx */ 5135 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 5136 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 5137 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 5138 #if defined(STM32F413xx) || defined(STM32F423xx) 5139 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 5140 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 5141 #endif /* STM32F413xx || STM32F423xx */ 5142 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 5143 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 5144 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) 5145 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 5146 #if defined(STM32F413xx) || defined(STM32F423xx) 5147 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 5148 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 5149 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 5150 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 5151 #endif /* STM32F413xx || STM32F423xx */ 5152 5153 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 5154 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 5155 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 5156 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 5157 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 5158 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 5159 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 5160 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 5161 #if defined(STM32F413xx) || defined(STM32F423xx) 5162 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 5163 #endif /* STM32F413xx || STM32F423xx */ 5164 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 5165 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 5166 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 5167 #if defined(STM32F413xx) || defined(STM32F423xx) 5168 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 5169 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 5170 #endif /* STM32F413xx || STM32F423xx */ 5171 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 5172 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 5173 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 5174 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 5175 #if defined(STM32F413xx) || defined(STM32F423xx) 5176 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 5177 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 5178 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 5179 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 5180 #endif /* STM32F413xx || STM32F423xx */ 5181 /** 5182 * @} 5183 */ 5184 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 5185 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 5186 * @note After reset, the peripheral clock (used for registers read/write access) 5187 * is disabled and the application software has to enable this clock before 5188 * using it. 5189 * @{ 5190 */ 5191 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 5192 __IO uint32_t tmpreg = 0x00U; \ 5193 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5194 /* Delay after an RCC peripheral clock enabling */ \ 5195 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5196 UNUSED(tmpreg); \ 5197 } while(0U) 5198 #if defined(STM32F413xx) || defined(STM32F423xx) 5199 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 5200 __IO uint32_t tmpreg = 0x00U; \ 5201 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5202 /* Delay after an RCC peripheral clock enabling */ \ 5203 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5204 UNUSED(tmpreg); \ 5205 } while(0U) 5206 #define __HAL_RCC_UART10_CLK_ENABLE() do { \ 5207 __IO uint32_t tmpreg = 0x00U; \ 5208 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5209 /* Delay after an RCC peripheral clock enabling */ \ 5210 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5211 UNUSED(tmpreg); \ 5212 } while(0U) 5213 #endif /* STM32F413xx || STM32F423xx */ 5214 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 5215 __IO uint32_t tmpreg = 0x00U; \ 5216 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5217 /* Delay after an RCC peripheral clock enabling */ \ 5218 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5219 UNUSED(tmpreg); \ 5220 } while(0U) 5221 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 5222 __IO uint32_t tmpreg = 0x00U; \ 5223 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5224 /* Delay after an RCC peripheral clock enabling */ \ 5225 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5226 UNUSED(tmpreg); \ 5227 } while(0U) 5228 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 5229 __IO uint32_t tmpreg = 0x00U; \ 5230 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5231 /* Delay after an RCC peripheral clock enabling */ \ 5232 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5233 UNUSED(tmpreg); \ 5234 } while(0U) 5235 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 5236 __IO uint32_t tmpreg = 0x00U; \ 5237 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5238 /* Delay after an RCC peripheral clock enabling */ \ 5239 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5240 UNUSED(tmpreg); \ 5241 } while(0U) 5242 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 5243 __IO uint32_t tmpreg = 0x00U; \ 5244 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5245 /* Delay after an RCC peripheral clock enabling */ \ 5246 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5247 UNUSED(tmpreg); \ 5248 } while(0U) 5249 #if defined(STM32F413xx) || defined(STM32F423xx) 5250 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 5251 __IO uint32_t tmpreg = 0x00U; \ 5252 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5253 /* Delay after an RCC peripheral clock enabling */ \ 5254 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5255 UNUSED(tmpreg); \ 5256 } while(0U) 5257 #endif /* STM32F413xx || STM32F423xx */ 5258 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 5259 __IO uint32_t tmpreg = 0x00U; \ 5260 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5261 /* Delay after an RCC peripheral clock enabling */ \ 5262 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5263 UNUSED(tmpreg); \ 5264 } while(0U) 5265 #if defined(STM32F413xx) || defined(STM32F423xx) 5266 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 5267 __IO uint32_t tmpreg = 0x00U; \ 5268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5269 /* Delay after an RCC peripheral clock enabling */ \ 5270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5271 UNUSED(tmpreg); \ 5272 } while(0U) 5273 #endif /* STM32F413xx || STM32F423xx */ 5274 5275 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 5276 #if defined(STM32F413xx) || defined(STM32F423xx) 5277 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) 5278 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) 5279 #endif /* STM32F413xx || STM32F423xx */ 5280 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 5281 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 5282 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 5283 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 5284 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 5285 #if defined(STM32F413xx) || defined(STM32F423xx) 5286 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 5287 #endif /* STM32F413xx || STM32F423xx */ 5288 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 5289 #if defined(STM32F413xx) || defined(STM32F423xx) 5290 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) 5291 #endif /* STM32F413xx || STM32F423xx */ 5292 /** 5293 * @} 5294 */ 5295 5296 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 5297 * @brief Get the enable or disable status of the APB2 peripheral clock. 5298 * @note After reset, the peripheral clock (used for registers read/write access) 5299 * is disabled and the application software has to enable this clock before 5300 * using it. 5301 * @{ 5302 */ 5303 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 5304 #if defined(STM32F413xx) || defined(STM32F423xx) 5305 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) 5306 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) 5307 #endif /* STM32F413xx || STM32F423xx */ 5308 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 5309 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 5310 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 5311 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 5312 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 5313 #if defined(STM32F413xx) || defined(STM32F423xx) 5314 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 5315 #endif /* STM32F413xx || STM32F423xx */ 5316 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 5317 #if defined(STM32F413xx) || defined(STM32F423xx) 5318 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) 5319 #endif /* STM32F413xx || STM32F423xx */ 5320 5321 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 5322 #if defined(STM32F413xx) || defined(STM32F423xx) 5323 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 5324 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) 5325 #endif /* STM32F413xx || STM32F423xx */ 5326 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 5327 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 5328 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 5329 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 5330 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 5331 #if defined(STM32F413xx) || defined(STM32F423xx) 5332 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 5333 #endif /* STM32F413xx || STM32F423xx */ 5334 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 5335 #if defined(STM32F413xx) || defined(STM32F423xx) 5336 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) 5337 #endif /* STM32F413xx || STM32F423xx */ 5338 /** 5339 * @} 5340 */ 5341 5342 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 5343 * @brief Force or release AHB1 peripheral reset. 5344 * @{ 5345 */ 5346 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5347 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 5348 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5349 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5350 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 5351 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5352 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5353 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 5354 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 5355 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5356 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 5357 5358 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5359 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 5360 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5361 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5362 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 5363 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5364 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5365 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 5366 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 5367 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5368 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 5369 /** 5370 * @} 5371 */ 5372 5373 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 5374 * @brief Force or release AHB2 peripheral reset. 5375 * @{ 5376 */ 5377 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 5378 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 5379 5380 #if defined(STM32F423xx) 5381 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 5382 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 5383 #endif /* STM32F423xx */ 5384 5385 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 5386 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 5387 5388 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 5389 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 5390 /** 5391 * @} 5392 */ 5393 5394 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 5395 * @brief Force or release AHB3 peripheral reset. 5396 * @{ 5397 */ 5398 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5399 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 5400 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 5401 5402 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 5403 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 5404 5405 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 5406 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 5407 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5408 #if defined(STM32F412Cx) 5409 #define __HAL_RCC_AHB3_FORCE_RESET() 5410 #define __HAL_RCC_AHB3_RELEASE_RESET() 5411 5412 #define __HAL_RCC_FSMC_FORCE_RESET() 5413 #define __HAL_RCC_QSPI_FORCE_RESET() 5414 5415 #define __HAL_RCC_FSMC_RELEASE_RESET() 5416 #define __HAL_RCC_QSPI_RELEASE_RESET() 5417 #endif /* STM32F412Cx */ 5418 /** 5419 * @} 5420 */ 5421 5422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 5423 * @brief Force or release APB1 peripheral reset. 5424 * @{ 5425 */ 5426 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 5427 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 5428 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 5429 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 5430 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 5431 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 5432 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 5433 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 5434 #if defined(STM32F413xx) || defined(STM32F423xx) 5435 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 5436 #endif /* STM32F413xx || STM32F423xx */ 5437 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 5438 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 5439 #if defined(STM32F413xx) || defined(STM32F423xx) 5440 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 5441 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 5442 #endif /* STM32F413xx || STM32F423xx */ 5443 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 5444 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 5445 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 5446 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 5447 #if defined(STM32F413xx) || defined(STM32F423xx) 5448 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 5449 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 5450 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 5451 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 5452 #endif /* STM32F413xx || STM32F423xx */ 5453 5454 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 5455 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 5456 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 5457 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 5458 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 5459 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 5460 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 5461 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 5462 #if defined(STM32F413xx) || defined(STM32F423xx) 5463 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 5464 #endif /* STM32F413xx || STM32F423xx */ 5465 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 5466 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 5467 #if defined(STM32F413xx) || defined(STM32F423xx) 5468 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 5469 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 5470 #endif /* STM32F413xx || STM32F423xx */ 5471 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 5472 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 5473 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 5474 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 5475 #if defined(STM32F413xx) || defined(STM32F423xx) 5476 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 5477 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 5478 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 5479 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 5480 #endif /* STM32F413xx || STM32F423xx */ 5481 /** 5482 * @} 5483 */ 5484 5485 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 5486 * @brief Force or release APB2 peripheral reset. 5487 * @{ 5488 */ 5489 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 5490 #if defined(STM32F413xx) || defined(STM32F423xx) 5491 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) 5492 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) 5493 #endif /* STM32F413xx || STM32F423xx */ 5494 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 5495 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 5496 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 5497 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 5498 #if defined(STM32F413xx) || defined(STM32F423xx) 5499 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 5500 #endif /* STM32F413xx || STM32F423xx */ 5501 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 5502 #if defined(STM32F413xx) || defined(STM32F423xx) 5503 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) 5504 #endif /* STM32F413xx || STM32F423xx */ 5505 5506 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 5507 #if defined(STM32F413xx) || defined(STM32F423xx) 5508 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) 5509 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) 5510 #endif /* STM32F413xx || STM32F423xx */ 5511 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 5512 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 5513 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 5514 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 5515 #if defined(STM32F413xx) || defined(STM32F423xx) 5516 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 5517 #endif /* STM32F413xx || STM32F423xx */ 5518 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 5519 #if defined(STM32F413xx) || defined(STM32F423xx) 5520 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) 5521 #endif /* STM32F413xx || STM32F423xx */ 5522 /** 5523 * @} 5524 */ 5525 5526 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 5527 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 5528 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5529 * power consumption. 5530 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5531 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5532 * @{ 5533 */ 5534 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 5535 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 5536 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 5537 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 5538 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 5539 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 5540 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 5541 #if defined(STM32F413xx) || defined(STM32F423xx) 5542 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 5543 #endif /* STM32F413xx || STM32F423xx */ 5544 5545 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 5546 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 5547 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 5548 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 5549 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 5550 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 5551 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 5552 #if defined(STM32F413xx) || defined(STM32F423xx) 5553 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 5554 #endif /* STM32F413xx || STM32F423xx */ 5555 /** 5556 * @} 5557 */ 5558 5559 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 5560 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 5561 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5562 * power consumption. 5563 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 5564 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5565 * @{ 5566 */ 5567 #if defined(STM32F423xx) 5568 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 5569 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 5570 #endif /* STM32F423xx */ 5571 5572 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 5573 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 5574 5575 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 5576 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 5577 /** 5578 * @} 5579 */ 5580 5581 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 5582 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 5583 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5584 * power consumption. 5585 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5586 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5587 * @{ 5588 */ 5589 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5590 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 5591 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 5592 5593 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 5594 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 5595 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5596 5597 /** 5598 * @} 5599 */ 5600 5601 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 5602 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 5603 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5604 * power consumption. 5605 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5606 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5607 * @{ 5608 */ 5609 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 5610 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 5611 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 5612 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 5613 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 5614 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 5615 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 5616 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 5617 #if defined(STM32F413xx) || defined(STM32F423xx) 5618 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 5619 #endif /* STM32F413xx || STM32F423xx */ 5620 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 5621 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 5622 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 5623 #if defined(STM32F413xx) || defined(STM32F423xx) 5624 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 5625 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 5626 #endif /* STM32F413xx || STM32F423xx */ 5627 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 5628 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 5629 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 5630 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 5631 #if defined(STM32F413xx) || defined(STM32F423xx) 5632 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 5633 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 5634 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 5635 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 5636 #endif /* STM32F413xx || STM32F423xx */ 5637 5638 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 5639 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 5640 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 5641 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 5642 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 5643 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 5644 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 5645 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 5646 #if defined(STM32F413xx) || defined(STM32F423xx) 5647 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 5648 #endif /* STM32F413xx || STM32F423xx */ 5649 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 5650 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 5651 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 5652 #if defined(STM32F413xx) || defined(STM32F423xx) 5653 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 5654 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 5655 #endif /* STM32F413xx || STM32F423xx */ 5656 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 5657 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 5658 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 5659 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 5660 #if defined(STM32F413xx) || defined(STM32F423xx) 5661 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 5662 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 5663 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 5664 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 5665 #endif /* STM32F413xx || STM32F423xx */ 5666 /** 5667 * @} 5668 */ 5669 5670 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 5671 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 5672 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5673 * power consumption. 5674 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5675 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5676 * @{ 5677 */ 5678 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 5679 #if defined(STM32F413xx) || defined(STM32F423xx) 5680 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) 5681 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) 5682 #endif /* STM32F413xx || STM32F423xx */ 5683 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 5684 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 5685 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 5686 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 5687 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 5688 #if defined(STM32F413xx) || defined(STM32F423xx) 5689 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 5690 #endif /* STM32F413xx || STM32F423xx */ 5691 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 5692 #if defined(STM32F413xx) || defined(STM32F423xx) 5693 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) 5694 #endif /* STM32F413xx || STM32F423xx */ 5695 5696 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 5697 #if defined(STM32F413xx) || defined(STM32F423xx) 5698 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) 5699 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) 5700 #endif /* STM32F413xx || STM32F423xx */ 5701 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 5702 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 5703 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 5704 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 5705 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 5706 #if defined(STM32F413xx) || defined(STM32F423xx) 5707 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 5708 #endif /* STM32F413xx || STM32F423xx */ 5709 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 5710 #if defined(STM32F413xx) || defined(STM32F423xx) 5711 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) 5712 #endif /* STM32F413xx || STM32F423xx */ 5713 /** 5714 * @} 5715 */ 5716 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 5717 /*----------------------------------------------------------------------------*/ 5718 5719 /*------------------------------- PLL Configuration --------------------------*/ 5720 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ 5721 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5722 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5723 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5724 * @note This function must be used only when the main PLL is disabled. 5725 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5726 * This parameter can be one of the following values: 5727 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5728 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5729 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5730 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5731 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5732 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5733 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5734 * of 2 MHz to limit PLL jitter. 5735 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5736 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5737 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5738 * output frequency is between 100 and 432 MHz. 5739 * 5740 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5741 * This parameter must be a number in the range {2, 4, 6, or 8}. 5742 * 5743 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5744 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5745 * @note If the USB OTG FS is used in your application, you have to set the 5746 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5747 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5748 * correctly. 5749 * 5750 * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 5751 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5752 * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ 5753 STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 5754 * 5755 */ 5756 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 5757 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 5758 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5759 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5760 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 5761 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 5762 #else 5763 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5764 * @note This function must be used only when the main PLL is disabled. 5765 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5766 * This parameter can be one of the following values: 5767 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5768 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5769 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5770 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5771 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5772 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5773 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5774 * of 2 MHz to limit PLL jitter. 5775 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5776 * This parameter must be a number between Min_Data = 50 and Max_Data = 432 5777 * Except for STM32F411xE devices where Min_Data = 192. 5778 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5779 * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices 5780 * where frequency is between 192 and 432 MHz. 5781 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5782 * This parameter must be a number in the range {2, 4, 6, or 8}. 5783 * 5784 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5785 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5786 * @note If the USB OTG FS is used in your application, you have to set the 5787 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5788 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5789 * correctly. 5790 * 5791 */ 5792 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 5793 (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ 5794 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5795 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5796 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 5797 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 5798 /*----------------------------------------------------------------------------*/ 5799 5800 /*----------------------------PLLI2S Configuration ---------------------------*/ 5801 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 5802 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 5803 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 5804 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5805 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5806 5807 /** @brief Macros to enable or disable the PLLI2S. 5808 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 5809 */ 5810 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 5811 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 5812 5813 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 5814 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 5815 STM32F412Rx || STM32F412Cx */ 5816 #if defined(STM32F446xx) 5817 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5818 * @note This macro must be used only when the PLLI2S is disabled. 5819 * @note PLLI2S clock source is common with the main PLL (configured in 5820 * HAL_RCC_ClockConfig() API). 5821 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5822 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5823 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5824 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5825 * of 1 MHz to limit PLLI2S jitter. 5826 * 5827 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5828 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5829 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5830 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5831 * 5832 * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. 5833 * This parameter must be a number in the range {2, 4, 6, or 8}. 5834 * @note the PLLI2SP parameter is only available with STM32F446xx Devices 5835 * 5836 * @param __PLLI2SR__ specifies the division factor for I2S clock 5837 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5838 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5839 * on the I2S clock frequency. 5840 * 5841 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5842 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5843 */ 5844 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 5845 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5846 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5847 ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 5848 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5849 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5850 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 5851 defined(STM32F413xx) || defined(STM32F423xx) 5852 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5853 * @note This macro must be used only when the PLLI2S is disabled. 5854 * @note PLLI2S clock source is common with the main PLL (configured in 5855 * HAL_RCC_ClockConfig() API). 5856 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5857 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5858 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5859 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5860 * of 1 MHz to limit PLLI2S jitter. 5861 * 5862 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5863 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5864 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5865 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5866 * 5867 * @param __PLLI2SR__ specifies the division factor for I2S clock 5868 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5869 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5870 * on the I2S clock frequency. 5871 * 5872 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5873 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5874 */ 5875 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 5876 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5877 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5878 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5879 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5880 #else 5881 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5882 * @note This macro must be used only when the PLLI2S is disabled. 5883 * @note PLLI2S clock source is common with the main PLL (configured in 5884 * HAL_RCC_ClockConfig() API). 5885 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5886 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5887 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5888 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5889 * 5890 * @param __PLLI2SR__ specifies the division factor for I2S clock 5891 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5892 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5893 * on the I2S clock frequency. 5894 * 5895 */ 5896 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ 5897 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5898 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5899 #endif /* STM32F446xx */ 5900 5901 #if defined(STM32F411xE) 5902 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5903 * @note This macro must be used only when the PLLI2S is disabled. 5904 * @note This macro must be used only when the PLLI2S is disabled. 5905 * @note PLLI2S clock source is common with the main PLL (configured in 5906 * HAL_RCC_ClockConfig() API). 5907 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5908 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5909 * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices 5910 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5911 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5912 * of 2 MHz to limit PLLI2S jitter. 5913 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5914 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 5915 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5916 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 5917 * @param __PLLI2SR__ specifies the division factor for I2S clock 5918 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5919 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5920 * on the I2S clock frequency. 5921 */ 5922 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5923 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5924 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5925 #endif /* STM32F411xE */ 5926 5927 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 5928 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. 5929 * @note This macro must be used only when the PLLI2S is disabled. 5930 * @note PLLI2S clock source is common with the main PLL (configured in 5931 * HAL_RCC_ClockConfig() API) 5932 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 5933 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5934 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5935 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5936 * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. 5937 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5938 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 5939 * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro 5940 * @param __PLLI2SR__ specifies the division factor for I2S clock 5941 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5942 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5943 * on the I2S clock frequency. 5944 */ 5945 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ 5946 ((__PLLI2SQ__) << 24U) |\ 5947 ((__PLLI2SR__) << 28U)) 5948 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 5949 /*----------------------------------------------------------------------------*/ 5950 5951 /*------------------------------ PLLSAI Configuration ------------------------*/ 5952 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 5953 /** @brief Macros to Enable or Disable the PLLISAI. 5954 * @note The PLLSAI is only available with STM32F429x/439x Devices. 5955 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 5956 */ 5957 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) 5958 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) 5959 5960 #if defined(STM32F446xx) 5961 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 5962 * 5963 * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock 5964 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5965 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input 5966 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5967 * of 1 MHz to limit PLLI2S jitter. 5968 * @note The PLLSAIM parameter is only used with STM32F446xx Devices 5969 * 5970 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 5971 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5972 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 5973 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5974 * 5975 * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. 5976 * This parameter must be a number in the range {2, 4, 6, or 8}. 5977 * @note the PLLSAIP parameter is only available with STM32F446xx Devices 5978 * 5979 * @param __PLLSAIQ__ specifies the division factor for SAI clock 5980 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5981 * 5982 * @param __PLLSAIR__ specifies the division factor for LTDC clock 5983 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5984 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 5985 */ 5986 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 5987 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ 5988 ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 5989 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ 5990 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 5991 #endif /* STM32F446xx */ 5992 5993 #if defined(STM32F469xx) || defined(STM32F479xx) 5994 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 5995 * 5996 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 5997 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5998 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 5999 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6000 * 6001 * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. 6002 * This parameter must be a number in the range {2, 4, 6, or 8}. 6003 * 6004 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6005 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6006 * 6007 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6008 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6009 */ 6010 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 6011 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 6012 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 6013 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 6014 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6015 #endif /* STM32F469xx || STM32F479xx */ 6016 6017 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 6018 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 6019 * 6020 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 6021 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6022 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6023 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6024 * 6025 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6026 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6027 * 6028 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6029 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6030 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 6031 */ 6032 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ 6033 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 6034 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ 6035 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6036 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6037 6038 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6039 /*----------------------------------------------------------------------------*/ 6040 6041 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ 6042 #if defined(STM32F413xx) || defined(STM32F423xx) 6043 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6044 * @note This function must be called before enabling the PLLI2S. 6045 * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. 6046 * This parameter must be a number between 1 and 32. 6047 * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 6048 */ 6049 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) 6050 6051 /** @brief Macro to configure the SAI clock Divider coming from PLL. 6052 * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. 6053 * This parameter must be a number between 1 and 32. 6054 * SAI1 clock frequency = f(PLLR) / __PLLDivR__ 6055 */ 6056 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) 6057 #endif /* STM32F413xx || STM32F423xx */ 6058 6059 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 6060 defined(STM32F469xx) || defined(STM32F479xx) 6061 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6062 * @note This function must be called before enabling the PLLI2S. 6063 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. 6064 * This parameter must be a number between 1 and 32. 6065 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 6066 */ 6067 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) 6068 6069 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 6070 * @note This function must be called before enabling the PLLSAI. 6071 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 6072 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 6073 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 6074 */ 6075 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) 6076 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6077 6078 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6079 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 6080 * 6081 * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6082 * @note This function must be called before enabling the PLLSAI. 6083 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 6084 * This parameter must be a number between Min_Data = 2 and Max_Data = 16. 6085 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 6086 */ 6087 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) 6088 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6089 /*----------------------------------------------------------------------------*/ 6090 6091 /*------------------------- Peripheral Clock selection -----------------------*/ 6092 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 6093 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6094 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ 6095 defined(STM32F479xx) 6096 /** @brief Macro to configure the I2S clock source (I2SCLK). 6097 * @note This function must be called before enabling the I2S APB clock. 6098 * @param __SOURCE__ specifies the I2S clock source. 6099 * This parameter can be one of the following values: 6100 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6101 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6102 * used as I2S clock source. 6103 */ 6104 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) 6105 6106 6107 /** @brief Macro to get the I2S clock source (I2SCLK). 6108 * @retval The clock source can be one of the following values: 6109 * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6110 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 6111 * used as I2S clock source 6112 */ 6113 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 6114 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ 6115 6116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6117 6118 /** @brief Macro to configure SAI1BlockA clock source selection. 6119 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6120 * @note This function must be called before enabling PLLSAI, PLLI2S and 6121 * the SAI clock. 6122 * @param __SOURCE__ specifies the SAI Block A clock source. 6123 * This parameter can be one of the following values: 6124 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6125 * as SAI1 Block A clock. 6126 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6127 * as SAI1 Block A clock. 6128 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6129 * used as SAI1 Block A clock. 6130 */ 6131 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6132 6133 /** @brief Macro to configure SAI1BlockB clock source selection. 6134 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6135 * @note This function must be called before enabling PLLSAI, PLLI2S and 6136 * the SAI clock. 6137 * @param __SOURCE__ specifies the SAI Block B clock source. 6138 * This parameter can be one of the following values: 6139 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6140 * as SAI1 Block B clock. 6141 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6142 * as SAI1 Block B clock. 6143 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6144 * used as SAI1 Block B clock. 6145 */ 6146 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6147 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6148 6149 #if defined(STM32F446xx) 6150 /** @brief Macro to configure SAI1 clock source selection. 6151 * @note This configuration is only available with STM32F446xx Devices. 6152 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6153 * the SAI clock. 6154 * @param __SOURCE__ specifies the SAI1 clock source. 6155 * This parameter can be one of the following values: 6156 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6157 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6158 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6159 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6160 */ 6161 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) 6162 6163 /** @brief Macro to Get SAI1 clock source selection. 6164 * @note This configuration is only available with STM32F446xx Devices. 6165 * @retval The clock source can be one of the following values: 6166 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6167 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6168 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6169 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6170 */ 6171 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) 6172 6173 /** @brief Macro to configure SAI2 clock source selection. 6174 * @note This configuration is only available with STM32F446xx Devices. 6175 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6176 * the SAI clock. 6177 * @param __SOURCE__ specifies the SAI2 clock source. 6178 * This parameter can be one of the following values: 6179 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6180 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6181 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6182 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6183 */ 6184 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) 6185 6186 /** @brief Macro to Get SAI2 clock source selection. 6187 * @note This configuration is only available with STM32F446xx Devices. 6188 * @retval The clock source can be one of the following values: 6189 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6190 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6191 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6192 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6193 */ 6194 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) 6195 6196 /** @brief Macro to configure I2S APB1 clock source selection. 6197 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6198 * @param __SOURCE__ specifies the I2S APB1 clock source. 6199 * This parameter can be one of the following values: 6200 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6201 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6202 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6203 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6204 */ 6205 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6206 6207 /** @brief Macro to Get I2S APB1 clock source selection. 6208 * @retval The clock source can be one of the following values: 6209 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6210 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6211 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6212 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6213 */ 6214 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6215 6216 /** @brief Macro to configure I2S APB2 clock source selection. 6217 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6218 * @param __SOURCE__ specifies the SAI Block A clock source. 6219 * This parameter can be one of the following values: 6220 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6221 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6222 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6223 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6224 */ 6225 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6226 6227 /** @brief Macro to Get I2S APB2 clock source selection. 6228 * @retval The clock source can be one of the following values: 6229 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6230 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6231 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6232 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6233 */ 6234 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6235 6236 /** @brief Macro to configure the CEC clock. 6237 * @param __SOURCE__ specifies the CEC clock source. 6238 * This parameter can be one of the following values: 6239 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 6240 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6241 */ 6242 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) 6243 6244 /** @brief Macro to Get the CEC clock. 6245 * @retval The clock source can be one of the following values: 6246 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock 6247 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6248 */ 6249 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) 6250 6251 /** @brief Macro to configure the FMPI2C1 clock. 6252 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6253 * This parameter can be one of the following values: 6254 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6255 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6256 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6257 */ 6258 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6259 6260 /** @brief Macro to Get the FMPI2C1 clock. 6261 * @retval The clock source can be one of the following values: 6262 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6263 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6264 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6265 */ 6266 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6267 6268 /** @brief Macro to configure the CLK48 clock. 6269 * @param __SOURCE__ specifies the CLK48 clock source. 6270 * This parameter can be one of the following values: 6271 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6272 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6273 */ 6274 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6275 6276 /** @brief Macro to Get the CLK48 clock. 6277 * @retval The clock source can be one of the following values: 6278 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6279 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6280 */ 6281 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6282 6283 /** @brief Macro to configure the SDIO clock. 6284 * @param __SOURCE__ specifies the SDIO clock source. 6285 * This parameter can be one of the following values: 6286 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6287 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6288 */ 6289 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6290 6291 /** @brief Macro to Get the SDIO clock. 6292 * @retval The clock source can be one of the following values: 6293 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6294 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6295 */ 6296 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6297 6298 /** @brief Macro to configure the SPDIFRX clock. 6299 * @param __SOURCE__ specifies the SPDIFRX clock source. 6300 * This parameter can be one of the following values: 6301 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6302 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6303 */ 6304 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) 6305 6306 /** @brief Macro to Get the SPDIFRX clock. 6307 * @retval The clock source can be one of the following values: 6308 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6309 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6310 */ 6311 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) 6312 #endif /* STM32F446xx */ 6313 6314 #if defined(STM32F469xx) || defined(STM32F479xx) 6315 6316 /** @brief Macro to configure the CLK48 clock. 6317 * @param __SOURCE__ specifies the CLK48 clock source. 6318 * This parameter can be one of the following values: 6319 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6320 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6321 */ 6322 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) 6323 6324 /** @brief Macro to Get the CLK48 clock. 6325 * @retval The clock source can be one of the following values: 6326 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6327 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6328 */ 6329 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) 6330 6331 /** @brief Macro to configure the SDIO clock. 6332 * @param __SOURCE__ specifies the SDIO clock source. 6333 * This parameter can be one of the following values: 6334 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6335 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6336 */ 6337 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) 6338 6339 /** @brief Macro to Get the SDIO clock. 6340 * @retval The clock source can be one of the following values: 6341 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6342 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6343 */ 6344 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) 6345 6346 /** @brief Macro to configure the DSI clock. 6347 * @param __SOURCE__ specifies the DSI clock source. 6348 * This parameter can be one of the following values: 6349 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6350 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6351 */ 6352 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) 6353 6354 /** @brief Macro to Get the DSI clock. 6355 * @retval The clock source can be one of the following values: 6356 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6357 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6358 */ 6359 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) 6360 6361 #endif /* STM32F469xx || STM32F479xx */ 6362 6363 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6364 defined(STM32F413xx) || defined(STM32F423xx) 6365 /** @brief Macro to configure the DFSDM1 clock. 6366 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 6367 * This parameter can be one of the following values: 6368 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6369 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6370 * @retval None 6371 */ 6372 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 6373 6374 /** @brief Macro to get the DFSDM1 clock source. 6375 * @retval The clock source can be one of the following values: 6376 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6377 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6378 */ 6379 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6380 6381 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6382 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6383 STM32F413xx/STM32F423xx Devices. 6384 * @param __SOURCE__ specifies the DFSDM1 Audio clock source. 6385 * This parameter can be one of the following values: 6386 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6387 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6388 */ 6389 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) 6390 6391 /** @brief Macro to Get DFSDM1 Audio clock source selection. 6392 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6393 STM32F413xx/STM32F423xx Devices. 6394 * @retval The clock source can be one of the following values: 6395 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6396 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6397 */ 6398 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) 6399 6400 #if defined(STM32F413xx) || defined(STM32F423xx) 6401 /** @brief Macro to configure the DFSDM2 clock. 6402 * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. 6403 * This parameter can be one of the following values: 6404 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6405 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6406 * @retval None 6407 */ 6408 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) 6409 6410 /** @brief Macro to get the DFSDM2 clock source. 6411 * @retval The clock source can be one of the following values: 6412 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6413 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6414 */ 6415 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6416 6417 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6418 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6419 * @param __SOURCE__ specifies the DFSDM2 Audio clock source. 6420 * This parameter can be one of the following values: 6421 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6422 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6423 */ 6424 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) 6425 6426 /** @brief Macro to Get DFSDM2 Audio clock source selection. 6427 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6428 * @retval The clock source can be one of the following values: 6429 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6430 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6431 */ 6432 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) 6433 6434 /** @brief Macro to configure SAI1BlockA clock source selection. 6435 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6436 * @note This function must be called before enabling PLLSAI, PLLI2S and 6437 * the SAI clock. 6438 * @param __SOURCE__ specifies the SAI Block A clock source. 6439 * This parameter can be one of the following values: 6440 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6441 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6442 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6443 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6444 */ 6445 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6446 6447 /** @brief Macro to Get SAI1 BlockA clock source selection. 6448 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6449 * @retval The clock source can be one of the following values: 6450 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6451 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6452 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6453 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6454 */ 6455 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) 6456 6457 /** @brief Macro to configure SAI1 BlockB clock source selection. 6458 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6459 * @note This function must be called before enabling PLLSAI, PLLI2S and 6460 * the SAI clock. 6461 * @param __SOURCE__ specifies the SAI Block B clock source. 6462 * This parameter can be one of the following values: 6463 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6464 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6465 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6466 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6467 */ 6468 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6469 6470 /** @brief Macro to Get SAI1 BlockB clock source selection. 6471 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6472 * @retval The clock source can be one of the following values: 6473 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6474 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6475 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6476 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6477 */ 6478 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) 6479 6480 /** @brief Macro to configure the LPTIM1 clock. 6481 * @param __SOURCE__ specifies the LPTIM1 clock source. 6482 * This parameter can be one of the following values: 6483 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6484 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6485 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6486 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6487 */ 6488 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6489 6490 /** @brief Macro to Get the LPTIM1 clock. 6491 * @retval The clock source can be one of the following values: 6492 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6493 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6494 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6495 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6496 */ 6497 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6498 #endif /* STM32F413xx || STM32F423xx */ 6499 6500 /** @brief Macro to configure I2S APB1 clock source selection. 6501 * @param __SOURCE__ specifies the I2S APB1 clock source. 6502 * This parameter can be one of the following values: 6503 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6504 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6505 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6506 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6507 */ 6508 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6509 6510 /** @brief Macro to Get I2S APB1 clock source selection. 6511 * @retval The clock source can be one of the following values: 6512 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6513 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6514 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6515 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6516 */ 6517 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6518 6519 /** @brief Macro to configure I2S APB2 clock source selection. 6520 * @param __SOURCE__ specifies the I2S APB2 clock source. 6521 * This parameter can be one of the following values: 6522 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6523 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6524 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6525 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6526 */ 6527 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6528 6529 /** @brief Macro to Get I2S APB2 clock source selection. 6530 * @retval The clock source can be one of the following values: 6531 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6532 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6533 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6534 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6535 */ 6536 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6537 6538 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). 6539 * @note This macro must be called before enabling the I2S APB clock. 6540 * @param __SOURCE__ specifies the I2S clock source. 6541 * This parameter can be one of the following values: 6542 * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6543 * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6544 * used as I2S clock source. 6545 */ 6546 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) 6547 6548 /** @brief Macro to configure the FMPI2C1 clock. 6549 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6550 * This parameter can be one of the following values: 6551 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6552 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6553 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6554 */ 6555 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6556 6557 /** @brief Macro to Get the FMPI2C1 clock. 6558 * @retval The clock source can be one of the following values: 6559 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6560 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6561 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6562 */ 6563 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6564 6565 /** @brief Macro to configure the CLK48 clock. 6566 * @param __SOURCE__ specifies the CLK48 clock source. 6567 * This parameter can be one of the following values: 6568 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6569 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. 6570 */ 6571 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6572 6573 /** @brief Macro to Get the CLK48 clock. 6574 * @retval The clock source can be one of the following values: 6575 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6576 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock 6577 */ 6578 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6579 6580 /** @brief Macro to configure the SDIO clock. 6581 * @param __SOURCE__ specifies the SDIO clock source. 6582 * This parameter can be one of the following values: 6583 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6584 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6585 */ 6586 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6587 6588 /** @brief Macro to Get the SDIO clock. 6589 * @retval The clock source can be one of the following values: 6590 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6591 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6592 */ 6593 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6594 6595 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6596 6597 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6598 /** @brief Macro to configure I2S clock source selection. 6599 * @param __SOURCE__ specifies the I2S clock source. 6600 * This parameter can be one of the following values: 6601 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6602 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6603 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6604 */ 6605 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) 6606 6607 /** @brief Macro to Get I2S clock source selection. 6608 * @retval The clock source can be one of the following values: 6609 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6610 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6611 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6612 */ 6613 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) 6614 6615 /** @brief Macro to configure the FMPI2C1 clock. 6616 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6617 * This parameter can be one of the following values: 6618 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6619 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6620 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6621 */ 6622 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6623 6624 /** @brief Macro to Get the FMPI2C1 clock. 6625 * @retval The clock source can be one of the following values: 6626 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6627 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6628 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6629 */ 6630 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6631 6632 /** @brief Macro to configure the LPTIM1 clock. 6633 * @param __SOURCE__ specifies the LPTIM1 clock source. 6634 * This parameter can be one of the following values: 6635 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6636 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6637 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6638 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6639 */ 6640 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6641 6642 /** @brief Macro to Get the LPTIM1 clock. 6643 * @retval The clock source can be one of the following values: 6644 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6645 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6646 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6647 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6648 */ 6649 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6650 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6651 6652 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6653 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 6654 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6655 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6656 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6657 /** @brief Macro to configure the Timers clocks prescalers 6658 * @note This feature is only available with STM32F429x/439x Devices. 6659 * @param __PRESC__ specifies the Timers clocks prescalers selection 6660 * This parameter can be one of the following values: 6661 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 6662 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 6663 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 6664 * division by 4 or more. 6665 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 6666 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 6667 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 6668 * to division by 8 or more. 6669 */ 6670 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) 6671 6672 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ 6673 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ 6674 STM32F423xx */ 6675 6676 /*----------------------------------------------------------------------------*/ 6677 6678 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6679 /** @brief Enable PLLSAI_RDY interrupt. 6680 */ 6681 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 6682 6683 /** @brief Disable PLLSAI_RDY interrupt. 6684 */ 6685 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 6686 6687 /** @brief Clear the PLLSAI RDY interrupt pending bits. 6688 */ 6689 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 6690 6691 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 6692 * @retval The new state (TRUE or FALSE). 6693 */ 6694 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 6695 6696 /** @brief Check PLLSAI RDY flag is set or not. 6697 * @retval The new state (TRUE or FALSE). 6698 */ 6699 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 6700 6701 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6702 6703 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6704 /** @brief Macros to enable or disable the RCC MCO1 feature. 6705 */ 6706 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) 6707 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) 6708 6709 /** @brief Macros to enable or disable the RCC MCO2 feature. 6710 */ 6711 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) 6712 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) 6713 6714 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6715 6716 /** 6717 * @} 6718 */ 6719 6720 /* Exported functions --------------------------------------------------------*/ 6721 /** @addtogroup RCCEx_Exported_Functions 6722 * @{ 6723 */ 6724 6725 /** @addtogroup RCCEx_Exported_Functions_Group1 6726 * @{ 6727 */ 6728 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6729 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6730 6731 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 6732 6733 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 6734 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 6735 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 6736 defined(STM32F423xx) 6737 void HAL_RCCEx_SelectLSEMode(uint8_t Mode); 6738 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6739 #if defined(RCC_PLLI2S_SUPPORT) 6740 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 6741 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 6742 #endif /* RCC_PLLI2S_SUPPORT */ 6743 #if defined(RCC_PLLSAI_SUPPORT) 6744 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 6745 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 6746 #endif /* RCC_PLLSAI_SUPPORT */ 6747 /** 6748 * @} 6749 */ 6750 6751 /** 6752 * @} 6753 */ 6754 /* Private types -------------------------------------------------------------*/ 6755 /* Private variables ---------------------------------------------------------*/ 6756 /* Private constants ---------------------------------------------------------*/ 6757 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 6758 * @{ 6759 */ 6760 6761 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 6762 * @brief RCC registers bit address in the alias region 6763 * @{ 6764 */ 6765 /* --- CR Register ---*/ 6766 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6767 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6768 /* Alias word address of PLLSAION bit */ 6769 #define RCC_PLLSAION_BIT_NUMBER 0x1CU 6770 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) 6771 6772 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6773 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6774 6775 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6776 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6777 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6778 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6779 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6780 /* Alias word address of PLLI2SON bit */ 6781 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 6782 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 6783 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6784 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 6785 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6786 6787 /* --- DCKCFGR Register ---*/ 6788 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6789 defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ 6790 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6791 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6792 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6793 /* Alias word address of TIMPRE bit */ 6794 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) 6795 #define RCC_TIMPRE_BIT_NUMBER 0x18U 6796 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) 6797 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ 6798 STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 6799 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6800 6801 /* --- CFGR Register ---*/ 6802 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 6803 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6804 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6805 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6806 defined(STM32F469xx) || defined(STM32F479xx) 6807 /* Alias word address of I2SSRC bit */ 6808 #define RCC_I2SSRC_BIT_NUMBER 0x17U 6809 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 6810 6811 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6812 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6813 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ 6814 6815 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6816 defined(STM32F413xx) || defined(STM32F423xx) 6817 /* --- PLLI2SCFGR Register ---*/ 6818 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) 6819 /* Alias word address of PLLI2SSRC bit */ 6820 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U 6821 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) 6822 6823 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6824 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ 6825 6826 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6827 /* Alias word address of MCO1EN bit */ 6828 #define RCC_MCO1EN_BIT_NUMBER 0x8U 6829 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) 6830 6831 /* Alias word address of MCO2EN bit */ 6832 #define RCC_MCO2EN_BIT_NUMBER 0x9U 6833 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) 6834 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6835 6836 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */ 6837 /** 6838 * @} 6839 */ 6840 6841 /** 6842 * @} 6843 */ 6844 6845 /* Private macros ------------------------------------------------------------*/ 6846 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 6847 * @{ 6848 */ 6849 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 6850 * @{ 6851 */ 6852 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6853 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6854 6855 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 6856 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) 6857 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6858 6859 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 6860 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) 6861 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 6862 6863 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 6864 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) 6865 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 6866 6867 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6868 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) 6869 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6870 6871 #if defined(STM32F446xx) 6872 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) 6873 #endif /* STM32F446xx */ 6874 6875 #if defined(STM32F469xx) || defined(STM32F479xx) 6876 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) 6877 #endif /* STM32F469xx || STM32F479xx */ 6878 6879 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 6880 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) 6881 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6882 6883 #if defined(STM32F413xx) || defined(STM32F423xx) 6884 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) 6885 #endif /* STM32F413xx || STM32F423xx */ 6886 6887 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6888 6889 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ 6890 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6891 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6892 6893 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6894 6895 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6896 6897 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6898 6899 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6900 6901 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6902 6903 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 6904 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 6905 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 6906 ((VALUE) == RCC_PLLSAIDIVR_16)) 6907 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6908 6909 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6910 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6911 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) 6912 6913 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 6914 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 6915 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6916 6917 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6918 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6919 6920 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 6921 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 6922 6923 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 6924 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 6925 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 6926 6927 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 6928 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 6929 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 6930 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 6931 6932 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ 6933 ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ 6934 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 6935 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6936 6937 #if defined(STM32F446xx) 6938 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6939 6940 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 6941 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 6942 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 6943 ((VALUE) == RCC_PLLI2SP_DIV8)) 6944 6945 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) 6946 6947 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 6948 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 6949 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 6950 ((VALUE) == RCC_PLLSAIP_DIV8)) 6951 6952 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ 6953 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ 6954 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ 6955 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) 6956 6957 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ 6958 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ 6959 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ 6960 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 6961 6962 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 6963 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 6964 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 6965 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 6966 6967 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 6968 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 6969 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 6970 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 6971 6972 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 6973 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 6974 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 6975 6976 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ 6977 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 6978 6979 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 6980 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 6981 6982 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 6983 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 6984 6985 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ 6986 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 6987 #endif /* STM32F446xx */ 6988 6989 #if defined(STM32F469xx) || defined(STM32F479xx) 6990 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6991 6992 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 6993 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 6994 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 6995 ((VALUE) == RCC_PLLSAIP_DIV8)) 6996 6997 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 6998 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 6999 7000 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7001 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7002 7003 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 7004 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 7005 7006 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 7007 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 7008 #endif /* STM32F469xx || STM32F479xx */ 7009 7010 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 7011 defined(STM32F413xx) || defined(STM32F423xx) 7012 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 7013 7014 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 7015 7016 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ 7017 ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) 7018 7019 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 7020 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 7021 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 7022 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 7023 7024 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 7025 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 7026 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 7027 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 7028 7029 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 7030 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 7031 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 7032 7033 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7034 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) 7035 7036 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7037 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7038 7039 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 7040 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 7041 7042 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ 7043 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) 7044 7045 #if defined(STM32F413xx) || defined(STM32F423xx) 7046 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ 7047 ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) 7048 7049 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ 7050 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) 7051 7052 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 7053 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 7054 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 7055 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 7056 7057 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ 7058 ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ 7059 ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ 7060 ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) 7061 7062 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ 7063 ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ 7064 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ 7065 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) 7066 7067 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7068 7069 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7070 7071 #endif /* STM32F413xx || STM32F423xx */ 7072 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 7073 7074 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 7075 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 7076 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 7077 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 7078 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 7079 7080 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 7081 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7082 7083 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 7084 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ 7085 STM32F412Rx */ 7086 7087 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 7088 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ 7089 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7090 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 7091 /** 7092 * @} 7093 */ 7094 7095 /** 7096 * @} 7097 */ 7098 7099 /** 7100 * @} 7101 */ 7102 7103 /** 7104 * @} 7105 */ 7106 #ifdef __cplusplus 7107 } 7108 #endif 7109 7110 #endif /* __STM32F4xx_HAL_RCC_EX_H */ 7111 7112
