1 /**
2   ******************************************************************************
3   * @file    stm32wb0x_hal_rcc.h
4   * @author  MCD Application Team
5   * @brief   Header file of RCC HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2024 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WB0x_HAL_RCC_H
21 #define STM32WB0x_HAL_RCC_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x_hal_def.h"
29 #include "stm32wb0x_ll_rcc.h"
30 #include "stm32wb0x_ll_bus.h"
31 #include "stm32wb0x_ll_pwr.h"
32 
33 /** @addtogroup STM32WB0x_HAL_Driver
34   * @{
35   */
36 
37 /** @addtogroup RCC
38   * @{
39   */
40 
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup RCC_Private_Macros
44   * @{
45   */
46 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
47   * @{
48   */
49 
50 #if defined(STM32WB05) || defined(STM32WB06)|| defined(STM32WB07)
51 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__)                            == RCC_OSCILLATORTYPE_NONE)               || \
52                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)                || \
53                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)                || \
54                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)                || \
55                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE_BYPASS) == RCC_OSCILLATORTYPE_LSE_BYPASS))
56 #endif
57 #if defined(STM32WB09)
58 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)                || \
59                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)                || \
60                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)                || \
61                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE_BYPASS) == RCC_OSCILLATORTYPE_LSE_BYPASS))
62 #endif
63 
64 
65 #define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON))
66 
67 #define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
68 
69 #define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON))
70 
71 #define IS_RCC_LSE_BYPASS(__LSE_BYPASS__)  (((__LSE_BYPASS__) == RCC_LSE_BYPASS_OFF) ||\
72                                             ((__LSE_BYPASS__) == RCC_LSE_BYPASS_ON))
73 
74 #define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
75 
76 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_RC64MPLL) || \
77                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_DIRECT_HSE))
78 
79 #define IS_RCC_SYSCLK_DIVIDER(__HCLK__) ((((__HCLK__) == RCC_RC64MPLL_DIV1) || ((__HCLK__) == RCC_RC64MPLL_DIV2)  || \
80                                           ((__HCLK__) == RCC_RC64MPLL_DIV4) || ((__HCLK__) == RCC_RC64MPLL_DIV8)  || \
81                                           ((__HCLK__) == RCC_RC64MPLL_DIV16)|| ((__HCLK__) == RCC_RC64MPLL_DIV32) || \
82                                           ((__HCLK__) == RCC_RC64MPLL_DIV64)) || \
83                                          (((__HCLK__) == RCC_DIRECT_HSE_DIV1) || ((__HCLK__) == RCC_DIRECT_HSE_DIV2)  || \
84                                           ((__HCLK__) == RCC_DIRECT_HSE_DIV4) || ((__HCLK__) == RCC_DIRECT_HSE_DIV8)  || \
85                                           ((__HCLK__) == RCC_RC64MPLL_DIV16)|| ((__HCLK__) == RCC_DIRECT_HSE_DIV32)))
86 
87 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )
88 
89 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCOSOURCE_NOCLOCK)        || \
90                                        ((__SOURCE__) == RCC_MCOSOURCE_SYSCLK)         || \
91                                        ((__SOURCE__) == RCC_MCOSOURCE_HSI)            || \
92                                        ((__SOURCE__) == RCC_MCOSOURCE_HSE)            || \
93                                        ((__SOURCE__) == RCC_MCOSOURCE_RC64MPLL)       || \
94                                        ((__SOURCE__) == RCC_MCOSOURCE_HSI64M_DIV2048) || \
95                                        ((__SOURCE__) == RCC_MCOSOURCE_SMPS)           || \
96                                        ((__SOURCE__) == RCC_MCOSOURCE_ADC))
97 
98 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
99                                 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
100                                 ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32))
101 
102 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
103                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
104                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
105                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
106 /**
107   * @}
108   */
109 
110 /**
111   * @}
112   */
113 
114 /* Exported types ------------------------------------------------------------*/
115 /** @defgroup RCC_Exported_Types RCC Exported Types
116   * @{
117   */
118 
119 /**
120   * @brief  RCC Internal/External Oscillator (HSE, LSE and LSI) configuration structure definition
121   */
122 typedef struct
123 {
124   uint32_t OscillatorType;       /*!< The oscillators to be configured.
125                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
126 
127   uint32_t HSEState;             /*!< The new state of the HSE.
128                                       This parameter can be a value of @ref RCC_HSE_Config                        */
129 
130   uint32_t HSIState;             /*!< The new state of the HSI.
131                                       This parameter can be a value of @ref RCC_HSI_Config                        */
132 
133   uint32_t LSEState;             /*!< The new state of the LSE.
134                                       This parameter can be a value of @ref RCC_LSE_Config                        */
135 
136   uint32_t LSIState;             /*!< The new state of the LSI.
137                                       This parameter can be a value of @ref RCC_LSI_Config                        */
138 
139   uint32_t LSEBYPASSState;       /*!< The new state of the LSE Bypass.
140                                       This parameter can be a value of @ref RCC_LSEBYPASS_Config                  */
141 } RCC_OscInitTypeDef;
142 
143 /**
144   * @brief  RCC System clock configuration structure definition
145   */
146 typedef struct
147 {
148   uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
149                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
150 
151   uint32_t SYSCLKDivider;         /*!< The clock divider used as system clock (SYSCLK).
152                                        This parameter can be a value of @ref RCC_RC64MPLL_Clock_Divider or
153                                        @ref RCC_DIRECT_HSE_Clock_Divider */
154 } RCC_ClkInitTypeDef;
155 
156 /**
157   * @}
158   */
159 
160 /* Exported constants --------------------------------------------------------*/
161 /** @defgroup RCC_Exported_Constants RCC Exported Constants
162   * @{
163   */
164 
165 /** @defgroup RCC_Timeout_Value Timeout Values
166   * @{
167   */
168 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT  /* LSE timeout in ms        */
169 /**
170   * @}
171   */
172 
173 /** @defgroup RCC_HSI_CALIBRATION_DEFAULT HSI default calibration trimming value
174   * @{
175   */
176 #define RCC_HSICALIBRATION_DEFAULT     0x1FU        /*!< Default HSI calibration trimming value */
177 /**
178   * @}
179   */
180 
181 /** @defgroup RCC_Oscillator_Type Oscillator Type
182   * @{
183   */
184 #define RCC_OSCILLATORTYPE_HSI         0x00000010U   /*!< Oscillator configuration unchanged  */
185 #define RCC_OSCILLATORTYPE_NONE         0x00000000U   /*!< Oscillator configuration unchanged  */
186 #define RCC_OSCILLATORTYPE_HSE         0x00000001U   /*!< HSE to configure                    */
187 #define RCC_OSCILLATORTYPE_LSE         0x00000002U   /*!< LSE to configure                    */
188 #define RCC_OSCILLATORTYPE_LSI         0x00000004U   /*!< LSI to configure                    */
189 #define RCC_OSCILLATORTYPE_LSE_BYPASS  0x00000008U   /*!< Slow clock is directly provided     */
190 /**
191   * @}
192   */
193 
194 /** @defgroup RCC_HSI_Config HSI Config
195   * @{
196   */
197 #define RCC_HSI_OFF                   RCC_CFGR_STOPHSI     /*!< HSI clock activation   */
198 #define RCC_HSI_ON                    0x00000000U          /*!< HSI clock deactivation */
199 /**
200   * @}
201   */
202 
203 /** @defgroup RCC_HSE_Config HSE Config
204   * @{
205   */
206 #define RCC_HSE_OFF                    0x00000000U      /*!< HSE clock deactivation */
207 #define RCC_HSE_ON                     RCC_CR_HSEON     /*!< HSE clock activation   */
208 /**
209   * @}
210   */
211 
212 /** @defgroup RCC_LSE_Config LSE Config
213   * @{
214   */
215 #define RCC_LSE_OFF                    0x00000000U     /*!< LSE clock deactivation */
216 #define RCC_LSE_ON                     RCC_CR_LSEON    /*!< LSE clock activation   */
217 /**
218   * @}
219   */
220 
221 /** @defgroup RCC_LSI_Config LSI Config
222   * @{
223   */
224 #define RCC_LSI_OFF                    0x00000000U     /*!< LSI clock deactivation */
225 #define RCC_LSI_ON                     RCC_CR_LSION    /*!< LSI clock activation   */
226 /**
227   * @}
228   */
229 
230 /** @defgroup RCC_LSEBYPASS_Config LSE BYPASS Config
231   * @{
232   */
233 #define RCC_LSE_BYPASS_OFF             0x00000000U     /*!< LSE clock deactivation */
234 #define RCC_LSE_BYPASS_ON              RCC_CR_LSEBYP   /*!< LSE clock activation   */
235 /**
236   * @}
237   */
238 
239 /** @defgroup RCC_RF_Clock  RF Clock
240   * @{
241   */
242 #define RCC_RF_CLK_16M       LL_RCC_RF_CLK_16M   /*!< RF system clock 16 MHz*/
243 #define RCC_RF_CLK_32M       LL_RCC_RF_CLK_32M   /*!< RF system clock 32 MHz */
244 /**
245   * @}
246   */
247 
248 /** @defgroup RCC_DIRECT_HSE_Clock_Divider DIRECT HSE Clock Divider
249   * @{
250   */
251 #define RCC_DIRECT_HSE_DIV1              LL_RCC_DIRECT_HSE_DIV_1   /*!< DIRECT HSE division factor = 1   */
252 #define RCC_DIRECT_HSE_DIV2              LL_RCC_DIRECT_HSE_DIV_2   /*!< DIRECT HSE division factor = 2   */
253 #define RCC_DIRECT_HSE_DIV4              LL_RCC_DIRECT_HSE_DIV_4   /*!< DIRECT HSE division factor = 4   */
254 #define RCC_DIRECT_HSE_DIV8              LL_RCC_DIRECT_HSE_DIV_8   /*!< DIRECT HSE division factor = 8   */
255 #define RCC_DIRECT_HSE_DIV16             LL_RCC_DIRECT_HSE_DIV_16  /*!< DIRECT HSE division factor = 16  */
256 #define RCC_DIRECT_HSE_DIV32             LL_RCC_DIRECT_HSE_DIV_32  /*!< DIRECT HSE division factor = 32  */
257 /**
258   * @}
259   */
260 
261 /** @defgroup RCC_RC64MPLL_Clock_Divider RC64MPLL Clock Divider
262   * @{
263   */
264 #define RCC_RC64MPLL_DIV1              LL_RCC_RC64MPLL_DIV_1    /*!< RC64MPLL division factor = 1   */
265 #define RCC_RC64MPLL_DIV2              LL_RCC_RC64MPLL_DIV_2    /*!< RC64MPLL division factor = 2   */
266 #define RCC_RC64MPLL_DIV4              LL_RCC_RC64MPLL_DIV_4    /*!< RC64MPLL division factor = 4   */
267 #define RCC_RC64MPLL_DIV8              LL_RCC_RC64MPLL_DIV_8    /*!< RC64MPLL division factor = 8   */
268 #define RCC_RC64MPLL_DIV16             LL_RCC_RC64MPLL_DIV_16   /*!< RC64MPLL division factor = 16  */
269 #define RCC_RC64MPLL_DIV32             LL_RCC_RC64MPLL_DIV_32   /*!< RC64MPLL division factor = 32  */
270 #define RCC_RC64MPLL_DIV64             LL_RCC_RC64MPLL_DIV_64   /*!< RC64MPLL division factor = 64  */
271 /**
272   * @}
273   */
274 
275 /** @defgroup RCC_Clock_SWITCH_Divider Clock Switch Divider
276   * @{
277   */
278 #define RCC_RC64MPLL_SWITCH_DIV1           LL_RCC_RC64MPLL_SWITCH_DIV_1    /*!< RC64MPLL division factor = 1   */
279 #define RCC_RC64MPLL_SWITCH_DIV2           LL_RCC_RC64MPLL_SWITCH_DIV_2    /*!< RC64MPLL division factor = 2   */
280 #define RCC_RC64MPLL_SWITCH_DIV4           LL_RCC_RC64MPLL_SWITCH_DIV_4    /*!< RC64MPLL division factor = 4   */
281 #define RCC_DIRECT_HSE_SWITCH_DIV1         LL_RCC_RC64MPLL_SWITCH_DIV_2    /*!< Direct HSE division factor = 1 */
282 #define RCC_DIRECT_HSE_SWITCH_DIV2         LL_RCC_RC64MPLL_SWITCH_DIV_4    /*!< Direct HSE division factor = 2 */
283 /**
284   * @}
285   */
286 
287 /** @defgroup RCC_System_Clock_Source System Clock Source
288   * @{
289   */
290 #define RCC_SYSCLKSOURCE_RC64MPLL      0x00000000U   /*!< RC64MPLL system clock configuration   */
291 #define RCC_SYSCLKSOURCE_DIRECT_HSE    0x00000001U   /*!< DIRECT HSE system clock configuration */
292 #define RCC_SYSCLKSOURCE_HSI           0x00000002U   /*!< RC64MPLL system clock configuration   */
293 
294 /**
295   * @}
296   */
297 
298 /** @defgroup RCC_MCO_Index MCO Index
299   * @{
300   */
301 #define RCC_MCO1                       0x00000000U          /*!< MCO1 index */
302 #define RCC_MCO2                       0x00000001U          /*!< MCO2 index */
303 #define RCC_MCO3                       0x00000002U          /*!< MCO3 index */
304 /**
305   * @}
306   */
307 
308 /** @defgroup RCC_MCO_Clock_Source MCO Clock Source
309   * @{
310   */
311 #define RCC_MCOSOURCE_NOCLOCK         LL_RCC_MCOSOURCE_NOCLOCK            /*!< MCO output disabled, no clock on MCO */
312 #define RCC_MCO1SOURCE_SYSCLK          LL_RCC_MCOSOURCE_SYSCLK             /*!< SYSCLK selection as MCO source */
313 #define RCC_MCO1SOURCE_HSI             LL_RCC_MCOSOURCE_HSI                /*!< HSI selection as MCO source */
314 #define RCC_MCO1SOURCE_HSE             LL_RCC_MCOSOURCE_HSE                /*!< HSE after stabilization selection as MCO source */
315 #define RCC_MCOSOURCE_RC64MPLL        LL_RCC_MCOSOURCE_RC64MPLL           /*!< RC64MPLL selection as MCO source */
316 #define RCC_MCOSOURCE_HSI64M_DIV2048  LL_RCC_MCOSOURCE_HSI64M_DIV2048     /*!< HSI64M_DIV2048 selection as MCO source */
317 #define RCC_MCOSOURCE_SMPS            LL_RCC_MCOSOURCE_SMPS               /*!< SMPS selection as MCO source */
318 #define RCC_MCOSOURCE_ADC             LL_RCC_MCOSOURCE_ADC                /*!< ADC selection as MCO source */
319 /**
320   * @}
321   */
322 
323 
324 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
325   * @{
326   */
327 #define RCC_MCODIV_1                   LL_RCC_MCO_DIV_1                  /*!< MCO not divided */
328 #define RCC_MCODIV_2                   LL_RCC_MCO_DIV_2                  /*!< MCO divided by 2 */
329 #define RCC_MCODIV_4                   LL_RCC_MCO_DIV_4                  /*!< MCO divided by 4 */
330 #define RCC_MCODIV_8                   LL_RCC_MCO_DIV_8                  /*!< MCO divided by 8 */
331 #define RCC_MCODIV_16                  LL_RCC_MCO_DIV_16                 /*!< MCO divided by 16 */
332 #define RCC_MCODIV_32                  LL_RCC_MCO_DIV_32                 /*!< MCO divided by 32 */
333 /**
334   * @}
335   */
336 
337 /** @defgroup RCC_HSEAMPTHRESHOLD HSE bias current factor
338   * @{
339   */
340 #if defined(RCC_RFSWHSECR_SATRG)
341 #define RCC_HSEAMPTHRESHOLD_1_2       LL_RCC_HSEAMPTHRESHOLD_1_2           /*!< HSE bias current factor 1/2 */
342 #define RCC_HSEAMPTHRESHOLD_3_4       LL_RCC_HSEAMPTHRESHOLD_3_4           /*!< HSE bias current factor 3/4 */
343 #endif
344 /**
345   * @}
346   */
347 
348 /** @defgroup RCC_HSE_CURRENTMAX HSE current max limit
349   * @{
350   */
351 #define RCC_HSE_CURRENTMAX_0           LL_RCC_HSE_CURRENTMAX_0             /*!< HSE current max limit 0.18 mA/V */
352 #define RCC_HSE_CURRENTMAX_1           LL_RCC_HSE_CURRENTMAX_1             /*!< HSE current max limit 0.57 mA/V */
353 #define RCC_HSE_CURRENTMAX_2           LL_RCC_HSE_CURRENTMAX_2             /*!< HSE current max limit 0.78 mA/V */
354 #define RCC_HSE_CURRENTMAX_3           LL_RCC_HSE_CURRENTMAX_3             /*!< HSE current max limit 1.13 mA/V */
355 #define RCC_HSE_CURRENTMAX_4           LL_RCC_HSE_CURRENTMAX_4             /*!< HSE current max limit 0.61 mA/V */
356 #define RCC_HSE_CURRENTMAX_5           LL_RCC_HSE_CURRENTMAX_5             /*!< HSE current max limit 1.65 mA/V */
357 #define RCC_HSE_CURRENTMAX_6           LL_RCC_HSE_CURRENTMAX_6             /*!< HSE current max limit 2.12 mA/V */
358 #define RCC_HSE_CURRENTMAX_7           LL_RCC_HSE_CURRENTMAX_7             /*!< HSE current max limit 2.84 mA/V */
359 /**
360   * @}
361   */
362 
363 /** @defgroup RCC_Interrupt Interrupts
364   * @{
365   */
366 #define RCC_IT_LSIRDY                  LL_RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
367 #define RCC_IT_LSERDY                  LL_RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
368 #define RCC_IT_HSIRDY                  LL_RCC_CIFR_HSIRDYF      /*!< HSI Ready Interrupt flag */
369 #define RCC_IT_HSERDY                  LL_RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
370 #define RCC_IT_PLLRDY                  LL_RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
371 #define RCC_IT_PLL_UNLOCK              LL_RCC_CIFR_PLLUNLOCKDETF /*!< PLL Unlock Interrupt flag */
372 #define RCC_IT_RTCRSTRELRDY            LL_RCC_CIFR_RTCRSTRELF   /*!< RTC Reset Release Interrupt Flag */
373 #define RCC_IT_WDGRSTRELRDY            LL_RCC_CIFR_WDGRSTRELF   /*!< WDG Reset Release Interrupt Flag */
374 #if defined(RCC_CIFR_LPURSTF)
375 #define RCC_IT_LPURSTRELRDY            LL_RCC_CIFR_LPURSTRELF   /*!< LPU Reset Release Interrupt Flag */
376 #endif
377 /**
378   * @}
379   */
380 
381 /** @defgroup RCC_Flag Flags
382   * @{
383   */
384 /* Flags in the CR register */
385 #define RCC_FLAG_HSIRDY                RCC_CR_HSIRDY        /*!< HSI Ready flag */
386 #define RCC_FLAG_HSERDY                RCC_CR_HSERDY        /*!< HSE Ready flag */
387 #define RCC_FLAG_PLLRDY                RCC_CR_HSIPLLRDY     /*!< PLL Ready flag */
388 #define RCC_FLAG_LSIRDY                RCC_CR_LSIRDY        /*!< LSI Ready flag */
389 #define RCC_FLAG_LSERDY                RCC_CR_LSERDY        /*!< LSE Ready flag */
390 
391 /* Flags in the CSR register */
392 #define RCC_FLAG_LOCKUPRST             RCC_CSR_LOCKUPRSTF   /*!< CPU lockup reset flag      */
393 #define RCC_FLAG_WDGRST                RCC_CSR_WDGRSTF      /*!< Watchdog reset flag        */
394 #define RCC_FLAG_SFTRST                RCC_CSR_SFTRSTF      /*!< Software reset flag        */
395 #define RCC_FLAG_PORRST                RCC_CSR_PORRSTF      /*!< Power-On or BOR reset flag */
396 #define RCC_FLAG_PADRSTF               RCC_CSR_PADRSTF      /*!< NRSTn pad reset flag       */
397 /**
398   * @}
399   */
400 
401 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration
402   * @{
403   */
404 #define RCC_LSEDRIVE_LOW                 LL_RCC_LSEDRIVE_LOW            /*!< LSE low drive capability */
405 #define RCC_LSEDRIVE_MEDIUMLOW           LL_RCC_LSEDRIVE_MEDIUMLOW      /*!< LSE medium low drive capability */
406 #define RCC_LSEDRIVE_MEDIUMHIGH          LL_RCC_LSEDRIVE_MEDIUMHIGH     /*!< LSE medium high drive capability */
407 #define RCC_LSEDRIVE_HIGH                LL_RCC_LSEDRIVE_HIGH           /*!< LSE high drive capability */
408 /**
409   * @}
410   */
411 
412 /**
413   * @}
414   */
415 
416 /* Exported macros -----------------------------------------------------------*/
417 
418 /** @defgroup RCC_Exported_Macros RCC Exported Macros
419   * @{
420   */
421 
422 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
423   * @brief  Enable or disable the AHB peripheral clock.
424   * @note   After reset, the peripheral clock (used for registers read/write access)
425   *         is disabled and the application software has to enable this clock before
426   *         using it.
427   * @{
428   */
429 #define __HAL_RCC_DMA_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA)
430 #define __HAL_RCC_GPIOA_CLK_ENABLE()           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA)
431 #define __HAL_RCC_GPIOB_CLK_ENABLE()           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB)
432 #define __HAL_RCC_CRC_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)
433 #if defined(PKA)
434 #define __HAL_RCC_PKA_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_PKA)
435 #endif
436 #define __HAL_RCC_RNG_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_RNG)
437 
438 
439 #define __HAL_RCC_DMA_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA)
440 #define __HAL_RCC_GPIOA_CLK_DISABLE()          LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_GPIOA)
441 #define __HAL_RCC_GPIOB_CLK_DISABLE()          LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_GPIOB)
442 #define __HAL_RCC_CRC_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)
443 #if defined(PKA)
444 #define __HAL_RCC_PKA_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_PKA)
445 #endif
446 #define __HAL_RCC_RNG_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_RNG)
447 
448 /**
449   * @}
450   */
451 
452 /** @defgroup RCC_APB0_Clock_Enable_Disable APB0 Peripheral Clock Enable Disable
453   * @brief  Enable or disable the APB0 peripheral clock.
454   * @note   After reset, the peripheral clock (used for registers read/write access)
455   *         is disabled and the application software has to enable this clock before
456   *         using it.
457   * @{
458   */
459 #if defined(TIM1)
460 #define __HAL_RCC_TIM1_CLK_ENABLE()            LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_TIM1)
461 #endif
462 #if defined(TIM2)
463 #define __HAL_RCC_TIM2_CLK_ENABLE()            LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_TIM2)
464 #endif
465 #define __HAL_RCC_SYSCFG_CLK_ENABLE()          LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_SYSCFG)
466 #if defined(COMP1)
467 #define __HAL_RCC_COMP_CLK_ENABLE()            LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_COMP)
468 #endif
469 #if defined(DAC)
470 #define __HAL_RCC_DAC_CLK_ENABLE()            LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_DAC)
471 #endif
472 #define __HAL_RCC_RTC_CLK_ENABLE()             LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_RTC)
473 
474 #define __HAL_RCC_WDG_CLK_ENABLE()             LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_WDG)
475 #if defined(TIM16)
476 #define __HAL_RCC_TIM16_CLK_ENABLE()           LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_TIM16)
477 #endif
478 #if defined(TIM17)
479 #define __HAL_RCC_TIM17_CLK_ENABLE()           LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_TIM17)
480 #endif
481 
482 #if defined(TIM1)
483 #define __HAL_RCC_TIM1_CLK_DISABLE()           LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_TIM1)
484 #endif
485 #if defined(TIM2)
486 #define __HAL_RCC_TIM2_CLK_DISABLE()           LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_TIM2)
487 #endif
488 #define __HAL_RCC_SYSCFG_CLK_DISABLE()         LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_SYSCFG)
489 #if defined(COMP1)
490 #define __HAL_RCC_COMP_CLK_DISABLE()           LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_COMP)
491 #endif
492 #if defined(DAC)
493 #define __HAL_RCC_DAC_CLK_DISABLE()            LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_DAC)
494 #endif
495 #define __HAL_RCC_RTC_CLK_DISABLE()            LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_RTC)
496 
497 #define __HAL_RCC_WDG_CLK_DISABLE()            LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_WDG)
498 #if defined(TIM16)
499 #define __HAL_RCC_TIM16_CLK_DISABLE()          LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_TIM16)
500 #endif
501 #if defined(TIM17)
502 #define __HAL_RCC_TIM17_CLK_DISABLE()          LL_APB0_GRP1_DisableClock(LL_APB0_GRP1_PERIPH_TIM17)
503 #endif
504 /**
505   * @}
506   */
507 
508 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
509   * @brief  Enable or disable the APB1 peripheral clock.
510   * @note   After reset, the peripheral clock (used for registers read/write access)
511   *         is disabled and the application software has to enable this clock before
512   *         using it.
513   * @{
514   */
515 #if defined(SPI1)
516 #define __HAL_RCC_SPI1_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI1)
517 #endif
518 #define __HAL_RCC_ADCDIG_CLK_ENABLE()          LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_ADCDIG)
519 #define __HAL_RCC_ADCANA_CLK_ENABLE()          LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_ADCANA)
520 #define __HAL_RCC_LPUART1_CLK_ENABLE()         LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1)
521 #define __HAL_RCC_USART1_CLK_ENABLE()          LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART1)
522 #if defined(SPI2)
523 #define __HAL_RCC_SPI2_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
524 #endif
525 #if defined(SPI3)
526 #define __HAL_RCC_SPI3_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3)
527 #endif
528 #if defined(I2C1)
529 #define __HAL_RCC_I2C1_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
530 #endif
531 #if defined(I2C2)
532 #define __HAL_RCC_I2C2_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2)
533 #endif
534 
535 #if defined(SPI1)
536 #define __HAL_RCC_SPI1_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI1)
537 #endif
538 #define __HAL_RCC_ADCDIG_CLK_DISABLE()         LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_ADCDIG)
539 #define __HAL_RCC_ADCANA_CLK_DISABLE()         LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_ADCANA)
540 #define __HAL_RCC_LPUART1_CLK_DISABLE()        LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPUART1)
541 #define __HAL_RCC_USART1_CLK_DISABLE()         LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART1)
542 #if defined(SPI2)
543 #define __HAL_RCC_SPI2_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
544 #endif
545 #if defined(SPI3)
546 #define __HAL_RCC_SPI3_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI3)
547 #endif
548 #if defined(I2C1)
549 #define __HAL_RCC_I2C1_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
550 #endif
551 #if defined(I2C2)
552 #define __HAL_RCC_I2C2_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2)
553 #endif
554 /**
555   * @}
556   */
557 
558 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
559   * @brief  Enable or disable the APB2 peripheral clock.
560   * @note   After reset, the peripheral clock (used for registers read/write access)
561   *         is disabled and the application software has to enable this clock before
562   *         using it.
563   * @{
564   */
565 #if defined(BLUE)
566 #define __HAL_RCC_RADIO_CLK_ENABLE()            LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_MRBLE)
567 
568 #define __HAL_RCC_RADIO_CLK_DISABLE()           LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_MRBLE)
569 #endif
570 
571 /**
572   * @}
573   */
574 
575 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
576   * @brief  Check whether the AHB peripheral clock is enabled or not.
577   * @note   After reset, the peripheral clock (used for registers read/write access)
578   *         is disabled and the application software has to enable this clock before
579   *         using it.
580   * @{
581   */
582 #define __HAL_RCC_DMA_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA)
583 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()           LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPIOA)
584 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()           LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPIOB)
585 #define __HAL_RCC_CRC_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)
586 #if defined(PKA)
587 #define __HAL_RCC_PKA_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_PKA)
588 #endif
589 #define __HAL_RCC_RNG_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_RNG)
590 
591 
592 #define __HAL_RCC_DMA_IS_CLK_DISABLED()            !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA))
593 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()          !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPIOA))
594 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()          !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPIOB))
595 #define __HAL_RCC_CRC_IS_CLK_DISABLED()            !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC))
596 #if defined(PKA)
597 #define __HAL_RCC_PKA_IS_CLK_DISABLED()            !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_PKA))
598 #endif
599 #define __HAL_RCC_RNG_IS_CLK_DISABLED()            !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_RNG))
600 
601 /**
602   * @}
603   */
604 
605 /** @defgroup RCC_APB0_Clock_Enable_Disable_Status APB0 Peripheral Clock Enabled or Disabled Status
606   * @brief  Check whether the APB0 peripheral clock is enabled or not.
607   * @note   After reset, the peripheral clock (used for registers read/write access)
608   *         is disabled and the application software has to enable this clock before
609   *         using it.
610   * @{
611   */
612 #if defined(TIM1)
613 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()            LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM1)
614 #endif
615 #if defined(TIM2)
616 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()            LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM2)
617 #endif
618 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()          LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_SYSCFG)
619 #if defined(COMP1)
620 #define __HAL_RCC_COMP_IS_CLK_ENABLED()            LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_COMP)
621 #endif
622 #if defined(DAC)
623 #define __HAL_RCC_DAC_IS_CLK_ENABLED()             LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_DAC)
624 #endif
625 #define __HAL_RCC_RTC_IS_CLK_ENABLED()             LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_RTC)
626 
627 #define __HAL_RCC_WDG_IS_CLK_ENABLED()             LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_WDG)
628 #if defined(TIM16)
629 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()           LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM16)
630 #endif
631 #if defined(TIM17)
632 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()           LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM17)
633 #endif
634 
635 #if defined(TIM1)
636 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()           !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM1))
637 #endif
638 #if defined(TIM2)
639 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()           !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM2))
640 #endif
641 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()         !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_SYSCFG))
642 #if defined(COMP1)
643 #define __HAL_RCC_COMP_IS_CLK_DISABLED()           !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_COMP))
644 #endif
645 #if defined(DAC)
646 #define __HAL_RCC_DAC_IS_CLK_DISABLED()            !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_DAC))
647 #endif
648 #define __HAL_RCC_RTC_IS_CLK_DISABLED()            !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_RTC))
649 
650 #define __HAL_RCC_WDG_IS_CLK_DISABLED()            !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_WDG))
651 #if defined(TIM16)
652 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()          !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM16))
653 #endif
654 #if defined(TIM17)
655 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()          !(LL_APB0_GRP1_IsEnabledClock(LL_APB0_GRP1_PERIPH_TIM17))
656 #endif
657 /**
658   * @}
659   */
660 
661 
662 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
663   * @brief  Check whether the APB1 peripheral clock is enabled or not.
664   * @note   After reset, the peripheral clock (used for registers read/write access)
665   *         is disabled and the application software has to enable this clock before
666   *         using it.
667   * @{
668   */
669 #if defined(SPI1)
670 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI1)
671 #endif
672 #define __HAL_RCC_ADCDIG_IS_CLK_ENABLED()          LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_ADCDIG)
673 #define __HAL_RCC_ADCANA_IS_CLK_ENABLED()          LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_ADCANA)
674 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()         LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPUART1)
675 #define __HAL_RCC_USART1_IS_CLK_ENABLED()          LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART1)
676 #if defined(SPI2)
677 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
678 #endif
679 #if defined(SPI3)
680 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3)
681 #endif
682 #if defined(I2C1)
683 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
684 #endif
685 #if defined(I2C2)
686 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2)
687 #endif
688 
689 #if defined(SPI1)
690 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI1))
691 #endif
692 #define __HAL_RCC_ADCDIG_IS_CLK_DISABLED()         !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_ADCDIG))
693 #define __HAL_RCC_ADCANA_IS_CLK_DISABLED()         !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_ADCANA))
694 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()        !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPUART1))
695 #define __HAL_RCC_USART1_IS_CLK_DISABLED()         !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART1))
696 #if defined(SPI2)
697 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2))
698 #endif
699 #if defined(SPI3)
700 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3))
701 #endif
702 #if defined(I2C1)
703 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1))
704 #endif
705 #if defined(I2C2)
706 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2))
707 #endif
708 /**
709   * @}
710   */
711 
712 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
713   * @brief  Check whether the APB2 peripheral clock is enabled or not.
714   * @note   After reset, the peripheral clock (used for registers read/write access)
715   *         is disabled and the application software has to enable this clock before
716   *         using it.
717   * @{
718   */
719 #if defined(BLUE)
720 #define __HAL_RCC_RADIO_IS_CLK_ENABLED()            LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_MRBLE)
721 
722 #define __HAL_RCC_RADIO_IS_CLK_DISABLED()           !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_MRBLE))
723 #endif
724 
725 /**
726   * @}
727   */
728 
729 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
730   * @brief  Force or release AHB peripheral reset.
731   * @{
732   */
733 #define __HAL_RCC_AHB1_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)
734 #define __HAL_RCC_DMA_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA)
735 #define __HAL_RCC_GPIOA_FORCE_RESET()           LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA)
736 #define __HAL_RCC_GPIOB_FORCE_RESET()           LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB)
737 #define __HAL_RCC_CRC_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)
738 #if defined(PKA)
739 #define __HAL_RCC_PKA_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_PKA)
740 #endif
741 #define __HAL_RCC_RNG_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG)
742 
743 #define __HAL_RCC_AHB1_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)
744 #define __HAL_RCC_DMA_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA)
745 #define __HAL_RCC_GPIOA_RELEASE_RESET()         LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA)
746 #define __HAL_RCC_GPIOB_RELEASE_RESET()         LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB)
747 #define __HAL_RCC_CRC_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)
748 #if defined(PKA)
749 #define __HAL_RCC_PKA_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_PKA)
750 #endif
751 #define __HAL_RCC_RNG_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG)
752 
753 
754 /**
755   * @}
756   */
757 
758 /** @defgroup RCC_APB0_Force_Release_Reset APB0 Peripheral Force Release Reset
759   * @brief  Force or release APB0 peripheral reset.
760   * @{
761   */
762 
763 #define __HAL_RCC_APB0_FORCE_RESET()            LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_ALL)
764 #if defined(TIM1)
765 #define __HAL_RCC_TIM1_FORCE_RESET()            LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM1)
766 #endif
767 #if defined(TIM2)
768 #define __HAL_RCC_TIM2_FORCE_RESET()            LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM2)
769 #endif
770 #define __HAL_RCC_SYSCFG_FORCE_RESET()          LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_SYSCFG)
771 #if defined(COMP1)
772 #define __HAL_RCC_COMP_FORCE_RESET()            LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_COMP)
773 #endif
774 #if defined(DAC)
775 #define __HAL_RCC_DAC_FORCE_RESET()             LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_DAC)
776 #endif
777 #define __HAL_RCC_RTC_FORCE_RESET()             LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_RTC)
778 
779 #define __HAL_RCC_WDG_FORCE_RESET()             LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_WDG)
780 #if defined(TIM16)
781 #define __HAL_RCC_TIM16_FORCE_RESET()           LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM16)
782 #endif
783 #if defined(TIM17)
784 #define __HAL_RCC_TIM17_FORCE_RESET()           LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_TIM17)
785 #endif
786 
787 #define __HAL_RCC_APB0_RELEASE_RESET()          LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_ALL)
788 #if defined(TIM1)
789 #define __HAL_RCC_TIM1_RELEASE_RESET()          LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM1)
790 #endif
791 #if defined(TIM2)
792 #define __HAL_RCC_TIM2_RELEASE_RESET()          LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM2)
793 #endif
794 #define __HAL_RCC_SYSCFG_RELEASE_RESET()        LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_SYSCFG)
795 #if defined(COMP1)
796 #define __HAL_RCC_COMP_RELEASE_RESET()          LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_COMP)
797 #endif
798 #if defined(DAC)
799 #define __HAL_RCC_DAC_RELEASE_RESET()           LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_DAC)
800 #endif
801 #define __HAL_RCC_RTC_RELEASE_RESET()           LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_RTC)
802 
803 #define __HAL_RCC_WDG_RELEASE_RESET()           LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_WDG)
804 #if defined(TIM16)
805 #define __HAL_RCC_TIM16_RELEASE_RESET()         LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM16)
806 #endif
807 #if defined(TIM17)
808 #define __HAL_RCC_TIM17_RELEASE_RESET()         LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_TIM17)
809 #endif
810 /**
811   * @}
812   */
813 
814 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
815   * @brief  Force or release APB1 peripheral reset.
816   * @{
817   */
818 #define __HAL_RCC_APB1_FORCE_RESET()            LL_APB1_GRP1_ForceReset( LL_APB1_GRP1_RESET_PERIPH_ALL)
819 
820 #if defined(SPI1)
821 #define __HAL_RCC_SPI1_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI1)
822 #endif
823 #define __HAL_RCC_ADC_FORCE_RESET()             LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ADCDIG)
824 #define __HAL_RCC_LPUART1_FORCE_RESET()         LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1)
825 #define __HAL_RCC_USART1_FORCE_RESET()          LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART1)
826 #if defined(SPI2)
827 #define __HAL_RCC_SPI2_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
828 #endif
829 #if defined(SPI3)
830 #define __HAL_RCC_SPI3_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3)
831 #endif
832 #if defined(I2C1)
833 #define __HAL_RCC_I2C1_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
834 #endif
835 #if defined(I2C2)
836 #define __HAL_RCC_I2C2_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2)
837 #endif
838 
839 #define __HAL_RCC_APB1_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset( LL_APB1_GRP1_RESET_PERIPH_ALL)
840 
841 #if defined(SPI1)
842 #define __HAL_RCC_SPI1_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI1)
843 #endif
844 #define __HAL_RCC_ADC_RELEASE_RESET()           LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ADCDIG)
845 #define __HAL_RCC_LPUART1_RELEASE_RESET()       LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1)
846 #define __HAL_RCC_USART1_RELEASE_RESET()        LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART1)
847 #if defined(SPI2)
848 #define __HAL_RCC_SPI2_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
849 #endif
850 #if defined(SPI3)
851 #define __HAL_RCC_SPI3_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3)
852 #endif
853 #if defined(I2C1)
854 #define __HAL_RCC_I2C1_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
855 #endif
856 #if defined(I2C2)
857 #define __HAL_RCC_I2C2_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2)
858 #endif
859 /**
860   * @}
861   */
862 
863 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
864   * @brief  Force or release APB2 peripheral reset.
865   * @{
866   */
867 #define __HAL_RCC_APB2_FORCE_RESET()             LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
868 #if defined(BLUE)
869 #define __HAL_RCC_RADIO_FORCE_RESET()            LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_MRBLE)
870 #endif
871 
872 #define __HAL_RCC_APB2_RELEASE_RESET()           LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
873 #if defined(BLUE)
874 #define __HAL_RCC_RADIO_RELEASE_RESET()          LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_MRBLE)
875 #endif
876 
877 /**
878   * @}
879   */
880 
881 /** @defgroup RCC_CLK_CONFIG_MACROS Clock Configuration Macros
882   * @{
883   */
884 /** @defgroup RCC_LSI_MACROS LSI Macros
885   * @{
886   */
887 
888  /**
889   * @brief  Macro to configure the Internal High Speed oscillator (HSI).
890   * @note   After enabling the HSI (RCC_HSI_ON), the application
891   *         software should wait on HSIRDY flag to be set indicating that HSI clock
892   *         is stable.
893   * @note   The HSI is stopped by hardware when entering DEEPSTOP and SHUTDOWN modes.
894   * @param  __STATE__  specifies the new state of the HSE.
895   *         This parameter can be one of the following values:
896   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator.
897   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
898   * @retval None
899   */
900 #define __HAL_RCC_HSI_CONFIG(__STATE__)    \
901   do {                                     \
902     if((__STATE__) == RCC_HSI_ON)          \
903     {                                      \
904       LL_RCC_HSI_Enable();                 \
905     }                                      \
906     else                                   \
907     {                                      \
908       LL_RCC_HSI_Disable();                \
909     }                                      \
910   } while(0U)
911 
912 /**
913   * @brief  Macro to get the HSI ready flag.
914   * @retval Returns the Ready Flag status
915   */
916 #define __HAL_RCC_GET_HSI_READYFLAG() LL_RCC_HSI_IsReady()
917 
918 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
919   * @note   The calibration is used to compensate for the variations in voltage
920   *         and temperature that influence the frequency of the internal HSI RC.
921   * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
922   *         (default is RCC_HSICALIBRATION_DEFAULT).
923   *         This parameter must be a number between Min_data=0 and Max_Data=63.
924   * @retval None
925   */
926 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)  LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)
927 /**
928   * @}
929   */
930 
931 /** @defgroup RCC_LSI_MACROS LSI Macros
932   * @{
933   */
934 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
935   * @note   After enabling the LSI, the application software should wait on
936   *         LSIRDY flag to be set indicating that LSI clock is stable.
937   * @note   LSI can not be disabled if the IWDG is running.
938   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI1 oscillator
939   *         clock cycles.
940   * @retval None
941   */
942 #define __HAL_RCC_LSI_ENABLE()         LL_RCC_LSI_Enable()
943 #define __HAL_RCC_LSI_DISABLE()        LL_RCC_LSI_Disable()
944 
945 /**
946   * @brief  Macro to get the LSI ready flag.
947   * @retval Returns the Ready Flag status
948   */
949 #define __HAL_RCC_GET_LSI_READYFLAG() LL_RCC_LSI_IsReady()
950 
951 /** @brief  Macro to adjust the Internal Low Speed oscillator (LSI) calibration value.
952   * @note   The calibration is used to compensate for the variations in voltage
953   *         and temperature that influence the frequency of the internal HSI RC.
954   * @param  __LSITRIMMINGVALUE__ specifies the calibration trimming value
955   *         This parameter must be a number between Min_data=0 and Max_Data=15.
956   * @retval None
957   */
958 #define __HAL_RCC_LSI_CALIBRATIONVALUE_ADJUST(__LSITRIMMINGVALUE__)  LL_RCC_LSI_SetTrimming(__LSITRIMMINGVALUE__)
959 /**
960   * @}
961   */
962 
963 /** @defgroup RCC_HSE_MACROS HSE Macros
964   * @{
965   */
966 /**
967   * @brief  Macro to configure the External High Speed oscillator (HSE).
968   * @note   After enabling the HSE (RCC_HSE_ON), the application
969   *         software should wait on HSERDY flag to be set indicating that HSE clock
970   *         is stable and can be used to clock the RC64MPLL.
971   * @note   The HSE is stopped by hardware when entering DEEPSTOP and SHUTDOWN modes.
972   * @param  __STATE__  specifies the new state of the HSE.
973   *         This parameter can be one of the following values:
974   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator.
975   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
976   * @retval None
977   */
978 #define __HAL_RCC_HSE_CONFIG(__STATE__)                      \
979   do {                                     \
980     if((__STATE__) == RCC_HSE_ON)          \
981     {                                      \
982       LL_RCC_HSE_Enable();                  \
983     }                                      \
984     else                                   \
985     {                                      \
986       LL_RCC_HSE_Disable();                \
987     }                                      \
988   } while(0U)
989 
990 /**
991   * @brief  Macro to get the HSE ready flag.
992   * @retval Returns the Ready Flag status
993   */
994 #define __HAL_RCC_GET_HSE_READYFLAG() LL_RCC_HSE_IsReady()
995 
996 /**
997   * @brief  Macro to configure the External Low Speed oscillator (LSE).
998   * @note   After enabling the LSE (RCC_LSE_ON), the application
999   *         software should wait on LSERDY flag to be set indicating that LSE clock
1000   *         is stable and can be used.
1001   * @param  __STATE__  specifies the new state of the LSE.
1002   *         This parameter can be one of the following values:
1003   *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator.
1004   *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
1005   * @retval None
1006   */
1007 #define __HAL_RCC_LSE_CONFIG(__STATE__)                        \
1008   do {                                       \
1009     if((__STATE__) == RCC_LSE_ON)            \
1010     {                                        \
1011       LL_RCC_LSE_Enable();                   \
1012     }                                        \
1013     else                                     \
1014     {                                        \
1015       LL_RCC_LSE_Disable();                  \
1016     }                                        \
1017   } while(0U)
1018 
1019 /**
1020   * @brief  Macro to get the LSE ready flag.
1021   * @retval Returns the Ready Flag status
1022   */
1023 #define __HAL_RCC_GET_LSE_READYFLAG() LL_RCC_LSE_IsReady()
1024 
1025 /**
1026   * @brief  Macro to configure the External Low Speed oscillator (LSE) in Bypass mode.
1027   * @param  __STATE__  specifies the new state of the LSE bypass configuration.
1028   *         This parameter can be one of the following values:
1029   *            @arg @ref RCC_LSE_BYPASS_OFF  Turn OFF the LSE bypass configuration.
1030   *            @arg @ref RCC_LSE_BYPASS_ON  Turn ON the LSE bypass configuration.
1031   * @retval None
1032   */
1033 #define __HAL_RCC_LSE_BYPASS_CONFIG(__STATE__)                 \
1034   do {                                       \
1035     if((__STATE__) == RCC_LSE_BYPASS_ON)     \
1036     {                                        \
1037       LL_RCC_LSE_EnableBypass();             \
1038     }                                        \
1039     else                                     \
1040     {                                        \
1041       LL_RCC_LSE_DisableBypass();            \
1042     }                                        \
1043   } while(0U)
1044 
1045 #if defined(RCC_RFSWHSECR_SATRG)
1046 /** @brief  Macros to configure HSE sense amplifier threshold.
1047   * @note   to configure HSE sense amplifier, first disable HSE
1048   *         using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
1049   *
1050   * @param  __HSE_AMPTHRES__  specifies the HSE sense amplifier threshold.
1051   *         This parameter can be one of the following values:
1052   *            @arg @ref RCC_HSEAMPTHRESHOLD_1_2  HSE bias current factor 1/2.
1053   *            @arg @ref RCC_HSEAMPTHRESHOLD_3_4  HSE bias current factor 3/4.
1054   * @retval None
1055   */
1056 #define __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__)  LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__)
1057 #endif
1058 
1059 /** @brief  Macros to configure HSE current control.
1060   * @note   to configure HSE current control, first disable HSE
1061   *         using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
1062   *
1063   * @param  __HSE_CURRENTMAX__  specifies the HSE current max limit.
1064   *         This parameter can be one of the following values:
1065   *            @arg @ref RCC_HSE_CURRENTMAX_0  HSE current max limit 0.18 mA/V.
1066   *            @arg @ref RCC_HSE_CURRENTMAX_1  HSE current max limit 0.57 mA/V.
1067   *            @arg @ref RCC_HSE_CURRENTMAX_2  HSE current max limit 0.78 mA/V.
1068   *            @arg @ref RCC_HSE_CURRENTMAX_3  HSE current max limit 1.13 mA/V.
1069   *            @arg @ref RCC_HSE_CURRENTMAX_4  HSE current max limit 0.61 mA/V.
1070   *            @arg @ref RCC_HSE_CURRENTMAX_5  HSE current max limit 1.65 mA/V.
1071   *            @arg @ref RCC_HSE_CURRENTMAX_6  HSE current max limit 2.12 mA/V.
1072   *            @arg @ref RCC_HSE_CURRENTMAX_7  HSE current max limit 2.84 mA/V.
1073   * @retval None
1074   */
1075 #define __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__)  LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__)
1076 
1077 /** @brief  Macros to configure HSE capacitor tuning.
1078   * @note   to configure HSE current control, first disable HSE
1079   *         using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
1080   *
1081   * @param  __HSE_LOAD_CAPACITANCE__  specifies the HSE capacitor value.
1082   *         This Value Between Min_Data = 0 and Max_Data = 63
1083   * @retval None
1084   */
1085 #define __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__)  LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__)
1086 
1087 /**
1088   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
1089   * @param  __LSEDRIVE__  specifies the new state of the LSE drive capability.
1090   *          This parameter can be one of the following values:
1091   *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
1092   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
1093   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
1094   *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
1095   * @retval None
1096   */
1097 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__)  LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)
1098 /**
1099   * @}
1100   */
1101 
1102 /** @defgroup RCC_CLK_SOURCE_CONFIG_MACROS Clock Source Configuration Macros
1103   * @{
1104   */
1105 /** @brief  Macros to enable or disable the main RC64MPLL.
1106   * @note   After enabling the main RC64MPLL, the application software should wait on
1107   *         PLLRDY flag to be set indicating that PLL clock is stable and can
1108   *         be used as system clock source.
1109   * @note   The main RC64MPLL can not be disabled if it is used as system clock source
1110   * @note   The main RC64MPLL is disabled by hardware when entering DEEPSTOP and SHUTDOWN modes.
1111   * @retval None
1112   */
1113 #define __HAL_RCC_RC64MPLL_ENABLE()         LL_RCC_RC64MPLL_Enable()
1114 #define __HAL_RCC_RC64MPLL_DISABLE()        LL_RCC_RC64MPLL_Disable()
1115 
1116 /**
1117   * @brief  Macro to get the RC64MPLL ready flag.
1118   * @retval Returns the Ready Flag status
1119   */
1120 #define __HAL_RCC_RC64MPLL_READYFLAG()      LL_RCC_RC64MPLL_IsReady()
1121 
1122 /** @brief  Macro to configure the RC64MPLL division factor.
1123   * @note   This function must be used only when the main RC64MPLL is disabled.
1124   * @param  __PLLD__  specifies the division factor
1125   *         This parameter must be a value of RCC_RC64MPLL_Clock_Divider.
1126   * @retval None
1127   *
1128   */
1129 #define __HAL_RCC_RC64MPLL_PRESC_CONFIG(__PLLD__) LL_RCC_SetRC64MPLLPrescaler(__PLLD__)
1130 
1131 /** @brief  Macro to configure the DIRERCT HSE division factor.
1132   * @note   This function must be used only when the main DIRECT HSE is disabled.
1133   * @param  __DIRECTHSED__  specifies the division factor
1134   *         This parameter must be a value of RCC_DIRECT_HSE_Clock_Divider.
1135   * @retval None
1136   *
1137   */
1138 #define __HAL_RCC_DIRECT_HSE_PRESC_CONFIG(__DIRECTHSED__) MODIFY_REG(RCC->CFGR, RCC_CFGR_CLKSYSDIV, __DIRECTHSED__);
1139 
1140 /** @brief  Macro to configure the RF clock frequency.
1141   * @param  __FREQ__  specifies the RF BLE clock frequency.
1142   *         This parameter must be a value of RCC_RF_Clock.
1143   * @retval None
1144   *
1145   */
1146 #define __HAL_RCC_RF_CLK_SET_CONFIG(__FREQ__) LL_RCC_SetRFClock(__FREQ__)
1147 
1148 /** @brief  Macro to get the RF BLE clock source.
1149   * @retval The RF BLE clock source. The returned value can be one of the
1150   *         following values:
1151   *              @arg @ref RCC_RF_CLK_16M
1152   *              @arg @ref RCC_RF_CLK_32M
1153   *
1154   */
1155 #define __HAL_RCC_RF_CLK_GET_CONFIG() LL_RCC_GetRFClock()
1156 
1157 /**
1158   * @brief  Macro to configure the system clock source.
1159   * @param  __SYSCLKSOURCE__  specifies the system clock source.
1160   *          This parameter can be one of the following values:
1161   *              @arg @ref RCC_SYSCLKSOURCE_RC64MPLL RC64PLL configuration is used as system clock source.
1162   *              @arg @ref RCC_SYSCLKSOURCE_DIRECT_HSE DIRECT HSE configuration is used as system clock source.
1163   * @retval None
1164   */
1165 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__)                           \
1166   do {                                                    \
1167     if((__SYSCLKSOURCE__) == RCC_SYSCLKSOURCE_RC64MPLL)   \
1168     {                                                     \
1169       LL_RCC_RC64MPLL_Enable();                           \
1170     }                                                     \
1171     else                                                  \
1172     {                                                     \
1173       LL_RCC_DIRECT_HSE_Enable();                         \
1174     }                                                     \
1175   } while(0U)
1176 
1177 /** @brief  Macro to get the clock source used as system clock.
1178   * @retval The clock source used as system clock. The returned value can be one
1179   *         of the following:
1180   *              @arg @ref RCC_SYSCLKSOURCE_RC64MPLL RC64PLL configuration is used as system clock source..
1181   *              @arg @ref RCC_SYSCLKSOURCE_DIRECT_HSE DIRECT HSE configuration is used as system clock source.
1182   */
1183 #define __HAL_RCC_GET_SYSCLK_SOURCE()        \
1184   (LL_RCC_DIRECT_HSE_IsEnabled() ? RCC_SYSCLKSOURCE_DIRECT_HSE : RCC_SYSCLKSOURCE_RC64MPLL)
1185 
1186 /**
1187   * @}
1188   */
1189 
1190 /** @defgroup RCC_MCO_CONFIG_MACROS Main Configurable Clock Output Selection Macros
1191   * @{
1192   */
1193 /**
1194   * @brief  Macro to configure the MCO clock.
1195   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
1196   *          This parameter can be one of the following values:
1197   *            @arg @ref RCC_MCOSOURCE_NOCLOCK          MCO output disabled
1198   *            @arg @ref RCC_MCO1SOURCE_SYSCLK           System  clock selected as MCO source
1199   *            @arg @ref RCC_MCO1SOURCE_HSI              HSI clock selected as MCO source
1200   *            @arg @ref RCC_MCO1SOURCE_HSE              HSE clock selected as MCO source
1201   *            @arg @ref RCC_MCOSOURCE_RC64MPLL         Main PLL clock selected as MCO source
1202   *            @arg @ref RCC_MCOSOURCE_HSI64M_DIV2048   HSI div 2048 clock selected as MCO source
1203   *            @arg @ref RCC_MCOSOURCE_SMPS             SMPS clock selected as MCO source
1204   *            @arg @ref RCC_MCOSOURCE_ADC              ADC clock selected as MCO source
1205 
1206   * @param  __MCODIV__ specifies the MCO clock prescaler.
1207   *          This parameter can be one of the following values:
1208   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
1209   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
1210   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
1211   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
1212   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
1213   *            @arg @ref RCC_MCODIV_32  MCO clock source is divided by 32
1214 
1215   */
1216 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)  LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
1217 /**
1218   * @}
1219   */
1220 /**
1221   * @}
1222   */
1223 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1224   * @brief macros to manage the specified RCC Flags and interrupts.
1225   * @{
1226   */
1227 /** @brief  Enable RCC interrupt.
1228   * @param  __INTERRUPT__  specifies the RCC interrupt sources to be enabled.
1229   *         This parameter can be any combination of the following values:
1230   *            @arg RCC_IT_LSIRDY        LSI ready interrupt enable
1231   *            @arg RCC_IT_LSERDY        LSE ready interrupt enable
1232   *            @arg RCC_IT_HSIRDY        HSI ready interrupt enable
1233   *            @arg RCC_IT_HSERDY        HSE ready interrupt enable
1234   *            @arg RCC_IT_PLLRDY        Main PLL ready interrupt enable
1235   *            @arg RCC_IT_PLL_UNLOCKRDY PLL unlock interrupt enable
1236   *            @arg RCC_IT_RTCRSTRELRDY  RTC Reset Release ready interrupt enable
1237   *            @arg RCC_IT_WDGRSTRELRDY  WDG Reset Release ready interrupt enable
1238   *            @arg RCC_IT_LPURSTRELRDY  LPU Reset Release ready interrupt enable
1239   * @retval None
1240   */
1241 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
1242 
1243 /** @brief Disable RCC interrupt.
1244   * @param  __INTERRUPT__  specifies the RCC interrupt sources to be disabled.
1245   *         This parameter can be any combination of the following values:
1246   *            @arg RCC_IT_LSIRDY        LSI ready interrupt disable
1247   *            @arg RCC_IT_LSERDY        LSE ready interrupt disable
1248   *            @arg RCC_IT_HSIRDY        HSI ready interrupt disable
1249   *            @arg RCC_IT_HSERDY        HSE ready interrupt disable
1250   *            @arg RCC_IT_PLLRDY        Main PLL ready interrupt disable
1251   *            @arg RCC_IT_PLL_UNLOCKRDY PLL Unlock interrupt disable
1252   *            @arg RCC_IT_RTCRSTRELRDY  RTC Reset Release ready interrupt disable
1253   *            @arg RCC_IT_WDGRSTRELRDY  WDG Reset Release ready interrupt disable
1254   *            @arg RCC_IT_LPURSTRELRDY  LPU Reset Release ready interrupt disable
1255   * @retval None
1256   */
1257 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
1258 
1259 /** @brief  Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0]
1260   *         bits to clear the selected interrupt pending bits.
1261   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
1262   *         This parameter can be any combination of the following values:
1263   *            @arg RCC_IT_LSIRDY        LSI ready interrupt clear
1264   *            @arg RCC_IT_LSERDY        LSE ready interrupt clear
1265   *            @arg RCC_IT_HSIRDY        HSI ready interrupt clear
1266   *            @arg RCC_IT_HSERDY        HSE ready interrupt clear
1267   *            @arg RCC_IT_PLLRDY        Main PLL ready interrupt clear
1268   *            @arg RCC_IT_PLL_UNLOCKRDY PLL Unlock interrupt clear
1269   *            @arg RCC_IT_RTCRSTRELRDY  RTC Reset Release ready interrupt clear
1270   *            @arg RCC_IT_WDGRSTRELRDY  WDG Reset Release ready interrupt clear
1271   *            @arg RCC_IT_LPURSTRELRDY  LPU Reset Release ready interrupt clear
1272   */
1273 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CIFR = (__INTERRUPT__))
1274 
1275 /** @brief  Check whether the RCC interrupt has occurred or not.
1276   * @param  __INTERRUPT__  specifies the RCC interrupt source to check.
1277   *         This parameter can be one of the following values:
1278   *            @arg RCC_IT_LSIRDY        LSI ready interrupt flag
1279   *            @arg RCC_IT_LSERDY        LSE ready interrupt flag
1280   *            @arg RCC_IT_HSIRDY        HSI ready interrupt flag
1281   *            @arg RCC_IT_HSERDY        HSE ready interrupt flag
1282   *            @arg RCC_IT_PLLRDY        Main PLL ready interrupt flag
1283   *            @arg RCC_IT_PLL_UNLOCKRDY PLL Unlock interrupt flag
1284   *            @arg RCC_IT_RTCRSTRELRDY  RTC Reset Release ready interrupt flag
1285   *            @arg RCC_IT_WDGRSTRELRDY  WDG Reset Release ready interrupt flag
1286   *            @arg RCC_IT_LPURSTRELRDY  LPU Reset Release ready interrupt flag
1287   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1288   */
1289 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
1290 /**
1291   * @}
1292   */
1293 
1294 /** @defgroup RCC_Reset_Status_Management Rest Status Flags Management
1295   * @brief macros to manage the specified RCC Reset Flags.
1296   * @{
1297   */
1298 /** @brief Set RMVF bit to clear the reset flags.
1299   *        The reset flags are: RCC_FLAG_LOCKUPRST, RCC_FLAG_WDGRST, RCC_FLAG_SFTRST,
1300   *                             RCC_FLAG_PORRST and RCC_FLAG_PADRSTF.
1301   * @retval None
1302  */
1303 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
1304 
1305 /** @brief  Check whether the selected RCC Reset flag is set or not.
1306   * @param  __FLAG__  specifies the flag to check.
1307   *         This parameter can be one of the following values:
1308   *            @arg @ref RCC_FLAG_LOCKUPRST   CPU lockup reset flag
1309   *            @arg @ref RCC_FLAG_WDGRST      Watchdog reset flag
1310   *            @arg @ref RCC_FLAG_SFTRST      Software reset flag
1311   *            @arg @ref RCC_FLAG_PORRST      Power-On or BOR reset flag
1312   *            @arg @ref RCC_FLAG_PADRSTF      NRSTn pad reset flag
1313   * @retval The new state of __FLAG__ (TRUE or FALSE).
1314   */
1315 #define __HAL_RCC_GET_FLAG(__FLAG__) (((__FLAG__) & 0x3FFFF) ?\
1316                                       ((RCC->CR & (__FLAG__)) == (__FLAG__)) :\
1317                                       ((RCC->CSR & (__FLAG__)) == (__FLAG__)))
1318 
1319 /**
1320   * @}
1321   */
1322 
1323 /** @defgroup RCC_HSECLK_BUFFER_RF_MACROS External high speed clock buffer for PLL RF2G4
1324   * @{
1325   */
1326 /** @brief  Macros to enable or disable the high speed clock buffer for PLL RF2G4.
1327   * @retval Status of the high speed clock buffer for PLL RF2G4
1328   */
1329 #define __HAL_RCC_HSEPLLBUFON_ENABLE()          LL_RCC_HSEPLLBUFON_Enable()
1330 #define __HAL_RCC_HSEPLLBUFON_DISABLE()         LL_RCC_HSEPLLBUFON_Disable()
1331 
1332 /** @brief  Macros to read the status of the high speed clock buffer for PLL RF2G4.
1333   * @retval Configuration status
1334   */
1335 #define __HAL_RCC_HSEPLLBUFON_IS_ENABLED()  LL_RCC_HSEPLLBUFON_Disable()
1336 /**
1337   * @}
1338   */
1339 
1340 /** @defgroup RCC_CLOCK_SWITCH_MACROS Clock switch macros
1341   * @{
1342   */
1343 /** @brief  Set RC64MPLL prescaler to switch the clock when the MR_BLE is enabled.
1344   * @note   The CPU/system frequency must be kept at minimum 16 MHz clock when the radio is used.
1345   * @param  __PLLD__  specifies the DIRECT_HSE or RC64MPLL value to setup.
1346   *         This parameter can be one of the following values:
1347   *            @arg @ref RCC_DIRECT_HSE_SWITCH_DIV1      DIRECT HSE division factor = 1
1348   *            @arg @ref RCC_DIRECT_HSE_SWITCH_DIV2      DIRECT HSE division factor = 2
1349   *            @arg @ref RCC_RC64MPLL_SWITCH_DIV1        RC64MPLL division factor = 1
1350   *            @arg @ref RCC_RC64MPLL_SWITCH_DIV2        RC64MPLL division factor = 2
1351   *            @arg @ref RCC_RC64MPLL_SWITCH_DIV4        RC64MPLL division factor = 4
1352   * @retval The new state of __FLAG__ (TRUE or FALSE).
1353   */
1354 #define __HAL_RCC_CLOCK_SWITCH(__PLLD__)        \
1355   do {                                                                                \
1356     if (LL_RCC_GetRC64MPLLSwitchStatus() == LL_RCC_RC64MPLL_SWITCH_STATUS_IDLE)       \
1357     {                                                                                 \
1358       LL_RCC_SwitchRC64MPLLPrescaler(__PLLD__);                                 \
1359       LL_RCC_RequestSwitchRC64MPLLClock();                                    \
1360       while (LL_RCC_GetRC64MPLLSwitchStatus() != LL_RCC_RC64MPLL_SWITCH_STATUS_DONE); \
1361       LL_RCC_ClearFlag_EOFSEQ();                                                      \
1362     }                                                                                 \
1363   } while(0U)
1364 
1365 /** @brief  Macros to enable or disable the interrupt of the CPU / system clock frequency switch.
1366   * @retval Status of the interrupt of the CPU / system clock frequency switch
1367   */
1368 #define __HAL_RCC_CLOCK_SWITCH_IT_ENABLE()             LL_RCC_EnableIT_EOFSEQ()
1369 #define __HAL_RCC_CLOCK_SWITCH_IT_DISABLE()            LL_RCC_DisableIT_EOFSEQ()
1370 
1371 /** @brief  Macros to read the configuration status of the interrupt of the CPU / system clock frequency switch.
1372   * @retval Interrupt Enable status
1373   */
1374 #define __HAL_RCC_CLOCK_SWITCH_INTERRUPT_IS_ENABLED()  LL_RCC_IsEnabledIT_EOFSEQ()
1375 
1376 /** @brief  Macros to read the status of the interrupt of the CPU / system clock frequency switch.
1377   * @retval Interrupt status
1378   */
1379 #define __HAL_RCC_CLOCK_SWITCH_INTERRUPT_STATUS()   LL_RCC_IsActiveFlag_EOFSEQ()
1380 
1381 /** @brief  Macros to clear the status of the interrupt of the CPU / system clock frequency switch.
1382   * @retval Clear Interrupt status
1383   */
1384 #define __HAL_RCC_CLOCK_SWITCH_CLEAR_INTERRUPT_STATUS()  LL_RCC_ClearFlag_EOFSEQ()
1385 /**
1386   * @}
1387   */
1388 
1389 /**
1390   * @}
1391   */
1392 
1393 /* Include RCC HAL Extended module */
1394 #include "stm32wb0x_hal_rcc_ex.h"
1395 
1396 /* Exported functions --------------------------------------------------------*/
1397 /** @addtogroup RCC_Exported_Functions
1398   * @{
1399   */
1400 
1401 
1402 /** @addtogroup RCC_Exported_Functions_Group1
1403   * @{
1404   */
1405 
1406 /* Initialization and de-initialization functions  ******************************/
1407 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1408 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1409 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1410 
1411 /**
1412   * @}
1413   */
1414 
1415 /** @addtogroup RCC_Exported_Functions_Group2
1416   * @{
1417   */
1418 
1419 /* Peripheral Control functions  ************************************************/
1420 void       HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1421 uint32_t   HAL_RCC_GetSysClockFreq(void);
1422 
1423 void       HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1424 void       HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1425 
1426 /**
1427   * @}
1428   */
1429 
1430 /**
1431   * @}
1432   */
1433 
1434 /**
1435   * @}
1436   */
1437 
1438 /**
1439   * @}
1440   */
1441 
1442 #ifdef __cplusplus
1443 }
1444 #endif
1445 
1446 #endif /* STM32WB0x_HAL_RCC_H */
1447