1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_RCC_H 21 #define STM32C0xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 #include "stm32c0xx_ll_rcc.h" 30 31 /** @addtogroup STM32C0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Private constants ---------------------------------------------------------*/ 40 /** @addtogroup RCC_Private_Constants 41 * @{ 42 */ 43 44 /** @defgroup RCC_Timeout_Value Timeout Values 45 * @{ 46 */ 47 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 48 /** 49 * @} 50 */ 51 52 /* Defines used for Flags */ 53 #define RCC_CR_REG_INDEX 1U 54 #define RCC_CSR1_REG_INDEX 2U 55 #define RCC_CSR2_REG_INDEX 3U 56 #if defined(RCC_HSI48_SUPPORT) 57 #define RCC_CRRCR_REG_INDEX 4U 58 #endif /* RCC_HSI48_SUPPORT */ 59 60 #define RCC_FLAG_MASK 0x1FU 61 62 /* Define used for IS_RCC_CLOCKTYPE() */ 63 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ 64 /** 65 * @} 66 */ 67 68 /* Private macros ------------------------------------------------------------*/ 69 /** @addtogroup RCC_Private_Macros 70 * @{ 71 */ 72 73 #if defined(RCC_CR_HSIUSB48ON) 74 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 75 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 76 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 77 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 78 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 79 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 80 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 81 #else 82 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 83 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 84 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 85 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 86 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 87 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 88 #endif /* RCC_CR_HSIUSB48ON */ 89 90 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 91 ((__HSE__) == RCC_HSE_BYPASS)) 92 93 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 94 ((__LSE__) == RCC_LSE_BYPASS)) 95 96 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 97 98 #if defined(RCC_CR_HSIUSB48ON) 99 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 100 #endif /* RCC_CR_HSIUSB48ON */ 101 102 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 103 104 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 105 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ 106 ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ 107 ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) 108 109 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 110 111 112 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ 113 & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) 114 #if defined(RCC_HSI48_SUPPORT) 115 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 116 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 117 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSIUSB48) || \ 118 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ 119 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)) 120 #else 121 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 122 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 123 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ 124 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)) 125 #endif /* RCC_HSI48_SUPPORT */ 126 127 #if defined(RCC_CR_SYSDIV) 128 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ 129 ((SYSCLK) == RCC_SYSCLK_DIV3) || ((SYSCLK) == RCC_SYSCLK_DIV4) || \ 130 ((SYSCLK) == RCC_SYSCLK_DIV5) || ((SYSCLK) == RCC_SYSCLK_DIV6) || \ 131 ((SYSCLK) == RCC_SYSCLK_DIV7) || ((SYSCLK) == RCC_SYSCLK_DIV8)) 132 #else 133 #define IS_RCC_SYSCLK(SYSCLK) ((SYSCLK) == RCC_SYSCLK_DIV1) 134 #endif /* RCC_CR_SYSDIV */ 135 136 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ 137 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ 138 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ 139 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ 140 ((HCLK) == RCC_HCLK_DIV512)) 141 142 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_APB1_DIV1) || ((__PCLK__) == RCC_APB1_DIV2) || \ 143 ((__PCLK__) == RCC_APB1_DIV4) || ((__PCLK__) == RCC_APB1_DIV8) || \ 144 ((__PCLK__) == RCC_APB1_DIV16)) 145 146 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 147 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 148 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 149 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 150 151 #if defined(STM32C011xx) 152 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 153 ((__MCOX__) == RCC_MCO1_PA9) || \ 154 ((__MCOX__) == RCC_MCO1_PF2) || \ 155 ((__MCOX__) == RCC_MCO2_PA8) || \ 156 ((__MCOX__) == RCC_MCO2_PA10) || \ 157 ((__MCOX__) == RCC_MCO2_PA14)) 158 #else 159 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 160 ((__MCOX__) == RCC_MCO1_PA9) || \ 161 ((__MCOX__) == RCC_MCO1_PF2) || \ 162 ((__MCOX__) == RCC_MCO2_PA8) || \ 163 ((__MCOX__) == RCC_MCO2_PA10) || \ 164 ((__MCOX__) == RCC_MCO2_PA14) || \ 165 ((__MCOX__) == RCC_MCO2_PA15) || \ 166 ((__MCOX__) == RCC_MCO2_PB2)) 167 #endif /* STM32C011xx */ 168 169 #if defined(RCC_CR_HSIUSB48ON) 170 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 171 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 172 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ 173 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 174 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 175 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 176 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 177 #else 178 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 179 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 180 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 181 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 182 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 183 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 184 #endif /* RCC_CR_HSIUSB48ON */ 185 186 #if defined(RCC_CR_HSIUSB48ON) 187 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 188 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 189 ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ 190 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 191 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 192 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 193 ((__SOURCE__) == RCC_MCO2SOURCE_LSE)) 194 #else 195 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 196 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 197 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 198 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 199 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 200 ((__SOURCE__) == RCC_MCO2SOURCE_LSE)) 201 #endif /* RCC_CR_HSIUSB48ON */ 202 203 #if defined(RCC_CFGR_MCOPRE_3) 204 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 205 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 206 ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \ 207 ((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128) || \ 208 ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \ 209 ((__DIV__) == RCC_MCODIV_1024)) 210 #else 211 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 212 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 213 ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \ 214 ((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128)) 215 #endif /* RCC_CFGR_MCOPRE_3 */ 216 217 #if defined(RCC_CFGR_MCO2PRE_3) 218 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ 219 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ 220 ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ 221 ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128) || \ 222 ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512) || \ 223 ((__DIV__) == RCC_MCO2DIV_1024)) 224 #else 225 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ 226 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ 227 ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ 228 ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128)) 229 #endif /* RCC_CFGR_MCO2PRE_3 */ 230 231 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 232 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 233 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 234 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 235 236 /** 237 * @} 238 */ 239 240 /* Exported types ------------------------------------------------------------*/ 241 /** @defgroup RCC_Exported_Types RCC Exported Types 242 * @{ 243 */ 244 245 246 /** 247 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 248 */ 249 typedef struct 250 { 251 uint32_t OscillatorType; /*!< The oscillators to be configured. 252 This parameter can be a value of @ref RCC_Oscillator_Type */ 253 254 uint32_t HSEState; /*!< The new state of the HSE. 255 This parameter can be a value of @ref RCC_HSE_Config */ 256 257 uint32_t LSEState; /*!< The new state of the LSE. 258 This parameter can be a value of @ref RCC_LSE_Config */ 259 260 uint32_t HSIState; /*!< The new state of the HSI. 261 This parameter can be a value of @ref RCC_HSI_Config */ 262 263 uint32_t HSIDiv; /*!< The division factor of the HSI48. 264 This parameter can be a value of @ref RCC_HSI_Div */ 265 266 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 267 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 268 269 uint32_t LSIState; /*!< The new state of the LSI. 270 This parameter can be a value of @ref RCC_LSI_Config */ 271 272 #if defined(RCC_CR_HSIUSB48ON) 273 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32C071xx devices). 274 This parameter can be a value of @ref RCC_HSI48_Config */ 275 276 #endif /* RCC_CR_HSIUSB48ON */ 277 } RCC_OscInitTypeDef; 278 279 /** 280 * @brief RCC System, AHB and APB busses clock configuration structure definition 281 */ 282 typedef struct 283 { 284 uint32_t ClockType; /*!< The clock to be configured. 285 This parameter can be a combination of @ref RCC_System_Clock_Type */ 286 287 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 288 This parameter can be a value of @ref RCC_System_Clock_Source */ 289 290 uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be 291 a value of @ref RCC_SYS_Clock_Divider */ 292 293 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 294 This parameter can be a value of @ref RCC_HCLK_Clock_Divider */ 295 296 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 297 This parameter can be a value of @ref RCC_APB1_Clock_Divider */ 298 299 300 } RCC_ClkInitTypeDef; 301 302 /** 303 * @} 304 */ 305 306 /* Exported constants --------------------------------------------------------*/ 307 /** @defgroup RCC_Exported_Constants RCC Exported Constants 308 * @{ 309 */ 310 311 /** @defgroup RCC_Oscillator_Type Oscillator Type 312 * @{ 313 */ 314 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 315 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 316 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 317 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 318 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 319 #if defined(RCC_CR_HSIUSB48ON) 320 #define RCC_OSCILLATORTYPE_HSI48 0x00000010U /*!< HSI48 to configure */ 321 #endif /* RCC_CR_HSIUSB48ON */ 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCC_HSE_Config HSE Config 327 * @{ 328 */ 329 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 330 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 331 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_LSE_Config LSE Config 337 * @{ 338 */ 339 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 340 #define RCC_LSE_ON RCC_CSR1_LSEON /*!< LSE clock activation */ 341 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR1_LSEBYP | RCC_CSR1_LSEON)) /*!< External clock source for LSE clock */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_HSI_Config HSI Config 347 * @{ 348 */ 349 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 350 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 351 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCC_HSI_Div HSI Div 357 * @{ 358 */ 359 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 360 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 361 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 362 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 363 #define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ 364 #define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ 365 #define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ 366 #define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ 367 /** 368 * @} 369 */ 370 371 372 /** @defgroup RCC_LSI_Config LSI Config 373 * @{ 374 */ 375 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 376 #define RCC_LSI_ON RCC_CSR2_LSION /*!< LSI clock activation */ 377 /** 378 * @} 379 */ 380 381 #if defined(RCC_CR_HSIUSB48ON) 382 /** @defgroup RCC_HSI48_Config HSI48 Config 383 * @{ 384 */ 385 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 386 #define RCC_HSI48_ON RCC_CR_HSIUSB48ON /*!< HSI48 clock activation */ 387 /** 388 * @} 389 */ 390 #endif /* RCC_CR_HSIUSB48ON */ 391 392 /** @defgroup RCC_System_Clock_Type System Clock Type 393 * @{ 394 */ 395 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 396 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 397 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_System_Clock_Source System Clock Source 403 * @{ 404 */ 405 #define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ 406 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ 407 #if defined(RCC_HSI48_SUPPORT) 408 #define RCC_SYSCLKSOURCE_HSIUSB48 RCC_CFGR_SW_1 /*!< HSIUSB48 selection used as system clock */ 409 #endif /* RCC_HSI48_SUPPORT */ 410 #define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ 411 #define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ 412 /** 413 * @} 414 */ 415 416 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 417 * @{ 418 */ 419 #define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ 420 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ 421 #if defined(RCC_HSI48_SUPPORT) 422 #define RCC_SYSCLKSOURCE_STATUS_HSIUSB48 RCC_CFGR_SWS_1 /*!< HSIUSB48 used as system clock */ 423 #endif /* RCC_HSI48_SUPPORT */ 424 #define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ 425 #define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCC_SYS_Clock_Divider RCC SYS Clock Divider 431 * @{ 432 */ 433 #if defined(RCC_CR_SYSDIV) 434 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 435 #define RCC_SYSCLK_DIV2 RCC_CR_SYSDIV_0 /*!< SYSCLK is divided by 2 */ 436 #define RCC_SYSCLK_DIV3 RCC_CR_SYSDIV_1 /*!< SYSCLK is divided by 3 */ 437 #define RCC_SYSCLK_DIV4 (RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 4 */ 438 #define RCC_SYSCLK_DIV5 RCC_CR_SYSDIV_2 /*!< SYSCLK is divided by 5 */ 439 #define RCC_SYSCLK_DIV6 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 6 */ 440 #define RCC_SYSCLK_DIV7 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1) /*!< SYSCLK is divided by 7 */ 441 #define RCC_SYSCLK_DIV8 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK is divided by 8 */ 442 #else 443 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 444 #endif /* RCC_CR_SYSDIV */ 445 /** 446 * @} 447 */ 448 449 /** @defgroup RCC_HCLK_Clock_Divider RCC HCLK Clock Divider 450 * @{ 451 */ 452 #define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ 453 #define RCC_HCLK_DIV2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */ 454 #define RCC_HCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */ 455 #define RCC_HCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */ 456 #define RCC_HCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */ 457 #define RCC_HCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */ 458 #define RCC_HCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */ 459 #define RCC_HCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */ 460 #define RCC_HCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup RCC_APB1_Clock_Divider RCC APB1 Clock Divider 466 * @{ 467 */ 468 #define RCC_APB1_DIV1 0x00000000U /*!< APB not divided */ 469 #define RCC_APB1_DIV2 RCC_CFGR_PPRE_2 /*!< APB divided by 2 */ 470 #define RCC_APB1_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< APB divided by 4 */ 471 #define RCC_APB1_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< APB divided by 4 */ 472 #define RCC_APB1_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< APB divided by 16 */ 473 /** 474 * @} 475 */ 476 477 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 478 * @{ 479 */ 480 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ 481 #define RCC_RTCCLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 482 #define RCC_RTCCLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 483 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_MCO_Index MCO Index 489 * @{ 490 */ 491 492 /* @cond */ 493 /* 32 28 20 16 0 494 -------------------------------- 495 | MCO | GPIO | GPIO | GPIO | 496 | Index | AF | Port | Pin | 497 -------------------------------*/ 498 499 #define RCC_MCO_GPIOPORT_POS 16U 500 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 501 #define RCC_MCO_GPIOAF_POS 20U 502 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 503 #define RCC_MCO_INDEX_POS 28U 504 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 505 506 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 507 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ 508 /* @endcond */ 509 510 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ 511 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 512 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 513 #define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ 514 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 515 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) 516 #define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ 517 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 518 (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 519 #define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ 520 521 #define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ 522 (GPIO_AF15_MCO2 << RCC_MCO_GPIOAF_POS) | \ 523 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 524 #define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ 525 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ 526 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) 527 #define RCC_MCO2_PA14 (RCC_MCO2_INDEX |\ 528 (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | \ 529 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_14) 530 #if !defined(STM32C011xx) 531 #define RCC_MCO2_PA15 (RCC_MCO2_INDEX |\ 532 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ 533 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) 534 #define RCC_MCO2_PB2 (RCC_MCO2_INDEX |\ 535 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ 536 (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 537 #endif /* STM32C011xx */ 538 #define RCC_MCO2 RCC_MCO2_PA10 /*!< Alias for compatibility */ 539 540 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 541 /** 542 * @} 543 */ 544 545 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 546 * @{ 547 */ 548 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 549 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 550 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 551 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 552 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 553 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 554 #if defined(RCC_HSI48_SUPPORT) 555 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 556 #endif /* RCC_HSI48_SUPPORT */ 557 /** 558 * @} 559 */ 560 561 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 562 * @{ 563 */ 564 #define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ 565 #define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ 566 #define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI selection as MCO2 source */ 567 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ 568 #define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */ 569 #define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */ 570 #if defined(RCC_HSI48_SUPPORT) 571 #define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_3 /*!< HSI48 selection as MCO2 source */ 572 #endif /* RCC_HSI48_SUPPORT */ 573 /** 574 * @} 575 */ 576 /** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler 577 * @{ 578 */ 579 #define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ 580 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ 581 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ 582 #define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ 583 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ 584 #define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ 585 #define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ 586 #define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ 587 #if defined(RCC_CFGR_MCOPRE_3) 588 #define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ 589 #define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ 590 #define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024*/ 591 #endif /* RCC_CFGR_MCOPRE_3 */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler 597 * @{ 598 */ 599 #define RCC_MCO2DIV_1 0x00000000U /*!< MCO not divided */ 600 #define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO divided by 2 */ 601 #define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO divided by 4 */ 602 #define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 8 */ 603 #define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO divided by 16 */ 604 #define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 32 */ 605 #define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 64 */ 606 #define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 128 */ 607 #if defined(RCC_CFGR_MCO2PRE_3) 608 #define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO divided by 256 */ 609 #define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 512 */ 610 #define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 1024*/ 611 #endif /* RCC_CFGR_MCO2PRE_3 */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCC_Interrupt Interrupts 617 * @{ 618 */ 619 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 620 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 621 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 622 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 623 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 624 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 625 #if defined(RCC_HSI48_SUPPORT) 626 #define RCC_IT_HSI48RDY RCC_CIFR_HSIUSB48RDYF /*!< HSI48 Ready Interrupt flag */ 627 #endif /* RCC_HSI48_SUPPORT */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup RCC_Flag Flags 633 * Elements values convention: XXXYYYYYb 634 * - YYYYY : Flag position in the register 635 * - XXX : Register index 636 * - 001: CR register 637 * - 010: CSR1 register 638 * - 011: CSR2 register 639 * @{ 640 */ 641 /* Flags in the CR register */ 642 #define RCC_FLAG_HSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 643 #define RCC_FLAG_HSERDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 644 #if defined(RCC_HSI48_SUPPORT) 645 /* Flags in the CR register */ 646 #define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 647 #endif /* RCC_HSI48_SUPPORT */ 648 649 /* Flags in the CSR1 register */ 650 #define RCC_FLAG_LSERDY ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSERDY_Pos) /*!< LSE Ready flag */ 651 #define RCC_FLAG_LSECSSD ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 652 653 /* Flags in the CSR2 register */ 654 #define RCC_FLAG_LSIRDY ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LSIRDY_Pos) /*!< LSI Ready flag */ 655 #define RCC_FLAG_OBLRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 656 #define RCC_FLAG_PINRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PINRSTF_Pos) /*!< PIN reset flag */ 657 #define RCC_FLAG_PWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ 658 #define RCC_FLAG_SFTRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_SFTRSTF_Pos) /*!< Software Reset flag */ 659 #define RCC_FLAG_IWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 660 #define RCC_FLAG_WWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 661 #define RCC_FLAG_LPWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 662 663 /** 664 * @} 665 */ 666 667 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 668 * @{ 669 */ 670 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 671 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< LSE medium low drive capability */ 672 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< LSE medium high drive capability */ 673 #define RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< LSE high drive capability */ 674 /** 675 * @} 676 */ 677 678 /** 679 * @} 680 */ 681 682 /* Exported macros -----------------------------------------------------------*/ 683 684 /** @defgroup RCC_Exported_Macros RCC Exported Macros 685 * @{ 686 */ 687 688 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 689 * @brief Enable or disable the AHB peripheral clock. 690 * @note After reset, the peripheral clock (used for registers read/write access) 691 * is disabled and the application software has to enable this clock before 692 * using it. 693 * @{ 694 */ 695 696 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 697 __IO uint32_t tmpreg; \ 698 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 699 /* Delay after an RCC peripheral clock enabling */ \ 700 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 701 UNUSED(tmpreg); \ 702 } while(0U) 703 704 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 705 __IO uint32_t tmpreg; \ 706 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 707 /* Delay after an RCC peripheral clock enabling */ \ 708 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 709 UNUSED(tmpreg); \ 710 } while(0U) 711 712 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 713 __IO uint32_t tmpreg; \ 714 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 715 /* Delay after an RCC peripheral clock enabling */ \ 716 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 717 UNUSED(tmpreg); \ 718 } while(0U) 719 720 721 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 722 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) 723 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 724 725 /** 726 * @} 727 */ 728 729 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable 730 * @brief Enable or disable the IO Ports clock. 731 * @note After reset, the IO ports clock (used for registers read/write access) 732 * is disabled and the application software has to enable this clock before 733 * using it. 734 * @{ 735 */ 736 737 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 738 __IO uint32_t tmpreg; \ 739 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 740 /* Delay after an RCC peripheral clock enabling */ \ 741 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 742 UNUSED(tmpreg); \ 743 } while(0U) 744 745 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 746 __IO uint32_t tmpreg; \ 747 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 748 /* Delay after an RCC peripheral clock enabling */ \ 749 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 750 UNUSED(tmpreg); \ 751 } while(0U) 752 753 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 754 __IO uint32_t tmpreg; \ 755 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 756 /* Delay after an RCC peripheral clock enabling */ \ 757 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 758 UNUSED(tmpreg); \ 759 } while(0U) 760 #if defined (GPIOD) 761 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 762 __IO uint32_t tmpreg; \ 763 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 764 /* Delay after an RCC peripheral clock enabling */ \ 765 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 766 UNUSED(tmpreg); \ 767 } while(0U) 768 #endif /* GPIOD */ 769 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 770 __IO uint32_t tmpreg; \ 771 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 772 /* Delay after an RCC peripheral clock enabling */ \ 773 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 774 UNUSED(tmpreg); \ 775 } while(0U) 776 777 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 778 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 779 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 780 #if defined (GPIOD) 781 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) 782 #endif /* GPIOD */ 783 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) 784 785 /** 786 * @} 787 */ 788 789 /** @defgroup RCC_APB1_GRP1_Clock_Enable_Disable APB1_GRP1 Peripheral Clock Enable Disable 790 * @brief Enable or disable the APB1 peripheral clock. 791 * @note After reset, the peripheral clock (used for registers read/write access) 792 * is disabled and the application software has to enable this clock before 793 * using it. 794 * @{ 795 */ 796 #if defined(TIM2) 797 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 798 __IO uint32_t tmpreg; \ 799 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 800 /* Delay after an RCC peripheral clock enabling */ \ 801 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 802 UNUSED(tmpreg); \ 803 } while(0) 804 #endif /* TIM2 */ 805 806 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 807 __IO uint32_t tmpreg; \ 808 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 809 /* Delay after an RCC peripheral clock enabling */ \ 810 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 811 UNUSED(tmpreg); \ 812 } while(0U) 813 814 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 815 __IO uint32_t tmpreg; \ 816 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 817 /* Delay after an RCC peripheral clock enabling */ \ 818 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 819 UNUSED(tmpreg); \ 820 } while(0U) 821 822 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 823 __IO uint32_t tmpreg; \ 824 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 825 /* Delay after an RCC peripheral clock enabling */ \ 826 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 827 UNUSED(tmpreg); \ 828 } while(0U) 829 830 #if defined (USB_DRD_FS) 831 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 832 __IO uint32_t tmpreg; \ 833 SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 834 /* Delay after an RCC peripheral clock enabling */ \ 835 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 836 UNUSED(tmpreg); \ 837 } while(0U) 838 #endif /* USB_DRD_FS */ 839 840 #if defined(SPI2) 841 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 842 __IO uint32_t tmpreg; \ 843 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 844 /* Delay after an RCC peripheral clock enabling */ \ 845 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 846 UNUSED(tmpreg); \ 847 } while(0) 848 #endif /* SPI2 */ 849 850 #if defined(CRS) 851 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 852 __IO uint32_t tmpreg; \ 853 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 854 /* Delay after an RCC peripheral clock enabling */ \ 855 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 856 UNUSED(tmpreg); \ 857 } while(0) 858 #endif /* CRS */ 859 860 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 861 __IO uint32_t tmpreg; \ 862 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 863 /* Delay after an RCC peripheral clock enabling */ \ 864 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 865 UNUSED(tmpreg); \ 866 } while(0U) 867 868 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 869 __IO uint32_t tmpreg; \ 870 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 871 /* Delay after an RCC peripheral clock enabling */ \ 872 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 873 UNUSED(tmpreg); \ 874 } while(0U) 875 876 #if defined(I2C2) 877 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 878 __IO uint32_t tmpreg; \ 879 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 880 /* Delay after an RCC peripheral clock enabling */ \ 881 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 882 UNUSED(tmpreg); \ 883 } while(0) 884 #endif /* I2C2 */ 885 886 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ 887 __IO uint32_t tmpreg; \ 888 SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 889 /* Delay after an RCC peripheral clock enabling */ \ 890 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 891 UNUSED(tmpreg); \ 892 } while(0U) 893 894 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 895 __IO uint32_t tmpreg; \ 896 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 897 /* Delay after an RCC peripheral clock enabling */ \ 898 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 899 UNUSED(tmpreg); \ 900 } while(0U) 901 #if defined(TIM2) 902 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) 903 #endif /* TIM2 */ 904 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) 905 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) 906 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) 907 #if defined (USB_DRD_FS) 908 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) 909 #endif /* USB_DRD_FS */ 910 #if defined(SPI2) 911 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) 912 #endif /* SPI2 */ 913 #if defined(CRS) 914 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) 915 #endif /* CRS */ 916 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) 917 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) 918 #if defined(I2C2) 919 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) 920 #endif /* I2C2 */ 921 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) 922 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) 923 /** 924 * @} 925 */ 926 927 /** @defgroup RCC_APB1_GRP2_Clock_Enable_Disable APB1_GRP2 Peripheral Clock Enable Disable 928 * @brief Enable or disable the APB1_GRP2 peripheral clock. 929 * @note After reset, the peripheral clock (used for registers read/write access) 930 * is disabled and the application software has to enable this clock before 931 * using it. 932 * @{ 933 */ 934 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 935 __IO uint32_t tmpreg; \ 936 SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 937 /* Delay after an RCC peripheral clock enabling */ \ 938 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 939 UNUSED(tmpreg); \ 940 } while(0U) 941 942 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 943 __IO uint32_t tmpreg; \ 944 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 945 /* Delay after an RCC peripheral clock enabling */ \ 946 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 947 UNUSED(tmpreg); \ 948 } while(0U) 949 950 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 951 __IO uint32_t tmpreg; \ 952 SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 953 /* Delay after an RCC peripheral clock enabling */ \ 954 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 955 UNUSED(tmpreg); \ 956 } while(0U) 957 958 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 959 __IO uint32_t tmpreg; \ 960 SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 961 /* Delay after an RCC peripheral clock enabling */ \ 962 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 963 UNUSED(tmpreg); \ 964 } while(0U) 965 966 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 967 __IO uint32_t tmpreg; \ 968 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 969 /* Delay after an RCC peripheral clock enabling */ \ 970 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 971 UNUSED(tmpreg); \ 972 } while(0U) 973 974 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 975 __IO uint32_t tmpreg; \ 976 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 977 /* Delay after an RCC peripheral clock enabling */ \ 978 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 979 UNUSED(tmpreg); \ 980 } while(0U) 981 982 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 983 __IO uint32_t tmpreg; \ 984 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 985 /* Delay after an RCC peripheral clock enabling */ \ 986 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 987 UNUSED(tmpreg); \ 988 } while(0U) 989 990 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 991 __IO uint32_t tmpreg; \ 992 SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 993 /* Delay after an RCC peripheral clock enabling */ \ 994 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 995 UNUSED(tmpreg); \ 996 } while(0U) 997 998 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) 999 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) 1000 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) 1001 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) 1002 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) 1003 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) 1004 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) 1005 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status 1011 * @brief Check whether the AHB peripheral clock is enabled or not. 1012 * @note After reset, the peripheral clock (used for registers read/write access) 1013 * is disabled and the application software has to enable this clock before 1014 * using it. 1015 * @{ 1016 */ 1017 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U) 1018 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != 0U) 1019 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U) 1020 1021 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U) 1022 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == 0U) 1023 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U) 1024 /** 1025 * @} 1026 */ 1027 1028 /** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status 1029 * @brief Check whether the IO Port clock is enabled or not. 1030 * @note After reset, the peripheral clock (used for registers read/write access) 1031 * is disabled and the application software has to enable this clock before 1032 * using it. 1033 * @{ 1034 */ 1035 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U) 1036 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U) 1037 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U) 1038 #if defined (GPIOD) 1039 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U) 1040 #endif /* GPIOD */ 1041 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != 0U) 1042 1043 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U) 1044 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U) 1045 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U) 1046 #if defined (GPIOD) 1047 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U) 1048 #endif /* GPIOD */ 1049 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == 0U) 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup RCC_APB1_GRP1_Clock_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Enabled or Disabled Status 1055 * @brief Check whether the APB1_GRP1 peripheral clock is enabled or not. 1056 * @note After reset, the peripheral clock (used for registers read/write access) 1057 * is disabled and the application software has to enable this clock before 1058 * using it. 1059 * @{ 1060 */ 1061 #if defined(TIM2) 1062 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) 1063 #endif /* TIM2 */ 1064 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) 1065 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) 1066 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) 1067 #if defined (USB_DRD_FS) 1068 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) 1069 #endif /* USB_DRD_FS */ 1070 #if defined(SPI2) 1071 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) 1072 #endif /* SPI2 */ 1073 #if defined(CRS) 1074 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) 1075 #endif /* CRS */ 1076 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) 1077 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) 1078 #if defined(I2C2) 1079 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) 1080 #endif /* I2C2 */ 1081 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) 1082 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) 1083 1084 #if defined(TIM2) 1085 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) 1086 #endif /* TIM2 */ 1087 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) 1088 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) 1089 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) 1090 #if defined (USB_DRD_FS) 1091 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) 1092 #endif /* USB_DRD_FS */ 1093 #if defined(SPI2) 1094 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) 1095 #endif /* SPI2 */ 1096 #if defined(CRS) 1097 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) 1098 #endif /* CRS */ 1099 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) 1100 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) 1101 #if defined(I2C2) 1102 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) 1103 #endif /* I2C2 */ 1104 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) 1105 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) 1106 /** 1107 * @} 1108 */ 1109 1110 /** @defgroup RCC_APB1_GRP2_Clock_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Enabled or Disabled Status 1111 * @brief Check whether the APB1_GRP2 peripheral clock is enabled or not. 1112 * @note After reset, the peripheral clock (used for registers read/write access) 1113 * is disabled and the application software has to enable this clock before 1114 * using it. 1115 * @{ 1116 */ 1117 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) 1118 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) 1119 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) 1120 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) 1121 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) 1122 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) 1123 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) 1124 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) 1125 1126 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) 1127 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) 1128 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) 1129 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) 1130 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) 1131 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) 1132 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) 1133 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) 1134 /** 1135 * @} 1136 */ 1137 1138 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 1139 * @brief Force or release AHB1 peripheral reset. 1140 * @{ 1141 */ 1142 #define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) 1143 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1144 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1145 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1146 1147 #define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) 1148 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1149 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1150 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1151 /** 1152 * @} 1153 */ 1154 1155 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset 1156 * @brief Force or release IO Port reset. 1157 * @{ 1158 */ 1159 #define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) 1160 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1161 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1162 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1163 #if defined (GPIOD) 1164 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1165 #endif /* GPIOD */ 1166 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1167 1168 #define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) 1169 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1170 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1171 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1172 #if defined (GPIOD) 1173 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1174 #endif /* GPIOD */ 1175 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1176 /** 1177 * @} 1178 */ 1179 1180 /** @defgroup RCC_APB1_GRP1_Force_Release_Reset APB1_GRP1 Peripheral Force Release Reset 1181 * @brief Force or release APB1_GRP1 peripheral reset. 1182 * @{ 1183 */ 1184 #define __HAL_RCC_APB1_GRP1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) 1185 #if defined(TIM2) 1186 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1187 #endif /* TIM2 */ 1188 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1189 #if defined (USB_DRD_FS) 1190 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1191 #endif /* USB_DRD_FS */ 1192 #if defined(SPI2) 1193 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1194 #endif /* SPI2 */ 1195 #if defined(CRS) 1196 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1197 #endif /* CRS */ 1198 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1199 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1200 #if defined(I2C2) 1201 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1202 #endif /* I2C2 */ 1203 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 1204 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1205 1206 #define __HAL_RCC_APB1_GRP1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) 1207 #if defined(TIM2) 1208 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1209 #endif /* TIM2 */ 1210 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1211 #if defined (USB_DRD_FS) 1212 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1213 #endif /* USB_DRD_FS */ 1214 #if defined(SPI2) 1215 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1216 #endif /* SPI2 */ 1217 #if defined(CRS) 1218 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1219 #endif /* CRS */ 1220 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1221 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1222 #if defined(I2C2) 1223 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1224 #endif /* I2C2 */ 1225 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 1226 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1227 /** 1228 * @} 1229 */ 1230 1231 /** @defgroup RCC_APB1_GRP2_Force_Release_Reset APB1_GRP2 Peripheral Force Release Reset 1232 * @brief Force or release APB1_GRP2 peripheral reset. 1233 * @{ 1234 */ 1235 #define __HAL_RCC_APB1_GRP2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) 1236 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1237 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1238 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1239 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1240 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 1241 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1242 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 1243 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1244 1245 #define __HAL_RCC_APB1_GRP2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00000000U) 1246 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1247 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1248 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1249 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1250 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 1251 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1252 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 1253 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1254 /** 1255 * @} 1256 */ 1257 1258 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable 1259 * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. 1260 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1261 * power consumption. 1262 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1263 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1264 * @{ 1265 */ 1266 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1267 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1268 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1269 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1270 1271 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1272 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1273 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1274 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1275 /** 1276 * @} 1277 */ 1278 1279 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable 1280 * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. 1281 * @note IOPORT clock gating in SLEEP mode can be used to further reduce 1282 * power consumption. 1283 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1284 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1285 * @{ 1286 */ 1287 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1288 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1289 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1290 #if defined (GPIOD) 1291 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1292 #endif /* GPIOD */ 1293 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1294 1295 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1296 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1297 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1298 #if defined (GPIOD) 1299 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1300 #endif /* GPIOD */ 1301 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1302 /** 1303 * @} 1304 */ 1305 1306 /** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enable_Disable APB1_GRP1 Peripheral Clock Sleep Enable Disable 1307 * @brief Enable or disable the APB1_GRP1 peripheral clock during Low Power (Sleep) mode. 1308 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1309 * power consumption. 1310 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1311 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1312 * @{ 1313 */ 1314 #if defined(TIM2) 1315 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 1316 #endif /* TIM2 */ 1317 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1318 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1319 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1320 #if defined (USB_DRD_FS) 1321 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 1322 #endif /* USB_DRD_FS */ 1323 #if defined(SPI2) 1324 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 1325 #endif /* SPI2 */ 1326 #if defined(CRS) 1327 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 1328 #endif /* CRS */ 1329 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1330 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1331 #if defined(I2C2) 1332 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 1333 #endif /* I2C2 */ 1334 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 1335 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1336 1337 #if defined(TIM2) 1338 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 1339 #endif /* TIM2 */ 1340 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1341 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1342 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1343 #if defined (USB_DRD_FS) 1344 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 1345 #endif /* USB_DRD_FS */ 1346 #if defined(SPI2) 1347 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 1348 #endif /* SPI2 */ 1349 #if defined(CRS) 1350 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 1351 #endif /* CRS */ 1352 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1353 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1354 #if defined(I2C2) 1355 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 1356 #endif /* I2C2 */ 1357 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 1358 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1359 /** 1360 * @} 1361 */ 1362 1363 /** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enable_Disable APB1_GRP2 Peripheral Clock Sleep Enable Disable 1364 * @brief Enable or disable the APB1_GRP2 peripheral clock during Low Power (Sleep) mode. 1365 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1366 * power consumption. 1367 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1368 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1369 * @{ 1370 */ 1371 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1372 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1373 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1374 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1375 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 1376 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1377 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 1378 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1379 1380 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1381 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1382 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1383 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1384 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 1385 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1386 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 1387 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1388 /** 1389 * @} 1390 */ 1391 1392 1393 /** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status 1394 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. 1395 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1396 * power consumption. 1397 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1398 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1399 * @{ 1400 */ 1401 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) 1402 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) 1403 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) 1404 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) 1405 1406 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) 1407 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) 1408 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) 1409 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status 1415 * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. 1416 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1417 * power consumption. 1418 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1419 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1420 * @{ 1421 */ 1422 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) 1423 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) 1424 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) 1425 #if defined (GPIOD) 1426 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) 1427 #endif /* GPIOD */ 1428 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) 1429 1430 1431 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) 1432 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) 1433 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) 1434 #if defined (GPIOD) 1435 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) 1436 #endif /* GPIOD */ 1437 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup RCC_APB1_GRP1_Clock_Sleep_Enabled_Disabled_Status APB1_GRP1 Peripheral Clock Sleep Enabled or Disabled Status 1443 * @brief Check whether the APB1_GRP1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1444 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1445 * power consumption. 1446 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1447 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1448 * @{ 1449 */ 1450 #if defined(TIM2) 1451 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET) 1452 #endif /* TIM2 */ 1453 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) 1454 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) 1455 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) 1456 #if defined (USB_DRD_FS) 1457 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) 1458 #endif /* USB_DRD_FS */ 1459 #if defined(SPI2) 1460 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) 1461 #endif /* SPI2 */ 1462 #if defined(CRS) 1463 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) 1464 #endif /* CRS */ 1465 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) 1466 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) 1467 #if defined(I2C2) 1468 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) 1469 #endif /* I2C2 */ 1470 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) 1471 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) 1472 1473 #if defined(TIM2) 1474 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET) 1475 #endif /* TIM2 */ 1476 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) 1477 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) 1478 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) 1479 #if defined (USB_DRD_FS) 1480 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) 1481 #endif /* USB_DRD_FS */ 1482 #if defined(SPI2) 1483 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) 1484 #endif /* SPI2 */ 1485 #if defined(CRS) 1486 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) 1487 #endif /* CRS */ 1488 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) 1489 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) 1490 #if defined(I2C2) 1491 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) 1492 #endif /* I2C2 */ 1493 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) 1494 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) 1495 /** 1496 * @} 1497 */ 1498 1499 /** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enabled_Disabled_Status APB1_GRP2 Peripheral Clock Sleep Enabled or Disabled Status 1500 * @brief Check whether the APB1_GRP2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1501 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1502 * power consumption. 1503 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1504 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1505 * @{ 1506 */ 1507 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) 1508 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) 1509 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) 1510 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) 1511 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) 1512 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) 1513 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) 1514 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) 1515 1516 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) 1517 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) 1518 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) 1519 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) 1520 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) 1521 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) 1522 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) 1523 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) 1524 /** 1525 * @} 1526 */ 1527 1528 /** @defgroup RCC_RTC_Domain_Reset RCC RTC Domain Reset 1529 * @{ 1530 */ 1531 1532 /** @brief Macros to force or release the RTC domain reset. 1533 * @note This function resets the RTC peripheral 1534 * and the RTC clock source selection in RCC_CSR1 register. 1535 * @retval None 1536 */ 1537 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST) 1538 1539 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST) 1540 /** 1541 * @} 1542 */ 1543 1544 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1545 * @{ 1546 */ 1547 1548 /** @brief Macros to enable or disable the RTC clock. 1549 * @note These macros must be used after the RTC clock source was selected. 1550 * @retval None 1551 */ 1552 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN) 1553 1554 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN) 1555 /** 1556 * @} 1557 */ 1558 1559 /** @defgroup RCC_Clock_Configuration RCC Clock Configuration 1560 * @{ 1561 */ 1562 1563 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 1564 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1565 * It is used (enabled by hardware) as system clock source after startup 1566 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1567 * of the HSE used directly or indirectly as system clock (if the Clock 1568 * Security System CSS is enabled). 1569 * @note After enabling the HSI, the application software should wait on HSIRDY 1570 * flag to be set indicating that HSI clock is stable and can be used as 1571 * system clock source. 1572 * This parameter can be: ENABLE or DISABLE. 1573 * @retval None 1574 */ 1575 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 1576 1577 /** @brief Macros to disable the Internal High Speed oscillator (HSI). 1578 * @note HSI can not be stopped if it is used as system clock source. In this case, 1579 * you have to select another source of the system clock then stop the HSI. 1580 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1581 * clock cycles. 1582 * @retval None 1583 */ 1584 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 1585 1586 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1587 * @note The calibration is used to compensate for the variations in voltage 1588 * and temperature that influence the frequency of the internal HSI RC. 1589 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 1590 * (default is RCC_HSICALIBRATION_DEFAULT). 1591 * This parameter must be a number between 0 and 127. 1592 * @retval None 1593 */ 1594 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 1595 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 1596 1597 /** 1598 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 1599 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 1600 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 1601 * speed because of the HSI startup time. 1602 * @note The enable of this function has not effect on the HSION bit. 1603 * This parameter can be: ENABLE or DISABLE. 1604 * @retval None 1605 */ 1606 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 1607 1608 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 1609 1610 /** @brief Macro to configure the HSISYS clock. 1611 * @param __HSIDIV__ specifies the HSI16 division factor. 1612 * This parameter can be one of the following values: 1613 * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 1614 * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 1615 * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 1616 * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 1617 * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 1618 * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 1619 * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 1620 * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 1621 */ 1622 #define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ 1623 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) 1624 1625 /** @brief Macro to get the HSI divider. 1626 * @retval The HSI divider. The returned value can be one 1627 * of the following: 1628 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 1629 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 1630 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 (default after reset) 1631 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 1632 * - RCC_CR_HSIDIV_16 HSI oscillator divided by 16 1633 * - RCC_CR_HSIDIV_32 HSI oscillator divided by 32 1634 * - RCC_CR_HSIDIV_64 HSI oscillator divided by 64 1635 * - RCC_CR_HSIDIV_128 HSI oscillator divided by 128 1636 */ 1637 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 1638 1639 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 1640 * @note After enabling the LSI, the application software should wait on 1641 * LSIRDY flag to be set indicating that LSI clock is stable and can 1642 * be used to clock the IWDG and/or the RTC. 1643 * @note LSI can not be disabled if the IWDG is running. 1644 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1645 * clock cycles. 1646 * @retval None 1647 */ 1648 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR2, RCC_CSR2_LSION) 1649 1650 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION) 1651 1652 /** 1653 * @brief Macro to configure the External High Speed oscillator (HSE). 1654 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1655 * supported by this macro. User should request a transition to HSE Off 1656 * first and then HSE On or HSE Bypass. 1657 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1658 * software should wait on HSERDY flag to be set indicating that HSE clock 1659 * is stable and can be used to clock the PLL and/or system clock. 1660 * @note HSE state can not be changed if it is used directly or through the 1661 * PLL as system clock. In this case, you have to select another source 1662 * of the system clock then change the HSE state (ex. disable it). 1663 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1664 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1665 * was previously enabled you have to enable it again after calling this 1666 * function. 1667 * @param __STATE__ specifies the new state of the HSE. 1668 * This parameter can be one of the following values: 1669 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 1670 * 6 HSE oscillator clock cycles. 1671 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 1672 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 1673 * @retval None 1674 */ 1675 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1676 do { \ 1677 if((__STATE__) == RCC_HSE_ON) \ 1678 { \ 1679 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1680 } \ 1681 else if((__STATE__) == RCC_HSE_BYPASS) \ 1682 { \ 1683 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1684 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1685 } \ 1686 else \ 1687 { \ 1688 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1689 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1690 } \ 1691 } while(0U) 1692 1693 /** 1694 * @brief Macro to configure the External Low Speed oscillator (LSE). 1695 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 1696 * supported by this macro. User should request a transition to LSE Off 1697 * first and then LSE On or LSE Bypass. 1698 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1699 * software should wait on LSERDY flag to be set indicating that LSE clock 1700 * is stable and can be used to clock the RTC. 1701 * @param __STATE__ specifies the new state of the LSE. 1702 * This parameter can be one of the following values: 1703 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 1704 * 6 LSE oscillator clock cycles. 1705 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 1706 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1707 * @retval None 1708 */ 1709 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1710 do { \ 1711 if((__STATE__) == RCC_LSE_ON) \ 1712 { \ 1713 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1714 } \ 1715 else if((__STATE__) == RCC_LSE_BYPASS) \ 1716 { \ 1717 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ 1718 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1719 } \ 1720 else \ 1721 { \ 1722 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1723 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ 1724 } \ 1725 } while(0U) 1726 #if defined(RCC_CR_HSIUSB48ON) 1727 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 1728 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 1729 * @note After enabling the HSI48, the application software should wait on HSI48RDY 1730 * flag to be set indicating that HSI48 clock is stable. 1731 * This parameter can be: ENABLE or DISABLE. 1732 * @retval None 1733 */ 1734 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIUSB48ON) 1735 1736 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIUSB48ON) 1737 #endif /* RCC_CR_HSIUSB48ON */ 1738 /** 1739 * @} 1740 */ 1741 1742 /** @addtogroup RCC_RTC_Clock_Configuration 1743 * @{ 1744 */ 1745 1746 /** @brief Macros to configure the RTC clock (RTCCLK). 1747 * @note As the RTC clock configuration bits are in the RTC domain and write 1748 * access is denied to this domain after reset, you have to enable write 1749 * access using the Power RTC Access macro before to configure 1750 * the RTC clock source (to be done once after reset). 1751 * @note Once the RTC clock is configured it cannot be changed unless the 1752 * RTC domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1753 * a Power On Reset (POR). 1754 * 1755 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1756 * This parameter can be one of the following values: 1757 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 1758 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1759 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1760 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1761 * 1762 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1763 * work in STOP and STANDBY modes, and can be used as wakeup source. 1764 * However, when the HSE clock is used as RTC clock source, the RTC 1765 * cannot be used in STOP and STANDBY modes. 1766 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1767 * RTC clock source). 1768 * @retval None 1769 */ 1770 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 1771 MODIFY_REG( RCC->CSR1, RCC_CSR1_RTCSEL, (__RTC_CLKSOURCE__)) 1772 1773 1774 /** @brief Macro to get the RTC clock source. 1775 * @retval The returned value can be one of the following: 1776 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 1777 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1778 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1779 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1780 */ 1781 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL))) 1782 1783 /** 1784 * @} 1785 */ 1786 1787 /** @addtogroup RCC_Clock_Configuration 1788 * @{ 1789 */ 1790 1791 /** 1792 * @brief Macro to configure the system clock source. 1793 * @param __SYSCLKSOURCE__ specifies the system clock source. 1794 * This parameter can be one of the following values: 1795 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1796 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1797 * @arg @ref RCC_SYSCLKSOURCE_HSIUSB48 HSIUSB48 oscillator is used as system clock source.(*) 1798 * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. 1799 * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. 1800 * @note (*) peripheral not available on all devices 1801 * @retval None 1802 */ 1803 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1804 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1805 1806 /** @brief Macro to get the clock source used as system clock. 1807 * @retval The clock source used as system clock. The returned value can be one 1808 * of the following: 1809 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 1810 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 1811 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSIUSB48 HSIUSB48 used as system clock.(*) 1812 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. 1813 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. 1814 * @note (*) peripheral not available on all devices 1815 */ 1816 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 1817 1818 /** 1819 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 1820 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 1821 * This parameter can be one of the following values: 1822 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 1823 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 1824 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 1825 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 1826 * @retval None 1827 */ 1828 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 1829 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, (uint32_t)(__LSEDRIVE__)) 1830 1831 /** @brief Macro to configure the MCO clock. 1832 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1833 * This parameter can be one of the following values: 1834 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 1835 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 1836 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 1837 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 1838 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 1839 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 1840 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 (*) 1841 * @param __MCODIV__ specifies the MCO clock prescaler. 1842 * This parameter can be one of the following values: 1843 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1844 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1845 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1846 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1847 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1848 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 1849 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 1850 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 1851 * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256 (*) 1852 * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512 (*) 1853 * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024 (*) 1854 * @note (*) not available on all devices 1855 * @retval None 1856 */ 1857 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1858 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1859 1860 /** @brief Macro to configure the MCO clock. 1861 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1862 * This parameter can be one of the following values: 1863 * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO output disabled 1864 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source 1865 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO source 1866 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO source 1867 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO source 1868 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO source 1869 * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48 (*) 1870 * @param __MCODIV__ specifies the MCO clock prescaler. 1871 * This parameter can be one of the following values: 1872 * @arg @ref RCC_MCO2DIV_1 MCO clock source is divided by 1 1873 * @arg @ref RCC_MCO2DIV_2 MCO clock source is divided by 2 1874 * @arg @ref RCC_MCO2DIV_4 MCO clock source is divided by 4 1875 * @arg @ref RCC_MCO2DIV_8 MCO clock source is divided by 8 1876 * @arg @ref RCC_MCO2DIV_16 MCO clock source is divided by 16 1877 * @arg @ref RCC_MCO2DIV_32 MCO clock source is divided by 32 1878 * @arg @ref RCC_MCO2DIV_64 MCO clock source is divided by 64 1879 * @arg @ref RCC_MCO2DIV_128 MCO clock source is divided by 128 1880 * @arg @ref RCC_MCO2DIV_256 MCO clock source is divided by 256 (*) 1881 * @arg @ref RCC_MCO2DIV_512 MCO clock source is divided by 512 (*) 1882 * @arg @ref RCC_MCO2DIV_1024 MCO clock source is divided by 1024 (*) 1883 * @note (*) not available on all devices 1884 * @retval None 1885 */ 1886 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1887 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1888 /** 1889 * @} 1890 */ 1891 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1892 * @brief macros to manage the specified RCC Flags and interrupts. 1893 * @{ 1894 */ 1895 1896 /** @brief Enable RCC interrupt. 1897 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1898 * This parameter can be any combination of the following values: 1899 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1900 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1901 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1902 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1903 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) 1904 * @note (*) peripheral not available on all devices 1905 * @retval None 1906 */ 1907 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 1908 1909 /** @brief Disable RCC interrupt. 1910 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1911 * This parameter can be any combination of the following values: 1912 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1913 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1914 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1915 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1916 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) 1917 * @note (*) peripheral not available on all devices 1918 * @retval None 1919 */ 1920 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 1921 1922 /** @brief Clear RCC interrupt pending bits. 1923 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1924 * This parameter can be any combination of the following values: 1925 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1926 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1927 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1928 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1929 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 1930 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 1931 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) 1932 * @retval None 1933 */ 1934 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 1935 1936 /** @brief Check whether the RCC interrupt has occurred or not. 1937 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1938 * This parameter can be one of the following values: 1939 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1940 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1941 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1942 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1943 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 1944 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 1945 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) 1946 * @note (*) peripheral not available on all devices 1947 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1948 */ 1949 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 1950 1951 /** @brief Set RMVF bit to clear the reset flags. 1952 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, 1953 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 1954 * @retval None 1955 */ 1956 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR2 |= RCC_CSR2_RMVF) 1957 1958 /** @brief Check whether the selected RCC flag is set or not. 1959 * @param __FLAG__ specifies the flag to check. 1960 * This parameter can be one of the following values: 1961 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 1962 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 1963 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 1964 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 1965 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 1966 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 (*) 1967 * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset 1968 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 1969 * @arg @ref RCC_FLAG_PINRST Pin reset 1970 * @arg @ref RCC_FLAG_SFTRST Software reset 1971 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 1972 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 1973 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 1974 * @note (*) peripheral not available on all devices 1975 * @retval The new state of __FLAG__ (TRUE or FALSE). 1976 */ 1977 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX) ? RCC->CR : \ 1978 ((((__FLAG__) >> 5U) == RCC_CSR1_REG_INDEX) ? RCC->CSR1 : \ 1979 ((((__FLAG__) >> 5U) == RCC_CSR2_REG_INDEX) ? RCC->CSR2 : RCC->CIFR))) & \ 1980 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 1981 ? 1U : 0U) 1982 1983 /** 1984 * @} 1985 */ 1986 1987 /** 1988 * @} 1989 */ 1990 1991 /* Include RCC HAL Extended module */ 1992 #include "stm32c0xx_hal_rcc_ex.h" 1993 1994 /* Exported functions --------------------------------------------------------*/ 1995 /** @addtogroup RCC_Exported_Functions 1996 * @{ 1997 */ 1998 1999 2000 /** @addtogroup RCC_Exported_Functions_Group1 2001 * @{ 2002 */ 2003 2004 /* Initialization and de-initialization functions ******************************/ 2005 HAL_StatusTypeDef HAL_RCC_DeInit(void); 2006 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); 2007 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 2008 2009 /** 2010 * @} 2011 */ 2012 2013 /** @addtogroup RCC_Exported_Functions_Group2 2014 * @{ 2015 */ 2016 2017 /* Peripheral Control functions ************************************************/ 2018 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 2019 void HAL_RCC_EnableCSS(void); 2020 void HAL_RCC_EnableLSECSS(void); 2021 void HAL_RCC_DisableLSECSS(void); 2022 uint32_t HAL_RCC_GetSysClockFreq(void); 2023 uint32_t HAL_RCC_GetHCLKFreq(void); 2024 uint32_t HAL_RCC_GetPCLK1Freq(void); 2025 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 2026 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, 2027 uint32_t *pFLatency); 2028 /* LSE & HSE CSS NMI IRQ handler */ 2029 void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ 2030 void HAL_RCC_CSSCallback(void); 2031 void HAL_RCC_LSECSSCallback(void); 2032 2033 /** 2034 * @} 2035 */ 2036 2037 /** 2038 * @} 2039 */ 2040 2041 /** 2042 * @} 2043 */ 2044 2045 /** 2046 * @} 2047 */ 2048 2049 #ifdef __cplusplus 2050 } 2051 #endif 2052 2053 #endif /* STM32C0xx_HAL_RCC_H */ 2054
