1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32H5xx_HAL_RCC_EX_H 22 #define __STM32H5xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PLL2 Clock structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. 50 This parameter must be a value of @ref RCC_PLL2_Clock_Source */ 51 52 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 53 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 54 55 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 56 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 57 58 uint32_t PLL2P; /*!< PLL2P: Division factor for peripheral clock. 59 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 60 61 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 62 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 63 64 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 66 odd division factors are not allowed */ 67 68 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 69 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 70 71 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 72 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 73 74 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 75 PLL2 VCO It should be a value between 0 and 8191 */ 76 77 uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. 78 This parameter must be a value or a combination of @ref RCC_PLL2_Clock_Output */ 79 } RCC_PLL2InitTypeDef; 80 81 82 #if defined(RCC_CR_PLL3ON) 83 /** 84 * @brief PLL3 Clock structure definition 85 */ 86 typedef struct 87 { 88 uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. 89 This parameter must be a value of @ref RCC_PLL3_Clock_Source */ 90 91 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 92 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 93 94 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 95 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 96 97 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 98 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 99 100 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 101 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 102 103 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 104 This parameter must be a number between Min_Data = 1 and Max_Data = 128 105 odd division factors are not allowed */ 106 107 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 108 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 109 110 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 111 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 112 113 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 114 PLL3 VCO It should be a value between 0 and 8191 */ 115 116 uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. 117 This parameter must be a value or a combination of @ref RCC_PLL3_Clock_Output */ 118 } RCC_PLL3InitTypeDef; 119 #endif /* RCC_CR_PLL3ON */ 120 121 /** 122 * @brief RCC PLL1 Clocks structure definition 123 */ 124 typedef struct 125 { 126 uint32_t PLL1_P_Frequency; 127 uint32_t PLL1_Q_Frequency; 128 uint32_t PLL1_R_Frequency; 129 } PLL1_ClocksTypeDef; 130 131 /** 132 * @brief RCC PLL2 Clocks structure definition 133 */ 134 typedef struct 135 { 136 uint32_t PLL2_P_Frequency; 137 uint32_t PLL2_Q_Frequency; 138 uint32_t PLL2_R_Frequency; 139 } PLL2_ClocksTypeDef; 140 141 #if defined(RCC_CR_PLL3ON) 142 /** 143 * @brief RCC PLL3 Clocks structure definition 144 */ 145 typedef struct 146 { 147 uint32_t PLL3_P_Frequency; 148 uint32_t PLL3_Q_Frequency; 149 uint32_t PLL3_R_Frequency; 150 } PLL3_ClocksTypeDef; 151 #endif /* RCC_CR_PLL3ON */ 152 153 154 /** 155 * @brief RCC extended clocks structure definition 156 */ 157 typedef struct 158 { 159 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 160 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 161 162 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 163 This parameter will be used only when PLL2 is selected as kernel clock Source 164 for some peripherals */ 165 166 #if defined(RCC_CR_PLL3ON) 167 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 168 This parameter will be used only when PLL2 is selected as kernel clock Source 169 for some peripherals */ 170 #endif /* RCC_CR_PLL3ON */ 171 172 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 173 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 174 175 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 176 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 177 178 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 179 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 180 181 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 182 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 183 184 #if defined(UART4) 185 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 186 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 187 #endif /* UART4 */ 188 189 #if defined(UART5) 190 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 191 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 192 #endif /* UART5 */ 193 194 #if defined(USART6) 195 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. 196 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 197 #endif /* USART6 */ 198 199 #if defined(UART7) 200 uint32_t Uart7ClockSelection; /*!< Specifies UART7 clock source. 201 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ 202 #endif /* UART7 */ 203 204 #if defined(UART8) 205 uint32_t Uart8ClockSelection; /*!< Specifies UART8 clock source. 206 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ 207 #endif /* UART8 */ 208 209 #if defined(UART9) 210 uint32_t Uart9ClockSelection; /*!< Specifies UART9 clock source. 211 This parameter can be a value of @ref RCCEx_UART9_Clock_Source */ 212 #endif /* UART9 */ 213 214 #if defined(USART10) 215 uint32_t Usart10ClockSelection; /*!< Specifies USART10 clock source. 216 This parameter can be a value of @ref RCCEx_USART10_Clock_Source */ 217 #endif /* USART10 */ 218 219 #if defined(USART11) 220 uint32_t Usart11ClockSelection; /*!< Specifies USART11 clock source. 221 This parameter can be a value of @ref RCCEx_USART11_Clock_Source */ 222 #endif /* USART11 */ 223 224 #if defined(UART12) 225 uint32_t Uart12ClockSelection; /*!< Specifies UART12 clock source. 226 This parameter can be a value of @ref RCCEx_UART12_Clock_Source */ 227 #endif /* UART12 */ 228 229 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 230 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 231 232 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 233 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 234 235 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 236 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 237 238 #if defined(I2C3) 239 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 240 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 241 #endif /* I2C3 */ 242 243 #if defined(I2C4) 244 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 245 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 246 #endif /* I2C4 */ 247 248 uint32_t I3c1ClockSelection; /*!< Specifies I3C1 clock source. 249 This parameter can be a value of @ref RCCEx_I3C1_Clock_Source */ 250 251 #if defined(I3C2) 252 uint32_t I3c2ClockSelection; /*!< Specifies I3C2 clock source. 253 This parameter can be a value of @ref RCCEx_I3C2_Clock_Source */ 254 #endif /* I3C2*/ 255 256 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 257 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 258 259 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 260 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 261 262 #if defined(LPTIM3) 263 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 264 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 265 #endif /* LPTIM3 */ 266 267 #if defined(LPTIM4) 268 uint32_t Lptim4ClockSelection; /*!< Specifies LPTIM4 clock source. 269 This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source */ 270 #endif /* LPTIM4 */ 271 272 #if defined(LPTIM5) 273 uint32_t Lptim5ClockSelection; /*!< Specifies LPTIM5 clock source. 274 This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source */ 275 #endif /* LPTIM5 */ 276 277 #if defined(LPTIM6) 278 uint32_t Lptim6ClockSelection; /*!< Specifies LPTIM6 clock source. 279 This parameter can be a value of @ref RCCEx_LPTIM6_Clock_Source */ 280 #endif /* LPTIM6 */ 281 282 #if defined(FDCAN2) 283 uint32_t Fdcan12ClockSelection; /*!< Specifies FDCAN12 kernel clock source. 284 This parameter can be a value of @ref RCCEx_FDCAN12_Clock_Source */ 285 #else 286 uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 kernel clock source. 287 This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ 288 #endif /* FDCAN2*/ 289 290 #if defined(SAI1) 291 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 292 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 293 #endif /* SAI1*/ 294 295 #if defined(SAI2) 296 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 297 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 298 #endif /* SAI2*/ 299 300 uint32_t RngClockSelection; /*!< Specifies RNG clock source. 301 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 302 303 #if defined(SDMMC1) 304 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source. 305 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 306 #endif /* SDMMC1 */ 307 308 #if defined(SDMMC2) 309 uint32_t Sdmmc2ClockSelection; /*!< Specifies SDMMC2 clock source. 310 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ 311 #endif /* SDMMC2 */ 312 313 uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC2 and DAC interface clock source. 314 This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ 315 316 uint32_t DacLowPowerClockSelection; /*!< Specifies DAC low-power clock source used in Sample and hold mode. 317 This parameter can be a value of @ref RCCEx_DAC_Low_Power_Clock_Source */ 318 319 #if defined(OCTOSPI1) 320 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 321 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 322 #endif /* OCTOSPI1 */ 323 324 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source. 325 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 326 327 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source. 328 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 329 330 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source. 331 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 332 333 #if defined(SPI4) 334 uint32_t Spi4ClockSelection; /*!< Specifies SPI4 clock source. 335 This parameter can be a value of @ref RCCEx_SPI4_Clock_Source */ 336 #endif /* SPI4 */ 337 338 #if defined(SPI5) 339 uint32_t Spi5ClockSelection; /*!< Specifies SPI5 clock source. 340 This parameter can be a value of @ref RCCEx_SPI5_Clock_Source */ 341 #endif /* SPI5 */ 342 343 #if defined(SPI6) 344 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source. 345 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 346 #endif /* SPI6 */ 347 348 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 349 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 350 351 #if defined(CEC) 352 uint32_t CecClockSelection; /*!< Specifies CEC clock source. 353 This parameter can be a value of @ref RCC_CEC_Clock_Source */ 354 #endif /* CEC */ 355 356 uint32_t UsbClockSelection; /*!< Specifies USB clock source. 357 This parameter can be a value of @ref RCC_USB_Clock_Source */ 358 359 uint32_t TimPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 360 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 361 362 } RCC_PeriphCLKInitTypeDef; 363 364 #if defined(CRS) 365 366 /** 367 * @brief RCC_CRS Init structure definition 368 */ 369 typedef struct 370 { 371 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 372 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 373 374 uint32_t Source; /*!< Specifies the SYNC signal source. 375 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 376 377 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 378 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 379 380 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 381 event. It can be calculated in using macro 382 __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 383 This parameter must be a number between 0 and 0xFFFF or a value of 384 @ref RCCEx_CRS_ReloadValueDefault .*/ 385 386 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 387 This parameter must be a number between 0 and 0xFF or a value of 388 @ref RCCEx_CRS_ErrorLimitDefault */ 389 390 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 391 This parameter must be a number between 0 and 0x7F or a value of 392 @ref RCCEx_CRS_HSI48CalibrationDefault */ 393 394 } RCC_CRSInitTypeDef; 395 396 /** 397 * @brief RCC_CRS Synchronization structure definition 398 */ 399 typedef struct 400 { 401 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 402 This parameter must be a number between 0 and 0xFFFF */ 403 404 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 405 This parameter must be a number between 0 and 0x3F */ 406 407 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 408 value latched in the time of the last SYNC event. 409 This parameter must be a number between 0 and 0xFFFF */ 410 411 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 412 frequency error counter latched in the time of the last SYNC event. 413 It shows whether the actual frequency is below or above the target. 414 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection */ 415 416 } RCC_CRSSynchroInfoTypeDef; 417 418 #endif /* CRS */ 419 /** 420 * @} 421 */ 422 423 424 /* Exported constants --------------------------------------------------------*/ 425 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 426 * @{ 427 */ 428 429 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Microcontroller Clock Output Source 430 * @{ 431 */ 432 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed microcontroller clock output */ 433 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed microcontroller clock output */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 439 * @{ 440 */ 441 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) 442 #define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) 443 #define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) 444 #if defined(UART4) 445 #define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) 446 #endif /* UART4 */ 447 #if defined(UART5) 448 #define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) 449 #endif /* UART5 */ 450 #if defined(USART6) 451 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x00000020U) 452 #endif /* USART6 */ 453 #if defined(UART7) 454 #define RCC_PERIPHCLK_UART7 ((uint64_t)0x00000040U) 455 #endif /* UART7 */ 456 #if defined(UART8) 457 #define RCC_PERIPHCLK_UART8 ((uint64_t)0x00000080U) 458 #endif /* UART8 */ 459 #if defined(UART9) 460 #define RCC_PERIPHCLK_UART9 ((uint64_t)0x00000100U) 461 #endif /* UART9 */ 462 #if defined(USART10) 463 #define RCC_PERIPHCLK_USART10 ((uint64_t)0x00000200U) 464 #endif /* USART10 */ 465 #if defined(USART11) 466 #define RCC_PERIPHCLK_USART11 ((uint64_t)0x00000400U) 467 #endif /* USART11 */ 468 #if defined(UART12) 469 #define RCC_PERIPHCLK_UART12 ((uint64_t)0x00000800U) 470 #endif /* UART12 */ 471 #define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00001000U) 472 #define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00002000U) 473 #define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00004000U) 474 #if defined(I2C3) 475 #define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00008000U) 476 #endif /* I2C3 */ 477 #define RCC_PERIPHCLK_I3C1 ((uint64_t)0x00010000U) 478 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00020000U) 479 #define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00040000U) 480 #if defined(SAI1) 481 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00080000U) 482 #endif /* SAI1 */ 483 #if defined(SAI2) 484 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00100000U) 485 #endif /* SAI2 */ 486 #define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00200000U) 487 #define RCC_PERIPHCLK_ADC1 RCC_PERIPHCLK_ADCDAC 488 #define RCC_PERIPHCLK_ADC2 RCC_PERIPHCLK_ADCDAC 489 #define RCC_PERIPHCLK_DAC RCC_PERIPHCLK_ADCDAC 490 #if defined(SDMMC1) 491 #define RCC_PERIPHCLK_SDMMC1 ((uint64_t)0x00400000U) 492 #endif /* SDMMC1 */ 493 #if defined(SDMMC2) 494 #define RCC_PERIPHCLK_SDMMC2 ((uint64_t)0x00800000U) 495 #endif /* SDMMC2 */ 496 #define RCC_PERIPHCLK_CKPER ((uint64_t)0x01000000U) 497 #define RCC_PERIPHCLK_RTC ((uint64_t)0x02000000U) 498 #define RCC_PERIPHCLK_RNG ((uint64_t)0x04000000U) 499 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x08000000U) 500 #define RCC_PERIPHCLK_SPI2 ((uint64_t)0x10000000U) 501 #define RCC_PERIPHCLK_SPI3 ((uint64_t)0x20000000U) 502 #if defined(SPI4) 503 #define RCC_PERIPHCLK_SPI4 ((uint64_t)0x40000000U) 504 #endif /* SPI4 */ 505 #if defined(SPI5) 506 #define RCC_PERIPHCLK_SPI5 ((uint64_t)0x80000000U) 507 #endif /* SPI5 */ 508 #if defined(SPI6) 509 #define RCC_PERIPHCLK_SPI6 ((uint64_t)0x100000000U) 510 #endif /* SPI6 */ 511 #if defined(OCTOSPI1) 512 #define RCC_PERIPHCLK_OSPI ((uint64_t)0x200000000U) 513 #endif /* OCTOSPI1 */ 514 #if defined(FDCAN2) 515 #define RCC_PERIPHCLK_FDCAN12 ((uint64_t)0x400000000U) 516 #else 517 #define RCC_PERIPHCLK_FDCAN1 ((uint64_t)0x400000000U) 518 #endif /* FDCAN2*/ 519 #if defined(CEC) 520 #define RCC_PERIPHCLK_CEC ((uint64_t)0x800000000U) 521 #endif /* CEC */ 522 #define RCC_PERIPHCLK_USB ((uint64_t)0x1000000000U) 523 #if defined(LPTIM3) 524 #define RCC_PERIPHCLK_LPTIM3 ((uint64_t)0x2000000000U) 525 #endif /* LPTIM3 */ 526 #if defined(LPTIM4) 527 #define RCC_PERIPHCLK_LPTIM4 ((uint64_t)0x4000000000U) 528 #endif /* LPTIM4 */ 529 #if defined(LPTIM5) 530 #define RCC_PERIPHCLK_LPTIM5 ((uint64_t)0x8000000000U) 531 #endif /* LPTIM5 */ 532 #if defined(LPTIM6) 533 #define RCC_PERIPHCLK_LPTIM6 ((uint64_t)0x10000000000U) 534 #endif /* LPTIM6 */ 535 #define RCC_PERIPHCLK_DAC_LP ((uint64_t)0x20000000000U) 536 #if defined(I2C4) 537 #define RCC_PERIPHCLK_I2C4 ((uint64_t)0x40000000000U) 538 #endif /* I2C4 */ 539 #define RCC_PERIPHCLK_TIM ((uint64_t)0x80000000000U) 540 #if defined(I3C2) 541 #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) 542 #endif /* I3C2 */ 543 544 /** 545 * @} 546 */ 547 548 549 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 550 * @{ 551 */ 552 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN 553 #define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN 554 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN 555 /** 556 * @} 557 */ 558 559 #if defined(RCC_CR_PLL3ON) 560 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 561 * @{ 562 */ 563 #define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN 564 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN 565 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN 566 /** 567 * @} 568 */ 569 #endif /* RCC_CR_PLL3ON */ 570 571 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 572 * @{ 573 */ 574 #define RCC_PLL2_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 575 #define RCC_PLL2_VCIRANGE_1 RCC_PLL2CFGR_PLL2RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 576 #define RCC_PLL2_VCIRANGE_2 RCC_PLL2CFGR_PLL2RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 577 #define RCC_PLL2_VCIRANGE_3 (RCC_PLL2CFGR_PLL2RGE_0 | RCC_PLL2CFGR_PLL2RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 578 /** 579 * @} 580 */ 581 582 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 583 * @{ 584 */ 585 #define RCC_PLL2_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 586 #define RCC_PLL2_VCORANGE_MEDIUM RCC_PLL2CFGR_PLL2VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 587 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCC_PLL2_Clock_Source RCC PLL2 Clock Source 593 * @{ 594 */ 595 #define RCC_PLL2_SOURCE_NONE (0x00000000U) 596 #define RCC_PLL2_SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 597 #define RCC_PLL2_SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 598 #define RCC_PLL2_SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) 599 /** 600 * @} 601 */ 602 603 #if defined(RCC_CR_PLL3ON) 604 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 605 * @{ 606 */ 607 #define RCC_PLL3_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 608 #define RCC_PLL3_VCIRANGE_1 RCC_PLL3CFGR_PLL3RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 609 #define RCC_PLL3_VCIRANGE_2 RCC_PLL3CFGR_PLL3RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 610 #define RCC_PLL3_VCIRANGE_3 (RCC_PLL3CFGR_PLL3RGE_0 | RCC_PLL3CFGR_PLL3RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 616 * @{ 617 */ 618 #define RCC_PLL3_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 619 #define RCC_PLL3_VCORANGE_MEDIUM RCC_PLL3CFGR_PLL3VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_PLL3_Clock_Source RCC PLL3 Clock Source 625 * @{ 626 */ 627 #define RCC_PLL3_SOURCE_NONE (0x00000000U) 628 #define RCC_PLL3_SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 629 #define RCC_PLL3_SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 630 #define RCC_PLL3_SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) 631 /** 632 * @} 633 */ 634 #endif /* RCC_CR_PLL3ON */ 635 636 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 637 * @{ 638 */ 639 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 640 #define RCC_USART1CLKSOURCE_PLL2Q RCC_CCIPR1_USART1SEL_0 641 #if defined(RCC_CR_PLL3ON) 642 #define RCC_USART1CLKSOURCE_PLL3Q RCC_CCIPR1_USART1SEL_1 643 #endif /* RCC_CR_PLL3ON */ 644 #define RCC_USART1CLKSOURCE_HSI (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 645 #define RCC_USART1CLKSOURCE_CSI RCC_CCIPR1_USART1SEL_2 646 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_2) 647 /** 648 * @} 649 */ 650 651 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 652 * @{ 653 */ 654 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 655 #define RCC_USART2CLKSOURCE_PLL2Q RCC_CCIPR1_USART2SEL_0 656 #if defined(RCC_CR_PLL3ON) 657 #define RCC_USART2CLKSOURCE_PLL3Q RCC_CCIPR1_USART2SEL_1 658 #endif /* RCC_CR_PLL3ON */ 659 #define RCC_USART2CLKSOURCE_HSI (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 660 #define RCC_USART2CLKSOURCE_CSI RCC_CCIPR1_USART2SEL_2 661 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_2) 662 /** 663 * @} 664 */ 665 666 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 667 * @{ 668 */ 669 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 670 #define RCC_USART3CLKSOURCE_PLL2Q RCC_CCIPR1_USART3SEL_0 671 #if defined(RCC_CR_PLL3ON) 672 #define RCC_USART3CLKSOURCE_PLL3Q RCC_CCIPR1_USART3SEL_1 673 #endif /* RCC_CR_PLL3ON */ 674 #define RCC_USART3CLKSOURCE_HSI (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) 675 #define RCC_USART3CLKSOURCE_CSI RCC_CCIPR1_USART3SEL_2 676 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_2) 677 /** 678 * @} 679 */ 680 681 #if defined(UART4) 682 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 683 * @{ 684 */ 685 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 686 #define RCC_UART4CLKSOURCE_PLL2Q RCC_CCIPR1_UART4SEL_0 687 #define RCC_UART4CLKSOURCE_PLL3Q RCC_CCIPR1_UART4SEL_1 688 #define RCC_UART4CLKSOURCE_HSI (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) 689 #define RCC_UART4CLKSOURCE_CSI RCC_CCIPR1_UART4SEL_2 690 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_2) 691 /** 692 * @} 693 */ 694 #endif /* UART4 */ 695 696 #if defined(UART5) 697 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 698 * @{ 699 */ 700 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 701 #define RCC_UART5CLKSOURCE_PLL2Q RCC_CCIPR1_UART5SEL_0 702 #define RCC_UART5CLKSOURCE_PLL3Q RCC_CCIPR1_UART5SEL_1 703 #define RCC_UART5CLKSOURCE_HSI (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) 704 #define RCC_UART5CLKSOURCE_CSI RCC_CCIPR1_UART5SEL_2 705 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_2) 706 /** 707 * @} 708 */ 709 #endif /* UART5 */ 710 711 #if defined(USART6) 712 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 713 * @{ 714 */ 715 #define RCC_USART6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 716 #define RCC_USART6CLKSOURCE_PLL2Q RCC_CCIPR1_USART6SEL_0 717 #define RCC_USART6CLKSOURCE_PLL3Q RCC_CCIPR1_USART6SEL_1 718 #define RCC_USART6CLKSOURCE_HSI (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_1) 719 #define RCC_USART6CLKSOURCE_CSI RCC_CCIPR1_USART6SEL_2 720 #define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_2) 721 /** 722 * @} 723 */ 724 #endif /* USART6 */ 725 726 #if defined(UART7) 727 /** @defgroup RCCEx_UART7_Clock_Source UART7 Clock Source 728 * @{ 729 */ 730 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 731 #define RCC_UART7CLKSOURCE_PLL2Q RCC_CCIPR1_UART7SEL_0 732 #define RCC_UART7CLKSOURCE_PLL3Q RCC_CCIPR1_UART7SEL_1 733 #define RCC_UART7CLKSOURCE_HSI (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_1) 734 #define RCC_UART7CLKSOURCE_CSI RCC_CCIPR1_UART7SEL_2 735 #define RCC_UART7CLKSOURCE_LSE (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_2) 736 /** 737 * @} 738 */ 739 #endif /* UART7 */ 740 741 #if defined(UART8) 742 /** @defgroup RCCEx_UART8_Clock_Source UART8 Clock Source 743 * @{ 744 */ 745 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 746 #define RCC_UART8CLKSOURCE_PLL2Q RCC_CCIPR1_UART8SEL_0 747 #define RCC_UART8CLKSOURCE_PLL3Q RCC_CCIPR1_UART8SEL_1 748 #define RCC_UART8CLKSOURCE_HSI (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_1) 749 #define RCC_UART8CLKSOURCE_CSI RCC_CCIPR1_UART8SEL_2 750 #define RCC_UART8CLKSOURCE_LSE (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_2) 751 /** 752 * @} 753 */ 754 #endif /* UART8 */ 755 756 #if defined(UART9) 757 /** @defgroup RCCEx_UART9_Clock_Source UART9 Clock Source 758 * @{ 759 */ 760 #define RCC_UART9CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 761 #define RCC_UART9CLKSOURCE_PLL2Q RCC_CCIPR1_UART9SEL_0 762 #define RCC_UART9CLKSOURCE_PLL3Q RCC_CCIPR1_UART9SEL_1 763 #define RCC_UART9CLKSOURCE_HSI (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_1) 764 #define RCC_UART9CLKSOURCE_CSI RCC_CCIPR1_UART9SEL_2 765 #define RCC_UART9CLKSOURCE_LSE (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_2) 766 /** 767 * @} 768 */ 769 #endif /* UART9 */ 770 771 #if defined(USART10) 772 /** @defgroup RCCEx_USART10_Clock_Source USART10 Clock Source 773 * @{ 774 */ 775 #define RCC_USART10CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 776 #define RCC_USART10CLKSOURCE_PLL2Q RCC_CCIPR1_USART10SEL_0 777 #define RCC_USART10CLKSOURCE_PLL3Q RCC_CCIPR1_USART10SEL_1 778 #define RCC_USART10CLKSOURCE_HSI (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_1) 779 #define RCC_USART10CLKSOURCE_CSI RCC_CCIPR1_USART10SEL_2 780 #define RCC_USART10CLKSOURCE_LSE (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_2) 781 /** 782 * @} 783 */ 784 #endif /* USART10 */ 785 786 #if defined(USART11) 787 /** @defgroup RCCEx_USART11_Clock_Source USART11 Clock Source 788 * @{ 789 */ 790 #define RCC_USART11CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 791 #define RCC_USART11CLKSOURCE_PLL2Q RCC_CCIPR2_USART11SEL_0 792 #define RCC_USART11CLKSOURCE_PLL3Q RCC_CCIPR2_USART11SEL_1 793 #define RCC_USART11CLKSOURCE_HSI (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_1) 794 #define RCC_USART11CLKSOURCE_CSI RCC_CCIPR2_USART11SEL_2 795 #define RCC_USART11CLKSOURCE_LSE (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_2) 796 /** 797 * @} 798 */ 799 #endif /* USART11 */ 800 801 #if defined(UART12) 802 /** @defgroup RCCEx_UART12_Clock_Source UART12 Clock Source 803 * @{ 804 */ 805 #define RCC_UART12CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 806 #define RCC_UART12CLKSOURCE_PLL2Q RCC_CCIPR2_UART12SEL_0 807 #define RCC_UART12CLKSOURCE_PLL3Q RCC_CCIPR2_UART12SEL_1 808 #define RCC_UART12CLKSOURCE_HSI (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_1) 809 #define RCC_UART12CLKSOURCE_CSI RCC_CCIPR2_UART12SEL_2 810 #define RCC_UART12CLKSOURCE_LSE (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_2) 811 /** 812 * @} 813 */ 814 #endif /* UART12 */ 815 816 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 817 * @{ 818 */ 819 #define RCC_LPUART1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 820 #define RCC_LPUART1CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 821 #if defined(RCC_CR_PLL3ON) 822 #define RCC_LPUART1CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 823 #endif /* RCC_CR_PLL3ON */ 824 #define RCC_LPUART1CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 825 #define RCC_LPUART1CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 826 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) 827 828 /** 829 * @} 830 */ 831 832 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 833 * @{ 834 */ 835 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 836 #if defined(RCC_CR_PLL3ON) 837 #define RCC_I2C1CLKSOURCE_PLL3R RCC_CCIPR4_I2C1SEL_0 838 #else 839 #define RCC_I2C1CLKSOURCE_PLL2R RCC_CCIPR4_I2C1SEL_0 840 #endif /* RCC_CR_PLL3ON */ 841 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR4_I2C1SEL_1 842 #define RCC_I2C1CLKSOURCE_CSI (RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0) 843 /** 844 * @} 845 */ 846 847 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 848 * @{ 849 */ 850 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 851 #if defined(RCC_CR_PLL3ON) 852 #define RCC_I2C2CLKSOURCE_PLL3R RCC_CCIPR4_I2C2SEL_0 853 #else 854 #define RCC_I2C2CLKSOURCE_PLL2R RCC_CCIPR4_I2C2SEL_0 855 #endif /* RCC_CR_PLL3ON */ 856 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR4_I2C2SEL_1 857 #define RCC_I2C2CLKSOURCE_CSI (RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0) 858 /** 859 * @} 860 */ 861 862 #if defined(I2C3) 863 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 864 * @{ 865 */ 866 #define RCC_I2C3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 867 #define RCC_I2C3CLKSOURCE_PLL3R RCC_CCIPR4_I2C3SEL_0 868 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR4_I2C3SEL_1 869 #define RCC_I2C3CLKSOURCE_CSI (RCC_CCIPR4_I2C3SEL_0 | RCC_CCIPR4_I2C3SEL_1) 870 /** 871 * @} 872 */ 873 #endif /* I2C3 */ 874 875 #if defined(I2C4) 876 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 877 * @{ 878 */ 879 #define RCC_I2C4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 880 #define RCC_I2C4CLKSOURCE_PLL3R RCC_CCIPR4_I2C4SEL_0 881 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR4_I2C4SEL_1 882 #define RCC_I2C4CLKSOURCE_CSI (RCC_CCIPR4_I2C4SEL_0 | RCC_CCIPR4_I2C4SEL_1) 883 /** 884 * @} 885 */ 886 #endif /* I2C4 */ 887 888 /** @defgroup RCCEx_I3C1_Clock_Source I3C1 Clock Source 889 * @{ 890 */ 891 #define RCC_I3C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 892 #if defined(RCC_CR_PLL3ON) 893 #define RCC_I3C1CLKSOURCE_PLL3R RCC_CCIPR4_I3C1SEL_0 894 #else 895 #define RCC_I3C1CLKSOURCE_PLL2R RCC_CCIPR4_I3C1SEL_0 896 #endif /* RCC_CR_PLL3ON */ 897 #define RCC_I3C1CLKSOURCE_HSI RCC_CCIPR4_I3C1SEL_1 898 /** 899 * @} 900 */ 901 902 #if defined(I3C2) 903 /** @defgroup RCCEx_I3C2_Clock_Source I3C2 Clock Source 904 * @{ 905 */ 906 #define RCC_I3C2CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 907 #define RCC_I3C2CLKSOURCE_PLL2R RCC_CCIPR4_I3C2SEL_0 908 #define RCC_I3C2CLKSOURCE_HSI RCC_CCIPR4_I3C2SEL_1 909 /** 910 * @} 911 */ 912 #endif /* I3C2 */ 913 914 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 915 * @{ 916 */ 917 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) 918 #define RCC_RNGCLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 919 #define RCC_RNGCLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 920 #define RCC_RNGCLKSOURCE_LSI (RCC_CCIPR5_RNGSEL_0 | RCC_CCIPR5_RNGSEL_1) 921 /** 922 * @} 923 */ 924 925 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 926 * @{ 927 */ 928 #define RCC_SPI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 929 #define RCC_SPI1CLKSOURCE_PLL2P RCC_CCIPR3_SPI1SEL_0 930 #if defined(RCC_CR_PLL3ON) 931 #define RCC_SPI1CLKSOURCE_PLL3P RCC_CCIPR3_SPI1SEL_1 932 #endif /* RCC_CR_PLL3ON */ 933 #define RCC_SPI1CLKSOURCE_PIN (RCC_CCIPR3_SPI1SEL_0 | RCC_CCIPR3_SPI1SEL_1) 934 #define RCC_SPI1CLKSOURCE_CLKP RCC_CCIPR3_SPI1SEL_2 935 /** 936 * @} 937 */ 938 939 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 940 * @{ 941 */ 942 #define RCC_SPI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 943 #define RCC_SPI2CLKSOURCE_PLL2P RCC_CCIPR3_SPI2SEL_0 944 #if defined(RCC_CR_PLL3ON) 945 #define RCC_SPI2CLKSOURCE_PLL3P RCC_CCIPR3_SPI2SEL_1 946 #endif /* RCC_CR_PLL3ON */ 947 #define RCC_SPI2CLKSOURCE_PIN (RCC_CCIPR3_SPI2SEL_0 | RCC_CCIPR3_SPI2SEL_1) 948 #define RCC_SPI2CLKSOURCE_CLKP RCC_CCIPR3_SPI2SEL_2 949 /** 950 * @} 951 */ 952 953 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 954 * @{ 955 */ 956 #define RCC_SPI3CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 957 #define RCC_SPI3CLKSOURCE_PLL2P RCC_CCIPR3_SPI3SEL_0 958 #if defined(RCC_CR_PLL3ON) 959 #define RCC_SPI3CLKSOURCE_PLL3P RCC_CCIPR3_SPI3SEL_1 960 #endif /* RCC_CR_PLL3ON */ 961 #define RCC_SPI3CLKSOURCE_PIN (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) 962 #define RCC_SPI3CLKSOURCE_CLKP RCC_CCIPR3_SPI3SEL_2 963 /** 964 * @} 965 */ 966 967 #if defined(SPI4) 968 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 969 * @{ 970 */ 971 #define RCC_SPI4CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 972 #define RCC_SPI4CLKSOURCE_PLL2Q RCC_CCIPR3_SPI4SEL_0 973 #define RCC_SPI4CLKSOURCE_PLL3Q RCC_CCIPR3_SPI4SEL_1 974 #define RCC_SPI4CLKSOURCE_HSI (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_1) 975 #define RCC_SPI4CLKSOURCE_CSI RCC_CCIPR3_SPI4SEL_2 976 #define RCC_SPI4CLKSOURCE_HSE (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_2) 977 /** 978 * @} 979 */ 980 #endif /* SPI4 */ 981 982 #if defined(SPI5) 983 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 984 * @{ 985 */ 986 #define RCC_SPI5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 987 #define RCC_SPI5CLKSOURCE_PLL2Q RCC_CCIPR3_SPI5SEL_0 988 #define RCC_SPI5CLKSOURCE_PLL3Q RCC_CCIPR3_SPI5SEL_1 989 #define RCC_SPI5CLKSOURCE_HSI (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_1) 990 #define RCC_SPI5CLKSOURCE_CSI RCC_CCIPR3_SPI5SEL_2 991 #define RCC_SPI5CLKSOURCE_HSE (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_2) 992 /** 993 * @} 994 */ 995 #endif /* SPI5 */ 996 997 #if defined(SPI6) 998 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 999 * @{ 1000 */ 1001 #define RCC_SPI6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 1002 #define RCC_SPI6CLKSOURCE_PLL2Q RCC_CCIPR3_SPI6SEL_0 1003 #define RCC_SPI6CLKSOURCE_PLL3Q RCC_CCIPR3_SPI6SEL_1 1004 #define RCC_SPI6CLKSOURCE_HSI (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_1) 1005 #define RCC_SPI6CLKSOURCE_CSI RCC_CCIPR3_SPI6SEL_2 1006 #define RCC_SPI6CLKSOURCE_HSE (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_2) 1007 /** 1008 * @} 1009 */ 1010 #endif /* SPI6 */ 1011 1012 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 1013 * @{ 1014 */ 1015 #define RCC_LPTIM1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1016 #define RCC_LPTIM1CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM1SEL_0 1017 #if defined(RCC_CR_PLL3ON) 1018 #define RCC_LPTIM1CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM1SEL_1 1019 #endif /* RCC_CR_PLL3ON */ 1020 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) 1021 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL_2 1022 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) 1023 /** 1024 * @} 1025 */ 1026 1027 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 1028 * @{ 1029 */ 1030 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 1031 #define RCC_LPTIM2CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM2SEL_0 1032 #if defined(RCC_CR_PLL3ON) 1033 #define RCC_LPTIM2CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM2SEL_1 1034 #endif /* RCC_CR_PLL3ON */ 1035 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) 1036 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR2_LPTIM2SEL_2 1037 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) 1038 /** 1039 * @} 1040 */ 1041 1042 #if defined(LPTIM3) 1043 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 1044 * @{ 1045 */ 1046 #define RCC_LPTIM3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1047 #define RCC_LPTIM3CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM3SEL_0 1048 #define RCC_LPTIM3CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM3SEL_1 1049 #define RCC_LPTIM3CLKSOURCE_LSE (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) 1050 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR2_LPTIM3SEL_2 1051 #define RCC_LPTIM3CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) 1052 /** 1053 * @} 1054 */ 1055 #endif /* LPTIM3 */ 1056 1057 #if defined(LPTIM4) 1058 /** @defgroup RCCEx_LPTIM4_Clock_Source LPTIM4 Clock Source 1059 * @{ 1060 */ 1061 #define RCC_LPTIM4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1062 #define RCC_LPTIM4CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM4SEL_0 1063 #define RCC_LPTIM4CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM4SEL_1 1064 #define RCC_LPTIM4CLKSOURCE_LSE (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) 1065 #define RCC_LPTIM4CLKSOURCE_LSI RCC_CCIPR2_LPTIM4SEL_2 1066 #define RCC_LPTIM4CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) 1067 /** 1068 * @} 1069 */ 1070 #endif /* LPTIM4 */ 1071 1072 #if defined(LPTIM5) 1073 /** @defgroup RCCEx_LPTIM5_Clock_Source LPTIM5 Clock Source 1074 * @{ 1075 */ 1076 #define RCC_LPTIM5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1077 #define RCC_LPTIM5CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM5SEL_0 1078 #define RCC_LPTIM5CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM5SEL_1 1079 #define RCC_LPTIM5CLKSOURCE_LSE (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) 1080 #define RCC_LPTIM5CLKSOURCE_LSI RCC_CCIPR2_LPTIM5SEL_2 1081 #define RCC_LPTIM5CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) 1082 /** 1083 * @} 1084 */ 1085 #endif /* LPTIM5 */ 1086 1087 #if defined(LPTIM6) 1088 /** @defgroup RCCEx_LPTIM6_Clock_Source LPTIM6 Clock Source 1089 * @{ 1090 */ 1091 #define RCC_LPTIM6CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1092 #define RCC_LPTIM6CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM6SEL_0 1093 #define RCC_LPTIM6CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM6SEL_1 1094 #define RCC_LPTIM6CLKSOURCE_LSE (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) 1095 #define RCC_LPTIM6CLKSOURCE_LSI RCC_CCIPR2_LPTIM6SEL_2 1096 #define RCC_LPTIM6CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) 1097 /** 1098 * @} 1099 */ 1100 #endif /* LPTIM6 */ 1101 1102 #if defined(FDCAN2) 1103 /** @defgroup RCCEx_FDCAN12_Clock_Source FDCAN12 Kernel Clock Source 1104 * @{ 1105 */ 1106 #define RCC_FDCAN12CLKSOURCE_HSE ((uint32_t)0x00000000U) 1107 #define RCC_FDCAN12CLKSOURCE_PLL1Q RCC_CCIPR5_FDCAN12SEL_0 1108 #define RCC_FDCAN12CLKSOURCE_PLL2Q RCC_CCIPR5_FDCAN12SEL_1 1109 /** 1110 * @} 1111 */ 1112 1113 #else 1114 /** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Kernel Clock Source 1115 * @{ 1116 */ 1117 #define RCC_FDCAN1CLKSOURCE_HSE ((uint32_t)0x00000000U) 1118 #define RCC_FDCAN1CLKSOURCE_PLL1Q RCC_CCIPR5_FDCAN1SEL_0 1119 #define RCC_FDCAN1CLKSOURCE_PLL2Q RCC_CCIPR5_FDCAN1SEL_1 1120 /** 1121 * @} 1122 */ 1123 1124 #endif /*FDCAN2*/ 1125 1126 /** @defgroup RCCEx_ADCDAC_Clock_Source ADCDAC Kernel Clock Source 1127 * @{ 1128 */ 1129 #define RCC_ADCDACCLKSOURCE_HCLK ((uint32_t)0x00000000U) 1130 #define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 1131 #define RCC_ADCDACCLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 1132 #define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_1 | RCC_CCIPR5_ADCDACSEL_0) 1133 #define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 1134 #define RCC_ADCDACCLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_2 | RCC_CCIPR5_ADCDACSEL_0) 1135 1136 /** 1137 * @} 1138 */ 1139 1140 /** @defgroup RCCEx_DAC_Low_Power_Clock_Source DAC Low Power Kernel Clock Source 1141 * @{ 1142 */ 1143 #define RCC_DACLPCLKSOURCE_LSE ((uint32_t)0x00000000U) 1144 #define RCC_DACLPCLKSOURCE_LSI RCC_CCIPR5_DACSEL 1145 /** 1146 * @} 1147 */ 1148 1149 #if defined(SAI1) 1150 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 1151 * @{ 1152 */ 1153 #define RCC_SAI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1154 #define RCC_SAI1CLKSOURCE_PLL2P RCC_CCIPR5_SAI1SEL_0 1155 #define RCC_SAI1CLKSOURCE_PLL3P RCC_CCIPR5_SAI1SEL_1 1156 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) 1157 #define RCC_SAI1CLKSOURCE_CLKP RCC_CCIPR5_SAI1SEL_2 1158 /** 1159 * @} 1160 */ 1161 #endif /* SAI1 */ 1162 1163 #if defined(SAI2) 1164 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 1165 * @{ 1166 */ 1167 #define RCC_SAI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1168 #define RCC_SAI2CLKSOURCE_PLL2P RCC_CCIPR5_SAI2SEL_0 1169 #define RCC_SAI2CLKSOURCE_PLL3P RCC_CCIPR5_SAI2SEL_1 1170 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) 1171 #define RCC_SAI2CLKSOURCE_CLKP RCC_CCIPR5_SAI2SEL_2 1172 /** 1173 * @} 1174 */ 1175 #endif /* SAI2 */ 1176 1177 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1178 * @{ 1179 */ 1180 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1181 #define RCC_CLKPSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 1182 #define RCC_CLKPSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 1183 /** 1184 * @} 1185 */ 1186 1187 #if defined(SDMMC1) 1188 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1 Clock Source 1189 * @{ 1190 */ 1191 #define RCC_SDMMC1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1192 #define RCC_SDMMC1CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC1SEL 1193 /** 1194 * @} 1195 */ 1196 #endif /* SDMMC1 */ 1197 1198 #if defined(SDMMC2) 1199 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC2 Clock Source 1200 * @{ 1201 */ 1202 #define RCC_SDMMC2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1203 #define RCC_SDMMC2CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC2SEL 1204 /** 1205 * @} 1206 */ 1207 #endif /* SDMMC2 */ 1208 1209 #if defined(OCTOSPI1) 1210 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 1211 * @{ 1212 */ 1213 #define RCC_OSPICLKSOURCE_HCLK ((uint32_t)0x00000000U) 1214 #define RCC_OSPICLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 1215 #define RCC_OSPICLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 1216 #define RCC_OSPICLKSOURCE_CLKP (RCC_CCIPR4_OCTOSPISEL_0 | RCC_CCIPR4_OCTOSPISEL_1) 1217 /** 1218 * @} 1219 */ 1220 #endif /* OCTOSPI1 */ 1221 1222 #if defined(CEC) 1223 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 1224 * @{ 1225 */ 1226 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) 1227 #define RCC_CECCLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 1228 #define RCC_CECCLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 1229 /** 1230 * @} 1231 */ 1232 #endif /* CEC */ 1233 1234 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 1235 * @{ 1236 */ 1237 #define RCC_USBCLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 1238 #if defined(RCC_CR_PLL3ON) 1239 #define RCC_USBCLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 1240 #else 1241 #define RCC_USBCLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 1242 #endif /* RCC_CR_PLL3ON */ 1243 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR4_USBSEL 1244 /** 1245 * @} 1246 */ 1247 1248 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1249 * @{ 1250 */ 1251 #define RCC_TIMPRES_DEACTIVATED (0x00000000U) 1252 #define RCC_TIMPRES_ACTIVATED RCC_CFGR1_TIMPRE 1253 1254 /** 1255 * @} 1256 */ 1257 1258 #if defined(CRS) 1259 1260 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1261 * @{ 1262 */ 1263 #define RCC_CRS_NONE ((uint32_t)0x00000000U) 1264 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) 1265 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) 1266 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) 1267 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) 1268 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) 1269 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1275 * @{ 1276 */ 1277 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ 1278 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1279 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1285 * @{ 1286 */ 1287 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ 1288 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1289 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1290 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1291 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1292 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1293 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1294 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1295 /** 1296 * @} 1297 */ 1298 1299 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1300 * @{ 1301 */ 1302 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ 1303 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1304 /** 1305 * @} 1306 */ 1307 1308 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1309 * @{ 1310 */ 1311 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1312 to a target frequency of 48 MHz and a synchronization 1313 signal frequency of 1 kHz (SOF signal from USB). */ 1314 /** 1315 * @} 1316 */ 1317 1318 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1319 * @{ 1320 */ 1321 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ 1322 /** 1323 * @} 1324 */ 1325 1326 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1327 * @{ 1328 */ 1329 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the 1330 middle of the trimming interval. The trimming step 1331 is around 67 kHz between two consecutive TRIM 1332 steps. A higher TRIM value corresponds to a higher 1333 output frequency */ 1334 /** 1335 * @} 1336 */ 1337 1338 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1339 * @{ 1340 */ 1341 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1342 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1343 /** 1344 * @} 1345 */ 1346 1347 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1348 * @{ 1349 */ 1350 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1351 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1352 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1353 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1354 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1355 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1356 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1357 /** 1358 * @} 1359 */ 1360 1361 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1362 * @{ 1363 */ 1364 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1365 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1366 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1367 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1368 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1369 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1370 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1371 /** 1372 * @} 1373 */ 1374 1375 #endif /* CRS */ 1376 1377 /** 1378 * @} 1379 */ 1380 1381 /* Exported macros -----------------------------------------------------------*/ 1382 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1383 * @{ 1384 */ 1385 1386 /** @brief Macros to enable or disable the HSI and CSI divided clock for Timers 12, 15 and LPTimer2 input capture. 1387 * @note HSI and CSI clocks without division are available when TIMIC is enabled 1388 * @retval None 1389 */ 1390 #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ 1391 #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ 1392 1393 /** @brief Macro to configure the PLL2 clock source. 1394 * @note This function must be used only when all PLL2 is disabled. 1395 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1396 * This parameter can be one of the following values: 1397 * @arg RCC_PLL2_SOURCE_NONE: No oscillator clock selected as PLL2 clock entry 1398 * @arg RCC_PLL2_SOURCE_CSI: CSI oscillator clock selected as PLL2 clock entry 1399 * @arg RCC_PLL2_SOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry 1400 * @arg RCC_PLL2_SOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry 1401 * 1402 */ 1403 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, \ 1404 (__PLL2SOURCE__)) 1405 1406 /** @brief Macro to get the oscillator used as PLL2 clock source. 1407 * @retval The oscillator used as PLL2 clock source. The returned value can be one 1408 * of the following: 1409 * - RCC_PLL2_SOURCE_NONE: No oscillator is used as PLL clock source. 1410 * - RCC_PLL2_SOURCE_CSI: CSI oscillator is used as PLL clock source. 1411 * - RCC_PLL2_SOURCE_HSI: HSI oscillator is used as PLL clock source. 1412 * - RCC_PLL2_SOURCE_HSE: HSE oscillator is used as PLL clock source. 1413 */ 1414 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) 1415 1416 /** 1417 * @brief Macro to configures the PLL2 source, multiplication and division factors. 1418 * @note This function must be used only when PLL2 is disabled. 1419 * 1420 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1421 * This parameter can be one of the following values: 1422 * @arg @ref RCC_PLL2_SOURCE_NONE No clock selected as PLL2 clock entry 1423 * @arg @ref RCC_PLL2_SOURCE_CSI CSI oscillator clock selected as PLL2 clock entry 1424 * @arg @ref RCC_PLL2_SOURCE_HSI HSI oscillator clock selected as PLL2 clock entry 1425 * @arg @ref RCC_PLL2_SOURCE_HSE HSE oscillator clock selected as PLL2 clock entry 1426 * 1427 * @param __PLL2M__ specifies the division factor of PLL2 input clock. 1428 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1429 * 1430 * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock 1431 * This parameter must be a number between 4 and 512. 1432 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1433 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1434 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1435 * 1436 * @param __PLL2P__: specifies the division factor for peripheral kernel clocks 1437 * This parameter must be a number between 1 and 128 1438 * 1439 * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks 1440 * This parameter must be a number between 1 and 128 1441 * 1442 * @param __PLL2R__: specifies the division factor for peripheral kernel clocks 1443 * This parameter must be a number between 1 and 128 1444 * 1445 * @retval None 1446 */ 1447 #define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ 1448 do{ \ 1449 WRITE_REG(RCC->PLL2CFGR,((__PLL2SOURCE__) << RCC_PLL2CFGR_PLL2SRC_Pos) | \ 1450 ((__PLL2M__) << RCC_PLL2CFGR_PLL2M_Pos));\ 1451 WRITE_REG(RCC->PLL2DIVR , ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | \ 1452 ((((__PLL2P__) - 1U) << RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) | \ 1453 ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR_PLL2Q_Pos) & RCC_PLL2DIVR_PLL2Q) | \ 1454 ((((__PLL2R__) - 1U) << RCC_PLL2DIVR_PLL2R_Pos) & RCC_PLL2DIVR_PLL2R))); \ 1455 } while(0) 1456 /** 1457 * @brief Macro to configure the PLL2 clock multiplication factor N. 1458 * 1459 * @note This function must be used only when the PLL2 is disabled. 1460 * @note PLL2 clock source is independent from the main PLL and is configured through 1461 * __HAL_RCC_PLL2_CONFIG() macro. 1462 * 1463 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock. 1464 * This parameter must be a number between 4 and 512. 1465 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1466 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1467 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1468 * 1469 * @retval None 1470 */ 1471 #define __HAL_RCC_PLL2_MULN_CONFIG(__PLL2N__) \ 1472 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos) 1473 1474 /** @brief Macro to configure the PLL2 input clock division factor M. 1475 * 1476 * @note This function must be used only when the PLL2 is disabled. 1477 * @note PLL2 clock source is independent from the main PLL and is configured through 1478 * __HAL_RCC_PLL2_CONFIG() macro. 1479 * 1480 * @param __PLL2M__ specifies the division factor for PLL2 clock. 1481 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1482 * In order to save power when PLL2 is not used, the value of PLL2M must be set to 0. 1483 * 1484 * @retval None 1485 */ 1486 #define __HAL_RCC_PLL2_DIVM_CONFIG(__PLL2M__) \ 1487 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos) 1488 1489 /** @brief Macro to configure the PLL2 clock division factor P. 1490 * 1491 * @note This function must be used only when the PLL2 is disabled. 1492 * @note PLL2 clock source is independent from the main PLL and is configured through 1493 * __HAL_RCC_PLL2_CONFIG() macro. 1494 * 1495 * @param __PLL2P__ specifies the division factor for PLL2 output P clock. 1496 * This parameter must be a number in the range (1 to 128). 1497 * Use to set PLL2 output P clock frequency = f(PLL2) / PLL2P 1498 * 1499 * @retval None 1500 */ 1501 #define __HAL_RCC_PLL2_DIVP_CONFIG(__PLL2P__) \ 1502 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, ((__PLL2P__) - 1U) << RCC_PLL2DIVR_P2_Pos) 1503 1504 /** @brief Macro to configure the PLL2 clock division factor Q. 1505 * 1506 * @note This function must be used only when the PLL2 is disabled. 1507 * @note PLL2 clock source is independent from the main PLL and is configured through 1508 * __HAL_RCC_PLL2_CONFIG() macro. 1509 * 1510 * @param __PLL2Q__ specifies the division factor for PLL2 output Q clock. 1511 * This parameter must be a number in the range (1 to 128). 1512 * Use to set PLL2 output Q clock frequency = f(PLL2) / PLL2Q 1513 * 1514 * @retval None 1515 */ 1516 #define __HAL_RCC_PLL2_DIVQ_CONFIG(__PLL2Q__) \ 1517 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, ((__PLL2Q__) - 1U) << RCC_PLL2DIVR_Q2_Pos) 1518 1519 /** @brief Macro to configure the PLL2 clock division factor R. 1520 * 1521 * @note This function must be used only when the PLL2 is disabled. 1522 * @note PLL2 clock source is independent from the main PLL and is configured through 1523 * __HAL_RCC_PLL2_CONFIG() macro. 1524 * 1525 * @param __PLL2R__ specifies the division factor for PLL2 output R clock. 1526 * This parameter must be a number in the range (1 to 128). 1527 * Use to set PLL2 output R clock frequency = f(PLL2) / PLL2R 1528 * 1529 * @retval None 1530 */ 1531 #define __HAL_RCC_PLL2_DIVR_CONFIG(__PLL2R__) \ 1532 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, ((__PLL2R__) - 1U) << RCC_PLL2DIVR_R2_Pos) 1533 1534 /** @brief Macros to enable or disable the PLL2. 1535 * @note After enabling PLL2, the application software should wait on 1536 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1537 * be used as kernel clock source. 1538 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1539 * @retval None 1540 */ 1541 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1542 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1543 1544 /** 1545 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1546 * @note Enabling/disabling those clocks can be done at any time without the need to stop the PLL2, 1547 * This is mainly used to save Power. 1548 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1549 * This parameter can be one or a combination of the following values: 1550 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1551 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1552 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1553 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1554 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1555 * @retval None 1556 */ 1557 #define __HAL_RCC_PLL2_CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1558 #define __HAL_RCC_PLL2_CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1559 1560 /** 1561 * @brief Macro to get the PLL2 clock output enable status. 1562 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1563 * This parameter can be one of the following values: 1564 * This parameter can be one or a combination of the following values: 1565 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1566 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1567 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1568 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1569 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1570 * @retval SET / RESET 1571 */ 1572 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1573 1574 /** 1575 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1576 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL2 1577 * @retval None 1578 */ 1579 #define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1580 #define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1581 1582 /** 1583 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1584 * 1585 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1586 * 1587 * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1588 * It should be a value between 0 and 8191 1589 * @note Warning: the software has to set correctly these bits to insure that the VCO 1590 * output frequency is between its valid frequency range, which is: 1591 * 192 to 836 MHz if PLL2VCOSEL = 0 1592 * 150 to 420 MHz if PLL2VCOSEL = 1. 1593 * 1594 * @retval None 1595 */ 1596 #define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, \ 1597 (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) 1598 1599 /** @brief Macro to select the PLL2 reference frequency range. 1600 * @param __PLL2VCIRange__: specifies the PLL2 input frequency range 1601 * This parameter can be one of the following values: 1602 * @arg RCC_PLL2_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1603 * @arg RCC_PLL2_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1604 * @arg RCC_PLL2_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1605 * @arg RCC_PLL2_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1606 * @retval None 1607 */ 1608 #define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ 1609 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) 1610 1611 /** @brief Macro to select the PLL2 reference frequency range. 1612 * @param __RCC_PLL2VCORange__: specifies the PLL2 output frequency range 1613 * This parameter can be one of the following values: 1614 * @arg RCC_PLL2_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 1615 * @arg RCC_PLL2_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 1616 * 1617 * @retval None 1618 */ 1619 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1620 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1621 1622 #if defined(RCC_CR_PLL3ON) 1623 /** @brief Macro to configure the PLL3 clock source. 1624 * @note This function must be used only when all PLL3 is disabled. 1625 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1626 * This parameter can be one of the following values: 1627 * @arg RCC_PLL3_SOURCE_NONE: No oscillator clock selected as PLL3 clock entry 1628 * @arg RCC_PLL3_SOURCE_CSI: CSI oscillator clock selected as PLL3 clock entry 1629 * @arg RCC_PLL3_SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 1630 * @arg RCC_PLL3_SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 1631 * 1632 */ 1633 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ 1634 (__PLL3SOURCE__)) 1635 1636 /** @brief Macro to get the oscillator used as PLL3 clock source. 1637 * @retval The oscillator used as PLL3 clock source. The returned value can be one 1638 * of the following: 1639 * - RCC_PLL3_SOURCE_NONE: No oscillator is used as PLL3 clock source. 1640 * - RCC_PLL3_SOURCE_CSI: CSI oscillator is used as PLL3 clock source. 1641 * - RCC_PLL3_SOURCE_HSI: HSI oscillator is used as PLL3 clock source. 1642 * - RCC_PLL3_SOURCE_HSE: HSE oscillator is used as PLL3 clock source. 1643 */ 1644 #define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) 1645 1646 /** 1647 * @brief Macro to configures the PLL3 source, multiplication and division factors. 1648 * @note This function must be used only when PLL3 is disabled. 1649 * 1650 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1651 * This parameter can be one of the following values: 1652 * @arg @ref RCC_PLL3_SOURCE_NONE No clock selected as PLL3 clock entry 1653 * @arg @ref RCC_PLL3_SOURCE_CSI CSI oscillator clock selected as PLL3 clock entry 1654 * @arg @ref RCC_PLL3_SOURCE_HSI HSI oscillator clock selected as PLL3 clock entry 1655 * @arg @ref RCC_PLL3_SOURCE_HSE HSE oscillator clock selected as PLL3 clock entry 1656 * 1657 * @param __PLL3M__ specifies the division factor of PLL3 input clock. 1658 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1659 * 1660 * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock 1661 * This parameter must be a number between 4 and 512. 1662 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1663 * output frequency is between 150 and 420 MHz (when in medium VCO range) 1664 * or between 192 and 836 MHZ (when in wide VCO range) 1665 * 1666 * @param __PLL3P__: specifies the division factor for peripheral kernel clocks 1667 * This parameter must be a number between 1 and 128 1668 * 1669 * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks 1670 * This parameter must be a number between 1 and 128 1671 * 1672 * @param __PLL3R__: specifies the division factor for peripheral kernel clocks 1673 * This parameter must be a number between 1 and 128 1674 * 1675 * @retval None 1676 */ 1677 #define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ 1678 do{\ 1679 WRITE_REG(RCC->PLL3CFGR, ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos) | \ 1680 ((__PLL3M__) << RCC_PLL3CFGR_PLL3M_Pos)); \ 1681 WRITE_REG(RCC->PLL3DIVR , ( (((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | \ 1682 ((((__PLL3P__) - 1U) << RCC_PLL3DIVR_PLL3P_Pos) & RCC_PLL3DIVR_PLL3P) | \ 1683 ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR_PLL3Q_Pos) & RCC_PLL3DIVR_PLL3Q) | \ 1684 ((((__PLL3R__) - 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ 1685 } while(0) 1686 1687 /** 1688 * @brief Macro to configure the PLL3 clock multiplication factor N. 1689 * 1690 * @note This function must be used only when the PLL3 is disabled. 1691 * @note PLL3 clock source is independent from the main PLL and is configured through 1692 * __HAL_RCC_PLL3_CONFIG() macro. 1693 * 1694 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock. 1695 * This parameter must be a number between 8 and 86. 1696 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1697 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1698 * PLL3 clock frequency = f(PLL3) multiplied by PLL3N 1699 * 1700 * @retval None 1701 */ 1702 #define __HAL_RCC_PLL3_MULN_CONFIG(__PLL3N__) \ 1703 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, ((__PLL3N__) - 1U) << RCC_PLL3DIVR_N3_Pos) 1704 1705 /** @brief Macro to configure the PLL3 input clock division factor M. 1706 * 1707 * @note This function must be used only when the PLL3 is disabled. 1708 * @note PLL3 clock source is independent from the main PLL and is configured through 1709 * __HAL_RCC_PLL3_CONFIG() macro. 1710 * 1711 * @param __PLL3M__ specifies the division factor for PLL3 clock. 1712 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1713 * In order to save power when PLL3 is not used, the value of PLL3M must be set to 0. 1714 * 1715 * @retval None 1716 */ 1717 #define __HAL_RCC_PLL3_DIVM_CONFIG(__PLL3M__) \ 1718 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_DIVM3, (__PLL3M__) << RCC_PLL3CFGR_DIVM3_Pos) 1719 1720 /** @brief Macro to configure the PLL3 clock division factor P. 1721 * 1722 * @note This function must be used only when the PLL3 is disabled. 1723 * @note PLL3 clock source is independent from the main PLL and is configured through 1724 * __HAL_RCC_PLL3_CONFIG() macro. 1725 * 1726 * @param __PLL3P__ specifies the division factor for PLL3 output P clock. 1727 * This parameter must be a number in the range (1 to 128). 1728 * Use to set PLL3 output P clock frequency = f(PLL3) / PLL3P 1729 * 1730 * @retval None 1731 */ 1732 #define __HAL_RCC_PLL3_DIVP_CONFIG(__PLL3P__) \ 1733 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, ((__PLL3P__) - 1U) << RCC_PLL3DIVR_P3_Pos) 1734 1735 /** @brief Macro to configure the PLL3 clock division factor Q. 1736 * 1737 * @note This function must be used only when the PLL3 is disabled. 1738 * @note PLL3 clock source is independent from the main PLL and is configured through 1739 * __HAL_RCC_PLL3_CONFIG() macro. 1740 * 1741 * @param __PLL3Q__ specifies the division factor for PLL3 output Q clock. 1742 * This parameter must be a number in the range (1 to 128). 1743 * Use to set PLL3 output Q clock frequency = f(PLL3) / PLL3Q 1744 * 1745 * @retval None 1746 */ 1747 #define __HAL_RCC_PLL3_DIVQ_CONFIG(__PLL3Q__) \ 1748 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, ((__PLL3Q__) - 1U) << RCC_PLL3DIVR_Q3_Pos) 1749 1750 /** @brief Macro to configure the PLL3 clock division factor R. 1751 * 1752 * @note This function must be used only when the PLL3 is disabled. 1753 * @note PLL3 clock source is independent from the main PLL and is configured through 1754 * __HAL_RCC_PLL3_CONFIG() macro. 1755 * 1756 * @param __PLL3R__ specifies the division factor for PLL3 output R clock. 1757 * This parameter must be a number in the range (1 to 128). 1758 * Use to set PLL3 output R clock frequency = f(PLL3) / PLL3R 1759 * 1760 * @retval None 1761 */ 1762 #define __HAL_RCC_PLL3_DIVR_CONFIG(__PLL3R__) \ 1763 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, ((__PLL3R__) - 1U) << RCC_PLL3DIVR_R3_Pos) 1764 1765 /** 1766 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1767 * 1768 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1769 * 1770 * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1771 * It should be a value between 0 and 8191 1772 * @note Warning: the software has to set correctly these bits to insure that the VCO 1773 * output frequency is between its valid frequency range, which is: 1774 * 192 to 836 MHz if PLL3VCOSEL = 0 1775 * 150 to 420 MHz if PLL3VCOSEL = 1. 1776 * 1777 * @retval None 1778 */ 1779 #define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ 1780 (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) 1781 1782 /** @brief Macro to select the PLL3 reference frequency range. 1783 * @param __PLL3VCIRange__: specifies the PLL3 input frequency range 1784 * This parameter can be one of the following values: 1785 * @arg RCC_PLL3_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1786 * @arg RCC_PLL3_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1787 * @arg RCC_PLL3_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1788 * @arg RCC_PLL3_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1789 * 1790 * @retval None 1791 */ 1792 #define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ 1793 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) 1794 1795 /** @brief Macro to select the PLL3 reference frequency range. 1796 * @param __RCC_PLL3VCORange__: specifies the PLL3 input frequency range 1797 * This parameter can be one of the following values: 1798 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz 1799 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 1800 * 1801 * @retval None 1802 */ 1803 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 1804 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 1805 1806 /** 1807 * @brief Macros to enable or disable the PLL3. 1808 * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1809 * @retval None 1810 */ 1811 1812 /** @brief Macros to enable or disable the main PLL3. 1813 * @note After enabling PLL3, the application software should wait on 1814 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1815 * be used as kernel clock source. 1816 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1817 */ 1818 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1819 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1820 1821 /** 1822 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1823 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL3 1824 * @retval None 1825 */ 1826 #define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1827 #define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1828 1829 /** 1830 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1831 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, 1832 * This is mainly used to save Power. 1833 * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted 1834 * This parameter can be one of the following values: 1835 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1836 * high-quality audio performance on SAI and SPI/I2S interfaces. 1837 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1838 * and USB peripherals. 1839 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1840 * 1841 * @retval None 1842 */ 1843 #define __HAL_RCC_PLL3_CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1844 #define __HAL_RCC_PLL3_CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1845 1846 /** 1847 * @brief Macro to get clock output enable status (PLL3_SAI2). 1848 * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be output. 1849 * This parameter can be one of the following values: 1850 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1851 * high-quality audio performance on SAI and SPI/I2S interfaces. 1852 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1853 * and USB peripherals. 1854 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1855 * 1856 * @retval SET / RESET 1857 */ 1858 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1859 #endif /* RCC_CR_PLL3ON */ 1860 1861 /** @brief Macro to configure the ADC and DAC kernel clock source. 1862 * @param __ADCDAC_CLKSOURCE__ specifies the ADC and DAC kernel clock source. 1863 * This parameter can be one of the following values: 1864 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB bus clock selected as ADC and DAC kernel clock 1865 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock selected as ADC and DAC kernel clock 1866 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock selected as ADC and DAC kernel clock 1867 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE clock selected as ADC and DAC kernel clock 1868 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI clock selected as ADC and DAC kernel clock 1869 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI clock selected as ADC and DAC kernel clock 1870 * @retval None 1871 */ 1872 #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ 1873 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) 1874 1875 /** @brief Macro to get the ADC and DAC kernel clock source. 1876 * @retval The clock source can be one of the following values: 1877 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB Bus clock used as ADC and DAC kernel clock 1878 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock used as ADC and DAC kernel clock 1879 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock used as ADC and DAC kernel clock 1880 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE oscillator used as ADC and DAC kernel clock 1881 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI oscillator used as ADC and DAC kernel clock 1882 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI oscillator used as ADC and DAC kernel clock 1883 */ 1884 #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL))) 1885 1886 /** @brief Macro to configure the DAC kernel clock source in low-power mode. 1887 * @param __DACLPCLKSOURCE__ specifies the DAC kernel clock source in low-power mode. 1888 * This parameter can be one of the following values: 1889 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator selected as DAC kernel clock in low-power mode 1890 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator selected as DAC kernel clock in low-power mode 1891 * @retval None 1892 */ 1893 #define __HAL_RCC_DAC_LP_CONFIG(__DACLPCLKSOURCE__) \ 1894 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, (uint32_t)(__DACLPCLKSOURCE__)) 1895 1896 /** @brief Macro to get the DAC kernel clock source in low-power mode. 1897 * @retval The clock source can be one of the following values: 1898 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator used as DAC kernel clock in low-power mode 1899 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator used as DAC kernel clock in low-power mode 1900 */ 1901 #define __HAL_RCC_GET_DAC_LP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_DACSEL))) 1902 1903 #if defined(FDCAN2) 1904 /** @brief Macro to configure the FDCAN12 kernel clock (FDCAN2CLK). 1905 * 1906 * @param __FDCAN12_CLKSOURCE__ specifies the FDCAN12 kernel clock source. 1907 * This parameter can be one of the following values: 1908 * @arg @ref RCC_FDCAN12CLKSOURCE_HSE HSE oscillator selected as FDCAN12 kernel clock 1909 * @arg @ref RCC_FDCAN12CLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN12 kernel clock 1910 * @arg @ref RCC_FDCAN12CLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN12 kernel clock 1911 * @retval None 1912 */ 1913 #define __HAL_RCC_FDCAN12_CONFIG(__FDCAN12_CLKSOURCE__) \ 1914 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCAN12SEL, (uint32_t)(__FDCAN12_CLKSOURCE__)) 1915 1916 /** @brief Macro to get the FDCAN12 clock source. 1917 * @retval The clock source can be one of the following values: 1918 * @arg @ref RCC_FDCAN12CLKSOURCE_HSE HSE oscillator selected as FDCAN12 kernel clock 1919 * @arg @ref RCC_FDCAN12CLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN12 kernel clock 1920 * @arg @ref RCC_FDCAN12CLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN12 kernel clock 1921 */ 1922 #define __HAL_RCC_GET_FDCAN12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_FDCAN12SEL))) 1923 1924 #else 1925 /** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). 1926 * 1927 * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. 1928 * This parameter can be one of the following values: 1929 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE oscillator selected as FDCAN1 kernel clock 1930 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN1 kernel clock 1931 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN1 kernel clock 1932 * @retval None 1933 */ 1934 #define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ 1935 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCAN1SEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) 1936 1937 /** @brief Macro to get the FDCAN1 clock source. 1938 * @retval The clock source can be one of the following values: 1939 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE oscillator selected as FDCAN1 kernel clock 1940 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN1 kernel clock 1941 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN1 kernel clock 1942 */ 1943 #define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_FDCAN1SEL))) 1944 #endif /*FDCAN2*/ 1945 1946 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1947 * 1948 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1949 * This parameter can be one of the following values: 1950 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1951 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1952 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1953 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1954 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1955 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1956 * @retval None 1957 * 1958 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1959 */ 1960 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1961 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1962 1963 /** @brief Macro to get the LPTIM1 clock source. 1964 * @retval The clock source can be one of the following values: 1965 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1966 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1967 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1968 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1969 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1970 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1971 * 1972 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1973 */ 1974 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) 1975 1976 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1977 * 1978 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1979 * This parameter can be one of the following values: 1980 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1981 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1982 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1983 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1984 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1985 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 1986 * @retval None 1987 * 1988 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1989 */ 1990 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1991 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1992 1993 /** @brief Macro to get the LPTIM2 clock source. 1994 * @retval The clock source can be one of the following values: 1995 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1996 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1997 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1998 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1999 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 2000 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 2001 * 2002 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2003 */ 2004 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL))) 2005 2006 #if defined(LPTIM3) 2007 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 2008 * 2009 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 2010 * This parameter can be one of the following values: 2011 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 2012 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 2013 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 2014 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 2015 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 2016 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 2017 * @retval None 2018 */ 2019 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 2020 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 2021 2022 /** @brief Macro to get the LPTIM3 clock source. 2023 * @retval The clock source can be one of the following values: 2024 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 2025 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 2026 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 2027 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 2028 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 2029 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 2030 */ 2031 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL))) 2032 #endif /* LPTIM3 */ 2033 2034 #if defined(LPTIM4) 2035 /** @brief Macro to configure the LPTIM4 clock (LPTIM4CLK). 2036 * 2037 * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. 2038 * This parameter can be one of the following values: 2039 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 2040 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 2041 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 2042 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 2043 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 2044 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 2045 * @retval None 2046 */ 2047 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ 2048 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL, (uint32_t)(__LPTIM4_CLKSOURCE__)) 2049 2050 /** @brief Macro to get the LPTIM4 clock source. 2051 * @retval The clock source can be one of the following values: 2052 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 2053 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 2054 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 2055 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 2056 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 2057 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 2058 */ 2059 #define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL))) 2060 #endif /* LPTIM4 */ 2061 2062 #if defined(LPTIM5) 2063 /** @brief Macro to configure the LPTIM5 clock (LPTIM5CLK). 2064 * 2065 * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. 2066 * This parameter can be one of the following values: 2067 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2068 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2069 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2070 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2071 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2072 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2073 * @retval None 2074 */ 2075 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ 2076 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL, (uint32_t)(__LPTIM5_CLKSOURCE__)) 2077 2078 /** @brief Macro to get the LPTIM5 clock source. 2079 * @retval The clock source can be one of the following values: 2080 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2081 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2082 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2083 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2084 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2085 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2086 */ 2087 #define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL))) 2088 #endif /* LPTIM5 */ 2089 2090 #if defined(LPTIM6) 2091 /** @brief Macro to configure the LPTIM6 clock (LPTIM6CLK). 2092 * 2093 * @param __LPTIM6_CLKSOURCE__ specifies the LPTIM6 clock source. 2094 * This parameter can be one of the following values: 2095 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2096 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2097 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2098 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2099 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2100 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2101 * @retval None 2102 */ 2103 #define __HAL_RCC_LPTIM6_CONFIG(__LPTIM6_CLKSOURCE__) \ 2104 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL, (uint32_t)(__LPTIM6_CLKSOURCE__)) 2105 2106 /** @brief Macro to get the LPTIM6 clock source. 2107 * @retval The clock source can be one of the following values: 2108 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2109 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2110 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2111 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2112 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2113 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2114 */ 2115 #define __HAL_RCC_GET_LPTIM6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL))) 2116 #endif /* LPTIM6 */ 2117 2118 /** @brief macro to configure the SPI1 clock source. 2119 * @retval The clock source can be one of the following values: 2120 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2121 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2122 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2123 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2124 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2125 * 2126 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2127 */ 2128 #define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ 2129 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) 2130 2131 /** @brief macro to get the SPI1 clock source. 2132 * @retval The clock source can be one of the following values: 2133 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2134 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2135 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2136 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2137 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2138 * 2139 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2140 */ 2141 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) 2142 2143 /** @brief macro to configure the SPI2 clock source. 2144 * @retval The clock source can be one of the following values: 2145 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2146 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2147 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2148 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2149 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2150 * 2151 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2152 */ 2153 #define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ 2154 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) 2155 2156 /** @brief macro to get the SPI2 clock source. 2157 * @retval The clock source can be one of the following values: 2158 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2159 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2160 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2161 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2162 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2163 * 2164 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2165 */ 2166 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL))) 2167 2168 /** @brief macro to configure the SPI3 clock source. 2169 * @retval The clock source can be one of the following values: 2170 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2171 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2172 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2173 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2174 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2175 * 2176 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2177 */ 2178 #define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ 2179 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) 2180 2181 /** @brief macro to get the SPI3 clock source. 2182 * @retval The clock source can be one of the following values: 2183 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2184 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2185 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2186 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2187 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2188 * 2189 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2190 */ 2191 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) 2192 2193 #if defined(SPI4) 2194 /** @brief macro to configure the SPI4 clock source. 2195 * @retval The clock source can be one of the following values: 2196 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2197 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2198 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2199 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2200 * @arg RCC_SPI4CLKSOURCE_CSI CSI Clock used as SPI4 clock 2201 * @arg RCC_SPI4CLKSOURCE_HSE HSE Clock used as SPI4 clock 2202 */ 2203 #define __HAL_RCC_SPI4_CONFIG(__SPI4CLKSource__) \ 2204 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL, (uint32_t)(__SPI4CLKSource__)) 2205 2206 /** @brief macro to get the SPI4 clock source. 2207 * @retval The clock source can be one of the following values: 2208 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2209 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2210 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2211 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2212 * @arg RCC_SPI4CLKSOURCE_CSI CSI used as SPI4 clock 2213 * @arg RCC_SPI4CLKSOURCE_HSE HSE used as SPI4 clock 2214 */ 2215 #define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL))) 2216 #endif /* SPI4 */ 2217 2218 #if defined(SPI5) 2219 /** @brief macro to configure the SPI5 clock source. 2220 * @retval The clock source can be one of the following values: 2221 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2222 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2223 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2224 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2225 * @arg RCC_SPI5CLKSOURCE_CSI CSI Clock used as SPI5 clock 2226 * @arg RCC_SPI5CLKSOURCE_HSE HSE Clock used as SPI5 clock 2227 */ 2228 #define __HAL_RCC_SPI5_CONFIG(__SPI5CLKSource__) \ 2229 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL, (uint32_t)(__SPI5CLKSource__)) 2230 2231 /** @brief macro to get the SPI5 clock source. 2232 * @retval The clock source can be one of the following values: 2233 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2234 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2235 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2236 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2237 * @arg RCC_SPI5CLKSOURCE_CSI CSI used as SPI5 clock 2238 * @arg RCC_SPI5CLKSOURCE_HSE HSE used as SPI5 clock 2239 */ 2240 #define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL))) 2241 #endif /* SPI5 */ 2242 2243 #if defined(SPI6) 2244 /** @brief macro to configure the SPI6 clock source. 2245 * @retval The clock source can be one of the following values: 2246 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2247 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2248 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2249 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2250 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2251 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2252 */ 2253 #define __HAL_RCC_SPI6_CONFIG(__SPI6CLKSource__) \ 2254 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL, (uint32_t)(__SPI6CLKSource__)) 2255 2256 /** @brief macro to get the SPI6 clock source. 2257 * @retval The clock source can be one of the following values: 2258 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2259 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2260 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2261 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2262 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2263 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2264 */ 2265 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL))) 2266 #endif /* SPI6 */ 2267 2268 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 2269 * 2270 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 2271 * This parameter can be one of the following values: 2272 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2273 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2274 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2275 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2276 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2277 * @retval None 2278 * 2279 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2280 * (**) : For stm32h503xx family line. 2281 */ 2282 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 2283 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 2284 2285 /** @brief Macro to get the I2C1 clock source. 2286 * @retval The clock source can be one of the following values: 2287 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2288 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2289 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2290 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2291 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2292 * 2293 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2294 * (**) : For stm32h503xx family line. 2295 */ 2296 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL))) 2297 2298 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 2299 * 2300 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 2301 * This parameter can be one of the following values: 2302 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2303 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2304 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2305 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2306 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2307 * @retval None 2308 * 2309 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2310 * (**) : For stm32h503xx family line. 2311 */ 2312 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 2313 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 2314 2315 /** @brief Macro to get the I2C2 clock source. 2316 * @retval The clock source can be one of the following values: 2317 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2318 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2319 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2320 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2321 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2322 * 2323 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2324 * (**) : For stm32h503xx family line. 2325 */ 2326 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL))) 2327 2328 #if defined(I2C3) 2329 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 2330 * 2331 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 2332 * This parameter can be one of the following values: 2333 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2334 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2335 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2336 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2337 * @retval None 2338 */ 2339 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 2340 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 2341 2342 /** @brief Macro to get the I2C3 clock source. 2343 * @retval The clock source can be one of the following values: 2344 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2345 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2346 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2347 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2348 */ 2349 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL))) 2350 #endif /* I2C3 */ 2351 2352 #if defined(I2C4) 2353 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 2354 * 2355 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 2356 * This parameter can be one of the following values: 2357 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2358 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2359 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2360 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2361 * @retval None 2362 */ 2363 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 2364 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 2365 2366 /** @brief Macro to get the I2C4 clock source. 2367 * @retval The clock source can be one of the following values: 2368 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2369 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2370 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2371 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2372 */ 2373 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL))) 2374 #endif /* I2C4 */ 2375 2376 /** @brief Macro to configure the I3C1 clock (I3C1CLK). 2377 * 2378 * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. 2379 * This parameter can be one of the following values: 2380 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2381 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2382 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2383 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2384 * @retval None 2385 * 2386 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2387 * (**) : For stm32h503xx family line. 2388 */ 2389 #define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ 2390 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) 2391 2392 /** @brief Macro to get the I3C1 clock source. 2393 * @retval The clock source can be one of the following values: 2394 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2395 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2396 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2397 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2398 * 2399 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2400 * (**) : For stm32h503xx family line. 2401 */ 2402 #define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL))) 2403 2404 #if defined(I3C2) 2405 /** @brief Macro to configure the I3C2 clock (I3C2CLK). 2406 * 2407 * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. 2408 * This parameter can be one of the following values: 2409 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2410 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2411 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2412 * @retval None 2413 */ 2414 #define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ 2415 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__)) 2416 2417 /** @brief Macro to get the I3C2 clock source. 2418 * @retval The clock source can be one of the following values: 2419 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2420 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2421 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2422 */ 2423 #define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL))) 2424 #endif /* I3C2 */ 2425 2426 /** @brief Macro to configure the USART1 clock (USART1CLK). 2427 * 2428 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 2429 * This parameter can be one of the following values: 2430 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2431 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2432 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2433 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2434 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2435 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2436 * @retval None 2437 * 2438 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2439 */ 2440 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 2441 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 2442 2443 /** @brief Macro to get the USART1 clock source. 2444 * @retval The clock source can be one of the following values: 2445 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2446 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2447 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2448 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2449 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2450 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2451 * 2452 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2453 */ 2454 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 2455 2456 /** @brief Macro to configure the USART2 clock (USART2CLK). 2457 * 2458 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 2459 * This parameter can be one of the following values: 2460 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2461 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2462 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2463 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2464 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2465 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2466 * @retval None 2467 * 2468 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2469 */ 2470 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 2471 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 2472 2473 /** @brief Macro to get the USART2 clock source. 2474 * @retval The clock source can be one of the following values: 2475 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2476 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2477 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2478 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2479 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2480 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2481 * 2482 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2483 */ 2484 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 2485 2486 /** @brief Macro to configure the USART3 clock (USART3CLK). 2487 * 2488 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 2489 * This parameter can be one of the following values: 2490 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2491 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2492 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2493 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2494 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2495 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2496 * @retval None 2497 * 2498 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2499 */ 2500 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 2501 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 2502 2503 /** @brief Macro to get the USART3 clock source. 2504 * @retval The clock source can be one of the following values: 2505 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2506 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2507 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2508 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2509 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2510 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2511 * 2512 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2513 */ 2514 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 2515 2516 #if defined(UART4) 2517 /** @brief Macro to configure the UART4 clock (UART4CLK). 2518 * 2519 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 2520 * This parameter can be one of the following values: 2521 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2522 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2523 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2524 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2525 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2526 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2527 * @retval None 2528 */ 2529 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 2530 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 2531 2532 /** @brief Macro to get the UART4 clock source. 2533 * @retval The clock source can be one of the following values: 2534 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2535 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2536 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2537 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2538 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2539 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2540 */ 2541 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 2542 #endif /* UART4 */ 2543 2544 #if defined(UART5) 2545 /** @brief Macro to configure the UART5 clock (UART5CLK). 2546 * 2547 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 2548 * This parameter can be one of the following values: 2549 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2550 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2551 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2552 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2553 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2554 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2555 * @retval None 2556 */ 2557 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 2558 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 2559 2560 /** @brief Macro to get the UART5 clock source. 2561 * @retval The clock source can be one of the following values: 2562 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2563 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2564 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2565 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2566 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2567 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2568 */ 2569 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 2570 #endif /* UART5 */ 2571 2572 #if defined(USART6) 2573 /** @brief Macro to configure the USART6 clock (USART6CLK). 2574 * 2575 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 2576 * This parameter can be one of the following values: 2577 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK2 selected as USART6 clock 2578 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2579 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2580 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2581 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2582 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2583 * @retval None 2584 */ 2585 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 2586 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 2587 2588 /** @brief Macro to get the USART6 clock source. 2589 * @retval The clock source can be one of the following values: 2590 * @arg @ref RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock 2591 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2592 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2593 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2594 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2595 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2596 */ 2597 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART6SEL))) 2598 #endif /* USART6 */ 2599 2600 #if defined(UART7) 2601 /** @brief Macro to configure the UART7 clock (UART7CLK). 2602 * 2603 * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. 2604 * This parameter can be one of the following values: 2605 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2606 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2607 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2608 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2609 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2610 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2611 * @retval None 2612 */ 2613 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ 2614 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) 2615 2616 /** @brief Macro to get the UART7 clock source. 2617 * @retval The clock source can be one of the following values: 2618 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2619 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2620 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2621 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2622 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2623 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2624 */ 2625 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART7SEL))) 2626 #endif /* UART5 */ 2627 2628 #if defined(UART8) 2629 /** @brief Macro to configure the UART8 clock (UART8CLK). 2630 * 2631 * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. 2632 * This parameter can be one of the following values: 2633 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2634 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2635 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2636 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2637 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2638 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2639 * @retval None 2640 */ 2641 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ 2642 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) 2643 2644 /** @brief Macro to get the UART8 clock source. 2645 * @retval The clock source can be one of the following values: 2646 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2647 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2648 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2649 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2650 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2651 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2652 */ 2653 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART8SEL))) 2654 #endif /* UART8 */ 2655 2656 #if defined(UART9) 2657 /** @brief Macro to configure the UART9 clock (UART9CLK). 2658 * 2659 * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. 2660 * This parameter can be one of the following values: 2661 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2662 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2663 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2664 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2665 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2666 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2667 * @retval None 2668 */ 2669 #define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ 2670 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART9SEL, (uint32_t)(__UART9_CLKSOURCE__)) 2671 2672 /** @brief Macro to get the UART9 clock source. 2673 * @retval The clock source can be one of the following values: 2674 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2675 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2676 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2677 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2678 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2679 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2680 */ 2681 #define __HAL_RCC_GET_UART9_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART9SEL))) 2682 #endif /* UART9 */ 2683 2684 #if defined(USART10) 2685 /** @brief Macro to configure the USART10 clock (USART10CLK). 2686 * 2687 * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. 2688 * This parameter can be one of the following values: 2689 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2690 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2691 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2692 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2693 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2694 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2695 * @retval None 2696 */ 2697 #define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ 2698 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART10SEL, (uint32_t)(__USART10_CLKSOURCE__)) 2699 2700 /** @brief Macro to get the USART10 clock source. 2701 * @retval The clock source can be one of the following values: 2702 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2703 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2704 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2705 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2706 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2707 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2708 */ 2709 #define __HAL_RCC_GET_USART10_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART10SEL))) 2710 #endif /* USART10 */ 2711 2712 #if defined(USART11) 2713 /** @brief Macro to configure the USART11 clock (USART11CLK). 2714 * 2715 * @param __USART11_CLKSOURCE__ specifies the USART11 clock source. 2716 * This parameter can be one of the following values: 2717 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2718 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2719 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2720 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2721 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2722 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2723 * @retval None 2724 */ 2725 #define __HAL_RCC_USART11_CONFIG(__USART11_CLKSOURCE__) \ 2726 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART11SEL, (uint32_t)(__USART11_CLKSOURCE__)) 2727 2728 /** @brief Macro to get the USART11 clock source. 2729 * @retval The clock source can be one of the following values: 2730 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2731 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2732 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2733 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2734 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2735 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2736 */ 2737 #define __HAL_RCC_GET_USART11_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART11SEL))) 2738 #endif /* USART11 */ 2739 2740 #if defined(UART12) 2741 /** @brief Macro to configure the UART12 clock (UART12CLK). 2742 * 2743 * @param __UART12_CLKSOURCE__ specifies the UART12 clock source. 2744 * This parameter can be one of the following values: 2745 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2746 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2747 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2748 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2749 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2750 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2751 * @retval None 2752 */ 2753 #define __HAL_RCC_UART12_CONFIG(__UART12_CLKSOURCE__) \ 2754 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART12SEL, (uint32_t)(__UART12_CLKSOURCE__)) 2755 2756 /** @brief Macro to get the UART12 clock source. 2757 * @retval The clock source can be one of the following values: 2758 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2759 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2760 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2761 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2762 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2763 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2764 */ 2765 #define __HAL_RCC_GET_UART12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART12SEL))) 2766 #endif /* UART12 */ 2767 2768 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 2769 * 2770 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 2771 * This parameter can be one of the following values: 2772 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2773 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2774 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2775 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2776 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2777 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2778 * 2779 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2780 * @retval None 2781 */ 2782 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 2783 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 2784 2785 /** @brief Macro to get the LPUART1 clock source. 2786 * @retval The clock source can be one of the following values: 2787 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2788 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2789 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2790 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2791 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2792 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2793 * 2794 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2795 */ 2796 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) 2797 2798 #if defined(OCTOSPI1) 2799 /** @brief Macro to configure the OctoSPI clock. 2800 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 2801 * This parameter can be one of the following values: 2802 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2803 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2804 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2805 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2806 * @retval None 2807 */ 2808 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 2809 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 2810 2811 /** @brief Macro to get the OctoSPI clock source. 2812 * @retval The clock source can be one of the following values: 2813 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2814 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2815 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2816 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2817 */ 2818 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL))) 2819 #endif /* OCTOSPI1 */ 2820 2821 #if defined(SDMMC1) 2822 /** @brief Macro to configure the SDMMC1 clock (SDMMCCLK). 2823 * 2824 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. 2825 * This parameter can be one of the following values: 2826 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2827 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2828 */ 2829 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 2830 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) 2831 2832 /** @brief macro to get the SDMMC1 clock source. 2833 * @retval The clock source can be one of the following values: 2834 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2835 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2836 */ 2837 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL))) 2838 #endif /* SDMMC1 */ 2839 2840 #if defined(SDMMC2) 2841 /** @brief Macro to configure the SDMMC2 clock (SDMMCCLK). 2842 * 2843 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. 2844 * This parameter can be one of the following values: 2845 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2846 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2847 */ 2848 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ 2849 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) 2850 2851 /** @brief macro to get the SDMMC2 clock source. 2852 * @retval The clock source can be one of the following values: 2853 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2854 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2855 */ 2856 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL))) 2857 #endif /*SDMMC2*/ 2858 2859 /** @brief macro to configure the RNG clock (RNGCLK). 2860 * 2861 * @param __RNGCLKSource__: specifies the RNG clock source. 2862 * This parameter can be one of the following values: 2863 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2864 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2865 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2866 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2867 */ 2868 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 2869 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, (uint32_t)(__RNGCLKSource__)) 2870 2871 /** @brief macro to get the RNG clock source. 2872 * @retval The clock source can be one of the following values: 2873 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2874 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2875 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2876 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2877 */ 2878 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_RNGSEL))) 2879 2880 #if defined(SAI1) 2881 /** 2882 * @brief Macro to configure the SAI1 clock source. 2883 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. 2884 * This parameter can be one of the following values: 2885 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2886 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2Pselected as SAI1 clock 2887 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2888 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2889 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2890 * @retval None 2891 */ 2892 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 2893 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 2894 2895 /** @brief Macro to get the SAI1 clock source. 2896 * @retval The clock source can be one of the following values: 2897 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2898 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2P selected as SAI1 clock 2899 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2900 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2901 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2902 */ 2903 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL))) 2904 #endif /* SAI1 */ 2905 2906 #if defined(SAI2) 2907 /** 2908 * @brief Macro to configure the SAI2 clock source. 2909 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. 2910 * This parameter can be one of the following values: 2911 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2912 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2913 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2914 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2915 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2916 * @retval None 2917 */ 2918 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 2919 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 2920 2921 /** @brief Macro to get the SAI2 clock source. 2922 * @retval The clock source can be one of the following values: 2923 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2924 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2925 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2926 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2927 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2928 */ 2929 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL))) 2930 #endif /* SAI2 */ 2931 2932 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 2933 * @param __CLKPSource__ specifies Oscillator clock for peripheral 2934 * This parameter can be one of the following values: 2935 * @arg RCC_CLKPSOURCE_HSI HSI oscillator selected as clock for peripheral 2936 * @arg RCC_CLKPSOURCE_CSI CSI oscillator selected as clock for peripheral 2937 * @arg RCC_CLKPSOURCE_HSE HSE oscillator selected as clock for peripheral 2938 */ 2939 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 2940 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, (uint32_t)(__CLKPSource__)) 2941 2942 /** @brief Macro to get the oscillator clock for peripheral clock source. 2943 * @retval The clock source can be one of the following values: 2944 * @arg RCC_CLKPSOURCE_HSI HSI selected Oscillator clock for peripheral 2945 * @arg RCC_CLKPSOURCE_CSI CSI selected Oscillator clock for peripheral 2946 * @arg RCC_CLKPSOURCE_HSE HSE selected Oscillator clock for peripheral 2947 */ 2948 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL))) 2949 2950 #if defined(CEC) 2951 /** @brief Macro to configure the CEC clock (CECCLK) 2952 * @param __CECCLKSource__ specifies the CEC clock source. 2953 * This parameter can be one of the following values: 2954 * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 2955 * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock 2956 * @arg RCC_CECCLKSOURCE_CSI_DIV122 CSI Divided by 122 selected as CEC clock 2957 */ 2958 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 2959 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, (uint32_t)(__CECCLKSource__)) 2960 2961 /** @brief Macro to get the CEC clock source. 2962 * @retval The clock source can be one of the following values: 2963 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 2964 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 2965 * @arg RCC_CECCLKSOURCE_CSI_DIV122: CSI Divided by 122 selected as CEC clock 2966 */ 2967 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL))) 2968 #endif /* CEC */ 2969 2970 /** @brief Macro to configure the USB clock (USBCLK). 2971 * @param __USBCLKSource__ specifies the USB clock source. 2972 * This parameter can be one of the following values: 2973 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2974 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2975 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2976 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2977 * 2978 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2979 * (**) : For stm32h503xx family line. 2980 */ 2981 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 2982 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, (uint32_t)(__USBCLKSource__)) 2983 2984 /** @brief Macro to get the USB clock source. 2985 * @retval The clock source can be one of the following values: 2986 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2987 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2988 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2989 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2990 * 2991 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2992 * (**) : For stm32h503xx family line. 2993 */ 2994 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL))) 2995 2996 /** @brief Macro to configure the Timers clocks prescalers 2997 * @param __PRESC__ specifies the Timers clocks prescalers selection 2998 * This parameter can be one of the following values: 2999 * @arg RCC_TIMPRES_DEACTIVATED: The Timers kernels clocks prescaler is 3000 * equal to rcc_hclk1 if PPREx is corresponding to division by 1 or 2, 3001 * else it is equal to 2 x Frcc_pclkx (default after reset) 3002 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 3003 * equal to rcc_hclk1 if PPREx is corresponding to division by 1, 2 or 4, 3004 * else it is equal to 4 x Frcc_pclkx 3005 */ 3006 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR1 &= ~(RCC_CFGR1_TIMPRE);\ 3007 RCC->CFGR1 |= (__PRESC__); \ 3008 }while(0) 3009 3010 #if defined(CRS) 3011 3012 /** 3013 * @brief Enable the specified CRS interrupts. 3014 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 3015 * This parameter can be any combination of the following values: 3016 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3017 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3018 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3019 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3020 * @retval None 3021 */ 3022 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 3023 3024 /** 3025 * @brief Disable the specified CRS interrupts. 3026 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 3027 * This parameter can be any combination of the following values: 3028 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3029 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3030 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3031 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3032 * @retval None 3033 */ 3034 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 3035 3036 /** @brief Check whether the CRS interrupt has occurred or not. 3037 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 3038 * This parameter can be one of the following values: 3039 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3040 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3041 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3042 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3043 * @retval The new state of __INTERRUPT__ (0 or 1). 3044 */ 3045 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) 3046 3047 /** @brief Clear the CRS interrupt pending bits 3048 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3049 * This parameter can be any combination of the following values: 3050 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3051 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3052 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3053 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3054 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 3055 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 3056 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 3057 */ 3058 /* CRS IT Error Mask */ 3059 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ 3060 RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 3061 3062 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 3063 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 3064 { \ 3065 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3066 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 3067 } \ 3068 else \ 3069 { \ 3070 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 3071 } \ 3072 } while(0) 3073 3074 /** 3075 * @brief Check whether the specified CRS flag is set or not. 3076 * @param __FLAG__ specifies the flag to check. 3077 * This parameter can be one of the following values: 3078 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3079 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3080 * @arg @ref RCC_CRS_FLAG_ERR Error 3081 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3082 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3083 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3084 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3085 * @retval The new state of _FLAG_ (TRUE or FALSE). 3086 */ 3087 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 3088 3089 /** 3090 * @brief Clear the CRS specified FLAG. 3091 * @param __FLAG__ specifies the flag to clear. 3092 * This parameter can be any combination of the following values: 3093 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3094 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3095 * @arg @ref RCC_CRS_FLAG_ERR Error 3096 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3097 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3098 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3099 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3100 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS 3101 and consequently RCC_CRS_FLAG_ERR 3102 * @retval None 3103 */ 3104 3105 /* CRS Flag Error Mask */ 3106 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ 3107 RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 3108 3109 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 3110 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 3111 { \ 3112 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3113 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 3114 } \ 3115 else \ 3116 { \ 3117 WRITE_REG(CRS->ICR, (__FLAG__)); \ 3118 } \ 3119 } while(0) 3120 3121 /** 3122 * @} 3123 */ 3124 3125 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 3126 * @{ 3127 */ 3128 /** 3129 * @brief Enable the oscillator clock for frequency error counter. 3130 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 3131 * @retval None 3132 */ 3133 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 3134 3135 /** 3136 * @brief Disable the oscillator clock for frequency error counter. 3137 * @retval None 3138 */ 3139 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 3140 3141 /** 3142 * @brief Enable the automatic hardware adjustment of TRIM bits. 3143 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 3144 * @retval None 3145 */ 3146 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3147 3148 /** 3149 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 3150 * @retval None 3151 */ 3152 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3153 3154 /** 3155 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 3156 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 3157 * of the synchronization source after prescaling. It is then decreased by one in order to 3158 * reach the expected synchronization on the zero value. The formula is the following: 3159 * RELOAD = (fTARGET / fSYNC) -1 3160 * @param __FTARGET__ Target frequency (value in Hz) 3161 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 3162 * @retval None 3163 */ 3164 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 3165 3166 3167 /** 3168 * @} 3169 */ 3170 3171 #endif /* CRS */ 3172 3173 /* Private constants ---------------------------------------------------------*/ 3174 /** @addtogroup RCCEx_Private_Constants 3175 * @{ 3176 */ 3177 /* Define used for IS_RCC_* macros below */ 3178 #if defined(FDCAN2) && defined(SDMMC2) 3179 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3180 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3181 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3182 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3183 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3184 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3185 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3186 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3187 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3188 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3189 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ 3190 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 3191 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \ 3192 RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN12 | \ 3193 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3194 #elif defined(RCC_CR_PLL3ON) 3195 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3196 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3197 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3198 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3199 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3200 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3201 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3202 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3203 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3204 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3205 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_I3C1 | \ 3206 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ 3207 RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ 3208 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_CEC | \ 3209 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3210 #else 3211 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3212 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3213 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \ 3214 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ 3215 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ 3216 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 3217 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_USB | \ 3218 RCC_PERIPHCLK_CKPER) 3219 #endif /*FDCAN2 && SDMMC2 */ 3220 /** 3221 * @} 3222 */ 3223 3224 /* Private macros ------------------------------------------------------------*/ 3225 /** @addtogroup RCCEx_Private_Macros 3226 * @{ 3227 */ 3228 3229 #define IS_RCC_PLL2_SOURCE(SOURCE) (((SOURCE) == RCC_PLL2_SOURCE_CSI) || \ 3230 ((SOURCE) == RCC_PLL2_SOURCE_HSI) || \ 3231 ((SOURCE) == RCC_PLL2_SOURCE_HSE)) 3232 3233 #define IS_RCC_PLL2_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3234 #define IS_RCC_PLL2_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3235 #define IS_RCC_PLL2_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3236 #define IS_RCC_PLL2_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3237 #define IS_RCC_PLL2_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3238 3239 #define IS_RCC_PLL2_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3240 3241 #define IS_RCC_PLL2_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCIRANGE_0) || \ 3242 ((VALUE) == RCC_PLL2_VCIRANGE_1) || \ 3243 ((VALUE) == RCC_PLL2_VCIRANGE_2) || \ 3244 ((VALUE) == RCC_PLL2_VCIRANGE_3)) 3245 3246 #define IS_RCC_PLL2_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCORANGE_WIDE) || ((VALUE) == RCC_PLL2_VCORANGE_MEDIUM)) 3247 3248 #define IS_RCC_PLL2_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3249 3250 #if defined(RCC_CR_PLL3ON) 3251 #define IS_RCC_PLL3_SOURCE(SOURCE) (((SOURCE) == RCC_PLL3_SOURCE_CSI) || \ 3252 ((SOURCE) == RCC_PLL3_SOURCE_HSI) || \ 3253 ((SOURCE) == RCC_PLL3_SOURCE_HSE)) 3254 3255 #define IS_RCC_PLL3_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCIRANGE_0) || \ 3256 ((VALUE) == RCC_PLL3_VCIRANGE_1) || \ 3257 ((VALUE) == RCC_PLL3_VCIRANGE_2) || \ 3258 ((VALUE) == RCC_PLL3_VCIRANGE_3)) 3259 3260 #define IS_RCC_PLL3_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3261 #define IS_RCC_PLL3_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3262 #define IS_RCC_PLL3_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3263 #define IS_RCC_PLL3_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3264 #define IS_RCC_PLL3_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3265 3266 #define IS_RCC_PLL3_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3267 3268 #define IS_RCC_PLL3_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCORANGE_WIDE) || ((VALUE) == RCC_PLL3_VCORANGE_MEDIUM)) 3269 3270 #define IS_RCC_PLL3_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3271 3272 #endif /* RCC_CR_PLL3ON */ 3273 3274 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 3275 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 3276 3277 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 3278 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 3279 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 3280 3281 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != ((uint64_t)0x00)) && \ 3282 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == ((uint64_t)0x00))) 3283 #if defined(RCC_CR_PLL3ON) 3284 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3285 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3286 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3287 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ 3288 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3289 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3290 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3291 3292 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3293 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3294 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3295 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL3Q) || \ 3296 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3297 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3298 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3299 3300 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3301 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3302 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3303 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL3Q) || \ 3304 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3305 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3306 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3307 3308 #else 3309 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3310 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3311 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3312 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3313 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3314 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3315 3316 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3317 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3318 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3319 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3320 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3321 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3322 3323 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3324 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3325 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3326 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3327 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3328 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3329 3330 #endif /* RCC_CR_PLL3ON */ 3331 3332 #if defined(UART4) 3333 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 3334 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 3335 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL2Q) || \ 3336 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL3Q) || \ 3337 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ 3338 ((__SOURCE__) == RCC_UART4CLKSOURCE_CSI) || \ 3339 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) 3340 #endif /* UART4 */ 3341 3342 #if defined(UART5) 3343 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 3344 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 3345 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL2Q) || \ 3346 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL3Q) || \ 3347 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ 3348 ((__SOURCE__) == RCC_UART5CLKSOURCE_CSI) || \ 3349 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) 3350 #endif /* UART5 */ 3351 3352 #if defined(USART6) 3353 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ 3354 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ 3355 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL2Q) || \ 3356 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL3Q) || \ 3357 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ 3358 ((__SOURCE__) == RCC_USART6CLKSOURCE_CSI) || \ 3359 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) 3360 #endif /* USART6 */ 3361 3362 #if defined(UART7) 3363 #define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ 3364 (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ 3365 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL2Q) || \ 3366 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL3Q) || \ 3367 ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI) || \ 3368 ((__SOURCE__) == RCC_UART7CLKSOURCE_CSI) || \ 3369 ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)) 3370 #endif /* UART7 */ 3371 3372 #if defined(UART8) 3373 #define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ 3374 (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ 3375 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL2Q) || \ 3376 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL3Q) || \ 3377 ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI) || \ 3378 ((__SOURCE__) == RCC_UART8CLKSOURCE_CSI) || \ 3379 ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)) 3380 #endif /* UART8 */ 3381 3382 #if defined(UART9) 3383 #define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ 3384 (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK1) || \ 3385 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL2Q) || \ 3386 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL3Q) || \ 3387 ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI) || \ 3388 ((__SOURCE__) == RCC_UART9CLKSOURCE_CSI) || \ 3389 ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE)) 3390 #endif /* UART9 */ 3391 3392 #if defined(USART10) 3393 #define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ 3394 (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK1) || \ 3395 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL2Q) || \ 3396 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL3Q) || \ 3397 ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI) || \ 3398 ((__SOURCE__) == RCC_USART10CLKSOURCE_CSI) || \ 3399 ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE)) 3400 #endif /* USART10 */ 3401 3402 #if defined(USART11) 3403 #define IS_RCC_USART11CLKSOURCE(__SOURCE__) \ 3404 (((__SOURCE__) == RCC_USART11CLKSOURCE_PCLK1) || \ 3405 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL2Q) || \ 3406 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL3Q) || \ 3407 ((__SOURCE__) == RCC_USART11CLKSOURCE_HSI) || \ 3408 ((__SOURCE__) == RCC_USART11CLKSOURCE_CSI) || \ 3409 ((__SOURCE__) == RCC_USART11CLKSOURCE_LSE)) 3410 #endif /* USART11 */ 3411 3412 #if defined(UART12) 3413 #define IS_RCC_UART12CLKSOURCE(__SOURCE__) \ 3414 (((__SOURCE__) == RCC_UART12CLKSOURCE_PCLK1) || \ 3415 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL2Q) || \ 3416 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL3Q) || \ 3417 ((__SOURCE__) == RCC_UART12CLKSOURCE_HSI) || \ 3418 ((__SOURCE__) == RCC_UART12CLKSOURCE_CSI) || \ 3419 ((__SOURCE__) == RCC_UART12CLKSOURCE_LSE)) 3420 #endif /* UART12 */ 3421 3422 #if defined(RCC_CR_PLL3ON) 3423 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3424 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3425 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3426 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ 3427 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3428 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3429 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3430 3431 #else 3432 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3433 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3434 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3435 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3436 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3437 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3438 3439 #endif /* RCC_CR_PLL3ON */ 3440 3441 #if defined(RCC_CR_PLL3ON) 3442 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3443 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3444 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL3R) || \ 3445 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3446 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3447 3448 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3449 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3450 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL3R) || \ 3451 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3452 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3453 3454 #else 3455 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3456 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3457 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL2R) || \ 3458 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3459 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3460 3461 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3462 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3463 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL2R) || \ 3464 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3465 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3466 3467 #endif /* RCC_CR_PLL3ON */ 3468 3469 3470 #if defined(I2C3) 3471 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 3472 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ 3473 ((__SOURCE__) == RCC_I2C3CLKSOURCE_PLL3R) || \ 3474 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ 3475 ((__SOURCE__) == RCC_I2C3CLKSOURCE_CSI)) 3476 #endif /* I2C3 */ 3477 3478 #if defined(I2C4) 3479 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 3480 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK3) || \ 3481 ((__SOURCE__) == RCC_I2C4CLKSOURCE_PLL3R) || \ 3482 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI ) || \ 3483 ((__SOURCE__) == RCC_I2C4CLKSOURCE_CSI)) 3484 #endif /* I2C4 */ 3485 3486 #if defined(RCC_CR_PLL3ON) 3487 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3488 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3489 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ 3490 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3491 3492 #else 3493 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3494 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3495 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL2R) || \ 3496 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3497 3498 #endif /* RCC_CR_PLL3ON */ 3499 3500 #if defined(I3C2) 3501 #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ 3502 (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ 3503 ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ 3504 ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) 3505 #endif /* I3C2 */ 3506 3507 #if defined(SAI1) 3508 #define IS_RCC_SAI1CLK(__SOURCE__) \ 3509 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q)|| \ 3510 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P)|| \ 3511 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P)|| \ 3512 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 3513 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP)) 3514 3515 #endif /* SAI1 */ 3516 3517 #if defined(SAI2) 3518 #define IS_RCC_SAI2CLK(__SOURCE__) \ 3519 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q)|| \ 3520 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P)|| \ 3521 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P)|| \ 3522 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 3523 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP)) 3524 #endif /* SAI2 */ 3525 3526 #if defined(RCC_CR_PLL3ON) 3527 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3528 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3529 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3530 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ 3531 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3532 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3533 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3534 3535 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3536 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3537 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3538 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL3R) || \ 3539 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3540 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3541 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3542 3543 #else 3544 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3545 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3546 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3547 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3548 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3549 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3550 3551 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3552 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3553 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3554 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3555 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3556 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3557 3558 #endif /* RCC_CR_PLL3ON */ 3559 3560 #if defined(LPTIM3) 3561 #define IS_RCC_LPTIM3CLK(__SOURCE__) \ 3562 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK3) || \ 3563 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL2P) || \ 3564 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL3R) || \ 3565 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ 3566 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 3567 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP)) 3568 3569 #endif /* LPTIM3 */ 3570 3571 #if defined(LPTIM4) 3572 #define IS_RCC_LPTIM4CLK(__SOURCE__) \ 3573 (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK3) || \ 3574 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL2P) || \ 3575 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL3R) || \ 3576 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ 3577 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ 3578 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP)) 3579 3580 #endif /* LPTIM4 */ 3581 3582 #if defined(LPTIM5) 3583 #define IS_RCC_LPTIM5CLK(__SOURCE__) \ 3584 (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK3) || \ 3585 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL2P) || \ 3586 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL3R) || \ 3587 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ 3588 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ 3589 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP)) 3590 #endif /* LPTIM5 */ 3591 3592 #if defined(LPTIM6) 3593 #define IS_RCC_LPTIM6CLK(__SOURCE__) \ 3594 (((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PCLK3) || \ 3595 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL2P) || \ 3596 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL3R) || \ 3597 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSE) || \ 3598 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSI) || \ 3599 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_CLKP)) 3600 #endif /* LPTIM6 */ 3601 3602 #if defined(FDCAN2) 3603 #define IS_RCC_FDCAN12CLK(__SOURCE__) \ 3604 (((__SOURCE__) == RCC_FDCAN12CLKSOURCE_HSE) || \ 3605 ((__SOURCE__) == RCC_FDCAN12CLKSOURCE_PLL1Q) || \ 3606 ((__SOURCE__) == RCC_FDCAN12CLKSOURCE_PLL2Q)) 3607 #else 3608 #define IS_RCC_FDCAN1CLK(__SOURCE__) \ 3609 (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \ 3610 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1Q) || \ 3611 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2Q)) 3612 #endif /*FDCAN2*/ 3613 3614 #if defined(SDMMC1) 3615 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 3616 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL1Q) || \ 3617 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL2R)) 3618 #endif /* SDMMC1 */ 3619 3620 #if defined(SDMMC2) 3621 #define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ 3622 (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL1Q) || \ 3623 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL2R)) 3624 #endif /*SDMMC2*/ 3625 3626 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 3627 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 3628 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q) || \ 3629 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ 3630 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)) 3631 3632 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ 3633 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ 3634 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ 3635 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2R) || \ 3636 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ 3637 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ 3638 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_CSI)) 3639 3640 #define IS_RCC_DACLPCLKSOURCE(__SOURCE__) \ 3641 (((__SOURCE__) == RCC_DACLPCLKSOURCE_LSI) || \ 3642 ((__SOURCE__) == RCC_DACLPCLKSOURCE_LSE)) 3643 3644 #if defined(OCTOSPI1) 3645 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 3646 (((__SOURCE__) == RCC_OSPICLKSOURCE_HCLK) || \ 3647 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1Q) || \ 3648 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2R) || \ 3649 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 3650 #endif /* OCTOSPI1 */ 3651 3652 #if defined(RCC_CR_PLL3ON) 3653 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3654 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3655 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3656 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ 3657 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3658 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3659 3660 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3661 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3662 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3663 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3P) || \ 3664 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3665 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3666 3667 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3668 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3669 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3670 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3P) || \ 3671 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3672 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3673 #else 3674 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3675 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3676 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3677 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3678 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3679 3680 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3681 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3682 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3683 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3684 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3685 3686 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3687 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3688 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3689 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3690 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3691 3692 #endif /* RCC_CR_PLL3ON */ 3693 3694 #if defined(SPI4) 3695 #define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ 3696 (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ 3697 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2Q) || \ 3698 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3Q) || \ 3699 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 3700 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 3701 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 3702 #endif /* SPI4 */ 3703 3704 #if defined(SPI5) 3705 #define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ 3706 (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK3) || \ 3707 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2Q) || \ 3708 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3Q) || \ 3709 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 3710 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 3711 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 3712 #endif /* SPI5 */ 3713 3714 #if defined(SPI6) 3715 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 3716 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK2) || \ 3717 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ 3718 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ 3719 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 3720 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 3721 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 3722 #endif /* SPI6 */ 3723 3724 #if defined(RCC_CR_PLL3ON) 3725 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3726 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3727 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL3Q) || \ 3728 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3729 #else 3730 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3731 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3732 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \ 3733 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3734 #endif /* RCC_CR_PLL3ON */ 3735 3736 #if defined(CEC) 3737 #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ 3738 (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ 3739 ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ 3740 ((__SOURCE__) == RCC_CECCLKSOURCE_CSI_DIV122)) 3741 #endif /*CEC*/ 3742 3743 #define IS_RCC_TIMPRES(VALUE) \ 3744 (((VALUE) == RCC_TIMPRES_DEACTIVATED) || \ 3745 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 3746 3747 #if defined(CRS) 3748 3749 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 3750 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3751 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 3752 3753 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3754 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3755 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3756 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3757 3758 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3759 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3760 3761 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3762 3763 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3764 3765 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 3766 3767 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3768 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3769 3770 #endif /* CRS */ 3771 3772 /** 3773 * @} 3774 */ 3775 3776 /* Exported functions --------------------------------------------------------*/ 3777 /** @addtogroup RCCEx_Exported_Functions 3778 * @{ 3779 */ 3780 3781 /** @addtogroup RCCEx_Exported_Functions_Group1 3782 * @{ 3783 */ 3784 3785 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3786 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3787 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 3788 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks); 3789 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks); 3790 #if defined(RCC_CR_PLL3ON) 3791 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks); 3792 #endif /* RCC_CR_PLL3ON */ 3793 /** 3794 * @} 3795 */ 3796 3797 /** @addtogroup RCCEx_Exported_Functions_Group2 3798 * @{ 3799 */ 3800 3801 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init); 3802 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 3803 #if defined(RCC_CR_PLL3ON) 3804 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init); 3805 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); 3806 #endif /* RCC_CR_PLL3ON */ 3807 3808 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 3809 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 3810 void HAL_RCCEx_EnableLSECSS(void); 3811 void HAL_RCCEx_DisableLSECSS(void); 3812 void HAL_RCCEx_LSECSS_IRQHandler(void); 3813 void HAL_RCCEx_LSECSS_Callback(void); 3814 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 3815 void HAL_RCCEx_DisableLSCO(void); 3816 /** 3817 * @} 3818 */ 3819 3820 #if defined(CRS) 3821 3822 /** @addtogroup RCCEx_Exported_Functions_Group3 3823 * @{ 3824 */ 3825 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 3826 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 3827 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 3828 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 3829 void HAL_RCCEx_CRS_IRQHandler(void); 3830 void HAL_RCCEx_CRS_SyncOkCallback(void); 3831 void HAL_RCCEx_CRS_SyncWarnCallback(void); 3832 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 3833 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 3834 /** 3835 * @} 3836 */ 3837 3838 #endif /* CRS */ 3839 3840 /** 3841 * @} 3842 */ 3843 3844 /** 3845 * @} 3846 */ 3847 3848 /** 3849 * @} 3850 */ 3851 3852 #ifdef __cplusplus 3853 } 3854 #endif 3855 3856 #endif /* __STM32H5xx_HAL_RCC_EX_H */ 3857 3858
