1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32G4xx_HAL_RCC_EX_H 22 #define STM32G4xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32g4xx_hal_def.h" 30 31 /** @addtogroup STM32G4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief RCC extended clocks structure definition 47 */ 48 typedef struct 49 { 50 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 51 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 52 53 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 54 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 55 56 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 57 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 58 59 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 60 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 61 62 #if defined(UART4) 63 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 64 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 65 #endif /* UART4 */ 66 67 #if defined(UART5) 68 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 69 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 70 71 #endif /* UART5 */ 72 73 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 74 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 75 76 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 77 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 78 79 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 80 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 81 82 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 83 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 84 85 #if defined(I2C4) 86 87 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 88 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 89 #endif /* I2C4 */ 90 91 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 92 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 93 94 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 95 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 96 97 uint32_t I2sClockSelection; /*!< Specifies I2S clock source. 98 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 99 #if defined(FDCAN1) 100 101 uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. 102 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 103 #endif /* FDCAN1 */ 104 #if defined(USB) 105 106 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). 107 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 108 #endif /* USB */ 109 110 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). 111 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 112 113 uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. 114 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 115 116 #if defined(ADC345_COMMON) 117 uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. 118 This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ 119 #endif /* ADC345_COMMON */ 120 121 #if defined(QUADSPI) 122 uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. 123 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 124 #endif 125 126 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 127 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 128 }RCC_PeriphCLKInitTypeDef; 129 130 /** 131 * @brief RCC_CRS Init structure definition 132 */ 133 typedef struct 134 { 135 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 136 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 137 138 uint32_t Source; /*!< Specifies the SYNC signal source. 139 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 140 141 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 142 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 143 144 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 145 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 146 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 147 148 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 149 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 150 151 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 152 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 153 154 }RCC_CRSInitTypeDef; 155 156 /** 157 * @brief RCC_CRS Synchronization structure definition 158 */ 159 typedef struct 160 { 161 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 162 This parameter must be a number between 0 and 0xFFFF */ 163 164 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 165 This parameter must be a number between 0 and 0x7F */ 166 167 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 168 value latched in the time of the last SYNC event. 169 This parameter must be a number between 0 and 0xFFFF */ 170 171 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 172 frequency error counter latched in the time of the last SYNC event. 173 It shows whether the actual frequency is below or above the target. 174 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 175 176 }RCC_CRSSynchroInfoTypeDef; 177 178 /** 179 * @} 180 */ 181 182 /* Exported constants --------------------------------------------------------*/ 183 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 184 * @{ 185 */ 186 187 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 188 * @{ 189 */ 190 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 191 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 197 * @{ 198 */ 199 #define RCC_PERIPHCLK_USART1 0x00000001U 200 #define RCC_PERIPHCLK_USART2 0x00000002U 201 #define RCC_PERIPHCLK_USART3 0x00000004U 202 #if defined(UART4) 203 #define RCC_PERIPHCLK_UART4 0x00000008U 204 #endif /* UART4 */ 205 #if defined(UART5) 206 #define RCC_PERIPHCLK_UART5 0x00000010U 207 #endif /* UART5 */ 208 #define RCC_PERIPHCLK_LPUART1 0x00000020U 209 #define RCC_PERIPHCLK_I2C1 0x00000040U 210 #define RCC_PERIPHCLK_I2C2 0x00000080U 211 #define RCC_PERIPHCLK_I2C3 0x00000100U 212 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 213 #define RCC_PERIPHCLK_SAI1 0x00000400U 214 #define RCC_PERIPHCLK_I2S 0x00000800U 215 #if defined(FDCAN1) 216 #define RCC_PERIPHCLK_FDCAN 0x00001000U 217 #endif /* FDCAN1 */ 218 #define RCC_PERIPHCLK_USB 0x00002000U 219 #define RCC_PERIPHCLK_RNG 0x00004000U 220 #define RCC_PERIPHCLK_ADC12 0x00008000U 221 #if defined(ADC345_COMMON) 222 #define RCC_PERIPHCLK_ADC345 0x00010000U 223 #endif /* ADC345_COMMON */ 224 #if defined(I2C4) 225 #define RCC_PERIPHCLK_I2C4 0x00020000U 226 #endif /* I2C4 */ 227 #if defined(QUADSPI) 228 #define RCC_PERIPHCLK_QSPI 0x00040000U 229 #endif /* QUADSPI */ 230 #define RCC_PERIPHCLK_RTC 0x00080000U 231 /** 232 * @} 233 */ 234 235 236 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 237 * @{ 238 */ 239 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 240 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 241 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 242 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 243 /** 244 * @} 245 */ 246 247 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 248 * @{ 249 */ 250 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 251 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 252 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 253 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 254 /** 255 * @} 256 */ 257 258 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 259 * @{ 260 */ 261 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 262 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 263 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 264 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 265 /** 266 * @} 267 */ 268 269 #if defined(UART4) 270 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 271 * @{ 272 */ 273 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 274 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 275 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 276 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 277 /** 278 * @} 279 */ 280 #endif /* UART4 */ 281 282 #if defined(UART5) 283 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 284 * @{ 285 */ 286 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 287 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 288 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 289 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 290 /** 291 * @} 292 */ 293 #endif /* UART5 */ 294 295 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 296 * @{ 297 */ 298 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 299 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 300 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 301 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 302 /** 303 * @} 304 */ 305 306 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 307 * @{ 308 */ 309 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 310 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 311 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 312 /** 313 * @} 314 */ 315 316 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 317 * @{ 318 */ 319 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 320 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 321 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 327 * @{ 328 */ 329 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 330 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 331 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 337 * @{ 338 */ 339 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 340 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 341 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 342 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 343 /** 344 * @} 345 */ 346 347 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 348 * @{ 349 */ 350 #define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U 351 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 352 #define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 353 #define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) 354 /** 355 * @} 356 */ 357 358 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 359 * @{ 360 */ 361 #define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U 362 #define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 363 #define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 364 #define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) 365 /** 366 * @} 367 */ 368 #if defined(FDCAN1) 369 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source 370 * @{ 371 */ 372 #define RCC_FDCANCLKSOURCE_HSE 0x00000000U 373 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 374 #define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 375 /** 376 * @} 377 */ 378 #endif /* FDCAN1 */ 379 380 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 381 * @{ 382 */ 383 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 384 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 385 /** 386 * @} 387 */ 388 389 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 390 * @{ 391 */ 392 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 393 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 394 /** 395 * @} 396 */ 397 398 /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source 399 * @{ 400 */ 401 #define RCC_ADC12CLKSOURCE_NONE 0x00000000U 402 #define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 403 #define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 404 /** 405 * @} 406 */ 407 408 #if defined(ADC345_COMMON) 409 /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source 410 * @{ 411 */ 412 #define RCC_ADC345CLKSOURCE_NONE 0x00000000U 413 #define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 414 #define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 415 /** 416 * @} 417 */ 418 #endif /* ADC345_COMMON */ 419 420 #if defined(I2C4) 421 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 422 * @{ 423 */ 424 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 425 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 426 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 427 /** 428 * @} 429 */ 430 #endif /* I2C4 */ 431 432 #if defined(QUADSPI) 433 /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source 434 * @{ 435 */ 436 #define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U 437 #define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 438 #define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 439 /** 440 * @} 441 */ 442 #endif /* QUADSPI */ 443 444 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 445 * @{ 446 */ 447 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 453 * @{ 454 */ 455 #define RCC_CRS_NONE 0x00000000U 456 #define RCC_CRS_TIMEOUT 0x00000001U 457 #define RCC_CRS_SYNCOK 0x00000002U 458 #define RCC_CRS_SYNCWARN 0x00000004U 459 #define RCC_CRS_SYNCERR 0x00000008U 460 #define RCC_CRS_SYNCMISS 0x00000010U 461 #define RCC_CRS_TRIMOVF 0x00000020U 462 /** 463 * @} 464 */ 465 466 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 467 * @{ 468 */ 469 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 470 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 471 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 472 /** 473 * @} 474 */ 475 476 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 477 * @{ 478 */ 479 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 480 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 481 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 482 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 483 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 484 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 485 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 486 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 492 * @{ 493 */ 494 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 495 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 496 /** 497 * @} 498 */ 499 500 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 501 * @{ 502 */ 503 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 504 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 510 * @{ 511 */ 512 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 518 * @{ 519 */ 520 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 521 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 522 corresponds to a higher output frequency */ 523 /** 524 * @} 525 */ 526 527 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 528 * @{ 529 */ 530 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 531 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 537 * @{ 538 */ 539 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 540 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 541 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 542 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 543 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 544 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 545 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 546 547 /** 548 * @} 549 */ 550 551 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 552 * @{ 553 */ 554 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 555 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 556 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 557 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 558 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 559 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 560 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 561 562 /** 563 * @} 564 */ 565 566 /** 567 * @} 568 */ 569 570 /* Exported macros -----------------------------------------------------------*/ 571 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 572 * @{ 573 */ 574 575 /** @brief Macro to configure the USART1 clock (USART1CLK). 576 * 577 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 578 * This parameter can be one of the following values: 579 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 580 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 581 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 582 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 583 * @retval None 584 */ 585 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 586 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 587 588 /** @brief Macro to get the USART1 clock source. 589 * @retval The clock source can be one of the following values: 590 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 591 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 592 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 593 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 594 */ 595 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 596 597 /** @brief Macro to configure the USART2 clock (USART2CLK). 598 * 599 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 600 * This parameter can be one of the following values: 601 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 602 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 603 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 604 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 605 * @retval None 606 */ 607 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 608 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 609 610 /** @brief Macro to get the USART2 clock source. 611 * @retval The clock source can be one of the following values: 612 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 613 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 614 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 615 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 616 */ 617 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 618 619 /** @brief Macro to configure the USART3 clock (USART3CLK). 620 * 621 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 622 * This parameter can be one of the following values: 623 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 624 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 625 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 626 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 627 * @retval None 628 */ 629 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 630 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 631 632 /** @brief Macro to get the USART3 clock source. 633 * @retval The clock source can be one of the following values: 634 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 635 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 636 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 637 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 638 */ 639 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 640 641 #if defined(UART4) 642 /** @brief Macro to configure the UART4 clock (UART4CLK). 643 * 644 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 645 * This parameter can be one of the following values: 646 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 647 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 648 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 649 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 650 * @retval None 651 */ 652 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 654 655 /** @brief Macro to get the UART4 clock source. 656 * @retval The clock source can be one of the following values: 657 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 658 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 659 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 660 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 661 */ 662 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 663 #endif /* UART4 */ 664 665 #if defined(UART5) 666 667 /** @brief Macro to configure the UART5 clock (UART5CLK). 668 * 669 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 670 * This parameter can be one of the following values: 671 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 672 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 673 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 674 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 675 * @retval None 676 */ 677 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 678 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 679 680 /** @brief Macro to get the UART5 clock source. 681 * @retval The clock source can be one of the following values: 682 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 683 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 684 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 685 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 686 */ 687 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 688 689 #endif /* UART5 */ 690 691 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 692 * 693 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 694 * This parameter can be one of the following values: 695 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 696 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 697 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 698 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 699 * @retval None 700 */ 701 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 702 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 703 704 /** @brief Macro to get the LPUART1 clock source. 705 * @retval The clock source can be one of the following values: 706 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 707 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 708 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 709 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 710 */ 711 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 712 713 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 714 * 715 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 716 * This parameter can be one of the following values: 717 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 718 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 719 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 720 * @retval None 721 */ 722 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 723 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 724 725 /** @brief Macro to get the I2C1 clock source. 726 * @retval The clock source can be one of the following values: 727 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 728 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 729 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 730 */ 731 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 732 733 734 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 735 * 736 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 737 * This parameter can be one of the following values: 738 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 739 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 740 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 741 * @retval None 742 */ 743 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 744 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 745 746 /** @brief Macro to get the I2C2 clock source. 747 * @retval The clock source can be one of the following values: 748 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 749 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 750 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 751 */ 752 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 753 754 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 755 * 756 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 757 * This parameter can be one of the following values: 758 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 759 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 760 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 761 * @retval None 762 */ 763 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 764 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 765 766 /** @brief Macro to get the I2C3 clock source. 767 * @retval The clock source can be one of the following values: 768 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 769 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 770 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 771 */ 772 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 773 774 #if defined(I2C4) 775 776 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 777 * 778 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 779 * This parameter can be one of the following values: 780 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 781 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 782 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 783 * @retval None 784 */ 785 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 786 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 787 788 /** @brief Macro to get the I2C4 clock source. 789 * @retval The clock source can be one of the following values: 790 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 791 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 792 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 793 */ 794 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 795 796 #endif /* I2C4 */ 797 798 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 799 * 800 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 801 * This parameter can be one of the following values: 802 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 803 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 804 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 805 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 806 * @retval None 807 */ 808 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 809 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 810 811 /** @brief Macro to get the LPTIM1 clock source. 812 * @retval The clock source can be one of the following values: 813 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 814 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 815 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 816 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 817 */ 818 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 819 820 /** 821 * @brief Macro to configure the SAI1 clock source. 822 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 823 * from the HSI, system PLL, System Clock or external clock. 824 * This parameter can be one of the following values: 825 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 826 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 827 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 828 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 829 * 830 * @retval None 831 */ 832 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 833 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 834 835 /** @brief Macro to get the SAI1 clock source. 836 * @retval The clock source can be one of the following values: 837 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 838 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 839 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 840 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 841 * 842 */ 843 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 844 845 /** 846 * @brief Macro to configure the I2S clock source. 847 * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived 848 * from the HSI, system PLL, System Clock or external clock. 849 * This parameter can be one of the following values: 850 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 851 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 852 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 853 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 854 * 855 * @retval None 856 */ 857 #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ 858 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) 859 860 /** @brief Macro to get the I2S clock source. 861 * @retval The clock source can be one of the following values: 862 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 863 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 864 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 865 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 866 * 867 */ 868 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) 869 870 #if defined(FDCAN1) 871 /** 872 * @brief Macro to configure the FDCAN clock source. 873 * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived 874 * from the HSE, system PLL or PCLK1. 875 * This parameter can be one of the following values: 876 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 877 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 878 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 879 * 880 * @retval None 881 */ 882 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ 883 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 884 885 /** @brief Macro to get the FDCAN clock source. 886 * @retval The clock source can be one of the following values: 887 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 888 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 889 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 890 * 891 */ 892 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) 893 #endif /* FDCAN1 */ 894 895 /** @brief Macro to configure the RNG clock. 896 * 897 * @note USB and RNG peripherals share the same 48MHz clock source. 898 * 899 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 900 * This parameter can be one of the following values: 901 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 902 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 903 * @retval None 904 */ 905 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 906 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 907 908 /** @brief Macro to get the RNG clock. 909 * @retval The clock source can be one of the following values: 910 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 911 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock 912 */ 913 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 914 915 #if defined(USB) 916 917 /** @brief Macro to configure the USB clock (USBCLK). 918 * 919 * @note USB, RNG peripherals share the same 48MHz clock source. 920 * 921 * @param __USB_CLKSOURCE__ specifies the USB clock source. 922 * This parameter can be one of the following values: 923 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 924 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 925 * @retval None 926 */ 927 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 928 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 929 930 /** @brief Macro to get the USB clock source. 931 * @retval The clock source can be one of the following values: 932 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 933 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 934 */ 935 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 936 937 #endif /* USB */ 938 939 /** @brief Macro to configure the ADC12 interface clock. 940 * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. 941 * This parameter can be one of the following values: 942 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 943 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 944 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 945 * @retval None 946 */ 947 #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ 948 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) 949 950 /** @brief Macro to get the ADC12 clock source. 951 * @retval The clock source can be one of the following values: 952 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 953 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 954 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 955 */ 956 #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) 957 958 #if defined(ADC345_COMMON) 959 /** @brief Macro to configure the ADC345 interface clock. 960 * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. 961 * This parameter can be one of the following values: 962 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 963 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 964 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 965 * @retval None 966 */ 967 #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ 968 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) 969 970 /** @brief Macro to get the ADC345 clock source. 971 * @retval The clock source can be one of the following values: 972 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 973 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 974 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 975 */ 976 #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) 977 #endif /* ADC345_COMMON */ 978 979 #if defined(QUADSPI) 980 981 /** @brief Macro to configure the QuadSPI clock. 982 * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. 983 * This parameter can be one of the following values: 984 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 985 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 986 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 987 * @retval None 988 */ 989 #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ 990 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) 991 992 /** @brief Macro to get the QuadSPI clock source. 993 * @retval The clock source can be one of the following values: 994 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 995 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 996 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 997 */ 998 #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) 999 1000 #endif /* QUADSPI */ 1001 1002 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1003 * @brief macros to manage the specified RCC Flags and interrupts. 1004 * @{ 1005 */ 1006 1007 /** 1008 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 1009 * @retval None 1010 */ 1011 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1012 1013 /** 1014 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 1015 * @retval None 1016 */ 1017 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1018 1019 /** 1020 * @brief Enable the RCC LSE CSS Event Line. 1021 * @retval None. 1022 */ 1023 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1024 1025 /** 1026 * @brief Disable the RCC LSE CSS Event Line. 1027 * @retval None. 1028 */ 1029 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1030 1031 1032 /** 1033 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1034 * @retval None. 1035 */ 1036 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1037 1038 1039 /** 1040 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1041 * @retval None. 1042 */ 1043 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1044 1045 1046 /** 1047 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1048 * @retval None. 1049 */ 1050 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1051 1052 /** 1053 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1054 * @retval None. 1055 */ 1056 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1057 1058 /** 1059 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1060 * @retval None. 1061 */ 1062 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1063 do { \ 1064 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1065 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1066 } while(0) 1067 1068 /** 1069 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1070 * @retval None. 1071 */ 1072 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1073 do { \ 1074 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1075 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1076 } while(0) 1077 1078 /** 1079 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1080 * @retval EXTI RCC LSE CSS Line Status. 1081 */ 1082 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 1083 1084 /** 1085 * @brief Clear the RCC LSE CSS EXTI flag. 1086 * @retval None. 1087 */ 1088 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 1089 1090 /** 1091 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1092 * @retval None. 1093 */ 1094 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 1095 1096 1097 /** 1098 * @brief Enable the specified CRS interrupts. 1099 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1100 * This parameter can be any combination of the following values: 1101 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1102 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1103 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1104 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1105 * @retval None 1106 */ 1107 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1108 1109 /** 1110 * @brief Disable the specified CRS interrupts. 1111 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1112 * This parameter can be any combination of the following values: 1113 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1114 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1115 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1116 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1117 * @retval None 1118 */ 1119 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1120 1121 /** @brief Check whether the CRS interrupt has occurred or not. 1122 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1123 * This parameter can be one of the following values: 1124 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1125 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1126 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1127 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1128 * @retval The new state of __INTERRUPT__ (SET or RESET). 1129 */ 1130 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 1131 1132 /** @brief Clear the CRS interrupt pending bits 1133 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1134 * This parameter can be any combination of the following values: 1135 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1136 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1137 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1138 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1139 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1140 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1141 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1142 */ 1143 /* CRS IT Error Mask */ 1144 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 1145 1146 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1147 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1148 { \ 1149 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1150 } \ 1151 else \ 1152 { \ 1153 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1154 } \ 1155 } while(0) 1156 1157 /** 1158 * @brief Check whether the specified CRS flag is set or not. 1159 * @param __FLAG__ specifies the flag to check. 1160 * This parameter can be one of the following values: 1161 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1162 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1163 * @arg @ref RCC_CRS_FLAG_ERR Error 1164 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1165 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1166 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1167 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1168 * @retval The new state of _FLAG_ (TRUE or FALSE). 1169 */ 1170 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1171 1172 /** 1173 * @brief Clear the CRS specified FLAG. 1174 * @param __FLAG__ specifies the flag to clear. 1175 * This parameter can be one of the following values: 1176 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1177 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1178 * @arg @ref RCC_CRS_FLAG_ERR Error 1179 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1180 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1181 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1182 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1183 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1184 * @retval None 1185 */ 1186 1187 /* CRS Flag Error Mask */ 1188 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 1189 1190 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1191 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1192 { \ 1193 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1194 } \ 1195 else \ 1196 { \ 1197 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1198 } \ 1199 } while(0) 1200 1201 1202 /** 1203 * @} 1204 */ 1205 1206 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1207 * @{ 1208 */ 1209 /** 1210 * @brief Enable the oscillator clock for frequency error counter. 1211 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1212 * @retval None 1213 */ 1214 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1215 1216 /** 1217 * @brief Disable the oscillator clock for frequency error counter. 1218 * @retval None 1219 */ 1220 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1221 1222 /** 1223 * @brief Enable the automatic hardware adjustment of TRIM bits. 1224 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1225 * @retval None 1226 */ 1227 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1228 1229 /** 1230 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1231 * @retval None 1232 */ 1233 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1234 1235 /** 1236 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1237 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1238 * of the synchronization source after prescaling. It is then decreased by one in order to 1239 * reach the expected synchronization on the zero value. The formula is the following: 1240 * RELOAD = (fTARGET / fSYNC) -1 1241 * @param __FTARGET__ Target frequency (value in Hz) 1242 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1243 * @retval None 1244 */ 1245 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1246 1247 /** 1248 * @} 1249 */ 1250 1251 /** 1252 * @} 1253 */ 1254 1255 /* Exported functions --------------------------------------------------------*/ 1256 /** @addtogroup RCCEx_Exported_Functions 1257 * @{ 1258 */ 1259 1260 /** @addtogroup RCCEx_Exported_Functions_Group1 1261 * @{ 1262 */ 1263 1264 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1265 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1266 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1267 1268 /** 1269 * @} 1270 */ 1271 1272 /** @addtogroup RCCEx_Exported_Functions_Group2 1273 * @{ 1274 */ 1275 1276 void HAL_RCCEx_EnableLSECSS(void); 1277 void HAL_RCCEx_DisableLSECSS(void); 1278 void HAL_RCCEx_EnableLSECSS_IT(void); 1279 void HAL_RCCEx_LSECSS_IRQHandler(void); 1280 void HAL_RCCEx_LSECSS_Callback(void); 1281 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1282 void HAL_RCCEx_DisableLSCO(void); 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /** @addtogroup RCCEx_Exported_Functions_Group3 1289 * @{ 1290 */ 1291 1292 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1293 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1294 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1295 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1296 void HAL_RCCEx_CRS_IRQHandler(void); 1297 void HAL_RCCEx_CRS_SyncOkCallback(void); 1298 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1299 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1300 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1301 1302 /** 1303 * @} 1304 */ 1305 1306 /** 1307 * @} 1308 */ 1309 1310 /* Private macros ------------------------------------------------------------*/ 1311 /** @addtogroup RCCEx_Private_Macros 1312 * @{ 1313 */ 1314 1315 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1316 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1317 1318 #if defined(STM32G474xx) || defined(STM32G484xx) 1319 1320 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1321 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1322 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1323 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1324 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1325 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1326 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1327 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1328 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1329 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1330 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1331 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1332 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1333 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1334 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1335 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1336 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1337 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1338 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1339 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1340 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1341 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 1342 1343 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1344 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1345 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1346 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1347 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1348 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1349 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1350 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1351 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1352 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1353 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1354 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1355 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1356 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1357 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1358 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1359 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1360 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1361 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1362 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1363 #elif defined(STM32G473xx) || defined(STM32G483xx) 1364 1365 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1366 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1367 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1368 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1369 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1370 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1371 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1372 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1373 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1374 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1375 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1376 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1377 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1378 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1379 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1380 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1381 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1382 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1383 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1384 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1385 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1386 1387 #elif defined(STM32G471xx) 1388 1389 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1390 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1391 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1392 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1393 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1394 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1395 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1396 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1397 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1398 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1399 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1400 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1401 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1402 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1403 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1404 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1405 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1406 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1407 1408 #elif defined(STM32G431xx) || defined(STM32G441xx) 1409 1410 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1411 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1412 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1413 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1414 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1415 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1416 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1417 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1418 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1419 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1420 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1421 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1422 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1423 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1424 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1425 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1426 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1427 1428 #elif defined(STM32GBK1CB) 1429 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1430 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1431 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1432 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1433 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1434 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1435 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1436 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1437 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1438 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1439 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1440 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1441 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1442 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1443 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1444 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1445 1446 #endif /* STM32G474xx || STM32G484xx */ 1447 1448 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1449 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1450 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1451 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1452 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1453 1454 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1455 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1456 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1457 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1458 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1459 1460 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1461 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1462 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1463 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1464 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1465 1466 #if defined(UART4) 1467 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 1468 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 1469 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 1470 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 1471 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 1472 #endif /* UART4 */ 1473 1474 #if defined(UART5) 1475 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 1476 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 1477 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 1478 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 1479 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 1480 1481 #endif /* UART5 */ 1482 1483 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1484 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 1485 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 1486 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 1487 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 1488 1489 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 1490 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 1491 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 1492 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 1493 1494 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 1495 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 1496 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 1497 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 1498 1499 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 1500 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 1501 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 1502 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 1503 1504 #if defined(I2C4) 1505 1506 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 1507 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 1508 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 1509 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 1510 1511 #endif /* I2C4 */ 1512 1513 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1514 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 1515 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1516 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 1517 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 1518 1519 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 1520 (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ 1521 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 1522 ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ 1523 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 1524 1525 #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ 1526 (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ 1527 ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ 1528 ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ 1529 ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) 1530 1531 #if defined(FDCAN1) 1532 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 1533 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 1534 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 1535 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) 1536 1537 #endif /* FDCAN1 */ 1538 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1539 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 1540 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) 1541 1542 #if defined(USB) 1543 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1544 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 1545 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 1546 1547 #endif /* USB */ 1548 1549 #define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ 1550 (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ 1551 ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ 1552 ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) 1553 1554 #if defined(ADC345_COMMON) 1555 #define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ 1556 (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ 1557 ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ 1558 ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) 1559 #endif /* ADC345_COMMON */ 1560 1561 #if defined(QUADSPI) 1562 1563 #define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ 1564 (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ 1565 ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ 1566 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) 1567 1568 #endif /* QUADSPI */ 1569 1570 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 1571 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1572 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 1573 1574 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1575 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1576 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1577 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1578 1579 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1580 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1581 1582 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 1583 1584 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 1585 1586 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 1587 1588 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1589 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1590 1591 /** 1592 * @} 1593 */ 1594 1595 /** 1596 * @} 1597 */ 1598 1599 /** 1600 * @} 1601 */ 1602 1603 #ifdef __cplusplus 1604 } 1605 #endif 1606 1607 #endif /* STM32G4xx_HAL_RCC_EX_H */ 1608 1609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1610
