1 /*
2 * Copyright (c) 2022 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/ztest.h>
8 #include <soc.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <stm32_ll_rcc.h>
12 #include <zephyr/logging/log.h>
13 LOG_MODULE_REGISTER(test);
14
15 #if defined(CONFIG_SOC_SERIES_STM32WBX) || \
16 defined(CONFIG_SOC_SERIES_STM32WLX)
17 #define CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
18 #else
19 #define CALC_HCLK_FREQ __LL_RCC_CALC_HCLK_FREQ
20 #endif
21
ZTEST(stm32_sysclck_config,test_hclk_freq)22 ZTEST(stm32_sysclck_config, test_hclk_freq)
23 {
24 uint32_t soc_hclk_freq;
25
26 soc_hclk_freq = CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(),
27 LL_RCC_GetAHBPrescaler());
28
29 zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq,
30 "Expected hclck_freq: %d. Actual hclck_freq: %d",
31 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq);
32 }
33
ZTEST(stm32_sysclck_config,test_sysclk_src)34 ZTEST(stm32_sysclck_config, test_sysclk_src)
35 {
36 int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
37
38 #if STM32_SYSCLK_SRC_PLL
39 zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
40 "Expected sysclk src: PLL (0x%x). Actual: 0x%x",
41 RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src);
42 #elif STM32_SYSCLK_SRC_HSE
43 zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
44 "Expected sysclk src: HSE (0x%x). Actual: 0x%x",
45 RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src);
46 #elif STM32_SYSCLK_SRC_HSI
47 zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
48 "Expected sysclk src: HSI (0x%x). Actual: 0x%x",
49 RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src);
50 #elif STM32_SYSCLK_SRC_MSI
51 zassert_equal(RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src,
52 "Expected sysclk src: MSI (0x%x). Actual: 0x%x",
53 RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src);
54 #else
55 /* Case not expected */
56 zassert_true((STM32_SYSCLK_SRC_PLL ||
57 STM32_SYSCLK_SRC_HSE ||
58 STM32_SYSCLK_SRC_HSI ||
59 STM32_SYSCLK_SRC_MSI),
60 "Not expected. sys_clk_src: 0x%x\n", sys_clk_src);
61 #endif
62
63 }
64
ZTEST(stm32_sysclck_config,test_pll_src)65 ZTEST(stm32_sysclck_config, test_pll_src)
66 {
67 uint32_t pll_src = __HAL_RCC_GET_PLL_OSCSOURCE();
68
69 #if STM32_PLL_SRC_HSE
70 zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
71 "Expected PLL src: HSE (%d). Actual PLL src: %d",
72 RCC_PLLSOURCE_HSE, pll_src);
73 #elif STM32_PLL_SRC_HSI
74 #if defined(CONFIG_SOC_SERIES_STM32F1X)
75 zassert_equal(RCC_PLLSOURCE_HSI_DIV2, pll_src,
76 "Expected PLL src: HSI (%d). Actual PLL src: %d",
77 RCC_PLLSOURCE_HSI_DIV2, pll_src);
78 #else
79 zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
80 "Expected PLL src: HSI (%d). Actual PLL src: %d",
81 RCC_PLLSOURCE_HSI, pll_src);
82 #endif /* CONFIG_SOC_SERIES_STM32F1X */
83 #elif STM32_PLL_SRC_MSI
84 zassert_equal(RCC_PLLSOURCE_MSI, pll_src,
85 "Expected PLL src: MSI (%d). Actual PLL src: %d",
86 RCC_PLLSOURCE_MSI, pll_src);
87 #else /* --> RCC_PLLSOURCE_NONE */
88 #if defined(CONFIG_SOC_SERIES_STM32L0X) || defined(CONFIG_SOC_SERIES_STM32L1X) || \
89 defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F1X) || \
90 defined(CONFIG_SOC_SERIES_STM32F2X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
91 defined(CONFIG_SOC_SERIES_STM32F4X) || defined(CONFIG_SOC_SERIES_STM32F7X)
92 #define RCC_PLLSOURCE_NONE 0
93 /* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */
94 if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) {
95 /* should not happen : PLL must be disabled when not used */
96 pll_src = 0xFFFF; /* error code */
97 } else {
98 pll_src = RCC_PLLSOURCE_NONE;
99 }
100 #endif /* RCC_CR_PLLON */
101 zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
102 "Expected PLL src: none (%d). Actual PLL src: %d",
103 RCC_PLLSOURCE_NONE, pll_src);
104
105 #endif
106
107 }
108
109 #if STM32_HSE_ENABLED
ZTEST(stm32_sysclck_config,test_hse_css)110 ZTEST(stm32_sysclck_config, test_hse_css)
111 {
112 /* there is no function to read CSS status, so read directly from the register */
113 #if STM32_HSE_CSS
114 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled");
115 #else
116 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled");
117 #endif /* STM32_HSE_CSS */
118
119 }
120 #endif /* STM32_HSE_ENABLED */
121 ZTEST_SUITE(stm32_sysclck_config, NULL, NULL, NULL, NULL, NULL);
122
