1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_RCC_H 21 #define __STM32H5xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL1 configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< PLLState: The new state of the PLL1. 49 This parameter can be a value of @ref RCC_PLL1_Config */ 50 51 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL1_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. 55 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 56 57 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. 58 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 59 60 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 61 This parameter must be a number between Min_Data = 2 and Max_Data = 128 62 odd division factors are not allowed */ 63 64 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 66 67 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 68 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 69 70 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 71 This parameter must be a value of @ref RCC_PLL1_VCI_Range */ 72 73 uint32_t PLLVCOSEL; /*!< PLLVCOSEL: PLL1 clock Output range 74 This parameter must be a value of @ref RCC_PLL1_VCO_Range */ 75 76 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 8191 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSIDiv; /*!< The division factor of the HSI. 99 This parameter can be a value of @ref RCC_HSI_Div */ 100 101 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 103 on the other devices */ 104 105 uint32_t LSIState; /*!< The new state of the LSI. 106 This parameter can be a value of @ref RCC_LSI_Config */ 107 108 uint32_t CSIState; /*!< The new state of the CSI. 109 This parameter can be a value of @ref RCC_CSI_Config */ 110 111 uint32_t CSICalibrationValue; /*!< The calibration trimming value (default is RCC_CSICALIBRATION_DEFAULT). 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */ 113 114 uint32_t HSI48State; /*!< The new state of the HSI48. 115 This parameter can be a value of @ref RCC_HSI48_Config */ 116 117 RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ 118 119 } RCC_OscInitTypeDef; 120 121 /** 122 * @brief RCC System, AHB and APB busses clock configuration structure definition 123 */ 124 typedef struct 125 { 126 uint32_t ClockType; /*!< The clock to be configured. 127 This parameter can be a value of @ref RCC_System_Clock_Type */ 128 129 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 130 This parameter can be a value of @ref RCC_System_Clock_Source */ 131 132 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 133 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 134 135 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 136 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 137 138 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 139 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 140 141 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 142 This parameter can be a value of @ref RCC_APB3_Clock_Source */ 143 } RCC_ClkInitTypeDef; 144 145 /** 146 * @} 147 */ 148 149 /* Exported constants --------------------------------------------------------*/ 150 /** @defgroup RCC_Exported_Constants RCC Exported Constants 151 * @{ 152 */ 153 154 /** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping 155 * @{ 156 */ 157 158 /** 159 * @} 160 */ 161 162 /** @defgroup RCC_Timeout_Value Timeout Values 163 * @{ 164 */ 165 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 167 /** 168 * @} 169 */ 170 171 /** @defgroup RCC_Oscillator_Type Oscillator Type 172 * @{ 173 */ 174 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) /*!< Oscillator configuration unchanged */ 175 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) /*!< HSE to configure */ 176 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) /*!< HSI to configure */ 177 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) /*!< LSE to configure */ 178 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) /*!< LSI to configure */ 179 #define RCC_OSCILLATORTYPE_CSI (0x00000010U) /*!< CSI to configure */ 180 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) /*!< HSI48 to configure */ 181 /** 182 * @} 183 */ 184 185 /** @defgroup RCC_HSE_Config HSE Config 186 * @{ 187 */ 188 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 189 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 190 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Analog clock source for HSE clock */ 191 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Digital clock source for HSE clock */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup RCC_LSE_Config LSE Config 197 * @{ 198 */ 199 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 200 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 201 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock */ 202 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock */ 203 /** 204 * @} 205 */ 206 207 /** @defgroup RCC_HSI_Config HSI Config 208 * @{ 209 */ 210 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 212 213 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup RCC_HSI_Div HSI Div 219 * @{ 220 */ 221 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 222 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 223 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 224 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup RCC_LSI_Config LSI Config 230 * @{ 231 */ 232 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 233 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_CSI_Config CSI Config 239 * @{ 240 */ 241 #define RCC_CSI_OFF (0x00000000U) /*!< CSI clock deactivation */ 242 #define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ 243 244 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /*!< Default CSI calibration trimming value */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup RCC_HSI48_Config HSI48 Config 250 * @{ 251 */ 252 #define RCC_HSI48_OFF (0x00000000U) /*!< HSI48 clock deactivation */ 253 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup RCC_PLL1_Config RCC PLL1 Config 259 * @{ 260 */ 261 #define RCC_PLL_NONE (0x00000000U) 262 #define RCC_PLL_OFF (0x00000001U) 263 #define RCC_PLL_ON (0x00000002U) 264 /** 265 * @} 266 */ 267 268 /** @defgroup RCC_PLL1_Clock_Output RCC PLL1 Clock Output 269 * @{ 270 */ 271 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 272 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 273 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 274 /** 275 * @} 276 */ 277 278 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range 279 * @{ 280 */ 281 #define RCC_PLL1_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 282 #define RCC_PLL1_VCIRANGE_1 RCC_PLL1CFGR_PLL1RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 283 #define RCC_PLL1_VCIRANGE_2 RCC_PLL1CFGR_PLL1RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 284 #define RCC_PLL1_VCIRANGE_3 (RCC_PLL1CFGR_PLL1RGE_0 | RCC_PLL1CFGR_PLL1RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range 290 * @{ 291 */ 292 #define RCC_PLL1_VCORANGE_WIDE (0x00000000U) /*!< Clock range frequency between 192 and 836 MHz */ 293 #define RCC_PLL1_VCORANGE_MEDIUM RCC_PLL1CFGR_PLL1VCOSEL /*!< Clock range frequency between 150 and 420 MHz */ 294 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCC_PLL1_Clock_Source RCC PLL1 Clock Source 300 * @{ 301 */ 302 #define RCC_PLL1_SOURCE_NONE (0x00000000U) 303 #define RCC_PLL1_SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 304 #define RCC_PLL1_SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 305 #define RCC_PLL1_SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 306 /** 307 * @} 308 */ 309 310 311 /** @defgroup RCC_System_Clock_Type System Clock Type 312 * @{ 313 */ 314 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 315 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 316 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 317 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ 318 #define RCC_CLOCKTYPE_PCLK3 (0x00000010U) /*!< PCLK3 to configure */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup RCC_System_Clock_Source System Clock Source 324 * @{ 325 */ 326 #define RCC_SYSCLKSOURCE_HSI (0x00000000U) /*!< HSI selection as system clock */ 327 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI selection as system clock */ 328 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 329 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 335 * @{ 336 */ 337 #define RCC_SYSCLKSOURCE_STATUS_HSI (0x00000000U) /*!< HSI used as system clock */ 338 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI used as system clock */ 339 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 340 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 346 * @{ 347 */ 348 #define RCC_SYSCLK_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 349 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 350 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 351 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 352 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 353 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 354 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 355 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 356 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 362 * @{ 363 */ 364 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 365 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 366 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 367 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 368 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 369 /** 370 * @} 371 */ 372 373 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 374 * @{ 375 */ 376 #define RCC_RTC_HSE_NOCLOCK (0x00000000U) 377 #define RCC_RTC_HSE_DIV2 (0x00000200U) 378 #define RCC_RTC_HSE_DIV3 (0x00000300U) 379 #define RCC_RTC_HSE_DIV4 (0x00000400U) 380 #define RCC_RTC_HSE_DIV5 (0x00000500U) 381 #define RCC_RTC_HSE_DIV6 (0x00000600U) 382 #define RCC_RTC_HSE_DIV7 (0x00000700U) 383 #define RCC_RTC_HSE_DIV8 (0x00000800U) 384 #define RCC_RTC_HSE_DIV9 (0x00000900U) 385 #define RCC_RTC_HSE_DIV10 (0x00000A00U) 386 #define RCC_RTC_HSE_DIV11 (0x00000B00U) 387 #define RCC_RTC_HSE_DIV12 (0x00000C00U) 388 #define RCC_RTC_HSE_DIV13 (0x00000D00U) 389 #define RCC_RTC_HSE_DIV14 (0x00000E00U) 390 #define RCC_RTC_HSE_DIV15 (0x00000F00U) 391 #define RCC_RTC_HSE_DIV16 (0x00001000U) 392 #define RCC_RTC_HSE_DIV17 (0x00001100U) 393 #define RCC_RTC_HSE_DIV18 (0x00001200U) 394 #define RCC_RTC_HSE_DIV19 (0x00001300U) 395 #define RCC_RTC_HSE_DIV20 (0x00001400U) 396 #define RCC_RTC_HSE_DIV21 (0x00001500U) 397 #define RCC_RTC_HSE_DIV22 (0x00001600U) 398 #define RCC_RTC_HSE_DIV23 (0x00001700U) 399 #define RCC_RTC_HSE_DIV24 (0x00001800U) 400 #define RCC_RTC_HSE_DIV25 (0x00001900U) 401 #define RCC_RTC_HSE_DIV26 (0x00001A00U) 402 #define RCC_RTC_HSE_DIV27 (0x00001B00U) 403 #define RCC_RTC_HSE_DIV28 (0x00001C00U) 404 #define RCC_RTC_HSE_DIV29 (0x00001D00U) 405 #define RCC_RTC_HSE_DIV30 (0x00001E00U) 406 #define RCC_RTC_HSE_DIV31 (0x00001F00U) 407 #define RCC_RTC_HSE_DIV32 (0x00002000U) 408 #define RCC_RTC_HSE_DIV33 (0x00002100U) 409 #define RCC_RTC_HSE_DIV34 (0x00002200U) 410 #define RCC_RTC_HSE_DIV35 (0x00002300U) 411 #define RCC_RTC_HSE_DIV36 (0x00002400U) 412 #define RCC_RTC_HSE_DIV37 (0x00002500U) 413 #define RCC_RTC_HSE_DIV38 (0x00002600U) 414 #define RCC_RTC_HSE_DIV39 (0x00002700U) 415 #define RCC_RTC_HSE_DIV40 (0x00002800U) 416 #define RCC_RTC_HSE_DIV41 (0x00002900U) 417 #define RCC_RTC_HSE_DIV42 (0x00002A00U) 418 #define RCC_RTC_HSE_DIV43 (0x00002B00U) 419 #define RCC_RTC_HSE_DIV44 (0x00002C00U) 420 #define RCC_RTC_HSE_DIV45 (0x00002D00U) 421 #define RCC_RTC_HSE_DIV46 (0x00002E00U) 422 #define RCC_RTC_HSE_DIV47 (0x00002F00U) 423 #define RCC_RTC_HSE_DIV48 (0x00003000U) 424 #define RCC_RTC_HSE_DIV49 (0x00003100U) 425 #define RCC_RTC_HSE_DIV50 (0x00003200U) 426 #define RCC_RTC_HSE_DIV51 (0x00003300U) 427 #define RCC_RTC_HSE_DIV52 (0x00003400U) 428 #define RCC_RTC_HSE_DIV53 (0x00003500U) 429 #define RCC_RTC_HSE_DIV54 (0x00003600U) 430 #define RCC_RTC_HSE_DIV55 (0x00003700U) 431 #define RCC_RTC_HSE_DIV56 (0x00003800U) 432 #define RCC_RTC_HSE_DIV57 (0x00003900U) 433 #define RCC_RTC_HSE_DIV58 (0x00003A00U) 434 #define RCC_RTC_HSE_DIV59 (0x00003B00U) 435 #define RCC_RTC_HSE_DIV60 (0x00003C00U) 436 #define RCC_RTC_HSE_DIV61 (0x00003D00U) 437 #define RCC_RTC_HSE_DIV62 (0x00003E00U) 438 #define RCC_RTC_HSE_DIV63 (0x00003F00U) 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 444 * @{ 445 */ 446 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock used as RTC clock source */ 447 #define RCC_RTCCLKSOURCE_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock source */ 448 #define RCC_RTCCLKSOURCE_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock source */ 449 #define RCC_RTCCLKSOURCE_HSE_DIVx (0x00000300U) /*!< HSE oscillator clock divided by X used as RTC clock source */ 450 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) 451 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) 452 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) 453 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) 454 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) 455 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) 456 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) 457 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) 458 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) 459 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) 460 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) 461 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) 462 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) 463 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) 464 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) 465 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) 466 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) 467 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) 468 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) 469 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) 470 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) 471 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) 472 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) 473 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) 474 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) 475 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) 476 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) 477 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) 478 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) 479 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) 480 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) 481 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) 482 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) 483 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) 484 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) 485 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) 486 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) 487 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) 488 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) 489 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) 490 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) 491 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) 492 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) 493 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) 494 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) 495 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) 496 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) 497 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) 498 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) 499 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) 500 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) 501 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) 502 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) 503 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) 504 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) 505 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) 506 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) 507 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) 508 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) 509 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) 510 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) 511 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCC_MCO_Index MCO Index 517 * @{ 518 */ 519 #define RCC_MCO1 (0x00000000U) 520 #define RCC_MCO2 (0x00000001U) 521 /** 522 * @} 523 */ 524 525 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 526 * @{ 527 */ 528 #define RCC_MCO1SOURCE_HSI (0x00000000U) 529 #define RCC_MCO1SOURCE_LSE RCC_CFGR1_MCO1SEL_0 530 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCO1SEL_1 531 #define RCC_MCO1SOURCE_PLL1Q ((uint32_t)RCC_CFGR1_MCO1SEL_0 | RCC_CFGR1_MCO1SEL_1) 532 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCO1SEL_2 533 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 539 * @{ 540 */ 541 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) 542 #define RCC_MCO2SOURCE_PLL2P RCC_CFGR1_MCO2SEL_0 543 #define RCC_MCO2SOURCE_HSE RCC_CFGR1_MCO2SEL_1 544 #define RCC_MCO2SOURCE_PLL1P ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_1) 545 #define RCC_MCO2SOURCE_CSI RCC_CFGR1_MCO2SEL_2 546 #define RCC_MCO2SOURCE_LSI ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_2) 547 548 /** 549 * @} 550 */ 551 552 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 553 * @{ 554 */ 555 #define RCC_MCODIV_1 RCC_CFGR1_MCO1PRE_0 556 #define RCC_MCODIV_2 RCC_CFGR1_MCO1PRE_1 557 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) 558 #define RCC_MCODIV_4 RCC_CFGR1_MCO1PRE_2 559 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2) 560 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 561 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 562 #define RCC_MCODIV_8 RCC_CFGR1_MCO1PRE_3 563 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3) 564 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 565 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 566 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 567 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 568 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 569 #define RCC_MCODIV_15 RCC_CFGR1_MCO1PRE 570 /** 571 * @} 572 */ 573 574 /** @defgroup RCC_Interrupt Interrupts 575 * @{ 576 */ 577 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 578 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 579 #define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt flag */ 580 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 581 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 582 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 583 #define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 584 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 585 #if defined(RCC_CR_PLL3ON) 586 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 587 #endif /* RCC_CR_PLL3ON */ 588 #define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */ 589 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCC_Flag Flags 595 * Elements values convention: XXXYYYYYb 596 * - YYYYY : Flag position in the register 597 * - XXX : Register index 598 * - 001: CR register 599 * - 010: BDCR register 600 * - 011: RSR register 601 * @{ 602 */ 603 /* Flags in the CR register */ 604 #define RCC_FLAG_CSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos)) /*!< CSI Ready flag */ 605 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 606 #define RCC_FLAG_HSIDIVF ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos)) /*!< HSI divider flag */ 607 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 608 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL1 Ready flag */ 609 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 610 #if defined(RCC_CR_PLL3ON) 611 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 612 #endif /* RCC_CR_PLL3ON */ 613 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 614 615 /* Flags in the BDCR register */ 616 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 617 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 618 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 619 620 /* Flags in the RSR register */ 621 #define RCC_FLAG_RMVF ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_RMVF_Pos)) /*!< Remove reset flag */ 622 #define RCC_FLAG_PINRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos)) /*!< PIN reset flag */ 623 #define RCC_FLAG_BORRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos)) /*!< BOR reset flag */ 624 #define RCC_FLAG_SFTRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 625 #define RCC_FLAG_IWDGRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 626 #define RCC_FLAG_WWDGRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 627 #define RCC_FLAG_LPWRRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 628 629 /** 630 * @} 631 */ 632 633 /** @defgroup RCC_Reset_Flag Reset Flag 634 * @{ 635 */ 636 #define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ 637 #define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 638 #define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ 639 #define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 640 #define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ 641 #define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ 642 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | RCC_RESET_FLAG_SW | \ 643 RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | RCC_RESET_FLAG_LPWR) 644 /** 645 * @} 646 */ 647 648 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 649 * @{ 650 */ 651 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 652 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 653 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 654 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 660 * @{ 661 */ 662 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) /*!< HSI selection after wake-up from STOP */ 663 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection after wake-up from STOP */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 669 * @{ 670 */ 671 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) /*!< HSI kernel clock selection after wake-up from STOP */ 672 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI kernel clock selection after wake-up from STOP */ 673 674 /** 675 * @} 676 */ 677 678 #if defined(RCC_SECCFGR_HSISEC) 679 /** @defgroup RCC_items RCC items 680 * @brief RCC items to configure attributes on 681 * @{ 682 */ 683 #define RCC_HSI RCC_SECCFGR_HSISEC 684 #define RCC_HSE RCC_SECCFGR_HSESEC 685 #define RCC_CSI RCC_SECCFGR_CSISEC 686 #define RCC_LSI RCC_SECCFGR_LSISEC 687 #define RCC_LSE RCC_SECCFGR_LSESEC 688 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 689 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 690 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 691 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 692 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 693 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 694 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 695 #define RCC_CKPERSEL RCC_SECCFGR_CKPERSELSEC 696 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_CSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 697 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 698 RCC_PLL3|RCC_CKPERSEL|RCC_RMVF) 699 /** 700 * @} 701 */ 702 #endif /* RCC_SECCFGR_HSISEC */ 703 704 /** @defgroup RCC_attributes RCC attributes 705 * @brief RCC privilege/non-privilege and secure/non-secure attributes 706 * @{ 707 */ 708 #if defined(RCC_PRIVCFGR_NSPRIV) 709 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 710 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 711 #else 712 #define RCC_PRIV 0x00000001U /*!< Privilege attribute item */ 713 #define RCC_NPRIV 0x00000002U /*!< Non-privilege attribute item */ 714 #endif /* RCC_PRIVCFGR_NSPRIV */ 715 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 716 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 717 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 718 #endif /* __ARM_FEATURE_CMSE */ 719 /** 720 * @} 721 */ 722 723 /** 724 * @} 725 */ 726 727 /* Exported macros -----------------------------------------------------------*/ 728 729 /** @defgroup RCC_Exported_Macros RCC Exported Macros 730 * @{ 731 */ 732 733 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 734 * @brief Enable or disable the AHB1 peripheral clock. 735 * @note After reset, the peripheral clock (used for registers read/write access) 736 * is disabled and the application software has to enable this clock before 737 * using it. 738 * @{ 739 */ 740 741 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 742 __IO uint32_t tmpreg; \ 743 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 744 /* Delay after an RCC peripheral clock enabling */ \ 745 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 746 UNUSED(tmpreg); \ 747 } while(0) 748 749 #define __HAL_RCC_GPDMA2_CLK_ENABLE() do { \ 750 __IO uint32_t tmpreg; \ 751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 752 /* Delay after an RCC peripheral clock enabling */ \ 753 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 754 UNUSED(tmpreg); \ 755 } while(0) 756 757 #if defined(CORDIC) 758 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 759 __IO uint32_t tmpreg; \ 760 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 761 /* Delay after an RCC peripheral clock enabling */ \ 762 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 763 UNUSED(tmpreg); \ 764 } while(0) 765 #endif /* CORDIC */ 766 767 #if defined(FMAC) 768 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 769 __IO uint32_t tmpreg; \ 770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 771 /* Delay after an RCC peripheral clock enabling */ \ 772 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 773 UNUSED(tmpreg); \ 774 } while(0) 775 #endif /* FMAC */ 776 777 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 778 __IO uint32_t tmpreg; \ 779 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 780 /* Delay after an RCC peripheral clock enabling */ \ 781 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 782 UNUSED(tmpreg); \ 783 } while(0) 784 785 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 786 __IO uint32_t tmpreg; \ 787 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 788 /* Delay after an RCC peripheral clock enabling */ \ 789 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 790 UNUSED(tmpreg); \ 791 } while(0) 792 793 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 794 __IO uint32_t tmpreg; \ 795 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 796 /* Delay after an RCC peripheral clock enabling */ \ 797 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 798 UNUSED(tmpreg); \ 799 } while(0) 800 801 #if defined(ETH) 802 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 803 __IO uint32_t tmpreg; \ 804 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 805 /* Delay after an RCC peripheral clock enabling */ \ 806 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 807 UNUSED(tmpreg); \ 808 } while(0) 809 810 #define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ 811 __IO uint32_t tmpreg; \ 812 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 813 /* Delay after an RCC peripheral clock enabling */ \ 814 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 815 UNUSED(tmpreg); \ 816 } while(0) 817 818 #define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ 819 __IO uint32_t tmpreg; \ 820 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 821 /* Delay after an RCC peripheral clock enabling */ \ 822 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 823 UNUSED(tmpreg); \ 824 } while(0) 825 #endif /*ETH*/ 826 827 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 828 __IO uint32_t tmpreg; \ 829 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 830 /* Delay after an RCC peripheral clock enabling */ \ 831 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 832 UNUSED(tmpreg); \ 833 } while(0) 834 835 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 836 __IO uint32_t tmpreg; \ 837 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 838 /* Delay after an RCC peripheral clock enabling */ \ 839 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 840 UNUSED(tmpreg); \ 841 } while(0) 842 843 #if defined(DCACHE1) 844 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 845 __IO uint32_t tmpreg; \ 846 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 847 /* Delay after an RCC peripheral clock enabling */ \ 848 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 849 UNUSED(tmpreg); \ 850 } while(0) 851 #endif /* DCACHE1 */ 852 853 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 854 __IO uint32_t tmpreg; \ 855 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 856 /* Delay after an RCC peripheral clock enabling */ \ 857 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 858 UNUSED(tmpreg); \ 859 } while(0) 860 861 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 862 863 #define __HAL_RCC_GPDMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) 864 865 #if defined(CORDIC) 866 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 867 #endif /* CORDIC */ 868 869 #if defined(FMAC) 870 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 871 #endif /* FMAC */ 872 873 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) 874 875 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 876 877 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 878 879 #if defined(ETH) 880 #define __HAL_RCC_ETH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) 881 882 #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) 883 884 #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) 885 #endif /*ETH*/ 886 887 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) 888 889 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) 890 891 #if defined(DCACHE1) 892 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 893 #endif /* DCACHE1 */ 894 895 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 896 /** 897 * @} 898 */ 899 900 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 901 * @brief Enable or disable the AHB2 peripheral clock. 902 * @note After reset, the peripheral clock (used for registers read/write access) 903 * is disabled and the application software has to enable this clock before 904 * using it. 905 * @{ 906 */ 907 908 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 909 __IO uint32_t tmpreg; \ 910 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 911 /* Delay after an RCC peripheral clock enabling */ \ 912 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 913 UNUSED(tmpreg); \ 914 } while(0) 915 916 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 917 __IO uint32_t tmpreg; \ 918 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 919 /* Delay after an RCC peripheral clock enabling */ \ 920 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 921 UNUSED(tmpreg); \ 922 } while(0) 923 924 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 925 __IO uint32_t tmpreg; \ 926 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 927 /* Delay after an RCC peripheral clock enabling */ \ 928 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 929 UNUSED(tmpreg); \ 930 } while(0) 931 932 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 933 __IO uint32_t tmpreg; \ 934 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 935 /* Delay after an RCC peripheral clock enabling */ \ 936 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 937 UNUSED(tmpreg); \ 938 } while(0) 939 940 #if defined(GPIOE) 941 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 942 __IO uint32_t tmpreg; \ 943 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 944 /* Delay after an RCC peripheral clock enabling */ \ 945 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 946 UNUSED(tmpreg); \ 947 } while(0) 948 #endif /* GPIOE */ 949 950 #if defined(GPIOF) 951 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 952 __IO uint32_t tmpreg; \ 953 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 954 /* Delay after an RCC peripheral clock enabling */ \ 955 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 956 UNUSED(tmpreg); \ 957 } while(0) 958 #endif /* GPIOF */ 959 960 #if defined(GPIOG) 961 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 962 __IO uint32_t tmpreg; \ 963 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 964 /* Delay after an RCC peripheral clock enabling */ \ 965 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 966 UNUSED(tmpreg); \ 967 } while(0) 968 #endif /* GPIOG */ 969 970 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 971 __IO uint32_t tmpreg; \ 972 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 973 /* Delay after an RCC peripheral clock enabling */ \ 974 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 975 UNUSED(tmpreg); \ 976 } while(0) 977 978 #if defined(GPIOI) 979 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 980 __IO uint32_t tmpreg; \ 981 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 982 /* Delay after an RCC peripheral clock enabling */ \ 983 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 984 UNUSED(tmpreg); \ 985 } while(0) 986 #endif /* GPIOI */ 987 988 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 989 __IO uint32_t tmpreg; \ 990 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 991 /* Delay after an RCC peripheral clock enabling */ \ 992 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 993 UNUSED(tmpreg); \ 994 } while(0) 995 996 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 997 __IO uint32_t tmpreg; \ 998 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 999 /* Delay after an RCC peripheral clock enabling */ \ 1000 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 1001 UNUSED(tmpreg); \ 1002 } while(0) 1003 1004 #if defined(DCMI) 1005 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 1006 __IO uint32_t tmpreg; \ 1007 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1008 /* Delay after an RCC peripheral clock enabling */ \ 1009 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1010 UNUSED(tmpreg); \ 1011 } while(0) 1012 1013 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility */ 1014 #endif /* DCMI */ 1015 1016 #if defined(AES) 1017 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 1018 __IO uint32_t tmpreg; \ 1019 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1020 /* Delay after an RCC peripheral clock enabling */ \ 1021 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1022 UNUSED(tmpreg); \ 1023 } while(0) 1024 #endif /* AES */ 1025 1026 #if defined(HASH) 1027 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1028 __IO uint32_t tmpreg; \ 1029 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1030 /* Delay after an RCC peripheral clock enabling */ \ 1031 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1032 UNUSED(tmpreg); \ 1033 } while(0) 1034 #endif /* HASH */ 1035 1036 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1037 __IO uint32_t tmpreg; \ 1038 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1039 /* Delay after an RCC peripheral clock enabling */ \ 1040 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1041 UNUSED(tmpreg); \ 1042 } while(0) 1043 1044 #if defined(PKA) 1045 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1046 __IO uint32_t tmpreg; \ 1047 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1048 /* Delay after an RCC peripheral clock enabling */ \ 1049 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1050 UNUSED(tmpreg); \ 1051 } while(0) 1052 #endif /* PKA */ 1053 1054 #if defined(SAES) 1055 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1056 __IO uint32_t tmpreg; \ 1057 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1058 /* Delay after an RCC peripheral clock enabling */ \ 1059 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1060 UNUSED(tmpreg); \ 1061 } while(0) 1062 #endif /* SAES */ 1063 1064 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 1065 __IO uint32_t tmpreg; \ 1066 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1067 /* Delay after an RCC peripheral clock enabling */ \ 1068 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1069 UNUSED(tmpreg); \ 1070 } while(0) 1071 #if defined(SRAM3_BASE) 1072 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 1073 __IO uint32_t tmpreg; \ 1074 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1075 /* Delay after an RCC peripheral clock enabling */ \ 1076 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1077 UNUSED(tmpreg); \ 1078 } while(0) 1079 #endif /* SRAM3_BASE */ 1080 1081 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 1082 1083 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 1084 1085 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 1086 1087 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 1088 1089 #if defined(GPIOE) 1090 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 1091 #endif /* GPIOE */ 1092 1093 #if defined(GPIOF) 1094 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 1095 #endif /* GPIOF */ 1096 1097 #if defined(GPIOG) 1098 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 1099 #endif /* GPIOG */ 1100 1101 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 1102 1103 #if defined(GPIOI) 1104 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 1105 #endif /* GPIOI */ 1106 1107 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 1108 1109 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) 1110 1111 #if defined(DCMI) 1112 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) 1113 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ 1114 #endif /* DCMI */ 1115 1116 #if defined(AES) 1117 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 1118 #endif /* AES */ 1119 1120 #if defined(HASH) 1121 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 1122 #endif /* HASH */ 1123 1124 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 1125 1126 #if defined(PKA) 1127 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 1128 #endif /* PKA */ 1129 1130 #if defined(SAES) 1131 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) 1132 #endif /* SAES */ 1133 1134 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) 1135 1136 #if defined(SRAM3_BASE) 1137 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) 1138 #endif /* SRAM3_BASE */ 1139 /** 1140 * @} 1141 */ 1142 1143 /** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable 1144 * @brief Enable or disable the AHB4 peripheral clock. 1145 * @note After reset, the peripheral clock (used for registers read/write access) 1146 * is disabled and the application software has to enable this clock before 1147 * using it. 1148 * @{ 1149 */ 1150 1151 #if defined(OTFDEC1) 1152 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 1153 __IO uint32_t tmpreg; \ 1154 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1155 /* Delay after an RCC peripheral clock enabling */ \ 1156 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1157 UNUSED(tmpreg); \ 1158 } while(0) 1159 #endif /* OTFDEC1 */ 1160 1161 #if defined(SDMMC1) 1162 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1163 __IO uint32_t tmpreg; \ 1164 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1165 /* Delay after an RCC peripheral clock enabling */ \ 1166 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1167 UNUSED(tmpreg); \ 1168 } while(0) 1169 #endif /* SDMMC1 */ 1170 1171 #if defined(SDMMC2) 1172 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1173 __IO uint32_t tmpreg; \ 1174 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1175 /* Delay after an RCC peripheral clock enabling */ \ 1176 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1177 UNUSED(tmpreg); \ 1178 } while(0) 1179 #endif /* SDMMC2 */ 1180 1181 #if defined(FMC_BASE) 1182 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1183 __IO uint32_t tmpreg; \ 1184 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1185 /* Delay after an RCC peripheral clock enabling */ \ 1186 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1187 UNUSED(tmpreg); \ 1188 } while(0) 1189 #endif /* FMC_BASE */ 1190 1191 #if defined(OCTOSPI1) 1192 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1193 __IO uint32_t tmpreg; \ 1194 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1195 /* Delay after an RCC peripheral clock enabling */ \ 1196 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1197 UNUSED(tmpreg); \ 1198 } while(0) 1199 #endif /* OCTOSPI1 */ 1200 1201 #if defined(OTFDEC1) 1202 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) 1203 #endif /* OTFDEC1 */ 1204 1205 #if defined(SDMMC1) 1206 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) 1207 #endif /* SDMMC1 */ 1208 1209 #if defined(SDMMC2) 1210 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) 1211 #endif /* SDMMC2 */ 1212 1213 #if defined(FMC_BASE) 1214 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) 1215 #endif /* FMC_BASE */ 1216 1217 #if defined(OCTOSPI1) 1218 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) 1219 #endif /* OCTOSPI1 */ 1220 1221 /** 1222 * @} 1223 */ 1224 1225 1226 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1227 * @brief Enable or disable the APB1 peripheral clock. 1228 * @note After reset, the peripheral clock (used for registers read/write access) 1229 * is disabled and the application software has to enable this clock before 1230 * using it. 1231 * @{ 1232 */ 1233 1234 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1235 __IO uint32_t tmpreg; \ 1236 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1237 /* Delay after an RCC peripheral clock enabling */ \ 1238 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1239 UNUSED(tmpreg); \ 1240 } while(0) 1241 1242 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1243 __IO uint32_t tmpreg; \ 1244 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1245 /* Delay after an RCC peripheral clock enabling */ \ 1246 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1247 UNUSED(tmpreg); \ 1248 } while(0) 1249 1250 #if defined(TIM4) 1251 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1252 __IO uint32_t tmpreg; \ 1253 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1254 /* Delay after an RCC peripheral clock enabling */ \ 1255 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1256 UNUSED(tmpreg); \ 1257 } while(0) 1258 #endif /* TIM4 */ 1259 1260 #if defined(TIM5) 1261 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1262 __IO uint32_t tmpreg; \ 1263 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1264 /* Delay after an RCC peripheral clock enabling */ \ 1265 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1266 UNUSED(tmpreg); \ 1267 } while(0) 1268 #endif /* TIM5 */ 1269 1270 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1271 __IO uint32_t tmpreg; \ 1272 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1273 /* Delay after an RCC peripheral clock enabling */ \ 1274 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1275 UNUSED(tmpreg); \ 1276 } while(0) 1277 1278 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1279 __IO uint32_t tmpreg; \ 1280 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1281 /* Delay after an RCC peripheral clock enabling */ \ 1282 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1283 UNUSED(tmpreg); \ 1284 } while(0) 1285 1286 #if defined(TIM12) 1287 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1288 __IO uint32_t tmpreg; \ 1289 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1290 /* Delay after an RCC peripheral clock enabling */ \ 1291 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1292 UNUSED(tmpreg); \ 1293 } while(0) 1294 1295 #endif /* TIM12 */ 1296 1297 #if defined(TIM13) 1298 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1299 __IO uint32_t tmpreg; \ 1300 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1301 /* Delay after an RCC peripheral clock enabling */ \ 1302 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1303 UNUSED(tmpreg); \ 1304 } while(0) 1305 #endif /* TIM13 */ 1306 1307 #if defined(TIM14) 1308 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1309 __IO uint32_t tmpreg; \ 1310 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1311 /* Delay after an RCC peripheral clock enabling */ \ 1312 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1313 UNUSED(tmpreg); \ 1314 } while(0) 1315 #endif /* TIM14 */ 1316 1317 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1318 __IO uint32_t tmpreg; \ 1319 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1320 /* Delay after an RCC peripheral clock enabling */ \ 1321 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1322 UNUSED(tmpreg); \ 1323 } while(0) 1324 1325 #if defined(OPAMP1) 1326 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1327 __IO uint32_t tmpreg; \ 1328 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1329 /* Delay after an RCC peripheral clock enabling */ \ 1330 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1331 UNUSED(tmpreg); \ 1332 } while(0) 1333 #endif /* OPAMP1 */ 1334 1335 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1336 __IO uint32_t tmpreg; \ 1337 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1338 /* Delay after an RCC peripheral clock enabling */ \ 1339 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1340 UNUSED(tmpreg); \ 1341 } while(0) 1342 1343 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1344 __IO uint32_t tmpreg; \ 1345 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1346 /* Delay after an RCC peripheral clock enabling */ \ 1347 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1348 UNUSED(tmpreg); \ 1349 } while(0) 1350 1351 #if defined(COMP1) 1352 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1353 __IO uint32_t tmpreg; \ 1354 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1355 /* Delay after an RCC peripheral clock enabling */ \ 1356 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1357 UNUSED(tmpreg); \ 1358 } while(0) 1359 #endif /* COMP1 */ 1360 1361 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1362 __IO uint32_t tmpreg; \ 1363 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1364 /* Delay after an RCC peripheral clock enabling */ \ 1365 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1366 UNUSED(tmpreg); \ 1367 } while(0) 1368 1369 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1370 __IO uint32_t tmpreg; \ 1371 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1372 /* Delay after an RCC peripheral clock enabling */ \ 1373 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1374 UNUSED(tmpreg); \ 1375 } while(0) 1376 1377 #if defined(UART4) 1378 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1379 __IO uint32_t tmpreg; \ 1380 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1381 /* Delay after an RCC peripheral clock enabling */ \ 1382 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1383 UNUSED(tmpreg); \ 1384 } while(0) 1385 #endif /* UART4 */ 1386 1387 #if defined(UART5) 1388 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1389 __IO uint32_t tmpreg; \ 1390 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1391 /* Delay after an RCC peripheral clock enabling */ \ 1392 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1393 UNUSED(tmpreg); \ 1394 } while(0) 1395 #endif /* UART5 */ 1396 1397 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1398 __IO uint32_t tmpreg; \ 1399 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1400 /* Delay after an RCC peripheral clock enabling */ \ 1401 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1402 UNUSED(tmpreg); \ 1403 } while(0) 1404 1405 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1406 __IO uint32_t tmpreg; \ 1407 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1408 /* Delay after an RCC peripheral clock enabling */ \ 1409 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1410 UNUSED(tmpreg); \ 1411 } while(0) 1412 1413 #define __HAL_RCC_I3C1_CLK_ENABLE() do { \ 1414 __IO uint32_t tmpreg; \ 1415 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1416 /* Delay after an RCC peripheral clock enabling */ \ 1417 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1418 UNUSED(tmpreg); \ 1419 } while(0) 1420 1421 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1422 __IO uint32_t tmpreg; \ 1423 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1424 /* Delay after an RCC peripheral clock enabling */ \ 1425 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1426 UNUSED(tmpreg); \ 1427 } while(0) 1428 1429 #if defined(USART6) 1430 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1431 __IO uint32_t tmpreg; \ 1432 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1433 /* Delay after an RCC peripheral clock enabling */ \ 1434 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1435 UNUSED(tmpreg); \ 1436 } while(0) 1437 #endif /* USART6 */ 1438 1439 #if defined(USART10) 1440 #define __HAL_RCC_USART10_CLK_ENABLE() do { \ 1441 __IO uint32_t tmpreg; \ 1442 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1443 /* Delay after an RCC peripheral clock enabling */ \ 1444 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1445 UNUSED(tmpreg); \ 1446 } while(0) 1447 #endif /* USART10 */ 1448 1449 #if defined(USART11) 1450 #define __HAL_RCC_USART11_CLK_ENABLE() do { \ 1451 __IO uint32_t tmpreg; \ 1452 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1453 /* Delay after an RCC peripheral clock enabling */ \ 1454 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1455 UNUSED(tmpreg); \ 1456 } while(0) 1457 #endif /* USART11 */ 1458 1459 #if defined(CEC) 1460 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1461 __IO uint32_t tmpreg; \ 1462 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1463 /* Delay after an RCC peripheral clock enabling */ \ 1464 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1465 UNUSED(tmpreg); \ 1466 } while(0) 1467 #endif /* CEC */ 1468 1469 #if defined(UART7) 1470 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1471 __IO uint32_t tmpreg; \ 1472 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1473 /* Delay after an RCC peripheral clock enabling */ \ 1474 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1475 UNUSED(tmpreg); \ 1476 } while(0) 1477 #endif /* UART7 */ 1478 1479 #if defined(UART8) 1480 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1481 __IO uint32_t tmpreg; \ 1482 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1483 /* Delay after an RCC peripheral clock enabling */ \ 1484 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1485 UNUSED(tmpreg); \ 1486 } while(0) 1487 #endif /* UART8 */ 1488 1489 #if defined(UART9) 1490 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 1491 __IO uint32_t tmpreg; \ 1492 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1493 /* Delay after an RCC peripheral clock enabling */ \ 1494 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1495 UNUSED(tmpreg); \ 1496 } while(0) 1497 #endif /* UART9 */ 1498 1499 #if defined(UART12) 1500 #define __HAL_RCC_UART12_CLK_ENABLE() do { \ 1501 __IO uint32_t tmpreg; \ 1502 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1503 /* Delay after an RCC peripheral clock enabling */ \ 1504 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1505 UNUSED(tmpreg); \ 1506 } while(0) 1507 #endif /* UART12 */ 1508 1509 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1510 __IO uint32_t tmpreg; \ 1511 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1512 /* Delay after an RCC peripheral clock enabling */ \ 1513 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1514 UNUSED(tmpreg); \ 1515 } while(0) 1516 1517 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1518 __IO uint32_t tmpreg; \ 1519 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1520 /* Delay after an RCC peripheral clock enabling */ \ 1521 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1522 UNUSED(tmpreg); \ 1523 } while(0) 1524 1525 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 1526 __IO uint32_t tmpreg; \ 1527 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ 1528 /* Delay after an RCC peripheral clock enabling */ \ 1529 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ 1530 UNUSED(tmpreg); \ 1531 } while(0) 1532 1533 #if defined(UCPD1) 1534 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1535 __IO uint32_t tmpreg; \ 1536 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1537 /* Delay after an RCC peripheral clock enabling */ \ 1538 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1539 UNUSED(tmpreg); \ 1540 } while(0) 1541 #endif /* UCPD1 */ 1542 1543 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) 1544 1545 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) 1546 1547 #if defined(TIM4) 1548 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) 1549 #endif /* TIM4 */ 1550 1551 #if defined(TIM5) 1552 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) 1553 #endif /* TIM5 */ 1554 1555 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) 1556 1557 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) 1558 1559 #if defined(TIM12) 1560 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) 1561 #endif /* TIM12 */ 1562 1563 #if defined(TIM13) 1564 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) 1565 #endif /* TIM13 */ 1566 1567 #if defined(TIM14) 1568 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) 1569 #endif /* TIM14 */ 1570 1571 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) 1572 1573 #if defined(OPAMP1) 1574 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) 1575 #endif /* OPAMP1 */ 1576 1577 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) 1578 1579 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) 1580 1581 #if defined(COMP1) 1582 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) 1583 #endif /* COMP1 */ 1584 1585 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) 1586 1587 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) 1588 1589 #if defined(UART4) 1590 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) 1591 #endif /* UART4 */ 1592 1593 #if defined(UART5) 1594 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) 1595 #endif /* UART5 */ 1596 1597 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) 1598 1599 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) 1600 1601 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) 1602 1603 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) 1604 1605 #if defined(USART6) 1606 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) 1607 #endif /* USART6 */ 1608 1609 #if defined(USART10) 1610 #define __HAL_RCC_USART10_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) 1611 #endif /* USART10 */ 1612 1613 #if defined(USART11) 1614 #define __HAL_RCC_USART11_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) 1615 #endif /* USART11 */ 1616 1617 #if defined(CEC) 1618 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) 1619 #endif /* CEC */ 1620 1621 #if defined(UART7) 1622 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) 1623 #endif /* UART7 */ 1624 1625 #if defined(UART8) 1626 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) 1627 #endif /* UART8 */ 1628 1629 1630 #if defined(UART9) 1631 #define __HAL_RCC_UART9_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) 1632 #endif /* UART9 */ 1633 1634 #if defined(UART12) 1635 #define __HAL_RCC_UART12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) 1636 #endif /* UART12 */ 1637 1638 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR , RCC_APB1HENR_DTSEN) 1639 1640 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) 1641 1642 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) 1643 1644 #if defined(UCPD1) 1645 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) 1646 #endif /* UCPD1 */ 1647 1648 /** 1649 * @} 1650 */ 1651 1652 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1653 * @brief Enable or disable the APB2 peripheral clock. 1654 * @note After reset, the peripheral clock (used for registers read/write access) 1655 * is disabled and the application software has to enable this clock before 1656 * using it. 1657 * @{ 1658 */ 1659 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1660 __IO uint32_t tmpreg; \ 1661 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1662 /* Delay after an RCC peripheral clock enabling */ \ 1663 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1664 UNUSED(tmpreg); \ 1665 } while(0) 1666 1667 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1668 __IO uint32_t tmpreg; \ 1669 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1670 /* Delay after an RCC peripheral clock enabling */ \ 1671 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1672 UNUSED(tmpreg); \ 1673 } while(0) 1674 1675 #if defined(TIM8) 1676 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1677 __IO uint32_t tmpreg; \ 1678 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1679 /* Delay after an RCC peripheral clock enabling */ \ 1680 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1681 UNUSED(tmpreg); \ 1682 } while(0) 1683 #endif /* TIM8 */ 1684 1685 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1686 __IO uint32_t tmpreg; \ 1687 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1688 /* Delay after an RCC peripheral clock enabling */ \ 1689 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1690 UNUSED(tmpreg); \ 1691 } while(0) 1692 1693 #if defined(TIM15) 1694 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1695 __IO uint32_t tmpreg; \ 1696 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1697 /* Delay after an RCC peripheral clock enabling */ \ 1698 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1699 UNUSED(tmpreg); \ 1700 } while(0) 1701 #endif /* TIM15 */ 1702 1703 #if defined(TIM16) 1704 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1705 __IO uint32_t tmpreg; \ 1706 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1707 /* Delay after an RCC peripheral clock enabling */ \ 1708 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1709 UNUSED(tmpreg); \ 1710 } while(0) 1711 #endif /* TIM16 */ 1712 1713 #if defined(TIM17) 1714 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1715 __IO uint32_t tmpreg; \ 1716 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1717 /* Delay after an RCC peripheral clock enabling */ \ 1718 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1719 UNUSED(tmpreg); \ 1720 } while(0) 1721 #endif /* TIM17 */ 1722 1723 #if defined(SPI4) 1724 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1725 __IO uint32_t tmpreg; \ 1726 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1727 /* Delay after an RCC peripheral clock enabling */ \ 1728 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1729 UNUSED(tmpreg); \ 1730 } while(0) 1731 #endif /* SPI4 */ 1732 1733 #if defined(SPI6) 1734 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1735 __IO uint32_t tmpreg; \ 1736 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1737 /* Delay after an RCC peripheral clock enabling */ \ 1738 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1739 UNUSED(tmpreg); \ 1740 } while(0) 1741 #endif /* SPI6 */ 1742 1743 #if defined(SAI1) 1744 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1745 __IO uint32_t tmpreg; \ 1746 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1747 /* Delay after an RCC peripheral clock enabling */ \ 1748 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1749 UNUSED(tmpreg); \ 1750 } while(0) 1751 #endif /* SAI1 */ 1752 1753 #if defined(SAI2) 1754 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1755 __IO uint32_t tmpreg; \ 1756 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1757 /* Delay after an RCC peripheral clock enabling */ \ 1758 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1759 UNUSED(tmpreg); \ 1760 } while(0) 1761 #endif /* SAI2 */ 1762 1763 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1764 __IO uint32_t tmpreg; \ 1765 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1766 /* Delay after an RCC peripheral clock enabling */ \ 1767 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1768 UNUSED(tmpreg); \ 1769 } while(0) 1770 1771 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1772 1773 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1774 1775 #if defined(TIM8) 1776 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1777 #endif /* TIM8 */ 1778 1779 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1780 1781 #if defined(TIM15) 1782 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1783 #endif /* TIM15 */ 1784 1785 #if defined(TIM16) 1786 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1787 #endif /* TIM16 */ 1788 1789 #if defined(TIM17) 1790 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1791 #endif /* TIM17 */ 1792 1793 #if defined(SPI4) 1794 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) 1795 #endif /* SPI4 */ 1796 1797 #if defined(SPI6) 1798 #define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) 1799 #endif /* SPI6 */ 1800 1801 #if defined(SAI1) 1802 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1803 #endif /* SAI1 */ 1804 1805 #if defined(SAI2) 1806 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1807 #endif /* SAI2 */ 1808 1809 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) 1810 1811 /** 1812 * @} 1813 */ 1814 1815 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1816 * @brief Enable or disable the APB3 peripheral clock. 1817 * @note After reset, the peripheral clock (used for registers read/write access) 1818 * is disabled and the application software has to enable this clock before 1819 * using it. 1820 * @{ 1821 */ 1822 #define __HAL_RCC_SBS_CLK_ENABLE() do { \ 1823 __IO uint32_t tmpreg; \ 1824 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1825 /* Delay after an RCC peripheral clock enabling */ \ 1826 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1827 UNUSED(tmpreg); \ 1828 } while(0) 1829 1830 #if defined(SPI5) 1831 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1832 __IO uint32_t tmpreg; \ 1833 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1834 /* Delay after an RCC peripheral clock enabling */ \ 1835 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1836 UNUSED(tmpreg); \ 1837 } while(0) 1838 #endif /* SPI5 */ 1839 1840 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1841 __IO uint32_t tmpreg; \ 1842 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1843 /* Delay after an RCC peripheral clock enabling */ \ 1844 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1845 UNUSED(tmpreg); \ 1846 } while(0) 1847 1848 #if defined(I2C3) 1849 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1850 __IO uint32_t tmpreg; \ 1851 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1852 /* Delay after an RCC peripheral clock enabling */ \ 1853 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1854 UNUSED(tmpreg); \ 1855 } while(0) 1856 #endif /* I2C3 */ 1857 1858 #if defined(I2C4) 1859 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1860 __IO uint32_t tmpreg; \ 1861 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1862 /* Delay after an RCC peripheral clock enabling */ \ 1863 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1864 UNUSED(tmpreg); \ 1865 } while(0) 1866 #endif /* I2C4 */ 1867 1868 #if defined(I3C2) 1869 #define __HAL_RCC_I3C2_CLK_ENABLE() do { \ 1870 __IO uint32_t tmpreg; \ 1871 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1872 /* Delay after an RCC peripheral clock enabling */ \ 1873 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1874 UNUSED(tmpreg); \ 1875 } while(0) 1876 #endif /* I3C2 */ 1877 1878 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1879 __IO uint32_t tmpreg; \ 1880 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1881 /* Delay after an RCC peripheral clock enabling */ \ 1882 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1883 UNUSED(tmpreg); \ 1884 } while(0) 1885 1886 #if defined(LPTIM3) 1887 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1888 __IO uint32_t tmpreg; \ 1889 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1890 /* Delay after an RCC peripheral clock enabling */ \ 1891 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1892 UNUSED(tmpreg); \ 1893 } while(0) 1894 #endif /* LPTIM3 */ 1895 1896 #if defined(LPTIM4) 1897 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1898 __IO uint32_t tmpreg; \ 1899 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1900 /* Delay after an RCC peripheral clock enabling */ \ 1901 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1902 UNUSED(tmpreg); \ 1903 } while(0) 1904 #endif /* LPTIM4 */ 1905 1906 #if defined(LPTIM5) 1907 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 1908 __IO uint32_t tmpreg; \ 1909 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1910 /* Delay after an RCC peripheral clock enabling */ \ 1911 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1912 UNUSED(tmpreg); \ 1913 } while(0) 1914 #endif /* LPTIM5 */ 1915 1916 #if defined(LPTIM6) 1917 #define __HAL_RCC_LPTIM6_CLK_ENABLE() do { \ 1918 __IO uint32_t tmpreg; \ 1919 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1920 /* Delay after an RCC peripheral clock enabling */ \ 1921 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1922 UNUSED(tmpreg); \ 1923 } while(0) 1924 #endif /* LPTIM6 */ 1925 1926 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1927 __IO uint32_t tmpreg; \ 1928 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1929 /* Delay after an RCC peripheral clock enabling */ \ 1930 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1931 UNUSED(tmpreg); \ 1932 } while(0) 1933 1934 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 1935 __IO uint32_t tmpreg; \ 1936 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1937 /* Delay after an RCC peripheral clock enabling */ \ 1938 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1939 UNUSED(tmpreg); \ 1940 } while(0) 1941 1942 #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) 1943 1944 #if defined(SPI5) 1945 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) 1946 #endif /* SPI5 */ 1947 1948 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1949 1950 #if defined(I2C3) 1951 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1952 #endif /* I2C3 */ 1953 1954 #if defined(I2C4) 1955 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) 1956 #endif /* I2C4 */ 1957 1958 #if defined(I3C2) 1959 #define __HAL_RCC_I3C2_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) 1960 #endif /* I3C2 */ 1961 1962 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1963 1964 #if defined(LPTIM3) 1965 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1966 #endif /* LPTIM3 */ 1967 1968 #if defined(LPTIM4) 1969 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1970 #endif /* LPTIM4 */ 1971 1972 #if defined(LPTIM5) 1973 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) 1974 #endif /* LPTIM5 */ 1975 1976 #if defined(LPTIM6) 1977 #define __HAL_RCC_LPTIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) 1978 #endif /* LPTIM6 */ 1979 1980 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1981 1982 #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1983 1984 /** 1985 * @} 1986 */ 1987 1988 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable AHB APB Branch Clock Disable Clear Disable 1989 * @brief Disable or clear Disable the AHBx/APBx branch clock for all AHBx/APBx peripherals. 1990 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 1991 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 1992 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 1993 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 1994 * @{ 1995 */ 1996 1997 #define __HAL_RCC_AHB1_CLK_DISABLE() do { \ 1998 __IO uint32_t tmpreg; \ 1999 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2000 /* Delay after AHB peripherals bus clocks branch disable */ \ 2001 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2002 UNUSED(tmpreg); \ 2003 } while(0) 2004 2005 #define __HAL_RCC_AHB2_CLK_DISABLE() do { \ 2006 __IO uint32_t tmpreg; \ 2007 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2008 /* Delay after AHB peripherals bus clocks branch disable */ \ 2009 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2010 UNUSED(tmpreg); \ 2011 } while(0) 2012 2013 #if defined(AHB4PERIPH_BASE) 2014 #define __HAL_RCC_AHB4_CLK_DISABLE() do { \ 2015 __IO uint32_t tmpreg; \ 2016 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2017 /* Delay after AHB peripherals bus clocks branch disable */ \ 2018 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2019 UNUSED(tmpreg); \ 2020 } while(0) 2021 #endif /* AHB4PERIPH_BASE */ 2022 2023 #define __HAL_RCC_APB1_CLK_DISABLE() do { \ 2024 __IO uint32_t tmpreg; \ 2025 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2026 /* Delay after APB peripherals bus clocks branch disable */ \ 2027 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2028 UNUSED(tmpreg); \ 2029 } while(0) 2030 2031 #define __HAL_RCC_APB2_CLK_DISABLE() do { \ 2032 __IO uint32_t tmpreg; \ 2033 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2034 /* Delay after APB peripherals bus clocks branch disable */ \ 2035 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2036 UNUSED(tmpreg); \ 2037 } while(0) 2038 2039 #define __HAL_RCC_APB3_CLK_DISABLE() do { \ 2040 __IO uint32_t tmpreg; \ 2041 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2042 /* Delay after APB peripherals bus clocks branch disable */ \ 2043 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2044 UNUSED(tmpreg); \ 2045 } while(0) 2046 2047 2048 #define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) 2049 2050 #define __HAL_RCC_AHB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) 2051 2052 #if defined(AHB4PERIPH_BASE) 2053 #define __HAL_RCC_AHB4_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) 2054 #endif /* AHB4PERIPH_BASE */ 2055 2056 #define __HAL_RCC_APB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) 2057 2058 #define __HAL_RCC_APB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) 2059 2060 #define __HAL_RCC_APB3_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) 2061 2062 /** 2063 * @} 2064 */ 2065 2066 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 2067 * @brief Check whether the AHB1 peripheral clock is enabled or not. 2068 * @note After reset, the peripheral clock (used for registers read/write access) 2069 * is disabled and the application software has to enable this clock before 2070 * using it. 2071 * @{ 2072 */ 2073 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 2074 2075 #define __HAL_RCC_GPDMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) != 0U) 2076 2077 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) != 0U) 2078 2079 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 2080 2081 #if defined(CORDIC) 2082 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 2083 #endif /* CORDIC */ 2084 2085 #if defined(FMAC) 2086 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 2087 #endif /* FMAC */ 2088 2089 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 2090 2091 #if defined(ETH) 2092 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) != 0U) 2093 2094 #define __HAL_RCC_ETHTX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) != 0U) 2095 2096 #define __HAL_RCC_ETHRX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) != 0U) 2097 #endif /*ETH*/ 2098 2099 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) != 0U) 2100 2101 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) != 0U) 2102 2103 #if defined(DCACHE1) 2104 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 2105 #endif /* DCACHE1 */ 2106 2107 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 2108 2109 2110 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 2111 2112 #define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) 2113 2114 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) 2115 2116 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 2117 2118 #if defined(CORDIC) 2119 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 2120 #endif /* CORDIC */ 2121 2122 #if defined(FMAC) 2123 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 2124 #endif /* FMAC */ 2125 2126 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 2127 2128 #if defined(ETH) 2129 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) 2130 2131 #define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) 2132 2133 #define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) 2134 #endif /*ETH*/ 2135 2136 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) 2137 2138 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) 2139 2140 #if defined(DCACHE1) 2141 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 2142 #endif /* DCACHE1 */ 2143 2144 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 2145 /** 2146 * @} 2147 */ 2148 2149 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 2150 * @brief Check whether the AHB2 peripheral clock is enabled or not. 2151 * @note After reset, the peripheral clock (used for registers read/write access) 2152 * is disabled and the application software has to enable this clock before 2153 * using it. 2154 * @{ 2155 */ 2156 2157 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 2158 2159 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 2160 2161 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 2162 2163 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 2164 2165 #if defined(GPIOE) 2166 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 2167 #endif /* GPIOE */ 2168 2169 #if defined(GPIOF) 2170 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 2171 #endif /* GPIOF */ 2172 2173 #if defined(GPIOG) 2174 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 2175 #endif /* GPIOG */ 2176 2177 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 2178 2179 #if defined(GPIOI) 2180 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 2181 #endif /* GPIOI */ 2182 2183 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 2184 2185 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) 2186 2187 #if defined(DCMI) 2188 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) != 0U) 2189 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility */ 2190 #endif /* DCMI */ 2191 2192 #if defined(AES) 2193 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 2194 #endif /* AES */ 2195 2196 #if defined(HASH) 2197 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 2198 #endif /* HASH */ 2199 2200 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 2201 2202 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 2203 2204 #if defined(SAES) 2205 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) 2206 #endif /*SAES*/ 2207 2208 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) 2209 2210 #if defined(SRAM3_BASE) 2211 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) != 0U) 2212 #endif /* SRAM3_BASE */ 2213 2214 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 2215 2216 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 2217 2218 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 2219 2220 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 2221 2222 #if defined(GPIOE) 2223 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 2224 #endif /* GPIOE */ 2225 2226 #if defined(GPIOF) 2227 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 2228 #endif /* GPIOF */ 2229 2230 #if defined(GPIOG) 2231 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 2232 #endif /* GPIOG */ 2233 2234 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 2235 2236 #if defined(GPIOI) 2237 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 2238 #endif /* GPIOI */ 2239 2240 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 2241 2242 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) 2243 2244 #if defined(DCMI) 2245 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) == 0U) 2246 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility */ 2247 #endif /* DCMI */ 2248 2249 #if defined(AES) 2250 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 2251 #endif /* AES */ 2252 2253 #if defined(HASH) 2254 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 2255 #endif /* HASH */ 2256 2257 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 2258 2259 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 2260 2261 #if defined(SAES) 2262 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) == 0U) 2263 #endif /* SAES */ 2264 2265 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) == 0U) 2266 2267 #if defined(SRAM3_BASE) 2268 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) == 0U) 2269 #endif /* SRAM3_BASE */ 2270 /** 2271 * @} 2272 */ 2273 2274 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status 2275 * @brief Check whether the AHB4 peripheral clock is enabled or not. 2276 * @note After reset, the peripheral clock (used for registers read/write access) 2277 * is disabled and the application software has to enable this clock before 2278 * using it. 2279 * @{ 2280 */ 2281 2282 #if defined(OTFDEC1) 2283 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) 2284 #endif /* OTFDEC1 */ 2285 2286 #if defined(OCTOSPI1) 2287 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) 2288 #endif /* OCTOSPI1 */ 2289 2290 #if defined(SDMMC1) 2291 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) 2292 #endif /* SDMMC1 */ 2293 2294 #if defined(SDMMC2) 2295 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) != 0U) 2296 #endif /* SDMMC2 */ 2297 2298 #if defined(FMC_BASE) 2299 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U) 2300 #endif /* FMC_BASE */ 2301 2302 2303 #if defined(OTFDEC1) 2304 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) 2305 #endif /* OTFDEC1 */ 2306 2307 #if defined(OCTOSPI1) 2308 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) 2309 #endif /* OCTOSPI1 */ 2310 2311 #if defined(SDMMC1) 2312 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) 2313 #endif /* SDMMC1 */ 2314 2315 #if defined(SDMMC2) 2316 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) 2317 #endif /* SDMMC2 */ 2318 2319 #if defined(FMC_BASE) 2320 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) 2321 #endif /* FMC_BASE */ 2322 2323 /** 2324 * @} 2325 */ 2326 2327 2328 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2329 * @brief Check whether the APB1 peripheral clock is enabled or not. 2330 * @note After reset, the peripheral clock (used for registers read/write access) 2331 * is disabled and the application software has to enable this clock before 2332 * using it. 2333 * @{ 2334 */ 2335 2336 2337 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) != 0U) 2338 2339 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) != 0U) 2340 2341 #if defined(TIM4) 2342 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) != 0U) 2343 #endif /* TIM4 */ 2344 2345 #if defined(TIM5) 2346 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) != 0U) 2347 #endif /* TIM5 */ 2348 2349 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) != 0U) 2350 2351 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) != 0U) 2352 2353 #if defined(TIM12) 2354 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) != 0U) 2355 #endif /* TIM12 */ 2356 2357 #if defined(TIM13) 2358 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) != 0U) 2359 #endif /* TIM13 */ 2360 2361 #if defined(TIM14) 2362 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) != 0U) 2363 #endif /* TIM14 */ 2364 2365 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) != 0U) 2366 2367 #if defined(OPAMP1) 2368 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) != 0U) 2369 #endif /* OPAMP1 */ 2370 2371 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) != 0U) 2372 2373 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) != 0U) 2374 2375 #if defined(COMP1) 2376 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) != 0U) 2377 #endif /* COMP1 */ 2378 2379 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) != 0U) 2380 2381 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) != 0U) 2382 2383 #if defined(UART4) 2384 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) != 0U) 2385 #endif /* UART4 */ 2386 2387 #if defined(UART5) 2388 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) != 0U) 2389 #endif /* UART5 */ 2390 2391 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) != 0U) 2392 2393 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) != 0U) 2394 2395 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) != 0U) 2396 2397 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) != 0U) 2398 2399 #if defined(USART6) 2400 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) != 0U) 2401 #endif /* USART6 */ 2402 2403 #if defined(USART10) 2404 #define __HAL_RCC_USART10_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) != 0U) 2405 #endif /* USART10 */ 2406 2407 #if defined(USART11) 2408 #define __HAL_RCC_USART11_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) != 0U) 2409 #endif /* USART11 */ 2410 2411 #if defined(CEC) 2412 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) != 0U) 2413 #endif /* CEC */ 2414 2415 #if defined(UART7) 2416 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) != 0U) 2417 #endif /* UART7 */ 2418 2419 #if defined(UART8) 2420 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) != 0U) 2421 #endif /* UART8 */ 2422 2423 2424 #if defined(UART9) 2425 #define __HAL_RCC_UART9_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) != 0U) 2426 #endif /* UART9 */ 2427 2428 #if defined(UART12) 2429 #define __HAL_RCC_UART12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) != 0U) 2430 #endif /* UART12 */ 2431 2432 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) != 0U) 2433 2434 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) != 0U) 2435 2436 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) != 0U) 2437 2438 #if defined(UCPD1) 2439 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) != 0U) 2440 #endif /* UCPD1 */ 2441 2442 2443 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) == 0U) 2444 2445 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) == 0U) 2446 2447 #if defined(TIM4) 2448 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) == 0U) 2449 #endif /* TIM4 */ 2450 2451 #if defined(TIM5) 2452 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) == 0U) 2453 #endif /* TIM5 */ 2454 2455 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) == 0U) 2456 2457 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) == 0U) 2458 2459 #if defined(TIM12) 2460 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) == 0U) 2461 #endif /* TIM12 */ 2462 2463 #if defined(TIM13) 2464 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) == 0U) 2465 #endif /* TIM13 */ 2466 2467 #if defined(TIM14) 2468 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) == 0U) 2469 #endif /* TIM14 */ 2470 2471 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) == 0U) 2472 2473 #if defined(OPAMP1) 2474 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) == 0U) 2475 #endif /* OPAMP1 */ 2476 2477 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) == 0U) 2478 2479 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) == 0U) 2480 2481 #if defined(COMP1) 2482 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) == 0U) 2483 #endif /* COMP1 */ 2484 2485 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) == 0U) 2486 2487 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) == 0U) 2488 2489 #if defined(UART4) 2490 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) == 0U) 2491 #endif /* UART4 */ 2492 2493 #if defined(UART5) 2494 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) == 0U) 2495 #endif /* UART5 */ 2496 2497 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) == 0U) 2498 2499 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) == 0U) 2500 2501 #define __HAL_RCC_I3C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) == 0U) 2502 2503 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) == 0U) 2504 2505 #if defined(USART6) 2506 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) == 0U) 2507 #endif /* USART6 */ 2508 2509 #if defined(USART10) 2510 #define __HAL_RCC_USART10_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) == 0U) 2511 #endif /* USART10 */ 2512 2513 #if defined(USART11) 2514 #define __HAL_RCC_USART11_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) == 0U) 2515 #endif /* USART11 */ 2516 2517 #if defined(CEC) 2518 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) == 0U) 2519 #endif /* CEC */ 2520 2521 #if defined(UART7) 2522 #define __HAL_RCC_UART7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) == 0U) 2523 #endif /* UART7 */ 2524 2525 #if defined(UART8) 2526 #define __HAL_RCC_UART8_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) == 0U) 2527 #endif /* UART8 */ 2528 2529 2530 #if defined(UART9) 2531 #define __HAL_RCC_UART9_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) == 0U) 2532 #endif /* UART9 */ 2533 2534 #if defined(UART12) 2535 #define __HAL_RCC_UART12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) == 0U) 2536 #endif /* UART12 */ 2537 2538 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) == 0U) 2539 2540 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) == 0U) 2541 2542 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) == 0U) 2543 2544 #if defined(UCPD1) 2545 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) == 0U) 2546 #endif /* UCPD1 */ 2547 /** 2548 * @} 2549 */ 2550 2551 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2552 * @brief Check whether the APB2 peripheral clock is enabled or not. 2553 * @note After reset, the peripheral clock (used for registers read/write access) 2554 * is disabled and the application software has to enable this clock before 2555 * using it. 2556 * @{ 2557 */ 2558 2559 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2560 2561 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2562 2563 #if defined(TIM8) 2564 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2565 #endif /* TIM8 */ 2566 2567 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2568 2569 #if defined(TIM15) 2570 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2571 #endif /* TIM15 */ 2572 2573 #if defined(TIM16) 2574 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2575 #endif /* TIM16 */ 2576 2577 #if defined(TIM17) 2578 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2579 #endif /* TIM17 */ 2580 2581 #if defined(SPI4) 2582 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) 2583 #endif /* SPI4 */ 2584 2585 #if defined(SPI6) 2586 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) != 0U) 2587 #endif /* SPI6 */ 2588 2589 #if defined(SAI1) 2590 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2591 #endif /* SAI1 */ 2592 2593 #if defined(SAI2) 2594 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2595 #endif /* SAI2 */ 2596 2597 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) 2598 2599 2600 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2601 2602 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2603 2604 #if defined(TIM8) 2605 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2606 #endif /* TIM8 */ 2607 2608 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2609 2610 #if defined(TIM15) 2611 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2612 #endif /* TIM15 */ 2613 2614 #if defined(TIM16) 2615 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2616 #endif /* TIM16 */ 2617 2618 #if defined(TIM17) 2619 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2620 #endif /* TIM17 */ 2621 2622 #if defined(SPI4) 2623 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) 2624 #endif /* SPI4 */ 2625 2626 #if defined(SPI6) 2627 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) 2628 #endif /* SPI6 */ 2629 2630 #if defined(SAI1) 2631 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2632 #endif /* SAI1 */ 2633 2634 #if defined(SAI2) 2635 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2636 #endif /* SAI2 */ 2637 2638 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) 2639 /** 2640 * @} 2641 */ 2642 2643 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2644 * @brief Check whether the APB3 peripheral clock is enabled or not. 2645 * @note After reset, the peripheral clock (used for registers read/write access) 2646 * is disabled and the application software has to enable this clock before 2647 * using it. 2648 * @{ 2649 */ 2650 2651 #define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) != 0U) 2652 2653 #if defined(SPI5) 2654 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) != 0U) 2655 #endif /* SPI5 */ 2656 2657 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2658 2659 #if defined(I2C3) 2660 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2661 #endif /* I2C3 */ 2662 2663 #if defined(I2C4) 2664 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) != 0U) 2665 #endif /* I2C4 */ 2666 2667 #if defined(I3C2) 2668 #define __HAL_RCC_I3C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) != 0U) 2669 #endif /* I3C2 */ 2670 2671 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2672 2673 #if defined(LPTIM3) 2674 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2675 #endif /* LPTIM3 */ 2676 2677 #if defined(LPTIM4) 2678 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2679 #endif /* LPTIM4 */ 2680 2681 #if defined(LPTIM5) 2682 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) != 0U) 2683 #endif /* LPTIM5 */ 2684 2685 #if defined(LPTIM6) 2686 #define __HAL_RCC_LPTIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) != 0U) 2687 #endif /* LPTIM6 */ 2688 2689 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2690 2691 #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2692 2693 2694 #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) 2695 2696 #if defined(SPI5) 2697 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) == 0U) 2698 #endif /* SPI5 */ 2699 2700 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2701 2702 #if defined(I2C3) 2703 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2704 #endif /* I2C3 */ 2705 2706 #if defined(I2C4) 2707 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) == 0U) 2708 #endif /* I2C4 */ 2709 2710 #if defined(I3C2) 2711 #define __HAL_RCC_I3C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) == 0U) 2712 #endif /* I3C2 */ 2713 2714 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2715 2716 #if defined(LPTIM3) 2717 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2718 #endif /* LPTIM3 */ 2719 2720 #if defined(LPTIM4) 2721 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2722 #endif /* LPTIM4 */ 2723 2724 #if defined(LPTIM5) 2725 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) == 0U) 2726 #endif /* LPTIM5 */ 2727 2728 #if defined(LPTIM6) 2729 #define __HAL_RCC_LPTIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) == 0U) 2730 #endif /* LPTIM6 */ 2731 2732 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2733 2734 #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2735 2736 /** 2737 * @} 2738 */ 2739 2740 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable_Status AHB APB Branch Clock Disabled Status 2741 * @brief Check whether the AHBx/APBx branch clock for all AHBx/APBx peripherals is disabled or not. 2742 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 2743 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 2744 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 2745 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 2746 * @{ 2747 */ 2748 2749 #define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U) 2750 2751 #define __HAL_RCC_AHB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) != 0U) 2752 2753 #if defined(AHB4PERIPH_BASE) 2754 #define __HAL_RCC_AHB4_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) != 0U) 2755 #endif /* AHB4PERIPH_BASE */ 2756 2757 #define __HAL_RCC_APB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) != 0U) 2758 2759 #define __HAL_RCC_APB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) != 0U) 2760 2761 #define __HAL_RCC_APB3_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) != 0U) 2762 2763 /** 2764 * @} 2765 */ 2766 2767 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2768 * @brief Force or release AHB1 peripheral reset. 2769 * @{ 2770 */ 2771 2772 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x010AD003U) 2773 2774 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2775 2776 #define __HAL_RCC_GPDMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2777 2778 #if defined(CORDIC) 2779 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2780 #endif /* CORDIC */ 2781 2782 #if defined(FMAC) 2783 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2784 #endif /* FMAC */ 2785 2786 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2787 2788 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2789 2790 #if defined(ETH) 2791 #define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2792 #endif /* ETH */ 2793 2794 #define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2795 2796 2797 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2798 2799 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2800 2801 #define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2802 2803 #if defined(CORDIC) 2804 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2805 #endif /* CORDIC */ 2806 2807 #if defined(FMAC) 2808 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2809 #endif /* FMAC */ 2810 2811 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2812 2813 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2814 2815 #if defined(ETH) 2816 #define __HAL_RCC_ETH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2817 #endif /* ETH */ 2818 2819 #define __HAL_RCC_GTZC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2820 2821 /** 2822 * @} 2823 */ 2824 2825 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2826 * @brief Force or release AHB2 peripheral reset. 2827 * @{ 2828 */ 2829 2830 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x001F1DFFU) 2831 2832 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2833 2834 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2835 2836 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2837 2838 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2839 2840 #if defined(GPIOE) 2841 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2842 #endif /* GPIOE */ 2843 2844 #if defined(GPIOF) 2845 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2846 #endif /* GPIOF */ 2847 2848 #if defined(GPIOG) 2849 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2850 #endif /* GPIOG */ 2851 2852 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2853 2854 #if defined(GPIOI) 2855 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2856 #endif /* GPIOI */ 2857 2858 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2859 2860 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 2861 2862 #if defined(DCMI) 2863 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2864 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility */ 2865 #endif /* DCMI */ 2866 2867 #if defined(AES) 2868 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2869 #endif /* AES */ 2870 2871 #if defined(HASH) 2872 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2873 #endif /* HASH */ 2874 2875 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2876 2877 #if defined(PKA) 2878 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2879 #endif /* PKA */ 2880 2881 #if defined(SAES) 2882 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2883 #endif /* SAES*/ 2884 2885 2886 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 2887 2888 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2889 2890 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2891 2892 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2893 2894 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2895 2896 #if defined(GPIOE) 2897 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2898 #endif /* GPIOE */ 2899 2900 #if defined(GPIOF) 2901 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2902 #endif /* GPIOF */ 2903 2904 #if defined(GPIOG) 2905 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2906 #endif /* GPIOG */ 2907 2908 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2909 2910 #if defined(GPIOG) 2911 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2912 #endif /* GPIOI */ 2913 2914 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2915 2916 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 2917 2918 #if defined(DCMI) 2919 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2920 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility */ 2921 #endif /* DCMI */ 2922 2923 #if defined(AES) 2924 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2925 #endif /* AES */ 2926 2927 #if defined(HASH) 2928 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2929 #endif /* HASH */ 2930 2931 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2932 2933 #if defined(PKA) 2934 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2935 #endif /* PKA */ 2936 2937 #if defined(SAES) 2938 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2939 #endif /* SAES*/ 2940 2941 /** 2942 * @} 2943 */ 2944 2945 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 2946 * @brief Force or release AHB4 peripheral reset. 2947 * @{ 2948 */ 2949 2950 #if defined(FMC_BASE) 2951 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00111880U) 2952 #endif /* FMC_BASE */ 2953 2954 #if defined(OTFDEC1) 2955 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 2956 #endif /* OTFDEC1 */ 2957 2958 #if defined(SDMMC1) 2959 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 2960 #endif /* SDMMC1 */ 2961 2962 #if defined(SDMMC2) 2963 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 2964 #endif /* SDMMC2 */ 2965 2966 #if defined(FMC_BASE) 2967 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 2968 #endif /* FMC_BASE */ 2969 2970 #if defined(OCTOSPI1) 2971 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 2972 #endif /* OCTOSPI1 */ 2973 2974 2975 #if defined(FMC_BASE) 2976 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) 2977 #endif /* FMC_BASE */ 2978 2979 #if defined(OTFDEC1) 2980 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 2981 #endif /* OTFDEC1 */ 2982 2983 #if defined(SDMMC1) 2984 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 2985 #endif /* SDMMC1 */ 2986 2987 #if defined(SDMMC2) 2988 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 2989 #endif /* SDMMC2 */ 2990 2991 #if defined(FMC_BASE) 2992 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 2993 #endif /* FMC_BASE */ 2994 2995 #if defined(OCTOSPI1) 2996 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 2997 #endif /* OCTOSPI1 */ 2998 2999 /** 3000 * @} 3001 */ 3002 3003 3004 3005 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 3006 * @brief Force or release APB1 peripheral reset. 3007 * @{ 3008 */ 3009 3010 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 3011 WRITE_REG(RCC->APB1LRSTR, 0xDFFEC1FFU); \ 3012 WRITE_REG(RCC->APB1HRSTR, 0x4080062BU); \ 3013 } while(0) 3014 3015 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3016 3017 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3018 3019 #if defined(TIM4) 3020 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3021 #endif /* TIM4 */ 3022 3023 #if defined(TIM5) 3024 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3025 #endif /* TIM5 */ 3026 3027 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3028 3029 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3030 3031 #if defined(TIM12) 3032 #define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3033 #endif /* TIM12 */ 3034 3035 #if defined(TIM13) 3036 #define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3037 #endif /* TIM13 */ 3038 3039 #if defined(TIM14) 3040 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3041 #endif /* TIM14 */ 3042 3043 #if defined(OPAMP1) 3044 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3045 #endif /* OPAMP1 */ 3046 3047 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3048 3049 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3050 3051 #if defined(COMP1) 3052 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3053 #endif /* COMP1 */ 3054 3055 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3056 3057 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3058 3059 #if defined(UART4) 3060 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3061 #endif /* UART4 */ 3062 3063 #if defined(UART5) 3064 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3065 #endif /* UART5 */ 3066 3067 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3068 3069 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3070 3071 #define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3072 3073 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3074 3075 #if defined(USART6) 3076 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3077 #endif /* USART6 */ 3078 3079 #if defined(USART10) 3080 #define __HAL_RCC_USART10_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3081 #endif /* USART10 */ 3082 3083 #if defined(USART11) 3084 #define __HAL_RCC_USART11_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3085 #endif /* USART11 */ 3086 3087 #if defined(CEC) 3088 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3089 #endif /* CEC */ 3090 3091 #if defined(UART7) 3092 #define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3093 #endif /* UART7 */ 3094 3095 #if defined(UART8) 3096 #define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3097 #endif /* UART8 */ 3098 3099 3100 #if defined(UART9) 3101 #define __HAL_RCC_UART9_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3102 #endif /* UART9 */ 3103 3104 #if defined(UART12) 3105 #define __HAL_RCC_UART12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3106 #endif /* UART12 */ 3107 3108 #define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3109 3110 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3111 3112 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) 3113 3114 #if defined(UCPD1) 3115 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3116 #endif /* UCPD1 */ 3117 3118 3119 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 3120 WRITE_REG(RCC->APB1LRSTR, 0x00000000U); \ 3121 WRITE_REG(RCC->APB1HRSTR, 0x00000000U); \ 3122 } while(0) 3123 3124 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3125 3126 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3127 3128 #if defined(TIM4) 3129 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3130 #endif /* TIM4 */ 3131 3132 #if defined(TIM5) 3133 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3134 #endif /* TIM5 */ 3135 3136 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3137 3138 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3139 3140 #if defined(TIM12) 3141 #define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3142 #endif /* TIM12 */ 3143 3144 #if defined(TIM13) 3145 #define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3146 #endif /* TIM13 */ 3147 3148 #if defined(TIM14) 3149 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3150 #endif /* TIM14 */ 3151 3152 #if defined(OPAMP1) 3153 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3154 #endif /* OPAMP1 */ 3155 3156 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3157 3158 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3159 3160 #if defined(COMP1) 3161 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3162 #endif /* COMP1 */ 3163 3164 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3165 3166 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3167 3168 #if defined(UART4) 3169 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3170 #endif /* UART4 */ 3171 3172 #if defined(UART5) 3173 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3174 #endif /* UART5 */ 3175 3176 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3177 3178 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3179 3180 #define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3181 3182 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3183 3184 #if defined(USART6) 3185 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3186 #endif /* USART6 */ 3187 3188 #if defined(USART10) 3189 #define __HAL_RCC_USART10_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3190 #endif /* USART10 */ 3191 3192 #if defined(USART11) 3193 #define __HAL_RCC_USART11_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3194 #endif /* USART11 */ 3195 3196 #if defined(CEC) 3197 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3198 #endif /* CEC */ 3199 3200 #if defined(UART7) 3201 #define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3202 #endif /* UART7 */ 3203 3204 #if defined(UART8) 3205 #define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3206 #endif /* UART8 */ 3207 3208 3209 #if defined(UART9) 3210 #define __HAL_RCC_UART9_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3211 #endif /* UART9 */ 3212 3213 #if defined(UART12) 3214 #define __HAL_RCC_UART12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3215 #endif /* UART12 */ 3216 3217 #define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3218 3219 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3220 3221 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) 3222 3223 #if defined(UCPD1) 3224 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3225 #endif /* UCPD1 */ 3226 3227 /** 3228 * @} 3229 */ 3230 3231 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 3232 * @brief Force or release APB2 peripheral reset. 3233 * @{ 3234 */ 3235 3236 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x017F7800U) 3237 3238 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3239 3240 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3241 3242 #if defined(TIM8) 3243 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3244 #endif /* TIM8 */ 3245 3246 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3247 3248 #if defined(TIM15) 3249 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3250 #endif /* TIM15 */ 3251 3252 #if defined(TIM16) 3253 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3254 #endif /* TIM16 */ 3255 3256 #if defined(TIM17) 3257 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3258 #endif /* TIM17 */ 3259 3260 #if defined(SPI4) 3261 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3262 #endif /* SPI4 */ 3263 3264 #if defined(SPI6) 3265 #define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3266 #endif /* SPI6 */ 3267 3268 #if defined(SAI1) 3269 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3270 #endif /* SAI1 */ 3271 3272 #if defined(SAI2) 3273 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3274 #endif /* SAI2 */ 3275 3276 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3277 3278 3279 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 3280 3281 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3282 3283 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3284 3285 #if defined(TIM8) 3286 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3287 #endif /* TIM8 */ 3288 3289 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3290 3291 #if defined(TIM15) 3292 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3293 #endif /* TIM15 */ 3294 3295 #if defined(TIM16) 3296 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3297 #endif /* TIM16 */ 3298 3299 #if defined(TIM17) 3300 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3301 #endif /* TIM17 */ 3302 3303 #if defined(SPI4) 3304 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3305 #endif /* SPI4 */ 3306 3307 #if defined(SPI6) 3308 #define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3309 #endif /* SPI6 */ 3310 3311 #if defined(SAI1) 3312 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3313 #endif /* SAI1 */ 3314 3315 #if defined(SAI2) 3316 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3317 #endif /* SAI2 */ 3318 3319 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3320 3321 /** 3322 * @} 3323 */ 3324 3325 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 3326 * @brief Force or release APB3 peripheral reset. 3327 * @{ 3328 */ 3329 3330 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x001008E0U) 3331 3332 #if defined(SPI5) 3333 #define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3334 #endif /* SPI5 */ 3335 3336 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3337 3338 #if defined(I2C3) 3339 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3340 #endif /* I2C3 */ 3341 3342 #if defined(I2C4) 3343 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3344 #endif /* I2C4 */ 3345 3346 #if defined(I3C2) 3347 #define __HAL_RCC_I3C2_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3348 #endif /* I3C2 */ 3349 3350 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3351 3352 #if defined(LPTIM3) 3353 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3354 #endif /* LPTIM3 */ 3355 3356 #if defined(LPTIM4) 3357 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3358 #endif /* LPTIM4 */ 3359 3360 #if defined(LPTIM5) 3361 #define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3362 #endif /* LPTIM5 */ 3363 3364 #if defined(LPTIM6) 3365 #define __HAL_RCC_LPTIM6_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3366 #endif /* LPTIM6 */ 3367 3368 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3369 3370 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 3371 3372 #if defined(SPI5) 3373 #define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3374 #endif /* SPI5 */ 3375 3376 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3377 3378 #if defined(I2C3) 3379 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3380 #endif /* I2C3 */ 3381 3382 #if defined(I2C4) 3383 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3384 #endif /* I2C4 */ 3385 3386 #if defined(I3C2) 3387 #define __HAL_RCC_I3C2_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3388 #endif /* I3C2 */ 3389 3390 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3391 3392 #if defined(LPTIM3) 3393 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3394 #endif /* LPTIM3 */ 3395 3396 #if defined(LPTIM4) 3397 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3398 #endif /* LPTIM4 */ 3399 3400 #if defined(LPTIM5) 3401 #define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3402 #endif /* LPTIM5 */ 3403 3404 #if defined(LPTIM6) 3405 #define __HAL_RCC_LPTIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3406 #endif /* LPTIM6 */ 3407 3408 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3409 3410 /** 3411 * @} 3412 */ 3413 3414 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 3415 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3416 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3417 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3418 * @{ 3419 */ 3420 3421 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3422 3423 #define __HAL_RCC_GPDMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3424 3425 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3426 3427 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3428 3429 #if defined(CORDIC) 3430 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3431 #endif /* CORDIC */ 3432 3433 #if defined(FMAC) 3434 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3435 #endif /* FMAC */ 3436 3437 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3438 3439 #if defined(ETH) 3440 #define __HAL_RCC_ETH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3441 3442 #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3443 3444 #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3445 #endif /* ETH */ 3446 3447 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3448 3449 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3450 3451 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3452 3453 #if defined(DCACHE1) 3454 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3455 #endif /* DCACHE1 */ 3456 3457 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3458 3459 3460 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3461 3462 #define __HAL_RCC_GPDMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3463 3464 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3465 3466 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3467 3468 #if defined(CORDIC) 3469 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3470 #endif /* CORDIC */ 3471 3472 #if defined(FMAC) 3473 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3474 #endif /* FMAC */ 3475 3476 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3477 3478 #if defined(ETH) 3479 #define __HAL_RCC_ETH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3480 3481 #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3482 3483 #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3484 #endif /* ETH */ 3485 3486 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3487 3488 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3489 3490 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3491 3492 #if defined(DCACHE1) 3493 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3494 #endif /* DCACHE1 */ 3495 3496 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3497 3498 /** 3499 * @} 3500 */ 3501 3502 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 3503 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3504 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3505 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3506 * @{ 3507 */ 3508 3509 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3510 3511 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3512 3513 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3514 3515 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3516 3517 #if defined(GPIOE) 3518 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3519 #endif /* GPIOE */ 3520 3521 #if defined(GPIOF) 3522 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3523 #endif /* GPIOF */ 3524 3525 #if defined(GPIOG) 3526 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3527 #endif /* GPIOG */ 3528 3529 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3530 3531 #if defined(GPIOI) 3532 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3533 #endif /* GPIOI */ 3534 3535 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) 3536 3537 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) 3538 3539 #if defined(DCMI) 3540 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3541 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ 3542 #endif /* DCMI */ 3543 3544 #if defined(AES) 3545 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3546 #endif /* AES */ 3547 3548 #if defined(HASH) 3549 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3550 #endif /* HASH */ 3551 3552 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3553 3554 #if defined(PKA) 3555 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3556 #endif /*PKA*/ 3557 3558 #if defined(SAES) 3559 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3560 #endif /* AES */ 3561 3562 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3563 3564 #if defined(SRAM3_BASE) 3565 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3566 #endif /* SRAM3_BASE */ 3567 3568 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3569 3570 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3571 3572 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3573 3574 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3575 3576 #if defined(GPIOE) 3577 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3578 #endif /* GPIOE */ 3579 3580 #if defined(GPIOF) 3581 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3582 #endif /* GPIOF */ 3583 3584 #if defined(GPIOG) 3585 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3586 #endif /* GPIOG */ 3587 3588 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3589 3590 #if defined(GPIOI) 3591 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3592 #endif /* GPIOI */ 3593 3594 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) 3595 3596 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) 3597 3598 #if defined(DCMI) 3599 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3600 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ 3601 #endif /* DCMI */ 3602 3603 #if defined(AES) 3604 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3605 #endif /* AES */ 3606 3607 #if defined(HASH) 3608 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3609 #endif /* HASH */ 3610 3611 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3612 3613 #if defined(PKA) 3614 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3615 #endif /*PKA*/ 3616 3617 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3618 3619 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3620 3621 #if defined(SRAM3_BASE) 3622 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3623 #endif /* SRAM3_BASE */ 3624 /** 3625 * @} 3626 */ 3627 3628 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable 3629 * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 3630 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3631 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3632 * @{ 3633 */ 3634 3635 #if defined(OTFDEC1) 3636 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3637 #endif /* OTFDEC1 */ 3638 3639 #if defined(SDMMC1) 3640 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3641 #endif /* SDMMC1*/ 3642 3643 #if defined(SDMMC2) 3644 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3645 #endif /* SDMMC2*/ 3646 3647 #if defined(FMC_BASE) 3648 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3649 #endif /* FMC_BASE */ 3650 3651 #if defined(OCTOSPI1) 3652 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3653 #endif /* OCTOSPI1 */ 3654 3655 #if defined(OTFDEC1) 3656 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3657 #endif /* OTFDEC1 */ 3658 3659 #if defined(SDMMC1) 3660 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3661 #endif /* SDMMC1*/ 3662 3663 #if defined(SDMMC2) 3664 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3665 #endif /* SDMMC2*/ 3666 3667 #if defined(FMC_BASE) 3668 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3669 #endif /* FMC_BASE */ 3670 3671 #if defined(OCTOSPI1) 3672 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3673 #endif /* OCTOSPI1 */ 3674 3675 /** 3676 * @} 3677 */ 3678 3679 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3680 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3681 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3682 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3683 * @{ 3684 */ 3685 3686 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3687 3688 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3689 3690 #if defined(TIM4) 3691 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3692 #endif /* TIM4 */ 3693 3694 #if defined(TIM5) 3695 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3696 #endif /* TIM5 */ 3697 3698 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3699 3700 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3701 3702 #if defined(TIM12) 3703 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3704 #endif /* TIM12 */ 3705 3706 #if defined(TIM13) 3707 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3708 #endif /* TIM13 */ 3709 3710 #if defined(TIM14) 3711 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3712 #endif /* TIM14 */ 3713 3714 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3715 3716 #if defined(OPAMP1) 3717 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3718 #endif /* OPAMP1 */ 3719 3720 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3721 3722 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3723 3724 #if defined(COMP1) 3725 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3726 #endif /* COMP1 */ 3727 3728 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3729 3730 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3731 3732 #if defined(UART4) 3733 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3734 #endif /* UART4 */ 3735 3736 #if defined(UART5) 3737 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3738 #endif /* UART5 */ 3739 3740 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3741 3742 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3743 3744 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3745 3746 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3747 3748 #if defined(USART6) 3749 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3750 #endif /* USART6 */ 3751 3752 #if defined(USART10) 3753 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3754 #endif /* USART10 */ 3755 3756 #if defined(USART11) 3757 #define __HAL_RCC_USART11_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3758 #endif /* USART11 */ 3759 3760 #if defined(CEC) 3761 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3762 #endif /* CEC */ 3763 3764 #if defined(UART7) 3765 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3766 #endif /* UART7 */ 3767 3768 #if defined(UART8) 3769 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3770 #endif /* UART8 */ 3771 3772 3773 #if defined(UART9) 3774 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3775 #endif /* UART9 */ 3776 3777 #if defined(UART12) 3778 #define __HAL_RCC_UART12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3779 #endif /* UART12 */ 3780 3781 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3782 3783 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3784 3785 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) 3786 3787 #if defined(UCPD1) 3788 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3789 #endif /* UCPD1 */ 3790 3791 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3792 3793 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3794 3795 #if defined(TIM4) 3796 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3797 #endif /* TIM4 */ 3798 3799 #if defined(TIM5) 3800 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3801 #endif /* TIM5 */ 3802 3803 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3804 3805 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3806 3807 #if defined(TIM12) 3808 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3809 #endif /* TIM12 */ 3810 3811 #if defined(TIM13) 3812 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3813 #endif /* TIM12 */ 3814 3815 #if defined(TIM14) 3816 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3817 #endif /* TIM14 */ 3818 3819 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3820 3821 #if defined(OPAMP1) 3822 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3823 #endif /* OPAMP1 */ 3824 3825 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3826 3827 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3828 3829 #if defined(COMP1) 3830 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3831 #endif /* COMP1 */ 3832 3833 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3834 3835 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3836 3837 #if defined(UART4) 3838 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3839 #endif /* UART4 */ 3840 3841 #if defined(UART5) 3842 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3843 #endif /* UART5 */ 3844 3845 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3846 3847 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3848 3849 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3850 3851 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3852 3853 #if defined(USART6) 3854 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3855 #endif /* USART6 */ 3856 3857 #if defined(USART10) 3858 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3859 #endif /* USART10 */ 3860 3861 #if defined(USART11) 3862 #define __HAL_RCC_USART11_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3863 #endif /* USART11 */ 3864 3865 #if defined(CEC) 3866 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3867 #endif /* CEC */ 3868 3869 #if defined(UART7) 3870 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3871 #endif /* UART7 */ 3872 3873 #if defined(UART8) 3874 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3875 #endif /* UART8 */ 3876 3877 3878 #if defined(UART9) 3879 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3880 #endif /* UART9 */ 3881 3882 #if defined(UART12) 3883 #define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3884 #endif /* UART12 */ 3885 3886 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3887 3888 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3889 3890 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) 3891 3892 #if defined(UCPD1) 3893 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3894 #endif /* UCPD1 */ 3895 3896 /** 3897 * @} 3898 */ 3899 3900 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3901 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3902 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3903 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3904 * @{ 3905 */ 3906 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3907 3908 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3909 3910 #if defined(TIM8) 3911 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3912 #endif /* TIM8 */ 3913 3914 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3915 3916 #if defined(TIM15) 3917 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3918 #endif /* TIM15 */ 3919 3920 #if defined(TIM16) 3921 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3922 #endif /* TIM16 */ 3923 3924 #if defined(TIM17) 3925 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3926 #endif /* TIM17 */ 3927 3928 #if defined(SPI4) 3929 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3930 #endif /* SPI4 */ 3931 3932 #if defined(SPI6) 3933 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 3934 #endif /* SPI6 */ 3935 3936 #if defined(SAI1) 3937 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3938 #endif /* SAI1 */ 3939 3940 #if defined(SAI2) 3941 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3942 #endif /* SAI2 */ 3943 3944 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 3945 3946 3947 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3948 3949 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3950 3951 #if defined(TIM8) 3952 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3953 #endif /* TIM8 */ 3954 3955 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3956 3957 #if defined(TIM15) 3958 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3959 #endif /* TIM15 */ 3960 3961 #if defined(TIM16) 3962 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3963 #endif /* TIM16 */ 3964 3965 #if defined(TIM17) 3966 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3967 #endif /* TIM17 */ 3968 3969 #if defined(SPI4) 3970 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3971 #endif /* SPI4 */ 3972 3973 #if defined(SPI6) 3974 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 3975 #endif /* SPI6 */ 3976 3977 #if defined(SAI1) 3978 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3979 #endif /* SAI1 */ 3980 3981 #if defined(SAI2) 3982 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3983 #endif /* SAI2 */ 3984 3985 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 3986 3987 /** 3988 * @} 3989 */ 3990 3991 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 3992 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 3993 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3994 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3995 * @{ 3996 */ 3997 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 3998 3999 #if defined(SPI5) 4000 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4001 #endif /* SPI5 */ 4002 4003 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4004 4005 #if defined(I2C3) 4006 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4007 #endif /* I2C3 */ 4008 4009 #if defined(I2C4) 4010 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4011 #endif /* I2C4 */ 4012 4013 #if defined(I3C2) 4014 #define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4015 #endif /* I3C2 */ 4016 4017 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4018 4019 #if defined(LPTIM3) 4020 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4021 #endif /* LPTIM3 */ 4022 4023 #if defined(LPTIM4) 4024 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4025 #endif /* LPTIM4 */ 4026 4027 #if defined(LPTIM5) 4028 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4029 #endif /* LPTIM5 */ 4030 4031 #if defined(LPTIM6) 4032 #define __HAL_RCC_LPTIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4033 #endif /* LPTIM6 */ 4034 4035 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4036 4037 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4038 4039 4040 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 4041 4042 #if defined(SPI5) 4043 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4044 #endif /* SPI5 */ 4045 4046 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4047 4048 #if defined(I2C3) 4049 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4050 #endif /* I2C3 */ 4051 4052 #if defined(I2C4) 4053 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4054 #endif /* I2C4 */ 4055 4056 #if defined(I3C2) 4057 #define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4058 #endif /* I3C2 */ 4059 4060 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4061 4062 #if defined(LPTIM3) 4063 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4064 #endif /* LPTIM3 */ 4065 4066 #if defined(LPTIM4) 4067 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4068 #endif /* LPTIM4 */ 4069 4070 #if defined(LPTIM5) 4071 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4072 #endif /* LPTIM5 */ 4073 4074 #if defined(LPTIM6) 4075 #define __HAL_RCC_LPTIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4076 #endif /* LPTIM6 */ 4077 4078 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4079 4080 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4081 4082 /** 4083 * @} 4084 */ 4085 4086 4087 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 4088 * @{ 4089 */ 4090 4091 /** @brief Macros to force or release the Backup domain reset. 4092 * @note This function resets the RTC peripheral (including the backup registers) 4093 * and the RTC clock source selection in RCC_BDCR register. 4094 * @note The BKPSRAM is not affected by this reset. 4095 * @retval None 4096 */ 4097 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4098 4099 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4100 4101 /** 4102 * @} 4103 */ 4104 4105 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 4106 * @{ 4107 */ 4108 4109 /** @brief Macros to enable or disable the RTC clock. 4110 * @note As the RTC is in the Backup domain and write access is denied to 4111 * this domain after reset, you have to enable write access using 4112 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 4113 * (to be done once after reset). 4114 * @note These macros must be used after the RTC clock source was selected. 4115 * @retval None 4116 */ 4117 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4118 4119 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4120 4121 /** 4122 * @} 4123 */ 4124 4125 /** @brief Macro to configure the Internal High Speed oscillator (HSI). 4126 * @param __HSIDIV__ specifies the HSI division factor. 4127 * This parameter can be one of the following values: 4128 * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) 4129 * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 4130 * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 4131 * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 4132 */ 4133 #define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) \ 4134 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV , (uint32_t)(__HSIDIV__)) 4135 4136 4137 /** @brief Macro to get the HSI divider. 4138 * @retval The HSI divider. The returned value can be one 4139 * of the following: 4140 * - RCC_HSI_DIV1 HSI oscillator divided by 1 4141 * - RCC_HSI_DIV2 HSI oscillator divided by 2 4142 * - RCC_HSI_DIV4 HSI oscillator divided by 4 4143 * - RCC_HSI_DIV8 HSI oscillator divided by 8 4144 */ 4145 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 4146 4147 /** @brief Macros to enable or disable the Internal High Speed 64MHz oscillator (HSI). 4148 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 4149 * It is used (enabled by hardware) as system clock source after startup 4150 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 4151 * of the HSE used directly or indirectly as system clock (if the HSE Clock 4152 * Security System HSECSS is enabled). 4153 * @note HSI can not be stopped if it is used as system clock source. In this case, 4154 * you have to select another source of the system clock then stop the HSI. 4155 * @note After enabling the HSI, the application software should wait on HSIRDY 4156 * flag to be set indicating that HSI clock is stable and can be used as 4157 * system clock source. 4158 * This parameter can be: ENABLE or DISABLE. 4159 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 4160 * clock cycles. 4161 * @retval None 4162 */ 4163 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 4164 4165 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 4166 4167 /** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. 4168 * @note The calibration is used to compensate for the variations in voltage 4169 * and temperature that influence the frequency of the internal HSI RC. 4170 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 4171 * (default is RCC_HSICALIBRATION_DEFAULT). 4172 * This parameter must be a number between 0 and 0x7F. 4173 * @retval None 4174 */ 4175 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 4176 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos) 4177 4178 /** 4179 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 4180 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 4181 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 4182 * speed because of the HSI startup time. 4183 * @note The enable of this function has not effect on the HSION bit. 4184 * This parameter can be: ENABLE or DISABLE. 4185 * @retval None 4186 */ 4187 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 4188 4189 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 4190 4191 /** 4192 * @brief Macros to enable or disable the Internal Low-power oscillator (CSI). 4193 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 4194 * It is used (enabled by hardware) as system clock source after 4195 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 4196 * of failure of the HSE used directly or indirectly as system clock 4197 * (if the HSE Clock Security System HSECSS is enabled and CSI is selected 4198 * as system clock after wake up from system stop). 4199 * @note CSI can not be stopped if it is used as system clock source. 4200 * In this case, you have to select another source of the system 4201 * clock then stop the CSI. 4202 * @note After enabling the CSI, the application software should wait on 4203 * CSIRDY flag to be set indicating that CSI clock is stable and can 4204 * be used as system clock source. 4205 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 4206 * clock cycles. 4207 * @retval None 4208 */ 4209 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 4210 4211 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 4212 4213 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 4214 * @note The calibration is used to compensate for the variations in voltage 4215 * and temperature that influence the frequency of the internal CSI RC. 4216 * @param __CSICalibrationValue__: specifies the calibration trimming value. 4217 * This parameter must be a number between 0 and 0x3F. 4218 */ 4219 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 4220 do { \ 4221 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 4222 } while(0) 4223 4224 /** 4225 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 4226 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 4227 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 4228 * speed because of the CSI start-up time. 4229 * @note The enable of this function has not effect on the CSION bit. 4230 * This parameter can be: ENABLE or DISABLE. 4231 * @retval None 4232 */ 4233 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 4234 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 4235 4236 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4237 * @note After enabling the LSI, the application software should wait on 4238 * LSIRDY flag to be set indicating that LSI clock is stable and can 4239 * be used to clock the IWDG and/or the RTC. 4240 * @note LSI can not be disabled if the IWDG is running. 4241 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4242 * clock cycles. 4243 * @retval None 4244 */ 4245 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 4246 4247 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION) 4248 4249 /** 4250 * @brief Macro to configure the External High Speed oscillator (HSE). 4251 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4252 * supported by this macro. User should request a transition to HSE Off 4253 * first and then HSE On or HSE Bypass. 4254 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4255 * software should wait on HSERDY flag to be set indicating that HSE clock 4256 * is stable and can be used to clock the PLLs and/or system clock. 4257 * @note HSE state can not be changed if it is used directly or through the 4258 * PLL1 as system clock. In this case, you have to select another source 4259 * of the system clock then change the HSE state (ex. disable it). 4260 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 4261 * @param __STATE__: specifies the new state of the HSE. 4262 * This parameter can be one of the following values: 4263 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4264 * 6 HSE oscillator clock cycles. 4265 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4266 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4267 * @arg @ref RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. 4268 * @retval None 4269 */ 4270 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4271 do { \ 4272 if ((__STATE__) == RCC_HSE_ON) \ 4273 { \ 4274 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4275 } \ 4276 else if ((__STATE__) == RCC_HSE_OFF) \ 4277 { \ 4278 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4279 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4280 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4281 } \ 4282 else if ((__STATE__) == RCC_HSE_BYPASS) \ 4283 { \ 4284 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4285 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4286 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4287 } \ 4288 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 4289 { \ 4290 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4291 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4292 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4293 } \ 4294 else \ 4295 { \ 4296 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4297 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4298 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4299 } \ 4300 } while(0) 4301 4302 /** 4303 * @brief Macro to configure the External Low Speed oscillator (LSE). 4304 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4305 * supported by this macro. User should request a transition to LSE Off 4306 * first and then LSE On or LSE Bypass. 4307 * @note As the LSE is in the Backup domain and write access is denied to 4308 * this domain after reset, you have to enable write access using 4309 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4310 * (to be done once after reset). 4311 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4312 * software should wait on LSERDY flag to be set indicating that LSE clock 4313 * is stable and can be used to clock the RTC. 4314 * @param __STATE__: specifies the new state of the LSE. 4315 * This parameter can be one of the following values: 4316 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4317 * 6 LSE oscillator clock cycles. 4318 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4319 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4320 * @arg @ref RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. 4321 * @retval None 4322 */ 4323 4324 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4325 do { \ 4326 if((__STATE__) == RCC_LSE_ON) \ 4327 { \ 4328 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4329 } \ 4330 else if((__STATE__) == RCC_LSE_OFF) \ 4331 { \ 4332 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4333 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4334 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4335 } \ 4336 else if((__STATE__) == RCC_LSE_BYPASS) \ 4337 { \ 4338 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4339 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4340 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4341 } \ 4342 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 4343 { \ 4344 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4345 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4346 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4347 } \ 4348 else \ 4349 { \ 4350 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4351 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4352 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4353 } \ 4354 } while(0) 4355 4356 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4357 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4358 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4359 * flag to be set indicating that HSI48 clock is stable. 4360 * This parameter can be: ENABLE or DISABLE. 4361 * @retval None 4362 */ 4363 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 4364 4365 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 4366 4367 /** @brief Macros to configure the RTC clock (RTCCLK). 4368 * @note As the RTC clock configuration bits are in the Backup domain and write 4369 * access is denied to this domain after reset, you have to enable write 4370 * access using the Power Backup Access macro before to configure 4371 * the RTC clock source (to be done once after reset). 4372 * @note Once the RTC clock is configured it cannot be changed unless the 4373 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 4374 * a Power On Reset (POR). 4375 * @param __RTCCLKSource__: specifies the RTC clock source. 4376 * This parameter can be one of the following values: 4377 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 4378 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 4379 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected 4380 * as RTC clock, where x can be between 2 and 63 4381 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4382 * work in STOP and STANDBY modes, and can be used as wakeup source. 4383 * However, when the HSE clock is used as RTC clock source, the RTC 4384 * cannot be used in STOP and STANDBY modes. 4385 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4386 * RTC clock source). 4387 */ 4388 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 4389 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, \ 4390 (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE) 4391 4392 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 4393 RCC->BDCR &= ~RCC_BDCR_RTCSEL; \ 4394 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 4395 } while (0) 4396 4397 /** @brief Macro to get the RTC clock source. 4398 * @retval The returned value can be one of the following: 4399 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4400 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4401 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4402 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as 4403 * RTC clock, where x can be between 2 and 63 4404 (x can be retrieved with @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()) 4405 */ 4406 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 4407 4408 /** @brief Macro to get the HSE division factor for RTC clock. 4409 * 4410 * @retval The HSE division factor for RTC clock. The returned value can be one 4411 * of the following: 4412 * @arg @ref RCC_RTC_HSE_NOCLOCK : No HSE Clock selected as RTC clock 4413 * @arg @ref RCC_RTC_HSE_DIV2 : HSE Divided by 2 selected as RTC clock 4414 * @arg @ref RCC_RTC_HSE_DIV3 : HSE Divided by 3 selected as RTC clock 4415 * @arg @ref RCC_RTC_HSE_DIV4 : HSE Divided by 4 selected as RTC clock 4416 * @arg @ref RCC_RTC_HSE_DIV5 : HSE Divided by 5 selected as RTC clock 4417 * @arg @ref RCC_RTC_HSE_DIV6 : HSE Divided by 6 selected as RTC clock 4418 * @arg @ref RCC_RTC_HSE_DIV7 : HSE Divided by 7 selected as RTC clock 4419 * @arg @ref RCC_RTC_HSE_DIV8 : HSE Divided by 8 selected as RTC clock 4420 * @arg @ref RCC_RTC_HSE_DIV9 : HSE Divided by 9 selected as RTC clock 4421 * @arg @ref RCC_RTC_HSE_DIV10 : HSE Divided by 10 selected as RTC clock 4422 * @arg @ref RCC_RTC_HSE_DIV11 : HSE Divided by 11 selected as RTC clock 4423 * @arg @ref RCC_RTC_HSE_DIV12 : HSE Divided by 12 selected as RTC clock 4424 * @arg @ref RCC_RTC_HSE_DIV13 : HSE Divided by 13 selected as RTC clock 4425 * @arg @ref RCC_RTC_HSE_DIV14 : HSE Divided by 14 selected as RTC clock 4426 * @arg @ref RCC_RTC_HSE_DIV15 : HSE Divided by 15 selected as RTC clock 4427 * @arg @ref RCC_RTC_HSE_DIV16 : HSE Divided by 16 selected as RTC clock 4428 * @arg @ref RCC_RTC_HSE_DIV17 : HSE Divided by 17 selected as RTC clock 4429 * @arg @ref RCC_RTC_HSE_DIV18 : HSE Divided by 18 selected as RTC clock 4430 * @arg @ref RCC_RTC_HSE_DIV19 : HSE Divided by 19 selected as RTC clock 4431 * @arg @ref RCC_RTC_HSE_DIV20 : HSE Divided by 20 selected as RTC clock 4432 * @arg @ref RCC_RTC_HSE_DIV21 : HSE Divided by 21 selected as RTC clock 4433 * @arg @ref RCC_RTC_HSE_DIV22 : HSE Divided by 22 selected as RTC clock 4434 * @arg @ref RCC_RTC_HSE_DIV23 : HSE Divided by 23 selected as RTC clock 4435 * @arg @ref RCC_RTC_HSE_DIV24 : HSE Divided by 24 selected as RTC clock 4436 * @arg @ref RCC_RTC_HSE_DIV25 : HSE Divided by 25 selected as RTC clock 4437 * @arg @ref RCC_RTC_HSE_DIV26 : HSE Divided by 26 selected as RTC clock 4438 * @arg @ref RCC_RTC_HSE_DIV27 : HSE Divided by 27 selected as RTC clock 4439 * @arg @ref RCC_RTC_HSE_DIV28 : HSE Divided by 28 selected as RTC clock 4440 * @arg @ref RCC_RTC_HSE_DIV29 : HSE Divided by 29 selected as RTC clock 4441 * @arg @ref RCC_RTC_HSE_DIV30 : HSE Divided by 30 selected as RTC clock 4442 * @arg @ref RCC_RTC_HSE_DIV31 : HSE Divided by 31 selected as RTC clock 4443 * @arg @ref RCC_RTC_HSE_DIV32 : HSE Divided by 32 selected as RTC clock 4444 * @arg @ref RCC_RTC_HSE_DIV33 : HSE Divided by 33 selected as RTC clock 4445 * @arg @ref RCC_RTC_HSE_DIV34 : HSE Divided by 34 selected as RTC clock 4446 * @arg @ref RCC_RTC_HSE_DIV35 : HSE Divided by 35 selected as RTC clock 4447 * @arg @ref RCC_RTC_HSE_DIV36 : HSE Divided by 36 selected as RTC clock 4448 * @arg @ref RCC_RTC_HSE_DIV37 : HSE Divided by 37 selected as RTC clock 4449 * @arg @ref RCC_RTC_HSE_DIV38 : HSE Divided by 38 selected as RTC clock 4450 * @arg @ref RCC_RTC_HSE_DIV39 : HSE Divided by 39 selected as RTC clock 4451 * @arg @ref RCC_RTC_HSE_DIV40 : HSE Divided by 40 selected as RTC clock 4452 * @arg @ref RCC_RTC_HSE_DIV41 : HSE Divided by 41 selected as RTC clock 4453 * @arg @ref RCC_RTC_HSE_DIV42 : HSE Divided by 42 selected as RTC clock 4454 * @arg @ref RCC_RTC_HSE_DIV43 : HSE Divided by 43 selected as RTC clock 4455 * @arg @ref RCC_RTC_HSE_DIV44 : HSE Divided by 44 selected as RTC clock 4456 * @arg @ref RCC_RTC_HSE_DIV45 : HSE Divided by 45 selected as RTC clock 4457 * @arg @ref RCC_RTC_HSE_DIV46 : HSE Divided by 46 selected as RTC clock 4458 * @arg @ref RCC_RTC_HSE_DIV47 : HSE Divided by 47 selected as RTC clock 4459 * @arg @ref RCC_RTC_HSE_DIV48 : HSE Divided by 48 selected as RTC clock 4460 * @arg @ref RCC_RTC_HSE_DIV49 : HSE Divided by 49 selected as RTC clock 4461 * @arg @ref RCC_RTC_HSE_DIV50 : HSE Divided by 50 selected as RTC clock 4462 * @arg @ref RCC_RTC_HSE_DIV51 : HSE Divided by 51 selected as RTC clock 4463 * @arg @ref RCC_RTC_HSE_DIV52 : HSE Divided by 52 selected as RTC clock 4464 * @arg @ref RCC_RTC_HSE_DIV53 : HSE Divided by 53 selected as RTC clock 4465 * @arg @ref RCC_RTC_HSE_DIV54 : HSE Divided by 54 selected as RTC clock 4466 * @arg @ref RCC_RTC_HSE_DIV55 : HSE Divided by 55 selected as RTC clock 4467 * @arg @ref RCC_RTC_HSE_DIV56 : HSE Divided by 56 selected as RTC clock 4468 * @arg @ref RCC_RTC_HSE_DIV57 : HSE Divided by 57 selected as RTC clock 4469 * @arg @ref RCC_RTC_HSE_DIV58 : HSE Divided by 58 selected as RTC clock 4470 * @arg @ref RCC_RTC_HSE_DIV59 : HSE Divided by 59 selected as RTC clock 4471 * @arg @ref RCC_RTC_HSE_DIV60 : HSE Divided by 60 selected as RTC clock 4472 * @arg @ref RCC_RTC_HSE_DIV61 : HSE Divided by 61 selected as RTC clock 4473 * @arg @ref RCC_RTC_HSE_DIV62 : HSE Divided by 62 selected as RTC clock 4474 * @arg @ref RCC_RTC_HSE_DIV63 : HSE Divided by 63 selected as RTC clock 4475 */ 4476 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE))) 4477 4478 /** @brief Macros to enable or disable the main PLL. 4479 * @note After enabling the main PLL, the application software should wait on 4480 * PLLRDY flag to be set indicating that PLL clock is stable and can 4481 * be used as system clock source. 4482 * @note The main PLL can not be disabled if it is used as system clock source 4483 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4484 */ 4485 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 4486 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 4487 4488 /** 4489 * @brief Enables or disables each clock output (PLL1P_CLK, PLL1Q_CLK, PLL1R_CLK) 4490 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, 4491 * (except the ck_pll_p of the System PLL that cannot be stopped if used as System 4492 * Clock. This is mainly used to save Power. 4493 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 4494 * This parameter can be one of the following values: 4495 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 240MHz) 4496 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4497 * OCTOSPI, SPI, SAI and Ethernet 4498 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4499 * @retval None 4500 * 4501 */ 4502 #define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4503 4504 #define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4505 4506 /** 4507 * @brief Macro to get the PLL clock output enable status. 4508 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 4509 * This parameter can be one of the following values: 4510 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 240MHz) 4511 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4512 * OCTOSPI, SPI, SAI and Ethernet 4513 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4514 * @retval SET / RESET 4515 */ 4516 #define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4517 4518 /** 4519 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 4520 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 4521 * @retval None 4522 */ 4523 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4524 4525 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4526 4527 /** 4528 * @brief Macro to configures the main PLL (PLL1) clock source, multiplication and division factors. 4529 * @note This function must be used only when the main PLL1 is disabled. 4530 * 4531 * @param __PLLSOURCE__: specifies the PLL entry clock source. 4532 * This parameter can be one of the following values: 4533 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4534 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4535 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4536 * @note This clock source (__PLLSource__) is the clock source for PLL1 (main PLL) and is different 4537 from PLL2 & PLL3 clock sources. 4538 * 4539 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 4540 * This parameter must be a number between 1 and 63. 4541 * @note You have to set the PLL1M parameter correctly to ensure that the VCO input 4542 * frequency ranges from 1 to 16 MHz. 4543 * 4544 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 4545 * This parameter must be a number between 4 and 512. 4546 * @note You have to set the PLL1N parameter correctly to ensure that the VCO 4547 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 4548 * between 192 and 836 MHZ (when in wide VCO range) 4549 * 4550 * @param __PLL1P__: specifies the division factor for system clock. 4551 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 4552 * 4553 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 4554 * This parameter must be a number between 1 and 128 4555 * 4556 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 4557 * This parameter must be a number between 1 and 128 4558 * 4559 * @retval None 4560 */ 4561 #define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 4562 do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \ 4563 ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) | ((__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos));\ 4564 WRITE_REG(RCC->PLL1DIVR , ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) | \ 4565 ((((__PLL1P__) - 1U ) << RCC_PLL1DIVR_PLL1P_Pos) & RCC_PLL1DIVR_PLL1P) | \ 4566 ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) & RCC_PLL1DIVR_PLL1Q) | \ 4567 ((((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos) & RCC_PLL1DIVR_PLL1R))); \ 4568 } while(0) 4569 4570 /** @brief Macro to configure the PLL1 clock source. 4571 * @note This function must be used only when PLL1 is disabled. 4572 * @param __PLLSOURCE__: specifies the PLL1 entry clock source. 4573 * This parameter can be one of the following values: 4574 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4575 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4576 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4577 * 4578 */ 4579 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLLSOURCE__)) 4580 4581 /** @brief Macro to configure the PLL1 input clock division factor M. 4582 * 4583 * @note This function must be used only when the PLL1 is disabled. 4584 * @note PLL1 clock source is common with the main PLL (configured through 4585 * __HAL_RCC_PLL1_CONFIG() macro) 4586 * 4587 * @param __PLL1M__ specifies the division factor for PLL1 clock. 4588 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 4589 * In order to save power when PLL1 is not used, the value of PLL1M must be set to 0. 4590 * 4591 * @retval None 4592 */ 4593 #define __HAL_RCC_PLL1_DIVM_CONFIG(__PLL1M__) \ 4594 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos) 4595 4596 /** 4597 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor 4598 * 4599 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 4600 * 4601 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 4602 * It should be a value between 0 and 8191 4603 * @note Warning: The software has to set correctly these bits to insure that the VCO 4604 * output frequency is between its valid frequency range, which is: 4605 * 192 to 836 MHz if PLL1VCOSEL = 0 4606 * 150 to 420 MHz if PLL1VCOSEL = 1. 4607 * 4608 * 4609 * @retval None 4610 */ 4611 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ 4612 (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) 4613 4614 /** @brief Macro to select the PLL1 reference frequency range. 4615 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 4616 * This parameter can be one of the following values: 4617 * @arg RCC_PLL1_VCIRANGE_0: Range frequency is between 1 and 2 MHz 4618 * @arg RCC_PLL1_VCIRANGE_1: Range frequency is between 2 and 4 MHz 4619 * @arg RCC_PLL1_VCIRANGE_2: Range frequency is between 4 and 8 MHz 4620 * @arg RCC_PLL1_VCIRANGE_3: Range frequency is between 8 and 16 MHz 4621 * @retval None 4622 */ 4623 #define __HAL_RCC_PLL1_VCIRANGE(__PLL1VCIRange__) \ 4624 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 4625 4626 /** @brief Macro to select the PLL1 reference frequency range. 4627 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range 4628 * This parameter can be one of the following values: 4629 * @arg RCC_PLL1_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 4630 * @arg RCC_PLL1_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 4631 * 4632 * 4633 * @retval None 4634 */ 4635 #define __HAL_RCC_PLL1_VCORANGE(__RCC_PLL1VCORange__) \ 4636 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) 4637 4638 /** @brief Macro to get the oscillator used as PLL1 clock source. 4639 * @retval The oscillator used as PLL1 clock source. The returned value can be one 4640 * of the following: 4641 * - RCC_PLL1_SOURCE_NONE: No oscillator is used as PLL clock source. 4642 * - RCC_PLL1_SOURCE_CSI: CSI oscillator is used as PLL clock source. 4643 * - RCC_PLL1_SOURCE_HSI: HSI oscillator is used as PLL clock source. 4644 * - RCC_PLL1_SOURCE_HSE: HSE oscillator is used as PLL clock source. 4645 */ 4646 #define __HAL_RCC_GET_PLL1_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 4647 4648 /** 4649 * @brief Macro to configure the system clock source. 4650 * @param __SYSCLKSOURCE__: specifies the system clock source. 4651 * This parameter can be one of the following values: 4652 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. 4653 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4654 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4655 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1P output is used as system clock source. 4656 * @retval None 4657 */ 4658 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4659 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 4660 4661 /** @brief Macro to get the clock source used as system clock. 4662 * @retval The clock source used as system clock. The returned value can be one 4663 * of the following: 4664 * - RCC_SYSCLKSOURCE_STATUS_CSI: CSI used as system clock. 4665 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4666 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4667 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1P used as system clock. 4668 */ 4669 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 4670 4671 /** 4672 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4673 * @note As the LSE is in the Backup domain and write access is denied to 4674 * this domain after reset, you have to enable the write access using 4675 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4676 * (to be done once after reset). 4677 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 4678 * This parameter can be one of the following values: 4679 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4680 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4681 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4682 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4683 * @retval None 4684 */ 4685 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4686 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 4687 4688 /** 4689 * @brief Macro to configure the wake up from stop clock. 4690 * @note The configured clock is also used as emergency clock for the Clock Security System on HSE (HSECSS). 4691 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 4692 * This parameter can be one of the following values: 4693 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4694 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source 4695 * @retval None 4696 */ 4697 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4698 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 4699 4700 #define __HAL_RCC_HSECSS_RECOVCLK_CONFIG __HAL_RCC_WAKEUPSTOP_CLK_CONFIG 4701 4702 /** 4703 * @brief Macro to configure the Kernel wake up from stop clock. 4704 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 4705 * This parameter can be one of the following values: 4706 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source 4707 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 4708 * @retval None 4709 */ 4710 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 4711 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 4712 4713 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 4714 * @{ 4715 */ 4716 4717 /** @brief Macro to configure the MCO1 clock. 4718 * @param __MCOCLKSOURCE__ specifies the MCO1 clock source. 4719 * This parameter can be one of the following values: 4720 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 4721 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 4722 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 4723 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source 4724 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source 4725 * @param __MCODIV__ specifies the MCO clock prescaler. 4726 * This parameter can be one of the following values: 4727 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 4728 */ 4729 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4730 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4731 4732 /** @brief Macro to configure the MCO2 clock. 4733 * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. 4734 * This parameter can be one of the following values: 4735 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 4736 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source 4737 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 4738 * @arg RCC_MCO2SOURCE_PLL1PCLK: PLL1P clock selected as MCO2 source 4739 * @arg RCC_MCO2SOURCE_CSI: CSI clock selected as MCO2 source 4740 * @arg RCC_MCO2SOURCE_LSI: LSI clock selected as MCO2 source 4741 * @param __MCODIV__ specifies the MCO clock prescaler. 4742 * This parameter can be one of the following values: 4743 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 4744 */ 4745 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4746 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); 4747 4748 /** 4749 * @} 4750 */ 4751 4752 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4753 * @brief macros to manage the specified RCC Flags and interrupts. 4754 * @{ 4755 */ 4756 4757 /** @brief Enable RCC interrupt (Perform access to RCC_CIER[8:0] bits to enable 4758 * the selected interrupts). 4759 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4760 * This parameter can be any combination of the following values: 4761 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4762 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4763 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4764 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4765 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4766 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4767 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4768 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4769 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4770 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4771 * @retval None 4772 * 4773 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4774 */ 4775 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4776 4777 /** @brief Disable RCC interrupt (Perform access to RCC_CIER[8:0] bits to disable 4778 * the selected interrupts). 4779 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4780 * This parameter can be any combination of the following values: 4781 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4782 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4783 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4784 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4785 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4786 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4787 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4788 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4789 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4790 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4791 * @retval None 4792 * 4793 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4794 */ 4795 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4796 4797 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CICR[10:0] 4798 * bits to clear the selected interrupt pending bits. 4799 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4800 * This parameter can be any combination of the following values: 4801 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4802 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4803 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4804 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4805 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4806 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4807 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4808 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4809 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4810 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4811 * @retval None 4812 * 4813 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4814 */ 4815 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4816 4817 /** @brief Check whether the RCC interrupt has occurred or not. 4818 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4819 * This parameter can be one of the following values: 4820 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4821 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4822 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4823 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4824 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4825 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4826 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4827 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4828 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4829 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4830 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4831 * 4832 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4833 */ 4834 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4835 4836 /** @brief Set RMVF bit to clear the reset flags. 4837 * The reset flags are: RCC_FLAG_SFTRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4838 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4839 * @retval None 4840 */ 4841 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) 4842 4843 /** @brief Check whether the selected RCC flag is set or not. 4844 * @param __FLAG__: specifies the flag to check. 4845 * This parameter can be one of the following values: 4846 * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready 4847 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4848 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4849 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 4850 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4851 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready (*) 4852 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4853 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4854 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4855 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4856 * @arg @ref RCC_FLAG_HSIDIVF HSI Divider 4857 * @arg @ref RCC_FLAG_BORRST BOR reset 4858 * @arg @ref RCC_FLAG_PINRST Pin reset 4859 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 4860 * @arg @ref RCC_FLAG_SFTRST Software reset 4861 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4862 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4863 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4864 * @retval The new state of __FLAG__ (TRUE or FALSE). 4865 * 4866 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4867 */ 4868 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4869 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4870 ((((__FLAG__) >> 5U) == 3U) ? RCC->RSR : RCC->CIFR))) & \ 4871 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4872 /** 4873 * @} 4874 */ 4875 4876 /** 4877 * @} 4878 */ 4879 4880 /* Private constants ---------------------------------------------------------*/ 4881 /** @defgroup RCC_Private_Constants RCC Private Constants 4882 * @{ 4883 */ 4884 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 4885 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4886 #define CSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4887 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4888 #define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4889 #define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4890 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ 4891 4892 /* Defines used for Flags */ 4893 #define CR_REG_INDEX (1U) 4894 #define BDCR_REG_INDEX (2U) 4895 #define RSR_REG_INDEX (3U) 4896 4897 #define RCC_FLAG_MASK (0x1FU) 4898 4899 /* Defines Oscillator Masks */ 4900 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | \ 4901 RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) 4902 /*!< All Oscillator to configure */ 4903 4904 4905 /** 4906 * @} 4907 */ 4908 4909 /* Private macros ------------------------------------------------------------*/ 4910 /** @addtogroup RCC_Private_Macros 4911 * @{ 4912 */ 4913 4914 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4915 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 4916 4917 4918 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4919 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) 4920 4921 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4922 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) 4923 4924 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4925 4926 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 4927 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8)) 4928 4929 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4930 <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) 4931 4932 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4933 4934 #define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) 4935 4936 #define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4937 <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) 4938 4939 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4940 4941 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 4942 ((PLL) == RCC_PLL_ON)) 4943 4944 #define IS_RCC_PLL1_SOURCE(SOURCE) (((SOURCE) == RCC_PLL1_SOURCE_CSI) || \ 4945 ((SOURCE) == RCC_PLL1_SOURCE_HSI) || \ 4946 ((SOURCE) == RCC_PLL1_SOURCE_HSE)) 4947 4948 #define IS_RCC_PLL1_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4949 #define IS_RCC_PLL1_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4950 #define IS_RCC_PLL1_DIVP_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 128U)) 4951 #define IS_RCC_PLL1_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4952 #define IS_RCC_PLL1_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4953 4954 #define IS_RCC_PLL1_CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 4955 ((VALUE) == RCC_PLL1_DIVQ) || \ 4956 ((VALUE) == RCC_PLL1_DIVR)) 4957 4958 #define IS_RCC_PLL1_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCIRANGE_0) || \ 4959 ((VALUE) == RCC_PLL1_VCIRANGE_1) || \ 4960 ((VALUE) == RCC_PLL1_VCIRANGE_2) || \ 4961 ((VALUE) == RCC_PLL1_VCIRANGE_3)) 4962 4963 #define IS_RCC_PLL1_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCORANGE_WIDE) || ((VALUE) == RCC_PLL1_VCORANGE_MEDIUM)) 4964 4965 #define IS_RCC_PLL1_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 4966 4967 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) 4968 4969 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ 4970 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4971 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4972 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4973 4974 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 4975 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 4976 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 4977 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 4978 ((__HCLK__) == RCC_SYSCLK_DIV512)) 4979 4980 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 4981 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 4982 ((__PCLK__) == RCC_HCLK_DIV16)) 4983 4984 #define IS_RCC_RTCCLKSOURCE(SOURCE) \ 4985 (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 4986 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 4987 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 4988 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 4989 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 4990 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 4991 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 4992 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 4993 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 4994 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 4995 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 4996 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 4997 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 4998 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 4999 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 5000 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 5001 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 5002 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 5003 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 5004 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 5005 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 5006 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 5007 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 5008 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 5009 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 5010 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 5011 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 5012 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 5013 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 5014 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 5015 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 5016 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ 5017 ((SOURCE) == RCC_RTCCLKSOURCE_NO_CLK)) 5018 5019 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 5020 5021 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 5022 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1Q) || \ 5023 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 5024 5025 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2P) || \ 5026 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLL1P) || \ 5027 ((SOURCE) == RCC_MCO2SOURCE_CSI) || ((SOURCE) == RCC_MCO2SOURCE_LSI)) 5028 5029 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 5030 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 5031 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 5032 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 5033 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 5034 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 5035 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 5036 ((DIV) == RCC_MCODIV_15)) 5037 5038 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 5039 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 5040 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 5041 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 5042 5043 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 5044 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 5045 5046 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 5047 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 5048 5049 #if defined(RCC_SECCFGR_HSISEC) 5050 5051 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ALL) != 0U) && (((ITEM) & ~RCC_ALL) == 0U)) 5052 5053 #define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_HSI) || \ 5054 ((ITEM) == RCC_HSE) || \ 5055 ((ITEM) == RCC_CSI) || \ 5056 ((ITEM) == RCC_LSI) || \ 5057 ((ITEM) == RCC_LSE) || \ 5058 ((ITEM) == RCC_SYSCLK) || \ 5059 ((ITEM) == RCC_PRESC) || \ 5060 ((ITEM) == RCC_PLL1) || \ 5061 ((ITEM) == RCC_PLL2) || \ 5062 ((ITEM) == RCC_PLL3) || \ 5063 ((ITEM) == RCC_HSI48) || \ 5064 ((ITEM) == RCC_RMVF) || \ 5065 ((ITEM) == RCC_CKPERSEL)) 5066 #endif /* RCC_SECCFGR_HSISEC */ 5067 5068 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5069 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ 5070 ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ 5071 ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ 5072 ((ATTRIBUTES) == RCC_NSEC_NPRIV)) 5073 #elif defined(RCC_PRIVCFGR_NSPRIV) 5074 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) 5075 #else 5076 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NPRIV) || ((ATTRIBUTES) == RCC_PRIV)) 5077 #endif /* __ARM_FEATURE_CMSE */ 5078 /** 5079 * @} 5080 */ 5081 5082 /* Include RCC HAL Extended module */ 5083 #include "stm32h5xx_hal_rcc_ex.h" 5084 5085 /* Exported functions --------------------------------------------------------*/ 5086 /** @addtogroup RCC_Exported_Functions 5087 * @{ 5088 */ 5089 5090 /** @addtogroup RCC_Exported_Functions_Group1 5091 * @{ 5092 */ 5093 5094 /* Initialization and de-initialization functions ******************************/ 5095 HAL_StatusTypeDef HAL_RCC_DeInit(void); 5096 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pOscInitStruct); 5097 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t FLatency); 5098 5099 /** 5100 * @} 5101 */ 5102 5103 /** @addtogroup RCC_Exported_Functions_Group2 5104 * @{ 5105 */ 5106 5107 /* Peripheral Control functions **********************************************/ 5108 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 5109 void HAL_RCC_EnableCSS(void); 5110 uint32_t HAL_RCC_GetSysClockFreq(void); 5111 uint32_t HAL_RCC_GetHCLKFreq(void); 5112 uint32_t HAL_RCC_GetPCLK1Freq(void); 5113 uint32_t HAL_RCC_GetPCLK2Freq(void); 5114 uint32_t HAL_RCC_GetPCLK3Freq(void); 5115 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pOscInitStruct); 5116 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t *pFLatency); 5117 /* CSS NMI IRQ handler */ 5118 void HAL_RCC_NMI_IRQHandler(void); 5119 /* User Callbacks in non blocking mode (IT mode) */ 5120 void HAL_RCC_CSSCallback(void); 5121 uint32_t HAL_RCC_GetResetSource(void); 5122 5123 /** 5124 * @} 5125 */ 5126 5127 /** @addtogroup RCC_Exported_Functions_Group3 5128 * @{ 5129 */ 5130 5131 /* Attributes management functions ********************************************/ 5132 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 5133 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 5134 5135 /** 5136 * @} 5137 */ 5138 5139 /** 5140 * @} 5141 */ 5142 5143 /** 5144 * @} 5145 */ 5146 5147 /** 5148 * @} 5149 */ 5150 5151 #ifdef __cplusplus 5152 } 5153 #endif 5154 5155 #endif /* __STM32H5xx_HAL_RCC_H */ 5156
