1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32_HAL_LEGACY 23 #define STM32_HAL_LEGACY 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 /* Exported types ------------------------------------------------------------*/ 31 /* Exported constants --------------------------------------------------------*/ 32 33 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 34 * @{ 35 */ 36 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 37 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 38 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 39 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 40 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 41 #if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) 42 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 43 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 44 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 45 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 46 #if defined(STM32U5) 47 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 48 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 49 #endif /* STM32U5 */ 50 #endif /* STM32U5 || STM32H7 || STM32MP1 */ 51 /** 52 * @} 53 */ 54 55 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 56 * @{ 57 */ 58 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 59 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 60 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 61 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 62 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 63 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 64 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 65 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 66 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 67 #define REGULAR_GROUP ADC_REGULAR_GROUP 68 #define INJECTED_GROUP ADC_INJECTED_GROUP 69 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 70 #define AWD_EVENT ADC_AWD_EVENT 71 #define AWD1_EVENT ADC_AWD1_EVENT 72 #define AWD2_EVENT ADC_AWD2_EVENT 73 #define AWD3_EVENT ADC_AWD3_EVENT 74 #define OVR_EVENT ADC_OVR_EVENT 75 #define JQOVF_EVENT ADC_JQOVF_EVENT 76 #define ALL_CHANNELS ADC_ALL_CHANNELS 77 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 78 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 79 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 80 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 81 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 82 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 83 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 84 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 85 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 86 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 87 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 88 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 89 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 90 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 91 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 92 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 93 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 94 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 95 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 96 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 97 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 98 99 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 100 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 101 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 102 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 103 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 104 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 105 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 106 107 #if defined(STM32H7) 108 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 109 #endif /* STM32H7 */ 110 111 #if defined(STM32U5) 112 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 113 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 114 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 115 #endif /* STM32U5 */ 116 117 #if defined(STM32H5) 118 #define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE 119 #endif /* STM32H5 */ 120 /** 121 * @} 122 */ 123 124 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 125 * @{ 126 */ 127 128 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 129 130 /** 131 * @} 132 */ 133 134 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 135 * @{ 136 */ 137 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 138 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 139 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 140 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 141 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 142 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 143 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 144 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 145 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 146 #if defined(STM32L0) 147 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 148 #endif 149 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 150 #if defined(STM32F373xC) || defined(STM32F378xx) 151 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 152 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 153 #endif /* STM32F373xC || STM32F378xx */ 154 155 #if defined(STM32L0) || defined(STM32L4) 156 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 157 158 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 159 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 160 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 161 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 162 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 163 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 164 165 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 166 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 167 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 168 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 169 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 170 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 171 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 172 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 173 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 174 #if defined(STM32L0) 175 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 176 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 177 /* to the second dedicated IO (only for COMP2). */ 178 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 179 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 180 #else 181 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 182 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 183 #endif 184 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 185 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 186 187 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 188 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 189 190 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 191 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 192 #if defined(COMP_CSR_LOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_LOCK 194 #elif defined(COMP_CSR_COMP1LOCK) 195 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 196 #elif defined(COMP_CSR_COMPxLOCK) 197 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 198 #endif 199 200 #if defined(STM32L4) 201 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 202 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 203 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 204 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 205 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 206 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 207 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 208 #endif 209 210 #if defined(STM32L0) 211 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 213 #else 214 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 215 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 216 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 217 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 218 #endif 219 220 #endif 221 /** 222 * @} 223 */ 224 225 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 226 * @{ 227 */ 228 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 229 #if defined(STM32U5) 230 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 231 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 232 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 233 #endif /* STM32U5 */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup CRC_Aliases CRC API aliases 239 * @{ 240 */ 241 #if defined(STM32H5) || defined(STM32C0) 242 #else 243 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 244 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 245 #endif 246 /** 247 * @} 248 */ 249 250 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 251 * @{ 252 */ 253 254 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 255 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 256 257 /** 258 * @} 259 */ 260 261 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 262 * @{ 263 */ 264 265 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 266 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 267 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 268 #define DAC_WAVE_NONE 0x00000000U 269 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 270 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 271 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 272 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 273 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 274 275 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 276 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 277 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 278 #endif 279 280 #if defined(STM32U5) 281 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 282 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 283 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 284 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 285 #endif 286 287 #if defined(STM32H5) 288 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 289 #define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 290 #endif 291 292 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 293 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 294 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 295 #endif 296 297 /** 298 * @} 299 */ 300 301 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 302 * @{ 303 */ 304 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 305 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 306 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 307 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 308 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 309 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 310 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 311 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 312 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 313 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 314 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 315 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 316 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 317 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 318 319 #define IS_HAL_REMAPDMA IS_DMA_REMAP 320 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 321 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 322 323 #if defined(STM32L4) 324 325 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 326 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 327 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 328 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 332 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 333 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 334 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 335 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 336 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 337 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 338 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 339 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 340 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 341 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 342 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 343 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 344 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 345 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 346 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 347 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 348 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 349 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 350 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 351 352 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 353 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 354 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 355 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 356 357 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 358 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 359 #endif 360 361 #endif /* STM32L4 */ 362 363 #if defined(STM32G0) 364 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 365 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 366 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 367 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 368 369 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 370 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 371 #endif 372 373 #if defined(STM32H7) 374 375 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 376 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 377 378 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 379 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 380 381 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 382 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 383 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 384 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 385 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 386 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 387 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 388 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 389 390 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 391 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 392 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 393 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 394 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 395 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 396 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 397 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 398 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 399 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 400 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 401 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 402 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 403 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 404 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 405 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 406 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 407 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 408 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 409 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 410 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 411 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 412 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 413 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 414 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 415 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 416 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 417 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 418 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 419 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 420 421 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 422 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 423 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 424 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 425 426 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 427 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 428 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 429 430 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 431 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 432 433 #endif /* STM32H7 */ 434 435 #if defined(STM32U5) 436 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 437 #endif /* STM32U5 */ 438 /** 439 * @} 440 */ 441 442 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 443 * @{ 444 */ 445 446 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 447 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 448 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 449 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 450 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 451 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 452 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 453 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 454 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 455 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 456 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 457 #define OBEX_PCROP OPTIONBYTE_PCROP 458 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 459 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 460 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 461 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 462 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 463 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 464 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 465 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 466 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 467 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 468 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 469 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 470 #define PAGESIZE FLASH_PAGE_SIZE 471 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 472 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 473 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 474 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 475 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 476 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 477 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 478 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 479 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 480 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 481 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 482 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 483 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 484 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 485 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 486 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 487 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 488 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 489 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 490 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 491 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 492 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 493 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 494 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 495 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 496 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 497 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 498 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 499 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 500 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 501 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 502 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 503 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 504 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 505 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 506 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 507 #define OB_WDG_SW OB_IWDG_SW 508 #define OB_WDG_HW OB_IWDG_HW 509 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 510 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 511 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 512 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 513 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 514 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 515 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 516 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 517 #if defined(STM32G0) || defined(STM32C0) 518 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 519 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 520 #else 521 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 522 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 523 #endif 524 #if defined(STM32H7) 525 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 526 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 527 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 528 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 529 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 530 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 531 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 532 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 533 #endif /* STM32H7 */ 534 #if defined(STM32U5) 535 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 536 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 537 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 538 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 539 #define OB_USER_nBOOT0 OB_USER_NBOOT0 540 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 541 #define OB_nBOOT0_SET OB_NBOOT0_SET 542 #endif /* STM32U5 */ 543 544 /** 545 * @} 546 */ 547 548 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 549 * @{ 550 */ 551 552 #if defined(STM32H7) 553 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 554 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 555 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 556 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 557 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 558 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 559 #endif /* STM32H7 */ 560 561 /** 562 * @} 563 */ 564 565 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 566 * @{ 567 */ 568 569 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 570 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 571 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 572 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 573 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 574 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 575 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 576 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 577 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 578 #if defined(STM32G4) 579 580 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 581 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 582 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 583 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 584 #endif /* STM32G4 */ 585 586 #if defined(STM32H5) 587 #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC 588 #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC 589 #define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC 590 #define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC 591 #define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC 592 #define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC 593 594 #define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC 595 #define SYSCFG_BREAK_PVD SBS_BREAK_PVD 596 #define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC 597 #define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP 598 599 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 600 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 601 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 602 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 603 604 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE 605 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE 606 607 #define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 608 #define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 609 #define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 610 #define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 611 612 #define SYSCFG_ETH_MII SBS_ETH_MII 613 #define SYSCFG_ETH_RMII SBS_ETH_RMII 614 #define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG 615 616 #define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE 617 #define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR 618 #define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG 619 620 #define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG 621 622 #define SYSCFG_MPU_NSEC SBS_MPU_NSEC 623 #define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC 624 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 625 #define SYSCFG_SAU SBS_SAU 626 #define SYSCFG_MPU_SEC SBS_MPU_SEC 627 #define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC 628 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 629 #else 630 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 631 #endif /* __ARM_FEATURE_CMSE */ 632 633 #define SYSCFG_CLK SBS_CLK 634 #define SYSCFG_CLASSB SBS_CLASSB 635 #define SYSCFG_FPU SBS_FPU 636 #define SYSCFG_ALL SBS_ALL 637 638 #define SYSCFG_SEC SBS_SEC 639 #define SYSCFG_NSEC SBS_NSEC 640 641 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE 642 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE 643 644 #define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK 645 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK 646 #define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK 647 #define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK 648 649 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE 650 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE 651 652 #define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS 653 #define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS 654 655 #define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT 656 #define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG 657 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE 658 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE 659 #define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING 660 #define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS 661 #define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES 662 #define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES 663 #define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS 664 665 #define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig 666 #define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig 667 #define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig 668 #define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF 669 #define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF 670 671 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster 672 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster 673 #define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect 674 675 #define HAL_SYSCFG_Lock HAL_SBS_Lock 676 #define HAL_SYSCFG_GetLock HAL_SBS_GetLock 677 678 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 679 #define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes 680 #define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes 681 #endif /* __ARM_FEATURE_CMSE */ 682 683 #endif /* STM32H5 */ 684 685 686 /** 687 * @} 688 */ 689 690 691 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 692 * @{ 693 */ 694 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 695 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 696 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 697 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 698 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 699 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 700 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 701 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 702 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 703 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 704 #endif 705 /** 706 * @} 707 */ 708 709 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 710 * @{ 711 */ 712 713 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 714 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 715 /** 716 * @} 717 */ 718 719 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 720 * @{ 721 */ 722 #define GET_GPIO_SOURCE GPIO_GET_INDEX 723 #define GET_GPIO_INDEX GPIO_GET_INDEX 724 725 #if defined(STM32F4) 726 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 727 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 728 #endif 729 730 #if defined(STM32F7) 731 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 732 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 733 #endif 734 735 #if defined(STM32L4) 736 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 737 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 738 #endif 739 740 #if defined(STM32H7) 741 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 742 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 743 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 744 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 745 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 746 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 747 748 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 749 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 750 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 751 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 752 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 753 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 754 #endif /* STM32H7 */ 755 756 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 757 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 758 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 759 760 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 761 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 762 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 763 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 764 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 765 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 766 767 #if defined(STM32L1) 768 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 769 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 770 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 771 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 772 #endif /* STM32L1 */ 773 774 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 775 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 776 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 777 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 778 #endif /* STM32F0 || STM32F3 || STM32F1 */ 779 780 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 781 782 #if defined(STM32U5) || defined(STM32H5) 783 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 784 #endif /* STM32U5 || STM32H5 */ 785 #if defined(STM32U5) 786 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 787 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 788 #endif /* STM32U5 */ 789 /** 790 * @} 791 */ 792 793 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 794 * @{ 795 */ 796 #if defined(STM32U5) 797 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 798 #endif /* STM32U5 */ 799 /** 800 * @} 801 */ 802 803 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 804 * @{ 805 */ 806 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 807 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 808 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 809 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 810 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 811 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 812 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 813 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 814 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 815 816 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 817 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 818 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 819 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 820 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 821 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 822 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 823 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 824 825 #if defined(STM32G4) 826 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 827 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 828 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 829 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 830 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 831 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 832 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 833 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 834 #endif /* STM32G4 */ 835 836 #if defined(STM32H7) 837 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 838 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 839 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 840 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 841 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 842 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 843 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 844 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 845 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 846 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 847 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 848 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 849 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 850 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 851 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 852 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 853 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 854 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 855 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 856 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 857 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 858 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 859 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 860 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 861 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 862 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 863 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 864 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 865 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 866 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 867 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 868 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 869 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 870 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 871 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 872 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 873 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 874 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 875 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 876 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 877 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 878 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 879 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 880 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 881 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 882 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 883 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 884 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 885 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 886 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 887 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 888 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 889 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 890 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 891 892 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 893 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 894 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 895 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 896 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 897 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 898 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 899 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 900 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 901 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 902 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 903 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 904 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 905 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 906 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 907 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 908 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 909 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 910 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 911 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 912 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 913 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 914 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 915 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 916 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 917 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 918 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 919 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 920 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 921 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 922 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 923 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 924 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 925 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 926 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 927 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 928 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 929 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 930 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 931 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 932 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 933 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 934 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 935 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 936 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 937 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 938 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 939 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 940 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 941 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 942 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 943 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 944 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 945 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 946 #endif /* STM32H7 */ 947 948 #if defined(STM32F3) 949 /** @brief Constants defining available sources associated to external events. 950 */ 951 #define HRTIM_EVENTSRC_1 (0x00000000U) 952 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 953 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 954 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 955 956 /** @brief Constants defining the DLL calibration periods (in micro seconds) 957 */ 958 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 959 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 960 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 961 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 962 963 #endif /* STM32F3 */ 964 /** 965 * @} 966 */ 967 968 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 969 * @{ 970 */ 971 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 972 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 973 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 974 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 975 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 976 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 977 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 978 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 979 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 980 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 981 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 982 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 983 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 984 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 985 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 986 #endif 987 /** 988 * @} 989 */ 990 991 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 992 * @{ 993 */ 994 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 995 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 996 997 /** 998 * @} 999 */ 1000 1001 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 1002 * @{ 1003 */ 1004 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 1005 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 1006 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 1007 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 1008 /** 1009 * @} 1010 */ 1011 1012 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1013 * @{ 1014 */ 1015 1016 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 1017 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 1018 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 1019 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 1020 1021 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 1022 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 1023 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 1024 1025 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 1026 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1027 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1028 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1029 1030 /* The following 3 definition have also been present in a temporary version of lptim.h */ 1031 /* They need to be renamed also to the right name, just in case */ 1032 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1033 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1034 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1035 1036 1037 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1038 * @{ 1039 */ 1040 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 1041 /** 1042 * @} 1043 */ 1044 1045 #if defined(STM32U5) 1046 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 1047 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 1048 #define LPTIM_CHANNEL_ALL 0x00000000U 1049 #endif /* STM32U5 */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 1055 * @{ 1056 */ 1057 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 1058 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 1059 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 1060 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 1061 1062 #define NAND_AddressTypedef NAND_AddressTypeDef 1063 1064 #define __ARRAY_ADDRESS ARRAY_ADDRESS 1065 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 1066 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 1067 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 1068 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 1069 /** 1070 * @} 1071 */ 1072 1073 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 1074 * @{ 1075 */ 1076 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 1077 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 1078 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 1079 #define NOR_ERROR HAL_NOR_STATUS_ERROR 1080 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 1081 1082 #define __NOR_WRITE NOR_WRITE 1083 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 1084 /** 1085 * @} 1086 */ 1087 1088 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 1089 * @{ 1090 */ 1091 1092 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 1093 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 1094 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 1095 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 1096 1097 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 1098 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 1099 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 1100 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 1101 1102 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1103 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1104 1105 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1106 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1107 1108 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1109 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1110 1111 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1112 1113 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1114 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1115 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1116 1117 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 1118 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1119 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1120 #endif 1121 1122 #if defined(STM32L4) || defined(STM32L5) 1123 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1124 #elif defined(STM32G4) 1125 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1126 #endif 1127 1128 /** 1129 * @} 1130 */ 1131 1132 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1133 * @{ 1134 */ 1135 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1136 1137 #if defined(STM32H7) 1138 #define I2S_IT_TXE I2S_IT_TXP 1139 #define I2S_IT_RXNE I2S_IT_RXP 1140 1141 #define I2S_FLAG_TXE I2S_FLAG_TXP 1142 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1143 #endif 1144 1145 #if defined(STM32F7) 1146 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1147 #endif 1148 /** 1149 * @} 1150 */ 1151 1152 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1153 * @{ 1154 */ 1155 1156 /* Compact Flash-ATA registers description */ 1157 #define CF_DATA ATA_DATA 1158 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1159 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1160 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1161 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1162 #define CF_CARD_HEAD ATA_CARD_HEAD 1163 #define CF_STATUS_CMD ATA_STATUS_CMD 1164 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1165 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1166 1167 /* Compact Flash-ATA commands */ 1168 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1169 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1170 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1171 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1172 1173 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1174 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1175 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1176 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1177 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1178 /** 1179 * @} 1180 */ 1181 1182 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1183 * @{ 1184 */ 1185 1186 #define FORMAT_BIN RTC_FORMAT_BIN 1187 #define FORMAT_BCD RTC_FORMAT_BCD 1188 1189 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1190 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1191 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1192 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1193 1194 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1195 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1196 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1197 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1198 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1199 1200 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1201 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1202 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1203 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1204 1205 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1206 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1207 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1208 1209 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1210 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1211 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1212 1213 #if defined(STM32F7) 1214 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1215 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1216 #endif /* STM32F7 */ 1217 1218 #if defined(STM32H7) 1219 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1220 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1221 #endif /* STM32H7 */ 1222 1223 #if defined(STM32F7) || defined(STM32H7) 1224 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1225 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1226 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1227 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1228 #endif /* STM32F7 || STM32H7 */ 1229 1230 /** 1231 * @} 1232 */ 1233 1234 1235 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1236 * @{ 1237 */ 1238 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1239 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1240 1241 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1242 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1243 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1244 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1245 1246 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1247 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1248 1249 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1250 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1251 /** 1252 * @} 1253 */ 1254 1255 1256 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1257 * @{ 1258 */ 1259 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1260 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1261 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1262 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1263 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1264 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1265 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1266 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1267 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1268 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1269 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1275 * @{ 1276 */ 1277 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1278 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1279 1280 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1281 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1282 1283 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1284 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1285 1286 #if defined(STM32H7) 1287 1288 #define SPI_FLAG_TXE SPI_FLAG_TXP 1289 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1290 1291 #define SPI_IT_TXE SPI_IT_TXP 1292 #define SPI_IT_RXNE SPI_IT_RXP 1293 1294 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1295 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1296 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1297 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1298 1299 #endif /* STM32H7 */ 1300 1301 /** 1302 * @} 1303 */ 1304 1305 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1306 * @{ 1307 */ 1308 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1309 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1310 1311 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1312 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1313 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1314 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1315 #define TIM_DMABase_SR TIM_DMABASE_SR 1316 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1317 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1318 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1319 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1320 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1321 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1322 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1323 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1324 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1325 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1326 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1327 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1328 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1329 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1330 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1331 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1332 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1333 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1334 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1335 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1336 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1337 #define TIM_DMABase_OR TIM_DMABASE_OR 1338 1339 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1340 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1341 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1342 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1343 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1344 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1345 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1346 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1347 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1348 1349 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1350 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1351 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1352 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1353 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1354 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1355 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1356 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1357 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1358 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1359 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1360 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1361 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1362 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1363 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1364 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1365 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1366 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1367 1368 #if defined(STM32L0) 1369 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1370 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1371 #endif 1372 1373 #if defined(STM32F3) 1374 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1375 #endif 1376 1377 #if defined(STM32H7) 1378 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1379 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1380 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1381 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1382 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1383 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1384 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1385 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1386 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1387 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1388 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1389 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1390 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1391 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1392 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1393 #endif 1394 1395 #if defined(STM32U5) || defined(STM32MP2) 1396 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1397 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1398 #endif 1399 /** 1400 * @} 1401 */ 1402 1403 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1404 * @{ 1405 */ 1406 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1407 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1408 /** 1409 * @} 1410 */ 1411 1412 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1413 * @{ 1414 */ 1415 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1416 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1417 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1418 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1419 1420 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1421 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1422 1423 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1424 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1425 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1426 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1427 1428 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1429 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1430 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1431 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1432 1433 #define __DIV_LPUART UART_DIV_LPUART 1434 1435 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1436 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1437 1438 /** 1439 * @} 1440 */ 1441 1442 1443 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1444 * @{ 1445 */ 1446 1447 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1448 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1449 1450 #define USARTNACK_ENABLED USART_NACK_ENABLE 1451 #define USARTNACK_DISABLED USART_NACK_DISABLE 1452 /** 1453 * @} 1454 */ 1455 1456 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1457 * @{ 1458 */ 1459 #define CFR_BASE WWDG_CFR_BASE 1460 1461 /** 1462 * @} 1463 */ 1464 1465 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1466 * @{ 1467 */ 1468 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1469 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1470 #define CAN_IT_RQCP0 CAN_IT_TME 1471 #define CAN_IT_RQCP1 CAN_IT_TME 1472 #define CAN_IT_RQCP2 CAN_IT_TME 1473 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1474 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1475 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1476 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1477 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1478 1479 /** 1480 * @} 1481 */ 1482 1483 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1484 * @{ 1485 */ 1486 1487 #define VLAN_TAG ETH_VLAN_TAG 1488 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1489 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1490 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1491 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1492 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1493 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1494 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1495 1496 #define ETH_MMCCR 0x00000100U 1497 #define ETH_MMCRIR 0x00000104U 1498 #define ETH_MMCTIR 0x00000108U 1499 #define ETH_MMCRIMR 0x0000010CU 1500 #define ETH_MMCTIMR 0x00000110U 1501 #define ETH_MMCTGFSCCR 0x0000014CU 1502 #define ETH_MMCTGFMSCCR 0x00000150U 1503 #define ETH_MMCTGFCR 0x00000168U 1504 #define ETH_MMCRFCECR 0x00000194U 1505 #define ETH_MMCRFAECR 0x00000198U 1506 #define ETH_MMCRGUFCR 0x000001C4U 1507 1508 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1509 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1510 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1511 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1512 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1513 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1514 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1515 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1516 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1517 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1518 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1519 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1520 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1521 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1522 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1523 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1524 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1525 #if defined(STM32F1) 1526 #else 1527 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1528 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1529 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1530 #endif 1531 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1532 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1533 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1534 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1535 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1536 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1537 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1538 1539 /** 1540 * @} 1541 */ 1542 1543 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1544 * @{ 1545 */ 1546 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1547 #define DCMI_IT_OVF DCMI_IT_OVR 1548 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1549 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1550 1551 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1552 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1553 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1554 1555 /** 1556 * @} 1557 */ 1558 1559 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1560 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1561 || defined(STM32H7) 1562 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1563 * @{ 1564 */ 1565 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1566 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1567 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1568 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1569 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1570 1571 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1572 #define CM_RGB888 DMA2D_INPUT_RGB888 1573 #define CM_RGB565 DMA2D_INPUT_RGB565 1574 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1575 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1576 #define CM_L8 DMA2D_INPUT_L8 1577 #define CM_AL44 DMA2D_INPUT_AL44 1578 #define CM_AL88 DMA2D_INPUT_AL88 1579 #define CM_L4 DMA2D_INPUT_L4 1580 #define CM_A8 DMA2D_INPUT_A8 1581 #define CM_A4 DMA2D_INPUT_A4 1582 /** 1583 * @} 1584 */ 1585 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1586 1587 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1588 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1589 || defined(STM32H7) || defined(STM32U5) 1590 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1591 * @{ 1592 */ 1593 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1594 for compatibility with legacy code */ 1595 /** 1596 * @} 1597 */ 1598 1599 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1600 1601 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1602 * @{ 1603 */ 1604 1605 /** 1606 * @} 1607 */ 1608 1609 /* Exported functions --------------------------------------------------------*/ 1610 1611 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1612 * @{ 1613 */ 1614 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1615 /** 1616 * @} 1617 */ 1618 1619 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1620 * @{ 1621 */ 1622 1623 #if defined(STM32U5) 1624 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1625 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1626 #endif /* STM32U5 */ 1627 1628 /** 1629 * @} 1630 */ 1631 1632 #if !defined(STM32F2) 1633 /** @defgroup HASH_alias HASH API alias 1634 * @{ 1635 */ 1636 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1637 /** 1638 * 1639 * @} 1640 */ 1641 #endif /* STM32F2 */ 1642 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1643 * @{ 1644 */ 1645 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1646 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1647 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1648 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1649 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1650 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1651 1652 /*HASH Algorithm Selection*/ 1653 1654 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1655 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1656 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1657 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1658 1659 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1660 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1661 1662 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1663 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1664 1665 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1666 1667 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1668 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1669 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1670 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1671 1672 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1673 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1674 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1675 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1676 1677 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1678 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1679 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1680 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1681 1682 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1683 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1684 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1685 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1686 1687 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1688 /** 1689 * @} 1690 */ 1691 1692 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1693 * @{ 1694 */ 1695 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1696 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1697 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1698 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1699 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1700 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1701 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1702 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1703 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1704 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1705 #if defined(STM32L0) 1706 #else 1707 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1708 #endif 1709 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1710 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1711 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1712 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1713 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1714 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1715 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1716 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1717 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1718 1719 /** 1720 * @} 1721 */ 1722 1723 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1724 * @{ 1725 */ 1726 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1727 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1728 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1729 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1730 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1731 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1732 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1733 1734 /** 1735 * @} 1736 */ 1737 1738 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1739 * @{ 1740 */ 1741 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1742 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1743 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1744 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1745 1746 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1747 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1748 1749 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1750 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1751 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1752 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1753 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1754 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1755 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1756 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1757 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1758 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1759 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1760 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1761 1762 #if defined(STM32F4) 1763 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1764 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1765 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1766 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1767 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1768 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1769 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1770 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1771 #endif /* STM32F4 */ 1772 /** 1773 * @} 1774 */ 1775 1776 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1777 * @{ 1778 */ 1779 1780 #if defined(STM32G0) 1781 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1782 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1783 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1784 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1785 #endif 1786 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1787 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1788 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1789 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1790 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1791 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1792 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1793 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1794 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1795 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1796 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1797 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1798 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1799 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1800 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1801 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1802 1803 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1804 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1805 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1806 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1807 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1808 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1809 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1810 1811 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1812 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1813 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1814 #define CR_PMODE_BB CR_VOS_BB 1815 1816 #define DBP_BitNumber DBP_BIT_NUMBER 1817 #define PVDE_BitNumber PVDE_BIT_NUMBER 1818 #define PMODE_BitNumber PMODE_BIT_NUMBER 1819 #define EWUP_BitNumber EWUP_BIT_NUMBER 1820 #define FPDS_BitNumber FPDS_BIT_NUMBER 1821 #define ODEN_BitNumber ODEN_BIT_NUMBER 1822 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1823 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1824 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1825 #define BRE_BitNumber BRE_BIT_NUMBER 1826 1827 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1828 1829 #if defined (STM32U5) 1830 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1831 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1832 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1833 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1834 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1835 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1836 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1837 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1838 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1839 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1840 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1841 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1842 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1843 1844 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1845 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1846 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1847 1848 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1849 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1850 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1851 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1852 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1853 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1854 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1855 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1856 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1857 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1858 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1859 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1860 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1861 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1862 1863 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1864 1865 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1866 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1867 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1868 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1869 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1870 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1871 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1872 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1873 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1874 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1875 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1876 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1877 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1878 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1879 1880 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1881 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1882 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1883 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1884 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1885 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1886 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1887 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1888 1889 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1890 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1891 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1892 1893 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1894 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1895 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1896 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1897 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1898 1899 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1900 #endif 1901 1902 /** 1903 * @} 1904 */ 1905 1906 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1907 * @{ 1908 */ 1909 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1910 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1911 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1912 /** 1913 * @} 1914 */ 1915 1916 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1917 * @{ 1918 */ 1919 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1920 /** 1921 * @} 1922 */ 1923 1924 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1925 * @{ 1926 */ 1927 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1928 #define HAL_TIM_DMAError TIM_DMAError 1929 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1930 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1931 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1932 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1933 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1934 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1935 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1936 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1937 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1938 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1939 /** 1940 * @} 1941 */ 1942 1943 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1944 * @{ 1945 */ 1946 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1947 /** 1948 * @} 1949 */ 1950 1951 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1952 * @{ 1953 */ 1954 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1955 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1956 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1957 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1958 /** 1959 * @} 1960 */ 1961 1962 1963 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1964 * @{ 1965 */ 1966 1967 /** 1968 * @} 1969 */ 1970 1971 /* Exported macros ------------------------------------------------------------*/ 1972 1973 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1974 * @{ 1975 */ 1976 #define AES_IT_CC CRYP_IT_CC 1977 #define AES_IT_ERR CRYP_IT_ERR 1978 #define AES_FLAG_CCF CRYP_FLAG_CCF 1979 /** 1980 * @} 1981 */ 1982 1983 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1984 * @{ 1985 */ 1986 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1987 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1988 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1989 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1990 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1991 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1992 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1993 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1994 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1995 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1996 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1997 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1998 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1999 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 2000 2001 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 2002 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 2003 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 2004 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 2005 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 2006 2007 /** 2008 * @} 2009 */ 2010 2011 2012 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 2013 * @{ 2014 */ 2015 #define __ADC_ENABLE __HAL_ADC_ENABLE 2016 #define __ADC_DISABLE __HAL_ADC_DISABLE 2017 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 2018 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 2019 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 2020 #define __ADC_IS_ENABLED ADC_IS_ENABLE 2021 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 2022 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 2023 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 2024 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 2025 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 2026 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 2027 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 2028 2029 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 2030 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 2031 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 2032 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 2033 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 2034 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 2035 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 2036 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 2037 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 2038 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 2039 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 2040 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 2041 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 2042 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 2043 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 2044 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 2045 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 2046 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 2047 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 2048 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 2049 2050 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 2051 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 2052 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 2053 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 2054 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 2055 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2056 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2057 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 2058 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 2059 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 2060 2061 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 2062 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 2063 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 2064 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 2065 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 2066 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 2067 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 2068 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 2069 2070 #define __HAL_ADC_SQR1 ADC_SQR1 2071 #define __HAL_ADC_SMPR1 ADC_SMPR1 2072 #define __HAL_ADC_SMPR2 ADC_SMPR2 2073 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 2074 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 2075 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 2076 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 2077 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 2078 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 2079 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 2080 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 2081 #define __HAL_ADC_JSQR ADC_JSQR 2082 2083 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 2084 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 2085 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 2086 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 2087 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 2088 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 2089 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 2090 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 2091 2092 /** 2093 * @} 2094 */ 2095 2096 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2097 * @{ 2098 */ 2099 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 2100 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 2101 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 2102 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 2103 2104 /** 2105 * @} 2106 */ 2107 2108 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2109 * @{ 2110 */ 2111 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2112 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2113 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2114 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2115 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2116 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2117 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2118 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2119 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2120 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2121 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2122 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2123 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2124 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2125 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2126 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2127 2128 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2129 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2130 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2131 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2132 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2133 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2134 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2135 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2136 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2137 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2138 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2139 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2140 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2141 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2142 2143 2144 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2145 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2146 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2147 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2148 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2149 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2150 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2151 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2152 #if defined(STM32H7) 2153 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2154 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2155 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2156 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2157 #else 2158 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2159 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2160 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2161 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2162 #endif /* STM32H7 */ 2163 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2164 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2165 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2166 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2167 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2168 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2169 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2170 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2171 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2172 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2173 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2174 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2175 2176 /** 2177 * @} 2178 */ 2179 2180 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2181 * @{ 2182 */ 2183 #if defined(STM32F3) 2184 #define COMP_START __HAL_COMP_ENABLE 2185 #define COMP_STOP __HAL_COMP_DISABLE 2186 #define COMP_LOCK __HAL_COMP_LOCK 2187 2188 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2189 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2190 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2191 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2192 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2193 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2194 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2195 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2196 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2197 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2198 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2199 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2200 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2201 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2202 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2203 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2204 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2205 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2206 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2207 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2208 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2209 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2210 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2211 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2212 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2213 # endif 2214 # if defined(STM32F302xE) || defined(STM32F302xC) 2215 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2216 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2217 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2218 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2219 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2220 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2221 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2222 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2223 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2224 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2225 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2226 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2227 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2228 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2229 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2230 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2231 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2232 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2233 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2234 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2235 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2236 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2237 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2238 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2239 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2240 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2241 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2242 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2243 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2244 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2245 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2246 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2247 # endif 2248 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2249 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2250 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2251 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2252 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2253 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2254 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2255 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2256 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2257 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2258 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2259 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2260 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2261 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2262 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2263 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2264 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2265 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2266 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2267 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2268 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2269 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2270 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2271 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2272 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2273 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2274 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2275 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2276 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2277 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2278 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2279 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2280 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2281 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2282 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2283 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2284 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2285 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2286 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2287 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2288 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2289 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2290 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2291 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2292 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2293 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2294 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2295 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2296 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2297 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2298 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2299 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2300 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2301 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2302 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2303 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2304 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2305 # endif 2306 # if defined(STM32F373xC) ||defined(STM32F378xx) 2307 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2308 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2309 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2310 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2311 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2312 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2313 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2314 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2315 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2316 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2317 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2318 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2319 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2320 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2321 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2322 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2323 # endif 2324 #else 2325 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2326 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2327 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2328 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2329 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2330 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2331 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2332 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2333 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2334 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2335 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2336 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2337 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2338 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2339 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2340 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2341 #endif 2342 2343 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2344 2345 #if defined(STM32L0) || defined(STM32L4) 2346 /* Note: On these STM32 families, the only argument of this macro */ 2347 /* is COMP_FLAG_LOCK. */ 2348 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2349 /* argument. */ 2350 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2351 #endif 2352 /** 2353 * @} 2354 */ 2355 2356 #if defined(STM32L0) || defined(STM32L4) 2357 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2358 * @{ 2359 */ 2360 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2361 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2362 /** 2363 * @} 2364 */ 2365 #endif 2366 2367 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2368 * @{ 2369 */ 2370 2371 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2372 ((WAVE) == DAC_WAVE_NOISE)|| \ 2373 ((WAVE) == DAC_WAVE_TRIANGLE)) 2374 2375 /** 2376 * @} 2377 */ 2378 2379 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2380 * @{ 2381 */ 2382 2383 #define IS_WRPAREA IS_OB_WRPAREA 2384 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2385 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2386 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2387 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2388 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2389 2390 /** 2391 * @} 2392 */ 2393 2394 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2395 * @{ 2396 */ 2397 2398 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2399 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2400 #if defined(STM32F1) 2401 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2402 #else 2403 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2404 #endif /* STM32F1 */ 2405 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2406 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2407 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2408 #define __HAL_I2C_SPEED I2C_SPEED 2409 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2410 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2411 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2412 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2413 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2414 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2415 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2416 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2417 /** 2418 * @} 2419 */ 2420 2421 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2422 * @{ 2423 */ 2424 2425 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2426 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2427 2428 #if defined(STM32H7) 2429 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2430 #endif 2431 2432 /** 2433 * @} 2434 */ 2435 2436 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2437 * @{ 2438 */ 2439 2440 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2441 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2442 2443 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2444 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2445 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2446 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2447 2448 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2449 2450 2451 /** 2452 * @} 2453 */ 2454 2455 2456 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2457 * @{ 2458 */ 2459 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2460 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2461 /** 2462 * @} 2463 */ 2464 2465 2466 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2467 * @{ 2468 */ 2469 2470 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2471 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2472 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2473 2474 /** 2475 * @} 2476 */ 2477 2478 2479 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2480 * @{ 2481 */ 2482 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2483 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2484 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2485 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2486 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2487 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2488 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2489 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2490 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2491 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2492 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2493 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2494 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2495 2496 /** 2497 * @} 2498 */ 2499 2500 2501 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2502 * @{ 2503 */ 2504 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2505 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2506 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2507 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2508 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2509 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2510 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2511 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2512 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2513 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2514 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2515 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2516 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2517 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2518 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2519 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2520 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2521 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2522 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2523 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2524 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2525 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2526 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2527 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2528 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2529 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2530 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2531 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2532 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2533 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2534 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2535 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2536 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2537 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2538 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2539 2540 #if defined (STM32F4) 2541 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2542 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2543 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2544 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2545 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2546 #else 2547 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2548 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2549 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2550 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2551 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2552 #endif /* STM32F4 */ 2553 /** 2554 * @} 2555 */ 2556 2557 2558 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2559 * @{ 2560 */ 2561 2562 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2563 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2564 2565 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2566 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2567 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2568 2569 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2570 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2571 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2572 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2573 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2574 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2575 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2576 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2577 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2578 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2579 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2580 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2581 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2582 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2583 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2584 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2585 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2586 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2587 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2588 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2589 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2590 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2591 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2592 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2593 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2594 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2595 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2596 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2597 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2598 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2599 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2600 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2601 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2602 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2603 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2604 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2605 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2606 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2607 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2608 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2609 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2610 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2611 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2612 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2613 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2614 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2615 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2616 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2617 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2618 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2619 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2620 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2621 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2622 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2623 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2624 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2625 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2626 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2627 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2628 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2629 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2630 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2631 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2632 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2633 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2634 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2635 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2636 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2637 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2638 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2639 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2640 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2641 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2642 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2643 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2644 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2645 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2646 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2647 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2648 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2649 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2650 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2651 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2652 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2653 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2654 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2655 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2656 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2657 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2658 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2659 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2660 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2661 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2662 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2663 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2664 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2665 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2666 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2667 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2668 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2669 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2670 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2671 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2672 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2673 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2674 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2675 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2676 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2677 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2678 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2679 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2680 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2681 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2682 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2683 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2684 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2685 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2686 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2687 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2688 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2689 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2690 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2691 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2692 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2693 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2694 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2695 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2696 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2697 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2698 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2699 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2700 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2701 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2702 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2703 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2704 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2705 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2706 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2707 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2708 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2709 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2710 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2711 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2712 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2713 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2714 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2715 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2716 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2717 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2718 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2719 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2720 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2721 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2722 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2723 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2724 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2725 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2726 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2727 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2728 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2729 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2730 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2731 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2732 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2733 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2734 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2735 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2736 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2737 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2738 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2739 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2740 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2741 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2742 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2743 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2744 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2745 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2746 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2747 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2748 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2749 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2750 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2751 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2752 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2753 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2754 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2755 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2756 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2757 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2758 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2759 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2760 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2761 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2762 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2763 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2764 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2765 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2766 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2767 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2768 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2769 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2770 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2771 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2772 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2773 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2774 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2775 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2776 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2777 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2778 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2779 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2780 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2781 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2782 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2783 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2784 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2785 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2786 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2787 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2788 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2789 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2790 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2791 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2792 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2793 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2794 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2795 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2796 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2797 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2798 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2799 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2800 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2801 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2802 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2803 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2804 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2805 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2806 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2807 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2808 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2809 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2810 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2811 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2812 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2813 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2814 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2815 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2816 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2817 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2818 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2819 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2820 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2821 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2822 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2823 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2824 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2825 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2826 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2827 2828 #if defined(STM32WB) 2829 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2830 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2831 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2832 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2833 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2834 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2835 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2836 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2837 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2838 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2839 #define QSPI_IRQHandler QUADSPI_IRQHandler 2840 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2841 2842 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2843 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2844 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2845 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2846 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2847 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2848 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2849 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2850 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2851 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2852 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2853 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2854 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2855 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2856 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2857 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2858 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2859 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2860 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2861 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2862 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2863 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2864 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2865 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2866 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2867 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2868 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2869 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2870 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2871 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2872 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2873 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2874 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2875 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2876 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2877 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2878 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2879 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2880 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2881 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2882 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2883 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2884 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2885 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2886 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2887 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2888 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2889 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2890 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2891 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2892 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2893 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2894 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2895 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2896 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2897 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2898 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2899 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2900 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2901 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2902 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2903 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2904 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2905 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2906 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2907 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2908 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2909 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2910 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2911 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2912 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2913 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2914 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2915 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2916 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2917 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2918 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2919 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2920 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2921 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2922 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2923 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2924 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2925 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2926 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2927 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2928 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2929 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2930 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2931 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2932 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2933 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2934 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2935 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2936 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2937 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2938 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2939 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2940 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2941 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2942 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2943 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2944 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2945 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2946 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2947 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2948 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2949 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2950 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2951 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2952 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2953 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2954 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2955 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2956 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2957 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2958 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2959 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2960 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2961 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2962 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2963 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2964 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2965 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2966 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2967 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2968 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2969 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2970 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2971 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2972 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2973 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2974 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2975 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2976 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2977 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2978 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2979 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2980 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2981 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2982 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2983 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2984 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2985 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2986 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2987 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2988 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2989 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2990 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2991 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2992 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2993 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2994 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2995 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2996 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2997 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2998 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2999 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 3000 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3001 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3002 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3003 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3004 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3005 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3006 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3007 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3008 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3009 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3010 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3011 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3012 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 3013 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 3014 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 3015 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 3016 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 3017 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 3018 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 3019 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 3020 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 3021 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 3022 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 3023 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 3024 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 3025 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 3026 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 3027 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 3028 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 3029 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 3030 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3031 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3032 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3033 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3034 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3035 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3036 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3037 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3038 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3039 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3040 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3041 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3042 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3043 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3044 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3045 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3046 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3047 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3048 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3049 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3050 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 3051 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 3052 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 3053 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 3054 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 3055 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 3056 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 3057 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 3058 3059 #if defined(STM32H7) 3060 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 3061 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 3062 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 3063 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 3064 3065 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 3066 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 3067 3068 3069 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 3070 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 3071 #endif 3072 3073 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 3074 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 3075 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 3076 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 3077 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 3078 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 3079 3080 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 3081 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 3082 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 3083 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 3084 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 3085 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 3086 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 3087 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 3088 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 3089 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 3090 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 3091 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 3092 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 3093 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 3094 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 3095 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 3096 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 3097 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 3098 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 3099 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 3100 3101 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3102 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3103 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 3104 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 3105 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 3106 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 3107 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 3108 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3109 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3110 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3111 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3112 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3113 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3114 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3115 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3116 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3117 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3118 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3119 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3120 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3121 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3122 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3123 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3124 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3125 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3126 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3127 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3128 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3129 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3130 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3131 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3132 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3133 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3134 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3135 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3136 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3137 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3138 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3139 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3140 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3141 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3142 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3143 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3144 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3145 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3146 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3147 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3148 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3149 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3150 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3151 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3152 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3153 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3154 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3155 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3156 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3157 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3158 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3159 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3160 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3161 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3162 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3163 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3164 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3165 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3166 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3167 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3168 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3169 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3170 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3171 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3172 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3173 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3174 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3175 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3176 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3177 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3178 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3179 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3180 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3181 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3182 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3183 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3184 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3185 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3186 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3187 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3188 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3189 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3190 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3191 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3192 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3193 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3194 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3195 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3196 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3197 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3198 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3199 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3200 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3201 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3202 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3203 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3204 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3205 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3206 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3207 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3208 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3209 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3210 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3211 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3212 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3213 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3214 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3215 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3216 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3217 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3218 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3219 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3220 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3221 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3222 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3223 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3224 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3225 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3226 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3227 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3228 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3229 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3230 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3231 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3232 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3233 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3234 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3235 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3236 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3237 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3238 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3239 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3240 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3241 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3242 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3243 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3244 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3245 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3246 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3247 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3248 3249 /* alias define maintained for legacy */ 3250 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3251 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3252 3253 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3254 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3255 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3256 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3257 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3258 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3259 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3260 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3261 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3262 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3263 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3264 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3265 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3266 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3267 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3268 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3269 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3270 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3271 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3272 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3273 3274 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3275 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3276 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3277 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3278 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3279 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3280 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3281 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3282 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3283 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3284 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3285 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3286 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3287 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3288 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3289 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3290 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3291 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3292 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3293 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3294 3295 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3296 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3297 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3298 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3299 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3300 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3301 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3302 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3303 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3304 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3305 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3306 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3307 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3308 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3309 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3310 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3311 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3312 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3313 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3314 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3315 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3316 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3317 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3318 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3319 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3320 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3321 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3322 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3323 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3324 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3325 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3326 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3327 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3328 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3329 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3330 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3331 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3332 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3333 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3334 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3335 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3336 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3337 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3338 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3339 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3340 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3341 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3342 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3343 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3344 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3345 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3346 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3347 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3348 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3349 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3350 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3351 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3352 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3353 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3354 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3355 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3356 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3357 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3358 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3359 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3360 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3361 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3362 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3363 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3364 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3365 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3366 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3367 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3368 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3369 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3370 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3371 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3372 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3373 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3374 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3375 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3376 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3377 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3378 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3379 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3380 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3381 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3382 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3383 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3384 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3385 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3386 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3387 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3388 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3389 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3390 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3391 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3392 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3393 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3394 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3395 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3396 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3397 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3398 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3399 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3400 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3401 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3402 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3403 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3404 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3405 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3406 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3407 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3408 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3409 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3410 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3411 3412 #if defined(STM32L1) 3413 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3414 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3415 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3416 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3417 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3418 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3419 #endif /* STM32L1 */ 3420 3421 #if defined(STM32F4) 3422 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3423 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3424 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3425 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3426 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3427 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3428 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3429 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3430 #define Sdmmc1ClockSelection SdioClockSelection 3431 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3432 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3433 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3434 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3435 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3436 #endif 3437 3438 #if defined(STM32F7) || defined(STM32L4) 3439 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3440 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3441 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3442 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3443 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3444 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3445 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3446 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3447 #define SdioClockSelection Sdmmc1ClockSelection 3448 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3449 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3450 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3451 #endif 3452 3453 #if defined(STM32F7) 3454 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3455 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3456 #endif 3457 3458 #if defined(STM32H7) 3459 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3460 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3461 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3462 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3463 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3464 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3465 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3466 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3467 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3468 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3469 3470 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3471 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3472 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3473 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3474 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3475 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3476 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3477 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3478 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3479 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3480 #endif 3481 3482 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3483 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3484 3485 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3486 3487 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3488 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3489 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3490 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3491 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3492 3493 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3494 3495 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3496 #define RCC_IT_CSSHSE RCC_IT_CSS 3497 3498 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3499 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3500 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3501 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3502 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3503 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3504 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3505 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3506 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3507 3508 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3509 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3510 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3511 3512 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3513 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3514 #define RCC_MCO_NODIV RCC_MCODIV_1 3515 #define RCC_MCO_DIV1 RCC_MCODIV_1 3516 #define RCC_MCO_DIV2 RCC_MCODIV_2 3517 #define RCC_MCO_DIV4 RCC_MCODIV_4 3518 #define RCC_MCO_DIV8 RCC_MCODIV_8 3519 #define RCC_MCO_DIV16 RCC_MCODIV_16 3520 #define RCC_MCO_DIV32 RCC_MCODIV_32 3521 #define RCC_MCO_DIV64 RCC_MCODIV_64 3522 #define RCC_MCO_DIV128 RCC_MCODIV_128 3523 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3524 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3525 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3526 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3527 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3528 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3529 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3530 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3531 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3532 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3533 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3534 3535 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) 3536 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3537 #else 3538 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3539 #endif 3540 3541 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3542 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3543 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3544 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3545 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3546 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3547 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3548 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3549 3550 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3551 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3552 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3553 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3554 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3555 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3556 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3557 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3558 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3559 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3560 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3561 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3562 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3563 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3564 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3565 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3566 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3567 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3568 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3569 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3570 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3571 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3572 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3573 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3574 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3575 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3576 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3577 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3578 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3579 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3580 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3581 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3582 3583 #define CR_HSION_BB RCC_CR_HSION_BB 3584 #define CR_CSSON_BB RCC_CR_CSSON_BB 3585 #define CR_PLLON_BB RCC_CR_PLLON_BB 3586 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3587 #define CR_MSION_BB RCC_CR_MSION_BB 3588 #define CSR_LSION_BB RCC_CSR_LSION_BB 3589 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3590 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3591 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3592 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3593 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3594 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3595 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3596 #define CR_HSEON_BB RCC_CR_HSEON_BB 3597 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3598 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3599 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3600 3601 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3602 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3603 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3604 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3605 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3606 3607 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3608 3609 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3610 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3611 3612 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3613 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3614 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3615 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3616 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3617 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3618 3619 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3620 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3621 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3622 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3623 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3624 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3625 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3626 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3627 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3628 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3629 #define DfsdmClockSelection Dfsdm1ClockSelection 3630 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3631 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3632 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3633 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3634 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3635 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3636 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3637 #if !defined(STM32U0) 3638 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3639 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3640 #endif 3641 3642 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3643 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3644 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3645 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3646 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3647 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3648 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3649 #if defined(STM32U5) 3650 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3651 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3652 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3653 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3654 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3655 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3656 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3657 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3658 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3659 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3660 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3661 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3662 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3663 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3664 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3665 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3666 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3667 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3668 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3669 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3670 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3671 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3672 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3673 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3674 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3675 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3676 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3677 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3678 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3679 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3680 #endif /* STM32U5 */ 3681 3682 #if defined(STM32H5) 3683 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3684 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3685 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3686 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3687 3688 #define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE 3689 #define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI 3690 #define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI 3691 #define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE 3692 #define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 3693 #define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 3694 #define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 3695 #define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 3696 #define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE 3697 #define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM 3698 3699 #define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE 3700 #define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE 3701 #define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE 3702 #define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE 3703 #define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE 3704 #define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE 3705 #define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE 3706 #define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE 3707 #define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE 3708 #define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE 3709 3710 #define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE 3711 #define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE 3712 #define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE 3713 #define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE 3714 #define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG 3715 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG 3716 #define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG 3717 #define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG 3718 #define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE 3719 #define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE 3720 #define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE 3721 #define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE 3722 #define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE 3723 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG 3724 3725 #define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE 3726 #define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE 3727 #define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE 3728 #define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE 3729 #define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG 3730 3731 #define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE 3732 #define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE 3733 #define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE 3734 #define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE 3735 #define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG 3736 3737 #define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 3738 #define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 3739 #define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 3740 #define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 3741 3742 #define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE 3743 #define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM 3744 3745 #define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE 3746 #define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI 3747 #define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI 3748 #define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE 3749 3750 #define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 3751 #define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 3752 #define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 3753 #define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 3754 3755 #define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE 3756 #define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM 3757 3758 #define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE 3759 #define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI 3760 #define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI 3761 #define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE 3762 3763 3764 #endif /* STM32H5 */ 3765 3766 /** 3767 * @} 3768 */ 3769 3770 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3771 * @{ 3772 */ 3773 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3774 3775 /** 3776 * @} 3777 */ 3778 3779 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3780 * @{ 3781 */ 3782 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ 3783 defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32H5) || defined (STM32C0) 3784 #else 3785 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3786 #endif 3787 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3788 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3789 3790 #if defined (STM32F1) 3791 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3792 3793 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3794 3795 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3796 3797 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3798 3799 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3800 #else 3801 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3802 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3803 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3804 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3805 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3806 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3807 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3808 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3809 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3810 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3811 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3812 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3813 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3814 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3815 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3816 #endif /* STM32F1 */ 3817 3818 #define IS_ALARM IS_RTC_ALARM 3819 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3820 #define IS_TAMPER IS_RTC_TAMPER 3821 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3822 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3823 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3824 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3825 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3826 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3827 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3828 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3829 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3830 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3831 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3832 3833 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3834 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3835 3836 #if defined (STM32H5) 3837 #define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE 3838 #define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE 3839 #endif /* STM32H5 */ 3840 3841 /** 3842 * @} 3843 */ 3844 3845 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3846 * @{ 3847 */ 3848 3849 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3850 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3851 3852 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3853 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3854 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3855 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3856 3857 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3858 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3859 #endif 3860 3861 #if defined(STM32F4) || defined(STM32F2) 3862 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3863 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3864 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3865 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3866 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3867 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3868 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3869 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3870 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3871 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3872 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3873 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3874 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3875 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3876 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3877 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3878 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3879 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3880 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3881 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3882 /* alias CMSIS */ 3883 #define SDMMC1_IRQn SDIO_IRQn 3884 #define SDMMC1_IRQHandler SDIO_IRQHandler 3885 #endif 3886 3887 #if defined(STM32F7) || defined(STM32L4) 3888 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3889 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3890 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3891 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3892 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3893 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3894 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3895 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3896 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3897 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3898 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3899 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3900 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3901 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3902 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3903 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3904 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3905 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3906 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3907 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3908 /* alias CMSIS for compatibilities */ 3909 #define SDIO_IRQn SDMMC1_IRQn 3910 #define SDIO_IRQHandler SDMMC1_IRQHandler 3911 #endif 3912 3913 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3914 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3915 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3916 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3917 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3918 #endif 3919 3920 #if defined(STM32H7) || defined(STM32L5) 3921 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3922 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3923 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3924 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3925 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3926 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3927 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3928 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3929 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3930 #endif 3931 /** 3932 * @} 3933 */ 3934 3935 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3936 * @{ 3937 */ 3938 3939 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3940 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3941 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3942 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3943 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3944 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3945 3946 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3947 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3948 3949 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3950 3951 /** 3952 * @} 3953 */ 3954 3955 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3956 * @{ 3957 */ 3958 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3959 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3960 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3961 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3962 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3963 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3964 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3965 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3966 /** 3967 * @} 3968 */ 3969 3970 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3971 * @{ 3972 */ 3973 3974 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3975 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3976 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3977 3978 /** 3979 * @} 3980 */ 3981 3982 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3983 * @{ 3984 */ 3985 3986 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3987 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3988 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3989 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3990 3991 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3992 3993 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3994 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3995 3996 /** 3997 * @} 3998 */ 3999 4000 4001 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 4002 * @{ 4003 */ 4004 4005 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 4006 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 4007 #define __USART_ENABLE __HAL_USART_ENABLE 4008 #define __USART_DISABLE __HAL_USART_DISABLE 4009 4010 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4011 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4012 4013 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 4014 #define USART_OVERSAMPLING_16 0x00000000U 4015 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 4016 4017 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 4018 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 4019 #endif /* STM32F0 || STM32F3 || STM32F7 */ 4020 /** 4021 * @} 4022 */ 4023 4024 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 4025 * @{ 4026 */ 4027 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 4028 4029 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 4030 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 4031 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 4032 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 4033 4034 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 4035 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 4036 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 4037 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 4038 4039 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 4040 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 4041 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 4042 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 4043 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 4044 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4045 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4046 4047 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 4048 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 4049 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 4050 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 4051 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4052 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4053 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4054 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 4055 4056 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 4057 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 4058 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 4059 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 4060 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4061 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4062 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4063 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 4064 4065 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 4066 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 4067 4068 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 4069 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 4070 /** 4071 * @} 4072 */ 4073 4074 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 4075 * @{ 4076 */ 4077 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 4078 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 4079 4080 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4081 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 4082 4083 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4084 4085 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 4086 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 4087 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 4088 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 4089 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 4090 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 4091 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 4092 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 4093 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 4094 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 4095 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 4096 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 4097 4098 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 4099 /** 4100 * @} 4101 */ 4102 4103 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 4104 * @{ 4105 */ 4106 4107 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 4108 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 4109 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 4110 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 4111 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 4112 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 4113 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 4114 4115 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 4116 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 4117 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 4118 /** 4119 * @} 4120 */ 4121 4122 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 4123 * @{ 4124 */ 4125 #define __HAL_LTDC_LAYER LTDC_LAYER 4126 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 4127 /** 4128 * @} 4129 */ 4130 4131 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 4132 * @{ 4133 */ 4134 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 4135 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 4136 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 4137 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 4138 #define SAI_STREOMODE SAI_STEREOMODE 4139 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 4140 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 4141 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 4142 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 4143 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 4144 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 4145 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 4146 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 4147 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 4148 /** 4149 * @} 4150 */ 4151 4152 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 4153 * @{ 4154 */ 4155 #if defined(STM32H7) 4156 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 4157 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 4158 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 4159 #endif 4160 /** 4161 * @} 4162 */ 4163 4164 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 4165 * @{ 4166 */ 4167 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 4168 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 4169 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 4170 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 4171 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 4172 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 4173 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 4174 #endif 4175 /** 4176 * @} 4177 */ 4178 4179 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 4180 * @{ 4181 */ 4182 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 4183 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 4184 #endif /* STM32L4 || STM32F4 || STM32F7 */ 4185 /** 4186 * @} 4187 */ 4188 4189 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 4190 * @{ 4191 */ 4192 #if defined (STM32F7) 4193 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 4194 #endif /* STM32F7 */ 4195 /** 4196 * @} 4197 */ 4198 4199 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4200 * @{ 4201 */ 4202 4203 /** 4204 * @} 4205 */ 4206 4207 #ifdef __cplusplus 4208 } 4209 #endif 4210 4211 #endif /* STM32_HAL_LEGACY */ 4212 4213 4214
