1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F0xx_HAL_RCC_H 20 #define __STM32F0xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f0xx_hal_def.h" 28 29 /** @addtogroup STM32F0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @addtogroup RCC_Private_Constants 38 * @{ 39 */ 40 41 /** @defgroup RCC_Timeout RCC Timeout 42 * @{ 43 */ 44 45 /* Disable Backup domain write protection state change timeout */ 46 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ 47 /* LSE state change timeout */ 48 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 49 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 50 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 51 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 52 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 53 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 54 #define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 55 #if defined(RCC_HSI48_SUPPORT) 56 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 57 #endif /* RCC_HSI48_SUPPORT */ 58 /** 59 * @} 60 */ 61 62 /** @defgroup RCC_Register_Offset Register offsets 63 * @{ 64 */ 65 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 66 #define RCC_CR_OFFSET 0x00 67 #define RCC_CFGR_OFFSET 0x04 68 #define RCC_CIR_OFFSET 0x08 69 #define RCC_BDCR_OFFSET 0x20 70 #define RCC_CSR_OFFSET 0x24 71 72 /** 73 * @} 74 */ 75 76 77 /* CR register byte 2 (Bits[23:16]) base address */ 78 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) 79 80 /* CIR register byte 1 (Bits[15:8]) base address */ 81 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) 82 83 /* CIR register byte 2 (Bits[23:16]) base address */ 84 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) 85 86 /* Defines used for Flags */ 87 #define CR_REG_INDEX ((uint8_t)1U) 88 #define CR2_REG_INDEX ((uint8_t)2U) 89 #define BDCR_REG_INDEX ((uint8_t)3U) 90 #define CSR_REG_INDEX ((uint8_t)4U) 91 92 /* Bits position in in the CFGR register */ 93 #define RCC_CFGR_PLLMUL_BITNUMBER 18U 94 #define RCC_CFGR_HPRE_BITNUMBER 4U 95 #define RCC_CFGR_PPRE_BITNUMBER 8U 96 /* Flags in the CFGR2 register */ 97 #define RCC_CFGR2_PREDIV_BITNUMBER 0 98 /* Flags in the CR register */ 99 #define RCC_CR_HSIRDY_BitNumber 1 100 #define RCC_CR_HSERDY_BitNumber 17 101 #define RCC_CR_PLLRDY_BitNumber 25 102 /* Flags in the CR2 register */ 103 #define RCC_CR2_HSI14RDY_BitNumber 1 104 #define RCC_CR2_HSI48RDY_BitNumber 17 105 /* Flags in the BDCR register */ 106 #define RCC_BDCR_LSERDY_BitNumber 1 107 /* Flags in the CSR register */ 108 #define RCC_CSR_LSIRDY_BitNumber 1 109 #define RCC_CSR_V18PWRRSTF_BitNumber 23 110 #define RCC_CSR_RMVF_BitNumber 24 111 #define RCC_CSR_OBLRSTF_BitNumber 25 112 #define RCC_CSR_PINRSTF_BitNumber 26 113 #define RCC_CSR_PORRSTF_BitNumber 27 114 #define RCC_CSR_SFTRSTF_BitNumber 28 115 #define RCC_CSR_IWDGRSTF_BitNumber 29 116 #define RCC_CSR_WWDGRSTF_BitNumber 30 117 #define RCC_CSR_LPWRRSTF_BitNumber 31 118 /* Flags in the HSITRIM register */ 119 #define RCC_CR_HSITRIM_BitNumber 3 120 #define RCC_HSI14TRIM_BIT_NUMBER 3 121 #define RCC_FLAG_MASK ((uint8_t)0x1FU) 122 123 /** 124 * @} 125 */ 126 127 /** @addtogroup RCC_Private_Macros 128 * @{ 129 */ 130 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 131 ((__HSE__) == RCC_HSE_BYPASS)) 132 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 133 ((__LSE__) == RCC_LSE_BYPASS)) 134 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 135 #define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) 136 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 137 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 138 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 139 ((__PLL__) == RCC_PLL_ON)) 140 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ 141 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ 142 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ 143 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ 144 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ 145 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ 146 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ 147 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) 148 149 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 150 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 151 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 152 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 153 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 154 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 155 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 156 ((__MUL__) == RCC_PLL_MUL16)) 157 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 158 (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 159 (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) 160 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 161 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 162 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 163 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 164 ((__HCLK__) == RCC_SYSCLK_DIV512)) 165 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 166 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 167 ((__PCLK__) == RCC_HCLK_DIV16)) 168 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 169 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 170 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 171 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 172 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 173 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ 174 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 175 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 176 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 177 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 178 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) 179 180 /** 181 * @} 182 */ 183 184 /* Exported types ------------------------------------------------------------*/ 185 186 /** @defgroup RCC_Exported_Types RCC Exported Types 187 * @{ 188 */ 189 190 /** 191 * @brief RCC PLL configuration structure definition 192 */ 193 typedef struct 194 { 195 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 196 This parameter can be a value of @ref RCC_PLL_Config */ 197 198 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 199 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 200 201 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 202 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ 203 204 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock 205 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ 206 207 } RCC_PLLInitTypeDef; 208 209 /** 210 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 211 */ 212 typedef struct 213 { 214 uint32_t OscillatorType; /*!< The oscillators to be configured. 215 This parameter can be a value of @ref RCC_Oscillator_Type */ 216 217 uint32_t HSEState; /*!< The new state of the HSE. 218 This parameter can be a value of @ref RCC_HSE_Config */ 219 220 uint32_t LSEState; /*!< The new state of the LSE. 221 This parameter can be a value of @ref RCC_LSE_Config */ 222 223 uint32_t HSIState; /*!< The new state of the HSI. 224 This parameter can be a value of @ref RCC_HSI_Config */ 225 226 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 227 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ 228 229 uint32_t HSI14State; /*!< The new state of the HSI14. 230 This parameter can be a value of @ref RCC_HSI14_Config */ 231 232 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). 233 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ 234 235 uint32_t LSIState; /*!< The new state of the LSI. 236 This parameter can be a value of @ref RCC_LSI_Config */ 237 238 #if defined(RCC_HSI48_SUPPORT) 239 uint32_t HSI48State; /*!< The new state of the HSI48. 240 This parameter can be a value of @ref RCC_HSI48_Config */ 241 242 #endif /* RCC_HSI48_SUPPORT */ 243 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 244 245 } RCC_OscInitTypeDef; 246 247 /** 248 * @brief RCC System, AHB and APB busses clock configuration structure definition 249 */ 250 typedef struct 251 { 252 uint32_t ClockType; /*!< The clock to be configured. 253 This parameter can be a value of @ref RCC_System_Clock_Type */ 254 255 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 256 This parameter can be a value of @ref RCC_System_Clock_Source */ 257 258 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 259 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 260 261 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 262 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 263 264 } RCC_ClkInitTypeDef; 265 266 /** 267 * @} 268 */ 269 270 /* Exported constants --------------------------------------------------------*/ 271 /** @defgroup RCC_Exported_Constants RCC Exported Constants 272 * @{ 273 */ 274 275 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 276 * @{ 277 */ 278 279 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ 280 281 /** 282 * @} 283 */ 284 285 /** @defgroup RCC_Oscillator_Type Oscillator Type 286 * @{ 287 */ 288 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) 289 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) 290 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) 291 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) 292 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) 293 #define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) 294 #if defined(RCC_HSI48_SUPPORT) 295 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) 296 #endif /* RCC_HSI48_SUPPORT */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup RCC_HSE_Config HSE Config 302 * @{ 303 */ 304 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 305 #define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ 306 #define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup RCC_LSE_Config LSE Config 312 * @{ 313 */ 314 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ 315 #define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ 316 #define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ 317 318 /** 319 * @} 320 */ 321 322 /** @defgroup RCC_HSI_Config HSI Config 323 * @{ 324 */ 325 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 326 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 327 328 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ 329 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCC_HSI14_Config RCC HSI14 Config 335 * @{ 336 */ 337 #define RCC_HSI14_OFF (0x00000000U) 338 #define RCC_HSI14_ON RCC_CR2_HSI14ON 339 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) 340 341 #define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_LSI_Config LSI Config 347 * @{ 348 */ 349 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 350 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 351 352 /** 353 * @} 354 */ 355 356 #if defined(RCC_HSI48_SUPPORT) 357 /** @defgroup RCC_HSI48_Config HSI48 Config 358 * @{ 359 */ 360 #define RCC_HSI48_OFF ((uint8_t)0x00U) 361 #define RCC_HSI48_ON ((uint8_t)0x01U) 362 363 /** 364 * @} 365 */ 366 #endif /* RCC_HSI48_SUPPORT */ 367 368 /** @defgroup RCC_PLL_Config PLL Config 369 * @{ 370 */ 371 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ 372 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ 373 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ 374 375 /** 376 * @} 377 */ 378 379 /** @defgroup RCC_System_Clock_Type System Clock Type 380 * @{ 381 */ 382 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 383 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 384 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 385 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_System_Clock_Source System Clock Source 391 * @{ 392 */ 393 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 394 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 395 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 396 397 /** 398 * @} 399 */ 400 401 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 402 * @{ 403 */ 404 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 405 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 406 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 407 408 /** 409 * @} 410 */ 411 412 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 413 * @{ 414 */ 415 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 416 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 417 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 418 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 419 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 420 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 421 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 422 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 423 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 424 425 /** 426 * @} 427 */ 428 429 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source 430 * @{ 431 */ 432 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ 433 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ 434 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ 435 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ 436 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ 437 438 /** 439 * @} 440 */ 441 442 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 443 * @{ 444 */ 445 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ 446 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 447 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 448 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ 449 /** 450 * @} 451 */ 452 453 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor 454 * @{ 455 */ 456 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 457 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 458 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 459 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 460 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 461 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 462 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 463 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 464 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 465 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 466 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 467 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 468 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 469 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 470 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 471 472 /** 473 * @} 474 */ 475 476 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor 477 * @{ 478 */ 479 480 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 481 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 482 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 483 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 484 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 485 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 486 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 487 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 488 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 489 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 490 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 491 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 492 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 493 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 494 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 495 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 496 497 /** 498 * @} 499 */ 500 501 502 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source 503 * @{ 504 */ 505 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK 506 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 507 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 508 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 509 510 /** 511 * @} 512 */ 513 514 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source 515 * @{ 516 */ 517 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI 518 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK 519 520 /** 521 * @} 522 */ 523 /** @defgroup RCC_MCO_Index MCO Index 524 * @{ 525 */ 526 #define RCC_MCO1 (0x00000000U) 527 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 528 529 /** 530 * @} 531 */ 532 533 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source 534 * @{ 535 */ 536 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK 537 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI 538 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE 539 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK 540 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI 541 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE 542 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL 543 #define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 544 545 /** 546 * @} 547 */ 548 549 /** @defgroup RCC_Interrupt Interrupts 550 * @{ 551 */ 552 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 553 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 554 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 555 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 556 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 557 #define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ 558 #if defined(RCC_CIR_HSI48RDYF) 559 #define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ 560 #endif 561 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup RCC_Flag Flags 567 * Elements values convention: XXXYYYYYb 568 * - YYYYY : Flag position in the register 569 * - XXX : Register index 570 * - 001: CR register 571 * - 010: CR2 register 572 * - 011: BDCR register 573 * - 0100: CSR register 574 * @{ 575 */ 576 /* Flags in the CR register */ 577 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) 578 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) 579 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) 580 /* Flags in the CR2 register */ 581 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) 582 583 /* Flags in the CSR register */ 584 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) 585 #if defined(RCC_CSR_V18PWRRSTF) 586 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) 587 #endif 588 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) 589 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ 590 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ 591 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ 592 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ 593 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ 594 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ 595 596 /* Flags in the BDCR register */ 597 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ 598 599 /** 600 * @} 601 */ 602 603 /** 604 * @} 605 */ 606 607 /* Exported macro ------------------------------------------------------------*/ 608 609 /** @defgroup RCC_Exported_Macros RCC Exported Macros 610 * @{ 611 */ 612 613 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable 614 * @brief Enable or disable the AHB peripheral clock. 615 * @note After reset, the peripheral clock (used for registers read/write access) 616 * is disabled and the application software has to enable this clock before 617 * using it. 618 * @{ 619 */ 620 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 621 __IO uint32_t tmpreg; \ 622 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 623 /* Delay after an RCC peripheral clock enabling */\ 624 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 625 UNUSED(tmpreg); \ 626 } while(0U) 627 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 628 __IO uint32_t tmpreg; \ 629 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 630 /* Delay after an RCC peripheral clock enabling */\ 631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 632 UNUSED(tmpreg); \ 633 } while(0U) 634 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 635 __IO uint32_t tmpreg; \ 636 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 637 /* Delay after an RCC peripheral clock enabling */\ 638 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 639 UNUSED(tmpreg); \ 640 } while(0U) 641 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 642 __IO uint32_t tmpreg; \ 643 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 644 /* Delay after an RCC peripheral clock enabling */\ 645 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 646 UNUSED(tmpreg); \ 647 } while(0U) 648 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 649 __IO uint32_t tmpreg; \ 650 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 651 /* Delay after an RCC peripheral clock enabling */\ 652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 653 UNUSED(tmpreg); \ 654 } while(0U) 655 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 656 __IO uint32_t tmpreg; \ 657 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 658 /* Delay after an RCC peripheral clock enabling */\ 659 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 660 UNUSED(tmpreg); \ 661 } while(0U) 662 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 663 __IO uint32_t tmpreg; \ 664 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 665 /* Delay after an RCC peripheral clock enabling */\ 666 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 667 UNUSED(tmpreg); \ 668 } while(0U) 669 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 670 __IO uint32_t tmpreg; \ 671 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 672 /* Delay after an RCC peripheral clock enabling */\ 673 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 674 UNUSED(tmpreg); \ 675 } while(0U) 676 677 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) 678 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) 679 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) 680 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) 681 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 682 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 683 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 684 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 685 /** 686 * @} 687 */ 688 689 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 690 * @brief Get the enable or disable status of the AHB peripheral clock. 691 * @note After reset, the peripheral clock (used for registers read/write access) 692 * is disabled and the application software has to enable this clock before 693 * using it. 694 * @{ 695 */ 696 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) 697 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) 698 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) 699 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) 700 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 701 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 702 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 703 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 704 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) 705 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) 706 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) 707 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) 708 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 709 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 710 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 711 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 712 /** 713 * @} 714 */ 715 716 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable 717 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 718 * @note After reset, the peripheral clock (used for registers read/write access) 719 * is disabled and the application software has to enable this clock before 720 * using it. 721 * @{ 722 */ 723 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 724 __IO uint32_t tmpreg; \ 725 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 726 /* Delay after an RCC peripheral clock enabling */\ 727 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 728 UNUSED(tmpreg); \ 729 } while(0U) 730 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 731 __IO uint32_t tmpreg; \ 732 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 733 /* Delay after an RCC peripheral clock enabling */\ 734 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 735 UNUSED(tmpreg); \ 736 } while(0U) 737 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 738 __IO uint32_t tmpreg; \ 739 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 740 /* Delay after an RCC peripheral clock enabling */\ 741 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 742 UNUSED(tmpreg); \ 743 } while(0U) 744 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 745 __IO uint32_t tmpreg; \ 746 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 747 /* Delay after an RCC peripheral clock enabling */\ 748 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 749 UNUSED(tmpreg); \ 750 } while(0U) 751 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 752 __IO uint32_t tmpreg; \ 753 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 754 /* Delay after an RCC peripheral clock enabling */\ 755 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 756 UNUSED(tmpreg); \ 757 } while(0U) 758 759 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 760 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 761 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 762 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 763 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 764 /** 765 * @} 766 */ 767 768 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 769 * @brief Get the enable or disable status of the APB1 peripheral clock. 770 * @note After reset, the peripheral clock (used for registers read/write access) 771 * is disabled and the application software has to enable this clock before 772 * using it. 773 * @{ 774 */ 775 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 776 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 777 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 778 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 779 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 780 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 781 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 782 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 783 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 784 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 785 /** 786 * @} 787 */ 788 789 790 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable 791 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 792 * @note After reset, the peripheral clock (used for registers read/write access) 793 * is disabled and the application software has to enable this clock before 794 * using it. 795 * @{ 796 */ 797 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 798 __IO uint32_t tmpreg; \ 799 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 800 /* Delay after an RCC peripheral clock enabling */\ 801 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 802 UNUSED(tmpreg); \ 803 } while(0U) 804 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 805 __IO uint32_t tmpreg; \ 806 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 807 /* Delay after an RCC peripheral clock enabling */\ 808 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 809 UNUSED(tmpreg); \ 810 } while(0U) 811 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 812 __IO uint32_t tmpreg; \ 813 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 814 /* Delay after an RCC peripheral clock enabling */\ 815 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 816 UNUSED(tmpreg); \ 817 } while(0U) 818 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 819 __IO uint32_t tmpreg; \ 820 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 821 /* Delay after an RCC peripheral clock enabling */\ 822 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 823 UNUSED(tmpreg); \ 824 } while(0U) 825 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 826 __IO uint32_t tmpreg; \ 827 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 828 /* Delay after an RCC peripheral clock enabling */\ 829 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 830 UNUSED(tmpreg); \ 831 } while(0U) 832 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 833 __IO uint32_t tmpreg; \ 834 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 835 /* Delay after an RCC peripheral clock enabling */\ 836 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 837 UNUSED(tmpreg); \ 838 } while(0U) 839 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 840 __IO uint32_t tmpreg; \ 841 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 842 /* Delay after an RCC peripheral clock enabling */\ 843 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 844 UNUSED(tmpreg); \ 845 } while(0U) 846 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ 847 __IO uint32_t tmpreg; \ 848 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ 849 /* Delay after an RCC peripheral clock enabling */\ 850 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ 851 UNUSED(tmpreg); \ 852 } while(0U) 853 854 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 855 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 856 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 857 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 858 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 859 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 860 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 861 #define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) 862 /** 863 * @} 864 */ 865 866 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 867 * @brief Get the enable or disable status of the APB2 peripheral clock. 868 * @note After reset, the peripheral clock (used for registers read/write access) 869 * is disabled and the application software has to enable this clock before 870 * using it. 871 * @{ 872 */ 873 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 874 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 875 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 876 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 877 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 878 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 879 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 880 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) 881 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 882 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 883 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 884 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 885 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 886 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 887 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 888 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) 889 /** 890 * @} 891 */ 892 893 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset 894 * @brief Force or release AHB peripheral reset. 895 * @{ 896 */ 897 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 898 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) 899 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) 900 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) 901 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) 902 903 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) 904 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) 905 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) 906 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) 907 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) 908 /** 909 * @} 910 */ 911 912 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset 913 * @brief Force or release APB1 peripheral reset. 914 * @{ 915 */ 916 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 917 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 918 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 919 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 920 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 921 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 922 923 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) 924 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 925 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 926 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 927 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 928 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 929 /** 930 * @} 931 */ 932 933 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset 934 * @brief Force or release APB2 peripheral reset. 935 * @{ 936 */ 937 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 938 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 939 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 940 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 941 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 942 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 943 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 944 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 945 #define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) 946 947 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) 948 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 949 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 950 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 951 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 952 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 953 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 954 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 955 #define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) 956 /** 957 * @} 958 */ 959 /** @defgroup RCC_HSI_Configuration HSI Configuration 960 * @{ 961 */ 962 963 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 964 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 965 * @note HSI can not be stopped if it is used as system clock source. In this case, 966 * you have to select another source of the system clock then stop the HSI. 967 * @note After enabling the HSI, the application software should wait on HSIRDY 968 * flag to be set indicating that HSI clock is stable and can be used as 969 * system clock source. 970 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 971 * clock cycles. 972 */ 973 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 974 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 975 976 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 977 * @note The calibration is used to compensate for the variations in voltage 978 * and temperature that influence the frequency of the internal HSI RC. 979 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 980 * (default is RCC_HSICALIBRATION_DEFAULT). 981 * This parameter must be a number between 0 and 0x1F. 982 */ 983 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 984 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) 985 986 /** 987 * @} 988 */ 989 990 /** @defgroup RCC_LSI_Configuration LSI Configuration 991 * @{ 992 */ 993 994 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 995 * @note After enabling the LSI, the application software should wait on 996 * LSIRDY flag to be set indicating that LSI clock is stable and can 997 * be used to clock the IWDG and/or the RTC. 998 */ 999 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 1000 1001 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 1002 * @note LSI can not be disabled if the IWDG is running. 1003 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1004 * clock cycles. 1005 */ 1006 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 1007 1008 /** 1009 * @} 1010 */ 1011 1012 /** @defgroup RCC_HSE_Configuration HSE Configuration 1013 * @{ 1014 */ 1015 1016 /** 1017 * @brief Macro to configure the External High Speed oscillator (HSE). 1018 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1019 * supported by this macro. User should request a transition to HSE Off 1020 * first and then HSE On or HSE Bypass. 1021 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1022 * software should wait on HSERDY flag to be set indicating that HSE clock 1023 * is stable and can be used to clock the PLL and/or system clock. 1024 * @note HSE state can not be changed if it is used directly or through the 1025 * PLL as system clock. In this case, you have to select another source 1026 * of the system clock then change the HSE state (ex. disable it). 1027 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1028 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1029 * was previously enabled you have to enable it again after calling this 1030 * function. 1031 * @param __STATE__ specifies the new state of the HSE. 1032 * This parameter can be one of the following values: 1033 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 1034 * 6 HSE oscillator clock cycles. 1035 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 1036 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 1037 */ 1038 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1039 do{ \ 1040 if ((__STATE__) == RCC_HSE_ON) \ 1041 { \ 1042 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1043 } \ 1044 else if ((__STATE__) == RCC_HSE_OFF) \ 1045 { \ 1046 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1047 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1048 } \ 1049 else if ((__STATE__) == RCC_HSE_BYPASS) \ 1050 { \ 1051 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1052 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1053 } \ 1054 else \ 1055 { \ 1056 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1057 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1058 } \ 1059 }while(0U) 1060 1061 /** 1062 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1063 * @note Predivision factor can not be changed if PLL is used as system clock 1064 * In this case, you have to select another source of the system clock, disable the PLL and 1065 * then change the HSE predivision factor. 1066 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1067 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 1068 */ 1069 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 1070 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) 1071 1072 /** 1073 * @} 1074 */ 1075 1076 /** @defgroup RCC_LSE_Configuration LSE Configuration 1077 * @{ 1078 */ 1079 1080 /** 1081 * @brief Macro to configure the External Low Speed oscillator (LSE). 1082 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1083 * @note As the LSE is in the Backup domain and write access is denied to 1084 * this domain after reset, you have to enable write access using 1085 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1086 * (to be done once after reset). 1087 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1088 * software should wait on LSERDY flag to be set indicating that LSE clock 1089 * is stable and can be used to clock the RTC. 1090 * @param __STATE__ specifies the new state of the LSE. 1091 * This parameter can be one of the following values: 1092 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 1093 * 6 LSE oscillator clock cycles. 1094 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 1095 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1096 */ 1097 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1098 do{ \ 1099 if ((__STATE__) == RCC_LSE_ON) \ 1100 { \ 1101 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1102 } \ 1103 else if ((__STATE__) == RCC_LSE_OFF) \ 1104 { \ 1105 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1106 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1107 } \ 1108 else if ((__STATE__) == RCC_LSE_BYPASS) \ 1109 { \ 1110 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1111 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1112 } \ 1113 else \ 1114 { \ 1115 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1116 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1117 } \ 1118 }while(0U) 1119 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration 1125 * @{ 1126 */ 1127 1128 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). 1129 * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software 1130 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be 1131 * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. 1132 * clock cycles. 1133 */ 1134 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) 1135 1136 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). 1137 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. 1138 * @note HSI14 can not be stopped if it is used as system clock source. In this case, 1139 * you have to select another source of the system clock then stop the HSI14. 1140 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator 1141 * clock cycles. 1142 */ 1143 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) 1144 1145 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. 1146 */ 1147 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) 1148 1149 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. 1150 */ 1151 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) 1152 1153 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. 1154 * @note The calibration is used to compensate for the variations in voltage 1155 * and temperature that influence the frequency of the internal HSI14 RC. 1156 * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value 1157 * (default is RCC_HSI14CALIBRATION_DEFAULT). 1158 * This parameter must be a number between 0 and 0x1F. 1159 */ 1160 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ 1161 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) 1162 /** 1163 * @} 1164 */ 1165 1166 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config 1167 * @{ 1168 */ 1169 1170 /** @brief Macro to configure the USART1 clock (USART1CLK). 1171 * @param __USART1CLKSOURCE__ specifies the USART1 clock source. 1172 * This parameter can be one of the following values: 1173 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1174 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1175 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1176 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1177 */ 1178 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ 1179 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) 1180 1181 /** @brief Macro to get the USART1 clock source. 1182 * @retval The clock source can be one of the following values: 1183 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1184 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1185 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1186 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1187 */ 1188 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) 1189 1190 /** 1191 * @} 1192 */ 1193 1194 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config 1195 * @{ 1196 */ 1197 1198 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1199 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. 1200 * This parameter can be one of the following values: 1201 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1202 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1203 */ 1204 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ 1205 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) 1206 1207 /** @brief Macro to get the I2C1 clock source. 1208 * @retval The clock source can be one of the following values: 1209 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1210 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1211 */ 1212 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) 1213 /** 1214 * @} 1215 */ 1216 1217 /** @defgroup RCC_PLL_Configuration PLL Configuration 1218 * @{ 1219 */ 1220 1221 /** @brief Macro to enable the main PLL. 1222 * @note After enabling the main PLL, the application software should wait on 1223 * PLLRDY flag to be set indicating that PLL clock is stable and can 1224 * be used as system clock source. 1225 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1226 */ 1227 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 1228 1229 /** @brief Macro to disable the main PLL. 1230 * @note The main PLL can not be disabled if it is used as system clock source 1231 */ 1232 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 1233 1234 /** @brief Macro to configure the PLL clock source, multiplication and division factors. 1235 * @note This function must be used only when the main PLL is disabled. 1236 * 1237 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 1238 * This parameter can be one of the following values: 1239 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1240 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1241 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 1242 * This parameter can be one of the following values: 1243 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. 1244 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock 1245 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. 1246 * 1247 */ 1248 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ 1249 do { \ 1250 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ 1251 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ 1252 } while(0U) 1253 1254 1255 /** @brief Get oscillator clock selected as PLL input clock 1256 * @retval The clock source used for PLL entry. The returned value can be one 1257 * of the following: 1258 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 1259 */ 1260 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 1261 1262 /** 1263 * @} 1264 */ 1265 1266 /** @defgroup RCC_Get_Clock_source Get Clock source 1267 * @{ 1268 */ 1269 1270 /** 1271 * @brief Macro to configure the system clock source. 1272 * @param __SYSCLKSOURCE__ specifies the system clock source. 1273 * This parameter can be one of the following values: 1274 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1275 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1276 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 1277 */ 1278 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1279 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1280 1281 /** @brief Macro to get the clock source used as system clock. 1282 * @retval The clock source used as system clock. The returned value can be one 1283 * of the following: 1284 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 1285 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 1286 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 1287 */ 1288 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 1289 1290 /** 1291 * @} 1292 */ 1293 1294 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1295 * @{ 1296 */ 1297 1298 #if defined(RCC_CFGR_MCOPRE) 1299 /** @brief Macro to configure the MCO clock. 1300 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1301 * This parameter can be one of the following values: 1302 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1303 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1304 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock 1305 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 1306 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 1307 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 1308 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock 1309 @if STM32F042x6 1310 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1311 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1312 @elseif STM32F048xx 1313 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1314 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1315 @elseif STM32F071xB 1316 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1317 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1318 @elseif STM32F072xB 1319 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1320 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1321 @elseif STM32F078xx 1322 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1323 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1324 @elseif STM32F091xC 1325 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1326 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1327 @elseif STM32F098xx 1328 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock 1329 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1330 @elseif STM32F030x6 1331 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1332 @elseif STM32F030xC 1333 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1334 @elseif STM32F031x6 1335 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1336 @elseif STM32F038xx 1337 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1338 @elseif STM32F070x6 1339 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1340 @elseif STM32F070xB 1341 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock 1342 @endif 1343 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 1344 * @param __MCODIV__ specifies the MCO clock prescaler. 1345 * This parameter can be one of the following values: 1346 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1347 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1348 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1349 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1350 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1351 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 1352 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 1353 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 1354 */ 1355 #else 1356 /** @brief Macro to configure the MCO clock. 1357 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1358 * This parameter can be one of the following values: 1359 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1360 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1361 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 1362 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 1363 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 1364 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 1365 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock 1366 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 1367 * @param __MCODIV__ specifies the MCO clock prescaler. 1368 * This parameter can be one of the following values: 1369 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 1370 */ 1371 #endif 1372 #if defined(RCC_CFGR_MCOPRE) 1373 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1374 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1375 #else 1376 1377 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1378 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 1379 1380 #endif 1381 1382 /** 1383 * @} 1384 */ 1385 1386 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1387 * @{ 1388 */ 1389 1390 /** @brief Macro to configure the RTC clock (RTCCLK). 1391 * @note As the RTC clock configuration bits are in the Backup domain and write 1392 * access is denied to this domain after reset, you have to enable write 1393 * access using the Power Backup Access macro before to configure 1394 * the RTC clock source (to be done once after reset). 1395 * @note Once the RTC clock is configured it cannot be changed unless the 1396 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1397 * a Power On Reset (POR). 1398 * 1399 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1400 * This parameter can be one of the following values: 1401 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1402 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1403 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1404 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 1405 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1406 * work in STOP and STANDBY modes, and can be used as wakeup source. 1407 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, 1408 * the RTC cannot be used in STOP and STANDBY modes. 1409 * @note The system must always be configured so as to get a PCLK frequency greater than or 1410 * equal to the RTCCLK frequency for a proper operation of the RTC. 1411 */ 1412 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 1413 1414 /** @brief Macro to get the RTC clock source. 1415 * @retval The clock source can be one of the following values: 1416 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1417 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1418 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1419 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 1420 */ 1421 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 1422 1423 /** @brief Macro to enable the the RTC clock. 1424 * @note These macros must be used only after the RTC clock source was selected. 1425 */ 1426 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 1427 1428 /** @brief Macro to disable the the RTC clock. 1429 * @note These macros must be used only after the RTC clock source was selected. 1430 */ 1431 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 1432 1433 /** @brief Macro to force the Backup domain reset. 1434 * @note This function resets the RTC peripheral (including the backup registers) 1435 * and the RTC clock source selection in RCC_BDCR register. 1436 */ 1437 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 1438 1439 /** @brief Macros to release the Backup domain reset. 1440 */ 1441 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 1442 1443 /** 1444 * @} 1445 */ 1446 1447 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1448 * @brief macros to manage the specified RCC Flags and interrupts. 1449 * @{ 1450 */ 1451 1452 /** @brief Enable RCC interrupt. 1453 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1454 * This parameter can be any combination of the following values: 1455 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1456 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1457 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1458 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1459 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1460 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt 1461 @if STM32F042x6 1462 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1463 @elseif STM32F048xx 1464 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1465 @elseif STM32F071xB 1466 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1467 @elseif STM32F072xB 1468 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1469 @elseif STM32F078xx 1470 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1471 @elseif STM32F091xC 1472 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1473 @elseif STM32F098xx 1474 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1475 @endif 1476 */ 1477 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1478 1479 /** @brief Disable RCC interrupt. 1480 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1481 * This parameter can be any combination of the following values: 1482 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1483 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1484 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1485 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1486 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1487 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt 1488 @if STM32F042x6 1489 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1490 @elseif STM32F048xx 1491 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1492 @elseif STM32F071xB 1493 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1494 @elseif STM32F072xB 1495 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1496 @elseif STM32F078xx 1497 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1498 @elseif STM32F091xC 1499 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1500 @elseif STM32F098xx 1501 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1502 @endif 1503 */ 1504 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1505 1506 /** @brief Clear the RCC's interrupt pending bits. 1507 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1508 * This parameter can be any combination of the following values: 1509 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1510 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1511 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1512 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1513 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1514 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1515 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt 1516 @if STM32F042x6 1517 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1518 @elseif STM32F048xx 1519 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1520 @elseif STM32F071xB 1521 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1522 @elseif STM32F072xB 1523 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1524 @elseif STM32F078xx 1525 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1526 @elseif STM32F091xC 1527 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1528 @elseif STM32F098xx 1529 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1530 @endif 1531 */ 1532 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1533 1534 /** @brief Check the RCC's interrupt has occurred or not. 1535 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1536 * This parameter can be one of the following values: 1537 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1538 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1539 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1540 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1541 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1542 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1543 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable 1544 @if STM32F042x6 1545 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1546 @elseif STM32F048xx 1547 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1548 @elseif STM32F071xB 1549 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1550 @elseif STM32F072xB 1551 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1552 @elseif STM32F078xx 1553 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1554 @elseif STM32F091xC 1555 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1556 @elseif STM32F098xx 1557 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 1558 @endif 1559 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1560 */ 1561 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1562 1563 /** @brief Set RMVF bit to clear the reset flags. 1564 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1565 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1566 */ 1567 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1568 1569 /** @brief Check RCC flag is set or not. 1570 * @param __FLAG__ specifies the flag to check. 1571 * This parameter can be one of the following values: 1572 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 1573 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 1574 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 1575 * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready 1576 @if STM32F038xx 1577 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1578 @elseif STM32F042x6 1579 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1580 @elseif STM32F048xx 1581 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1582 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1583 @elseif STM32F058xx 1584 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1585 @elseif STM32F071xB 1586 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1587 @elseif STM32F072xB 1588 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1589 @elseif STM32F078xx 1590 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1591 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1592 @elseif STM32F091xC 1593 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1594 @elseif STM32F098xx 1595 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready 1596 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1597 @endif 1598 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 1599 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 1600 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset 1601 * @arg @ref RCC_FLAG_PINRST Pin reset. 1602 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 1603 * @arg @ref RCC_FLAG_SFTRST Software reset. 1604 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 1605 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 1606 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 1607 * @retval The new state of __FLAG__ (TRUE or FALSE). 1608 */ 1609 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ 1610 (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ 1611 (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 1612 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) 1613 1614 /** 1615 * @} 1616 */ 1617 1618 /** 1619 * @} 1620 */ 1621 1622 /* Include RCC HAL Extension module */ 1623 #include "stm32f0xx_hal_rcc_ex.h" 1624 1625 /* Exported functions --------------------------------------------------------*/ 1626 /** @addtogroup RCC_Exported_Functions 1627 * @{ 1628 */ 1629 1630 /** @addtogroup RCC_Exported_Functions_Group1 1631 * @{ 1632 */ 1633 1634 /* Initialization and de-initialization functions ******************************/ 1635 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1636 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1637 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1638 1639 /** 1640 * @} 1641 */ 1642 1643 /** @addtogroup RCC_Exported_Functions_Group2 1644 * @{ 1645 */ 1646 1647 /* Peripheral Control functions ************************************************/ 1648 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1649 void HAL_RCC_EnableCSS(void); 1650 /* CSS NMI IRQ handler */ 1651 void HAL_RCC_NMI_IRQHandler(void); 1652 /* User Callbacks in non blocking mode (IT mode) */ 1653 void HAL_RCC_CSSCallback(void); 1654 void HAL_RCC_DisableCSS(void); 1655 uint32_t HAL_RCC_GetSysClockFreq(void); 1656 uint32_t HAL_RCC_GetHCLKFreq(void); 1657 uint32_t HAL_RCC_GetPCLK1Freq(void); 1658 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1659 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1660 1661 /** 1662 * @} 1663 */ 1664 1665 /** 1666 * @} 1667 */ 1668 1669 /** 1670 * @} 1671 */ 1672 1673 /** 1674 * @} 1675 */ 1676 1677 #ifdef __cplusplus 1678 } 1679 #endif 1680 1681 #endif /* __STM32F0xx_HAL_RCC_H */ 1682 1683 1684
