1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G0xx_HAL_RCC_EX_H 20 #define STM32G0xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g0xx_hal_def.h" 28 29 /** @addtogroup STM32G0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC extended clocks structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 49 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 50 51 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 52 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 53 #if defined(RCC_CCIPR_USART2SEL) 54 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 55 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 56 #endif /* RCC_CCIPR_USART2SEL */ 57 58 #if defined(RCC_CCIPR_USART3SEL) 59 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 60 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 61 #endif /* RCC_CCIPR_USART3SEL */ 62 63 #if defined(LPUART1) 64 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 65 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 66 #endif /* LPUART1 */ 67 68 #if defined(LPUART2) 69 uint32_t Lpuart2ClockSelection; /*!< Specifies LPUART2 clock source 70 This parameter can be a value of @ref RCCEx_LPUART2_Clock_Source */ 71 #endif /* LPUART2 */ 72 73 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source 74 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 75 76 #if defined(RCC_CCIPR_I2C2SEL) 77 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source 78 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 79 #endif /* RCC_CCIPR_I2C2SEL */ 80 81 uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source 82 This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ 83 #if defined(RCC_CCIPR2_I2S2SEL) 84 uint32_t I2s2ClockSelection; /*!< Specifies I2S2 clock source 85 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ 86 #endif /* RCC_CCIPR2_I2S2SEL */ 87 #if defined(RCC_CCIPR_LPTIM1SEL) 88 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 89 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 90 #endif /* RCC_CCIPR_LPTIM1SEL */ 91 #if defined(RCC_CCIPR_LPTIM2SEL) 92 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source 93 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 94 #endif /* RCC_CCIPR_LPTIM2SEL */ 95 #if defined(RNG) 96 uint32_t RngClockSelection; /*!< Specifies RNG clock source 97 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 98 #endif /* RNG */ 99 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 100 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 101 #if defined(CEC) 102 uint32_t CecClockSelection; /*!< Specifies CEC Clock clock source 103 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 104 #endif /* CEC */ 105 #if defined(RCC_CCIPR_TIM1SEL) 106 uint32_t Tim1ClockSelection; /*!< Specifies TIM1 Clock clock source 107 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 108 #endif /* RCC_CCIPR_TIM1SEL */ 109 #if defined(RCC_CCIPR_TIM15SEL) 110 uint32_t Tim15ClockSelection; /*!< Specifies TIM15 Clock clock source 111 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 112 #endif /* RCC_CCIPR_TIM15SEL */ 113 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 114 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 115 #if defined(RCC_CCIPR2_USBSEL) 116 uint32_t UsbClockSelection; /*!< Specifies USB Clock clock source 117 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 118 #endif /* RCC_CCIPR2_USBSEL */ 119 #if defined(FDCAN1) || defined(FDCAN2) 120 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 121 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 122 #endif /* FDCAN1 || FDCAN2 */ 123 } RCC_PeriphCLKInitTypeDef; 124 125 #if defined(CRS) 126 127 /** 128 * @brief RCC_CRS Init structure definition 129 */ 130 typedef struct 131 { 132 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 133 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 134 135 uint32_t Source; /*!< Specifies the SYNC signal source. 136 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 137 138 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 139 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 140 141 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 142 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 143 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 144 145 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 146 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 147 148 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 149 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 150 151 } RCC_CRSInitTypeDef; 152 153 /** 154 * @brief RCC_CRS Synchronization structure definition 155 */ 156 typedef struct 157 { 158 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 159 This parameter must be a number between 0 and 0xFFFF */ 160 161 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 162 This parameter must be a number between 0 and 0x7F */ 163 164 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 165 value latched in the time of the last SYNC event. 166 This parameter must be a number between 0 and 0xFFFF */ 167 168 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 169 frequency error counter latched in the time of the last SYNC event. 170 It shows whether the actual frequency is below or above the target. 171 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 172 173 } RCC_CRSSynchroInfoTypeDef; 174 175 #endif /* CRS */ 176 /** 177 * @} 178 */ 179 180 /* Exported constants --------------------------------------------------------*/ 181 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 182 * @{ 183 */ 184 185 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 186 * @{ 187 */ 188 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 189 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 190 /** 191 * @} 192 */ 193 194 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 195 * @{ 196 */ 197 #define RCC_PERIPHCLK_USART1 0x00000001U 198 #if defined(RCC_CCIPR_USART2SEL) 199 #define RCC_PERIPHCLK_USART2 0x00000002U 200 #endif /* RCC_CCIPR_USART2SEL */ 201 #if defined(RCC_CCIPR_USART3SEL) 202 #define RCC_PERIPHCLK_USART3 0x00000004U 203 #endif /* RCC_CCIPR_USART3SEL */ 204 #if defined(LPUART1) 205 #define RCC_PERIPHCLK_LPUART1 0x00000010U 206 #endif /* LPUART1 */ 207 #define RCC_PERIPHCLK_I2C1 0x00000020U 208 #if defined(RCC_CCIPR_I2C2SEL) 209 #define RCC_PERIPHCLK_I2C2 0x00000040U 210 #endif /* RCC_CCIPR_I2C2SEL */ 211 #if defined(RCC_CCIPR_LPTIM1SEL) 212 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 213 #endif /* RCC_CCIPR_LPTIM1SEL */ 214 #if defined(RCC_CCIPR_LPTIM2SEL) 215 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 216 #endif /* RCC_CCIPR_LPTIM2SEL */ 217 #define RCC_PERIPHCLK_I2S1 0x00000800U 218 #if defined(LPUART2) 219 #define RCC_PERIPHCLK_LPUART2 0x00001000U 220 #endif /* LPUART2 */ 221 #if defined(RCC_CCIPR2_I2S2SEL) 222 #define RCC_PERIPHCLK_I2S2 0x00002000U 223 #endif /* RCC_CCIPR2_I2S2SEL */ 224 #define RCC_PERIPHCLK_ADC 0x00004000U 225 #define RCC_PERIPHCLK_RTC 0x00020000U 226 #if defined(RCC_CCIPR_RNGSEL) 227 #define RCC_PERIPHCLK_RNG 0x00040000U 228 #endif /* RCC_CCIPR_RNGSEL */ 229 #if defined(RCC_CCIPR_CECSEL) 230 #define RCC_PERIPHCLK_CEC 0x00080000U 231 #endif /* RCC_CCIPR_CECSEL */ 232 #if defined(RCC_CCIPR_TIM1SEL) 233 #define RCC_PERIPHCLK_TIM1 0x00200000U 234 #endif /* RCC_CCIPR_TIM1SEL */ 235 #if defined(RCC_CCIPR_TIM15SEL) 236 #define RCC_PERIPHCLK_TIM15 0x00400000U 237 #endif /* RCC_CCIPR_TIM15SEL */ 238 #if defined(RCC_CCIPR2_USBSEL) 239 #define RCC_PERIPHCLK_USB 0x01000000U 240 #endif /* RCC_CCIPR2_USBSEL */ 241 #if defined(FDCAN1) || defined(FDCAN2) 242 #define RCC_PERIPHCLK_FDCAN 0x02000000U 243 #endif /* FDCAN1 || FDCAN2 */ 244 /** 245 * @} 246 */ 247 248 249 /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source 250 * @{ 251 */ 252 #define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART1 clock */ 253 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART1 clock */ 254 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI clock selected as USART1 clock */ 255 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART1 clock */ 256 /** 257 * @} 258 */ 259 260 #if defined(RCC_CCIPR_USART2SEL) 261 /** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source 262 * @{ 263 */ 264 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART2 clock */ 265 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 /*!< SYSCLK clock selected as USART2 clock */ 266 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 /*!< HSI clock selected as USART2 clock */ 267 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) /*!< LSE clock selected as USART2 clock */ 268 /** 269 * @} 270 */ 271 #endif /* RCC_CCIPR_USART2SEL */ 272 #if defined(RCC_CCIPR_USART3SEL) 273 /** @defgroup RCCEx_USART3_Clock_Source RCC USART3 Clock Source 274 * @{ 275 */ 276 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART3 clock */ 277 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 /*!< SYSCLK clock selected as USART3 clock */ 278 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 /*!< HSI clock selected as USART3 clock */ 279 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) /*!< LSE clock selected as USART3 clock */ 280 /** 281 * @} 282 */ 283 #endif /* RCC_CCIPR_USART3SEL */ 284 285 #if defined(LPUART1) 286 /** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART1 Clock Source 287 * @{ 288 */ 289 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART1 clock */ 290 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock selected as LPUART1 clock */ 291 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock selected as LPUART1 clock */ 292 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) /*!< LSE clock selected as LPUART1 clock */ 293 /** 294 * @} 295 */ 296 #endif /* LPUART1 */ 297 298 #if defined(LPUART2) 299 /** @defgroup RCCEx_LPUART2_Clock_Source RCC LPUART2 Clock Source 300 * @{ 301 */ 302 #define RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART2 clock */ 303 #define RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0 /*!< SYSCLK clock selected as LPUART2 clock */ 304 #define RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1 /*!< HSI clock selected as LPUART2 clock */ 305 #define RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1) /*!< LSE clock selected as LPUART2 clock */ 306 /** 307 * @} 308 */ 309 #endif /* LPUART2 */ 310 311 /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source 312 * @{ 313 */ 314 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ 315 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ 316 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /*!< HSI clock selected as I2C1 clock */ 317 /** 318 * @} 319 */ 320 321 #if defined(RCC_CCIPR_I2C2SEL) 322 /** @defgroup RCCEx_I2C2_Clock_Source RCC I2C2 Clock Source 323 * @{ 324 */ 325 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C2 clock */ 326 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 /*!< SYSCLK clock selected as I2C2 clock */ 327 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /*!< HSI clock selected as I2C2 clock */ 328 /** 329 * @} 330 */ 331 #endif /* RCC_CCIPR_I2C2SEL */ 332 333 /** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source 334 * @{ 335 */ 336 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 337 #define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ 338 #define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ 339 #define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ 340 #define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ 341 #else 342 #define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ 343 #define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ 344 #define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ 345 #define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ 346 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 347 /** 348 * @} 349 */ 350 351 #if defined(RCC_CCIPR2_I2S2SEL) 352 /** @defgroup RCCEx_I2S2_Clock_Source RCC I2S2 Clock Source 353 * @{ 354 */ 355 #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S2 clock */ 356 #define RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0 /*!< PLL "P" selected as I2S2 clock */ 357 #define RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1 /*!< HSI clock selected as I2S2 clock */ 358 #define RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL /*!< External I2S clock source selected as I2S2 clock */ 359 /** 360 * @} 361 */ 362 #endif /* RCC_CCIPR2_I2S2SEL */ 363 364 #if defined(RCC_CCIPR_LPTIM1SEL) 365 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 366 * @{ 367 */ 368 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 1 clock */ 369 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock selected as LPTimer 1 clock */ 370 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock selected as LPTimer 1 clock */ 371 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock selected as LPTimer 1 clock */ 372 /** 373 * @} 374 */ 375 #endif /* RCC_CCIPR_LPTIM1SEL */ 376 377 #if defined(RCC_CCIPR_LPTIM2SEL) 378 /** @defgroup RCCEx_LPTIM2_Clock_Source RCC LPTIM2 Clock Source 379 * @{ 380 */ 381 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 2 clock */ 382 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 /*!< LSI clock selected as LPTimer 2 clock */ 383 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 /*!< HSI clock selected as LPTimer 2 clock */ 384 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL /*!< LSE clock selected as LPTimer 2 clock */ 385 /** 386 * @} 387 */ 388 #endif /* RCC_CCIPR_LPTIM2SEL */ 389 390 #if defined(RNG) 391 /** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source 392 * @{ 393 */ 394 #define RCC_RNGCLKSOURCE_NONE 0x00000000U /*!< No clock selected */ 395 #define RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator divided by 8 clock selected as RNG clock */ 396 #define RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK selected as RNG clock */ 397 #define RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1) /*!< PLL "Q" selected as RNG clock */ 398 399 /** 400 * @} 401 */ 402 403 /** @defgroup RCCEx_RNG_Division_factor RCC RNG Division factor 404 * @{ 405 */ 406 #define RCC_RNGCLK_DIV1 0x00000000U /*!< RNG clock not divided */ 407 #define RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */ 408 #define RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */ 409 #define RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1) /*!< RNG clock divided by 8 */ 410 411 /** 412 * @} 413 */ 414 #endif /* RNG */ 415 416 #if defined(FDCAN1) || defined(FDCAN2) 417 /** @defgroup RCCEx_FDCAN_Clock_Source RCC FDCAN Clock Source 418 * @{ 419 */ 420 #define RCC_FDCANCLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as FDCAN clock */ 421 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" selected as FDCAN clock */ 422 #define RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock selected as FDCAN clock */ 423 424 /** 425 * @} 426 */ 427 #endif /* FDCAN1 || FDCAN2 */ 428 429 #if defined(RCC_CCIPR2_USBSEL) 430 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 431 * @{ 432 */ 433 #if defined(RCC_HSI48_SUPPORT) 434 #define RCC_USBCLKSOURCE_HSI48 0x00000000U /*!< HSI48 oscillator clock selected as USB clock */ 435 #endif /* RCC_HSI48_SUPPORT */ 436 #define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< HSE oscillator clock selected as USB clock */ 437 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL "Q" selected as USB clock */ 438 /** 439 * @} 440 */ 441 #endif /* RCC_CCIPR2_USBSEL */ 442 443 /** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source 444 * @{ 445 */ 446 447 #define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ 448 #define RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0 /*!< PLL "P" (PLLADC) used as ADC clock */ 449 #define RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */ 450 /** 451 * @} 452 */ 453 454 #if defined(CEC) 455 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 456 * @{ 457 */ 458 #define RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as default CEC clock */ 459 #define RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */ 460 /** 461 * @} 462 */ 463 #endif /* CEC */ 464 465 #if defined(RCC_CCIPR_TIM1SEL) 466 /** @defgroup RCCEx_TIM1_Clock_Source RCC TIM1 Clock Source 467 * @{ 468 */ 469 #define RCC_TIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 1 clock */ 470 #define RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL /*!< PLL "Q" clock selected as Timer 1 clock */ 471 /** 472 * @} 473 */ 474 #endif /* RCC_CCIPR_TIM1SEL */ 475 476 #if defined(RCC_CCIPR_TIM15SEL) 477 /** @defgroup RCCEx_TIM15_Clock_Source RCC TIM15 Clock Source 478 * @{ 479 */ 480 #define RCC_TIM15CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 15 clock */ 481 #define RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL /*!< PLL "Q" clock selected as Timer 15 clock */ 482 483 /** 484 * @} 485 */ 486 #endif /* RCC_CCIPR_TIM15SEL */ 487 488 #if defined(CRS) 489 490 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 491 * @{ 492 */ 493 #define RCC_CRS_NONE 0x00000000U 494 #define RCC_CRS_TIMEOUT 0x00000001U 495 #define RCC_CRS_SYNCOK 0x00000002U 496 #define RCC_CRS_SYNCWARN 0x00000004U 497 #define RCC_CRS_SYNCERR 0x00000008U 498 #define RCC_CRS_SYNCMISS 0x00000010U 499 #define RCC_CRS_TRIMOVF 0x00000020U 500 /** 501 * @} 502 */ 503 504 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 505 * @{ 506 */ 507 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 508 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 509 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 510 /** 511 * @} 512 */ 513 514 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 515 * @{ 516 */ 517 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 518 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 519 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 520 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 521 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 522 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 523 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 524 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 530 * @{ 531 */ 532 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 533 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 539 * @{ 540 */ 541 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 542 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 543 /** 544 * @} 545 */ 546 547 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 548 * @{ 549 */ 550 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 551 /** 552 * @} 553 */ 554 555 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 556 * @{ 557 */ 558 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 559 The trimming step is specified in the product datasheet. A higher TRIM value 560 corresponds to a higher output frequency */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 566 * @{ 567 */ 568 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 569 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 575 * @{ 576 */ 577 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 578 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 579 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 580 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 581 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 582 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 583 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 584 585 /** 586 * @} 587 */ 588 589 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 590 * @{ 591 */ 592 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 593 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 594 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 595 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 596 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 597 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 598 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 599 600 /** 601 * @} 602 */ 603 604 #endif /* CRS */ 605 606 /** 607 * @} 608 */ 609 610 /* Exported macros -----------------------------------------------------------*/ 611 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 612 * @{ 613 */ 614 615 616 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 617 * 618 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 619 * This parameter can be one of the following values: 620 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 621 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 622 */ 623 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 624 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 625 626 /** @brief Macro to get the I2C1 clock source. 627 * @retval The clock source can be one of the following values: 628 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 629 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 630 */ 631 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 632 633 #if defined(RCC_CCIPR_I2C2SEL) 634 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 635 * 636 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 637 * This parameter can be one of the following values: 638 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 639 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 640 */ 641 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 642 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 643 644 /** @brief Macro to get the I2C2 clock source. 645 * @retval The clock source can be one of the following values: 646 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 647 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 648 */ 649 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) 650 #endif /* RCC_CCIPR_I2C2SEL */ 651 652 /** @brief Macro to configure the I2S1 clock (I2S1CLK). 653 * 654 * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. 655 * This parameter can be one of the following values: 656 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 657 * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock 658 * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock 659 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 660 */ 661 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 662 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ 663 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) 664 #else 665 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ 666 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) 667 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 668 /** @brief Macro to get the I2S1 clock source. 669 * @retval The clock source can be one of the following values: 670 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 671 * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock 672 * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock 673 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 674 */ 675 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 676 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL))) 677 #else 678 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) 679 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 680 681 #if defined(RCC_CCIPR2_I2S2SEL) 682 /** @brief Macro to configure the I2S2 clock (I2S2CLK). 683 * 684 * @param __I2S2_CLKSOURCE__ specifies the I2S2 clock source. 685 * This parameter can be one of the following values: 686 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock 687 * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock 688 * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock 689 * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock 690 */ 691 #define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \ 692 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__)) 693 694 /** @brief Macro to get the I2S2 clock source. 695 * @retval The clock source can be one of the following values: 696 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock 697 * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock 698 * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock 699 * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock 700 */ 701 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL))) 702 #endif /* RCC_CCIPR2_I2S2SEL */ 703 704 /** @brief Macro to configure the USART1 clock (USART1CLK). 705 * 706 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 707 * This parameter can be one of the following values: 708 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 709 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 710 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 711 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 712 */ 713 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 714 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 715 716 /** @brief Macro to get the USART1 clock source. 717 * @retval The clock source can be one of the following values: 718 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 719 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 720 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 721 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 722 */ 723 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 724 725 #if defined(RCC_CCIPR_USART2SEL) 726 /** @brief Macro to configure the USART2 clock (USART2CLK). 727 * 728 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 729 * This parameter can be one of the following values: 730 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 731 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 732 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 733 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 734 */ 735 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 736 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 737 738 /** @brief Macro to get the USART2 clock source. 739 * @retval The clock source can be one of the following values: 740 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 741 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 742 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 743 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 744 */ 745 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) 746 #endif /* RCC_CCIPR_USART2SEL */ 747 748 #if defined(RCC_CCIPR_USART3SEL) 749 /** @brief Macro to configure the USART3 clock (USART3CLK). 750 * 751 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 752 * This parameter can be one of the following values: 753 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 754 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 755 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 756 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 757 */ 758 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 759 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 760 761 /** @brief Macro to get the USART3 clock source. 762 * @retval The clock source can be one of the following values: 763 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 764 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 765 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 766 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 767 */ 768 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) 769 #endif /* RCC_CCIPR_USART3SEL */ 770 771 #if defined(RCC_CCIPR_LPUART1SEL) 772 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 773 * 774 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 775 * This parameter can be one of the following values: 776 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 777 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 778 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 779 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 780 */ 781 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 782 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 783 784 /** @brief Macro to get the LPUART1 clock source. 785 * @retval The clock source can be one of the following values: 786 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 787 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 788 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 789 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 790 */ 791 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) 792 #endif /* RCC_CCIPR_LPUART1SEL */ 793 794 #if defined(RCC_CCIPR_LPUART2SEL) 795 /** @brief Macro to configure the LPUART2 clock (LPUART2CLK). 796 * 797 * @param __LPUART2_CLKSOURCE__ specifies the LPUART2 clock source. 798 * This parameter can be one of the following values: 799 * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock 800 * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock 801 * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock 802 * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock 803 */ 804 #define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \ 805 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) 806 807 /** @brief Macro to get the LPUART2 clock source. 808 * @retval The clock source can be one of the following values: 809 * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock 810 * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock 811 * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock 812 * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock 813 */ 814 #define __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL))) 815 #endif /* RCC_CCIPR_LPUART2SEL */ 816 817 #if defined(RCC_CCIPR_LPTIM1SEL) 818 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 819 * 820 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 821 * This parameter can be one of the following values: 822 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 823 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 824 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 825 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 826 */ 827 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 828 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 829 830 /** @brief Macro to get the LPTIM1 clock source. 831 * @retval The clock source can be one of the following values: 832 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 833 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 834 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 835 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 836 */ 837 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) 838 #endif /* RCC_CCIPR_LPTIM1SEL */ 839 840 #if defined(RCC_CCIPR_LPTIM2SEL) 841 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 842 * 843 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 844 * This parameter can be one of the following values: 845 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 846 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 847 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 848 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 849 */ 850 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 851 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 852 853 /** @brief Macro to get the LPTIM2 clock source. 854 * @retval The clock source can be one of the following values: 855 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 856 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 857 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock 858 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 859 */ 860 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) 861 #endif /* RCC_CCIPR_LPTIM2SEL */ 862 863 #if defined(CEC) 864 /** @brief Macro to configure the CEC clock (CECCLK). 865 * 866 * @param __CEC_CLKSOURCE__ specifies the CEC clock source. 867 * This parameter can be one of the following values: 868 * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 selected as CEC clock 869 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 870 */ 871 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ 872 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) 873 874 /** @brief Macro to get the CEC clock source. 875 * @retval The clock source can be one of the following values: 876 * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 Clock selected as CEC clock 877 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 878 */ 879 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL))) 880 #endif /* CEC */ 881 882 #if defined(RNG) 883 /** @brief Macro to configure the RNG clock. 884 * 885 * 886 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 887 * This parameter can be one of the following values: 888 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock 889 * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divided by 8 selected as RNG clock 890 * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System Clock selected as RNG clock 891 * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock 892 */ 893 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 894 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__)) 895 896 /** @brief Macro to get the RNG clock. 897 * @retval The clock source can be one of the following values: 898 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock 899 * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divide by 8 selected as RNG clock 900 * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System clock selected as RNG clock 901 * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock 902 */ 903 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL))) 904 905 /** @brief Macro to configure the RNG clock. 906 * 907 * 908 * @param __RNG_CLKDIV__ specifies the RNG clock division factor. 909 * This parameter can be one of the following values: 910 * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided 911 * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 912 * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 913 * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 914 */ 915 #define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \ 916 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__)) 917 918 /** @brief Macro to get the RNG clock division factor. 919 * @retval The division factor can be one of the following values: 920 * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided 921 * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 922 * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 923 * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 924 */ 925 #define __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV))) 926 #endif /* RNG */ 927 928 /** @brief Macro to configure the ADC interface clock 929 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 930 * This parameter can be one of the following values: 931 * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock 932 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 933 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock 934 */ 935 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 936 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 937 938 /** @brief Macro to get the ADC clock source. 939 * @retval The clock source can be one of the following values: 940 * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock 941 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 942 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock 943 */ 944 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) 945 946 #if defined(RCC_CCIPR_TIM1SEL) 947 /** @brief Macro to configure the TIM1 interface clock 948 * @param __TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source. 949 * This parameter can be one of the following values: 950 * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock 951 * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock 952 */ 953 #define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \ 954 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__)) 955 956 /** @brief Macro to get the TIM1 clock source. 957 * @retval The clock source can be one of the following values: 958 * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock 959 * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock 960 */ 961 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL))) 962 #endif /* RCC_CCIPR_TIM1SEL */ 963 964 #if defined(RCC_CCIPR_TIM15SEL) 965 /** @brief Macro to configure the TIM15 interface clock 966 * @param __TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source. 967 * This parameter can be one of the following values: 968 * @arg RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock 969 * @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock 970 */ 971 #define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \ 972 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__)) 973 974 /** @brief Macro to get the TIM15 clock source. 975 * @retval The clock source can be one of the following values: 976 * @arg @ref RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock 977 * @arg @ref RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock 978 */ 979 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL))) 980 #endif /* RCC_CCIPR_TIM15SEL */ 981 982 #if defined(RCC_CCIPR2_USBSEL) 983 /** @brief Macro to configure the USB interface clock 984 * @param __USB_CLKSOURCE__ specifies the USB digital interface clock source. 985 * This parameter can be one of the following values: 986 * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock (*) 987 * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock 988 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock (*) 989 * (*) Feature not available on all devices 990 */ 991 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 992 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__)) 993 994 /** @brief Macro to get the USB clock source. 995 * @retval The clock source can be one of the following values: 996 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock 997 * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock 998 * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock 999 */ 1000 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) 1001 #endif /* RCC_CCIPR2_USBSEL */ 1002 1003 #if defined(FDCAN1) || defined(FDCAN2) 1004 /** @brief Macro to configure the FDCAN interface clock 1005 * @param __FDCAN_CLKSOURCE__ specifies the FDCAN digital interface clock source. 1006 * This parameter can be one of the following values: 1007 * @arg RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock 1008 * @arg RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock 1009 * @arg RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock 1010 */ 1011 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1012 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 1013 1014 /** @brief Macro to get the FDCAN clock source. 1015 * @retval The clock source can be one of the following values: 1016 * @arg @ref RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock 1017 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock 1018 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock 1019 */ 1020 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL))) 1021 #endif /* FDCAN1 || FDCAN2 */ 1022 1023 #if defined(CRS) 1024 1025 /** 1026 * @brief Enable the specified CRS interrupts. 1027 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1028 * This parameter can be any combination of the following values: 1029 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1030 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1031 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1032 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1033 * @retval None 1034 */ 1035 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1036 1037 /** 1038 * @brief Disable the specified CRS interrupts. 1039 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1040 * This parameter can be any combination of the following values: 1041 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1042 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1043 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1044 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1045 * @retval None 1046 */ 1047 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1048 1049 /** @brief Check whether the CRS interrupt has occurred or not. 1050 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1051 * This parameter can be one of the following values: 1052 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1053 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1054 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1055 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1056 * @retval The new state of __INTERRUPT__ (SET or RESET). 1057 */ 1058 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 1059 1060 /** @brief Clear the CRS interrupt pending bits 1061 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1062 * This parameter can be any combination of the following values: 1063 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1064 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1065 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1066 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1067 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1068 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1069 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1070 */ 1071 /* CRS IT Error Mask */ 1072 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 1073 1074 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1075 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1076 { \ 1077 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1078 } \ 1079 else \ 1080 { \ 1081 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1082 } \ 1083 } while(0) 1084 1085 /** 1086 * @brief Check whether the specified CRS flag is set or not. 1087 * @param __FLAG__ specifies the flag to check. 1088 * This parameter can be one of the following values: 1089 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1090 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1091 * @arg @ref RCC_CRS_FLAG_ERR Error 1092 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1093 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1094 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1095 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1096 * @retval The new state of _FLAG_ (TRUE or FALSE). 1097 */ 1098 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1099 1100 /** 1101 * @brief Clear the CRS specified FLAG. 1102 * @param __FLAG__ specifies the flag to clear. 1103 * This parameter can be one of the following values: 1104 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1105 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1106 * @arg @ref RCC_CRS_FLAG_ERR Error 1107 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1108 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1109 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1110 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1111 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1112 * @retval None 1113 */ 1114 1115 /* CRS Flag Error Mask */ 1116 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 1117 1118 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1119 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1120 { \ 1121 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1122 } \ 1123 else \ 1124 { \ 1125 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1126 } \ 1127 } while(0) 1128 1129 #endif /* CRS */ 1130 1131 /** 1132 * @} 1133 */ 1134 1135 #if defined(CRS) 1136 1137 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1138 * @{ 1139 */ 1140 /** 1141 * @brief Enable the oscillator clock for frequency error counter. 1142 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1143 * @retval None 1144 */ 1145 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1146 1147 /** 1148 * @brief Disable the oscillator clock for frequency error counter. 1149 * @retval None 1150 */ 1151 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1152 1153 /** 1154 * @brief Enable the automatic hardware adjustment of TRIM bits. 1155 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1156 * @retval None 1157 */ 1158 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1159 1160 /** 1161 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1162 * @retval None 1163 */ 1164 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1165 1166 /** 1167 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1168 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1169 * of the synchronization source after prescaling. It is then decreased by one in order to 1170 * reach the expected synchronization on the zero value. The formula is the following: 1171 * RELOAD = (fTARGET / fSYNC) -1 1172 * @param __FTARGET__ Target frequency (value in Hz) 1173 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1174 * @retval None 1175 */ 1176 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1177 1178 /** 1179 * @} 1180 */ 1181 1182 #endif /* CRS */ 1183 1184 /* Exported functions --------------------------------------------------------*/ 1185 /** @addtogroup RCCEx_Exported_Functions 1186 * @{ 1187 */ 1188 1189 /** @addtogroup RCCEx_Exported_Functions_Group1 1190 * @{ 1191 */ 1192 1193 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1194 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1195 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1196 1197 /** 1198 * @} 1199 */ 1200 1201 /** @addtogroup RCCEx_Exported_Functions_Group2 1202 * @{ 1203 */ 1204 1205 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1206 void HAL_RCCEx_DisableLSCO(void); 1207 1208 /** 1209 * @} 1210 */ 1211 1212 #if defined(CRS) 1213 1214 /** @addtogroup RCCEx_Exported_Functions_Group3 1215 * @{ 1216 */ 1217 1218 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1219 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1220 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1221 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1222 void HAL_RCCEx_CRS_IRQHandler(void); 1223 void HAL_RCCEx_CRS_SyncOkCallback(void); 1224 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1225 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1226 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1227 1228 /** 1229 * @} 1230 */ 1231 1232 #endif /* CRS */ 1233 1234 /** 1235 * @} 1236 */ 1237 1238 /* Private macros ------------------------------------------------------------*/ 1239 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 1240 * @{ 1241 */ 1242 1243 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1244 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1245 1246 #if defined(STM32G0C1xx) 1247 1248 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1249 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1250 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1251 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1252 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1253 (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ 1254 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1255 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1256 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1257 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 1258 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1259 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1260 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1261 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1262 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1263 (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 1264 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1265 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1266 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1267 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1268 1269 #elif defined(STM32G0B1xx) 1270 1271 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1272 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1273 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1274 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1275 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1276 (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ 1277 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1278 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1279 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1280 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 1281 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1282 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1283 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1284 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1285 (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 1286 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1287 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1288 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1289 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1290 1291 #elif defined(STM32G0B0xx) 1292 1293 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1294 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1295 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1296 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1297 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1298 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1299 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1300 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 1301 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1302 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1303 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 1304 1305 #elif defined(STM32G081xx) 1306 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1307 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1308 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1309 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1310 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1311 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1312 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1313 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1314 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1315 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1316 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1317 (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 1318 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1319 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1320 #elif defined(STM32G071xx) 1321 1322 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1323 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1324 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1325 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1326 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1327 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1328 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1329 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1330 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1331 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1332 (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 1333 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1334 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1335 1336 #elif defined(STM32G070xx) 1337 1338 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1339 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1340 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1341 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1342 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1343 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1344 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1345 1346 #elif defined(STM32G061xx) 1347 1348 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1349 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1350 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1351 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1352 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1353 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1354 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1355 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1356 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1357 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1358 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1359 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1360 1361 #elif defined(STM32G051xx) 1362 1363 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1364 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1365 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1366 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1367 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1368 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1369 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1370 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1371 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1372 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ 1373 (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) 1374 1375 #elif defined(STM32G041xx) 1376 1377 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1378 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1379 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1380 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1381 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1382 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1383 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1384 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1385 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1386 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1387 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) 1388 1389 #elif defined(STM32G031xx) 1390 1391 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1392 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1393 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1394 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1395 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1396 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1397 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1398 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1399 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1400 (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) 1401 1402 #elif defined(STM32G030xx) || defined(STM32G050xx) 1403 1404 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1405 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1406 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1407 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 1408 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1409 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1410 #endif /* STM32G0C1xx */ 1411 1412 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1413 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ 1414 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1415 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1416 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1417 1418 #if defined(RCC_CCIPR_USART2SEL) 1419 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1420 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1421 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1422 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1423 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1424 #endif /* RCC_CCIPR_USART2SEL */ 1425 1426 #if defined(RCC_CCIPR_USART3SEL) 1427 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1428 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1429 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1430 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1431 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1432 #endif /* RCC_CCIPR_USART3SEL */ 1433 1434 #if defined(LPUART1) 1435 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1436 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 1437 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 1438 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 1439 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 1440 #endif /* LPUART1 */ 1441 1442 #if defined(LPUART2) 1443 #define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \ 1444 (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ 1445 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ 1446 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \ 1447 ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI)) 1448 #endif /* LPUART2 */ 1449 1450 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 1451 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 1452 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ 1453 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 1454 1455 #if defined(RCC_CCIPR_I2C2SEL) 1456 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 1457 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 1458 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ 1459 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 1460 1461 #endif /* RCC_CCIPR_I2C2SEL */ 1462 1463 #define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ 1464 (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ 1465 ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \ 1466 ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \ 1467 ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) 1468 1469 #if defined(RCC_CCIPR2_I2S2SEL) 1470 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) \ 1471 (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \ 1472 ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ 1473 ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ 1474 ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT)) 1475 #endif /* RCC_CCIPR2_I2S2SEL */ 1476 1477 #if defined(RCC_CCIPR_LPTIM1SEL) 1478 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1479 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \ 1480 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1481 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 1482 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 1483 #endif /* RCC_CCIPR_LPTIM1SEL */ 1484 1485 #if defined(RCC_CCIPR_LPTIM2SEL) 1486 #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ 1487 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ 1488 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 1489 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 1490 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 1491 #endif /* RCC_CCIPR_LPTIM2SEL */ 1492 1493 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 1494 (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \ 1495 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ 1496 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) 1497 1498 #if defined(RNG) 1499 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1500 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 1501 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \ 1502 ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \ 1503 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) 1504 #define IS_RCC_RNGDIV(__DIV__) \ 1505 (((__DIV__) == RCC_RNGCLK_DIV1) || \ 1506 ((__DIV__) == RCC_RNGCLK_DIV2) || \ 1507 ((__DIV__) == RCC_RNGCLK_DIV4) || \ 1508 ((__DIV__) == RCC_RNGCLK_DIV8)) 1509 #endif /* RNG */ 1510 1511 #if defined(CEC) 1512 #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ 1513 (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \ 1514 ((__SOURCE__) == RCC_CECCLKSOURCE_LSE)) 1515 #endif /* CEC */ 1516 1517 #if defined(FDCAN1) || defined(FDCAN2) 1518 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 1519 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \ 1520 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \ 1521 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) 1522 1523 #endif /* FDCAN1 */ 1524 1525 #if defined(RCC_HSI48_SUPPORT) 1526 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1527 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \ 1528 ((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ 1529 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 1530 #else 1531 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1532 (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \ 1533 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 1534 #endif /* RCC_HSI48_SUPPORT */ 1535 1536 #if defined(RCC_CCIPR_TIM1SEL) 1537 #define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \ 1538 (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \ 1539 ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1)) 1540 #endif /* RCC_CCIPR_TIM1SEL */ 1541 1542 #if defined(RCC_CCIPR_TIM15SEL) 1543 #define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \ 1544 (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \ 1545 ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1)) 1546 #endif /* RCC_CCIPR_TIM15SEL */ 1547 1548 #if defined(CRS) 1549 1550 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 1551 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1552 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 1553 1554 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1555 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1556 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1557 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1558 1559 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1560 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1561 1562 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 1563 1564 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 1565 1566 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 1567 1568 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1569 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1570 1571 #endif /* CRS */ 1572 1573 /** 1574 * @} 1575 */ 1576 1577 /** 1578 * @} 1579 */ 1580 1581 /** 1582 * @} 1583 */ 1584 1585 #ifdef __cplusplus 1586 } 1587 #endif 1588 1589 #endif /* STM32G0xx_HAL_RCC_EX_H */ 1590 1591
