1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32WBAxx_HAL_RCC_EX_H 21 #define __STM32WBAxx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 #if defined(RCC_LSI2_SUPPORT) 43 /** 44 * @brief RCC LSI2 configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t FreqTempSens; /*!< The temperature at which the frequency temperature sensitivity is close to zero. 49 This parameter can be a value of @ref RCCEx_LSI2_Frequency_Temperature_Sensitivity */ 50 51 uint32_t OpMode; /*!< The operating mode of power consumption versus accuracy. 52 This parameter can be a value of @ref RCCEx_LSI2_Operating_Mode */ 53 } RCC_LSIConfigTypeDef; 54 #endif 55 56 /** 57 * @brief RCC extended clocks structure definition 58 */ 59 typedef struct 60 { 61 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 62 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 63 64 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 65 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 66 67 #if defined (USART2) 68 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 69 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 70 #endif 71 72 73 #if defined (I2C1) 74 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 75 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 76 #endif 77 78 79 80 81 #if defined (LPTIM2) 82 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 83 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 84 #endif 85 86 #if defined (SPI1) 87 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 88 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 89 #endif 90 91 uint32_t SystickClockSelection; /*!< Specifies SYSTICK clock source. 92 This parameter can be a value of @ref RCCEx_SYSTICK_Clock_Source */ 93 94 uint32_t TimIcClockSelection; /*!< Specifies TIMIC clock source. 95 This parameter can be a value of @ref RCCEx_TIMIC_Clock_Source */ 96 97 #if defined (SAI1) 98 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 99 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 100 #endif 101 102 uint32_t RngClockSelection; /*!< Specifies RNG clock source 103 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 104 105 106 #if defined (RCC_CCIPR2_ASSEL) 107 uint32_t AudioSyncClockSelection; /*!< Specifies Audio Sync clock source. 108 This parameter can be a value of @ref RCCEx_AudioSync_Clock_Source */ 109 #endif 110 111 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 112 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 113 114 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source 115 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 116 117 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 118 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 119 120 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 121 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 122 123 uint32_t AdcClockSelection; /*!< Specifies ADC4 interface clock source. 124 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 125 126 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 127 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 128 129 uint32_t RadioSlpTimClockSelection; /*!< Specifies Radio Sleep Timer clock source. 130 This parameter can be a value of @ref RCC_RadioSleepTimer_Clock_Source */ 131 } RCC_PeriphCLKInitTypeDef; 132 133 #if defined(RCC_CCIPR2_ASSEL) 134 /** 135 * @brief RCC extended clocks structure definition 136 */ 137 typedef struct 138 { 139 uint32_t CapturePrescaler; /*!< Capture Prescaler. 140 This parameter can ba a value between 0 and 0x7F */ 141 uint32_t ClockPrescaler; /*!< Clock Prescaler. 142 This parameter can ba a value between 0 and 0x7F */ 143 uint32_t AutoReloadValue; /*!< Auto-reload value. 144 This parameter can be a value between 0 and 0xFFFFF*/ 145 uint32_t CompareValue; /*!< Compare value. 146 This parameter can be a value between 0 and 0xFFFFF*/ 147 } RCC_AudioSyncConfigTypeDef; 148 #endif /* RCC_CCIPR2_ASSEL */ 149 /** 150 * @} 151 */ 152 153 /* Exported constants --------------------------------------------------------*/ 154 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 155 * @{ 156 */ 157 158 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 159 * @{ 160 */ 161 #define RCC_PERIPHCLK_USART1 0x00000001U 162 #if defined (USART2) 163 #define RCC_PERIPHCLK_USART2 0x00000002U 164 #endif 165 #if defined (I2C1) 166 #define RCC_PERIPHCLK_I2C1 0x00000004U 167 #endif 168 #if defined (LPTIM2) 169 #define RCC_PERIPHCLK_LPTIM2 0x00000008U 170 #endif 171 #if defined (SPI1) 172 #define RCC_PERIPHCLK_SPI1 0x00000010U 173 #endif 174 #define RCC_PERIPHCLK_SYSTICK 0x00000020U 175 #define RCC_PERIPHCLK_TIMIC 0x00000040U 176 #if defined (SAI1) 177 #define RCC_PERIPHCLK_SAI1 0x00000080U 178 #endif 179 #define RCC_PERIPHCLK_RNG 0x00000100U 180 #define RCC_PERIPHCLK_LPUART1 0x00000200U 181 #define RCC_PERIPHCLK_SPI3 0x00000400U 182 #define RCC_PERIPHCLK_I2C3 0x00000800U 183 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 184 #define RCC_PERIPHCLK_ADC 0x00002000U 185 #define RCC_PERIPHCLK_RTC 0x00004000U 186 #define RCC_PERIPHCLK_RADIOST 0x00008000U 187 #if defined (RCC_CCIPR2_ASSEL) 188 #define RCC_PERIPHCLK_AUDIOSYNC 0x00200000U 189 #endif 190 /** 191 * @} 192 */ 193 194 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 195 * @{ 196 */ 197 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 198 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 199 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 200 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 201 /** 202 * @} 203 */ 204 205 #if defined (USART2) 206 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 207 * @{ 208 */ 209 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 210 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 211 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 212 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 213 /** 214 * @} 215 */ 216 #endif 217 218 219 #if defined (I2C1) 220 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 221 * @{ 222 */ 223 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 224 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 225 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 226 /** 227 * @} 228 */ 229 #endif 230 231 232 233 234 #if defined (LPTIM2) 235 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 236 * @{ 237 */ 238 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 239 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 240 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 241 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL 242 /** 243 * @} 244 */ 245 #endif 246 247 #if defined (SPI1) 248 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 249 * @{ 250 */ 251 #define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U 252 #define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 253 #define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 254 /** 255 * @} 256 */ 257 #endif 258 259 /** @defgroup RCCEx_SYSTICK_Clock_Source SYSTICK Clock Source 260 * @{ 261 */ 262 #define RCC_SYSTICKCLKSOURCE_HCLK_DIV8 0x00000000U 263 #define RCC_SYSTICKCLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 264 #define RCC_SYSTICKCLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCCEx_TIMIC_Clock_Source RCC Timicsel Items 270 * @{ 271 */ 272 #define RCC_TIMICCLKSOURCE_HSI 0x00000000U /*!< HSI selected for Timer16/17 and LPTimer2 */ 273 #define RCC_TIMICCLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for Timer16/17 and LPTimer2 */ 274 /** 275 * @} 276 */ 277 278 #if defined (SAI1) 279 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 280 * @{ 281 */ 282 #define RCC_SAI1CLKSOURCE_PLL1P 0x00000000U 283 #define RCC_SAI1CLKSOURCE_PLL1Q RCC_CCIPR2_SAI1SEL_0 284 #define RCC_SAI1CLKSOURCE_SYSCLK RCC_CCIPR2_SAI1SEL_1 285 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 286 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 287 /** 288 * @} 289 */ 290 #endif 291 292 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 293 * @{ 294 */ 295 #define RCC_RNGCLKSOURCE_LSE 0x00000000U 296 #define RCC_RNGCLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 297 #define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 298 #define RCC_RNGCLKSOURCE_PLL1Q (RCC_CCIPR2_RNGSEL_0 | RCC_CCIPR2_RNGSEL_1) 299 /** 300 * @} 301 */ 302 303 304 #if defined (RCC_CCIPR2_ASSEL) 305 /** @defgroup RCCEx_AudioSync_Clock_Source Audio Sync Clock Source 306 * @{ 307 */ 308 #define RCC_ASCLKSOURCE_PLL1P 0x00000000U 309 #define RCC_ASCLKSOURCE_PLL1Q RCC_CCIPR2_ASSEL 310 /** 311 * @} 312 */ 313 #endif 314 315 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 316 * @{ 317 */ 318 #define RCC_LPUART1CLKSOURCE_PCLK7 0x00000000U 319 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 320 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 321 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 327 * @{ 328 */ 329 #define RCC_SPI3CLKSOURCE_PCLK7 0x00000000U 330 #define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 331 #define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 337 * @{ 338 */ 339 #define RCC_I2C3CLKSOURCE_PCLK7 0x00000000U 340 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 341 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 347 * @{ 348 */ 349 #define RCC_LPTIM1CLKSOURCE_PCLK7 0x00000000U 350 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 351 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 352 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCCEx_ADC_Clock_Source ADC4 Clock Source 358 * @{ 359 */ 360 #define RCC_ADCCLKSOURCE_HCLK 0x00000000U 361 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 362 #define RCC_ADCCLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 363 #define RCC_ADCCLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_0 | RCC_CCIPR3_ADCSEL_1) 364 #define RCC_ADCCLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 365 /** 366 * @} 367 */ 368 369 /** @defgroup RCC_RadioSleepTimer_Clock_Source Radio Sleep Timer Source 370 * @{ 371 */ 372 #define RCC_RADIOSTCLKSOURCE_DISABLE 0x00000000U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */ 373 #define RCC_RADIOSTCLKSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */ 374 #define RCC_RADIOSTCLKSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */ 375 #define RCC_RADIOSTCLKSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE32 oscillator clock divided by 1000 selected */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 381 * @{ 382 */ 383 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 384 #define RCC_LSCOSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock output */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup RCCEx_LSE_Trimming LSE Trimming 390 * @{ 391 */ 392 #define RCC_LSETRIMMING_R 0x00000000U /*!< Current source resistance R */ 393 #define RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */ 394 #define RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */ 395 #define RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */ 396 /** 397 * @} 398 */ 399 400 #if defined(RCC_LSI2_SUPPORT) 401 /** @defgroup RCCEx_LSI2_Frequency_Temperature_Sensitivity LSI2 Frequency Temperature Sensitivity 402 * @{ 403 */ 404 #define RCC_LSI2_FREQTEMPSENS_80 0x00000000U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */ 405 #define RCC_LSI2_FREQTEMPSENS_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */ 406 #define RCC_LSI2_FREQTEMPSENS_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */ 407 /** 408 * @} 409 */ 410 411 /** @defgroup RCCEx_LSI2_Operating_Mode LSI2 Operating Mode 412 * @{ 413 */ 414 #define RCC_LSI2_MODE_NOMINAL 0x00000000U /*!< Nominal-power, high accuracy */ 415 #define RCC_LSI2_MODE_LP RCC_BDCR2_LSI2MODE_0 /*!< Low-power, medium accuracy */ 416 #define RCC_LSI2_MODE_ULP RCC_BDCR2_LSI2MODE_1 /*!< Ultra-low-power, low accuracy */ 417 /** 418 * @} 419 */ 420 #endif /* RCC_BDCR1_LSI2ON */ 421 422 423 /** @defgroup RCCEx_RADIO_Bus_Clock_Readiness 2.4 GHz RADIO bus clock readiness 424 * @{ 425 */ 426 #define RCC_RADIO_BUS_CLOCK_NOT_READY 0x00000000U /*!< 2.4 GHz RADIO bus clock not ready */ 427 #define RCC_RADIO_BUS_CLOCK_READY RCC_RADIOENR_RADIOCLKRDY /*!< 2.4 GHz RADIO bus clock ready */ 428 /** 429 * @} 430 */ 431 432 /** 433 * @} 434 */ 435 436 /* Exported macros -----------------------------------------------------------*/ 437 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 438 * @{ 439 */ 440 441 /** @brief Macro to configure the USART1 clock (USART1CLK). 442 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 443 * This parameter can be one of the following values: 444 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 445 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 446 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 447 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 448 * @retval None 449 */ 450 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 451 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (__USART1_CLKSOURCE__)) 452 453 /** @brief Macro to get the USART1 clock source. 454 * @retval The clock source can be one of the following values: 455 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 456 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 457 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 458 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 459 */ 460 #define __HAL_RCC_GET_USART1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL) 461 462 #if defined (USART2) 463 /** @brief Macro to configure the USART2 clock (USART2CLK). 464 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 465 * This parameter can be one of the following values: 466 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 467 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 468 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 469 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 470 * @retval None 471 */ 472 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 473 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (__USART2_CLKSOURCE__)) 474 475 /** @brief Macro to get the USART2 clock source. 476 * @retval The clock source can be one of the following values: 477 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 478 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 479 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 480 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 481 */ 482 #define __HAL_RCC_GET_USART2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL) 483 #endif 484 485 486 #if defined (I2C1) 487 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 488 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 489 * This parameter can be one of the following values: 490 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 491 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 492 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 493 * @retval None 494 */ 495 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 496 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (__I2C1_CLKSOURCE__)) 497 498 /** @brief Macro to get the I2C1 clock source. 499 * @retval The clock source can be one of the following values: 500 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 501 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 502 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 503 */ 504 #define __HAL_RCC_GET_I2C1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL) 505 #endif 506 507 508 509 510 #if defined (LPTIM2) 511 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 512 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 513 * This parameter can be one of the following values: 514 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 515 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 516 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 517 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 518 * @retval None 519 */ 520 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 521 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) 522 523 /** @brief Macro to get the LPTIM2 clock source. 524 * @retval The clock source can be one of the following values: 525 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 526 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 527 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 528 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 529 */ 530 #define __HAL_RCC_GET_LPTIM2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL) 531 #endif 532 533 #if defined (SPI1) 534 /** @brief macro to configure the SPI1 clock source. 535 * @param __SPI1_CLKSOURCE__ specifies the SPI1 clock source. 536 * This parameter can be one of the following values: 537 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock 538 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock 539 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock 540 */ 541 #define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__) \ 542 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (__SPI1_CLKSOURCE__)) 543 544 /** @brief macro to get the SPI1 clock source. 545 * @retval The clock source can be one of the following values: 546 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock 547 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock 548 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock 549 */ 550 #define __HAL_RCC_GET_SPI1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL) 551 #endif 552 553 /** @brief macro to configure the SYSTICK clock source. 554 * @param __SYSTICK_CLKSOURCE__ specifies the SYSTICK clock source. 555 * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock 556 * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock 557 * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock 558 */ 559 #define __HAL_RCC_SYSTICK_CONFIG(__SYSTICK_CLKSOURCE__) \ 560 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (__SYSTICK_CLKSOURCE__)) 561 562 /** @brief macro to get the SYSTICK clock source. 563 * @retval The clock source can be one of the following values: 564 * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock 565 * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock 566 * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock 567 */ 568 #define __HAL_RCC_GET_SYSTICK_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL) 569 570 /** @brief macro to configure the TIMIC clock source. 571 * @param __TIMIC_CLKSOURCE__ specifies the TIMIC clock source. 572 * @arg RCC_TIMICCLKSOURCE_HSI : HSI Clock selected as TIMIC clock 573 * @arg RCC_TIMICCLKSOURCE_HSI_DIV256 : HSI divided by 256 Clock selected as TIMIC clock 574 */ 575 #define __HAL_RCC_TIMIC_CONFIG(__TIMIC_CLKSOURCE__) \ 576 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, (__TIMIC_CLKSOURCE__)) 577 578 /** @brief macro to get the TIMIC clock source. 579 * @retval The clock source can be one of the following values: 580 * @arg RCC_TIMICCLKSOURCE_HSI : HSI Clock selected as TIMIC clock 581 * @arg RCC_TIMICCLKSOURCE_HSI_DIV256 : HSI divided by 256 Clock selected as TIMIC clock 582 */ 583 #define __HAL_RCC_GET_TIMIC_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) 584 585 #if defined (SAI1) 586 /** 587 * @brief Macro to configure the SAI1 clock source. 588 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 589 * from the PLL2, system PLL1 or external clock (through a dedicated pin). 590 * This parameter can be one of the following values: 591 * @arg @ref RCC_SAI1CLKSOURCE_PLL1P SAI1 clock = PLL1 "P" clock (PLL1PCLK) 592 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q SAI1 clock = PLL1 "Q" clock (PLL1QCLK) 593 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 594 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 595 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 596 * @retval None 597 */ 598 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 599 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) 600 601 /** @brief Macro to get the SAI1 clock source. 602 * @retval The clock source can be one of the following values: 603 * @arg @ref RCC_SAI1CLKSOURCE_PLL1P SAI1 clock = PLL1 "P" clock (PLL1PCLK) 604 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q SAI1 clock = PLL1 "Q" clock (PLL1QCLK) 605 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 606 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 607 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 608 */ 609 #define __HAL_RCC_GET_SAI1_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL) 610 #endif 611 612 613 #if defined (RCC_CCIPR2_ASSEL) 614 /** @brief macro to configure the Audio Sync clock source. 615 * @param __AS_CLKSOURCE__ specifies the Audio Sync clock source. 616 * @arg RCC_ASCLKSOURCE_PLL1P : PLL1P Clock selected as Audio Sync clock 617 * @arg RCC_ASCLKSOURCE_PLL1Q : PLL1Q Clock selected as Audio Sync clock 618 */ 619 #define __HAL_RCC_AUDIOSYNC_CONFIG(__AS_CLKSOURCE__) \ 620 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ASSEL, (__AS_CLKSOURCE__)) 621 622 /** @brief macro to get the Audio Sync clock source. 623 * @retval The clock source can be one of the following values: 624 * @arg RCC_ASCLKSOURCE_PLL1P : PLL1P Clock selected as Audio Sync clock 625 * @arg RCC_ASCLKSOURCE_PLL1Q : PLL1Q Clock selected as Audio Sync clock 626 */ 627 #define __HAL_RCC_GET_AUDIOSYNC_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ASSEL) 628 #endif 629 630 /** @brief macro to configure the RNG clock (RNGCLK). 631 * @param __RNG_CLKSOURCE__: specifies the RNG clock source. 632 * This parameter can be one of the following values: 633 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 634 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 635 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 636 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 637 * @retval None 638 */ 639 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 640 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (__RNG_CLKSOURCE__)) 641 642 /** @brief macro to get the RNG clock source. 643 * @retval The clock source can be one of the following values: 644 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 645 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 646 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 647 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 648 */ 649 #define __HAL_RCC_GET_RNG_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL) 650 651 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 652 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 653 * This parameter can be one of the following values: 654 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK7 PCLK7 selected as LPUART1 clock 655 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 656 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 657 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 658 * @retval None 659 */ 660 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 661 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 662 663 /** @brief Macro to get the LPUART1 clock source. 664 * @retval The clock source can be one of the following values: 665 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK7 PCLK7 selected as LPUART1 clock 666 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 667 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 668 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 669 */ 670 #define __HAL_RCC_GET_LPUART1_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL) 671 672 /** @brief macro to configure the SPI3 clock source. 673 * @param __SPI3_CLKSOURCE__ specifies the SPI3 clock source.es: 674 * @arg RCC_SPI3CLKSOURCE_PCLK7 : PCLK7 selected as SPI3 clock 675 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock 676 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock 677 */ 678 #define __HAL_RCC_SPI3_CONFIG(__SPI3_CLKSOURCE__) \ 679 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (__SPI3_CLKSOURCE__)) 680 681 /** @brief macro to get the SPI3 clock source. 682 * @retval The clock source can be one of the following values: 683 * @arg RCC_SPI3CLKSOURCE_PCLK7 : PCLK7 selected as SPI3 clock 684 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock 685 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock 686 */ 687 #define __HAL_RCC_GET_SPI3_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL) 688 689 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 690 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 691 * This parameter can be one of the following values: 692 * @arg @ref RCC_I2C3CLKSOURCE_PCLK7 : PCLK7 selected as I2C3 clock 693 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : HSI selected as I2C3 clock 694 * @arg @ref RCC_I2C3CLKSOURCE_HSI : MSIK selected as I2C3 clock 695 * @retval None 696 */ 697 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 698 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (__I2C3_CLKSOURCE__)) 699 700 /** @brief Macro to get the I2C3 clock source. 701 * @retval The clock source can be one of the following values: 702 * @arg @ref RCC_I2C3CLKSOURCE_PCLK7 : PCLK7 selected as I2C3 clock 703 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : HSI selected as I2C3 clock 704 * @arg @ref RCC_I2C3CLKSOURCE_HSI : MSIK selected as I2C3 clock 705 */ 706 #define __HAL_RCC_GET_I2C3_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL) 707 708 709 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 710 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 711 * This parameter can be one of the following values: 712 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK7 PCLK7 selected as LPTIM1 clock 713 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 714 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 715 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 716 * @retval None 717 */ 718 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 719 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 720 721 /** @brief Macro to get the LPTIM1 clock source. 722 * @retval The clock source can be one of the following values: 723 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK7 PCLK7 selected as LPTIM1 clock 724 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 725 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 726 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 727 */ 728 #define __HAL_RCC_GET_LPTIM1_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL) 729 730 /** @brief Macro to configure the ADC4 interface clock. 731 * @param __ADC_CLKSOURCE__ specifies the ADC4 digital interface clock source. 732 * This parameter can be one of the following values: 733 * @arg @ref RCC_ADCCLKSOURCE_HCLK HCLK clock selected as ADC4 clock 734 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK SYSCLK clock selected as ADC4 clock 735 * @arg @ref RCC_ADCCLKSOURCE_PLL1P PLL1P clock selected as ADC4 clock 736 * @arg @ref RCC_ADCCLKSOURCE_HSE HSE clock selected as ADC4 clock 737 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI clock selected as ADC4 clock 738 * @retval None 739 */ 740 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 741 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, (__ADC_CLKSOURCE__)) 742 743 /** @brief Macro to get the ADC clock source. 744 * @retval The clock source can be one of the following values: 745 * @arg @ref RCC_ADCCLKSOURCE_HCLK HCLK clock used as ADC4 clock 746 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK SYSCLK clock used as ADC4 clock 747 * @arg @ref RCC_ADCCLKSOURCE_PLL1P PLL1P clock used as ADC4 clock 748 * @arg @ref RCC_ADCCLKSOURCE_HSE HSE clock used as ADC4 clock 749 * @arg @ref RCC_ADCCLKSOURCE_HSI HSI clock used as ADC4 clock 750 */ 751 #define __HAL_RCC_GET_ADC_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCSEL) 752 753 /** @brief Macro to configure the RADIO Sleep timer clock source. 754 * @param __RADIOST_CLKSOURCE__ specifies the Radio sleep timer clock source. 755 * This parameter can be one of the following values: 756 * @arg @ref RCC_RADIOSTCLKSOURCE_DISABLE 2.4 GHz RADIO sleep timer kernel clock disabled 757 * @arg @ref RCC_RADIOSTCLKSOURCE_LSE LSE oscillator clock selected 758 * @arg @ref RCC_RADIOSTCLKSOURCE_LSI LSI oscillator clock selected 759 * @arg @ref RCC_RADIOSTCLKSOURCE_HSE_DIV1000 HSE32 oscillator clock divided by 1000 selected 760 * @retval None 761 */ 762 #define __HAL_RCC_RADIOSLPTIM_CONFIG(__RADIOST_CLKSOURCE__) \ 763 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, (__RADIOST_CLKSOURCE__)) 764 765 /** @brief Macro to get the RADIO Sleep timer clock source. 766 * @retval The clock source can be one of the following values: 767 * @arg @ref RCC_RADIOSTCLKSOURCE_DISABLE 2.4 GHz RADIO sleep timer kernel clock disabled 768 * @arg @ref RCC_RADIOSTCLKSOURCE_LSE LSE oscillator clock selected 769 * @arg @ref RCC_RADIOSTCLKSOURCE_LSI LSI oscillator clock selected 770 * @arg @ref RCC_RADIOSTCLKSOURCE_HSE_DIV1000 HSE32 oscillator clock divided by 1000 selected 771 */ 772 #define __HAL_RCC_GET_RADIOSLPTIM_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL) 773 774 /** 775 * @} 776 */ 777 778 /* Exported functions --------------------------------------------------------*/ 779 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 780 * @{ 781 */ 782 783 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 784 * @{ 785 */ 786 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 787 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 788 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 789 /** 790 * @} 791 */ 792 793 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions 794 * @{ 795 */ 796 void HAL_RCCEx_EnableLSECSS(void); 797 void HAL_RCCEx_DisableLSECSS(void); 798 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 799 void HAL_RCCEx_DisableLSCO(void); 800 void HAL_RCCEx_HSESetTrimming(uint32_t Trimming); 801 uint32_t HAL_RCCEx_HSEGetTrimming(void); 802 void HAL_RCCEx_LSESetTrimming(uint32_t Trimming); 803 uint32_t HAL_RCCEx_LSEGetTrimming(void); 804 #if defined(RCC_LSI2_SUPPORT) 805 void HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef *pConfig); 806 void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig); 807 #endif /* RCC_BDCR1_LSI2ON */ 808 /** 809 * @} 810 */ 811 812 /** @defgroup RCCEx_Exported_Functions_Group3 Radio Clock management functions 813 * @{ 814 */ 815 void HAL_RCCEx_EnableRadioBBClock(void); 816 void HAL_RCCEx_DisableRadioBBClock(void); 817 void HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void); 818 void HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void); 819 uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); 820 /** 821 * @} 822 */ 823 824 #if defined(RCC_CCIPR2_ASSEL) 825 /** @defgroup RCCEx_Exported_Functions_Group4 Audio Synchronization management functions 826 * @{ 827 */ 828 void HAL_RCCEx_EnableAudioSyncClock(void); 829 void HAL_RCCEx_DisableAudioSyncClock(void); 830 HAL_StatusTypeDef HAL_RCCEx_SetConfigAudioSync(const RCC_AudioSyncConfigTypeDef *pConf); 831 void HAL_RCCEx_GetConfigAudioSync(RCC_AudioSyncConfigTypeDef *pConf); 832 uint32_t HAL_RCCEx_GetAudioSyncCounterValue(void); 833 uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); 834 /** 835 * @} 836 */ 837 #endif /* RCC_CCIPR2_ASSEL */ 838 839 /** 840 * @} 841 */ 842 843 /** @defgroup RCCEx_Private_Constants Private Constants 844 * @{ 845 */ 846 /* Define used for IS_RCC_* macros below */ 847 #if defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined(STM32WBA5Mxx) 848 #if !defined (STM32WBAXX_SI_CUT1_0) 849 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ 850 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ 851 RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ 852 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ 853 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 854 RCC_PERIPHCLK_RADIOST | RCC_PERIPHCLK_AUDIOSYNC) 855 #else 856 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ 857 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ 858 RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ 859 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ 860 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 861 RCC_PERIPHCLK_RADIOST) 862 #endif 863 #elif defined (STM32WBA52xx) 864 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ 865 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ 866 RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_RNG | \ 867 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ 868 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 869 RCC_PERIPHCLK_RADIOST) 870 #elif defined (STM32WBA50xx) 871 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | \ 872 RCC_PERIPHCLK_SYSTICK | \ 873 RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_RNG | \ 874 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ 875 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 876 RCC_PERIPHCLK_RADIOST) 877 #endif 878 /** 879 * @} 880 */ 881 882 /* Private macros ------------------------------------------------------------*/ 883 /** @defgroup RCCEx_Private_Macros Private Macros 884 * @{ 885 */ 886 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 887 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 888 889 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 890 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 891 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 892 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 893 894 #if defined(USART2) 895 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 896 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 897 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 898 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 899 #endif 900 901 902 #if defined(I2C1) 903 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 904 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ 905 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 906 #endif 907 908 909 910 911 #if defined (LPTIM2) 912 #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 913 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 914 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 915 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 916 #endif 917 918 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK7) || \ 919 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 920 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 921 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 922 923 #if defined (SPI1) 924 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ 925 ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \ 926 ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)) 927 #endif 928 929 #define IS_RCC_SYSTICKCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) || \ 930 ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSI) || \ 931 ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSE)) 932 933 #define IS_RCC_TIMICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI) || \ 934 ((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI_DIV256)) 935 936 #if defined(SAI1) 937 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1P) || \ 938 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q) || \ 939 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 940 ((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ 941 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 942 #endif 943 944 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ 945 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ 946 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI) || \ 947 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q)) 948 949 950 #if defined (RCC_CCIPR2_ASSEL) 951 #define IS_RCC_ASCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ASCLKSOURCE_PLL1P) || \ 952 ((__SOURCE__) == RCC_ASCLKSOURCE_PLL1Q)) 953 #endif 954 955 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK7) || \ 956 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 957 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 958 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)) 959 960 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK7) || \ 961 ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \ 962 ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)) 963 964 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK7) || \ 965 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \ 966 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 967 968 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ADCCLKSOURCE_HCLK) || \ 969 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ 970 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL1P) || \ 971 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSE) || \ 972 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) 973 974 #define IS_RCC_RADIOSLEEPTIMERSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RADIOSTCLKSOURCE_DISABLE) || \ 975 ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_LSE) || \ 976 ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_LSI) || \ 977 ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_HSE_DIV1000)) 978 979 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 980 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 981 982 #define IS_RCC_HSETRIM(__TRIM__) ((__TRIM__) <= (RCC_ECSCR1_HSETRIM >> RCC_ECSCR1_HSETRIM_Pos)) 983 984 #define IS_RCC_LSETRIM(__SOURCE__) (((__SOURCE__) == RCC_LSETRIMMING_R) || \ 985 ((__SOURCE__) == RCC_LSETRIMMING_3_4_R) || \ 986 ((__SOURCE__) == RCC_LSETRIMMING_2_3_R) || \ 987 ((__SOURCE__) == RCC_LSETRIMMING_1_2_R)) 988 989 #if defined(RCC_LSI2_SUPPORT) 990 #define IS_RCC_LSI2_FREQTEMPSENS(__SENS__) (((__SENS__) == RCC_LSI2_FREQTEMPSENS_80) || \ 991 ((__SENS__) == RCC_LSI2_FREQTEMPSENS_50) || \ 992 ((__SENS__) == RCC_LSI2_FREQTEMPSENS_20)) 993 994 #define IS_RCC_LSI2_OPERATINGMODE(__MODE__) (((__MODE__) == RCC_LSI2_MODE_NOMINAL) || \ 995 ((__MODE__) == RCC_LSI2_MODE_LP) || \ 996 ((__MODE__) == RCC_LSI2_MODE_ULP)) 997 #endif /* RCC_BDCR1_LSI2ON */ 998 999 #if defined(RCC_CCIPR2_ASSEL) 1000 #define IS_RCC_AUDIOSYNC_CAPTUREPRESCALER(__PRESCALER__) ((__PRESCALER__) <= (RCC_ASCR_CPS >> RCC_ASCR_CPS_Pos)) 1001 1002 #define IS_RCC_AUDIOSYNC_CLOCKPRESCALER(__PRESCALER__) ((__PRESCALER__) <= (RCC_ASCR_PSC >> RCC_ASCR_PSC_Pos)) 1003 1004 #define IS_RCC_AUDIOSYNC_AUTORELOAD(__VALUE__) ((__VALUE__) <= (RCC_ASARR_AR >> RCC_ASARR_AR_Pos)) 1005 1006 #define IS_RCC_AUDIOSYNC_COMPARE(__VALUE__) ((__VALUE__) <= (RCC_ASCOR_CO >> RCC_ASCOR_CO_Pos)) 1007 #endif /* RCC_CCIPR2_ASSEL */ 1008 1009 /** 1010 * @} 1011 */ 1012 1013 /** 1014 * @} 1015 */ 1016 1017 /** 1018 * @} 1019 */ 1020 1021 #ifdef __cplusplus 1022 } 1023 #endif 1024 1025 #endif /* __STM32WBAxx_HAL_RCC_EX_H */ 1026 1027