1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_RCC_EX_H 21 #define STM32C0xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /** @addtogroup STM32C0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC extended clocks structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 50 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 51 52 uint32_t HSIKerClockDivider; /*!< Specifies HSI Kernel divider. 53 This parameter can be a value of @ref RCCEx_HSIKER_Div */ 54 55 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 56 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 57 58 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source 59 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 60 61 uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source 62 This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ 63 64 #if defined(USB_DRD_FS) 65 uint32_t UsbClockSelection; /*!< Specifies USB clock source. 66 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 67 #endif /* USB_DRD_FS */ 68 69 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 70 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 71 72 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 73 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 74 } RCC_PeriphCLKInitTypeDef; 75 76 #if defined (CRS) 77 /** 78 * @brief RCC_CRS Init structure definition 79 */ 80 typedef struct 81 { 82 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 83 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 84 85 uint32_t Source; /*!< Specifies the SYNC signal source. 86 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 87 88 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 89 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 90 91 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 92 event. It can be calculated in using macro 93 @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 94 This parameter must be a number between 0 and 0xFFFF or a value of 95 @ref RCCEx_CRS_ReloadValueDefault .*/ 96 97 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 98 This parameter must be a number between 0 and 0xFF or a value of 99 @ref RCCEx_CRS_ErrorLimitDefault */ 100 101 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 102 This parameter must be a number between 0 and 0x3F or a value of 103 @ref RCCEx_CRS_HSI48CalibrationDefault */ 104 105 } RCC_CRSInitTypeDef; 106 107 /** 108 * @brief RCC_CRS Synchronization structure definition 109 */ 110 typedef struct 111 { 112 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 113 This parameter must be a number between 0 and 0xFFFF */ 114 115 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in RC48 oscillator smooth trimming. 116 This parameter must be a number between 0 and 0x3F */ 117 118 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 119 value latched in the time of the last SYNC event. 120 This parameter must be a number between 0 and 0xFFFF */ 121 122 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 123 frequency error counter latched in the time of the last SYNC event. 124 It shows whether the actual frequency is below or above the target. 125 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 126 127 } RCC_CRSSynchroInfoTypeDef; 128 129 #endif /* CRS */ 130 /** 131 * @} 132 */ 133 134 /* Exported constants --------------------------------------------------------*/ 135 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 136 * @{ 137 */ 138 139 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 140 * @{ 141 */ 142 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 143 #define RCC_LSCOSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock output */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 149 * @{ 150 */ 151 #define RCC_PERIPHCLK_USART1 0x00000001U 152 #define RCC_PERIPHCLK_I2C1 0x00000002U 153 #define RCC_PERIPHCLK_I2S1 0x00000004U 154 #if defined(USB_DRD_FS) 155 #define RCC_PERIPHCLK_USB 0x00000008U 156 #endif /* USB_DRD_FS */ 157 #define RCC_PERIPHCLK_ADC 0x00000020U 158 #define RCC_PERIPHCLK_RTC 0x00000040U 159 #define RCC_PERIPHCLK_HSIKER 0x00000080U 160 161 /** 162 * @} 163 */ 164 165 166 /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source 167 * @{ 168 */ 169 #define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART 1 clock */ 170 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART 1 clock */ 171 #define RCC_USART1CLKSOURCE_HSIKER RCC_CCIPR_USART1SEL_1 /*!< HSI Kernel clock selected as USART 1 clock */ 172 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART 1 clock */ 173 /** 174 * @} 175 */ 176 177 178 /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source 179 * @{ 180 */ 181 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ 182 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ 183 #define RCC_I2C1CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSI Kernel clock selected as I2C1 clock */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source 189 * @{ 190 */ 191 #define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ 192 #define RCC_I2S1CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSI Kernel clock selected as I2S1 clock */ 193 #define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ 194 195 /** 196 * @} 197 */ 198 #if defined(USB_DRD_FS) 199 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 200 * @{ 201 */ 202 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 203 #define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL 204 /** 205 * @} 206 */ 207 #endif /* USB_DRD_FS */ 208 209 /** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source 210 * @{ 211 */ 212 213 #define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ 214 #define RCC_ADCCLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSI kernel used as ADC clock */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCCEx_HSIKER_Div HSIKER Div 220 * @{ 221 */ 222 #define RCC_HSIKER_DIV1 0x00000000U /*!< HSI Kernek clock is not divided */ 223 #define RCC_HSIKER_DIV2 RCC_CR_HSIKERDIV_0 /*!< HSI Kernel clock is divided by 2 */ 224 #define RCC_HSIKER_DIV3 RCC_CR_HSIKERDIV_1 /*!< HSI Kernel clock is divided by 3 */ 225 #define RCC_HSIKER_DIV4 (RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 4 */ 226 #define RCC_HSIKER_DIV5 RCC_CR_HSIKERDIV_2 /*!< HSI Kernel clock is divided by 5 */ 227 #define RCC_HSIKER_DIV6 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 6 */ 228 #define RCC_HSIKER_DIV7 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1) /*!< HSI Kernel clock is divided by 7 */ 229 #define RCC_HSIKER_DIV8 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 8 */ 230 /** 231 * @} 232 */ 233 234 #if defined(CRS) 235 236 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 237 * @{ 238 */ 239 #define RCC_CRS_NONE 0x00000000U 240 #define RCC_CRS_TIMEOUT 0x00000001U 241 #define RCC_CRS_SYNCOK 0x00000002U 242 #define RCC_CRS_SYNCWARN 0x00000004U 243 #define RCC_CRS_SYNCERR 0x00000008U 244 #define RCC_CRS_SYNCMISS 0x00000010U 245 #define RCC_CRS_TRIMOVF 0x00000020U 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 251 * @{ 252 */ 253 #define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ 254 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 255 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 261 * @{ 262 */ 263 #define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ 264 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 265 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 266 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 267 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 268 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 269 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 270 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 276 * @{ 277 */ 278 #define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ 279 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 285 * @{ 286 */ 287 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 288 to a target frequency of 48 MHz and a synchronization 289 signal frequency of 1 kHz (SOF signal from USB). */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 295 * @{ 296 */ 297 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 303 * @{ 304 */ 305 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle 306 of the trimming interval. The trimming step is specified in 307 the product datasheet. A higher TRIM value corresponds 308 to a higher output frequency */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 314 * @{ 315 */ 316 #define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ 317 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 323 * @{ 324 */ 325 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 326 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 327 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 328 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 329 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 330 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 331 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 337 * @{ 338 */ 339 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 340 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 341 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 342 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 343 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 344 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 345 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 346 /** 347 * @} 348 */ 349 350 #endif /* CRS */ 351 352 /** 353 * @} 354 */ 355 356 /* Exported macros -----------------------------------------------------------*/ 357 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 358 * @{ 359 */ 360 361 362 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 363 * 364 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 365 * This parameter can be one of the following values: 366 * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock 367 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 368 */ 369 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 370 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 371 372 /** @brief Macro to get the I2C1 clock source. 373 * @retval The clock source can be one of the following values: 374 * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock 375 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 376 */ 377 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 378 379 /** @brief Macro to configure the I2S1 clock (I2S1CLK). 380 * 381 * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. 382 * This parameter can be one of the following values: 383 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 384 * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock 385 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 386 */ 387 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ 388 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) 389 390 /** @brief Macro to get the I2S1 clock source. 391 * @retval The clock source can be one of the following values: 392 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 393 * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock 394 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 395 */ 396 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) 397 398 399 /** @brief Macro to configure the USART1 clock (USART1CLK). 400 * 401 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 402 * This parameter can be one of the following values: 403 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 404 * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock 405 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 406 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 407 */ 408 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 409 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 410 411 /** @brief Macro to get the USART1 clock source. 412 * @retval The clock source can be one of the following values: 413 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 414 * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock 415 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 416 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 417 */ 418 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 419 420 #if defined(USB_DRD_FS) 421 /** @brief Macro to configure the CLK48 source (CLK48CLK). 422 * 423 * @param __USB_SOURCE__: specifies the CLK48 clock source. 424 * This parameter can be one of the following values: 425 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB source 426 * @arg RCC_USBCLKSOURCE_HSE : HSE selected as USB source 427 */ 428 #define __HAL_RCC_USB_CONFIG(__USB_SOURCE__) \ 429 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_SOURCE__)) 430 431 /** @brief macro to get the USB source. 432 * @retval The clock source can be one of the following values: 433 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 used as USB source 434 * @arg RCC_USBCLKSOURCE_HSE : HSE used as USB source 435 */ 436 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) 437 #endif /* USB_DRD_FS */ 438 439 /** @brief Macro to configure the ADC interface clock 440 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 441 * This parameter can be one of the following values: 442 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 443 * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock 444 */ 445 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 446 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 447 448 /** @brief Macro to get the ADC clock source. 449 * @retval The clock source can be one of the following values: 450 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 451 * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock 452 */ 453 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) 454 455 /** @brief Macro to configure the HSIKER clock. 456 * @param __HSIKERDIV__ specifies the HSI Kernel division factor. 457 * This parameter can be one of the following values: 458 * @arg @ref RCC_HSIKER_DIV1 HSI clock source is divided by 1 459 * @arg @ref RCC_HSIKER_DIV2 HSI clock source is divided by 2 460 * @arg @ref RCC_HSIKER_DIV3 HSI clock source is divided by 3 461 * @arg @ref RCC_HSIKER_DIV4 HSI clock source is divided by 4 462 * @arg @ref RCC_HSIKER_DIV5 HSI clock source is divided by 5 463 * @arg @ref RCC_HSIKER_DIV6 HSI clock source is divided by 6 464 * @arg @ref RCC_HSIKER_DIV7 HSI clock source is divided by 7 465 * @arg @ref RCC_HSIKER_DIV8 HSI clock source is divided by 8 466 */ 467 #define __HAL_RCC_HSIKER_CONFIG(__HSIKERDIV__) \ 468 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, (__HSIKERDIV__)) 469 470 /** @brief Macro to get the HSIKER divider. 471 * @retval The HSI Kernel divider. The returned value can be one 472 * of the following: 473 * - RCC_HSIKER_DIV1 HSI oscillator divided by 1 474 * - RCC_HSIKER_DIV2 HSI oscillator divided by 2 475 * - RCC_HSIKER_DIV3 HSI oscillator divided by 3 (default after reset) 476 * - RCC_HSIKER_DIV4 HSI oscillator divided by 4 477 * - RCC_HSIKER_DIV5 HSI oscillator divided by 5 478 * - RCC_HSIKER_DIV6 HSI oscillator divided by 6 479 * - RCC_HSIKER_DIV7 HSI oscillator divided by 7 480 * - RCC_HSIKER_DIV8 HSI oscillator divided by 8 481 */ 482 #define __HAL_RCC_GET_HSIKER_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIKERDIV))) 483 484 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 485 * @brief macros to manage the specified RCC Flags and interrupts. 486 * @{ 487 */ 488 489 490 /** 491 * @} 492 */ 493 494 #if defined(CRS) 495 496 /** 497 * @brief Enable the specified CRS interrupts. 498 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 499 * This parameter can be any combination of the following values: 500 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 501 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 502 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 503 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 504 * @retval None 505 */ 506 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 507 508 /** 509 * @brief Disable the specified CRS interrupts. 510 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 511 * This parameter can be any combination of the following values: 512 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 513 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 514 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 515 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 516 * @retval None 517 */ 518 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 519 520 /** @brief Check whether the CRS interrupt has occurred or not. 521 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 522 * This parameter can be one of the following values: 523 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 524 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 525 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 526 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 527 * @retval The new state of __INTERRUPT__ (SET or RESET). 528 */ 529 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 530 531 /** @brief Clear the CRS interrupt pending bits 532 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 533 * This parameter can be any combination of the following values: 534 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 535 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 536 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 537 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 538 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 539 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 540 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 541 */ 542 /* CRS IT Error Mask */ 543 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 544 545 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 546 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 547 { \ 548 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 549 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 550 } \ 551 else \ 552 { \ 553 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 554 } \ 555 } while(0) 556 557 /** 558 * @brief Check whether the specified CRS flag is set or not. 559 * @param __FLAG__ specifies the flag to check. 560 * This parameter can be one of the following values: 561 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 562 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 563 * @arg @ref RCC_CRS_FLAG_ERR Error 564 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 565 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 566 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 567 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 568 * @retval The new state of _FLAG_ (TRUE or FALSE). 569 */ 570 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 571 572 /** 573 * @brief Clear the CRS specified FLAG. 574 * @param __FLAG__ specifies the flag to clear. 575 * This parameter can be one of the following values: 576 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 577 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 578 * @arg @ref RCC_CRS_FLAG_ERR Error 579 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 580 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 581 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 582 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 583 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and 584 * consequently RCC_CRS_FLAG_ERR 585 * @retval None 586 */ 587 588 /* CRS Flag Error Mask */ 589 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 590 591 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 592 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 593 { \ 594 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 595 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 596 } \ 597 else \ 598 { \ 599 WRITE_REG(CRS->ICR, (__FLAG__)); \ 600 } \ 601 } while(0) 602 603 604 /** 605 * @} 606 */ 607 608 609 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 610 * @{ 611 */ 612 /** 613 * @brief Enable the oscillator clock for frequency error counter. 614 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 615 * @retval None 616 */ 617 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 618 619 /** 620 * @brief Disable the oscillator clock for frequency error counter. 621 * @retval None 622 */ 623 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 624 625 /** 626 * @brief Enable the automatic hardware adjustment of TRIM bits. 627 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 628 * @retval None 629 */ 630 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 631 632 /** 633 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 634 * @retval None 635 */ 636 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 637 638 /** 639 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 640 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 641 * of the synchronization source after prescaling. It is then decreased by one in order to 642 * reach the expected synchronization on the zero value. The formula is the following: 643 * RELOAD = (fTARGET / fSYNC) -1 644 * @param __FTARGET__ Target frequency (value in Hz) 645 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 646 * @retval None 647 */ 648 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 649 650 /** 651 * @} 652 */ 653 654 #endif /* CRS */ 655 656 /* Exported functions --------------------------------------------------------*/ 657 /** @addtogroup RCCEx_Exported_Functions 658 * @{ 659 */ 660 661 /** @addtogroup RCCEx_Exported_Functions_Group1 662 * @{ 663 */ 664 665 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 666 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 667 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 668 669 /** 670 * @} 671 */ 672 673 /** @addtogroup RCCEx_Exported_Functions_Group2 674 * @{ 675 */ 676 677 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 678 void HAL_RCCEx_DisableLSCO(void); 679 680 /** 681 * @} 682 */ 683 684 #if defined(CRS) 685 686 /** @addtogroup RCCEx_Exported_Functions_Group3 687 * @{ 688 */ 689 690 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 691 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 692 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 693 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 694 void HAL_RCCEx_CRS_IRQHandler(void); 695 void HAL_RCCEx_CRS_SyncOkCallback(void); 696 void HAL_RCCEx_CRS_SyncWarnCallback(void); 697 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 698 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 699 700 /** 701 * @} 702 */ 703 704 #endif /* CRS */ 705 706 /** 707 * @} 708 */ 709 710 /* Private macros ------------------------------------------------------------*/ 711 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 712 * @{ 713 */ 714 715 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 716 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 717 718 #if defined (USB_DRD_FS) 719 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 720 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 721 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 722 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 723 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 724 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 725 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 726 (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) 727 #else 728 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 729 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 730 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 731 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 732 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 733 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 734 (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) 735 #endif /* USB_DRD_FS */ 736 737 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 738 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ 739 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 740 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 741 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSIKER)) 742 743 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 744 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 745 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ 746 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSIKER)) 747 748 #define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ 749 (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ 750 ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSIKER) || \ 751 ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) 752 753 #if defined (USB_DRD_FS) 754 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 755 (((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ 756 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 757 #endif /* USB_DRD_FS */ 758 759 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 760 (((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ 761 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSIKER)) 762 763 #define IS_RCC_HSIKERDIV(__DIV__) (((__DIV__) == RCC_HSIKER_DIV1) || ((__DIV__) == RCC_HSIKER_DIV2) || \ 764 ((__DIV__) == RCC_HSIKER_DIV3) || ((__DIV__) == RCC_HSIKER_DIV4) || \ 765 ((__DIV__) == RCC_HSIKER_DIV5) || ((__DIV__) == RCC_HSIKER_DIV6) || \ 766 ((__DIV__) == RCC_HSIKER_DIV7) || ((__DIV__) == RCC_HSIKER_DIV8)) 767 768 #if defined(CRS) 769 770 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 771 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 772 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 773 774 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 775 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 776 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 777 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 778 779 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 780 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 781 782 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 783 784 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 785 786 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 787 788 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 789 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 790 791 #endif /* CRS */ 792 /** 793 * @} 794 */ 795 796 /** 797 * @} 798 */ 799 800 /** 801 * @} 802 */ 803 804 /** 805 * @} 806 */ 807 808 #ifdef __cplusplus 809 } 810 #endif 811 812 #endif /* STM32C0xx_HAL_RCC_EX_H */ 813
