1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L4xx_HAL_RCC_EX_H 20 #define STM32L4xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l4xx_hal_def.h" 28 29 /** @addtogroup STM32L4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 #if defined(RCC_PLLSAI1_SUPPORT) 44 /** 45 * @brief PLLSAI1 Clock structure definition 46 */ 47 typedef struct 48 { 49 50 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 54 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 56 #else 57 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 58 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 59 #endif 60 61 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 62 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 63 64 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 65 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 66 67 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 68 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 69 70 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 71 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 72 73 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 74 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 75 }RCC_PLLSAI1InitTypeDef; 76 #endif /* RCC_PLLSAI1_SUPPORT */ 77 78 #if defined(RCC_PLLSAI2_SUPPORT) 79 /** 80 * @brief PLLSAI2 Clock structure definition 81 */ 82 typedef struct 83 { 84 85 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 86 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 87 88 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 89 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 90 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 91 #else 92 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 93 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 94 #endif 95 96 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 97 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 98 99 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 100 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 101 102 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 103 uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. 104 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 105 #endif 106 107 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. 108 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 109 110 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 111 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 112 }RCC_PLLSAI2InitTypeDef; 113 114 #endif /* RCC_PLLSAI2_SUPPORT */ 115 116 /** 117 * @brief RCC extended clocks structure definition 118 */ 119 typedef struct 120 { 121 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 122 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 123 #if defined(RCC_PLLSAI1_SUPPORT) 124 125 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 126 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 127 #endif /* RCC_PLLSAI1_SUPPORT */ 128 #if defined(RCC_PLLSAI2_SUPPORT) 129 130 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 131 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 132 133 #endif /* RCC_PLLSAI2_SUPPORT */ 134 135 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 136 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 137 138 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 139 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 140 141 #if defined(USART3) 142 143 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 144 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 145 146 #endif /* USART3 */ 147 148 #if defined(UART4) 149 150 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 151 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 152 153 #endif /* UART4 */ 154 155 #if defined(UART5) 156 157 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 158 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 159 160 #endif /* UART5 */ 161 162 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 163 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 164 165 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 166 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 167 168 #if defined(I2C2) 169 170 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 171 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 172 173 #endif /* I2C2 */ 174 175 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 176 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 177 178 #if defined(I2C4) 179 180 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 181 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 182 183 #endif /* I2C4 */ 184 185 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 186 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 187 188 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 189 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 190 #if defined(SAI1) 191 192 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 193 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 194 #endif /* SAI1 */ 195 196 #if defined(SAI2) 197 198 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 199 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 200 201 #endif /* SAI2 */ 202 203 #if defined(USB_OTG_FS) || defined(USB) 204 205 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 206 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 207 208 #endif /* USB_OTG_FS || USB */ 209 210 #if defined(SDMMC1) 211 212 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 213 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 214 215 #endif /* SDMMC1 */ 216 217 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 218 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 219 220 #if !defined(STM32L412xx) && !defined(STM32L422xx) 221 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 222 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 223 #endif /* !STM32L412xx && !STM32L422xx */ 224 225 #if defined(SWPMI1) 226 227 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. 228 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 229 230 #endif /* SWPMI1 */ 231 232 #if defined(DFSDM1_Filter0) 233 234 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 235 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 236 237 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 238 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 239 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 240 241 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 242 243 #endif /* DFSDM1_Filter0 */ 244 245 #if defined(LTDC) 246 247 uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. 248 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 249 250 #endif /* LTDC */ 251 252 #if defined(DSI) 253 254 uint32_t DsiClockSelection; /*!< Specifies DSI clock source. 255 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 256 257 #endif /* DSI */ 258 259 #if defined(OCTOSPI1) || defined(OCTOSPI2) 260 261 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 262 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 263 264 #endif 265 266 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 267 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 268 }RCC_PeriphCLKInitTypeDef; 269 270 #if defined(CRS) 271 272 /** 273 * @brief RCC_CRS Init structure definition 274 */ 275 typedef struct 276 { 277 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 278 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 279 280 uint32_t Source; /*!< Specifies the SYNC signal source. 281 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 282 283 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 284 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 285 286 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 287 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 288 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 289 290 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 291 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 292 293 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 294 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise, 295 or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 296 297 }RCC_CRSInitTypeDef; 298 299 /** 300 * @brief RCC_CRS Synchronization structure definition 301 */ 302 typedef struct 303 { 304 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 305 This parameter must be a number between 0 and 0xFFFF */ 306 307 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 308 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */ 309 310 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 311 value latched in the time of the last SYNC event. 312 This parameter must be a number between 0 and 0xFFFF */ 313 314 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 315 frequency error counter latched in the time of the last SYNC event. 316 It shows whether the actual frequency is below or above the target. 317 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 318 319 }RCC_CRSSynchroInfoTypeDef; 320 321 #endif /* CRS */ 322 /** 323 * @} 324 */ 325 326 /* Exported constants --------------------------------------------------------*/ 327 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 328 * @{ 329 */ 330 331 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 332 * @{ 333 */ 334 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 335 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 341 * @{ 342 */ 343 #define RCC_PERIPHCLK_USART1 0x00000001U 344 #define RCC_PERIPHCLK_USART2 0x00000002U 345 #if defined(USART3) 346 #define RCC_PERIPHCLK_USART3 0x00000004U 347 #endif 348 #if defined(UART4) 349 #define RCC_PERIPHCLK_UART4 0x00000008U 350 #endif 351 #if defined(UART5) 352 #define RCC_PERIPHCLK_UART5 0x00000010U 353 #endif 354 #define RCC_PERIPHCLK_LPUART1 0x00000020U 355 #define RCC_PERIPHCLK_I2C1 0x00000040U 356 #if defined(I2C2) 357 #define RCC_PERIPHCLK_I2C2 0x00000080U 358 #endif 359 #define RCC_PERIPHCLK_I2C3 0x00000100U 360 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 361 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 362 #if defined(SAI1) 363 #define RCC_PERIPHCLK_SAI1 0x00000800U 364 #endif 365 #if defined(SAI2) 366 #define RCC_PERIPHCLK_SAI2 0x00001000U 367 #endif 368 #if defined(USB_OTG_FS) || defined(USB) 369 #define RCC_PERIPHCLK_USB 0x00002000U 370 #endif 371 #define RCC_PERIPHCLK_ADC 0x00004000U 372 #if defined(SWPMI1) 373 #define RCC_PERIPHCLK_SWPMI1 0x00008000U 374 #endif 375 #if defined(DFSDM1_Filter0) 376 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 377 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 378 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 379 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 380 #endif 381 #define RCC_PERIPHCLK_RTC 0x00020000U 382 #define RCC_PERIPHCLK_RNG 0x00040000U 383 #if defined(SDMMC1) 384 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 385 #endif 386 #if defined(I2C4) 387 #define RCC_PERIPHCLK_I2C4 0x00100000U 388 #endif 389 #if defined(LTDC) 390 #define RCC_PERIPHCLK_LTDC 0x00400000U 391 #endif 392 #if defined(DSI) 393 #define RCC_PERIPHCLK_DSI 0x00800000U 394 #endif 395 #if defined(OCTOSPI1) || defined(OCTOSPI2) 396 #define RCC_PERIPHCLK_OSPI 0x01000000U 397 #endif 398 /** 399 * @} 400 */ 401 402 403 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 404 * @{ 405 */ 406 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 407 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 408 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 409 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 410 /** 411 * @} 412 */ 413 414 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 415 * @{ 416 */ 417 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 418 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 419 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 420 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 421 /** 422 * @} 423 */ 424 425 #if defined(USART3) 426 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 427 * @{ 428 */ 429 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 430 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 431 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 432 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 433 /** 434 * @} 435 */ 436 #endif /* USART3 */ 437 438 #if defined(UART4) 439 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 440 * @{ 441 */ 442 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 443 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 444 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 445 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 446 /** 447 * @} 448 */ 449 #endif /* UART4 */ 450 451 #if defined(UART5) 452 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 453 * @{ 454 */ 455 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 456 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 457 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 458 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 459 /** 460 * @} 461 */ 462 #endif /* UART5 */ 463 464 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 465 * @{ 466 */ 467 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 468 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 469 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 470 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 471 /** 472 * @} 473 */ 474 475 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 476 * @{ 477 */ 478 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 479 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 480 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 481 /** 482 * @} 483 */ 484 485 #if defined(I2C2) 486 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 487 * @{ 488 */ 489 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 490 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 491 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 492 /** 493 * @} 494 */ 495 #endif /* I2C2 */ 496 497 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 498 * @{ 499 */ 500 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 501 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 502 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 503 /** 504 * @} 505 */ 506 507 #if defined(I2C4) 508 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 509 * @{ 510 */ 511 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 512 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 513 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 514 /** 515 * @} 516 */ 517 #endif /* I2C4 */ 518 519 #if defined(SAI1) 520 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 521 * @{ 522 */ 523 #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U 524 #if defined(RCC_PLLSAI2_SUPPORT) 525 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 526 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 527 #else 528 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 529 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 530 #endif /* RCC_PLLSAI2_SUPPORT */ 531 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 532 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 533 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 534 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 535 #else 536 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 537 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL 538 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 539 /** 540 * @} 541 */ 542 #endif /* SAI1 */ 543 544 #if defined(SAI2) 545 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 546 * @{ 547 */ 548 #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U 549 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 550 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 551 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 552 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 553 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 554 #else 555 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 556 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 557 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL 558 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 559 /** 560 * @} 561 */ 562 #endif /* SAI2 */ 563 564 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 565 * @{ 566 */ 567 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 568 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 569 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 570 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 571 /** 572 * @} 573 */ 574 575 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 576 * @{ 577 */ 578 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 579 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 580 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 581 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL 582 /** 583 * @} 584 */ 585 586 #if defined(SDMMC1) 587 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 588 * @{ 589 */ 590 #if defined(RCC_HSI48_SUPPORT) 591 #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ 592 #else 593 #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ 594 #endif /* RCC_HSI48_SUPPORT */ 595 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ 596 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ 597 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ 598 #if defined(RCC_CCIPR2_SDMMCSEL) 599 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ 600 #endif /* RCC_CCIPR2_SDMMCSEL */ 601 /** 602 * @} 603 */ 604 #endif /* SDMMC1 */ 605 606 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 607 * @{ 608 */ 609 #if defined(RCC_HSI48_SUPPORT) 610 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 611 #else 612 #define RCC_RNGCLKSOURCE_NONE 0x00000000U 613 #endif /* RCC_HSI48_SUPPORT */ 614 #if defined(RCC_PLLSAI1_SUPPORT) 615 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 616 #endif /* RCC_PLLSAI1_SUPPORT */ 617 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 618 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 619 /** 620 * @} 621 */ 622 623 #if defined(USB_OTG_FS) || defined(USB) 624 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 625 * @{ 626 */ 627 #if defined(RCC_HSI48_SUPPORT) 628 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 629 #else 630 #define RCC_USBCLKSOURCE_NONE 0x00000000U 631 #endif /* RCC_HSI48_SUPPORT */ 632 #if defined(RCC_PLLSAI1_SUPPORT) 633 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 634 #endif /* RCC_PLLSAI1_SUPPORT */ 635 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 636 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 637 /** 638 * @} 639 */ 640 #endif /* USB_OTG_FS || USB */ 641 642 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 643 * @{ 644 */ 645 #define RCC_ADCCLKSOURCE_NONE 0x00000000U 646 #if defined(RCC_PLLSAI1_SUPPORT) 647 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 648 #endif /* RCC_PLLSAI1_SUPPORT */ 649 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 650 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 651 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 652 #if defined(RCC_CCIPR_ADCSEL) 653 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL 654 #else 655 #define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U 656 #endif /* RCC_CCIPR_ADCSEL */ 657 /** 658 * @} 659 */ 660 661 #if defined(SWPMI1) 662 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source 663 * @{ 664 */ 665 #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U 666 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL 667 /** 668 * @} 669 */ 670 #endif /* SWPMI1 */ 671 672 #if defined(DFSDM1_Filter0) 673 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 674 * @{ 675 */ 676 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 677 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 678 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL 679 #else 680 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL 681 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 682 /** 683 * @} 684 */ 685 686 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 687 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 688 * @{ 689 */ 690 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U 691 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 692 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 693 /** 694 * @} 695 */ 696 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 697 #endif /* DFSDM1_Filter0 */ 698 699 #if defined(LTDC) 700 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 701 * @{ 702 */ 703 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U 704 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 705 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 706 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR 707 /** 708 * @} 709 */ 710 #endif /* LTDC */ 711 712 #if defined(DSI) 713 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 714 * @{ 715 */ 716 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 717 #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL 718 /** 719 * @} 720 */ 721 #endif /* DSI */ 722 723 #if defined(OCTOSPI1) || defined(OCTOSPI2) 724 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 725 * @{ 726 */ 727 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 728 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 729 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 730 /** 731 * @} 732 */ 733 #endif /* OCTOSPI1 || OCTOSPI2 */ 734 735 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 736 * @{ 737 */ 738 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 739 /** 740 * @} 741 */ 742 743 #if defined(CRS) 744 745 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 746 * @{ 747 */ 748 #define RCC_CRS_NONE 0x00000000U 749 #define RCC_CRS_TIMEOUT 0x00000001U 750 #define RCC_CRS_SYNCOK 0x00000002U 751 #define RCC_CRS_SYNCWARN 0x00000004U 752 #define RCC_CRS_SYNCERR 0x00000008U 753 #define RCC_CRS_SYNCMISS 0x00000010U 754 #define RCC_CRS_TRIMOVF 0x00000020U 755 /** 756 * @} 757 */ 758 759 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 760 * @{ 761 */ 762 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 763 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 764 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 765 /** 766 * @} 767 */ 768 769 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 770 * @{ 771 */ 772 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 773 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 774 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 775 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 776 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 777 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 778 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 779 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 780 /** 781 * @} 782 */ 783 784 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 785 * @{ 786 */ 787 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 788 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 789 /** 790 * @} 791 */ 792 793 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 794 * @{ 795 */ 796 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 797 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 798 /** 799 * @} 800 */ 801 802 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 803 * @{ 804 */ 805 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 806 /** 807 * @} 808 */ 809 810 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 811 * @{ 812 */ 813 #if defined(STM32L412xx) || defined(STM32L422xx) 814 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 815 The trimming step is specified in the product datasheet. A higher TRIM value 816 corresponds to a higher output frequency */ 817 #else 818 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 819 The trimming step is specified in the product datasheet. A higher TRIM value 820 corresponds to a higher output frequency */ 821 #endif 822 /** 823 * @} 824 */ 825 826 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 827 * @{ 828 */ 829 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 830 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 831 /** 832 * @} 833 */ 834 835 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 836 * @{ 837 */ 838 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 839 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 840 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 841 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 842 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 843 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 844 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 845 846 /** 847 * @} 848 */ 849 850 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 851 * @{ 852 */ 853 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 854 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 855 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 856 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 857 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 858 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 859 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 860 861 /** 862 * @} 863 */ 864 865 #endif /* CRS */ 866 867 /** 868 * @} 869 */ 870 871 /* Exported macros -----------------------------------------------------------*/ 872 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 873 * @{ 874 */ 875 876 #if defined(RCC_PLLSAI1_SUPPORT) 877 878 /** 879 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 880 * 881 * @note This function must be used only when the PLLSAI1 is disabled. 882 * @note PLLSAI1 clock source is common with the main PLL (configured through 883 * __HAL_RCC_PLL_CONFIG() macro) 884 * 885 @if STM32L4S9xx 886 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 887 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 888 * 889 @endif 890 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 891 * This parameter must be a number between 8 and 86 or 127 depending on devices. 892 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 893 * output frequency is between 64 and 344 MHz. 894 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 895 * 896 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 897 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 898 * else (2 to 31). 899 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 900 * 901 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 902 * This parameter must be in the range (2, 4, 6 or 8). 903 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 904 * 905 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 906 * This parameter must be in the range (2, 4, 6 or 8). 907 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 908 * 909 * @retval None 910 */ 911 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 912 913 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 914 915 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 916 MODIFY_REG(RCC->PLLSAI1CFGR, \ 917 (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 918 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 919 ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 920 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 921 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 922 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 923 ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 924 925 #else 926 927 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 928 MODIFY_REG(RCC->PLLSAI1CFGR, \ 929 (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 930 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ 931 ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 932 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 933 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 934 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 935 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) 936 937 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 938 939 #else 940 941 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 942 943 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 944 MODIFY_REG(RCC->PLLSAI1CFGR, \ 945 (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 946 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 947 (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 948 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 949 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 950 ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 951 952 #else 953 954 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 955 MODIFY_REG(RCC->PLLSAI1CFGR, \ 956 (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ 957 RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ 958 (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 959 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 960 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 961 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) 962 963 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 964 965 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 966 967 /** 968 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 969 * 970 * @note This function must be used only when the PLLSAI1 is disabled. 971 * @note PLLSAI1 clock source is common with the main PLL (configured through 972 * __HAL_RCC_PLL_CONFIG() macro) 973 * 974 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 975 * This parameter must be a number between 8 and 86 or 127 depending on devices. 976 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 977 * output frequency is between 64 and 344 MHz. 978 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 979 * 980 * @retval None 981 */ 982 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 983 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 984 985 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 986 987 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 988 * 989 * @note This function must be used only when the PLLSAI1 is disabled. 990 * @note PLLSAI1 clock source is common with the main PLL (configured through 991 * __HAL_RCC_PLL_CONFIG() macro) 992 * 993 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 994 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 995 * 996 * @retval None 997 */ 998 999 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 1000 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 1001 1002 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 1003 1004 /** @brief Macro to configure the PLLSAI1 clock division factor P. 1005 * 1006 * @note This function must be used only when the PLLSAI1 is disabled. 1007 * @note PLLSAI1 clock source is common with the main PLL (configured through 1008 * __HAL_RCC_PLL_CONFIG() macro) 1009 * 1010 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 1011 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 1012 * else (2 to 31). 1013 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 1014 * 1015 * @retval None 1016 */ 1017 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 1018 1019 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 1020 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 1021 1022 #else 1023 1024 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 1025 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) 1026 1027 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 1028 1029 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 1030 * 1031 * @note This function must be used only when the PLLSAI1 is disabled. 1032 * @note PLLSAI1 clock source is common with the main PLL (configured through 1033 * __HAL_RCC_PLL_CONFIG() macro) 1034 * 1035 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 1036 * This parameter must be in the range (2, 4, 6 or 8). 1037 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 1038 * 1039 * @retval None 1040 */ 1041 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 1042 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 1043 1044 /** @brief Macro to configure the PLLSAI1 clock division factor R. 1045 * 1046 * @note This function must be used only when the PLLSAI1 is disabled. 1047 * @note PLLSAI1 clock source is common with the main PLL (configured through 1048 * __HAL_RCC_PLL_CONFIG() macro) 1049 * 1050 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 1051 * This parameter must be in the range (2, 4, 6 or 8) 1052 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 1053 * 1054 * @retval None 1055 */ 1056 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 1057 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 1058 1059 /** 1060 * @brief Macros to enable or disable the PLLSAI1. 1061 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 1062 * @retval None 1063 */ 1064 1065 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 1066 1067 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 1068 1069 /** 1070 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 1071 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 1072 * This is mainly used to save Power. 1073 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 1074 * This parameter can be one or a combination of the following values: 1075 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 1076 * high-quality audio performance on SAI interface in case. 1077 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 1078 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 1079 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 1080 * @retval None 1081 */ 1082 1083 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1084 1085 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1086 1087 /** 1088 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 1089 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 1090 * This parameter can be one of the following values: 1091 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 1092 * high-quality audio performance on SAI interface in case. 1093 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 1094 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 1095 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 1096 * @retval SET / RESET 1097 */ 1098 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1099 1100 #endif /* RCC_PLLSAI1_SUPPORT */ 1101 1102 #if defined(RCC_PLLSAI2_SUPPORT) 1103 1104 /** 1105 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 1106 * 1107 * @note This function must be used only when the PLLSAI2 is disabled. 1108 * @note PLLSAI2 clock source is common with the main PLL (configured through 1109 * __HAL_RCC_PLL_CONFIG() macro) 1110 * 1111 @if STM32L4S9xx 1112 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 1113 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 1114 * 1115 @endif 1116 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 1117 * This parameter must be a number between 8 and 86. 1118 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 1119 * output frequency is between 64 and 344 MHz. 1120 * 1121 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 1122 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 1123 * else (2 to 31). 1124 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 1125 * 1126 @if STM32L4S9xx 1127 * @param __PLLSAI2Q__ specifies the division factor for DSI clock. 1128 * This parameter must be in the range (2, 4, 6 or 8). 1129 * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q 1130 * 1131 @endif 1132 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. 1133 * This parameter must be in the range (2, 4, 6 or 8). 1134 * 1135 * @retval None 1136 */ 1137 1138 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 1139 1140 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1141 1142 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 1143 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1144 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1145 RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 1146 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 1147 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1148 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 1149 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1150 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 1151 1152 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 1153 1154 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1155 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1156 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1157 RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 1158 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 1159 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1160 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1161 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 1162 1163 # else 1164 1165 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1166 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1167 (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1168 RCC_PLLSAI2CFGR_PLLSAI2R), \ 1169 ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 1170 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1171 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1172 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) 1173 1174 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 1175 1176 #else 1177 1178 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1179 1180 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 1181 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1182 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1183 RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 1184 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1185 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 1186 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1187 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 1188 1189 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 1190 1191 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1192 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1193 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1194 RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 1195 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1196 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1197 ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 1198 1199 # else 1200 1201 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1202 MODIFY_REG(RCC->PLLSAI2CFGR, \ 1203 (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ 1204 RCC_PLLSAI2CFGR_PLLSAI2R), \ 1205 (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1206 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1207 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) 1208 1209 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 1210 1211 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 1212 1213 1214 /** 1215 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 1216 * 1217 * @note This function must be used only when the PLLSAI2 is disabled. 1218 * @note PLLSAI2 clock source is common with the main PLL (configured through 1219 * __HAL_RCC_PLL_CONFIG() macro) 1220 * 1221 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 1222 * This parameter must be a number between 8 and 86. 1223 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 1224 * output frequency is between 64 and 344 MHz. 1225 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 1226 * 1227 * @retval None 1228 */ 1229 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 1230 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 1231 1232 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 1233 1234 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 1235 * 1236 * @note This function must be used only when the PLLSAI2 is disabled. 1237 * @note PLLSAI2 clock source is common with the main PLL (configured through 1238 * __HAL_RCC_PLL_CONFIG() macro) 1239 * 1240 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 1241 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 1242 * 1243 * @retval None 1244 */ 1245 1246 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 1247 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 1248 1249 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 1250 1251 /** @brief Macro to configure the PLLSAI2 clock division factor P. 1252 * 1253 * @note This function must be used only when the PLLSAI2 is disabled. 1254 * @note PLLSAI2 clock source is common with the main PLL (configured through 1255 * __HAL_RCC_PLL_CONFIG() macro) 1256 * 1257 * @param __PLLSAI2P__ specifies the division factor. 1258 * This parameter must be a number in the range (7 or 17). 1259 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 1260 * 1261 * @retval None 1262 */ 1263 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 1264 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 1265 1266 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1267 1268 /** @brief Macro to configure the PLLSAI2 clock division factor Q. 1269 * 1270 * @note This function must be used only when the PLLSAI2 is disabled. 1271 * @note PLLSAI2 clock source is common with the main PLL (configured through 1272 * __HAL_RCC_PLL_CONFIG() macro) 1273 * 1274 * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 1275 * This parameter must be in the range (2, 4, 6 or 8). 1276 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q 1277 * 1278 * @retval None 1279 */ 1280 #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ 1281 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) 1282 1283 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 1284 1285 /** @brief Macro to configure the PLLSAI2 clock division factor R. 1286 * 1287 * @note This function must be used only when the PLLSAI2 is disabled. 1288 * @note PLLSAI2 clock source is common with the main PLL (configured through 1289 * __HAL_RCC_PLL_CONFIG() macro) 1290 * 1291 * @param __PLLSAI2R__ specifies the division factor. 1292 * This parameter must be in the range (2, 4, 6 or 8). 1293 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ 1294 * 1295 * @retval None 1296 */ 1297 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ 1298 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) 1299 1300 /** 1301 * @brief Macros to enable or disable the PLLSAI2. 1302 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 1303 * @retval None 1304 */ 1305 1306 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 1307 1308 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 1309 1310 /** 1311 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 1312 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 1313 * This is mainly used to save Power. 1314 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 1315 * This parameter can be one or a combination of the following values: 1316 @if STM32L486xx 1317 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1318 * high-quality audio performance on SAI interface in case. 1319 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1320 @endif 1321 @if STM32L4A6xx 1322 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1323 * high-quality audio performance on SAI interface in case. 1324 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1325 @endif 1326 @if STM32L4S9xx 1327 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1328 * high-quality audio performance on SAI interface in case. 1329 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 1330 @endif 1331 * @retval None 1332 */ 1333 1334 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1335 1336 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1337 1338 /** 1339 * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 1340 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 1341 * This parameter can be one of the following values: 1342 @if STM32L486xx 1343 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1344 * high-quality audio performance on SAI interface in case. 1345 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1346 @endif 1347 @if STM32L4A6xx 1348 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1349 * high-quality audio performance on SAI interface in case. 1350 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1351 @endif 1352 @if STM32L4S9xx 1353 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1354 * high-quality audio performance on SAI interface in case. 1355 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 1356 @endif 1357 * @retval SET / RESET 1358 */ 1359 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1360 1361 #endif /* RCC_PLLSAI2_SUPPORT */ 1362 1363 #if defined(SAI1) 1364 1365 /** 1366 * @brief Macro to configure the SAI1 clock source. 1367 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 1368 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 1369 * This parameter can be one of the following values: 1370 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1371 @if STM32L486xx 1372 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 1373 @endif 1374 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 1375 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1376 @if STM32L4S9xx 1377 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1378 @endif 1379 * 1380 @if STM32L443xx 1381 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 1382 @endif 1383 * 1384 * @retval None 1385 */ 1386 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1387 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 1388 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) 1389 #else 1390 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 1391 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 1392 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1393 1394 /** @brief Macro to get the SAI1 clock source. 1395 * @retval The clock source can be one of the following values: 1396 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1397 @if STM32L486xx 1398 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 1399 @endif 1400 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 1401 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1402 * 1403 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 1404 * clock source when PLLs are disabled for devices without PLLSAI2. 1405 * 1406 */ 1407 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1408 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) 1409 #else 1410 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 1411 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1412 1413 #endif /* SAI1 */ 1414 1415 #if defined(SAI2) 1416 1417 /** 1418 * @brief Macro to configure the SAI2 clock source. 1419 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 1420 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 1421 * This parameter can be one of the following values: 1422 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1423 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1424 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1425 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1426 @if STM32L4S9xx 1427 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1428 @endif 1429 * 1430 * @retval None 1431 */ 1432 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1433 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1434 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) 1435 #else 1436 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1437 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) 1438 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1439 1440 /** @brief Macro to get the SAI2 clock source. 1441 * @retval The clock source can be one of the following values: 1442 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1443 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1444 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1445 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1446 */ 1447 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1448 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) 1449 #else 1450 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) 1451 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1452 1453 #endif /* SAI2 */ 1454 1455 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1456 * 1457 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1458 * This parameter can be one of the following values: 1459 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1460 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1461 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1462 * @retval None 1463 */ 1464 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1465 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 1466 1467 /** @brief Macro to get the I2C1 clock source. 1468 * @retval The clock source can be one of the following values: 1469 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1470 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1471 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1472 */ 1473 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 1474 1475 #if defined(I2C2) 1476 1477 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1478 * 1479 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1480 * This parameter can be one of the following values: 1481 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1482 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1483 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1484 * @retval None 1485 */ 1486 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1487 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 1488 1489 /** @brief Macro to get the I2C2 clock source. 1490 * @retval The clock source can be one of the following values: 1491 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1492 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1493 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1494 */ 1495 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 1496 1497 #endif /* I2C2 */ 1498 1499 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1500 * 1501 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1502 * This parameter can be one of the following values: 1503 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1504 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1505 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1506 * @retval None 1507 */ 1508 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1509 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 1510 1511 /** @brief Macro to get the I2C3 clock source. 1512 * @retval The clock source can be one of the following values: 1513 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1514 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1515 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1516 */ 1517 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 1518 1519 #if defined(I2C4) 1520 1521 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1522 * 1523 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1524 * This parameter can be one of the following values: 1525 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1526 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1527 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1528 * @retval None 1529 */ 1530 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1531 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 1532 1533 /** @brief Macro to get the I2C4 clock source. 1534 * @retval The clock source can be one of the following values: 1535 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1536 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1537 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1538 */ 1539 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 1540 1541 #endif /* I2C4 */ 1542 1543 1544 /** @brief Macro to configure the USART1 clock (USART1CLK). 1545 * 1546 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1547 * This parameter can be one of the following values: 1548 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1549 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1550 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1551 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1552 * @retval None 1553 */ 1554 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1555 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 1556 1557 /** @brief Macro to get the USART1 clock source. 1558 * @retval The clock source can be one of the following values: 1559 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1560 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1561 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1562 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1563 */ 1564 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 1565 1566 /** @brief Macro to configure the USART2 clock (USART2CLK). 1567 * 1568 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1569 * This parameter can be one of the following values: 1570 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1571 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1572 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1573 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1574 * @retval None 1575 */ 1576 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1577 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 1578 1579 /** @brief Macro to get the USART2 clock source. 1580 * @retval The clock source can be one of the following values: 1581 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1582 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1583 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1584 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1585 */ 1586 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 1587 1588 #if defined(USART3) 1589 1590 /** @brief Macro to configure the USART3 clock (USART3CLK). 1591 * 1592 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1593 * This parameter can be one of the following values: 1594 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1595 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1596 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1597 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1598 * @retval None 1599 */ 1600 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1601 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 1602 1603 /** @brief Macro to get the USART3 clock source. 1604 * @retval The clock source can be one of the following values: 1605 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1606 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1607 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1608 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1609 */ 1610 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 1611 1612 #endif /* USART3 */ 1613 1614 #if defined(UART4) 1615 1616 /** @brief Macro to configure the UART4 clock (UART4CLK). 1617 * 1618 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1619 * This parameter can be one of the following values: 1620 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1621 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1622 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1623 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1624 * @retval None 1625 */ 1626 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1627 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 1628 1629 /** @brief Macro to get the UART4 clock source. 1630 * @retval The clock source can be one of the following values: 1631 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1632 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1633 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1634 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1635 */ 1636 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 1637 1638 #endif /* UART4 */ 1639 1640 #if defined(UART5) 1641 1642 /** @brief Macro to configure the UART5 clock (UART5CLK). 1643 * 1644 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1645 * This parameter can be one of the following values: 1646 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1647 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1648 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1649 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1650 * @retval None 1651 */ 1652 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 1654 1655 /** @brief Macro to get the UART5 clock source. 1656 * @retval The clock source can be one of the following values: 1657 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1658 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1659 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1660 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1661 */ 1662 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 1663 1664 #endif /* UART5 */ 1665 1666 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1667 * 1668 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1669 * This parameter can be one of the following values: 1670 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1671 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1672 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1673 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1674 * @retval None 1675 */ 1676 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1677 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 1678 1679 /** @brief Macro to get the LPUART1 clock source. 1680 * @retval The clock source can be one of the following values: 1681 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1682 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1683 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1684 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1685 */ 1686 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 1687 1688 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1689 * 1690 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1691 * This parameter can be one of the following values: 1692 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1693 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1694 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1695 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1696 * @retval None 1697 */ 1698 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1699 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 1700 1701 /** @brief Macro to get the LPTIM1 clock source. 1702 * @retval The clock source can be one of the following values: 1703 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1704 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 1705 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 1706 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 1707 */ 1708 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 1709 1710 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1711 * 1712 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1713 * This parameter can be one of the following values: 1714 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1715 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1716 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 1717 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1718 * @retval None 1719 */ 1720 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1721 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) 1722 1723 /** @brief Macro to get the LPTIM2 clock source. 1724 * @retval The clock source can be one of the following values: 1725 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1726 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock 1727 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock 1728 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock 1729 */ 1730 #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) 1731 1732 #if defined(SDMMC1) 1733 1734 /** @brief Macro to configure the SDMMC1 clock. 1735 * 1736 @if STM32L486xx 1737 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1738 @endif 1739 * 1740 @if STM32L443xx 1741 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1742 @endif 1743 * 1744 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 1745 * This parameter can be one of the following values: 1746 @if STM32L486xx 1747 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 1748 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1749 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1750 @endif 1751 @if STM32L443xx 1752 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1753 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1754 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1755 @endif 1756 @if STM32L4S9xx 1757 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1758 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1759 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1760 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 1761 @endif 1762 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock 1763 * @retval None 1764 */ 1765 #if defined(RCC_CCIPR2_SDMMCSEL) 1766 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1767 do \ 1768 { \ 1769 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 1770 { \ 1771 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1772 } \ 1773 else \ 1774 { \ 1775 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1776 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ 1777 } \ 1778 } while(0) 1779 #else 1780 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1781 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) 1782 #endif /* RCC_CCIPR2_SDMMCSEL */ 1783 1784 /** @brief Macro to get the SDMMC1 clock. 1785 * @retval The clock source can be one of the following values: 1786 @if STM32L486xx 1787 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 1788 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1789 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1790 @endif 1791 @if STM32L443xx 1792 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1793 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1794 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1795 @endif 1796 @if STM32L4S9xx 1797 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1798 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1799 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1800 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock 1801 @endif 1802 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock 1803 */ 1804 #if defined(RCC_CCIPR2_SDMMCSEL) 1805 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1806 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 1807 #else 1808 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1809 (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1810 #endif /* RCC_CCIPR2_SDMMCSEL */ 1811 1812 #endif /* SDMMC1 */ 1813 1814 /** @brief Macro to configure the RNG clock. 1815 * 1816 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1817 * 1818 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1819 * This parameter can be one of the following values: 1820 @if STM32L486xx 1821 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 1822 @endif 1823 @if STM32L443xx 1824 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 1825 @endif 1826 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1827 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 1828 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 1829 * @retval None 1830 */ 1831 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1832 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 1833 1834 /** @brief Macro to get the RNG clock. 1835 * @retval The clock source can be one of the following values: 1836 @if STM32L486xx 1837 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 1838 @endif 1839 @if STM32L443xx 1840 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 1841 @endif 1842 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1843 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 1844 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 1845 */ 1846 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1847 1848 #if defined(USB_OTG_FS) || defined(USB) 1849 1850 /** @brief Macro to configure the USB clock (USBCLK). 1851 * 1852 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1853 * 1854 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1855 * This parameter can be one of the following values: 1856 @if STM32L486xx 1857 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 1858 @endif 1859 @if STM32L443xx 1860 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1861 @endif 1862 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1863 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1864 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1865 * @retval None 1866 */ 1867 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1868 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 1869 1870 /** @brief Macro to get the USB clock source. 1871 * @retval The clock source can be one of the following values: 1872 @if STM32L486xx 1873 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 1874 @endif 1875 @if STM32L443xx 1876 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1877 @endif 1878 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1879 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1880 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1881 */ 1882 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1883 1884 #endif /* USB_OTG_FS || USB */ 1885 1886 #if defined(RCC_CCIPR_ADCSEL) 1887 1888 /** @brief Macro to configure the ADC interface clock. 1889 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1890 * This parameter can be one of the following values: 1891 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1892 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1893 @if STM32L486xx 1894 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 1895 @endif 1896 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1897 * @retval None 1898 */ 1899 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 1900 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) 1901 1902 /** @brief Macro to get the ADC clock source. 1903 * @retval The clock source can be one of the following values: 1904 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1905 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1906 @if STM32L486xx 1907 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 1908 @endif 1909 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1910 */ 1911 #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) 1912 #else 1913 1914 /** @brief Macro to get the ADC clock source. 1915 * @retval The clock source can be one of the following values: 1916 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1917 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1918 */ 1919 #define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE) 1920 1921 #endif /* RCC_CCIPR_ADCSEL */ 1922 1923 #if defined(SWPMI1) 1924 1925 /** @brief Macro to configure the SWPMI1 clock. 1926 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. 1927 * This parameter can be one of the following values: 1928 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 1929 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 1930 * @retval None 1931 */ 1932 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ 1933 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) 1934 1935 /** @brief Macro to get the SWPMI1 clock source. 1936 * @retval The clock source can be one of the following values: 1937 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 1938 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 1939 */ 1940 #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) 1941 1942 #endif /* SWPMI1 */ 1943 1944 #if defined(DFSDM1_Filter0) 1945 /** @brief Macro to configure the DFSDM1 clock. 1946 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 1947 * This parameter can be one of the following values: 1948 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1949 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1950 * @retval None 1951 */ 1952 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1953 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1954 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 1955 #else 1956 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1957 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 1958 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1959 1960 /** @brief Macro to get the DFSDM1 clock source. 1961 * @retval The clock source can be one of the following values: 1962 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1963 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1964 */ 1965 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1966 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) 1967 #else 1968 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) 1969 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1970 1971 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1972 1973 /** @brief Macro to configure the DFSDM1 audio clock. 1974 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 1975 * This parameter can be one of the following values: 1976 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1977 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1978 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1979 * @retval None 1980 */ 1981 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 1982 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) 1983 1984 /** @brief Macro to get the DFSDM1 audio clock source. 1985 * @retval The clock source can be one of the following values: 1986 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1987 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1988 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1989 */ 1990 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) 1991 1992 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1993 1994 #endif /* DFSDM1_Filter0 */ 1995 1996 #if defined(LTDC) 1997 1998 /** @brief Macro to configure the LTDC clock. 1999 * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. 2000 * This parameter can be one of the following values: 2001 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 2002 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 2003 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 2004 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 2005 * @retval None 2006 */ 2007 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 2008 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) 2009 2010 /** @brief Macro to get the LTDC clock source. 2011 * @retval The clock source can be one of the following values: 2012 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 2013 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 2014 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 2015 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 2016 */ 2017 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) 2018 2019 #endif /* LTDC */ 2020 2021 #if defined(DSI ) 2022 2023 /** @brief Macro to configure the DSI clock. 2024 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 2025 * This parameter can be one of the following values: 2026 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2027 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 2028 * @retval None 2029 */ 2030 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ 2031 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) 2032 2033 /** @brief Macro to get the DSI clock source. 2034 * @retval The clock source can be one of the following values: 2035 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2036 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 2037 */ 2038 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) 2039 2040 #endif /* DSI */ 2041 2042 #if defined(OCTOSPI1) || defined(OCTOSPI2) 2043 2044 /** @brief Macro to configure the OctoSPI clock. 2045 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 2046 * This parameter can be one of the following values: 2047 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 2048 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 2049 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 2050 * @retval None 2051 */ 2052 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 2053 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) 2054 2055 /** @brief Macro to get the OctoSPI clock source. 2056 * @retval The clock source can be one of the following values: 2057 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 2058 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 2059 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 2060 */ 2061 #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) 2062 2063 #endif /* OCTOSPI1 || OCTOSPI2 */ 2064 2065 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 2066 * @brief macros to manage the specified RCC Flags and interrupts. 2067 * @{ 2068 */ 2069 #if defined(RCC_PLLSAI1_SUPPORT) 2070 2071 /** @brief Enable PLLSAI1RDY interrupt. 2072 * @retval None 2073 */ 2074 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 2075 2076 /** @brief Disable PLLSAI1RDY interrupt. 2077 * @retval None 2078 */ 2079 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 2080 2081 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 2082 * @retval None 2083 */ 2084 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 2085 2086 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 2087 * @retval TRUE or FALSE. 2088 */ 2089 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 2090 2091 /** @brief Check whether the PLLSAI1RDY flag is set or not. 2092 * @retval TRUE or FALSE. 2093 */ 2094 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 2095 2096 #endif /* RCC_PLLSAI1_SUPPORT */ 2097 2098 #if defined(RCC_PLLSAI2_SUPPORT) 2099 2100 /** @brief Enable PLLSAI2RDY interrupt. 2101 * @retval None 2102 */ 2103 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 2104 2105 /** @brief Disable PLLSAI2RDY interrupt. 2106 * @retval None 2107 */ 2108 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 2109 2110 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 2111 * @retval None 2112 */ 2113 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 2114 2115 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 2116 * @retval TRUE or FALSE. 2117 */ 2118 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 2119 2120 /** @brief Check whether the PLLSAI2RDY flag is set or not. 2121 * @retval TRUE or FALSE. 2122 */ 2123 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 2124 2125 #endif /* RCC_PLLSAI2_SUPPORT */ 2126 2127 2128 /** 2129 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 2130 * @retval None 2131 */ 2132 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 2133 2134 /** 2135 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 2136 * @retval None 2137 */ 2138 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 2139 2140 /** 2141 * @brief Enable the RCC LSE CSS Event Line. 2142 * @retval None. 2143 */ 2144 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 2145 2146 /** 2147 * @brief Disable the RCC LSE CSS Event Line. 2148 * @retval None. 2149 */ 2150 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 2151 2152 2153 /** 2154 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 2155 * @retval None. 2156 */ 2157 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 2158 2159 2160 /** 2161 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 2162 * @retval None. 2163 */ 2164 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 2165 2166 2167 /** 2168 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 2169 * @retval None. 2170 */ 2171 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 2172 2173 /** 2174 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 2175 * @retval None. 2176 */ 2177 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 2178 2179 /** 2180 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 2181 * @retval None. 2182 */ 2183 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 2184 do { \ 2185 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 2186 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 2187 } while(0) 2188 2189 /** 2190 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 2191 * @retval None. 2192 */ 2193 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 2194 do { \ 2195 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 2196 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 2197 } while(0) 2198 2199 /** 2200 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 2201 * @retval EXTI RCC LSE CSS Line Status. 2202 */ 2203 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 2204 2205 /** 2206 * @brief Clear the RCC LSE CSS EXTI flag. 2207 * @retval None. 2208 */ 2209 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 2210 2211 /** 2212 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 2213 * @retval None. 2214 */ 2215 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 2216 2217 2218 #if defined(CRS) 2219 2220 /** 2221 * @brief Enable the specified CRS interrupts. 2222 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2223 * This parameter can be any combination of the following values: 2224 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2225 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2226 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2227 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2228 * @retval None 2229 */ 2230 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 2231 2232 /** 2233 * @brief Disable the specified CRS interrupts. 2234 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 2235 * This parameter can be any combination of the following values: 2236 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2237 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2238 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2239 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2240 * @retval None 2241 */ 2242 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 2243 2244 /** @brief Check whether the CRS interrupt has occurred or not. 2245 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 2246 * This parameter can be one of the following values: 2247 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2248 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2249 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2250 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2251 * @retval The new state of __INTERRUPT__ (SET or RESET). 2252 */ 2253 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 2254 2255 /** @brief Clear the CRS interrupt pending bits 2256 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2257 * This parameter can be any combination of the following values: 2258 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2259 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2260 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2261 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2262 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 2263 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 2264 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 2265 */ 2266 /* CRS IT Error Mask */ 2267 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 2268 2269 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 2270 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 2271 { \ 2272 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 2273 } \ 2274 else \ 2275 { \ 2276 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 2277 } \ 2278 } while(0) 2279 2280 /** 2281 * @brief Check whether the specified CRS flag is set or not. 2282 * @param __FLAG__ specifies the flag to check. 2283 * This parameter can be one of the following values: 2284 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2285 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2286 * @arg @ref RCC_CRS_FLAG_ERR Error 2287 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2288 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2289 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2290 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2291 * @retval The new state of _FLAG_ (TRUE or FALSE). 2292 */ 2293 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 2294 2295 /** 2296 * @brief Clear the CRS specified FLAG. 2297 * @param __FLAG__ specifies the flag to clear. 2298 * This parameter can be one of the following values: 2299 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2300 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2301 * @arg @ref RCC_CRS_FLAG_ERR Error 2302 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2303 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2304 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2305 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2306 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 2307 * @retval None 2308 */ 2309 2310 /* CRS Flag Error Mask */ 2311 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 2312 2313 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 2314 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 2315 { \ 2316 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 2317 } \ 2318 else \ 2319 { \ 2320 WRITE_REG(CRS->ICR, (__FLAG__)); \ 2321 } \ 2322 } while(0) 2323 2324 #endif /* CRS */ 2325 2326 /** 2327 * @} 2328 */ 2329 2330 #if defined(CRS) 2331 2332 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 2333 * @{ 2334 */ 2335 /** 2336 * @brief Enable the oscillator clock for frequency error counter. 2337 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 2338 * @retval None 2339 */ 2340 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 2341 2342 /** 2343 * @brief Disable the oscillator clock for frequency error counter. 2344 * @retval None 2345 */ 2346 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 2347 2348 /** 2349 * @brief Enable the automatic hardware adjustment of TRIM bits. 2350 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 2351 * @retval None 2352 */ 2353 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2354 2355 /** 2356 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 2357 * @retval None 2358 */ 2359 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2360 2361 /** 2362 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 2363 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 2364 * of the synchronization source after prescaling. It is then decreased by one in order to 2365 * reach the expected synchronization on the zero value. The formula is the following: 2366 * RELOAD = (fTARGET / fSYNC) -1 2367 * @param __FTARGET__ Target frequency (value in Hz) 2368 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 2369 * @retval None 2370 */ 2371 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 2372 2373 /** 2374 * @} 2375 */ 2376 2377 #endif /* CRS */ 2378 2379 #if defined(PSSI) 2380 2381 /** @defgroup RCCEx_PSSI_Macros_Aliases RCCEx PSSI Macros Aliases 2382 * @{ 2383 */ 2384 2385 #define __HAL_RCC_PSSI_CLK_ENABLE() __HAL_RCC_DCMI_CLK_ENABLE() 2386 2387 #define __HAL_RCC_PSSI_CLK_DISABLE() __HAL_RCC_DCMI_CLK_DISABLE() 2388 2389 #define __HAL_RCC_PSSI_IS_CLK_ENABLED() __HAL_RCC_DCMI_IS_CLK_ENABLED() 2390 2391 #define __HAL_RCC_PSSI_IS_CLK_DISABLED() __HAL_RCC_DCMI_IS_CLK_DISABLED() 2392 2393 #define __HAL_RCC_PSSI_FORCE_RESET() __HAL_RCC_DCMI_FORCE_RESET() 2394 2395 #define __HAL_RCC_PSSI_RELEASE_RESET() __HAL_RCC_DCMI_RELEASE_RESET() 2396 2397 #define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() 2398 2399 #define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() 2400 2401 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() 2402 2403 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() 2404 2405 /** 2406 * @} 2407 */ 2408 2409 #endif /* PSSI */ 2410 2411 /** 2412 * @} 2413 */ 2414 2415 /* Exported functions --------------------------------------------------------*/ 2416 /** @addtogroup RCCEx_Exported_Functions 2417 * @{ 2418 */ 2419 2420 /** @addtogroup RCCEx_Exported_Functions_Group1 2421 * @{ 2422 */ 2423 2424 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2425 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2426 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 2427 2428 /** 2429 * @} 2430 */ 2431 2432 /** @addtogroup RCCEx_Exported_Functions_Group2 2433 * @{ 2434 */ 2435 #if defined(RCC_PLLSAI1_SUPPORT) 2436 2437 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 2438 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 2439 2440 #endif /* RCC_PLLSAI1_SUPPORT */ 2441 2442 #if defined(RCC_PLLSAI2_SUPPORT) 2443 2444 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 2445 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 2446 2447 #endif /* RCC_PLLSAI2_SUPPORT */ 2448 2449 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 2450 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 2451 void HAL_RCCEx_EnableLSECSS(void); 2452 void HAL_RCCEx_DisableLSECSS(void); 2453 void HAL_RCCEx_EnableLSECSS_IT(void); 2454 void HAL_RCCEx_LSECSS_IRQHandler(void); 2455 void HAL_RCCEx_LSECSS_Callback(void); 2456 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 2457 void HAL_RCCEx_DisableLSCO(void); 2458 void HAL_RCCEx_EnableMSIPLLMode(void); 2459 void HAL_RCCEx_DisableMSIPLLMode(void); 2460 #if defined (OCTOSPI1) && defined (OCTOSPI2) 2461 void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2); 2462 #endif /* OCTOSPI1 && OCTOSPI2 */ 2463 2464 /** 2465 * @} 2466 */ 2467 2468 #if defined(CRS) 2469 2470 /** @addtogroup RCCEx_Exported_Functions_Group3 2471 * @{ 2472 */ 2473 2474 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 2475 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 2476 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 2477 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 2478 void HAL_RCCEx_CRS_IRQHandler(void); 2479 void HAL_RCCEx_CRS_SyncOkCallback(void); 2480 void HAL_RCCEx_CRS_SyncWarnCallback(void); 2481 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 2482 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 2483 2484 /** 2485 * @} 2486 */ 2487 2488 #endif /* CRS */ 2489 2490 /** 2491 * @} 2492 */ 2493 2494 /* Private constants ---------------------------------------------------------*/ 2495 /** @addtogroup RCCEx_Private_Constants 2496 * @{ 2497 */ 2498 /* Define used for IS_RCC_* macros below */ 2499 #if defined(STM32L412xx) || defined(STM32L422xx) 2500 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2501 RCC_PERIPHCLK_LPUART1 | \ 2502 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2503 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2504 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ 2505 RCC_PERIPHCLK_RNG) 2506 #elif defined(STM32L431xx) 2507 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2508 RCC_PERIPHCLK_LPUART1 | \ 2509 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2510 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2511 RCC_PERIPHCLK_SAI1 | \ 2512 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 2513 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2514 #elif defined(STM32L432xx) || defined(STM32L442xx) 2515 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 2516 RCC_PERIPHCLK_LPUART1 | \ 2517 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ 2518 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2519 RCC_PERIPHCLK_SAI1 | \ 2520 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | \ 2521 RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG) 2522 #elif defined(STM32L433xx) || defined(STM32L443xx) 2523 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 2524 RCC_PERIPHCLK_LPUART1 | \ 2525 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2526 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2527 RCC_PERIPHCLK_SAI1 | \ 2528 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 2529 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2530 #elif defined(STM32L451xx) 2531 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 2532 RCC_PERIPHCLK_UART4 | \ 2533 RCC_PERIPHCLK_LPUART1 | \ 2534 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2535 RCC_PERIPHCLK_I2C4 | \ 2536 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2537 RCC_PERIPHCLK_SAI1 | \ 2538 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 2539 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2540 #elif defined(STM32L452xx) || defined(STM32L462xx) 2541 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ 2542 RCC_PERIPHCLK_UART4 | \ 2543 RCC_PERIPHCLK_LPUART1 | \ 2544 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2545 RCC_PERIPHCLK_I2C4 | \ 2546 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2547 RCC_PERIPHCLK_SAI1 | \ 2548 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 2549 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2550 #elif defined(STM32L471xx) 2551 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2552 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2553 RCC_PERIPHCLK_LPUART1 | \ 2554 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2555 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2556 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2557 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 2558 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2559 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 2560 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2561 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2562 RCC_PERIPHCLK_LPUART1 | \ 2563 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2564 RCC_PERIPHCLK_I2C4 | \ 2565 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2566 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2567 RCC_PERIPHCLK_USB | \ 2568 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 2569 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2570 #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) 2571 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2572 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2573 RCC_PERIPHCLK_LPUART1 | \ 2574 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2575 RCC_PERIPHCLK_I2C4 | \ 2576 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2577 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2578 RCC_PERIPHCLK_USB | \ 2579 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 2580 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 2581 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC) 2582 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 2583 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2584 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2585 RCC_PERIPHCLK_LPUART1 | \ 2586 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2587 RCC_PERIPHCLK_I2C4 | \ 2588 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2589 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2590 RCC_PERIPHCLK_USB | \ 2591 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 2592 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 2593 RCC_PERIPHCLK_OSPI) 2594 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) 2595 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2596 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2597 RCC_PERIPHCLK_LPUART1 | \ 2598 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2599 RCC_PERIPHCLK_I2C4 | \ 2600 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2601 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2602 RCC_PERIPHCLK_USB | \ 2603 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 2604 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 2605 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC) 2606 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 2607 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2608 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2609 RCC_PERIPHCLK_LPUART1 | \ 2610 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2611 RCC_PERIPHCLK_I2C4 | \ 2612 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2613 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2614 RCC_PERIPHCLK_USB | \ 2615 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \ 2616 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \ 2617 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI) 2618 #else 2619 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 2620 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 2621 RCC_PERIPHCLK_LPUART1 | \ 2622 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 2623 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 2624 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 2625 RCC_PERIPHCLK_USB | \ 2626 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 2627 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1) 2628 #endif /* STM32L412xx || STM32L422xx */ 2629 2630 /** 2631 * @} 2632 */ 2633 2634 /* Private macros ------------------------------------------------------------*/ 2635 /** @addtogroup RCCEx_Private_Macros 2636 * @{ 2637 */ 2638 2639 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 2640 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 2641 2642 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 2643 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 2644 2645 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 2646 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 2647 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 2648 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 2649 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 2650 2651 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 2652 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 2653 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 2654 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 2655 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 2656 2657 #if defined(USART3) 2658 2659 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 2660 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 2661 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 2662 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 2663 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 2664 2665 #endif /* USART3 */ 2666 2667 #if defined(UART4) 2668 2669 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 2670 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 2671 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 2672 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 2673 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 2674 2675 #endif /* UART4 */ 2676 2677 #if defined(UART5) 2678 2679 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 2680 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 2681 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 2682 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 2683 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 2684 2685 #endif /* UART5 */ 2686 2687 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 2688 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 2689 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 2690 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 2691 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 2692 2693 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 2694 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 2695 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 2696 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 2697 2698 #if defined(I2C2) 2699 2700 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 2701 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 2702 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 2703 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 2704 2705 #endif /* I2C2 */ 2706 2707 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 2708 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 2709 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 2710 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 2711 2712 #if defined(I2C4) 2713 2714 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 2715 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 2716 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 2717 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 2718 2719 #endif /* I2C4 */ 2720 2721 #if defined(RCC_PLLSAI2_SUPPORT) 2722 2723 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2724 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2725 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2726 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2727 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2728 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 2729 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 2730 #else 2731 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2732 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2733 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2734 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2735 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 2736 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2737 2738 #elif defined(RCC_PLLSAI1_SUPPORT) 2739 2740 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2741 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2742 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2743 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 2744 2745 #endif /* RCC_PLLSAI2_SUPPORT */ 2746 2747 #if defined(RCC_PLLSAI2_SUPPORT) 2748 2749 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2750 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2751 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2752 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2753 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2754 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 2755 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 2756 #else 2757 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2758 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2759 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2760 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2761 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 2762 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2763 2764 #endif /* RCC_PLLSAI2_SUPPORT */ 2765 2766 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 2767 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 2768 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 2769 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 2770 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 2771 2772 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 2773 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 2774 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 2775 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 2776 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 2777 2778 #if defined(SDMMC1) 2779 #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) 2780 2781 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2782 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ 2783 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2784 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2785 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2786 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2787 2788 #elif defined(RCC_HSI48_SUPPORT) 2789 2790 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2791 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2792 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2793 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2794 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2795 #else 2796 2797 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2798 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ 2799 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2800 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2801 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2802 2803 #endif /* RCC_HSI48_SUPPORT */ 2804 #endif /* SDMMC1 */ 2805 2806 #if defined(RCC_HSI48_SUPPORT) 2807 2808 #if defined(RCC_PLLSAI1_SUPPORT) 2809 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2810 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2811 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2812 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2813 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2814 #else 2815 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2816 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2817 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2818 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2819 #endif /* RCC_PLLSAI1_SUPPORT */ 2820 2821 #else 2822 2823 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2824 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 2825 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2826 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2827 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2828 2829 #endif /* RCC_HSI48_SUPPORT */ 2830 2831 #if defined(USB_OTG_FS) || defined(USB) 2832 #if defined(RCC_HSI48_SUPPORT) 2833 2834 #if defined(RCC_PLLSAI1_SUPPORT) 2835 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2836 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2837 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2838 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2839 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2840 #else 2841 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2842 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2843 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2844 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2845 #endif /* RCC_PLLSAI1_SUPPORT */ 2846 2847 #else 2848 2849 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2850 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ 2851 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2852 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2853 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2854 2855 #endif /* RCC_HSI48_SUPPORT */ 2856 #endif /* USB_OTG_FS || USB */ 2857 2858 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 2859 2860 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2861 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2862 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2863 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ 2864 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2865 2866 #else 2867 2868 #if defined(RCC_PLLSAI1_SUPPORT) 2869 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2870 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2871 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2872 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2873 #else 2874 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2875 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2876 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2877 #endif /* RCC_PLLSAI1_SUPPORT */ 2878 2879 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 2880 2881 #if defined(SWPMI1) 2882 2883 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ 2884 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ 2885 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) 2886 2887 #endif /* SWPMI1 */ 2888 2889 #if defined(DFSDM1_Filter0) 2890 2891 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 2892 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 2893 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 2894 2895 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2896 2897 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 2898 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 2899 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 2900 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 2901 2902 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2903 2904 #endif /* DFSDM1_Filter0 */ 2905 2906 #if defined(LTDC) 2907 2908 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 2909 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ 2910 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ 2911 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ 2912 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) 2913 2914 #endif /* LTDC */ 2915 2916 #if defined(DSI) 2917 2918 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 2919 (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ 2920 ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) 2921 2922 #endif /* DSI */ 2923 2924 #if defined(OCTOSPI1) || defined(OCTOSPI2) 2925 2926 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 2927 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 2928 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 2929 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 2930 2931 #endif /* OCTOSPI1 || OCTOSPI2 */ 2932 2933 #if defined(RCC_PLLSAI1_SUPPORT) 2934 2935 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2936 2937 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 2938 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2939 #else 2940 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 2941 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 2942 2943 #if defined(RCC_PLLSAI1N_MUL_8_127_SUPPORT) 2944 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 2945 #else 2946 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2947 #endif /* RCC_PLLSAI1N_MUL_8_127_SUPPORT */ 2948 2949 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 2950 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2951 #else 2952 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 2953 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 2954 2955 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2956 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2957 2958 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2959 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2960 2961 #endif /* RCC_PLLSAI1_SUPPORT */ 2962 2963 #if defined(RCC_PLLSAI2_SUPPORT) 2964 2965 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2966 2967 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 2968 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2969 #else 2970 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 2971 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 2972 2973 #if defined(RCC_PLLSAI2N_MUL_8_127_SUPPORT) 2974 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 2975 #else 2976 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2977 #endif /* RCC_PLLSAI2N_MUL_8_127_SUPPORT */ 2978 2979 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 2980 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2981 #else 2982 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 2983 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 2984 2985 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 2986 #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2987 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2988 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 2989 2990 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2991 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2992 2993 #endif /* RCC_PLLSAI2_SUPPORT */ 2994 2995 #if defined (OCTOSPI1) && defined (OCTOSPI2) 2996 #define IS_RCC_OCTOSPIDELAY(__DELAY__) (((__DELAY__) <= 0xFU)) 2997 #endif /* OCTOSPI1 && OCTOSPI2 */ 2998 2999 #if defined(CRS) 3000 3001 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 3002 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3003 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 3004 3005 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3006 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3007 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3008 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3009 3010 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3011 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3012 3013 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3014 3015 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3016 3017 #if defined(STM32L412xx) || defined(STM32L422xx) 3018 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 3019 #else 3020 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 3021 #endif /* STM32L412xx || STM32L422xx */ 3022 3023 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3024 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3025 3026 #endif /* CRS */ 3027 3028 /** 3029 * @} 3030 */ 3031 3032 /** 3033 * @} 3034 */ 3035 3036 /** 3037 * @} 3038 */ 3039 3040 #ifdef __cplusplus 3041 } 3042 #endif 3043 3044 #endif /* STM32L4xx_HAL_RCC_EX_H */ 3045 3046
