1 /**
2   ******************************************************************************
3   * @file    stm32h573xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32H573xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 #ifndef STM32H573xx_H
27 #define STM32H573xx_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /** @addtogroup ST
34   * @{
35   */
36 
37 
38 /** @addtogroup STM32H573xx
39   * @{
40   */
41 
42 
43 /** @addtogroup Configuration_of_CMSIS
44   * @{
45   */
46 
47 
48 /* =========================================================================================================================== */
49 /* ================                                Interrupt Number Definition                                ================ */
50 /* =========================================================================================================================== */
51 
52 typedef enum
53 {
54 /* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
55   Reset_IRQn                = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
56   NonMaskableInt_IRQn       = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted        */
57   HardFault_IRQn            = -13,    /*!< -13 Hard Fault, all classes of Fault                              */
58   MemoryManagement_IRQn     = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation
59                                                and No Match                                                  */
60   BusFault_IRQn             = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
61                                                related Fault                                                 */
62   UsageFault_IRQn           = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
63   SecureFault_IRQn          =  -9,    /*!< -9  Secure Fault                                                  */
64   SVCall_IRQn               =  -5,    /*!< -5  System Service Call via SVC instruction                       */
65   DebugMonitor_IRQn         =  -4,    /*!< -4  Debug Monitor                                                 */
66   PendSV_IRQn               =  -2,    /*!< -2  Pendable request for system service                           */
67   SysTick_IRQn              =  -1,    /*!< -1  System Tick Timer                                             */
68 
69 /* ===========================================  STM32H573xx Specific Interrupt Numbers  ====================================== */
70   WWDG_IRQn                 = 0,      /*!< Window WatchDog interrupt                                         */
71   PVD_AVD_IRQn              = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
72   RTC_IRQn                  = 2,      /*!< RTC non-secure interrupt                                          */
73   RTC_S_IRQn                = 3,      /*!< RTC secure interrupt                                              */
74   TAMP_IRQn                 = 4,      /*!< Tamper global interrupt                                           */
75   RAMCFG_IRQn               = 5,      /*!< RAMCFG global interrupt                                           */
76   FLASH_IRQn                = 6,      /*!< FLASH non-secure global interrupt                                 */
77   FLASH_S_IRQn              = 7,      /*!< FLASH secure global interrupt                                     */
78   GTZC_IRQn                 = 8,      /*!< Global TrustZone Controller interrupt                             */
79   RCC_IRQn                  = 9,      /*!< RCC non secure global interrupt                                   */
80   RCC_S_IRQn                = 10,     /*!< RCC secure global interrupt                                       */
81   EXTI0_IRQn                = 11,     /*!< EXTI Line0 interrupt                                              */
82   EXTI1_IRQn                = 12,     /*!< EXTI Line1 interrupt                                              */
83   EXTI2_IRQn                = 13,     /*!< EXTI Line2 interrupt                                              */
84   EXTI3_IRQn                = 14,     /*!< EXTI Line3 interrupt                                              */
85   EXTI4_IRQn                = 15,     /*!< EXTI Line4 interrupt                                              */
86   EXTI5_IRQn                = 16,     /*!< EXTI Line5 interrupt                                              */
87   EXTI6_IRQn                = 17,     /*!< EXTI Line6 interrupt                                              */
88   EXTI7_IRQn                = 18,     /*!< EXTI Line7 interrupt                                              */
89   EXTI8_IRQn                = 19,     /*!< EXTI Line8 interrupt                                              */
90   EXTI9_IRQn                = 20,     /*!< EXTI Line9 interrupt                                              */
91   EXTI10_IRQn               = 21,     /*!< EXTI Line10 interrupt                                             */
92   EXTI11_IRQn               = 22,     /*!< EXTI Line11 interrupt                                             */
93   EXTI12_IRQn               = 23,     /*!< EXTI Line12 interrupt                                             */
94   EXTI13_IRQn               = 24,     /*!< EXTI Line13 interrupt                                             */
95   EXTI14_IRQn               = 25,     /*!< EXTI Line14 interrupt                                             */
96   EXTI15_IRQn               = 26,     /*!< EXTI Line15 interrupt                                             */
97   GPDMA1_Channel0_IRQn      = 27,     /*!< GPDMA1 Channel 0 global interrupt                                 */
98   GPDMA1_Channel1_IRQn      = 28,     /*!< GPDMA1 Channel 1 global interrupt                                 */
99   GPDMA1_Channel2_IRQn      = 29,     /*!< GPDMA1 Channel 2 global interrupt                                 */
100   GPDMA1_Channel3_IRQn      = 30,     /*!< GPDMA1 Channel 3 global interrupt                                 */
101   GPDMA1_Channel4_IRQn      = 31,     /*!< GPDMA1 Channel 4 global interrupt                                 */
102   GPDMA1_Channel5_IRQn      = 32,     /*!< GPDMA1 Channel 5 global interrupt                                 */
103   GPDMA1_Channel6_IRQn      = 33,     /*!< GPDMA1 Channel 6 global interrupt                                 */
104   GPDMA1_Channel7_IRQn      = 34,     /*!< GPDMA1 Channel 7 global interrupt                                 */
105   IWDG_IRQn                 = 35,     /*!< IWDG global interrupt                                             */
106   SAES_IRQn                 = 36,     /*!< Secure AES global interrupt                                       */
107   ADC1_IRQn                 = 37,     /*!< ADC1 global interrupt                                             */
108   DAC1_IRQn                 = 38,     /*!< DAC1 global interrupt                                             */
109   FDCAN1_IT0_IRQn           = 39,     /*!< FDCAN1 interrupt 0                                                */
110   FDCAN1_IT1_IRQn           = 40,     /*!< FDCAN1 interrupt 1                                                */
111   TIM1_BRK_IRQn             = 41,     /*!< TIM1 Break interrupt                                              */
112   TIM1_UP_IRQn              = 42,     /*!< TIM1 Update interrupt                                             */
113   TIM1_TRG_COM_IRQn         = 43,     /*!< TIM1 Trigger and Commutation interrupt                            */
114   TIM1_CC_IRQn              = 44,     /*!< TIM1 Capture Compare interrupt                                    */
115   TIM2_IRQn                 = 45,     /*!< TIM2 global interrupt                                             */
116   TIM3_IRQn                 = 46,     /*!< TIM3 global interrupt                                             */
117   TIM4_IRQn                 = 47,     /*!< TIM4 global interrupt                                             */
118   TIM5_IRQn                 = 48,     /*!< TIM5 global interrupt                                             */
119   TIM6_IRQn                 = 49,     /*!< TIM6 global interrupt                                             */
120   TIM7_IRQn                 = 50,     /*!< TIM7 global interrupt                                             */
121   I2C1_EV_IRQn              = 51,     /*!< I2C1 Event interrupt                                              */
122   I2C1_ER_IRQn              = 52,     /*!< I2C1 Error interrupt                                              */
123   I2C2_EV_IRQn              = 53,     /*!< I2C2 Event interrupt                                              */
124   I2C2_ER_IRQn              = 54,     /*!< I2C2 Error interrupt                                              */
125   SPI1_IRQn                 = 55,     /*!< SPI1 global interrupt                                             */
126   SPI2_IRQn                 = 56,     /*!< SPI2 global interrupt                                             */
127   SPI3_IRQn                 = 57,     /*!< SPI3 global interrupt                                             */
128   USART1_IRQn               = 58,     /*!< USART1 global interrupt                                           */
129   USART2_IRQn               = 59,     /*!< USART2 global interrupt                                           */
130   USART3_IRQn               = 60,     /*!< USART3 global interrupt                                           */
131   UART4_IRQn                = 61,     /*!< UART4 global interrupt                                            */
132   UART5_IRQn                = 62,     /*!< UART5 global interrupt                                            */
133   LPUART1_IRQn              = 63,     /*!< LPUART1 global interrupt                                          */
134   LPTIM1_IRQn               = 64,     /*!< LPTIM1 global interrupt                                           */
135   TIM8_BRK_IRQn             = 65,     /*!< TIM8 Break interrupt                                              */
136   TIM8_UP_IRQn              = 66,     /*!< TIM8 Update interrupt                                             */
137   TIM8_TRG_COM_IRQn         = 67,     /*!< TIM8 Trigger and Commutation interrupt                            */
138   TIM8_CC_IRQn              = 68,     /*!< TIM8 Capture Compare interrupt                                    */
139   ADC2_IRQn                 = 69,     /*!< ADC2 global interrupt                                             */
140   LPTIM2_IRQn               = 70,     /*!< LPTIM2 global interrupt                                           */
141   TIM15_IRQn                = 71,     /*!< TIM15 global interrupt                                            */
142   TIM16_IRQn                = 72,     /*!< TIM16 global interrupt                                            */
143   TIM17_IRQn                = 73,     /*!< TIM17 global interrupt                                            */
144   USB_DRD_FS_IRQn           = 74,     /*!< USB FS global interrupt                                           */
145   CRS_IRQn                  = 75,     /*!< CRS global interrupt                                              */
146   UCPD1_IRQn                = 76,     /*!< UCPD1 global interrupt                                            */
147   FMC_IRQn                  = 77,     /*!< FMC global interrupt                                              */
148   OCTOSPI1_IRQn             = 78,     /*!< OctoSPI1 global interrupt                                         */
149   SDMMC1_IRQn               = 79,     /*!< SDMMC1 global interrupt                                           */
150   I2C3_EV_IRQn              = 80,     /*!< I2C3 event interrupt                                              */
151   I2C3_ER_IRQn              = 81,     /*!< I2C3 error interrupt                                              */
152   SPI4_IRQn                 = 82,     /*!< SPI4 global interrupt                                             */
153   SPI5_IRQn                 = 83,     /*!< SPI5 global interrupt                                             */
154   SPI6_IRQn                 = 84,     /*!< SPI6 global interrupt                                             */
155   USART6_IRQn               = 85,     /*!< USART6 global interrupt                                           */
156   USART10_IRQn              = 86,     /*!< USART10 global interrupt                                          */
157   USART11_IRQn              = 87,     /*!< USART11 global interrupt                                          */
158   SAI1_IRQn                 = 88,     /*!< Serial Audio Interface 1 global interrupt                         */
159   SAI2_IRQn                 = 89,     /*!< Serial Audio Interface 2 global interrupt                         */
160   GPDMA2_Channel0_IRQn      = 90,     /*!< GPDMA2 Channel 0 global interrupt                                 */
161   GPDMA2_Channel1_IRQn      = 91,     /*!< GPDMA2 Channel 1 global interrupt                                 */
162   GPDMA2_Channel2_IRQn      = 92,     /*!< GPDMA2 Channel 2 global interrupt                                 */
163   GPDMA2_Channel3_IRQn      = 93,     /*!< GPDMA2 Channel 3 global interrupt                                 */
164   GPDMA2_Channel4_IRQn      = 94,     /*!< GPDMA2 Channel 4 global interrupt                                 */
165   GPDMA2_Channel5_IRQn      = 95,     /*!< GPDMA2 Channel 5 global interrupt                                 */
166   GPDMA2_Channel6_IRQn      = 96,     /*!< GPDMA2 Channel 6 global interrupt                                 */
167   GPDMA2_Channel7_IRQn      = 97,     /*!< GPDMA2 Channel 7 global interrupt                                 */
168   UART7_IRQn                = 98,     /*!< UART7 global interrupt                                            */
169   UART8_IRQn                = 99,     /*!< UART8 global interrupt                                            */
170   UART9_IRQn                = 100,    /*!< UART9 global interrupt                                            */
171   UART12_IRQn               = 101,    /*!< UART12 global interrupt                                           */
172   SDMMC2_IRQn               = 102,    /*!< SDMMC2 global interrupt                                           */
173   FPU_IRQn                  = 103,    /*!< FPU global interrupt                                              */
174   ICACHE_IRQn               = 104,    /*!< Instruction cache global interrupt                                */
175   DCACHE1_IRQn              = 105,    /*!< Data cache global interrupt                                       */
176   ETH_IRQn                  = 106,    /*!< Ethernet global interrupt                                         */
177   ETH_WKUP_IRQn             = 107,    /*!< Ethernet Wakeup global interrupt                                  */
178   DCMI_PSSI_IRQn            = 108,    /*!< DCMI/PSSI global interrupt                                        */
179   FDCAN2_IT0_IRQn           = 109,    /*!< FDCAN2 interrupt 0                                                */
180   FDCAN2_IT1_IRQn           = 110,    /*!< FDCAN2 interrupt 1                                                */
181   CORDIC_IRQn               = 111,    /*!< CORDIC global interrupt                                           */
182   FMAC_IRQn                 = 112,    /*!< FMAC global interrupt                                             */
183   DTS_IRQn                  = 113,    /*!< DTS global interrupt                                              */
184   RNG_IRQn                  = 114,    /*!< RNG global interrupt                                              */
185   OTFDEC1_IRQn              = 115,    /*!< OTFDEC1 global interrupt                                          */
186   AES_IRQn                  = 116,    /*!< AES global interrupt                                              */
187   HASH_IRQn                 = 117,    /*!< HASH global interrupt                                             */
188   PKA_IRQn                  = 118,    /*!< PKA global interrupt                                              */
189   CEC_IRQn                  = 119,    /*!< CEC-HDMI global interrupt                                         */
190   TIM12_IRQn                = 120,    /*!< TIM12 global interrupt                                            */
191   TIM13_IRQn                = 121,    /*!< TIM13 global interrupt                                            */
192   TIM14_IRQn                = 122,    /*!< TIM14 global interrupt                                            */
193   I3C1_EV_IRQn              = 123,    /*!< I3C1 event interrupt                                              */
194   I3C1_ER_IRQn              = 124,    /*!< I3C1 error interrupt                                              */
195   I2C4_EV_IRQn              = 125,    /*!< I2C4 event interrupt                                              */
196   I2C4_ER_IRQn              = 126,    /*!< I2C4 error interrupt                                              */
197   LPTIM3_IRQn               = 127,    /*!< LPTIM3 global interrupt                                           */
198   LPTIM4_IRQn               = 128,    /*!< LPTIM4 global interrupt                                           */
199   LPTIM5_IRQn               = 129,    /*!< LPTIM5 global interrupt                                           */
200   LPTIM6_IRQn               = 130,    /*!< LPTIM6 global interrupt                                           */
201 } IRQn_Type;
202 
203 
204 
205 /* =========================================================================================================================== */
206 /* ================                           Processor and Core Peripheral Section                           ================ */
207 /* =========================================================================================================================== */
208 
209 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
210 #if   defined (__CC_ARM)
211   #pragma push
212   #pragma anon_unions
213 #elif defined (__ICCARM__)
214   #pragma language=extended
215 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
216   #pragma clang diagnostic push
217   #pragma clang diagnostic ignored "-Wc11-extensions"
218   #pragma clang diagnostic ignored "-Wreserved-id-macro"
219 #elif defined (__GNUC__)
220   /* anonymous unions are enabled by default */
221 #elif defined (__TMS470__)
222   /* anonymous unions are enabled by default */
223 #elif defined (__TASKING__)
224   #pragma warning 586
225 #elif defined (__CSMC__)
226   /* anonymous unions are enabled by default */
227 #else
228   #warning Not supported compiler type
229 #endif
230 
231 #define SMPS       /*!< Switched mode power supply feature */
232 
233 /* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ------ */
234 #define __CM33_REV                0x0000U   /* Core revision r0p1 */
235 #define __SAUREGION_PRESENT       1U        /* SAU regions present */
236 #define __MPU_PRESENT             1U        /* MPU present */
237 #define __VTOR_PRESENT            1U        /* VTOR present */
238 #define __NVIC_PRIO_BITS          4U        /* Number of Bits used for Priority Levels */
239 #define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
240 #define __FPU_PRESENT             1U        /* FPU present */
241 #define __DSP_PRESENT             1U        /* DSP extension present */
242 
243 /** @} */ /* End of group Configuration_of_CMSIS */
244 
245 
246 #include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
247 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
248 
249 
250 /* =========================================================================================================================== */
251 /* ================                            Device Specific Peripheral Section                             ================ */
252 /* =========================================================================================================================== */
253 
254 
255 /** @addtogroup STM32H5xx_peripherals
256   * @{
257   */
258 
259 /**
260   * @brief CRC calculation unit
261   */
262 typedef struct
263 {
264   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
265   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
266   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
267        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
268   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
269   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
270        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
271   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
272   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
273   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
274   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
275 } CRC_TypeDef;
276 
277 /**
278   * @brief Inter-integrated Circuit Interface
279   */
280 typedef struct
281 {
282   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
283   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
284   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
285   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
286   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
287   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
288   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
289   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
290   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
291   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
292   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
293 } I2C_TypeDef;
294 
295 /**
296   * @brief Improved Inter-integrated Circuit Interface
297   */
298 typedef struct
299 {
300   __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
301   __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
302   uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
303   __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
304   __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
305   __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
306   __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
307   __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
308   __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
309   uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
310   __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
311   __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
312   uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
313   __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
314   uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
315   __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
316   __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
317   __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
318   uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
319   __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
320   __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
321   uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
322   __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
323   __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
324   uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
325   __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
326   __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
327   __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
328   uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
329   __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
330   __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
331   __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
332   __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
333   __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
334   __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
335 } I3C_TypeDef;
336 
337 /**
338   * @brief DAC
339   */
340 typedef struct
341 {
342   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
343   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
344   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
345   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
346   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
347   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
348   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
349   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
350   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
351   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
352   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
353   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
354   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
355   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
356   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
357   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
358   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
359   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
360   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
361   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
362   __IO uint32_t RESERVED[1];
363   __IO uint32_t AUTOCR;      /*!< DAC Autonomous mode register,                         Address offset: 0x54 */
364 } DAC_TypeDef;
365 
366 /**
367   * @brief Clock Recovery System
368   */
369 typedef struct
370 {
371 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
372 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
373 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
374 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
375 } CRS_TypeDef;
376 
377 /**
378   * @brief AES hardware accelerator
379   */
380 typedef struct
381 {
382   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
383   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
384   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
385   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
386   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
387   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
388   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
389   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
390   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
391   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
392   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
393   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
394   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
395   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
396   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
397   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
398   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
399   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
400   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
401   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
402   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
403   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
404   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
405   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x5C */
406        uint32_t RESERVED1[168];/*!< Reserved,                                  Address offset: 0x60 -- 0x2FC */
407   __IO uint32_t IER;          /*!< AES Interrupt Enable Register,              Address offset: 0x300 */
408   __IO uint32_t ISR;          /*!< AES Interrupt Status Register,              Address offset: 0x304 */
409   __IO uint32_t ICR;          /*!< AES Interrupt Clear Register,               Address offset: 0x308 */
410 } AES_TypeDef;
411 
412 /**
413   * @brief HASH
414   */
415 typedef struct
416 {
417   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
418   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
419   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
420   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
421   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
422   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
423        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
424   __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
425 } HASH_TypeDef;
426 
427 /**
428   * @brief HASH_DIGEST
429   */
430 typedef struct
431 {
432   __IO uint32_t HR[16];     /*!< HASH digest registers,          Address offset: 0x310-0x34C */
433 } HASH_DIGEST_TypeDef;
434 
435 /**
436   * @brief RNG
437   */
438 typedef struct
439 {
440   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
441   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
442   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
443   uint32_t RESERVED;
444   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
445 } RNG_TypeDef;
446 
447 /**
448   * @brief Debug MCU
449   */
450 typedef struct
451 {
452   __IO uint32_t IDCODE;       /*!< MCU device ID code,                 Address offset: 0x00  */
453   __IO uint32_t CR;           /*!< Debug MCU configuration register,   Address offset: 0x04  */
454   __IO uint32_t APB1FZR1;     /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08  */
455   __IO uint32_t APB1FZR2;     /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C  */
456   __IO uint32_t APB2FZR;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10  */
457   __IO uint32_t APB3FZR;      /*!< Debug MCU APB3 freeze register,     Address offset: 0x14  */
458        uint32_t RESERVED1[2]; /*!< Reserved,                                    0x18 - 0x1C  */
459   __IO uint32_t AHB1FZR;      /*!< Debug MCU AHB1 freeze register,     Address offset: 0x20  */
460        uint32_t RESERVED2[54]; /*!< Reserved,                                   0x24 - 0xF8  */
461   __IO uint32_t SR;           /*!< Debug MCU SR register,              Address offset: 0xFC  */
462   __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register,      Address offset: 0x100 */
463   __IO uint32_t DBG_AUTH_DEV;  /*!< Debug DBG_AUTH_DEV register,       Address offset: 0x104 */
464   __IO uint32_t DBG_AUTH_ACK;  /*!< Debug DBG_AUTH_ACK register,       Address offset: 0x108 */
465        uint32_t RESERVED3[945]; /*!< Reserved,                                 0x10C - 0xFCC */
466   __IO uint32_t PIDR4;       /*!< Debug MCU Peripheral ID register 4,  Address offset: 0xFD0 */
467   __IO uint32_t PIDR5;       /*!< Debug MCU Peripheral ID register 5,  Address offset: 0xFD4 */
468   __IO uint32_t PIDR6;       /*!< Debug MCU Peripheral ID register 6,  Address offset: 0xFD8 */
469   __IO uint32_t PIDR7;       /*!< Debug MCU Peripheral ID register 7,  Address offset: 0xFDC */
470   __IO uint32_t PIDR0;       /*!< Debug MCU Peripheral ID register 0,  Address offset: 0xFE0 */
471   __IO uint32_t PIDR1;       /*!< Debug MCU Peripheral ID register 1,  Address offset: 0xFE4 */
472   __IO uint32_t PIDR2;       /*!< Debug MCU Peripheral ID register 2,  Address offset: 0xFE8 */
473   __IO uint32_t PIDR3;       /*!< Debug MCU Peripheral ID register 3,  Address offset: 0xFEC */
474   __IO uint32_t CIDR0;       /*!< Debug MCU Component ID register 0,   Address offset: 0xFF0 */
475   __IO uint32_t CIDR1;       /*!< Debug MCU Component ID register 1,   Address offset: 0xFF4 */
476   __IO uint32_t CIDR2;       /*!< Debug MCU Component ID register 2,   Address offset: 0xFF8 */
477   __IO uint32_t CIDR3;       /*!< Debug MCU Component ID register 3,   Address offset: 0xFFC */
478 } DBGMCU_TypeDef;
479 
480 /**
481   * @brief DCMI
482   */
483 typedef struct
484 {
485   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
486   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
487   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
488   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
489   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
490   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
491   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
492   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
493   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
494   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
495   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
496 } DCMI_TypeDef;
497 
498 /**
499   * @brief PSSI
500   */
501 typedef struct
502 {
503   __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
504   __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
505   __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
506   __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
507   __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
508   __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
509   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
510   __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
511 } PSSI_TypeDef;
512 
513 /**
514   * @brief DMA Controller
515   */
516 typedef struct
517 {
518   __IO uint32_t SECCFGR;     /*!< DMA secure configuration register,               Address offset: 0x00  */
519   __IO uint32_t PRIVCFGR;    /*!< DMA privileged configuration register,           Address offset: 0x04  */
520   __IO uint32_t RCFGLOCKR;   /*!< DMA lock configuration register,                 Address offset: 0x08  */
521   __IO uint32_t MISR;        /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
522   __IO uint32_t SMISR;       /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
523 } DMA_TypeDef;
524 
525 typedef struct
526 {
527   __IO uint32_t CLBAR;        /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
528        uint32_t RESERVED1[2]; /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
529   __IO uint32_t CFCR;         /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
530   __IO uint32_t CSR;          /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
531   __IO uint32_t CCR;          /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
532        uint32_t RESERVED2[10];/*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
533   __IO uint32_t CTR1;         /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
534   __IO uint32_t CTR2;         /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
535   __IO uint32_t CBR1;         /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
536   __IO uint32_t CSAR;         /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
537   __IO uint32_t CDAR;         /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
538   __IO uint32_t CTR3;         /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
539   __IO uint32_t CBR2;         /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
540        uint32_t RESERVED3[8]; /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
541   __IO uint32_t CLLR;         /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
542 } DMA_Channel_TypeDef;
543 
544 /**
545   * @brief Ethernet MAC
546   */
547 typedef struct
548 {
549   __IO uint32_t MACCR;
550   __IO uint32_t MACECR;
551   __IO uint32_t MACPFR;
552   __IO uint32_t MACWTR;
553   __IO uint32_t MACHT0R;
554   __IO uint32_t MACHT1R;
555   uint32_t      RESERVED1[14];
556   __IO uint32_t MACVTR;
557   uint32_t      RESERVED2;
558   __IO uint32_t MACVHTR;
559   uint32_t      RESERVED3;
560   __IO uint32_t MACVIR;
561   __IO uint32_t MACIVIR;
562   uint32_t      RESERVED4[2];
563   __IO uint32_t MACTFCR;
564   uint32_t      RESERVED5[7];
565   __IO uint32_t MACRFCR;
566   uint32_t      RESERVED6[7];
567   __IO uint32_t MACISR;
568   __IO uint32_t MACIER;
569   __IO uint32_t MACRXTXSR;
570   uint32_t      RESERVED7;
571   __IO uint32_t MACPCSR;
572   __IO uint32_t MACRWKPFR;
573   uint32_t      RESERVED8[2];
574   __IO uint32_t MACLCSR;
575   __IO uint32_t MACLTCR;
576   __IO uint32_t MACLETR;
577   __IO uint32_t MAC1USTCR;
578   uint32_t      RESERVED9[12];
579   __IO uint32_t MACVR;
580   __IO uint32_t MACDR;
581   uint32_t      RESERVED10;
582   __IO uint32_t MACHWF0R;
583   __IO uint32_t MACHWF1R;
584   __IO uint32_t MACHWF2R;
585   uint32_t      RESERVED11[54];
586   __IO uint32_t MACMDIOAR;
587   __IO uint32_t MACMDIODR;
588   uint32_t      RESERVED12[2];
589   __IO uint32_t MACARPAR;
590   uint32_t      RESERVED13[59];
591   __IO uint32_t MACA0HR;
592   __IO uint32_t MACA0LR;
593   __IO uint32_t MACA1HR;
594   __IO uint32_t MACA1LR;
595   __IO uint32_t MACA2HR;
596   __IO uint32_t MACA2LR;
597   __IO uint32_t MACA3HR;
598   __IO uint32_t MACA3LR;
599   uint32_t      RESERVED14[248];
600   __IO uint32_t MMCCR;
601   __IO uint32_t MMCRIR;
602   __IO uint32_t MMCTIR;
603   __IO uint32_t MMCRIMR;
604   __IO uint32_t MMCTIMR;
605   uint32_t      RESERVED15[14];
606   __IO uint32_t MMCTSCGPR;
607   __IO uint32_t MMCTMCGPR;
608   uint32_t      RESERVED16[5];
609   __IO uint32_t MMCTPCGR;
610   uint32_t      RESERVED17[10];
611   __IO uint32_t MMCRCRCEPR;
612   __IO uint32_t MMCRAEPR;
613   uint32_t      RESERVED18[10];
614   __IO uint32_t MMCRUPGR;
615   uint32_t      RESERVED19[9];
616   __IO uint32_t MMCTLPIMSTR;
617   __IO uint32_t MMCTLPITCR;
618   __IO uint32_t MMCRLPIMSTR;
619   __IO uint32_t MMCRLPITCR;
620   uint32_t      RESERVED20[65];
621   __IO uint32_t MACL3L4C0R;
622   __IO uint32_t MACL4A0R;
623   uint32_t      RESERVED21[2];
624   __IO uint32_t MACL3A0R0R;
625   __IO uint32_t MACL3A1R0R;
626   __IO uint32_t MACL3A2R0R;
627   __IO uint32_t MACL3A3R0R;
628   uint32_t      RESERVED22[4];
629   __IO uint32_t MACL3L4C1R;
630   __IO uint32_t MACL4A1R;
631   uint32_t      RESERVED23[2];
632   __IO uint32_t MACL3A0R1R;
633   __IO uint32_t MACL3A1R1R;
634   __IO uint32_t MACL3A2R1R;
635   __IO uint32_t MACL3A3R1R;
636   uint32_t      RESERVED24[108];
637   __IO uint32_t MACTSCR;
638   __IO uint32_t MACSSIR;
639   __IO uint32_t MACSTSR;
640   __IO uint32_t MACSTNR;
641   __IO uint32_t MACSTSUR;
642   __IO uint32_t MACSTNUR;
643   __IO uint32_t MACTSAR;
644   uint32_t      RESERVED25;
645   __IO uint32_t MACTSSR;
646   uint32_t      RESERVED26[3];
647   __IO uint32_t MACTTSSNR;
648   __IO uint32_t MACTTSSSR;
649   uint32_t      RESERVED27[2];
650   __IO uint32_t MACACR;
651   uint32_t      RESERVED28;
652   __IO uint32_t MACATSNR;
653   __IO uint32_t MACATSSR;
654   __IO uint32_t MACTSIACR;
655   __IO uint32_t MACTSEACR;
656   __IO uint32_t MACTSICNR;
657   __IO uint32_t MACTSECNR;
658   uint32_t      RESERVED29[4];
659   __IO uint32_t MACPPSCR;
660   uint32_t      RESERVED30[3];
661   __IO uint32_t MACPPSTTSR;
662   __IO uint32_t MACPPSTTNR;
663   __IO uint32_t MACPPSIR;
664   __IO uint32_t MACPPSWR;
665   uint32_t      RESERVED31[12];
666   __IO uint32_t MACPOCR;
667   __IO uint32_t MACSPI0R;
668   __IO uint32_t MACSPI1R;
669   __IO uint32_t MACSPI2R;
670   __IO uint32_t MACLMIR;
671   uint32_t      RESERVED32[11];
672   __IO uint32_t MTLOMR;
673   uint32_t      RESERVED33[7];
674   __IO uint32_t MTLISR;
675   uint32_t      RESERVED34[55];
676   __IO uint32_t MTLTQOMR;
677   __IO uint32_t MTLTQUR;
678   __IO uint32_t MTLTQDR;
679   uint32_t      RESERVED35[8];
680   __IO uint32_t MTLQICSR;
681   __IO uint32_t MTLRQOMR;
682   __IO uint32_t MTLRQMPOCR;
683   __IO uint32_t MTLRQDR;
684   uint32_t      RESERVED36[177];
685   __IO uint32_t DMAMR;
686   __IO uint32_t DMASBMR;
687   __IO uint32_t DMAISR;
688   __IO uint32_t DMADSR;
689   uint32_t      RESERVED37[60];
690   __IO uint32_t DMACCR;
691   __IO uint32_t DMACTCR;
692   __IO uint32_t DMACRCR;
693   uint32_t      RESERVED38[2];
694   __IO uint32_t DMACTDLAR;
695   uint32_t      RESERVED39;
696   __IO uint32_t DMACRDLAR;
697   __IO uint32_t DMACTDTPR;
698   uint32_t      RESERVED40;
699   __IO uint32_t DMACRDTPR;
700   __IO uint32_t DMACTDRLR;
701   __IO uint32_t DMACRDRLR;
702   __IO uint32_t DMACIER;
703   __IO uint32_t DMACRIWTR;
704   __IO uint32_t DMACSFCSR;
705   uint32_t      RESERVED41;
706   __IO uint32_t DMACCATDR;
707   uint32_t      RESERVED42;
708   __IO uint32_t DMACCARDR;
709   uint32_t      RESERVED43;
710   __IO uint32_t DMACCATBR;
711   uint32_t      RESERVED44;
712   __IO uint32_t DMACCARBR;
713   __IO uint32_t DMACSR;
714   uint32_t      RESERVED45[2];
715   __IO uint32_t DMACMFCR;
716 }ETH_TypeDef;
717 
718 /**
719   * @brief Asynch Interrupt/Event Controller (EXTI)
720   */
721 typedef struct
722 {
723   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
724   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
725   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
726   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
727   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
728   __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
729   __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
730        uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
731   __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
732   __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
733   __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
734   __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
735   __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
736   __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
737   __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
738        uint32_t RESERVED2[9];   /*!< Reserved 2,                                                 0x3C-- 0x5C */
739   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
740   __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
741        uint32_t RESERVED3[3];   /*!< Reserved 3,                                                0x74 -- 0x7C */
742   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
743   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
744        uint32_t RESERVED4[2];   /*!< Reserved 4,                                                0x88 -- 0x8C */
745   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
746   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
747 } EXTI_TypeDef;
748 
749 /**
750   * @brief FLASH Registers
751   */
752 typedef struct
753 {
754   __IO uint32_t ACR;             /*!< FLASH access control register,                                     Address offset: 0x00 */
755   __IO uint32_t NSKEYR;          /*!< FLASH non-secure key register,                                     Address offset: 0x04 */
756   __IO uint32_t SECKEYR;         /*!< FLASH secure key register,                                         Address offset: 0x08 */
757   __IO uint32_t OPTKEYR;         /*!< FLASH option key register,                                         Address offset: 0x0C */
758   __IO uint32_t NSOBKKEYR;       /*!< FLASH non-secure option bytes keys key register,                   Address offset: 0x10 */
759   __IO uint32_t SECOBKKEYR;      /*!< FLASH secure option bytes keys key register,                       Address offset: 0x14 */
760   __IO uint32_t OPSR;            /*!< FLASH OPSR register,                                               Address offset: 0x18 */
761   __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                                     Address offset: 0x1C */
762   __IO uint32_t NSSR;            /*!< FLASH non-secure status register,                                  Address offset: 0x20 */
763   __IO uint32_t SECSR;           /*!< FLASH secure status register,                                      Address offset: 0x24 */
764   __IO uint32_t NSCR;            /*!< FLASH non-secure control register,                                 Address offset: 0x28 */
765   __IO uint32_t SECCR;           /*!< FLASH secure control register,                                     Address offset: 0x2C */
766   __IO uint32_t NSCCR;           /*!< FLASH non-secure clear control register,                           Address offset: 0x30 */
767   __IO uint32_t SECCCR;          /*!< FLASH secure clear control register,                               Address offset: 0x34 */
768        uint32_t RESERVED1;       /*!< Reserved1,                                                         Address offset: 0x38 */
769   __IO uint32_t PRIVCFGR;        /*!< FLASH privilege configuration register,                            Address offset: 0x3C */
770   __IO uint32_t NSOBKCFGR;       /*!< FLASH non-secure option byte key configuration register,           Address offset: 0x40 */
771   __IO uint32_t SECOBKCFGR;      /*!< FLASH secure option byte key configuration register,               Address offset: 0x44 */
772   __IO uint32_t HDPEXTR;         /*!< FLASH HDP extension register,                                      Address offset: 0x48 */
773        uint32_t RESERVED2;       /*!< Reserved2,                                                         Address offset: 0x4C */
774   __IO uint32_t OPTSR_CUR;       /*!< FLASH option status current register,                              Address offset: 0x50 */
775   __IO uint32_t OPTSR_PRG;       /*!< FLASH option status to program register,                           Address offset: 0x54 */
776        uint32_t RESERVED3[2];    /*!< Reserved3,                                                         Address offset: 0x58-0x5C */
777   __IO uint32_t NSEPOCHR_CUR;    /*!< FLASH non-secure epoch current register,                           Address offset: 0x60 */
778   __IO uint32_t NSEPOCHR_PRG;    /*!< FLASH non-secure epoch to program register,                        Address offset: 0x64 */
779   __IO uint32_t SECEPOCHR_CUR;   /*!< FLASH secure epoch current register,                               Address offset: 0x68 */
780   __IO uint32_t SECEPOCHR_PRG;   /*!< FLASH secure epoch to program register,                            Address offset: 0x6C */
781   __IO uint32_t OPTSR2_CUR;      /*!< FLASH option status current register 2,                            Address offset: 0x70 */
782   __IO uint32_t OPTSR2_PRG;      /*!< FLASH option status to program register 2,                         Address offset: 0x74 */
783        uint32_t RESERVED4[2];    /*!< Reserved4,                                                         Address offset: 0x78-0x7C */
784   __IO uint32_t NSBOOTR_CUR;     /*!< FLASH non-secure unique boot entry current register,               Address offset: 0x80 */
785   __IO uint32_t NSBOOTR_PRG;     /*!< FLASH non-secure unique boot entry to program register,            Address offset: 0x84 */
786   __IO uint32_t SECBOOTR_CUR;    /*!< FLASH secure unique boot entry current register,                   Address offset: 0x88 */
787   __IO uint32_t SECBOOTR_PRG;    /*!< FLASH secure unique boot entry to program register,                Address offset: 0x8C */
788   __IO uint32_t OTPBLR_CUR;      /*!< FLASH OTP block lock current register,                             Address offset: 0x90 */
789   __IO uint32_t OTPBLR_PRG;      /*!< FLASH OTP block Lock to program register,                          Address offset: 0x94 */
790        uint32_t RESERVED5[2];    /*!< Reserved5,                                                         Address offset: 0x98-0x9C */
791   __IO uint32_t SECBB1R1;        /*!< FLASH secure block-based bank 1 register 1,                        Address offset: 0xA0 */
792   __IO uint32_t SECBB1R2;        /*!< FLASH secure block-based bank 1 register 2,                        Address offset: 0xA4 */
793   __IO uint32_t SECBB1R3;        /*!< FLASH secure block-based bank 1 register 3,                        Address offset: 0xA8 */
794   __IO uint32_t SECBB1R4;        /*!< FLASH secure block-based bank 1 register 4,                        Address offset: 0xAC */
795        uint32_t RESERVED6[4];    /*!< Reserved6,                                                         Address offset: 0xB0-0xBC */
796   __IO uint32_t PRIVBB1R1;       /*!< FLASH privilege block-based bank 1 register 1,                     Address offset: 0xC0 */
797   __IO uint32_t PRIVBB1R2;       /*!< FLASH privilege block-based bank 1 register 2,                     Address offset: 0xC4 */
798   __IO uint32_t PRIVBB1R3;       /*!< FLASH privilege block-based bank 1 register 3,                     Address offset: 0xC8 */
799   __IO uint32_t PRIVBB1R4;       /*!< FLASH privilege block-based bank 1 register 4,                     Address offset: 0xCC */
800        uint32_t RESERVED7[4];    /*!< Reserved7,                                                         Address offset: 0xD0-0xDC */
801   __IO uint32_t SECWM1R_CUR;     /*!< FLASH secure watermark 1 current register,                         Address offset: 0xE0 */
802   __IO uint32_t SECWM1R_PRG;     /*!< FLASH secure watermark 1 to program register,                      Address offset: 0xE4 */
803   __IO uint32_t WRP1R_CUR;       /*!< FLASH write sector group protection current register for bank1,    Address offset: 0xE8 */
804   __IO uint32_t WRP1R_PRG;       /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */
805   __IO uint32_t EDATA1R_CUR;     /*!< FLASH data sectors configuration current register for bank1,       Address offset: 0xF0 */
806   __IO uint32_t EDATA1R_PRG;     /*!< FLASH data sectors configuration to program register for bank1,    Address offset: 0xF4 */
807   __IO uint32_t HDP1R_CUR;       /*!< FLASH HDP configuration current register for bank1,                Address offset: 0xF8 */
808   __IO uint32_t HDP1R_PRG;       /*!< FLASH HDP configuration to program register for bank1,             Address offset: 0xFC */
809   __IO uint32_t ECCCORR;         /*!< FLASH ECC correction register,                                     Address offset: 0x100 */
810   __IO uint32_t ECCDETR;         /*!< FLASH ECC detection register,                                      Address offset: 0x104 */
811   __IO uint32_t ECCDR;           /*!< FLASH ECC data register,                                           Address offset: 0x108 */
812        uint32_t RESERVED8[37];   /*!< Reserved8,                                                         Address offset: 0x10C-0x19C */
813   __IO uint32_t SECBB2R1;        /*!< FLASH secure block-based bank 2 register 1,                        Address offset: 0x1A0 */
814   __IO uint32_t SECBB2R2;        /*!< FLASH secure block-based bank 2 register 2,                        Address offset: 0x1A4 */
815   __IO uint32_t SECBB2R3;        /*!< FLASH secure block-based bank 2 register 3,                        Address offset: 0x1A8 */
816   __IO uint32_t SECBB2R4;        /*!< FLASH secure block-based bank 2 register 4,                        Address offset: 0x1AC */
817        uint32_t RESERVED9[4];    /*!< Reserved9,                                                         Address offset: 0x1B0-0x1BC */
818   __IO uint32_t PRIVBB2R1;       /*!< FLASH privilege block-based bank 2 register 1,                     Address offset: 0x1C0 */
819   __IO uint32_t PRIVBB2R2;       /*!< FLASH privilege block-based bank 2 register 2,                     Address offset: 0x1C4 */
820   __IO uint32_t PRIVBB2R3;       /*!< FLASH privilege block-based bank 2 register 3,                     Address offset: 0x1C8 */
821   __IO uint32_t PRIVBB2R4;       /*!< FLASH privilege block-based bank 2 register 4,                     Address offset: 0x1CC */
822        uint32_t RESERVED10[4];   /*!< Reserved10,                                                        Address offset: 0x1D0-0x1DC */
823   __IO uint32_t SECWM2R_CUR;     /*!< FLASH secure watermark 2 current register,                         Address offset: 0x1E0 */
824   __IO uint32_t SECWM2R_PRG;     /*!< FLASH secure watermark 2 to program register,                      Address offset: 0x1E4 */
825   __IO uint32_t WRP2R_CUR;       /*!< FLASH write sector group protection current register for bank2,    Address offset: 0x1E8 */
826   __IO uint32_t WRP2R_PRG;       /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */
827   __IO uint32_t EDATA2R_CUR;     /*!< FLASH data sectors configuration current register for bank2,       Address offset: 0x1F0 */
828   __IO uint32_t EDATA2R_PRG;     /*!< FLASH data sectors configuration to program register for bank2,    Address offset: 0x1F4 */
829   __IO uint32_t HDP2R_CUR;       /*!< FLASH HDP configuration current register for bank2,                Address offset: 0x1F8 */
830   __IO uint32_t HDP2R_PRG;       /*!< FLASH HDP configuration to program register for bank2,             Address offset: 0x1FC */
831 } FLASH_TypeDef;
832 
833 /**
834   * @brief FMAC
835   */
836 typedef struct
837 {
838   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
839   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
840   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
841   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
842   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
843   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
844   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
845   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
846 } FMAC_TypeDef;
847 /**
848   * @brief General Purpose I/O
849   */
850 typedef struct
851 {
852   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
853   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
854   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
855   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
856   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
857   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
858   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
859   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
860   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
861   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
862   __IO uint32_t HSLVR;       /*!< GPIO high-speed low voltage register,  Address offset: 0x2C      */
863   __IO uint32_t SECCFGR;     /*!< GPIO secure configuration register,    Address offset: 0x30      */
864 } GPIO_TypeDef;
865 
866 /**
867   * @brief Global TrustZone Controller
868   */
869 typedef struct
870 {
871   __IO uint32_t CR;             /*!< TZSC control register,                                                Address offset: 0x00      */
872        uint32_t RESERVED1[3];   /*!< Reserved1,                                                            Address offset: 0x04-0x0C */
873   __IO uint32_t SECCFGR1;       /*!< TZSC secure configuration register 1,                                 Address offset: 0x10      */
874   __IO uint32_t SECCFGR2;       /*!< TZSC secure configuration register 2,                                 Address offset: 0x14      */
875   __IO uint32_t SECCFGR3;       /*!< TZSC secure configuration register 3,                                 Address offset: 0x18      */
876        uint32_t RESERVED2;      /*!< Reserved2,                                                            Address offset: 0x1C      */
877   __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,                              Address offset: 0x20      */
878   __IO uint32_t PRIVCFGR2;      /*!< TZSC privilege configuration register 2,                              Address offset: 0x24      */
879   __IO uint32_t PRIVCFGR3;      /*!< TZSC privilege configuration register 3,                              Address offset: 0x28      */
880        uint32_t RESERVED3[5];   /*!< Reserved3,                                                            Address offset: 0x2C-0x3C */
881   __IO uint32_t MPCWM1ACFGR;    /*!< TZSC memory 1 sub-region A watermark configuration register,          Address offset: 0x40      */
882   __IO uint32_t MPCWM1AR;       /*!< TZSC memory 1 sub-region A watermark register,                        Address offset: 0x44      */
883   __IO uint32_t MPCWM1BCFGR;    /*!< TZSC memory 1 sub-region B watermark configuration register,          Address offset: 0x48      */
884   __IO uint32_t MPCWM1BR;       /*!< TZSC memory 1 sub-region B watermark register,                        Address offset: 0x4C      */
885   __IO uint32_t MPCWM2ACFGR;    /*!< TZSC memory 2 sub-region A watermark configuration register,          Address offset: 0x50      */
886   __IO uint32_t MPCWM2AR;       /*!< TZSC memory 2 sub-region A watermark register,                        Address offset: 0x54      */
887   __IO uint32_t MPCWM2BCFGR;    /*!< TZSC memory 2 sub-region B watermark configuration register,          Address offset: 0x58      */
888   __IO uint32_t MPCWM2BR;       /*!< TZSC memory 2 sub-region B watermark register,                        Address offset: 0x5C      */
889   __IO uint32_t MPCWM3ACFGR;    /*!< TZSC memory 3 sub-region A watermark configuration register,          Address offset: 0x60      */
890   __IO uint32_t MPCWM3AR;       /*!< TZSC memory 3 sub-region A watermark register,                        Address offset: 0x64      */
891        uint32_t RESERVED4[2];   /*!< Reserved4,                                                            Address offset: 0x68-0x6C */
892   __IO uint32_t MPCWM4ACFGR;    /*!< TZSC memory 4 sub-region A watermark configuration register,          Address offset: 0x70      */
893   __IO uint32_t MPCWM4AR;       /*!< TZSC memory 4 sub-region A watermark register,                        Address offset: 0x74      */
894        uint32_t RESERVED5[2];   /*!< Reserved5,                                                            Address offset: 0x78-0x7C */
895 } GTZC_TZSC_TypeDef;
896 
897 typedef struct
898 {
899   __IO uint32_t CR;             /*!< MPCBBx control register,                  Address offset: 0x00        */
900   uint32_t RESERVED1[3];        /*!< Reserved1,                                Address offset: 0x04-0x0C   */
901   __IO uint32_t CFGLOCKR1;      /*!< MPCBBx lock register,                     Address offset: 0x10        */
902   uint32_t RESERVED2[59];       /*!< Reserved2,                                Address offset: 0x14-0xFC   */
903   __IO uint32_t SECCFGR[32];    /*!< MPCBBx security configuration registers,  Address offset: 0x100-0x180 */
904   uint32_t RESERVED3[32];       /*!< Reserved3,                                Address offset: 0x180-0x200 */
905   __IO uint32_t PRIVCFGR[32];   /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
906 } GTZC_MPCBB_TypeDef;
907 
908 typedef struct
909 {
910   __IO uint32_t IER1;           /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
911   __IO uint32_t IER2;           /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
912   __IO uint32_t IER3;           /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
913   __IO uint32_t IER4;           /*!< TZIC interrupt enable register 4, Address offset: 0x0C */
914   __IO uint32_t SR1;            /*!< TZIC status register 1,           Address offset: 0x10 */
915   __IO uint32_t SR2;            /*!< TZIC status register 2,           Address offset: 0x14 */
916   __IO uint32_t SR3;            /*!< TZIC status register 3,           Address offset: 0x18 */
917   __IO uint32_t SR4;            /*!< TZIC status register 4,           Address offset: 0x1C */
918   __IO uint32_t FCR1;           /*!< TZIC flag clear register 1,       Address offset: 0x20 */
919   __IO uint32_t FCR2;           /*!< TZIC flag clear register 2,       Address offset: 0x24 */
920   __IO uint32_t FCR3;           /*!< TZIC flag clear register 3,       Address offset: 0x28 */
921   __IO uint32_t FCR4;           /*!< TZIC flag clear register 3,       Address offset: 0x2C */
922 } GTZC_TZIC_TypeDef;
923 
924 /**
925   * @brief Instruction Cache
926   */
927 typedef struct
928 {
929   __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
930   __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
931   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
932   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,             Address offset: 0x0C */
933   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
934   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
935        uint32_t RESERVED1[2];   /*!< Reserved,                               Address offset: 0x018-0x01C */
936   __IO uint32_t CRR0;           /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
937   __IO uint32_t CRR1;           /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
938   __IO uint32_t CRR2;           /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
939   __IO uint32_t CRR3;           /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
940 } ICACHE_TypeDef;
941 
942 /**
943   * @brief Data Cache
944   */
945 typedef struct
946 {
947   __IO uint32_t CR;             /*!< DCACHE control register,               Address offset: 0x00 */
948   __IO uint32_t SR;             /*!< DCACHE status register,                Address offset: 0x04 */
949   __IO uint32_t IER;            /*!< DCACHE interrupt enable register,      Address offset: 0x08 */
950   __IO uint32_t FCR;            /*!< DCACHE Flag clear register,            Address offset: 0x0C */
951   __IO uint32_t RHMONR;         /*!< DCACHE Read hit monitor register,      Address offset: 0x10 */
952   __IO uint32_t RMMONR;         /*!< DCACHE Read miss monitor register,     Address offset: 0x14 */
953        uint32_t RESERVED1[2];   /*!< Reserved,                              Address offset: 0x18-0x1C */
954   __IO uint32_t WHMONR;         /*!< DCACHE Write hit monitor register,     Address offset: 0x20 */
955   __IO uint32_t WMMONR;         /*!< DCACHE Write miss monitor register,    Address offset: 0x24 */
956   __IO uint32_t CMDRSADDRR;     /*!< DCACHE Command Start Address register, Address offset: 0x28 */
957   __IO uint32_t CMDREADDRR;     /*!< DCACHE Command End Address register,   Address offset: 0x2C */
958 } DCACHE_TypeDef;
959 
960 /**
961   * @brief TIM
962   */
963 typedef struct
964 {
965   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
966   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
967   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
968   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
969   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
970   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
971   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
972   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
973   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
974   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
975   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
976   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
977   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
978   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
979   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
980   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
981   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
982   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
983   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
984   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
985   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
986   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
987   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
988   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
989   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
990   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
991        uint32_t RESERVED0[221];/*!< Reserved,                               Address offset: 0x68 */
992   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
993   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
994 } TIM_TypeDef;
995 
996 /**
997   * @brief LPTIMER
998   */
999 typedef struct
1000 {
1001   __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
1002   __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
1003   __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
1004   __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
1005   __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
1006   __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
1007   __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
1008   __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
1009   __IO uint32_t RESERVED0;      /*!< Reserved,                               Address offset: 0x20 */
1010   __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
1011   __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
1012   __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
1013   __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x30 */
1014   __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
1015 } LPTIM_TypeDef;
1016 
1017 /**
1018   * @brief OCTO Serial Peripheral Interface
1019   */
1020 
1021 typedef struct
1022 {
1023   __IO uint32_t CR;          /*!< OCTOSPI Control register,                            Address offset: 0x000 */
1024   uint32_t RESERVED;         /*!< Reserved,                                            Address offset: 0x004 */
1025   __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,             Address offset: 0x008 */
1026   __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,             Address offset: 0x00C */
1027   __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,             Address offset: 0x010 */
1028   __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,             Address offset: 0x014 */
1029   uint32_t RESERVED1[2];     /*!< Reserved,                                            Address offset: 0x018-0x01C */
1030   __IO uint32_t SR;          /*!< OCTOSPI Status register,                             Address offset: 0x020 */
1031   __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                         Address offset: 0x024 */
1032   uint32_t RESERVED2[6];     /*!< Reserved,                                            Address offset: 0x028-0x03C */
1033   __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                        Address offset: 0x040 */
1034   uint32_t RESERVED3;        /*!< Reserved,                                            Address offset: 0x044 */
1035   __IO uint32_t AR;          /*!< OCTOSPI Address register,                            Address offset: 0x048 */
1036   uint32_t RESERVED4;        /*!< Reserved,                                            Address offset: 0x04C */
1037   __IO uint32_t DR;          /*!< OCTOSPI Data register,                               Address offset: 0x050 */
1038   uint32_t RESERVED5[11];    /*!< Reserved,                                            Address offset: 0x054-0x07C */
1039   __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,                Address offset: 0x080 */
1040   uint32_t RESERVED6;        /*!< Reserved,                                            Address offset: 0x084 */
1041   __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,               Address offset: 0x088 */
1042   uint32_t RESERVED7;        /*!< Reserved,                                            Address offset: 0x08C */
1043   __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                   Address offset: 0x090 */
1044   uint32_t RESERVED8[27];    /*!< Reserved,                                            Address offset: 0x094-0x0FC */
1045   __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,        Address offset: 0x100 */
1046   uint32_t RESERVED9;        /*!< Reserved,                                            Address offset: 0x104 */
1047   __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,               Address offset: 0x108 */
1048   uint32_t RESERVED10;       /*!< Reserved,                                            Address offset: 0x10C */
1049   __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                        Address offset: 0x110 */
1050   uint32_t RESERVED11[3];    /*!< Reserved,                                            Address offset: 0x114-0x11C */
1051   __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                    Address offset: 0x120 */
1052   uint32_t RESERVED12[3];    /*!< Reserved,                                            Address offset: 0x124-0x12C */
1053   __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                  Address offset: 0x130 */
1054   uint32_t RESERVED13[3];    /*!< Reserved,                                            Address offset: 0x134-0x13C */
1055   __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,   Address offset: 0x140 */
1056   uint32_t RESERVED14;       /*!< Reserved,                                            Address offset: 0x144 */
1057   __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,          Address offset: 0x148 */
1058   uint32_t RESERVED15;       /*!< Reserved,                                            Address offset: 0x14C */
1059   __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                   Address offset: 0x150 */
1060   uint32_t RESERVED16[3];    /*!< Reserved,                                            Address offset: 0x154-0x15C */
1061   __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,               Address offset: 0x160 */
1062   uint32_t RESERVED17[7];    /*!< Reserved,                                            Address offset: 0x164-0x17C */
1063   __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register,  Address offset: 0x180 */
1064   uint32_t RESERVED18;       /*!< Reserved,                                            Address offset: 0x184 */
1065   __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,         Address offset: 0x188 */
1066   uint32_t RESERVED19;       /*!< Reserved,                                            Address offset: 0x18C */
1067   __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                  Address offset: 0x190 */
1068   uint32_t RESERVED20[3];    /*!< Reserved,                                            Address offset: 0x194-0x19C */
1069   __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,              Address offset: 0x1A0 */
1070   uint32_t RESERVED21[23];   /*!< Reserved,                                            Address offset: 0x1A4-0x1FC */
1071   __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,     Address offset: 0x200 */
1072 } XSPI_TypeDef;
1073 
1074 typedef  XSPI_TypeDef OCTOSPI_TypeDef;
1075 /**
1076   * @brief OTFDEC register
1077   */
1078 typedef struct
1079 {
1080   __IO uint32_t REG_CONFIGR;      /*!< OTFDEC Region Configuration register,          Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
1081   __IO uint32_t REG_START_ADDR;   /*!< OTFDEC Region Start Address register,          Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
1082   __IO uint32_t REG_END_ADDR;     /*!< OTFDEC Region End Address register,            Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
1083   __IO uint32_t REG_NONCER0;      /*!< OTFDEC Region Nonce register 0,                Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
1084   __IO uint32_t REG_NONCER1;      /*!< OTFDEC Region Nonce register 1,                Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
1085   __IO uint32_t REG_KEYR0;        /*!< OTFDEC Region Key register 0,                  Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
1086   __IO uint32_t REG_KEYR1;        /*!< OTFDEC Region Key register 1,                  Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
1087   __IO uint32_t REG_KEYR2;        /*!< OTFDEC Region Key register 2,                  Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
1088   __IO uint32_t REG_KEYR3;        /*!< OTFDEC Region Key register 3,                  Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
1089 } OTFDEC_Region_TypeDef;
1090 
1091 typedef struct
1092 {
1093   __IO uint32_t CR;               /*!< OTFDEC Control register,                                 Address offset: 0x000 */
1094   uint32_t RESERVED1[3];          /*!< Reserved,                                                Address offset: 0x004-0x00C */
1095   __IO uint32_t PRIVCFGR;         /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */
1096   uint32_t RESERVED2[187];        /*!< Reserved,                                                Address offset: 0x014-0x2FC */
1097   __IO uint32_t ISR;              /*!< OTFDEC Interrupt Status register,                        Address offset: 0x300 */
1098   __IO uint32_t ICR;              /*!< OTFDEC Interrupt Clear register,                         Address offset: 0x304 */
1099   __IO uint32_t IER;              /*!< OTFDEC Interrupt Enable register,                        Address offset: 0x308 */
1100 } OTFDEC_TypeDef;
1101 
1102 
1103 /**
1104   * @brief Power Control
1105   */
1106 typedef struct
1107 {
1108   __IO uint32_t PMCR;         /*!< Power mode control register ,          Address offset: 0x00      */
1109   __IO uint32_t PMSR;         /*!< Power mode status register ,           Address offset: 0x04      */
1110        uint32_t RESERVED1[2]; /*!< Reserved,                              Address offset: 0x08-0x0C */
1111   __IO uint32_t VOSCR;        /*!< Voltage scaling control register ,     Address offset: 0x10      */
1112   __IO uint32_t VOSSR;        /*!< Voltage sacling status register ,      Address offset: 0x14      */
1113        uint32_t RESERVED2[2]; /*!< Reserved,                              Address offset: 0x18-0x1C */
1114   __IO uint32_t BDCR;         /*!< BacKup domain control register ,       Address offset: 0x20      */
1115   __IO uint32_t DBPCR;        /*!< DBP control register,                  Address offset: 0x24      */
1116   __IO uint32_t BDSR;         /*!< BacKup domain status register,         Address offset: 0x28      */
1117   __IO uint32_t UCPDR;        /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C      */
1118   __IO uint32_t SCCR;         /*!< Supply configuration control register, Address offset: 0x30      */
1119   __IO uint32_t VMCR;         /*!< Voltage Monitor Control Register,      Address offset: 0x34      */
1120   __IO uint32_t USBSCR;       /*!< USB Supply Control Register            Address offset: 0x38      */
1121   __IO uint32_t VMSR;         /*!< Status Register Voltage Monitoring,    Address offset: 0x3C      */
1122   __IO uint32_t WUSCR;        /*!< WakeUP status clear register,          Address offset: 0x40      */
1123   __IO uint32_t WUSR;         /*!< WakeUP status Register,                Address offset: 0x44      */
1124   __IO uint32_t WUCR;         /*!< WakeUP configuration register,         Address offset: 0x48      */
1125        uint32_t RESERVED3;    /*!< Reserved,                              Address offset: 0x4C      */
1126   __IO uint32_t IORETR;       /*!< IO RETention Register,                 Address offset: 0x50      */
1127        uint32_t RESERVED4[43];/*!< Reserved,                              Address offset: 0x54-0xFC */
1128   __IO uint32_t SECCFGR;      /*!< Security configuration register,       Address offset: 0x100     */
1129   __IO uint32_t PRIVCFGR;     /*!< Privilege configuration register,     Address offset: 0x104      */
1130 }PWR_TypeDef;
1131 
1132 /**
1133   * @brief SRAMs configuration controller
1134   */
1135 typedef struct
1136 {
1137   __IO uint32_t CR;       /*!< Control Register,                  Address offset: 0x00 */
1138   __IO uint32_t IER;      /*!< Interrupt Enable Register,         Address offset: 0x04 */
1139   __IO uint32_t ISR;      /*!< Interrupt Status Register,         Address offset: 0x08 */
1140   __IO uint32_t SEAR;     /*!< ECC Single Error Address Register, Address offset: 0x0C */
1141   __IO uint32_t DEAR;     /*!< ECC Double Error Address Register, Address offset: 0x10 */
1142   __IO uint32_t ICR;      /*!< Interrupt Clear Register,          Address offset: 0x14 */
1143   __IO uint32_t WPR1;     /*!< SRAM Write Protection Register 1,  Address offset: 0x18 */
1144   __IO uint32_t WPR2;     /*!< SRAM Write Protection Register 2,  Address offset: 0x1C */
1145   uint32_t      RESERVED; /*!< Reserved,                          Address offset: 0x20 */
1146   __IO uint32_t ECCKEY;   /*!< SRAM ECC Key Register,             Address offset: 0x24 */
1147   __IO uint32_t ERKEYR;   /*!< SRAM Erase Key Register,           Address offset: 0x28 */
1148 }RAMCFG_TypeDef;
1149 
1150 /**
1151   * @brief Reset and Clock Control
1152   */
1153 typedef struct
1154 {
1155   __IO uint32_t CR;            /*!< RCC clock control register                                               Address offset: 0x00 */
1156   uint32_t      RESERVED1[3];  /*!< Reserved,                                                                Address offset: 0x04 */
1157   __IO uint32_t HSICFGR;       /*!< RCC HSI Clock Calibration Register,                                      Address offset: 0x10 */
1158   __IO uint32_t CRRCR;         /*!< RCC Clock Recovery RC Register,                                          Address offset: 0x14 */
1159   __IO uint32_t CSICFGR;       /*!< RCC CSI Clock Calibration Register,                                      Address offset: 0x18 */
1160   __IO uint32_t CFGR1;         /*!< RCC clock configuration register 1                                       Address offset: 0x1C */
1161   __IO uint32_t CFGR2;         /*!< RCC clock configuration register 2                                       Address offset: 0x20 */
1162   uint32_t      RESERVED2;     /*!< Reserved,                                                                Address offset: 0x24 */
1163   __IO uint32_t PLL1CFGR;      /*!< RCC PLL1 Configuration Register                                          Address offset: 0x28 */
1164   __IO uint32_t PLL2CFGR;      /*!< RCC PLL2 Configuration Register                                          Address offset: 0x2C */
1165   __IO uint32_t PLL3CFGR;      /*!< RCC PLL3 Configuration Register                                          Address offset: 0x30 */
1166   __IO uint32_t PLL1DIVR;      /*!< RCC PLL1 Dividers Configuration Register                                 Address offset: 0x34 */
1167   __IO uint32_t PLL1FRACR;     /*!< RCC PLL1 Fractional Divider Configuration Register                       Address offset: 0x38 */
1168   __IO uint32_t PLL2DIVR;      /*!< RCC PLL2 Dividers Configuration Register                                 Address offset: 0x3C */
1169   __IO uint32_t PLL2FRACR;     /*!< RCC PLL2 Fractional Divider Configuration Register                       Address offset: 0x40 */
1170   __IO uint32_t PLL3DIVR;      /*!< RCC PLL3 Dividers Configuration Register                                 Address offset: 0x44 */
1171   __IO uint32_t PLL3FRACR;     /*!< RCC PLL3 Fractional Divider Configuration Register                       Address offset: 0x48 */
1172   uint32_t      RESERVED5;     /*!< Reserved                                                                 Address offset: 0x4C */
1173   __IO uint32_t CIER;          /*!< RCC Clock Interrupt Enable Register                                      Address offset: 0x50 */
1174   __IO uint32_t CIFR;          /*!< RCC Clock Interrupt Flag Register                                        Address offset: 0x54 */
1175   __IO uint32_t CICR;          /*!< RCC Clock Interrupt Clear Register                                       Address offset: 0x58 */
1176   uint32_t      RESERVED6;     /*!< Reserved                                                                 Address offset: 0x5C */
1177   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 Peripherals Reset Register                                      Address offset: 0x60 */
1178   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 Peripherals Reset Register                                      Address offset: 0x64 */
1179   uint32_t      RESERVED7;     /*!< Reserved                                                                 Address offset: 0x68 */
1180   __IO uint32_t AHB4RSTR;      /*!< RCC AHB4 Peripherals Reset Register                                      Address offset: 0x6C */
1181   uint32_t      RESERVED9;     /*!< Reserved                                                                 Address offset: 0x70 */
1182   __IO uint32_t APB1LRSTR;     /*!< RCC APB1 Peripherals reset Low Word register                             Address offset: 0x74 */
1183   __IO uint32_t APB1HRSTR;     /*!< RCC APB1 Peripherals reset High Word register                            Address offset: 0x78 */
1184   __IO uint32_t APB2RSTR;      /*!< RCC APB2 Peripherals Reset Register                                      Address offset: 0x7C */
1185   __IO uint32_t APB3RSTR;      /*!< RCC APB3 Peripherals Reset Register                                      Address offset: 0x80 */
1186   uint32_t      RESERVED10;    /*!< Reserved                                                                 Address offset: 0x84 */
1187   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 Peripherals Clock Enable Register                               Address offset: 0x88 */
1188   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 Peripherals Clock Enable Register                               Address offset: 0x8C */
1189   uint32_t      RESERVED11;    /*!< Reserved                                                                 Address offset: 0x90 */
1190   __IO uint32_t AHB4ENR;       /*!< RCC AHB4 Peripherals Clock Enable Register                               Address offset: 0x94 */
1191   uint32_t      RESERVED13;    /*!< Reserved                                                                 Address offset: 0x98 */
1192   __IO uint32_t APB1LENR;      /*!< RCC APB1 Peripherals clock Enable Low Word register                      Address offset: 0x9C */
1193   __IO uint32_t APB1HENR;      /*!< RCC APB1 Peripherals clock Enable High Word register                     Address offset: 0xA0 */
1194   __IO uint32_t APB2ENR;       /*!< RCC APB2 Peripherals Clock Enable Register                               Address offset: 0xA4 */
1195   __IO uint32_t APB3ENR;       /*!< RCC APB3 Peripherals Clock Enable Register                               Address offset: 0xA8 */
1196   uint32_t      RESERVED14;    /*!< Reserved                                                                 Address offset: 0xAC */
1197   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 Peripheral sleep clock Register                                 Address offset: 0xB0 */
1198   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 Peripheral sleep clock Register                                 Address offset: 0xB4 */
1199   uint32_t      RESERVED15;    /*!< Reserved                                                                 Address offset: 0xB8 */
1200   __IO uint32_t AHB4LPENR;     /*!< RCC AHB4 Peripherals sleep clock Register                                Address offset: 0xBC */
1201   uint32_t      RESERVED17;    /*!< Reserved                                                                 Address offset: 0xC0 */
1202   __IO uint32_t APB1LLPENR;    /*!< RCC APB1 Peripherals sleep clock Low Word Register                       Address offset: 0xC4 */
1203   __IO uint32_t APB1HLPENR;    /*!< RCC APB1 Peripherals sleep clock High Word Register                      Address offset: 0xC8 */
1204   __IO uint32_t APB2LPENR;     /*!< RCC APB2 Peripherals sleep clock Register                                Address offset: 0xCC */
1205   __IO uint32_t APB3LPENR;     /*!< RCC APB3 Peripherals Clock Low Power Enable Register                     Address offset: 0xD0 */
1206   uint32_t      RESERVED18;    /*!< Reserved                                                                 Address offset: 0xD4 */
1207   __IO uint32_t CCIPR1;        /*!< RCC IPs Clocks Configuration Register 1                                  Address offset: 0xD8 */
1208   __IO uint32_t CCIPR2;        /*!< RCC IPs Clocks Configuration Register 2                                  Address offset: 0xDC */
1209   __IO uint32_t CCIPR3;        /*!< RCC IPs Clocks Configuration Register 3                                  Address offset: 0xE0 */
1210   __IO uint32_t CCIPR4;        /*!< RCC IPs Clocks Configuration Register 4                                  Address offset: 0xE4 */
1211   __IO uint32_t CCIPR5;        /*!< RCC IPs Clocks Configuration Register 5                                  Address offset: 0xE8 */
1212   uint32_t      RESERVED19;    /*!< Reserved,                                                                Address offset: 0xEC */
1213   __IO uint32_t BDCR;          /*!< RCC VSW Backup Domain & V33 Domain Control Register                      Address offset: 0xF0 */
1214   __IO uint32_t RSR;           /*!< RCC Reset status Register                                                Address offset: 0xF4 */
1215   uint32_t      RESERVED20[6]; /*!< Reserved                                                                 Address offset: 0xF8 */
1216   __IO uint32_t SECCFGR;       /*!< RCC Secure mode configuration register                                   Address offset: 0x110 */
1217   __IO uint32_t PRIVCFGR;      /*!< RCC Privilege configuration register                                     Address offset: 0x114 */
1218 } RCC_TypeDef;
1219 
1220 /**
1221   * @brief PKA
1222   */
1223 typedef struct
1224 {
1225   __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
1226   __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
1227   __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
1228   uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
1229   __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
1230 } PKA_TypeDef;
1231 
1232 /*
1233 * @brief RTC Specific device feature definitions
1234 */
1235 #define RTC_BKP_NB         32U
1236 #define RTC_TAMP_NB        8U
1237 
1238 /**
1239   * @brief Real-Time Clock
1240   */
1241 typedef struct
1242 {
1243   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
1244   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
1245   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
1246   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
1247   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
1248   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
1249   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
1250   __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
1251   __IO uint32_t SECCFGR;     /*!< RTC secure mode control register,               Address offset: 0x20 */
1252   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
1253   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
1254   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
1255   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
1256   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
1257   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
1258        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x3C */
1259   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
1260   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
1261   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
1262   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
1263   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
1264   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
1265   __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
1266   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
1267   __IO uint32_t OR;          /*!< RTC option register,                            Address offset: 0x60 */
1268        uint32_t RESERVED1[3];/*!< Reserved,                                       Address offset: 0x64 */
1269   __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
1270   __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
1271 } RTC_TypeDef;
1272 
1273 /**
1274   * @brief Tamper and backup registers
1275   */
1276 typedef struct
1277 {
1278   __IO uint32_t CR1;         /*!< TAMP control register 1,                  Address offset: 0x00 */
1279   __IO uint32_t CR2;         /*!< TAMP control register 2,                  Address offset: 0x04 */
1280   __IO uint32_t CR3;         /*!< TAMP control register 3,                  Address offset: 0x08 */
1281   __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
1282   __IO uint32_t ATCR1;       /*!< TAMP filter control register 1            Address offset: 0x10 */
1283   __IO uint32_t ATSEEDR;     /*!< TAMP active tamper seed register,         Address offset: 0x14 */
1284   __IO uint32_t ATOR;        /*!< TAMP active tamper output register,       Address offset: 0x18 */
1285   __IO uint32_t ATCR2;       /*!< TAMP filter control register 2,           Address offset: 0x1C */
1286   __IO uint32_t SECCFGR;     /*!< TAMP secure mode control register,        Address offset: 0x20 */
1287   __IO uint32_t PRIVCFGR;    /*!< TAMP privilege mode control register,     Address offset: 0x24 */
1288        uint32_t RESERVED0;   /*!< Reserved,                                 Address offset: 0x28 */
1289   __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
1290   __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
1291   __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
1292   __IO uint32_t SMISR;       /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
1293   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
1294   __IO uint32_t COUNT1R;     /*!< TAMP monotonic counter register,          Address offset: 0x40 */
1295        uint32_t RESERVED1[3];/*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
1296   __IO uint32_t OR;          /*!< TAMP option register,                     Address offset: 0x50 */
1297   __IO uint32_t ERCFGR;      /*!< TAMP erase configuration register,        Address offset: 0x54 */
1298        uint32_t RESERVED2[42];/*!< Reserved,                                Address offset: 0x58 -- 0xFC */
1299   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
1300   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
1301   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
1302   __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
1303   __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
1304   __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
1305   __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
1306   __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
1307   __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
1308   __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
1309   __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
1310   __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
1311   __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
1312   __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
1313   __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
1314   __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
1315   __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
1316   __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
1317   __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
1318   __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
1319   __IO uint32_t BKP20R;      /*!< TAMP backup register 20,                  Address offset: 0x150 */
1320   __IO uint32_t BKP21R;      /*!< TAMP backup register 21,                  Address offset: 0x154 */
1321   __IO uint32_t BKP22R;      /*!< TAMP backup register 22,                  Address offset: 0x158 */
1322   __IO uint32_t BKP23R;      /*!< TAMP backup register 23,                  Address offset: 0x15C */
1323   __IO uint32_t BKP24R;      /*!< TAMP backup register 24,                  Address offset: 0x160 */
1324   __IO uint32_t BKP25R;      /*!< TAMP backup register 25,                  Address offset: 0x164 */
1325   __IO uint32_t BKP26R;      /*!< TAMP backup register 26,                  Address offset: 0x168 */
1326   __IO uint32_t BKP27R;      /*!< TAMP backup register 27,                  Address offset: 0x16C */
1327   __IO uint32_t BKP28R;      /*!< TAMP backup register 28,                  Address offset: 0x170 */
1328   __IO uint32_t BKP29R;      /*!< TAMP backup register 29,                  Address offset: 0x174 */
1329   __IO uint32_t BKP30R;      /*!< TAMP backup register 30,                  Address offset: 0x178 */
1330   __IO uint32_t BKP31R;      /*!< TAMP backup register 31,                  Address offset: 0x17C */
1331 } TAMP_TypeDef;
1332 
1333 /**
1334   * @brief Universal Synchronous Asynchronous Receiver Transmitter
1335   */
1336 typedef struct
1337 {
1338   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
1339   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
1340   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
1341   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
1342   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
1343   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
1344   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
1345   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
1346   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
1347   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
1348   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
1349   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
1350 } USART_TypeDef;
1351 
1352 /**
1353   * @brief Serial Audio Interface
1354   */
1355 typedef struct
1356 {
1357   __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
1358   uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
1359   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
1360   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
1361 } SAI_TypeDef;
1362 
1363 typedef struct
1364 {
1365   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
1366   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
1367   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
1368   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
1369   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
1370   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
1371   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
1372   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
1373 } SAI_Block_TypeDef;
1374 /**
1375   * @brief System configuration, Boot and Security
1376   */
1377 typedef struct
1378 {
1379        uint32_t RESERVED1[4];   /*!< RESERVED1,                                       Address offset: 0x00 - 0x0C */
1380   __IO uint32_t HDPLCR;         /*!< SBS HDPL Control Register,                       Address offset: 0x10 */
1381   __IO uint32_t HDPLSR;         /*!< SBS HDPL Status Register,                        Address offset: 0x14 */
1382   __IO uint32_t NEXTHDPLCR;     /*!< NEXT HDPL Control Register,                      Address offset: 0x18 */
1383   __IO uint32_t RESERVED2;      /*!< RESERVED2,                                       Address offset: 0x1C */
1384   __IO uint32_t DBGCR;          /*!< SBS Debug Control Register,                      Address offset: 0x20 */
1385   __IO uint32_t DBGLOCKR;       /*!< SBS Debug Lock Register,                         Address offset: 0x24 */
1386        uint32_t RESERVED3[3];   /*!< RESERVED3,                                       Address offset: 0x28 - 0x30 */
1387   __IO uint32_t RSSCMDR;        /*!< SBS RSS Command Register,                        Address offset: 0x34 */
1388        uint32_t RESERVED4[26];  /*!< RESERVED4,                                       Address offset: 0x38 - 0x9C */
1389   __IO uint32_t EPOCHSELCR;     /*!< EPOCH Selection Register,                        Address offset: 0xA0 */
1390        uint32_t RESERVED5[7];   /*!< RESERVED5,                                       Address offset: 0xA4 - 0xBC */
1391   __IO uint32_t SECCFGR;        /*!< SBS Security Mode Configuration,                 Address offset: 0xC0 */
1392        uint32_t RESERVED6[15];  /*!< RESERVED6,                                       Address offset: 0xC4 - 0xFC */
1393   __IO uint32_t PMCR;           /*!< SBS Product Mode & Config Register,              Address offset: 0x100 */
1394   __IO uint32_t FPUIMR;         /*!< SBS FPU Interrupt Mask Register,                 Address offset: 0x104 */
1395   __IO uint32_t MESR;           /*!< SBS Memory Erase Status Register,                Address offset: 0x108 */
1396        uint32_t RESERVED7;      /*!< RESERVED7,                                       Address offset: 0x10C */
1397   __IO uint32_t CCCSR;          /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */
1398   __IO uint32_t CCVALR;         /*!< SBS Compensation Cell Value Register,            Address offset: 0x114 */
1399   __IO uint32_t CCSWCR;         /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */
1400   __IO uint32_t RESERVED8;      /*!< RESERVED8,                                       Address offset: 0x11C */
1401   __IO uint32_t CFGR2;          /*!< SBS Class B Register,                            Address offset: 0x120 */
1402        uint32_t RESERVED9[8];   /*!< RESERVED9,                                       Address offset: 0x124 - 0x140 */
1403   __IO uint32_t CNSLCKR;        /*!< SBS CPU Non-secure Lock Register,                Address offset: 0x144 */
1404   __IO uint32_t CSLCKR;         /*!< SBS CPU Secure Lock Register,                    Address offset: 0x148 */
1405   __IO uint32_t ECCNMIR;        /*!< SBS FLITF ECC NMI MASK Register,                 Address offset: 0x14C */
1406 } SBS_TypeDef;
1407 
1408 /**
1409   * @brief Secure digital input/output Interface
1410   */
1411 typedef struct
1412 {
1413   __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
1414   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
1415   __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
1416   __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
1417   __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
1418   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
1419   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
1420   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
1421   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
1422   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
1423   __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
1424   __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
1425   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
1426   __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
1427   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
1428   __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
1429   __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
1430   uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
1431   __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
1432   __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
1433   __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,   Address offset: 0x58  */
1434   uint32_t      RESERVED1[2];   /*!< Reserved, 0x60                                             */
1435   __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,   Address offset: 0x64  */
1436   __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
1437   uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
1438   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
1439 } SDMMC_TypeDef;
1440 
1441 
1442 
1443 /**
1444   * @brief Delay Block DLYB
1445   */
1446 
1447 typedef struct
1448 {
1449   __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
1450   __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
1451 } DLYB_TypeDef;
1452 
1453 /**
1454   * @brief UCPD
1455   */
1456 typedef struct
1457 {
1458   __IO uint32_t CFG1;         /*!< UCPD configuration register 1,             Address offset: 0x00 */
1459   __IO uint32_t CFG2;         /*!< UCPD configuration register 2,             Address offset: 0x04 */
1460   __IO uint32_t CFG3;         /*!< UCPD configuration register 3,             Address offset: 0x08 */
1461   __IO uint32_t CR;           /*!< UCPD control register,                     Address offset: 0x0C */
1462   __IO uint32_t IMR;          /*!< UCPD interrupt mask register,              Address offset: 0x10 */
1463   __IO uint32_t SR;           /*!< UCPD status register,                      Address offset: 0x14 */
1464   __IO uint32_t ICR;          /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
1465   __IO uint32_t TX_ORDSET;    /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
1466   __IO uint32_t TX_PAYSZ;     /*!< UCPD Tx payload size register,             Address offset: 0x20 */
1467   __IO uint32_t TXDR;         /*!< UCPD Tx data register,                     Address offset: 0x24 */
1468   __IO uint32_t RX_ORDSET;    /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
1469   __IO uint32_t RX_PAYSZ;     /*!< UCPD Rx payload size register,             Address offset: 0x2C */
1470   __IO uint32_t RXDR;         /*!< UCPD Rx data register,                     Address offset: 0x30 */
1471   __IO uint32_t RX_ORDEXT1;   /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
1472   __IO uint32_t RX_ORDEXT2;   /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
1473        uint32_t RESERVED[949];/*!< Reserved,                                  Address offset: 0x3C -- 0x3F0 */
1474   __IO uint32_t IPVER;        /*!< UCPD IP version register,                  Address offset: 0x3F4 */
1475   __IO uint32_t IPID;         /*!< UCPD IP Identification register,           Address offset: 0x3F8 */
1476   __IO uint32_t MID;          /*!< UCPD Magic Identification register,        Address offset: 0x3FC */
1477 } UCPD_TypeDef;
1478 
1479 /**
1480   * @brief Universal Serial Bus Full Speed Dual Role Device
1481   */
1482 typedef struct
1483 {
1484   __IO uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
1485   __IO uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
1486   __IO uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
1487   __IO uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
1488   __IO uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
1489   __IO uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
1490   __IO uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
1491   __IO uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
1492   __IO uint32_t RESERVED0[8];    /*!< Reserved,                                                  */
1493   __IO uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
1494   __IO uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
1495   __IO uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
1496   __IO uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
1497   __IO uint32_t RESERVED1;       /*!< Reserved */
1498   __IO uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
1499   __IO uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
1500 } USB_DRD_TypeDef;
1501 
1502 /**
1503   * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
1504   */
1505 typedef struct
1506 {
1507   __IO uint32_t TXBD;             /*!<Transmission buffer address*/
1508   __IO uint32_t RXBD;             /*!<Reception buffer address */
1509 } USB_DRD_PMABuffDescTypeDef;
1510 
1511 /**
1512   * @brief FD Controller Area Network
1513   */
1514 typedef struct
1515 {
1516   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
1517   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
1518        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
1519   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
1520   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
1521   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
1522   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
1523   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
1524   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
1525   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
1526   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
1527   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
1528        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
1529   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
1530   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
1531   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
1532        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
1533   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
1534   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
1535   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
1536   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
1537        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
1538   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
1539   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
1540   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
1541        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
1542   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
1543   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
1544   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
1545   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
1546        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
1547   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
1548   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
1549   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
1550   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
1551   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
1552   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
1553   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
1554   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
1555   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
1556   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
1557   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
1558 } FDCAN_GlobalTypeDef;
1559 
1560 /**
1561   * @brief FD Controller Area Network Configuration
1562   */
1563 typedef struct
1564 {
1565   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
1566        uint32_t RESERVED1[128];/*!< Reserved,                                               0x100 + 0x004 - 0x100 + 0x200 */
1567   __IO uint32_t OPTR;         /*!< FDCAN option register,                                   Address offset: 0x100 + 0x204 */
1568        uint32_t RESERVED2[58];/*!< Reserved,                                                0x100 + 0x208 - 0x100 + 0x2EC */
1569   __IO uint32_t HWCFG;        /*!< FDCAN hardware configuration register,                   Address offset: 0x100 + 0x2F0 */
1570   __IO uint32_t VERR;         /*!< FDCAN IP version register,                               Address offset: 0x100 + 0x2F4 */
1571   __IO uint32_t IPIDR;        /*!< FDCAN IP ID register,                                    Address offset: 0x100 + 0x2F8 */
1572   __IO uint32_t SIDR;         /*!< FDCAN size ID register,                                  Address offset: 0x100 + 0x2FC */
1573 } FDCAN_Config_TypeDef;
1574 
1575 /**
1576   * @brief Consumer Electronics Control
1577   */
1578 typedef struct
1579 {
1580   __IO uint32_t CR;           /*!< CEC control register,                                              Address offset:0x00 */
1581   __IO uint32_t CFGR;         /*!< CEC configuration register,                                        Address offset:0x04 */
1582   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                             Address offset:0x08 */
1583   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                              Address offset:0x0C */
1584   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                                 Address offset:0x10 */
1585   __IO uint32_t IER;          /*!< CEC interrupt enable register,                                     Address offset:0x14 */
1586 }CEC_TypeDef;
1587 
1588 /**
1589   * @brief Flexible Memory Controller
1590   */
1591 typedef struct
1592 {
1593   __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1594   __IO uint32_t PCSCNTR;     /*!< PSRAM chip-select counter register,                                               Address offset:    0x20 */
1595 } FMC_Bank1_TypeDef;
1596 
1597 /**
1598   * @brief Flexible Memory Controller Bank1E
1599   */
1600 typedef struct
1601 {
1602   __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1603 } FMC_Bank1E_TypeDef;
1604 
1605 /**
1606   * @brief Flexible Memory Controller Bank3
1607   */
1608 typedef struct
1609 {
1610   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
1611   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
1612   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
1613   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
1614   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
1615   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
1616 } FMC_Bank3_TypeDef;
1617 
1618 /**
1619   * @brief Flexible Memory Controller Bank5 and 6
1620   */
1621 typedef struct
1622 {
1623   __IO uint32_t SDCR[2];     /*!< SDRAM Control registers ,       Address offset: 0x140-0x144  */
1624   __IO uint32_t SDTR[2];     /*!< SDRAM Timing registers ,        Address offset: 0x148-0x14C  */
1625   __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150        */
1626   __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154        */
1627   __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158        */
1628 } FMC_Bank5_6_TypeDef;
1629 
1630 /**
1631   * @brief VREFBUF
1632   */
1633 typedef struct
1634 {
1635   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
1636   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
1637 } VREFBUF_TypeDef;
1638 
1639 /**
1640   * @brief ADC
1641   */
1642 typedef struct
1643 {
1644   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
1645   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
1646   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
1647   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
1648   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
1649   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
1650   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
1651        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
1652   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
1653   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
1654   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
1655        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
1656   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
1657   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
1658   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
1659   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
1660   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
1661        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
1662        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
1663   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
1664        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
1665   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
1666   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
1667   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
1668   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
1669        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
1670   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
1671   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
1672   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
1673   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
1674        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
1675   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
1676   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
1677        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
1678        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
1679   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
1680   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
1681        uint32_t RESERVED10[4];/*!< Reserved,                                             0x0B8 - 0x0C4 */
1682   __IO uint32_t OR;           /*!< ADC option register,                           Address offset: 0xC8 */
1683 } ADC_TypeDef;
1684 
1685 typedef struct
1686 {
1687   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
1688   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
1689   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
1690   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
1691 } ADC_Common_TypeDef;
1692 
1693 /**
1694   * @brief CORDIC
1695   */
1696 typedef struct
1697 {
1698   __IO uint32_t CSR;           /*!< CORDIC control and status register,        Address offset: 0x00 */
1699   __IO uint32_t WDATA;         /*!< CORDIC argument register,                  Address offset: 0x04 */
1700   __IO uint32_t RDATA;         /*!< CORDIC result register,                    Address offset: 0x08 */
1701 } CORDIC_TypeDef;
1702 
1703 /**
1704   * @brief IWDG
1705   */
1706 typedef struct
1707 {
1708   __IO uint32_t KR;            /*!< IWDG Key register,          Address offset: 0x00 */
1709   __IO uint32_t PR;            /*!< IWDG Prescaler register,    Address offset: 0x04 */
1710   __IO uint32_t RLR;           /*!< IWDG Reload register,       Address offset: 0x08 */
1711   __IO uint32_t SR;            /*!< IWDG Status register,       Address offset: 0x0C */
1712   __IO uint32_t WINR;          /*!< IWDG Window register,       Address offset: 0x10 */
1713   __IO uint32_t EWCR;          /*!< IWDG Early Wakeup register, Address offset: 0x14 */
1714 } IWDG_TypeDef;
1715 
1716 /**
1717   * @brief SPI
1718   */
1719 typedef struct
1720 {
1721   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
1722   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
1723   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
1724   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
1725   __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
1726   __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
1727   __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
1728   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
1729   __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
1730   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
1731   __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
1732   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
1733   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
1734   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
1735   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
1736   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
1737   __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
1738 } SPI_TypeDef;
1739 
1740 /**
1741   * @brief DTS
1742   */
1743 typedef struct
1744 {
1745   __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */
1746   uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */
1747   __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */
1748   uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */
1749   __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */
1750   __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */
1751   uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */
1752   __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */
1753   __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */
1754   __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */
1755   __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */
1756   __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */
1757 }
1758 DTS_TypeDef;
1759 
1760 /**
1761   * @brief WWDG
1762   */
1763 typedef struct
1764 {
1765   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
1766   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
1767   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
1768 } WWDG_TypeDef;
1769 
1770 /*@}*/ /* end of group STM32H573xx_Peripherals */
1771 
1772 
1773 /* --------  End of section using anonymous unions and disabling warnings  -------- */
1774 #if   defined (__CC_ARM)
1775   #pragma pop
1776 #elif defined (__ICCARM__)
1777   /* leave anonymous unions enabled */
1778 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1779   #pragma clang diagnostic pop
1780 #elif defined (__GNUC__)
1781   /* anonymous unions are enabled by default */
1782 #elif defined (__TMS470__)
1783   /* anonymous unions are enabled by default */
1784 #elif defined (__TASKING__)
1785   #pragma warning restore
1786 #elif defined (__CSMC__)
1787   /* anonymous unions are enabled by default */
1788 #else
1789   #warning Not supported compiler type
1790 #endif
1791 
1792 
1793 /* =========================================================================================================================== */
1794 /* ================                          Device Specific Peripheral Address Map                           ================ */
1795 /* =========================================================================================================================== */
1796 
1797 
1798 /** @addtogroup STM32H5xx_Peripheral_peripheralAddr
1799   * @{
1800   */
1801 
1802 /* Internal SRAMs size */
1803 #define SRAM1_SIZE               (0x40000UL)    /*!< SRAM1=256k */
1804 #define SRAM2_SIZE               (0x10000UL)    /*!< SRAM2=64k  */
1805 #define SRAM3_SIZE               (0x50000UL)    /*!< SRAM3=320k */
1806 
1807 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1808 #define FLASH_BASE_NS            (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address         */
1809 #define SRAM1_BASE_NS            (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address             */
1810 #define SRAM2_BASE_NS            (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address              */
1811 #define SRAM3_BASE_NS            (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address             */
1812 #define PERIPH_BASE_NS           (0x40000000UL) /*!< Peripheral non-secure base address                 */
1813 
1814 /* External memories base addresses - Not aliased */
1815 #define FMC_BASE                 (0x60000000UL) /*!< FMC base address                                   */
1816 #define OCTOSPI1_BASE            (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
1817 
1818 #define FMC_BANK1                FMC_BASE
1819 #define FMC_BANK1_1              FMC_BANK1
1820 #define FMC_BANK1_2              (FMC_BANK1 + 0x04000000UL)  /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */
1821 #define FMC_BANK1_3              (FMC_BANK1 + 0x08000000UL)
1822 #define FMC_BANK1_4              (FMC_BANK1 + 0x0C000000UL)
1823 #define FMC_BANK3                (FMC_BASE  + 0x20000000UL)  /*!< FMC Memory Bank3 for NAND */
1824 #define FMC_SDRAM_BANK_1         (FMC_BASE +  0x60000000UL)  /*!< FMC Memory SDRAM Bank1 */
1825 #define FMC_SDRAM_BANK_2         (FMC_BASE +  0x70000000UL)  /*!< FMC Memory SDRAM Bank2 */
1826 
1827 
1828 /* Peripheral memory map - Non secure */
1829 #define APB1PERIPH_BASE_NS       PERIPH_BASE_NS
1830 #define APB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00010000UL)
1831 #define AHB1PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00020000UL)
1832 #define AHB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x02020000UL)
1833 #define APB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04000000UL)
1834 #define AHB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04020000UL)
1835 #define AHB4PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x06000000UL)
1836 
1837 /*!< APB1 Non secure peripherals */
1838 #define TIM2_BASE_NS             (APB1PERIPH_BASE_NS + 0x0000UL)
1839 #define TIM3_BASE_NS             (APB1PERIPH_BASE_NS + 0x0400UL)
1840 #define TIM4_BASE_NS             (APB1PERIPH_BASE_NS + 0x0800UL)
1841 #define TIM5_BASE_NS             (APB1PERIPH_BASE_NS + 0x0C00UL)
1842 #define TIM6_BASE_NS             (APB1PERIPH_BASE_NS + 0x1000UL)
1843 #define TIM7_BASE_NS             (APB1PERIPH_BASE_NS + 0x1400UL)
1844 #define TIM12_BASE_NS            (APB1PERIPH_BASE_NS + 0x1800UL)
1845 #define TIM13_BASE_NS            (APB1PERIPH_BASE_NS + 0x1C00UL)
1846 #define TIM14_BASE_NS            (APB1PERIPH_BASE_NS + 0x2000UL)
1847 #define WWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x2C00UL)
1848 #define IWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x3000UL)
1849 #define SPI2_BASE_NS             (APB1PERIPH_BASE_NS + 0x3800UL)
1850 #define SPI3_BASE_NS             (APB1PERIPH_BASE_NS + 0x3C00UL)
1851 #define USART2_BASE_NS           (APB1PERIPH_BASE_NS + 0x4400UL)
1852 #define USART3_BASE_NS           (APB1PERIPH_BASE_NS + 0x4800UL)
1853 #define UART4_BASE_NS            (APB1PERIPH_BASE_NS + 0x4C00UL)
1854 #define UART5_BASE_NS            (APB1PERIPH_BASE_NS + 0x5000UL)
1855 #define I2C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5400UL)
1856 #define I2C2_BASE_NS             (APB1PERIPH_BASE_NS + 0x5800UL)
1857 #define I3C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5C00UL)
1858 #define CRS_BASE_NS              (APB1PERIPH_BASE_NS + 0x6000UL)
1859 #define USART6_BASE_NS           (APB1PERIPH_BASE_NS + 0x6400UL)
1860 #define USART10_BASE_NS          (APB1PERIPH_BASE_NS + 0x6800UL)
1861 #define USART11_BASE_NS          (APB1PERIPH_BASE_NS + 0x6C00UL)
1862 #define CEC_BASE_NS              (APB1PERIPH_BASE_NS + 0x7000UL)
1863 #define UART7_BASE_NS            (APB1PERIPH_BASE_NS + 0x7800UL)
1864 #define UART8_BASE_NS            (APB1PERIPH_BASE_NS + 0x7C00UL)
1865 #define UART9_BASE_NS            (APB1PERIPH_BASE_NS + 0x8000UL)
1866 #define UART12_BASE_NS           (APB1PERIPH_BASE_NS + 0x8400UL)
1867 #define DTS_BASE_NS              (APB1PERIPH_BASE_NS + 0x8C00UL)
1868 #define LPTIM2_BASE_NS           (APB1PERIPH_BASE_NS + 0x9400UL)
1869 #define FDCAN1_BASE_NS           (APB1PERIPH_BASE_NS + 0xA400UL)
1870 #define FDCAN_CONFIG_BASE_NS     (APB1PERIPH_BASE_NS + 0xA500UL)
1871 #define SRAMCAN_BASE_NS          (APB1PERIPH_BASE_NS + 0xAC00UL)
1872 #define FDCAN2_BASE_NS           (APB1PERIPH_BASE_NS + 0xA800UL)
1873 #define UCPD1_BASE_NS            (APB1PERIPH_BASE_NS + 0xDC00UL)
1874 
1875 /*!< APB2 Non secure peripherals */
1876 #define TIM1_BASE_NS             (APB2PERIPH_BASE_NS + 0x2C00UL)
1877 #define SPI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x3000UL)
1878 #define TIM8_BASE_NS             (APB2PERIPH_BASE_NS + 0x3400UL)
1879 #define USART1_BASE_NS           (APB2PERIPH_BASE_NS + 0x3800UL)
1880 #define TIM15_BASE_NS            (APB2PERIPH_BASE_NS + 0x4000UL)
1881 #define TIM16_BASE_NS            (APB2PERIPH_BASE_NS + 0x4400UL)
1882 #define TIM17_BASE_NS            (APB2PERIPH_BASE_NS + 0x4800UL)
1883 #define SPI4_BASE_NS             (APB2PERIPH_BASE_NS + 0x4C00UL)
1884 #define SPI6_BASE_NS             (APB2PERIPH_BASE_NS + 0x5000UL)
1885 #define SAI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x5400UL)
1886 #define SAI1_Block_A_BASE_NS     (SAI1_BASE_NS + 0x004UL)
1887 #define SAI1_Block_B_BASE_NS     (SAI1_BASE_NS + 0x024UL)
1888 #define SAI2_BASE_NS             (APB2PERIPH_BASE_NS + 0x5800UL)
1889 #define SAI2_Block_A_BASE_NS     (SAI2_BASE_NS + 0x004UL)
1890 #define SAI2_Block_B_BASE_NS     (SAI2_BASE_NS + 0x024UL)
1891 #define USB_DRD_BASE_NS          (APB2PERIPH_BASE_NS + 0x6000UL)
1892 #define USB_DRD_PMAADDR_NS       (APB2PERIPH_BASE_NS + 0x6400UL)
1893 
1894 /*!< AHB1 Non secure peripherals */
1895 #define GPDMA1_BASE_NS           AHB1PERIPH_BASE_NS
1896 #define GPDMA2_BASE_NS           (AHB1PERIPH_BASE_NS + 0x01000UL)
1897 #define FLASH_R_BASE_NS          (AHB1PERIPH_BASE_NS + 0x02000UL)
1898 #define CRC_BASE_NS              (AHB1PERIPH_BASE_NS + 0x03000UL)
1899 #define CORDIC_BASE_NS           (AHB1PERIPH_BASE_NS + 0x03800UL)
1900 #define FMAC_BASE_NS             (AHB1PERIPH_BASE_NS + 0x03C00UL)
1901 #define RAMCFG_BASE_NS           (AHB1PERIPH_BASE_NS + 0x06000UL)
1902 #define ETH_BASE_NS              (AHB1PERIPH_BASE_NS + 0x8000UL)
1903 #define ETH_MAC_BASE_NS          (ETH_BASE)
1904 #define ICACHE_BASE_NS           (AHB1PERIPH_BASE_NS + 0x10400UL)
1905 #define DCACHE1_BASE_NS          (AHB1PERIPH_BASE_NS + 0x11400UL)
1906 #define GTZC_TZSC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12400UL)
1907 #define GTZC_TZIC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12800UL)
1908 #define GTZC_MPCBB1_BASE_NS      (AHB1PERIPH_BASE_NS + 0x12C00UL)
1909 #define GTZC_MPCBB2_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13000UL)
1910 #define GTZC_MPCBB3_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13400UL)
1911 #define BKPSRAM_BASE_NS          (AHB1PERIPH_BASE_NS + 0x16400UL)
1912 
1913 #define GPDMA1_Channel0_BASE_NS   (GPDMA1_BASE_NS + 0x0050UL)
1914 #define GPDMA1_Channel1_BASE_NS   (GPDMA1_BASE_NS + 0x00D0UL)
1915 #define GPDMA1_Channel2_BASE_NS   (GPDMA1_BASE_NS + 0x0150UL)
1916 #define GPDMA1_Channel3_BASE_NS   (GPDMA1_BASE_NS + 0x01D0UL)
1917 #define GPDMA1_Channel4_BASE_NS   (GPDMA1_BASE_NS + 0x0250UL)
1918 #define GPDMA1_Channel5_BASE_NS   (GPDMA1_BASE_NS + 0x02D0UL)
1919 #define GPDMA1_Channel6_BASE_NS   (GPDMA1_BASE_NS + 0x0350UL)
1920 #define GPDMA1_Channel7_BASE_NS   (GPDMA1_BASE_NS + 0x03D0UL)
1921 #define GPDMA2_Channel0_BASE_NS   (GPDMA2_BASE_NS + 0x0050UL)
1922 #define GPDMA2_Channel1_BASE_NS   (GPDMA2_BASE_NS + 0x00D0UL)
1923 #define GPDMA2_Channel2_BASE_NS   (GPDMA2_BASE_NS + 0x0150UL)
1924 #define GPDMA2_Channel3_BASE_NS   (GPDMA2_BASE_NS + 0x01D0UL)
1925 #define GPDMA2_Channel4_BASE_NS   (GPDMA2_BASE_NS + 0x0250UL)
1926 #define GPDMA2_Channel5_BASE_NS   (GPDMA2_BASE_NS + 0x02D0UL)
1927 #define GPDMA2_Channel6_BASE_NS   (GPDMA2_BASE_NS + 0x0350UL)
1928 #define GPDMA2_Channel7_BASE_NS   (GPDMA2_BASE_NS + 0x03D0UL)
1929 
1930 #define RAMCFG_SRAM1_BASE_NS     (RAMCFG_BASE_NS)
1931 #define RAMCFG_SRAM2_BASE_NS     (RAMCFG_BASE_NS + 0x0040UL)
1932 #define RAMCFG_SRAM3_BASE_NS     (RAMCFG_BASE_NS + 0x0080UL)
1933 #define RAMCFG_BKPRAM_BASE_NS    (RAMCFG_BASE_NS + 0x0100UL)
1934 
1935 /*!< AHB2 Non secure peripherals */
1936 #define GPIOA_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00000UL)
1937 #define GPIOB_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00400UL)
1938 #define GPIOC_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00800UL)
1939 #define GPIOD_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00C00UL)
1940 #define GPIOE_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01000UL)
1941 #define GPIOF_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01400UL)
1942 #define GPIOG_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01800UL)
1943 #define GPIOH_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01C00UL)
1944 #define GPIOI_BASE_NS            (AHB2PERIPH_BASE_NS + 0x02000UL)
1945 #define ADC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08000UL)
1946 #define ADC2_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08100UL)
1947 #define ADC12_COMMON_BASE_NS     (AHB2PERIPH_BASE_NS + 0x08300UL)
1948 #define DAC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08400UL)
1949 #define DCMI_BASE_NS             (AHB2PERIPH_BASE_NS + 0x0C000UL)
1950 #define PSSI_BASE_NS             (AHB2PERIPH_BASE_NS + 0x0C400UL)
1951 
1952 #define AES_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0000UL)
1953 #define HASH_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0400UL)
1954 #define HASH_DIGEST_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA0710UL)
1955 #define RNG_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0800UL)
1956 #define SAES_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0C00UL)
1957 #define PKA_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA2000UL)
1958 #define PKA_RAM_BASE_NS          (AHB2PERIPH_BASE_NS + 0xA2400UL)
1959 
1960 
1961 /*!< APB3 Non secure peripherals */
1962 #define SBS_BASE_NS              (APB3PERIPH_BASE_NS + 0x0400UL)
1963 #define SPI5_BASE_NS             (APB3PERIPH_BASE_NS + 0x2000UL)
1964 #define LPUART1_BASE_NS          (APB3PERIPH_BASE_NS + 0x2400UL)
1965 #define I2C3_BASE_NS             (APB3PERIPH_BASE_NS + 0x2800UL)
1966 #define I2C4_BASE_NS             (APB3PERIPH_BASE_NS + 0x2C00UL)
1967 #define LPTIM1_BASE_NS           (APB3PERIPH_BASE_NS + 0x4400UL)
1968 #define LPTIM3_BASE_NS           (APB3PERIPH_BASE_NS + 0x4800UL)
1969 #define LPTIM4_BASE_NS           (APB3PERIPH_BASE_NS + 0x4C00UL)
1970 #define LPTIM5_BASE_NS           (APB3PERIPH_BASE_NS + 0x5000UL)
1971 #define LPTIM6_BASE_NS           (APB3PERIPH_BASE_NS + 0x5400UL)
1972 #define VREFBUF_BASE_NS          (APB3PERIPH_BASE_NS + 0x7400UL)
1973 #define RTC_BASE_NS              (APB3PERIPH_BASE_NS + 0x7800UL)
1974 #define TAMP_BASE_NS             (APB3PERIPH_BASE_NS + 0x7C00UL)
1975 
1976 /*!< AHB3 Non secure peripherals */
1977 #define PWR_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0800UL)
1978 #define RCC_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0C00UL)
1979 #define EXTI_BASE_NS             (AHB3PERIPH_BASE_NS + 0x2000UL)
1980 #define DEBUG_BASE_NS            (AHB3PERIPH_BASE_NS + 0x4000UL)
1981 /*!< AHB4 Non secure peripherals */
1982 #define OTFDEC1_BASE_NS          (AHB4PERIPH_BASE_NS + 0x5000UL)
1983 #define OTFDEC1_REGION1_BASE_NS  (OTFDEC1_BASE_NS + 0x20UL)
1984 #define OTFDEC1_REGION2_BASE_NS  (OTFDEC1_BASE_NS + 0x50UL)
1985 #define OTFDEC1_REGION3_BASE_NS  (OTFDEC1_BASE_NS + 0x80UL)
1986 #define OTFDEC1_REGION4_BASE_NS  (OTFDEC1_BASE_NS + 0xB0UL)
1987 #define SDMMC1_BASE_NS           (AHB4PERIPH_BASE_NS + 0x8000UL)
1988 #define DLYB_SDMMC1_BASE_NS      (AHB4PERIPH_BASE_NS + 0x8400UL)
1989 #define SDMMC2_BASE_NS           (AHB4PERIPH_BASE_NS + 0x8C00UL)
1990 #define DLYB_SDMMC2_BASE_NS      (AHB4PERIPH_BASE_NS + 0x8800UL)
1991 
1992 #define FMC_R_BASE_NS            (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address              */
1993 #define OCTOSPI1_R_BASE_NS       (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address         */
1994 #define DLYB_OCTOSPI1_BASE_NS    (AHB4PERIPH_BASE_NS + 0x0F000UL)
1995 
1996 /*!< FMC Banks Non secure registers base address */
1997 #define FMC_Bank1_R_BASE_NS      (FMC_R_BASE_NS + 0x0000UL)
1998 #define FMC_Bank1E_R_BASE_NS     (FMC_R_BASE_NS + 0x0104UL)
1999 #define FMC_Bank3_R_BASE_NS      (FMC_R_BASE_NS + 0x0080UL)
2000 #define FMC_Bank5_6_R_BASE_NS    (FMC_R_BASE_NS + 0x0140UL)
2001 
2002 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
2003 #define FLASH_BASE_S            (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
2004 #define SRAM1_BASE_S            (0x30000000UL) /*!< SRAM1 (192 KB) secure base address     */
2005 #define SRAM2_BASE_S            (0x30040000UL) /*!< SRAM2 (64 KB) secure base address      */
2006 #define SRAM3_BASE_S            (0x30050000UL) /*!< SRAM3 (512 KB) secure base address     */
2007 #define PERIPH_BASE_S           (0x50000000UL) /*!< Peripheral secure base address         */
2008 
2009 /* Peripheral memory map - Secure */
2010 #define APB1PERIPH_BASE_S       PERIPH_BASE_S
2011 #define APB2PERIPH_BASE_S       (PERIPH_BASE_S + 0x00010000UL)
2012 #define AHB1PERIPH_BASE_S       (PERIPH_BASE_S + 0x00020000UL)
2013 #define AHB2PERIPH_BASE_S       (PERIPH_BASE_S + 0x02020000UL)
2014 #define APB3PERIPH_BASE_S       (PERIPH_BASE_S + 0x04000000UL)
2015 #define AHB3PERIPH_BASE_S       (PERIPH_BASE_S + 0x04020000UL)
2016 #define AHB4PERIPH_BASE_S       (PERIPH_BASE_S + 0x06000000UL)
2017 
2018 /*!< APB1 secure peripherals */
2019 #define TIM2_BASE_S             (APB1PERIPH_BASE_S + 0x0000UL)
2020 #define TIM3_BASE_S             (APB1PERIPH_BASE_S + 0x0400UL)
2021 #define TIM4_BASE_S             (APB1PERIPH_BASE_S + 0x0800UL)
2022 #define TIM5_BASE_S             (APB1PERIPH_BASE_S + 0x0C00UL)
2023 #define TIM6_BASE_S             (APB1PERIPH_BASE_S + 0x1000UL)
2024 #define TIM7_BASE_S             (APB1PERIPH_BASE_S + 0x1400UL)
2025 #define TIM12_BASE_S            (APB1PERIPH_BASE_S + 0x1800UL)
2026 #define TIM13_BASE_S            (APB1PERIPH_BASE_S + 0x1C00UL)
2027 #define TIM14_BASE_S            (APB1PERIPH_BASE_S + 0x2000UL)
2028 #define WWDG_BASE_S             (APB1PERIPH_BASE_S + 0x2C00UL)
2029 #define IWDG_BASE_S             (APB1PERIPH_BASE_S + 0x3000UL)
2030 #define SPI2_BASE_S             (APB1PERIPH_BASE_S + 0x3800UL)
2031 #define SPI3_BASE_S             (APB1PERIPH_BASE_S + 0x3C00UL)
2032 #define USART2_BASE_S           (APB1PERIPH_BASE_S + 0x4400UL)
2033 #define USART3_BASE_S           (APB1PERIPH_BASE_S + 0x4800UL)
2034 #define UART4_BASE_S            (APB1PERIPH_BASE_S + 0x4C00UL)
2035 #define UART5_BASE_S            (APB1PERIPH_BASE_S + 0x5000UL)
2036 #define I2C1_BASE_S             (APB1PERIPH_BASE_S + 0x5400UL)
2037 #define I2C2_BASE_S             (APB1PERIPH_BASE_S + 0x5800UL)
2038 #define I3C1_BASE_S             (APB1PERIPH_BASE_S + 0x5C00UL)
2039 #define CRS_BASE_S              (APB1PERIPH_BASE_S + 0x6000UL)
2040 #define USART6_BASE_S           (APB1PERIPH_BASE_S + 0x6400UL)
2041 #define USART10_BASE_S          (APB1PERIPH_BASE_S + 0x6800UL)
2042 #define USART11_BASE_S          (APB1PERIPH_BASE_S + 0x6C00UL)
2043 #define CEC_BASE_S              (APB1PERIPH_BASE_S + 0x7000UL)
2044 #define UART7_BASE_S            (APB1PERIPH_BASE_S + 0x7800UL)
2045 #define UART8_BASE_S            (APB1PERIPH_BASE_S + 0x7C00UL)
2046 #define UART9_BASE_S            (APB1PERIPH_BASE_S + 0x8000UL)
2047 #define UART12_BASE_S           (APB1PERIPH_BASE_S + 0x8400UL)
2048 #define DTS_BASE_S              (APB1PERIPH_BASE_S + 0x8C00UL)
2049 #define LPTIM2_BASE_S           (APB1PERIPH_BASE_S + 0x9400UL)
2050 #define FDCAN1_BASE_S           (APB1PERIPH_BASE_S + 0xA400UL)
2051 #define FDCAN_CONFIG_BASE_S     (APB1PERIPH_BASE_S + 0xA500UL)
2052 #define SRAMCAN_BASE_S          (APB1PERIPH_BASE_S + 0xAC00UL)
2053 #define FDCAN2_BASE_S           (APB1PERIPH_BASE_S + 0xA800UL)
2054 #define UCPD1_BASE_S            (APB1PERIPH_BASE_S + 0xDC00UL)
2055 
2056 /*!< APB2 Secure peripherals */
2057 #define TIM1_BASE_S             (APB2PERIPH_BASE_S + 0x2C00UL)
2058 #define SPI1_BASE_S             (APB2PERIPH_BASE_S + 0x3000UL)
2059 #define TIM8_BASE_S             (APB2PERIPH_BASE_S + 0x3400UL)
2060 #define USART1_BASE_S           (APB2PERIPH_BASE_S + 0x3800UL)
2061 #define TIM15_BASE_S            (APB2PERIPH_BASE_S + 0x4000UL)
2062 #define TIM16_BASE_S            (APB2PERIPH_BASE_S + 0x4400UL)
2063 #define TIM17_BASE_S            (APB2PERIPH_BASE_S + 0x4800UL)
2064 #define SPI4_BASE_S             (APB2PERIPH_BASE_S + 0x4C00UL)
2065 #define SPI6_BASE_S             (APB2PERIPH_BASE_S + 0x5000UL)
2066 #define SAI1_BASE_S             (APB2PERIPH_BASE_S + 0x5400UL)
2067 #define SAI1_Block_A_BASE_S     (SAI1_BASE_S + 0x004UL)
2068 #define SAI1_Block_B_BASE_S     (SAI1_BASE_S + 0x024UL)
2069 #define SAI2_BASE_S             (APB2PERIPH_BASE_S + 0x5800UL)
2070 #define SAI2_Block_A_BASE_S     (SAI2_BASE_S + 0x004UL)
2071 #define SAI2_Block_B_BASE_S     (SAI2_BASE_S + 0x024UL)
2072 #define USB_DRD_BASE_S          (APB2PERIPH_BASE_S + 0x6000UL)
2073 #define USB_DRD_PMAADDR_S       (APB2PERIPH_BASE_S + 0x6400UL)
2074 
2075 /*!< AHB1 secure peripherals */
2076 #define GPDMA1_BASE_S           AHB1PERIPH_BASE_S
2077 #define GPDMA2_BASE_S           (AHB1PERIPH_BASE_S + 0x01000UL)
2078 #define FLASH_R_BASE_S          (AHB1PERIPH_BASE_S + 0x02000UL)
2079 #define CRC_BASE_S              (AHB1PERIPH_BASE_S + 0x03000UL)
2080 #define CORDIC_BASE_S           (AHB1PERIPH_BASE_S + 0x03800UL)
2081 #define FMAC_BASE_S             (AHB1PERIPH_BASE_S + 0x03C00UL)
2082 #define RAMCFG_BASE_S           (AHB1PERIPH_BASE_S + 0x06000UL)
2083 #define ETH_BASE_S              (AHB1PERIPH_BASE_S + 0x8000UL)
2084 #define ETH_MAC_BASE_S          (ETH_BASE_S)
2085 #define ICACHE_BASE_S           (AHB1PERIPH_BASE_S + 0x10400UL)
2086 #define DCACHE1_BASE_S          (AHB1PERIPH_BASE_S + 0x11400UL)
2087 #define GTZC_TZSC1_BASE_S       (AHB1PERIPH_BASE_S + 0x12400UL)
2088 #define GTZC_TZIC1_BASE_S       (AHB1PERIPH_BASE_S + 0x12800UL)
2089 #define GTZC_MPCBB1_BASE_S      (AHB1PERIPH_BASE_S + 0x12C00UL)
2090 #define GTZC_MPCBB2_BASE_S      (AHB1PERIPH_BASE_S + 0x13000UL)
2091 #define GTZC_MPCBB3_BASE_S      (AHB1PERIPH_BASE_S + 0x13400UL)
2092 #define BKPSRAM_BASE_S          (AHB1PERIPH_BASE_S + 0x16400UL)
2093 
2094 #define GPDMA1_Channel0_BASE_S   (GPDMA1_BASE_S + 0x0050UL)
2095 #define GPDMA1_Channel1_BASE_S   (GPDMA1_BASE_S + 0x00D0UL)
2096 #define GPDMA1_Channel2_BASE_S   (GPDMA1_BASE_S + 0x0150UL)
2097 #define GPDMA1_Channel3_BASE_S   (GPDMA1_BASE_S + 0x01D0UL)
2098 #define GPDMA1_Channel4_BASE_S   (GPDMA1_BASE_S + 0x0250UL)
2099 #define GPDMA1_Channel5_BASE_S   (GPDMA1_BASE_S + 0x02D0UL)
2100 #define GPDMA1_Channel6_BASE_S   (GPDMA1_BASE_S + 0x0350UL)
2101 #define GPDMA1_Channel7_BASE_S   (GPDMA1_BASE_S + 0x03D0UL)
2102 #define GPDMA2_Channel0_BASE_S   (GPDMA2_BASE_S + 0x0050UL)
2103 #define GPDMA2_Channel1_BASE_S   (GPDMA2_BASE_S + 0x00D0UL)
2104 #define GPDMA2_Channel2_BASE_S   (GPDMA2_BASE_S + 0x0150UL)
2105 #define GPDMA2_Channel3_BASE_S   (GPDMA2_BASE_S + 0x01D0UL)
2106 #define GPDMA2_Channel4_BASE_S   (GPDMA2_BASE_S + 0x0250UL)
2107 #define GPDMA2_Channel5_BASE_S   (GPDMA2_BASE_S + 0x02D0UL)
2108 #define GPDMA2_Channel6_BASE_S   (GPDMA2_BASE_S + 0x0350UL)
2109 #define GPDMA2_Channel7_BASE_S   (GPDMA2_BASE_S + 0x03D0UL)
2110 
2111 #define RAMCFG_SRAM1_BASE_S     (RAMCFG_BASE_S)
2112 #define RAMCFG_SRAM2_BASE_S     (RAMCFG_BASE_S + 0x0040UL)
2113 #define RAMCFG_SRAM3_BASE_S     (RAMCFG_BASE_S + 0x0080UL)
2114 #define RAMCFG_BKPRAM_BASE_S    (RAMCFG_BASE_S + 0x0100UL)
2115 
2116 /*!< AHB2 secure peripherals */
2117 #define GPIOA_BASE_S            (AHB2PERIPH_BASE_S + 0x00000UL)
2118 #define GPIOB_BASE_S            (AHB2PERIPH_BASE_S + 0x00400UL)
2119 #define GPIOC_BASE_S            (AHB2PERIPH_BASE_S + 0x00800UL)
2120 #define GPIOD_BASE_S            (AHB2PERIPH_BASE_S + 0x00C00UL)
2121 #define GPIOE_BASE_S            (AHB2PERIPH_BASE_S + 0x01000UL)
2122 #define GPIOF_BASE_S            (AHB2PERIPH_BASE_S + 0x01400UL)
2123 #define GPIOG_BASE_S            (AHB2PERIPH_BASE_S + 0x01800UL)
2124 #define GPIOH_BASE_S            (AHB2PERIPH_BASE_S + 0x01C00UL)
2125 #define GPIOI_BASE_S            (AHB2PERIPH_BASE_S + 0x02000UL)
2126 #define ADC1_BASE_S             (AHB2PERIPH_BASE_S + 0x08000UL)
2127 #define ADC2_BASE_S             (AHB2PERIPH_BASE_S + 0x08100UL)
2128 #define ADC12_COMMON_BASE_S     (AHB2PERIPH_BASE_S + 0x08300UL)
2129 #define DAC1_BASE_S             (AHB2PERIPH_BASE_S + 0x08400UL)
2130 #define DCMI_BASE_S             (AHB2PERIPH_BASE_S + 0x0C000UL)
2131 #define PSSI_BASE_S             (AHB2PERIPH_BASE_S + 0x0C400UL)
2132 #define AES_BASE_S              (AHB2PERIPH_BASE_S + 0xA0000UL)
2133 #define HASH_BASE_S             (AHB2PERIPH_BASE_S + 0xA0400UL)
2134 #define HASH_DIGEST_BASE_S      (AHB2PERIPH_BASE_S + 0xA0710UL)
2135 #define RNG_BASE_S              (AHB2PERIPH_BASE_S + 0xA0800UL)
2136 #define SAES_BASE_S             (AHB2PERIPH_BASE_S + 0xA0C00UL)
2137 #define PKA_BASE_S              (AHB2PERIPH_BASE_S + 0xA2000UL)
2138 #define PKA_RAM_BASE_S          (AHB2PERIPH_BASE_S + 0xA2400UL)
2139 
2140 /*!< APB3 secure peripherals */
2141 #define SBS_BASE_S              (APB3PERIPH_BASE_S + 0x0400UL)
2142 #define SPI5_BASE_S             (APB3PERIPH_BASE_S + 0x2000UL)
2143 #define LPUART1_BASE_S          (APB3PERIPH_BASE_S + 0x2400UL)
2144 #define I2C3_BASE_S             (APB3PERIPH_BASE_S + 0x2800UL)
2145 #define I2C4_BASE_S             (APB3PERIPH_BASE_S + 0x2C00UL)
2146 #define LPTIM1_BASE_S           (APB3PERIPH_BASE_S + 0x4400UL)
2147 #define LPTIM3_BASE_S           (APB3PERIPH_BASE_S + 0x4800UL)
2148 #define LPTIM4_BASE_S           (APB3PERIPH_BASE_S + 0x4C00UL)
2149 #define LPTIM5_BASE_S           (APB3PERIPH_BASE_S + 0x5000UL)
2150 #define LPTIM6_BASE_S           (APB3PERIPH_BASE_S + 0x5400UL)
2151 #define VREFBUF_BASE_S          (APB3PERIPH_BASE_S + 0x7400UL)
2152 #define RTC_BASE_S              (APB3PERIPH_BASE_S + 0x7800UL)
2153 #define TAMP_BASE_S             (APB3PERIPH_BASE_S + 0x7C00UL)
2154 
2155 /*!< AHB3 secure peripherals */
2156 #define PWR_BASE_S              (AHB3PERIPH_BASE_S + 0x0800UL)
2157 #define RCC_BASE_S              (AHB3PERIPH_BASE_S + 0x0C00UL)
2158 #define EXTI_BASE_S             (AHB3PERIPH_BASE_S + 0x2000UL)
2159 #define DEBUG_BASE_S            (AHB3PERIPH_BASE_S + 0x4000UL)
2160 
2161 /*!< AHB4 secure peripherals */
2162 #define OTFDEC1_BASE_S          (AHB4PERIPH_BASE_S + 0x5000UL)
2163 #define OTFDEC1_REGION1_BASE_S  (OTFDEC1_BASE_S + 0x20UL)
2164 #define OTFDEC1_REGION2_BASE_S  (OTFDEC1_BASE_S + 0x50UL)
2165 #define OTFDEC1_REGION3_BASE_S  (OTFDEC1_BASE_S + 0x80UL)
2166 #define OTFDEC1_REGION4_BASE_S  (OTFDEC1_BASE_S + 0xB0UL)
2167 #define SDMMC1_BASE_S           (AHB4PERIPH_BASE_S + 0x8000UL)
2168 #define DLYB_SDMMC1_BASE_S      (AHB4PERIPH_BASE_S + 0x8400UL)
2169 #define SDMMC2_BASE_S           (AHB4PERIPH_BASE_S + 0x8C00UL)
2170 #define DLYB_SDMMC2_BASE_S      (AHB4PERIPH_BASE_S + 0x8800UL)
2171 
2172 #define FMC_R_BASE_S            (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address              */
2173 #define OCTOSPI1_R_BASE_S       (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address         */
2174 #define DLYB_OCTOSPI1_BASE_S    (AHB4PERIPH_BASE_S + 0x0F000UL)
2175 
2176 /*!< FMC Banks Non secure registers base address */
2177 #define FMC_Bank1_R_BASE_S      (FMC_R_BASE_S + 0x0000UL)
2178 #define FMC_Bank1E_R_BASE_S     (FMC_R_BASE_S + 0x0104UL)
2179 #define FMC_Bank3_R_BASE_S      (FMC_R_BASE_S + 0x0080UL)
2180 #define FMC_Bank5_6_R_BASE_S    (FMC_R_BASE_S + 0x0140UL)
2181 
2182 /* Debug MCU registers base address */
2183 #define DBGMCU_BASE             (0x44024000UL)
2184 
2185 #define PACKAGE_BASE            (0x08FFF80CUL) /*!< Package data register base address     */
2186 #define UID_BASE                (0x08FFF800UL) /*!< Unique device ID register base address */
2187 #define FLASHSIZE_BASE          (0x08FFF80CUL) /*!< Flash size data register base address  */
2188 
2189 
2190 /* Internal Flash OTP Area */
2191 #define FLASH_OTP_BASE          (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
2192 #define FLASH_OTP_SIZE          (0x800U)       /*!< 2048 bytes OTP (one-time programmable)         */
2193 
2194 /* Flash system Area */
2195 #define FLASH_SYSTEM_BASE_NS    (0x0BF80000UL) /*!< FLASH System non-secure base address  */
2196 #define FLASH_SYSTEM_BASE_S     (0x0FF80000UL) /*!< FLASH System secure base address      */
2197 #define FLASH_SYSTEM_SIZE       (0x10000U)     /*!< 64 Kbytes system Flash */
2198 
2199 /* Internal Flash EDATA Area */
2200 #define FLASH_EDATA_BASE_NS     (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */
2201 #define FLASH_EDATA_BASE_S      (0x0D000000UL) /*!< FLASH high-cycle data secure base address     */
2202 #define FLASH_EDATA_SIZE        (0x18000U)     /*!< 96 KB of Flash high-cycle data                */
2203 
2204 /* Internal Flash OBK Area */
2205 #define FLASH_OBK_BASE_NS       (0x0BFD0000UL)  /*!< FLASH OBK (option byte keys) non-secure base address */
2206 #define FLASH_OBK_BASE_S        (0x0FFD0000UL)  /*!< FLASH OBK (option byte keys) secure base address     */
2207 #define FLASH_OBK_SIZE          (0x2000U)       /*!< 8 KB of option byte keys                             */
2208 #define FLASH_OBK_HDPL0_SIZE    (0x100U)        /*!< 256 Bytes of HDPL1 option byte keys                  */
2209 
2210 #define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE)         /*!< FLASH OBK HDPL1 non-secure base address         */
2211 #define FLASH_OBK_HDPL1_BASE_S  (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE)          /*!< FLASH OBK HDPL1 secure base address             */
2212 #define FLASH_OBK_HDPL1_SIZE    (0x800U)                                           /*!< 2 KB of HDPL1 option byte keys                  */
2213 
2214 #define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE)   /*!< FLASH OBK HDPL2 non-secure base address         */
2215 #define FLASH_OBK_HDPL2_BASE_S  (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE)    /*!< FLASH OBK HDPL2 secure base address             */
2216 #define FLASH_OBK_HDPL2_SIZE    (0x300U)                                           /*!< 768 Bytes of HDPL2 option byte keys             */
2217 
2218 #define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE)   /*!< FLASH OBK HDPL3 non-secure base address         */
2219 #define FLASH_OBK_HDPL3_BASE_S  (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE)    /*!< FLASH OBK HDPL3 secure base address             */
2220 #define FLASH_OBK_HDPL3_SIZE    (0x13F0U)                                          /*!< 5104 Bytes HDPL3 option byte keys */
2221 
2222 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2223 #define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS)                          /*!< FLASH OBK HDPL3 non-secure base address         */
2224 #define FLASH_OBK_HDPL3S_BASE_S  (FLASH_OBK_HDPL3_BASE_S)                           /*!< FLASH OBK HDPL3 secure base address             */
2225 #define FLASH_OBK_HDPL3S_SIZE    (0x0C00U)                                          /*!< 3072 Bytes of secure HDPL3 option byte keys     */
2226 
2227 #define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address         */
2228 #define FLASH_OBK_HDPL3NS_BASE_S  (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE)  /*!< FLASH OBK HDPL3 secure base address             */
2229 #define FLASH_OBK_HDPL3NS_SIZE    (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE)    /*!< 2032 Bytes of non-secure HDPL3 option byte keys */
2230 #endif /* CMSE */
2231 
2232 /*!< USB PMA SIZE */
2233 #define USB_DRD_PMA_SIZE        (2048U)         /*!< USB PMA Size 2Kbyte */
2234 
2235 /*!< Root Secure Service Library */
2236 /************ RSSLIB SAU system Flash region definition constants *************/
2237 #define RSSLIB_SYS_FLASH_NS_PFUNC_START   (0xBF9FE78UL)
2238 #define RSSLIB_SYS_FLASH_NS_PFUNC_END     (0xBF9FE84UL)
2239 
2240 /************ RSSLIB function return constants ********************************/
2241 #define RSSLIB_ERROR   (0xF5F5F5F5UL)
2242 #define RSSLIB_SUCCESS (0xEAEAEAEAUL)
2243 
2244 /*!< RSSLIB  pointer function structure address definition */
2245 #define RSSLIB_PFUNC_BASE (0xBF9FE78UL)
2246 #define RSSLIB_PFUNC      ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
2247 
2248 /**
2249   * @brief  Prototype of RSSLIB Jump to HDP level2 Function
2250   * @detail This function increments HDP level up to HDP level 2
2251   *         Then it enables the MPU region corresponding the MPU index
2252   *         provided as input parameter. The Vector Table shall be located
2253   *         within this MPU region.
2254   *         Then it jumps to the reset handler present within the
2255   *         Vector table. The function does not return on successful execution.
2256   * @param  pointer on the vector table containing the reset handler the function
2257   *         jumps to.
2258   * @param  MPU region index containing the vector table
2259   *         jumps to.
2260   * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2261   */
2262 typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
2263 
2264 /**
2265   * @brief  Prototype of RSSLIB Jump to HDP level3 Function
2266   * @detail This function increments HDP level up to HDP level 3
2267   *         Then it enables the MPU region corresponding the MPU index
2268   *         provided as input parameter. The Vector Table shall be located
2269   *         within this MPU region.
2270   *         Then it jumps to the reset handler present within the
2271   *         Vector table. The function does not return on successful execution.
2272   * @param  pointer on the vector table containing the reset handler the function
2273   *         jumps to.
2274   * @param  MPU region index containing the vector table
2275   *         jumps to.
2276   * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2277   */
2278 typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
2279 
2280 /**
2281   * @brief  Prototype of RSSLIB Jump to HDP level3 Function
2282   * @detail This function increments HDP level up to HDP level 3
2283   *         Then it jumps to the non-secure reset handler present within the
2284   *         Vector table. The function does not return on successful execution.
2285   * @param  pointer on the vector table containing the reset handler the function
2286   *         jumps to.
2287   * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2288   */
2289 typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr);
2290 
2291 /**
2292   * @brief RSSLib secure callable function pointer structure
2293   */
2294 typedef struct
2295 {
2296   __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2;
2297   __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
2298   __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS;
2299 } S_pFuncTypeDef;
2300 
2301 
2302 /**
2303   * @brief RSSLib function pointer structure
2304   */
2305 typedef struct
2306 {
2307   S_pFuncTypeDef S;
2308 }RSSLIB_pFunc_TypeDef;
2309 
2310 /*!< Non Secure Service Library */
2311 /************ RSSLIB SAU system Flash region definition constants *************/
2312 #define NSSLIB_SYS_FLASH_NS_PFUNC_START   (0xBF9FE6CUL)
2313 #define NSSLIB_SYS_FLASH_NS_PFUNC_END     (0xBF9FE74UL)
2314 
2315 /************ RSSLIB function return constants ********************************/
2316 #define NSSLIB_ERROR   (0xF5F5F5F5UL)
2317 #define NSSLIB_SUCCESS (0xEAEAEAEAUL)
2318 
2319 /*!< RSSLIB  pointer function structure address definition */
2320 #define NSSLIB_PFUNC_BASE (0xBF9FE6CUL)
2321 #define NSSLIB_PFUNC      ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE)
2322 
2323 /**
2324   * @brief  Prototype of RSSLIB Jump to HDP level2 Function
2325   * @detail This function increments HDP level up to HDP level 2
2326   *         Then it enables the MPU region corresponding the MPU index
2327   *         provided as input parameter. The Vector Table shall be located
2328   *         within this MPU region.
2329   *         Then it jumps to the reset handler present within the
2330   *         Vector table. The function does not return on successful execution.
2331   * @param  pointer on the vector table containing the reset handler the function
2332   *         jumps to.
2333   * @param  MPU region index containing the vector table
2334   *         jumps to.
2335   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2336   */
2337 typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
2338 
2339 /**
2340   * @brief  Prototype of RSSLIB Jump to HDP level3 Function
2341   * @detail This function increments HDP level up to HDP level 3
2342   *         Then it enables the MPU region corresponding the MPU index
2343   *         provided as input parameter. The Vector Table shall be located
2344   *         within this MPU region.
2345   *         Then it jumps to the reset handler present within the
2346   *         Vector table. The function does not return on successful execution.
2347   * @param  pointer on the vector table containing the reset handler the function
2348   *         jumps to.
2349   * @param  MPU region index containing the vector table
2350   *         jumps to.
2351   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2352   */
2353 typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
2354 
2355 /**
2356   * @brief RSSLib secure callable function pointer structure
2357   */
2358 typedef struct
2359 {
2360   __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2;
2361   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
2362 } NSSLIB_pFunc_TypeDef;
2363 
2364 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
2365 
2366 
2367 /* =========================================================================================================================== */
2368 /* ================                                  Peripheral declaration                                   ================ */
2369 /* =========================================================================================================================== */
2370 
2371 
2372 /** @addtogroup STM32H5xx_Peripheral_declaration
2373   * @{
2374   */
2375 
2376 /*!< APB1 Non secure peripherals */
2377 #define TIM2_NS                ((TIM_TypeDef *)TIM2_BASE_NS)
2378 #define TIM3_NS                ((TIM_TypeDef *)TIM3_BASE_NS)
2379 #define TIM4_NS                ((TIM_TypeDef *)TIM4_BASE_NS)
2380 #define TIM5_NS                ((TIM_TypeDef *)TIM5_BASE_NS)
2381 #define TIM6_NS                ((TIM_TypeDef *)TIM6_BASE_NS)
2382 #define TIM7_NS                ((TIM_TypeDef *)TIM7_BASE_NS)
2383 #define TIM12_NS               ((TIM_TypeDef *)TIM12_BASE_NS)
2384 #define TIM13_NS               ((TIM_TypeDef *)TIM13_BASE_NS)
2385 #define TIM14_NS               ((TIM_TypeDef *)TIM14_BASE_NS)
2386 #define WWDG_NS                ((WWDG_TypeDef *)WWDG_BASE_NS)
2387 #define IWDG_NS                ((IWDG_TypeDef *)IWDG_BASE_NS)
2388 #define SPI2_NS                ((SPI_TypeDef *)SPI2_BASE_NS)
2389 #define SPI3_NS                ((SPI_TypeDef *)SPI3_BASE_NS)
2390 #define USART2_NS              ((USART_TypeDef *)USART2_BASE_NS)
2391 #define USART3_NS              ((USART_TypeDef *)USART3_BASE_NS)
2392 #define UART4_NS               ((USART_TypeDef *)UART4_BASE_NS)
2393 #define UART5_NS               ((USART_TypeDef *)UART5_BASE_NS)
2394 #define I2C1_NS                ((I2C_TypeDef *)I2C1_BASE_NS)
2395 #define I2C2_NS                ((I2C_TypeDef *)I2C2_BASE_NS)
2396 #define I3C1_NS                ((I3C_TypeDef *)I3C1_BASE_NS)
2397 #define CRS_NS                 ((CRS_TypeDef *)CRS_BASE_NS)
2398 #define USART6_NS              ((USART_TypeDef *)USART6_BASE_NS)
2399 #define USART10_NS             ((USART_TypeDef *)USART10_BASE_NS)
2400 #define USART11_NS             ((USART_TypeDef *)USART11_BASE_NS)
2401 #define CEC_NS                 ((CEC_TypeDef *)CEC_BASE_NS)
2402 #define UART7_NS               ((USART_TypeDef *)UART7_BASE_NS)
2403 #define UART8_NS               ((USART_TypeDef *)UART8_BASE_NS)
2404 #define UART9_NS               ((USART_TypeDef *)UART9_BASE_NS)
2405 #define UART12_NS              ((USART_TypeDef *)UART12_BASE_NS)
2406 #define DTS_NS                 ((DTS_TypeDef *)DTS_BASE_NS)
2407 #define LPTIM2_NS              ((LPTIM_TypeDef *)LPTIM2_BASE_NS)
2408 #define FDCAN1_NS              ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS)
2409 #define FDCAN_CONFIG_NS        ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS)
2410 #define FDCAN2_NS              ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS)
2411 #define UCPD1_NS               ((UCPD_TypeDef *)UCPD1_BASE_NS)
2412 
2413 /*!< APB2 Non secure peripherals */
2414 #define TIM1_NS                ((TIM_TypeDef *) TIM1_BASE_NS)
2415 #define SPI1_NS                ((SPI_TypeDef *) SPI1_BASE_NS)
2416 #define TIM8_NS                ((TIM_TypeDef *) TIM8_BASE_NS)
2417 #define USART1_NS              ((USART_TypeDef *) USART1_BASE_NS)
2418 #define TIM15_NS               ((TIM_TypeDef *) TIM15_BASE_NS)
2419 #define TIM16_NS               ((TIM_TypeDef *) TIM16_BASE_NS)
2420 #define TIM17_NS               ((TIM_TypeDef *) TIM17_BASE_NS)
2421 #define SPI4_NS                ((SPI_TypeDef *) SPI4_BASE_NS)
2422 #define SPI6_NS                ((SPI_TypeDef *) SPI6_BASE_NS)
2423 #define SAI1_NS                ((SAI_TypeDef *) SAI1_BASE_NS)
2424 #define SAI1_Block_A_NS        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
2425 #define SAI1_Block_B_NS        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
2426 #define SAI2_NS                ((SAI_TypeDef *) SAI2_BASE_NS)
2427 #define SAI2_Block_A_NS        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
2428 #define SAI2_Block_B_NS        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
2429 #define USB_DRD_FS_NS          ((USB_DRD_TypeDef *) USB_DRD_BASE_NS)
2430 #define USB_DRD_PMA_BUFF_NS    ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS)
2431 
2432 /*!< AHB1 Non secure peripherals */
2433 #define GPDMA1_NS              ((DMA_TypeDef *) GPDMA1_BASE_NS)
2434 #define GPDMA2_NS              ((DMA_TypeDef *) GPDMA2_BASE_NS)
2435 #define FLASH_NS               ((FLASH_TypeDef *) FLASH_R_BASE_NS)
2436 #define CRC_NS                 ((CRC_TypeDef *) CRC_BASE_NS)
2437 #define CORDIC_NS              ((CORDIC_TypeDef *) CORDIC_BASE_NS)
2438 #define FMAC_NS                ((FMAC_TypeDef *) FMAC_BASE_NS)
2439 #define RAMCFG_SRAM1_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
2440 #define RAMCFG_SRAM2_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
2441 #define RAMCFG_SRAM3_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS)
2442 #define RAMCFG_BKPRAM_NS       ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
2443 #define ETH_NS                 ((ETH_TypeDef *) ETH_BASE_NS)
2444 #define ETH_MAC_NS             ((ETH_TypeDef *) ETH_MAC_BASE_NS)
2445 #define ICACHE_NS              ((ICACHE_TypeDef *) ICACHE_BASE_NS)
2446 #define DCACHE1_NS             ((DCACHE_TypeDef *) DCACHE1_BASE_NS)
2447 #define GTZC_TZSC1_NS          ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
2448 #define GTZC_TZIC1_NS          ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS)
2449 #define GTZC_MPCBB1_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
2450 #define GTZC_MPCBB2_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
2451 #define GTZC_MPCBB3_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS)
2452 #define GPDMA1_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
2453 #define GPDMA1_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
2454 #define GPDMA1_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
2455 #define GPDMA1_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
2456 #define GPDMA1_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
2457 #define GPDMA1_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
2458 #define GPDMA1_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
2459 #define GPDMA1_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
2460 #define GPDMA2_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS)
2461 #define GPDMA2_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS)
2462 #define GPDMA2_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS)
2463 #define GPDMA2_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS)
2464 #define GPDMA2_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS)
2465 #define GPDMA2_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS)
2466 #define GPDMA2_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS)
2467 #define GPDMA2_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS)
2468 
2469 /*!< AHB2 Non secure peripherals */
2470 #define GPIOA_NS               ((GPIO_TypeDef *) GPIOA_BASE_NS)
2471 #define GPIOB_NS               ((GPIO_TypeDef *) GPIOB_BASE_NS)
2472 #define GPIOC_NS               ((GPIO_TypeDef *) GPIOC_BASE_NS)
2473 #define GPIOD_NS               ((GPIO_TypeDef *) GPIOD_BASE_NS)
2474 #define GPIOE_NS               ((GPIO_TypeDef *) GPIOE_BASE_NS)
2475 #define GPIOF_NS               ((GPIO_TypeDef *) GPIOF_BASE_NS)
2476 #define GPIOG_NS               ((GPIO_TypeDef *) GPIOG_BASE_NS)
2477 #define GPIOH_NS               ((GPIO_TypeDef *) GPIOH_BASE_NS)
2478 #define GPIOI_NS               ((GPIO_TypeDef *) GPIOI_BASE_NS)
2479 #define ADC1_NS                ((ADC_TypeDef *) ADC1_BASE_NS)
2480 #define ADC2_NS                ((ADC_TypeDef *) ADC2_BASE_NS)
2481 #define ADC12_COMMON_NS        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
2482 #define DAC1_NS                ((DAC_TypeDef *) DAC1_BASE_NS)
2483 #define DCMI_NS                ((DCMI_TypeDef *) DCMI_BASE_NS)
2484 #define PSSI_NS                ((PSSI_TypeDef *) PSSI_BASE_NS)
2485 #define HASH_NS                ((HASH_TypeDef *) HASH_BASE_NS)
2486 #define HASH_DIGEST_NS         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
2487 #define AES_NS                 ((AES_TypeDef *) AES_BASE_NS)
2488 #define RNG_NS                 ((RNG_TypeDef *) RNG_BASE_NS)
2489 #define SAES_NS                ((AES_TypeDef *) SAES_BASE_NS)
2490 #define PKA_NS                 ((PKA_TypeDef *) PKA_BASE_NS)
2491 
2492 
2493 /*!< APB3 Non secure peripherals */
2494 #define SBS_NS                 ((SBS_TypeDef *) SBS_BASE_NS)
2495 #define SPI5_NS                ((SPI_TypeDef *) SPI5_BASE_NS)
2496 #define LPUART1_NS             ((USART_TypeDef *) LPUART1_BASE_NS)
2497 #define I2C3_NS                ((I2C_TypeDef *) I2C3_BASE_NS)
2498 #define I2C4_NS                ((I2C_TypeDef *) I2C4_BASE_NS)
2499 #define LPTIM1_NS              ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
2500 #define LPTIM3_NS              ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
2501 #define LPTIM4_NS              ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
2502 #define LPTIM5_NS              ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
2503 #define LPTIM6_NS              ((LPTIM_TypeDef *) LPTIM6_BASE_NS)
2504 #define VREFBUF_NS             ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
2505 #define RTC_NS                 ((RTC_TypeDef *) RTC_BASE_NS)
2506 #define TAMP_NS                ((TAMP_TypeDef *) TAMP_BASE_NS)
2507 
2508 /*!< AHB3 Non secure peripherals */
2509 #define PWR_NS                 ((PWR_TypeDef *) PWR_BASE_NS)
2510 #define RCC_NS                 ((RCC_TypeDef *) RCC_BASE_NS)
2511 #define EXTI_NS                ((EXTI_TypeDef *) EXTI_BASE_NS)
2512 
2513 /*!< AHB4 Non secure peripherals */
2514 #define OTFDEC1_NS             ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS)
2515 #define OTFDEC1_REGION1_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS)
2516 #define OTFDEC1_REGION2_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS)
2517 #define OTFDEC1_REGION3_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS)
2518 #define OTFDEC1_REGION4_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS)
2519 #define SDMMC1_NS              ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
2520 #define DLYB_SDMMC1_NS         ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
2521 #define SDMMC2_NS              ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
2522 #define DLYB_SDMMC2_NS         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
2523 
2524 #define OCTOSPI1_NS            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
2525 #define DLYB_OCTOSPI1_NS       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS)
2526 
2527 /*!< FMC Banks Non secure registers base address */
2528 #define FMC_Bank1_R_NS         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
2529 #define FMC_Bank1E_R_NS        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
2530 #define FMC_Bank3_R_NS         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
2531 #define FMC_Bank5_6_R_NS       ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
2532 
2533 /*!< APB1 Secure peripherals */
2534 #define TIM2_S                 ((TIM_TypeDef *)TIM2_BASE_S)
2535 #define TIM3_S                 ((TIM_TypeDef *)TIM3_BASE_S)
2536 #define TIM4_S                 ((TIM_TypeDef *)TIM4_BASE_S)
2537 #define TIM5_S                 ((TIM_TypeDef *)TIM5_BASE_S)
2538 #define TIM6_S                 ((TIM_TypeDef *)TIM6_BASE_S)
2539 #define TIM7_S                 ((TIM_TypeDef *)TIM7_BASE_S)
2540 #define TIM12_S                ((TIM_TypeDef *)TIM12_BASE_S)
2541 #define TIM13_S                ((TIM_TypeDef *)TIM13_BASE_S)
2542 #define TIM14_S                ((TIM_TypeDef *)TIM14_BASE_S)
2543 #define WWDG_S                 ((WWDG_TypeDef *)WWDG_BASE_S)
2544 #define IWDG_S                 ((IWDG_TypeDef *)IWDG_BASE_S)
2545 #define SPI2_S                 ((SPI_TypeDef *)SPI2_BASE_S)
2546 #define SPI3_S                 ((SPI_TypeDef *)SPI3_BASE_S)
2547 #define USART2_S               ((USART_TypeDef *)USART2_BASE_S)
2548 #define USART3_S               ((USART_TypeDef *)USART3_BASE_S)
2549 #define UART4_S                ((USART_TypeDef *)UART4_BASE_S)
2550 #define UART5_S                ((USART_TypeDef *)UART5_BASE_S)
2551 #define I2C1_S                 ((I2C_TypeDef *)I2C1_BASE_S)
2552 #define I2C2_S                 ((I2C_TypeDef *)I2C2_BASE_S)
2553 #define I3C1_S                 ((I3C_TypeDef *)I3C1_BASE_S)
2554 #define CRS_S                  ((CRS_TypeDef *)CRS_BASE_S)
2555 #define USART6_S               ((USART_TypeDef *)USART6_BASE_S)
2556 #define USART10_S              ((USART_TypeDef *)USART10_BASE_S)
2557 #define USART11_S              ((USART_TypeDef *)USART11_BASE_S)
2558 #define CEC_S                  ((CEC_TypeDef *)CEC_BASE_S)
2559 #define UART7_S                ((USART_TypeDef *)UART7_BASE_S)
2560 #define UART8_S                ((USART_TypeDef *)UART8_BASE_S)
2561 #define UART9_S                ((USART_TypeDef *)UART9_BASE_S)
2562 #define UART12_S               ((USART_TypeDef *)UART12_BASE_S)
2563 #define DTS_S                  ((DTS_TypeDef *)DTS_BASE_S)
2564 #define LPTIM2_S               ((LPTIM_TypeDef *)LPTIM2_BASE_S)
2565 #define FDCAN1_S               ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S)
2566 #define FDCAN_CONFIG_S         ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S)
2567 #define FDCAN2_S               ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S)
2568 #define UCPD1_S                ((UCPD_TypeDef *)UCPD1_BASE_S)
2569 
2570 /*!< APB2 secure peripherals */
2571 #define TIM1_S                 ((TIM_TypeDef *) TIM1_BASE_S)
2572 #define SPI1_S                 ((SPI_TypeDef *) SPI1_BASE_S)
2573 #define TIM8_S                 ((TIM_TypeDef *) TIM8_BASE_S)
2574 #define USART1_S               ((USART_TypeDef *) USART1_BASE_S)
2575 #define TIM15_S                ((TIM_TypeDef *) TIM15_BASE_S)
2576 #define TIM16_S                ((TIM_TypeDef *) TIM16_BASE_S)
2577 #define TIM17_S                ((TIM_TypeDef *) TIM17_BASE_S)
2578 #define SPI4_S                 ((SPI_TypeDef *) SPI4_BASE_S)
2579 #define SPI6_S                 ((SPI_TypeDef *) SPI6_BASE_S)
2580 #define SAI1_S                 ((SAI_TypeDef *) SAI1_BASE_S)
2581 #define SAI1_Block_A_S         ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
2582 #define SAI1_Block_B_S         ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
2583 #define SAI2_S                 ((SAI_TypeDef *) SAI2_BASE_S)
2584 #define SAI2_Block_A_S         ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
2585 #define SAI2_Block_B_S         ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
2586 #define USB_DRD_FS_S           ((USB_DRD_TypeDef *)USB_DRD_BASE_S)
2587 #define USB_DRD_PMA_BUFF_S     ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S)
2588 
2589 /*!< AHB1 secure peripherals */
2590 #define GPDMA1_S               ((DMA_TypeDef *) GPDMA1_BASE_S)
2591 #define GPDMA2_S               ((DMA_TypeDef *) GPDMA2_BASE_S)
2592 #define FLASH_S                ((FLASH_TypeDef *) FLASH_R_BASE_S)
2593 #define CRC_S                  ((CRC_TypeDef *) CRC_BASE_S)
2594 #define CORDIC_S               ((CORDIC_TypeDef *) CORDIC_BASE_S)
2595 #define FMAC_S                 ((FMAC_TypeDef *) FMAC_BASE_S)
2596 #define RAMCFG_SRAM1_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S)
2597 #define RAMCFG_SRAM2_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S)
2598 #define RAMCFG_SRAM3_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S)
2599 #define RAMCFG_BKPRAM_S        ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S)
2600 #define ETH_S                  ((ETH_TypeDef *) ETH_BASE_S)
2601 #define ETH_MAC_S              ((ETH_TypeDef *) ETH_MAC_BASE_S)
2602 #define ICACHE_S               ((ICACHE_TypeDef *) ICACHE_BASE_S)
2603 #define DCACHE1_S              ((DCACHE_TypeDef *) DCACHE1_BASE_S)
2604 #define GTZC_TZSC1_S           ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S)
2605 #define GTZC_TZIC1_S           ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S)
2606 #define GTZC_MPCBB1_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
2607 #define GTZC_MPCBB2_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
2608 #define GTZC_MPCBB3_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S)
2609 #define GPDMA1_Channel0_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
2610 #define GPDMA1_Channel1_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
2611 #define GPDMA1_Channel2_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
2612 #define GPDMA1_Channel3_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
2613 #define GPDMA1_Channel4_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
2614 #define GPDMA1_Channel5_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
2615 #define GPDMA1_Channel6_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
2616 #define GPDMA1_Channel7_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
2617 #define GPDMA2_Channel0_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S)
2618 #define GPDMA2_Channel1_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S)
2619 #define GPDMA2_Channel2_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S)
2620 #define GPDMA2_Channel3_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S)
2621 #define GPDMA2_Channel4_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S)
2622 #define GPDMA2_Channel5_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S)
2623 #define GPDMA2_Channel6_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S)
2624 #define GPDMA2_Channel7_S      ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S)
2625 
2626 
2627 /*!< AHB2 secure peripherals */
2628 #define GPIOA_S                ((GPIO_TypeDef *) GPIOA_BASE_S)
2629 #define GPIOB_S                ((GPIO_TypeDef *) GPIOB_BASE_S)
2630 #define GPIOC_S                ((GPIO_TypeDef *) GPIOC_BASE_S)
2631 #define GPIOD_S                ((GPIO_TypeDef *) GPIOD_BASE_S)
2632 #define GPIOE_S                ((GPIO_TypeDef *) GPIOE_BASE_S)
2633 #define GPIOF_S                ((GPIO_TypeDef *) GPIOF_BASE_S)
2634 #define GPIOG_S                ((GPIO_TypeDef *) GPIOG_BASE_S)
2635 #define GPIOH_S                ((GPIO_TypeDef *) GPIOH_BASE_S)
2636 #define GPIOI_S                ((GPIO_TypeDef *) GPIOI_BASE_S)
2637 #define ADC1_S                 ((ADC_TypeDef *) ADC1_BASE_S)
2638 #define ADC2_S                 ((ADC_TypeDef *) ADC2_BASE_S)
2639 #define ADC12_COMMON_S         ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
2640 #define DAC1_S                 ((DAC_TypeDef *) DAC1_BASE_S)
2641 #define DCMI_S                 ((DCMI_TypeDef *) DCMI_BASE_S)
2642 #define PSSI_S                 ((PSSI_TypeDef *) PSSI_BASE_S)
2643 #define HASH_S                 ((HASH_TypeDef *) HASH_BASE_S)
2644 #define HASH_DIGEST_S          ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
2645 #define AES_S                  ((AES_TypeDef *) AES_BASE_S)
2646 #define RNG_S                  ((RNG_TypeDef *) RNG_BASE_S)
2647 #define SAES_S                 ((AES_TypeDef *) SAES_BASE_S)
2648 #define PKA_S                  ((PKA_TypeDef *) PKA_BASE_S)
2649 
2650 /*!< APB3 secure peripherals */
2651 #define SBS_S                  ((SBS_TypeDef *) SBS_BASE_S)
2652 #define SPI5_S                 ((SPI_TypeDef *) SPI5_BASE_S)
2653 #define LPUART1_S              ((USART_TypeDef *) LPUART1_BASE_S)
2654 #define I2C3_S                 ((I2C_TypeDef *) I2C3_BASE_S)
2655 #define I2C4_S                 ((I2C_TypeDef *) I2C4_BASE_S)
2656 #define LPTIM1_S               ((LPTIM_TypeDef *) LPTIM1_BASE_S)
2657 #define LPTIM3_S               ((LPTIM_TypeDef *) LPTIM3_BASE_S)
2658 #define LPTIM4_S               ((LPTIM_TypeDef *) LPTIM4_BASE_S)
2659 #define LPTIM5_S               ((LPTIM_TypeDef *) LPTIM5_BASE_S)
2660 #define LPTIM6_S               ((LPTIM_TypeDef *) LPTIM6_BASE_S)
2661 #define VREFBUF_S              ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
2662 #define RTC_S                  ((RTC_TypeDef *) RTC_BASE_S)
2663 #define TAMP_S                 ((TAMP_TypeDef *) TAMP_BASE_S)
2664 
2665 /*!< AHB3 Secure peripherals */
2666 #define PWR_S                  ((PWR_TypeDef *) PWR_BASE_S)
2667 #define RCC_S                  ((RCC_TypeDef *) RCC_BASE_S)
2668 #define EXTI_S                 ((EXTI_TypeDef *) EXTI_BASE_S)
2669 
2670 /*!< AHB4 secure peripherals */
2671 #define OTFDEC1_S              ((OTFDEC_TypeDef *) OTFDEC1_BASE_S)
2672 #define OTFDEC1_REGION1_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S)
2673 #define OTFDEC1_REGION2_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S)
2674 #define OTFDEC1_REGION3_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S)
2675 #define OTFDEC1_REGION4_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S)
2676 #define SDMMC1_S               ((SDMMC_TypeDef *) SDMMC1_BASE_S)
2677 #define DLYB_SDMMC1_S          ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
2678 #define SDMMC2_S               ((SDMMC_TypeDef *) SDMMC2_BASE_S)
2679 #define DLYB_SDMMC2_S          ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
2680 
2681 #define FMC_Bank1_R_S          ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
2682 #define FMC_Bank1E_R_S         ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
2683 #define FMC_Bank3_R_S          ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
2684 #define FMC_Bank5_6_R_S        ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
2685 
2686 #define OCTOSPI1_S             ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
2687 #define DLYB_OCTOSPI1_S        ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S)
2688 
2689 #define DBGMCU                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
2690 
2691 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
2692 
2693 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2694 
2695 /*!< Memory base addresses for Secure peripherals */
2696 #define FLASH_BASE                     FLASH_BASE_S
2697 #define FLASH_OBK_BASE                 FLASH_OBK_BASE_S
2698 #define FLASH_EDATA_BASE               FLASH_EDATA_BASE_S
2699 #define FLASH_SYSTEM_BASE              FLASH_SYSTEM_BASE_S
2700 #define SRAM1_BASE                     SRAM1_BASE_S
2701 #define SRAM2_BASE                     SRAM2_BASE_S
2702 #define SRAM3_BASE                     SRAM3_BASE_S
2703 #define BKPSRAM_BASE                   BKPSRAM_BASE_S
2704 #define PERIPH_BASE                    PERIPH_BASE_S
2705 #define APB1PERIPH_BASE                APB1PERIPH_BASE_S
2706 #define APB2PERIPH_BASE                APB2PERIPH_BASE_S
2707 #define APB3PERIPH_BASE                APB3PERIPH_BASE_S
2708 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_S
2709 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_S
2710 #define AHB3PERIPH_BASE                AHB3PERIPH_BASE_S
2711 #define AHB4PERIPH_BASE                AHB4PERIPH_BASE_S
2712 
2713 /*!< Instance aliases and base addresses for Secure peripherals */
2714 #define CORDIC                         CORDIC_S
2715 #define CORDIC_BASE                    CORDIC_BASE_S
2716 
2717 #define RCC                            RCC_S
2718 #define RCC_BASE                       RCC_BASE_S
2719 
2720 #define DCMI                           DCMI_S
2721 #define DCMI_BASE                      DCMI_BASE_S
2722 
2723 #define PSSI                           PSSI_S
2724 #define PSSI_BASE                      PSSI_BASE_S
2725 
2726 #define DTS                            DTS_S
2727 #define DTS_BASE                       DTS_BASE_S
2728 
2729 #define FLASH                          FLASH_S
2730 #define FLASH_R_BASE                   FLASH_R_BASE_S
2731 
2732 #define FMAC                           FMAC_S
2733 #define FMAC_BASE                      FMAC_BASE_S
2734 
2735 #define GPDMA1                         GPDMA1_S
2736 #define GPDMA1_BASE                    GPDMA1_BASE_S
2737 
2738 #define GPDMA1_Channel0                GPDMA1_Channel0_S
2739 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_S
2740 
2741 #define GPDMA1_Channel1                GPDMA1_Channel1_S
2742 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_S
2743 
2744 #define GPDMA1_Channel2                GPDMA1_Channel2_S
2745 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_S
2746 
2747 #define GPDMA1_Channel3                GPDMA1_Channel3_S
2748 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_S
2749 
2750 #define GPDMA1_Channel4                GPDMA1_Channel4_S
2751 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_S
2752 
2753 #define GPDMA1_Channel5                GPDMA1_Channel5_S
2754 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_S
2755 
2756 #define GPDMA1_Channel6                GPDMA1_Channel6_S
2757 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_S
2758 
2759 #define GPDMA1_Channel7                GPDMA1_Channel7_S
2760 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_S
2761 
2762 #define GPDMA2                         GPDMA2_S
2763 #define GPDMA2_BASE                    GPDMA2_BASE_S
2764 
2765 #define GPDMA2_Channel0                GPDMA2_Channel0_S
2766 #define GPDMA2_Channel0_BASE           GPDMA2_Channel0_BASE_S
2767 
2768 #define GPDMA2_Channel1                GPDMA2_Channel1_S
2769 #define GPDMA2_Channel1_BASE           GPDMA2_Channel1_BASE_S
2770 
2771 #define GPDMA2_Channel2                GPDMA2_Channel2_S
2772 #define GPDMA2_Channel2_BASE           GPDMA2_Channel2_BASE_S
2773 
2774 #define GPDMA2_Channel3                GPDMA2_Channel3_S
2775 #define GPDMA2_Channel3_BASE           GPDMA2_Channel3_BASE_S
2776 
2777 #define GPDMA2_Channel4                GPDMA2_Channel4_S
2778 #define GPDMA2_Channel4_BASE           GPDMA2_Channel4_BASE_S
2779 
2780 #define GPDMA2_Channel5                GPDMA2_Channel5_S
2781 #define GPDMA2_Channel5_BASE           GPDMA2_Channel5_BASE_S
2782 
2783 #define GPDMA2_Channel6                GPDMA2_Channel6_S
2784 #define GPDMA2_Channel6_BASE           GPDMA2_Channel6_BASE_S
2785 
2786 #define GPDMA2_Channel7                GPDMA2_Channel7_S
2787 #define GPDMA2_Channel7_BASE           GPDMA2_Channel7_BASE_S
2788 
2789 #define GPIOA                          GPIOA_S
2790 #define GPIOA_BASE                     GPIOA_BASE_S
2791 
2792 #define GPIOB                          GPIOB_S
2793 #define GPIOB_BASE                     GPIOB_BASE_S
2794 
2795 #define GPIOC                          GPIOC_S
2796 #define GPIOC_BASE                     GPIOC_BASE_S
2797 
2798 #define GPIOD                          GPIOD_S
2799 #define GPIOD_BASE                     GPIOD_BASE_S
2800 
2801 #define GPIOE                          GPIOE_S
2802 #define GPIOE_BASE                     GPIOE_BASE_S
2803 
2804 #define GPIOF                          GPIOF_S
2805 #define GPIOF_BASE                     GPIOF_BASE_S
2806 
2807 #define GPIOG                          GPIOG_S
2808 #define GPIOG_BASE                     GPIOG_BASE_S
2809 
2810 #define GPIOH                          GPIOH_S
2811 #define GPIOH_BASE                     GPIOH_BASE_S
2812 
2813 #define GPIOI                          GPIOI_S
2814 #define GPIOI_BASE                     GPIOI_BASE_S
2815 
2816 #define PWR                            PWR_S
2817 #define PWR_BASE                       PWR_BASE_S
2818 
2819 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_S
2820 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_S
2821 
2822 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_S
2823 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_S
2824 
2825 #define RAMCFG_SRAM3                   RAMCFG_SRAM3_S
2826 #define RAMCFG_SRAM3_BASE              RAMCFG_SRAM3_BASE_S
2827 
2828 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_S
2829 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_S
2830 
2831 #define EXTI                           EXTI_S
2832 #define EXTI_BASE                      EXTI_BASE_S
2833 
2834 #define ICACHE                         ICACHE_S
2835 #define ICACHE_BASE                    ICACHE_BASE_S
2836 
2837 #define DCACHE1                        DCACHE1_S
2838 #define DCACHE1_BASE                   DCACHE1_BASE_S
2839 
2840 #define GTZC_TZSC1                     GTZC_TZSC1_S
2841 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_S
2842 
2843 #define GTZC_TZIC1                     GTZC_TZIC1_S
2844 #define GTZC_TZIC1_BASE                GTZC_TZIC1_BASE_S
2845 
2846 #define GTZC_MPCBB1                    GTZC_MPCBB1_S
2847 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_S
2848 
2849 #define GTZC_MPCBB2                    GTZC_MPCBB2_S
2850 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_S
2851 
2852 #define GTZC_MPCBB3                    GTZC_MPCBB3_S
2853 #define GTZC_MPCBB3_BASE               GTZC_MPCBB3_BASE_S
2854 
2855 #define RTC                            RTC_S
2856 #define RTC_BASE                       RTC_BASE_S
2857 
2858 #define TAMP                           TAMP_S
2859 #define TAMP_BASE                      TAMP_BASE_S
2860 
2861 #define TIM1                           TIM1_S
2862 #define TIM1_BASE                      TIM1_BASE_S
2863 
2864 #define TIM2                           TIM2_S
2865 #define TIM2_BASE                      TIM2_BASE_S
2866 
2867 #define TIM3                           TIM3_S
2868 #define TIM3_BASE                      TIM3_BASE_S
2869 
2870 #define TIM4                           TIM4_S
2871 #define TIM4_BASE                      TIM4_BASE_S
2872 
2873 #define TIM5                           TIM5_S
2874 #define TIM5_BASE                      TIM5_BASE_S
2875 
2876 #define TIM6                           TIM6_S
2877 #define TIM6_BASE                      TIM6_BASE_S
2878 
2879 #define TIM7                           TIM7_S
2880 #define TIM7_BASE                      TIM7_BASE_S
2881 
2882 #define TIM8                           TIM8_S
2883 #define TIM8_BASE                      TIM8_BASE_S
2884 
2885 #define TIM15                          TIM15_S
2886 #define TIM15_BASE                     TIM15_BASE_S
2887 
2888 #define TIM12                          TIM12_S
2889 #define TIM12_BASE                     TIM12_BASE_S
2890 
2891 #define TIM13                          TIM13_S
2892 #define TIM13_BASE                     TIM13_BASE_S
2893 
2894 #define TIM14                          TIM14_S
2895 #define TIM14_BASE                     TIM14_BASE_S
2896 
2897 #define TIM16                          TIM16_S
2898 #define TIM16_BASE                     TIM16_BASE_S
2899 
2900 #define TIM17                          TIM17_S
2901 #define TIM17_BASE                     TIM17_BASE_S
2902 
2903 #define WWDG                           WWDG_S
2904 #define WWDG_BASE                      WWDG_BASE_S
2905 
2906 #define IWDG                           IWDG_S
2907 #define IWDG_BASE                      IWDG_BASE_S
2908 
2909 #define SPI1                           SPI1_S
2910 #define SPI1_BASE                      SPI1_BASE_S
2911 
2912 #define SPI2                           SPI2_S
2913 #define SPI2_BASE                      SPI2_BASE_S
2914 
2915 #define SPI3                           SPI3_S
2916 #define SPI3_BASE                      SPI3_BASE_S
2917 
2918 #define SPI4                           SPI4_S
2919 #define SPI4_BASE                      SPI4_BASE_S
2920 
2921 #define SPI5                           SPI5_S
2922 #define SPI5_BASE                      SPI5_BASE_S
2923 
2924 #define SPI6                           SPI6_S
2925 #define SPI6_BASE                      SPI6_BASE_S
2926 
2927 #define USART1                         USART1_S
2928 #define USART1_BASE                    USART1_BASE_S
2929 
2930 #define USART2                         USART2_S
2931 #define USART2_BASE                    USART2_BASE_S
2932 
2933 #define USART3                         USART3_S
2934 #define USART3_BASE                    USART3_BASE_S
2935 
2936 #define UART4                          UART4_S
2937 #define UART4_BASE                     UART4_BASE_S
2938 
2939 #define UART5                          UART5_S
2940 #define UART5_BASE                     UART5_BASE_S
2941 
2942 #define USART6                         USART6_S
2943 #define USART6_BASE                    USART6_BASE_S
2944 
2945 #define UART7                          UART7_S
2946 #define UART7_BASE                     UART7_BASE_S
2947 
2948 #define UART8                          UART8_S
2949 #define UART8_BASE                     UART8_BASE_S
2950 
2951 #define UART9                          UART9_S
2952 #define UART9_BASE                     UART9_BASE_S
2953 
2954 #define USART10                        USART10_S
2955 #define USART10_BASE                   USART10_BASE_S
2956 
2957 #define USART11                        USART11_S
2958 #define USART11_BASE                   USART11_BASE_S
2959 
2960 #define UART12                         UART12_S
2961 #define UART12_BASE                    UART12_BASE_S
2962 
2963 #define CEC                            CEC_S
2964 #define CEC_BASE                       CEC_BASE_S
2965 
2966 #define I2C1                           I2C1_S
2967 #define I2C1_BASE                      I2C1_BASE_S
2968 
2969 #define I2C2                           I2C2_S
2970 #define I2C2_BASE                      I2C2_BASE_S
2971 
2972 #define I2C3                           I2C3_S
2973 #define I2C3_BASE                      I2C3_BASE_S
2974 
2975 #define I2C4                           I2C4_S
2976 #define I2C4_BASE                      I2C4_BASE_S
2977 
2978 #define I3C1                           I3C1_S
2979 #define I3C1_BASE                      I3C1_BASE_S
2980 
2981 #define CRS                            CRS_S
2982 #define CRS_BASE                       CRS_BASE_S
2983 
2984 #define FDCAN1                         FDCAN1_S
2985 #define FDCAN1_BASE                    FDCAN1_BASE_S
2986 
2987 #define FDCAN_CONFIG                   FDCAN_CONFIG_S
2988 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_S
2989 #define SRAMCAN_BASE                   SRAMCAN_BASE_S
2990 
2991 #define FDCAN2                         FDCAN2_S
2992 #define FDCAN2_BASE                    FDCAN2_BASE_S
2993 
2994 #define DAC                            DAC_S
2995 #define DAC_BASE                       DAC_BASE_S
2996 
2997 #define DAC1                           DAC1_S
2998 #define DAC1_BASE                      DAC1_BASE_S
2999 
3000 #define LPTIM1                         LPTIM1_S
3001 #define LPTIM1_BASE                    LPTIM1_BASE_S
3002 
3003 #define LPTIM2                         LPTIM2_S
3004 #define LPTIM2_BASE                    LPTIM2_BASE_S
3005 
3006 #define LPTIM3                         LPTIM3_S
3007 #define LPTIM3_BASE                    LPTIM3_BASE_S
3008 
3009 #define LPTIM4                         LPTIM4_S
3010 #define LPTIM4_BASE                    LPTIM4_BASE_S
3011 
3012 #define LPTIM5                         LPTIM5_S
3013 #define LPTIM5_BASE                    LPTIM5_BASE_S
3014 
3015 #define LPTIM6                         LPTIM6_S
3016 #define LPTIM6_BASE                    LPTIM6_BASE_S
3017 
3018 #define LPUART1                        LPUART1_S
3019 #define LPUART1_BASE                   LPUART1_BASE_S
3020 
3021 #define UCPD1                          UCPD1_S
3022 #define UCPD1_BASE                     UCPD1_BASE_S
3023 
3024 #define SBS                            SBS_S
3025 #define SBS_BASE                       SBS_BASE_S
3026 
3027 #define VREFBUF                        VREFBUF_S
3028 #define VREFBUF_BASE                   VREFBUF_BASE_S
3029 
3030 #define SAI1                           SAI1_S
3031 #define SAI1_BASE                      SAI1_BASE_S
3032 
3033 #define SAI1_Block_A                   SAI1_Block_A_S
3034 #define SAI1_Block_A_BASE              SAI1_Block_A_BASE_S
3035 
3036 #define SAI1_Block_B                   SAI1_Block_B_S
3037 #define SAI1_Block_B_BASE              SAI1_Block_B_BASE_S
3038 
3039 #define SAI2                           SAI2_S
3040 #define SAI2_BASE                      SAI2_BASE_S
3041 
3042 #define SAI2_Block_A                   SAI2_Block_A_S
3043 #define SAI2_Block_A_BASE              SAI2_Block_A_BASE_S
3044 
3045 #define SAI2_Block_B                   SAI2_Block_B_S
3046 #define SAI2_Block_B_BASE              SAI2_Block_B_BASE_S
3047 
3048 #define USB_DRD_FS                     USB_DRD_FS_S
3049 #define USB_DRD_BASE                   USB_DRD_BASE_S
3050 #define USB_DRD_PMAADDR                USB_DRD_PMAADDR_S
3051 #define USB_DRD_PMA_BUFF               USB_DRD_PMA_BUFF_S
3052 
3053 #define CRC                            CRC_S
3054 #define CRC_BASE                       CRC_BASE_S
3055 
3056 #define ADC1                           ADC1_S
3057 #define ADC1_BASE                      ADC1_BASE_S
3058 
3059 #define ADC2                           ADC2_S
3060 #define ADC2_BASE                      ADC2_BASE_S
3061 
3062 #define ADC12_COMMON                   ADC12_COMMON_S
3063 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_S
3064 
3065 #define HASH                           HASH_S
3066 #define HASH_BASE                      HASH_BASE_S
3067 
3068 #define HASH_DIGEST                    HASH_DIGEST_S
3069 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_S
3070 
3071 #define AES                            AES_S
3072 #define AES_BASE                       AES_BASE_S
3073 
3074 #define RNG                            RNG_S
3075 #define RNG_BASE                       RNG_BASE_S
3076 
3077 #define SAES                           SAES_S
3078 #define SAES_BASE                      SAES_BASE_S
3079 
3080 #define PKA                            PKA_S
3081 #define PKA_BASE                       PKA_BASE_S
3082 #define PKA_RAM_BASE                   PKA_RAM_BASE_S
3083 
3084 #define OTFDEC1                        OTFDEC1_S
3085 #define OTFDEC1_BASE                   OTFDEC1_BASE_S
3086 
3087 #define OTFDEC1_REGION1                OTFDEC1_REGION1_S
3088 #define OTFDEC1_REGION1_BASE           OTFDEC1_REGION1_BASE_S
3089 
3090 #define OTFDEC1_REGION2                OTFDEC1_REGION2_S
3091 #define OTFDEC1_REGION2_BASE           OTFDEC1_REGION2_BASE_S
3092 
3093 #define OTFDEC1_REGION3                OTFDEC1_REGION3_S
3094 #define OTFDEC1_REGION3_BASE           OTFDEC1_REGION3_BASE_S
3095 
3096 #define OTFDEC1_REGION4                OTFDEC1_REGION4_S
3097 #define OTFDEC1_REGION4_BASE           OTFDEC1_REGION4_BASE_S
3098 
3099 
3100 #define ETH                            ETH_S
3101 #define ETH_BASE                       ETH_BASE_S
3102 #define ETH_MAC                        ETH_MAC_S
3103 #define ETH_MAC_BASE                   ETH_MAC_BASE_S
3104 
3105 #define SDMMC1                         SDMMC1_S
3106 #define SDMMC1_BASE                    SDMMC1_BASE_S
3107 
3108 #define SDMMC2                         SDMMC2_S
3109 #define SDMMC2_BASE                    SDMMC2_BASE_S
3110 
3111 #define FMC_Bank1_R                    FMC_Bank1_R_S
3112 #define FMC_Bank1_R_BASE               FMC_Bank1_R_BASE_S
3113 
3114 #define FMC_Bank1E_R                   FMC_Bank1E_R_S
3115 #define FMC_Bank1E_R_BASE              FMC_Bank1E_R_BASE_S
3116 
3117 #define FMC_Bank3_R                    FMC_Bank3_R_S
3118 #define FMC_Bank3_R_BASE               FMC_Bank3_R_BASE_S
3119 
3120 #define FMC_Bank5_6_R                  FMC_Bank5_6_R_S
3121 #define FMC_Bank5_6_R_BASE             FMC_Bank5_6_R_BASE_S
3122 
3123 #define OCTOSPI1                       OCTOSPI1_S
3124 #define OCTOSPI1_R_BASE                OCTOSPI1_R_BASE_S
3125 
3126 #define DLYB_SDMMC1                    DLYB_SDMMC1_S
3127 #define DLYB_SDMMC1_BASE               DLYB_SDMMC1_BASE_S
3128 
3129 #define DLYB_SDMMC2                    DLYB_SDMMC2_S
3130 #define DLYB_SDMMC2_BASE               DLYB_SDMMC2_BASE_S
3131 
3132 #define DLYB_OCTOSPI1                  DLYB_OCTOSPI1_S
3133 #define DLYB_OCTOSPI1_BASE             DLYB_OCTOSPI1_BASE_S
3134 
3135 #else
3136 
3137 /*!< Memory base addresses for Non secure peripherals */
3138 #define FLASH_BASE                     FLASH_BASE_NS
3139 #define FLASH_OBK_BASE                 FLASH_OBK_BASE_NS
3140 #define FLASH_EDATA_BASE               FLASH_EDATA_BASE_NS
3141 #define FLASH_SYSTEM_BASE              FLASH_SYSTEM_BASE_NS
3142 
3143 #define SRAM1_BASE                     SRAM1_BASE_NS
3144 #define SRAM2_BASE                     SRAM2_BASE_NS
3145 
3146 #define SRAM3_BASE                     SRAM3_BASE_NS
3147 #define BKPSRAM_BASE                   BKPSRAM_BASE_NS
3148 
3149 #define PERIPH_BASE                    PERIPH_BASE_NS
3150 #define APB1PERIPH_BASE                APB1PERIPH_BASE_NS
3151 #define APB2PERIPH_BASE                APB2PERIPH_BASE_NS
3152 #define APB3PERIPH_BASE                APB3PERIPH_BASE_NS
3153 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_NS
3154 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_NS
3155 #define AHB3PERIPH_BASE                AHB3PERIPH_BASE_NS
3156 #define AHB4PERIPH_BASE                AHB4PERIPH_BASE_NS
3157 
3158 /*!< Instance aliases and base addresses for Non secure peripherals */
3159 #define CORDIC                         CORDIC_NS
3160 #define CORDIC_BASE                    CORDIC_BASE_NS
3161 
3162 #define RCC                            RCC_NS
3163 #define RCC_BASE                       RCC_BASE_NS
3164 
3165 #define DCMI                           DCMI_NS
3166 #define DCMI_BASE                      DCMI_BASE_NS
3167 
3168 #define PSSI                           PSSI_NS
3169 #define PSSI_BASE                      PSSI_BASE_NS
3170 
3171 #define DTS                            DTS_NS
3172 #define DTS_BASE                       DTS_BASE_NS
3173 
3174 #define FLASH                          FLASH_NS
3175 #define FLASH_R_BASE                   FLASH_R_BASE_NS
3176 
3177 #define FMAC                           FMAC_NS
3178 #define FMAC_BASE                      FMAC_BASE_NS
3179 
3180 #define GPDMA1                         GPDMA1_NS
3181 #define GPDMA1_BASE                    GPDMA1_BASE_NS
3182 
3183 #define GPDMA1_Channel0                GPDMA1_Channel0_NS
3184 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_NS
3185 
3186 #define GPDMA1_Channel1                GPDMA1_Channel1_NS
3187 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_NS
3188 
3189 #define GPDMA1_Channel2                GPDMA1_Channel2_NS
3190 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_NS
3191 
3192 #define GPDMA1_Channel3                GPDMA1_Channel3_NS
3193 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_NS
3194 
3195 #define GPDMA1_Channel4                GPDMA1_Channel4_NS
3196 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_NS
3197 
3198 #define GPDMA1_Channel5                GPDMA1_Channel5_NS
3199 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_NS
3200 
3201 #define GPDMA1_Channel6                GPDMA1_Channel6_NS
3202 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_NS
3203 
3204 #define GPDMA1_Channel7                GPDMA1_Channel7_NS
3205 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_NS
3206 
3207 #define GPDMA2                         GPDMA2_NS
3208 #define GPDMA2_BASE                    GPDMA2_BASE_NS
3209 
3210 #define GPDMA2_Channel0                GPDMA2_Channel0_NS
3211 #define GPDMA2_Channel0_BASE           GPDMA2_Channel0_BASE_NS
3212 
3213 #define GPDMA2_Channel1                GPDMA2_Channel1_NS
3214 #define GPDMA2_Channel1_BASE           GPDMA2_Channel1_BASE_NS
3215 
3216 #define GPDMA2_Channel2                GPDMA2_Channel2_NS
3217 #define GPDMA2_Channel2_BASE           GPDMA2_Channel2_BASE_NS
3218 
3219 #define GPDMA2_Channel3                GPDMA2_Channel3_NS
3220 #define GPDMA2_Channel3_BASE           GPDMA2_Channel3_BASE_NS
3221 
3222 #define GPDMA2_Channel4                GPDMA2_Channel4_NS
3223 #define GPDMA2_Channel4_BASE           GPDMA2_Channel4_BASE_NS
3224 
3225 #define GPDMA2_Channel5                GPDMA2_Channel5_NS
3226 #define GPDMA2_Channel5_BASE           GPDMA2_Channel5_BASE_NS
3227 
3228 #define GPDMA2_Channel6                GPDMA2_Channel6_NS
3229 #define GPDMA2_Channel6_BASE           GPDMA2_Channel6_BASE_NS
3230 
3231 #define GPDMA2_Channel7                GPDMA2_Channel7_NS
3232 #define GPDMA2_Channel7_BASE           GPDMA2_Channel7_BASE_NS
3233 
3234 #define GPIOA                          GPIOA_NS
3235 #define GPIOA_BASE                     GPIOA_BASE_NS
3236 
3237 #define GPIOB                          GPIOB_NS
3238 #define GPIOB_BASE                     GPIOB_BASE_NS
3239 
3240 #define GPIOC                          GPIOC_NS
3241 #define GPIOC_BASE                     GPIOC_BASE_NS
3242 
3243 #define GPIOD                          GPIOD_NS
3244 #define GPIOD_BASE                     GPIOD_BASE_NS
3245 
3246 #define GPIOE                          GPIOE_NS
3247 #define GPIOE_BASE                     GPIOE_BASE_NS
3248 
3249 #define GPIOF                          GPIOF_NS
3250 #define GPIOF_BASE                     GPIOF_BASE_NS
3251 
3252 #define GPIOG                          GPIOG_NS
3253 #define GPIOG_BASE                     GPIOG_BASE_NS
3254 
3255 #define GPIOH                          GPIOH_NS
3256 #define GPIOH_BASE                     GPIOH_BASE_NS
3257 
3258 #define GPIOI                          GPIOI_NS
3259 #define GPIOI_BASE                     GPIOI_BASE_NS
3260 
3261 #define PWR                            PWR_NS
3262 #define PWR_BASE                       PWR_BASE_NS
3263 
3264 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_NS
3265 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_NS
3266 
3267 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_NS
3268 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_NS
3269 
3270 #define RAMCFG_SRAM3                   RAMCFG_SRAM3_NS
3271 #define RAMCFG_SRAM3_BASE              RAMCFG_SRAM3_BASE_NS
3272 
3273 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_NS
3274 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_NS
3275 
3276 #define EXTI                           EXTI_NS
3277 #define EXTI_BASE                      EXTI_BASE_NS
3278 
3279 #define ICACHE                         ICACHE_NS
3280 #define ICACHE_BASE                    ICACHE_BASE_NS
3281 
3282 #define DCACHE1                        DCACHE1_NS
3283 #define DCACHE1_BASE                   DCACHE1_BASE_NS
3284 
3285 #define GTZC_TZSC1                     GTZC_TZSC1_NS
3286 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_NS
3287 
3288 #define GTZC_TZIC1                     GTZC_TZIC1_NS
3289 #define GTZC_TZIC1_BASE                GTZC_TZIC1_BASE_NS
3290 
3291 #define GTZC_MPCBB1                    GTZC_MPCBB1_NS
3292 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_NS
3293 
3294 #define GTZC_MPCBB2                    GTZC_MPCBB2_NS
3295 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_NS
3296 
3297 #define GTZC_MPCBB3                    GTZC_MPCBB3_NS
3298 #define GTZC_MPCBB3_BASE               GTZC_MPCBB3_BASE_NS
3299 
3300 #define RTC                            RTC_NS
3301 #define RTC_BASE                       RTC_BASE_NS
3302 
3303 #define TAMP                           TAMP_NS
3304 #define TAMP_BASE                      TAMP_BASE_NS
3305 
3306 #define TIM1                           TIM1_NS
3307 #define TIM1_BASE                      TIM1_BASE_NS
3308 
3309 #define TIM2                           TIM2_NS
3310 #define TIM2_BASE                      TIM2_BASE_NS
3311 
3312 #define TIM3                           TIM3_NS
3313 #define TIM3_BASE                      TIM3_BASE_NS
3314 
3315 #define TIM4                           TIM4_NS
3316 #define TIM4_BASE                      TIM4_BASE_NS
3317 
3318 #define TIM5                           TIM5_NS
3319 #define TIM5_BASE                      TIM5_BASE_NS
3320 
3321 #define TIM6                           TIM6_NS
3322 #define TIM6_BASE                      TIM6_BASE_NS
3323 
3324 #define TIM7                           TIM7_NS
3325 #define TIM7_BASE                      TIM7_BASE_NS
3326 
3327 #define TIM8                           TIM8_NS
3328 #define TIM8_BASE                      TIM8_BASE_NS
3329 
3330 #define TIM12                          TIM12_NS
3331 #define TIM12_BASE                     TIM12_BASE_NS
3332 
3333 #define TIM13                          TIM13_NS
3334 #define TIM13_BASE                     TIM13_BASE_NS
3335 
3336 #define TIM14                          TIM14_NS
3337 #define TIM14_BASE                     TIM14_BASE_NS
3338 
3339 #define TIM15                          TIM15_NS
3340 #define TIM15_BASE                     TIM15_BASE_NS
3341 
3342 #define TIM16                          TIM16_NS
3343 #define TIM16_BASE                     TIM16_BASE_NS
3344 
3345 #define TIM17                          TIM17_NS
3346 #define TIM17_BASE                     TIM17_BASE_NS
3347 
3348 #define WWDG                           WWDG_NS
3349 #define WWDG_BASE                      WWDG_BASE_NS
3350 
3351 #define IWDG                           IWDG_NS
3352 #define IWDG_BASE                      IWDG_BASE_NS
3353 
3354 #define SPI1                           SPI1_NS
3355 #define SPI1_BASE                      SPI1_BASE_NS
3356 
3357 #define SPI2                           SPI2_NS
3358 #define SPI2_BASE                      SPI2_BASE_NS
3359 
3360 #define SPI3                           SPI3_NS
3361 #define SPI3_BASE                      SPI3_BASE_NS
3362 
3363 #define SPI4                           SPI4_NS
3364 #define SPI4_BASE                      SPI4_BASE_NS
3365 
3366 #define SPI5                           SPI5_NS
3367 #define SPI5_BASE                      SPI5_BASE_NS
3368 
3369 #define SPI6                           SPI6_NS
3370 #define SPI6_BASE                      SPI6_BASE_NS
3371 
3372 #define USART1                         USART1_NS
3373 #define USART1_BASE                    USART1_BASE_NS
3374 
3375 #define USART2                         USART2_NS
3376 #define USART2_BASE                    USART2_BASE_NS
3377 
3378 #define USART3                         USART3_NS
3379 #define USART3_BASE                    USART3_BASE_NS
3380 
3381 #define UART4                          UART4_NS
3382 #define UART4_BASE                     UART4_BASE_NS
3383 
3384 #define UART5                          UART5_NS
3385 #define UART5_BASE                     UART5_BASE_NS
3386 
3387 #define USART6                         USART6_NS
3388 #define USART6_BASE                    USART6_BASE_NS
3389 
3390 #define UART7                          UART7_NS
3391 #define UART7_BASE                     UART7_BASE_NS
3392 
3393 #define UART8                          UART8_NS
3394 #define UART8_BASE                     UART8_BASE_NS
3395 
3396 #define UART9                          UART9_NS
3397 #define UART9_BASE                     UART9_BASE_NS
3398 
3399 #define USART10                        USART10_NS
3400 #define USART10_BASE                   USART10_BASE_NS
3401 
3402 #define USART11                        USART11_NS
3403 #define USART11_BASE                   USART11_BASE_NS
3404 
3405 #define UART12                         UART12_NS
3406 #define UART12_BASE                    UART12_BASE_NS
3407 
3408 #define CEC                            CEC_NS
3409 #define CEC_BASE                       CEC_BASE_NS
3410 
3411 #define I2C1                           I2C1_NS
3412 #define I2C1_BASE                      I2C1_BASE_NS
3413 
3414 #define I2C2                           I2C2_NS
3415 #define I2C2_BASE                      I2C2_BASE_NS
3416 
3417 #define I2C3                           I2C3_NS
3418 #define I2C3_BASE                      I2C3_BASE_NS
3419 
3420 #define I2C4                           I2C4_NS
3421 #define I2C4_BASE                      I2C4_BASE_NS
3422 
3423 #define I3C1                           I3C1_NS
3424 #define I3C1_BASE                      I3C1_BASE_NS
3425 
3426 #define CRS                            CRS_NS
3427 #define CRS_BASE                       CRS_BASE_NS
3428 
3429 #define FDCAN1                         FDCAN1_NS
3430 #define FDCAN1_BASE                    FDCAN1_BASE_NS
3431 
3432 #define FDCAN_CONFIG                   FDCAN_CONFIG_NS
3433 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_NS
3434 #define SRAMCAN_BASE                   SRAMCAN_BASE_NS
3435 
3436 #define FDCAN2                         FDCAN2_NS
3437 #define FDCAN2_BASE                    FDCAN2_BASE_NS
3438 
3439 #define DAC                            DAC_NS
3440 #define DAC_BASE                       DAC_BASE_NS
3441 
3442 #define DAC1                           DAC1_NS
3443 #define DAC1_BASE                      DAC1_BASE_NS
3444 
3445 #define LPTIM1                         LPTIM1_NS
3446 #define LPTIM1_BASE                    LPTIM1_BASE_NS
3447 
3448 #define LPTIM2                         LPTIM2_NS
3449 #define LPTIM2_BASE                    LPTIM2_BASE_NS
3450 
3451 #define LPTIM3                         LPTIM3_NS
3452 #define LPTIM3_BASE                    LPTIM3_BASE_NS
3453 
3454 #define LPTIM4                         LPTIM4_NS
3455 #define LPTIM4_BASE                    LPTIM4_BASE_NS
3456 
3457 #define LPTIM5                         LPTIM5_NS
3458 #define LPTIM5_BASE                    LPTIM5_BASE_NS
3459 
3460 #define LPTIM6                         LPTIM6_NS
3461 #define LPTIM6_BASE                    LPTIM6_BASE_NS
3462 
3463 #define LPUART1                        LPUART1_NS
3464 #define LPUART1_BASE                   LPUART1_BASE_NS
3465 
3466 #define UCPD1                          UCPD1_NS
3467 #define UCPD1_BASE                     UCPD1_BASE_NS
3468 
3469 #define SBS                            SBS_NS
3470 #define SBS_BASE                       SBS_BASE_NS
3471 
3472 #define VREFBUF                        VREFBUF_NS
3473 #define VREFBUF_BASE                   VREFBUF_BASE_NS
3474 
3475 #define SAI1                           SAI1_NS
3476 #define SAI1_BASE                      SAI1_BASE_NS
3477 
3478 #define SAI1_Block_A                   SAI1_Block_A_NS
3479 #define SAI1_Block_A_BASE              SAI1_Block_A_BASE_NS
3480 
3481 #define SAI1_Block_B                   SAI1_Block_B_NS
3482 #define SAI1_Block_B_BASE              SAI1_Block_B_BASE_NS
3483 
3484 #define SAI2                           SAI2_NS
3485 #define SAI2_BASE                      SAI2_BASE_NS
3486 
3487 #define SAI2_Block_A                   SAI2_Block_A_NS
3488 #define SAI2_Block_A_BASE              SAI2_Block_A_BASE_NS
3489 
3490 #define SAI2_Block_B                   SAI2_Block_B_NS
3491 #define SAI2_Block_B_BASE              SAI2_Block_B_BASE_NS
3492 
3493 #define USB_DRD_FS                     USB_DRD_FS_NS
3494 #define USB_DRD_BASE                   USB_DRD_BASE_NS
3495 #define USB_DRD_PMAADDR                USB_DRD_PMAADDR_NS
3496 #define USB_DRD_PMA_BUFF               USB_DRD_PMA_BUFF_NS
3497 
3498 #define CRC                            CRC_NS
3499 #define CRC_BASE                       CRC_BASE_NS
3500 
3501 #define ADC1                           ADC1_NS
3502 #define ADC1_BASE                      ADC1_BASE_NS
3503 
3504 #define ADC2                           ADC2_NS
3505 #define ADC2_BASE                      ADC2_BASE_NS
3506 
3507 #define ADC12_COMMON                   ADC12_COMMON_NS
3508 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_NS
3509 
3510 #define HASH                           HASH_NS
3511 #define HASH_BASE                      HASH_BASE_NS
3512 
3513 #define HASH_DIGEST                    HASH_DIGEST_NS
3514 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_NS
3515 
3516 #define AES                            AES_NS
3517 #define AES_BASE                       AES_BASE_NS
3518 
3519 #define RNG                            RNG_NS
3520 #define RNG_BASE                       RNG_BASE_NS
3521 
3522 #define SAES                           SAES_NS
3523 #define SAES_BASE                      SAES_BASE_NS
3524 
3525 #define PKA                            PKA_NS
3526 #define PKA_BASE                       PKA_BASE_NS
3527 #define PKA_RAM_BASE                   PKA_RAM_BASE_NS
3528 
3529 #define OTFDEC1                        OTFDEC1_NS
3530 #define OTFDEC1_BASE                   OTFDEC1_BASE_NS
3531 
3532 #define OTFDEC1_REGION1                OTFDEC1_REGION1_NS
3533 #define OTFDEC1_REGION1_BASE           OTFDEC1_REGION1_BASE_NS
3534 
3535 #define OTFDEC1_REGION2                OTFDEC1_REGION2_NS
3536 #define OTFDEC1_REGION2_BASE           OTFDEC1_REGION2_BASE_NS
3537 
3538 #define OTFDEC1_REGION3                OTFDEC1_REGION3_NS
3539 #define OTFDEC1_REGION3_BASE           OTFDEC1_REGION3_BASE_NS
3540 
3541 #define OTFDEC1_REGION4                OTFDEC1_REGION4_NS
3542 #define OTFDEC1_REGION4_BASE           OTFDEC1_REGION4_BASE_NS
3543 
3544 
3545 #define ETH                            ETH_NS
3546 #define ETH_BASE                       ETH_BASE_NS
3547 #define ETH_MAC                        ETH_MAC_NS
3548 #define ETH_MAC_BASE                   ETH_MAC_BASE_NS
3549 
3550 #define SDMMC1                         SDMMC1_NS
3551 #define SDMMC1_BASE                    SDMMC1_BASE_NS
3552 
3553 #define SDMMC2                         SDMMC2_NS
3554 #define SDMMC2_BASE                    SDMMC2_BASE_NS
3555 
3556 #define FMC_Bank1_R                    FMC_Bank1_R_NS
3557 #define FMC_Bank1_R_BASE               FMC_Bank1_R_BASE_NS
3558 
3559 #define FMC_Bank1E_R                   FMC_Bank1E_R_NS
3560 #define FMC_Bank1E_R_BASE              FMC_Bank1E_R_BASE_NS
3561 
3562 #define FMC_Bank3_R                    FMC_Bank3_R_NS
3563 #define FMC_Bank3_R_BASE               FMC_Bank3_R_BASE_NS
3564 
3565 #define FMC_Bank5_6_R                  FMC_Bank5_6_R_NS
3566 #define FMC_Bank5_6_R_BASE             FMC_Bank5_6_R_BASE_NS
3567 
3568 #define OCTOSPI1                       OCTOSPI1_NS
3569 #define OCTOSPI1_R_BASE                OCTOSPI1_R_BASE_NS
3570 
3571 #define DLYB_SDMMC1                    DLYB_SDMMC1_NS
3572 #define DLYB_SDMMC1_BASE               DLYB_SDMMC1_BASE_NS
3573 
3574 #define DLYB_SDMMC2                    DLYB_SDMMC2_NS
3575 #define DLYB_SDMMC2_BASE               DLYB_SDMMC2_BASE_NS
3576 
3577 #define DLYB_OCTOSPI1                  DLYB_OCTOSPI1_NS
3578 #define DLYB_OCTOSPI1_BASE             DLYB_OCTOSPI1_BASE_NS
3579 
3580 #endif
3581 
3582 
3583 /******************************************************************************/
3584 /*                                                                            */
3585 /*                        Analog to Digital Converter                         */
3586 /*                                                                            */
3587 /******************************************************************************/
3588 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3589 /********************  Bit definition for ADC_ISR register  *******************/
3590 #define ADC_ISR_ADRDY_Pos              (0U)
3591 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
3592 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
3593 #define ADC_ISR_EOSMP_Pos              (1U)
3594 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
3595 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
3596 #define ADC_ISR_EOC_Pos                (2U)
3597 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
3598 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
3599 #define ADC_ISR_EOS_Pos                (3U)
3600 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
3601 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
3602 #define ADC_ISR_OVR_Pos                (4U)
3603 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
3604 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
3605 #define ADC_ISR_JEOC_Pos               (5U)
3606 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
3607 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
3608 #define ADC_ISR_JEOS_Pos               (6U)
3609 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
3610 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
3611 #define ADC_ISR_AWD1_Pos               (7U)
3612 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
3613 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
3614 #define ADC_ISR_AWD2_Pos               (8U)
3615 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
3616 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
3617 #define ADC_ISR_AWD3_Pos               (9U)
3618 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
3619 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
3620 #define ADC_ISR_JQOVF_Pos              (10U)
3621 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
3622 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
3623 
3624 /********************  Bit definition for ADC_IER register  *******************/
3625 #define ADC_IER_ADRDYIE_Pos            (0U)
3626 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
3627 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
3628 #define ADC_IER_EOSMPIE_Pos            (1U)
3629 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
3630 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
3631 #define ADC_IER_EOCIE_Pos              (2U)
3632 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
3633 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
3634 #define ADC_IER_EOSIE_Pos              (3U)
3635 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
3636 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
3637 #define ADC_IER_OVRIE_Pos              (4U)
3638 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
3639 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
3640 #define ADC_IER_JEOCIE_Pos             (5U)
3641 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
3642 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
3643 #define ADC_IER_JEOSIE_Pos             (6U)
3644 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
3645 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
3646 #define ADC_IER_AWD1IE_Pos             (7U)
3647 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
3648 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
3649 #define ADC_IER_AWD2IE_Pos             (8U)
3650 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
3651 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
3652 #define ADC_IER_AWD3IE_Pos             (9U)
3653 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
3654 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
3655 #define ADC_IER_JQOVFIE_Pos            (10U)
3656 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
3657 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
3658 
3659 /********************  Bit definition for ADC_CR register  ********************/
3660 #define ADC_CR_ADEN_Pos                (0U)
3661 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
3662 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
3663 #define ADC_CR_ADDIS_Pos               (1U)
3664 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
3665 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
3666 #define ADC_CR_ADSTART_Pos             (2U)
3667 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
3668 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
3669 #define ADC_CR_JADSTART_Pos            (3U)
3670 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
3671 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
3672 #define ADC_CR_ADSTP_Pos               (4U)
3673 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
3674 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
3675 #define ADC_CR_JADSTP_Pos              (5U)
3676 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
3677 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
3678 #define ADC_CR_ADVREGEN_Pos            (28U)
3679 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
3680 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
3681 #define ADC_CR_DEEPPWD_Pos             (29U)
3682 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
3683 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
3684 #define ADC_CR_ADCALDIF_Pos            (30U)
3685 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
3686 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
3687 #define ADC_CR_ADCAL_Pos               (31U)
3688 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
3689 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
3690 
3691 /********************  Bit definition for ADC_CFGR register  ******************/
3692 #define ADC_CFGR_DMAEN_Pos             (0U)
3693 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
3694 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
3695 #define ADC_CFGR_DMACFG_Pos            (1U)
3696 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
3697 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
3698 
3699 #define ADC_CFGR_ADFCFG_Pos            (2U)
3700 #define ADC_CFGR_ADFCFG_Msk            (0x1UL << ADC_CFGR_ADFCFG_Pos)          /*!< 0x00000004 */
3701 #define ADC_CFGR_ADFCFG                ADC_CFGR_ADFCFG_Msk                     /*!< ADC ADF transfer configuration */
3702 
3703 #define ADC_CFGR_RES_Pos               (3U)
3704 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
3705 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
3706 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
3707 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
3708 
3709 #define ADC_CFGR_EXTSEL_Pos            (5U)
3710 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
3711 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
3712 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
3713 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
3714 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
3715 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
3716 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
3717 
3718 #define ADC_CFGR_EXTEN_Pos             (10U)
3719 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
3720 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
3721 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
3722 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
3723 
3724 #define ADC_CFGR_OVRMOD_Pos            (12U)
3725 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
3726 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
3727 #define ADC_CFGR_CONT_Pos              (13U)
3728 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
3729 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
3730 #define ADC_CFGR_AUTDLY_Pos            (14U)
3731 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
3732 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
3733 #define ADC_CFGR_ALIGN_Pos             (15U)
3734 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
3735 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
3736 #define ADC_CFGR_DISCEN_Pos            (16U)
3737 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
3738 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
3739 
3740 #define ADC_CFGR_DISCNUM_Pos           (17U)
3741 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
3742 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
3743 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
3744 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
3745 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
3746 
3747 #define ADC_CFGR_JDISCEN_Pos           (20U)
3748 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
3749 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
3750 #define ADC_CFGR_JQM_Pos               (21U)
3751 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
3752 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
3753 #define ADC_CFGR_AWD1SGL_Pos           (22U)
3754 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
3755 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3756 #define ADC_CFGR_AWD1EN_Pos            (23U)
3757 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
3758 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3759 #define ADC_CFGR_JAWD1EN_Pos           (24U)
3760 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
3761 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3762 #define ADC_CFGR_JAUTO_Pos             (25U)
3763 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
3764 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
3765 
3766 #define ADC_CFGR_AWD1CH_Pos            (26U)
3767 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
3768 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
3769 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
3770 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
3771 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
3772 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
3773 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
3774 
3775 #define ADC_CFGR_JQDIS_Pos             (31U)
3776 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
3777 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
3778 
3779 /********************  Bit definition for ADC_CFGR2 register  *****************/
3780 #define ADC_CFGR2_ROVSE_Pos            (0U)
3781 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
3782 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
3783 #define ADC_CFGR2_JOVSE_Pos            (1U)
3784 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
3785 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
3786 
3787 #define ADC_CFGR2_OVSR_Pos             (2U)
3788 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
3789 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
3790 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
3791 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
3792 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
3793 
3794 #define ADC_CFGR2_OVSS_Pos             (5U)
3795 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
3796 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
3797 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
3798 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
3799 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
3800 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
3801 
3802 #define ADC_CFGR2_TROVS_Pos            (9U)
3803 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
3804 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
3805 #define ADC_CFGR2_ROVSM_Pos            (10U)
3806 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
3807 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
3808 
3809 #define ADC_CFGR2_GCOMP_Pos            (16U)
3810 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
3811 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
3812 
3813 #define ADC_CFGR2_SWTRIG_Pos           (25U)
3814 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
3815 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
3816 #define ADC_CFGR2_BULB_Pos             (26U)
3817 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
3818 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
3819 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
3820 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
3821 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
3822 
3823 #define ADC_CFGR2_LFTRIG_Pos           (29U)
3824 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
3825 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC Low Frequency Trigger */
3826 
3827 /********************  Bit definition for ADC_SMPR1 register  *****************/
3828 #define ADC_SMPR1_SMP0_Pos             (0U)
3829 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
3830 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
3831 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
3832 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
3833 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
3834 
3835 #define ADC_SMPR1_SMP1_Pos             (3U)
3836 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
3837 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
3838 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
3839 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
3840 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
3841 
3842 #define ADC_SMPR1_SMP2_Pos             (6U)
3843 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
3844 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
3845 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
3846 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
3847 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
3848 
3849 #define ADC_SMPR1_SMP3_Pos             (9U)
3850 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
3851 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
3852 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
3853 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
3854 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
3855 
3856 #define ADC_SMPR1_SMP4_Pos             (12U)
3857 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
3858 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
3859 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
3860 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
3861 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
3862 
3863 #define ADC_SMPR1_SMP5_Pos             (15U)
3864 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
3865 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
3866 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
3867 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
3868 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
3869 
3870 #define ADC_SMPR1_SMP6_Pos             (18U)
3871 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
3872 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
3873 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
3874 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
3875 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
3876 
3877 #define ADC_SMPR1_SMP7_Pos             (21U)
3878 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
3879 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
3880 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
3881 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
3882 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
3883 
3884 #define ADC_SMPR1_SMP8_Pos             (24U)
3885 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
3886 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
3887 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
3888 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
3889 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
3890 
3891 #define ADC_SMPR1_SMP9_Pos             (27U)
3892 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
3893 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
3894 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
3895 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
3896 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
3897 
3898 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
3899 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
3900 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
3901 
3902 /********************  Bit definition for ADC_SMPR2 register  *****************/
3903 #define ADC_SMPR2_SMP10_Pos            (0U)
3904 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
3905 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
3906 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
3907 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
3908 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
3909 
3910 #define ADC_SMPR2_SMP11_Pos            (3U)
3911 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
3912 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
3913 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
3914 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
3915 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
3916 
3917 #define ADC_SMPR2_SMP12_Pos            (6U)
3918 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
3919 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
3920 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
3921 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
3922 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
3923 
3924 #define ADC_SMPR2_SMP13_Pos            (9U)
3925 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
3926 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
3927 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
3928 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
3929 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
3930 
3931 #define ADC_SMPR2_SMP14_Pos            (12U)
3932 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
3933 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
3934 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
3935 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
3936 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
3937 
3938 #define ADC_SMPR2_SMP15_Pos            (15U)
3939 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
3940 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
3941 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
3942 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
3943 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
3944 
3945 #define ADC_SMPR2_SMP16_Pos            (18U)
3946 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
3947 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
3948 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
3949 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
3950 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
3951 
3952 #define ADC_SMPR2_SMP17_Pos            (21U)
3953 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
3954 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
3955 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
3956 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
3957 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
3958 
3959 #define ADC_SMPR2_SMP18_Pos            (24U)
3960 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
3961 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
3962 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
3963 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
3964 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
3965 
3966 /********************  Bit definition for ADC_TR1 register  *******************/
3967 #define ADC_TR1_LT1_Pos                (0U)
3968 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
3969 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
3970 
3971 #define ADC_TR1_AWDFILT_Pos            (12U)
3972 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
3973 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
3974 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
3975 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
3976 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
3977 
3978 #define ADC_TR1_HT1_Pos                (16U)
3979 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
3980 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
3981 
3982 /********************  Bit definition for ADC_TR2 register  *******************/
3983 #define ADC_TR2_LT2_Pos                (0U)
3984 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
3985 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
3986 
3987 #define ADC_TR2_HT2_Pos                (16U)
3988 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
3989 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
3990 
3991 /********************  Bit definition for ADC_TR3 register  *******************/
3992 #define ADC_TR3_LT3_Pos                (0U)
3993 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
3994 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
3995 
3996 #define ADC_TR3_HT3_Pos                (16U)
3997 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
3998 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
3999 
4000 /********************  Bit definition for ADC_SQR1 register  ******************/
4001 #define ADC_SQR1_L_Pos                 (0U)
4002 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
4003 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
4004 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
4005 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
4006 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
4007 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
4008 
4009 #define ADC_SQR1_SQ1_Pos               (6U)
4010 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
4011 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
4012 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
4013 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
4014 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
4015 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
4016 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
4017 
4018 #define ADC_SQR1_SQ2_Pos               (12U)
4019 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
4020 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
4021 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
4022 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
4023 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
4024 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
4025 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
4026 
4027 #define ADC_SQR1_SQ3_Pos               (18U)
4028 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
4029 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
4030 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
4031 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
4032 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
4033 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
4034 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
4035 
4036 #define ADC_SQR1_SQ4_Pos               (24U)
4037 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
4038 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
4039 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
4040 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
4041 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
4042 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
4043 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
4044 
4045 /********************  Bit definition for ADC_SQR2 register  ******************/
4046 #define ADC_SQR2_SQ5_Pos               (0U)
4047 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
4048 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
4049 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
4050 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
4051 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
4052 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
4053 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
4054 
4055 #define ADC_SQR2_SQ6_Pos               (6U)
4056 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
4057 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
4058 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
4059 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
4060 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
4061 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
4062 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
4063 
4064 #define ADC_SQR2_SQ7_Pos               (12U)
4065 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
4066 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
4067 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
4068 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
4069 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
4070 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
4071 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
4072 
4073 #define ADC_SQR2_SQ8_Pos               (18U)
4074 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
4075 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
4076 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
4077 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
4078 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
4079 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
4080 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
4081 
4082 #define ADC_SQR2_SQ9_Pos               (24U)
4083 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
4084 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
4085 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
4086 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
4087 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
4088 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
4089 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
4090 
4091 /********************  Bit definition for ADC_SQR3 register  ******************/
4092 #define ADC_SQR3_SQ10_Pos              (0U)
4093 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
4094 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
4095 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
4096 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
4097 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
4098 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
4099 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
4100 
4101 #define ADC_SQR3_SQ11_Pos              (6U)
4102 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
4103 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
4104 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
4105 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
4106 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
4107 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
4108 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
4109 
4110 #define ADC_SQR3_SQ12_Pos              (12U)
4111 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
4112 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
4113 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
4114 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
4115 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
4116 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
4117 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
4118 
4119 #define ADC_SQR3_SQ13_Pos              (18U)
4120 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
4121 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
4122 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
4123 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
4124 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
4125 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
4126 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
4127 
4128 #define ADC_SQR3_SQ14_Pos              (24U)
4129 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
4130 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
4131 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
4132 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
4133 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
4134 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
4135 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
4136 
4137 /********************  Bit definition for ADC_SQR4 register  ******************/
4138 #define ADC_SQR4_SQ15_Pos              (0U)
4139 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
4140 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
4141 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
4142 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
4143 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
4144 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
4145 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
4146 
4147 #define ADC_SQR4_SQ16_Pos              (6U)
4148 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
4149 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
4150 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
4151 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
4152 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
4153 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
4154 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
4155 
4156 /********************  Bit definition for ADC_DR register  ********************/
4157 #define ADC_DR_RDATA_Pos               (0U)
4158 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
4159 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
4160 
4161 /********************  Bit definition for ADC_JSQR register  ******************/
4162 #define ADC_JSQR_JL_Pos                (0U)
4163 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
4164 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
4165 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
4166 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
4167 
4168 #define ADC_JSQR_JEXTSEL_Pos           (2U)
4169 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
4170 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
4171 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
4172 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
4173 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
4174 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
4175 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
4176 
4177 #define ADC_JSQR_JEXTEN_Pos            (7U)
4178 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
4179 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
4180 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
4181 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
4182 
4183 #define ADC_JSQR_JSQ1_Pos              (9U)
4184 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
4185 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
4186 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
4187 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
4188 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
4189 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
4190 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
4191 
4192 #define ADC_JSQR_JSQ2_Pos              (15U)
4193 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
4194 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
4195 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
4196 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
4197 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
4198 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
4199 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
4200 
4201 #define ADC_JSQR_JSQ3_Pos              (21U)
4202 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
4203 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
4204 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
4205 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
4206 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
4207 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
4208 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
4209 
4210 #define ADC_JSQR_JSQ4_Pos              (27U)
4211 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
4212 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
4213 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
4214 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
4215 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
4216 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
4217 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
4218 
4219 /********************  Bit definition for ADC_OFR1 register  ******************/
4220 #define ADC_OFR1_OFFSET1_Pos           (0U)
4221 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
4222 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
4223 
4224 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
4225 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
4226 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
4227 #define ADC_OFR1_SATEN_Pos             (25U)
4228 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
4229 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
4230 
4231 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
4232 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
4233 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
4234 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
4235 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
4236 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
4237 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
4238 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
4239 
4240 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
4241 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
4242 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
4243 
4244 /********************  Bit definition for ADC_OFR2 register  ******************/
4245 #define ADC_OFR2_OFFSET2_Pos           (0U)
4246 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
4247 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
4248 
4249 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
4250 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
4251 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
4252 #define ADC_OFR2_SATEN_Pos             (25U)
4253 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
4254 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
4255 
4256 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
4257 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
4258 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
4259 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
4260 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
4261 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
4262 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
4263 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
4264 
4265 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
4266 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
4267 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
4268 
4269 /********************  Bit definition for ADC_OFR3 register  ******************/
4270 #define ADC_OFR3_OFFSET3_Pos           (0U)
4271 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
4272 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
4273 
4274 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
4275 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
4276 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
4277 #define ADC_OFR3_SATEN_Pos             (25U)
4278 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
4279 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
4280 
4281 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
4282 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
4283 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
4284 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
4285 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
4286 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
4287 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
4288 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
4289 
4290 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
4291 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
4292 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
4293 
4294 /********************  Bit definition for ADC_OFR4 register  ******************/
4295 #define ADC_OFR4_OFFSET4_Pos           (0U)
4296 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
4297 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
4298 
4299 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
4300 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
4301 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
4302 #define ADC_OFR4_SATEN_Pos             (25U)
4303 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
4304 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
4305 
4306 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
4307 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
4308 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
4309 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
4310 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
4311 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
4312 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
4313 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
4314 
4315 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
4316 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
4317 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
4318 
4319 /********************  Bit definition for ADC_JDR1 register  ******************/
4320 #define ADC_JDR1_JDATA_Pos             (0U)
4321 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
4322 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
4323 
4324 /********************  Bit definition for ADC_JDR2 register  ******************/
4325 #define ADC_JDR2_JDATA_Pos             (0U)
4326 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
4327 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
4328 
4329 /********************  Bit definition for ADC_JDR3 register  ******************/
4330 #define ADC_JDR3_JDATA_Pos             (0U)
4331 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
4332 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
4333 
4334 /********************  Bit definition for ADC_JDR4 register  ******************/
4335 #define ADC_JDR4_JDATA_Pos             (0U)
4336 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
4337 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
4338 
4339 /********************  Bit definition for ADC_AWD2CR register  ****************/
4340 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
4341 #define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
4342 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
4343 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
4344 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
4345 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
4346 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
4347 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
4348 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
4349 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
4350 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
4351 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
4352 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
4353 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
4354 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
4355 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
4356 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
4357 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
4358 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
4359 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
4360 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
4361 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
4362 #define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
4363 
4364 /********************  Bit definition for ADC_AWD3CR register  ****************/
4365 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
4366 #define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
4367 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
4368 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
4369 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
4370 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
4371 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
4372 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
4373 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
4374 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
4375 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
4376 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
4377 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
4378 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
4379 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
4380 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
4381 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
4382 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
4383 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
4384 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
4385 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
4386 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
4387 #define ADC_AWD3CR_AWD2CH_19           (0x80000UL << ADC_AWD3CR_AWD2CH_Pos)    /*!< 0x00080000 */
4388 
4389 /********************  Bit definition for ADC_DIFSEL register  ****************/
4390 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
4391 #define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
4392 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
4393 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
4394 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
4395 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
4396 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
4397 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
4398 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
4399 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
4400 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
4401 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
4402 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
4403 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
4404 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
4405 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
4406 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
4407 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
4408 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
4409 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
4410 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
4411 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
4412 #define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
4413 
4414 /********************  Bit definition for ADC_CALFACT register  ***************/
4415 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
4416 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
4417 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
4418 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
4419 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
4420 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
4421 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
4422 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
4423 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
4424 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
4425 
4426 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
4427 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
4428 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
4429 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
4430 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
4431 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
4432 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
4433 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
4434 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
4435 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
4436 
4437 /********************  Bit definition for ADC_OR register  *****************/
4438 #define ADC_OR_OP0_Pos       (0U)
4439 #define ADC_OR_OP0_Msk       (0x01UL << ADC_OR_OP0_Pos)                        /*!< 0x00000001 */
4440 #define ADC_OR_OP0           ADC_OR_OP0_Msk                                    /*!< ADC Option bit 0 */
4441 #define ADC_OR_OP1_Pos       (1U)
4442 #define ADC_OR_OP1_Msk       (0x01UL << ADC_OR_OP1_Pos)                        /*!< 0x00000001 */
4443 #define ADC_OR_OP1           ADC_OR_OP1_Msk                                    /*!< ADC Option bit 1 */
4444 
4445 /*************************  ADC Common registers  *****************************/
4446 /********************  Bit definition for ADC_CSR register  *******************/
4447 #define ADC_CSR_ADRDY_MST_Pos          (0U)
4448 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
4449 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
4450 #define ADC_CSR_EOSMP_MST_Pos          (1U)
4451 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
4452 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
4453 #define ADC_CSR_EOC_MST_Pos            (2U)
4454 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
4455 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
4456 #define ADC_CSR_EOS_MST_Pos            (3U)
4457 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
4458 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
4459 #define ADC_CSR_OVR_MST_Pos            (4U)
4460 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
4461 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
4462 #define ADC_CSR_JEOC_MST_Pos           (5U)
4463 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
4464 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
4465 #define ADC_CSR_JEOS_MST_Pos           (6U)
4466 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
4467 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
4468 #define ADC_CSR_AWD1_MST_Pos           (7U)
4469 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
4470 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
4471 #define ADC_CSR_AWD2_MST_Pos           (8U)
4472 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
4473 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
4474 #define ADC_CSR_AWD3_MST_Pos           (9U)
4475 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
4476 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
4477 #define ADC_CSR_JQOVF_MST_Pos          (10U)
4478 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
4479 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
4480 
4481 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
4482 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
4483 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
4484 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
4485 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
4486 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
4487 #define ADC_CSR_EOC_SLV_Pos            (18U)
4488 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
4489 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
4490 #define ADC_CSR_EOS_SLV_Pos            (19U)
4491 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
4492 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
4493 #define ADC_CSR_OVR_SLV_Pos            (20U)
4494 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
4495 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
4496 #define ADC_CSR_JEOC_SLV_Pos           (21U)
4497 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
4498 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
4499 #define ADC_CSR_JEOS_SLV_Pos           (22U)
4500 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
4501 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
4502 #define ADC_CSR_AWD1_SLV_Pos           (23U)
4503 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
4504 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
4505 #define ADC_CSR_AWD2_SLV_Pos           (24U)
4506 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
4507 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
4508 #define ADC_CSR_AWD3_SLV_Pos           (25U)
4509 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
4510 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
4511 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
4512 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
4513 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
4514 
4515 /********************  Bit definition for ADC_CCR register  *******************/
4516 #define ADC_CCR_DUAL_Pos               (0U)
4517 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
4518 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
4519 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
4520 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
4521 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
4522 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
4523 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
4524 
4525 #define ADC_CCR_DELAY_Pos              (8U)
4526 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
4527 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
4528 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
4529 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
4530 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
4531 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
4532 
4533 #define ADC_CCR_DMACFG_Pos             (13U)
4534 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
4535 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
4536 
4537 #define ADC_CCR_MDMA_Pos               (14U)
4538 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
4539 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
4540 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
4541 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
4542 
4543 #define ADC_CCR_CKMODE_Pos             (16U)
4544 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
4545 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
4546 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
4547 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
4548 
4549 #define ADC_CCR_PRESC_Pos              (18U)
4550 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
4551 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
4552 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
4553 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
4554 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
4555 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
4556 
4557 #define ADC_CCR_VREFEN_Pos             (22U)
4558 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
4559 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
4560 #define ADC_CCR_TSEN_Pos               (23U)
4561 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
4562 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
4563 #define ADC_CCR_VBATEN_Pos             (24U)
4564 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
4565 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
4566 
4567 /********************  Bit definition for ADC_CDR register  *******************/
4568 #define ADC_CDR_RDATA_MST_Pos          (0U)
4569 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
4570 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
4571 
4572 #define ADC_CDR_RDATA_SLV_Pos          (16U)
4573 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
4574 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
4575 
4576 
4577 /******************************************************************************/
4578 /*                                                                            */
4579 /*                          CORDIC calculation unit                           */
4580 /*                                                                            */
4581 /******************************************************************************/
4582 /*******************  Bit definition for CORDIC_CSR register  *****************/
4583 #define CORDIC_CSR_FUNC_Pos                 (0U)
4584 #define CORDIC_CSR_FUNC_Msk                 (0xFUL << CORDIC_CSR_FUNC_Pos)          /*!< 0x0000000F */
4585 #define CORDIC_CSR_FUNC                     CORDIC_CSR_FUNC_Msk                     /*!< Function */
4586 #define CORDIC_CSR_FUNC_0                   (0x1UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000001 */
4587 #define CORDIC_CSR_FUNC_1                   (0x2UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000002 */
4588 #define CORDIC_CSR_FUNC_2                   (0x4UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000004 */
4589 #define CORDIC_CSR_FUNC_3                   (0x8UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000008 */
4590 #define CORDIC_CSR_PRECISION_Pos            (4U)
4591 #define CORDIC_CSR_PRECISION_Msk            (0xFUL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x000000F0 */
4592 #define CORDIC_CSR_PRECISION                CORDIC_CSR_PRECISION_Msk                /*!< Precision */
4593 #define CORDIC_CSR_PRECISION_0              (0x1UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000010 */
4594 #define CORDIC_CSR_PRECISION_1              (0x2UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000020 */
4595 #define CORDIC_CSR_PRECISION_2              (0x4UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000040 */
4596 #define CORDIC_CSR_PRECISION_3              (0x8UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000080 */
4597 #define CORDIC_CSR_SCALE_Pos                (8U)
4598 #define CORDIC_CSR_SCALE_Msk                (0x7UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000700 */
4599 #define CORDIC_CSR_SCALE                    CORDIC_CSR_SCALE_Msk                    /*!< Scaling factor */
4600 #define CORDIC_CSR_SCALE_0                  (0x1UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000100 */
4601 #define CORDIC_CSR_SCALE_1                  (0x2UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000200 */
4602 #define CORDIC_CSR_SCALE_2                  (0x4UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000400 */
4603 #define CORDIC_CSR_IEN_Pos                  (16U)
4604 #define CORDIC_CSR_IEN_Msk                  (0x1UL << CORDIC_CSR_IEN_Pos)           /*!< 0x00010000 */
4605 #define CORDIC_CSR_IEN                      CORDIC_CSR_IEN_Msk                      /*!< Interrupt Enable */
4606 #define CORDIC_CSR_DMAREN_Pos               (17U)
4607 #define CORDIC_CSR_DMAREN_Msk               (0x1UL << CORDIC_CSR_DMAREN_Pos)        /*!< 0x00020000 */
4608 #define CORDIC_CSR_DMAREN                   CORDIC_CSR_DMAREN_Msk                   /*!< DMA Read channel Enable */
4609 #define CORDIC_CSR_DMAWEN_Pos               (18U)
4610 #define CORDIC_CSR_DMAWEN_Msk               (0x1UL << CORDIC_CSR_DMAWEN_Pos)        /*!< 0x00040000 */
4611 #define CORDIC_CSR_DMAWEN                   CORDIC_CSR_DMAWEN_Msk                   /*!< DMA Write channel Enable */
4612 #define CORDIC_CSR_NRES_Pos                 (19U)
4613 #define CORDIC_CSR_NRES_Msk                 (0x1UL << CORDIC_CSR_NRES_Pos)          /*!< 0x00080000 */
4614 #define CORDIC_CSR_NRES                     CORDIC_CSR_NRES_Msk                     /*!< Number of results in WDATA register */
4615 #define CORDIC_CSR_NARGS_Pos                (20U)
4616 #define CORDIC_CSR_NARGS_Msk                (0x1UL << CORDIC_CSR_NARGS_Pos)         /*!< 0x00100000 */
4617 #define CORDIC_CSR_NARGS                    CORDIC_CSR_NARGS_Msk                    /*!< Number of arguments in RDATA register */
4618 #define CORDIC_CSR_RESSIZE_Pos              (21U)
4619 #define CORDIC_CSR_RESSIZE_Msk              (0x1UL << CORDIC_CSR_RESSIZE_Pos)       /*!< 0x00200000 */
4620 #define CORDIC_CSR_RESSIZE                  CORDIC_CSR_RESSIZE_Msk                  /*!< Width of output data */
4621 #define CORDIC_CSR_ARGSIZE_Pos              (22U)
4622 #define CORDIC_CSR_ARGSIZE_Msk              (0x1UL << CORDIC_CSR_ARGSIZE_Pos)       /*!< 0x00400000 */
4623 #define CORDIC_CSR_ARGSIZE                  CORDIC_CSR_ARGSIZE_Msk                  /*!< Width of input data */
4624 #define CORDIC_CSR_RRDY_Pos                 (31U)
4625 #define CORDIC_CSR_RRDY_Msk                 (0x1UL << CORDIC_CSR_RRDY_Pos)          /*!< 0x80000000 */
4626 #define CORDIC_CSR_RRDY                     CORDIC_CSR_RRDY_Msk                     /*!< Result Ready Flag */
4627 
4628 /*******************  Bit definition for CORDIC_WDATA register  ***************/
4629 #define CORDIC_WDATA_ARG_Pos                (0U)
4630 #define CORDIC_WDATA_ARG_Msk                (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)  /*!< 0xFFFFFFFF */
4631 #define CORDIC_WDATA_ARG                    CORDIC_WDATA_ARG_Msk                    /*!< Input Argument */
4632 
4633 /*******************  Bit definition for CORDIC_RDATA register  ***************/
4634 #define CORDIC_RDATA_RES_Pos                (0U)
4635 #define CORDIC_RDATA_RES_Msk                (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)  /*!< 0xFFFFFFFF */
4636 #define CORDIC_RDATA_RES                    CORDIC_RDATA_RES_Msk                    /*!< Output Result */
4637 
4638 /******************************************************************************/
4639 /*                                                                            */
4640 /*                          CRC calculation unit                              */
4641 /*                                                                            */
4642 /******************************************************************************/
4643 /*******************  Bit definition for CRC_DR register  *********************/
4644 #define CRC_DR_DR_Pos                       (0U)
4645 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
4646 #define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */
4647 
4648 /*******************  Bit definition for CRC_IDR register  ********************/
4649 #define CRC_IDR_IDR_Pos                     (0U)
4650 #define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
4651 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */
4652 
4653 /********************  Bit definition for CRC_CR register  ********************/
4654 #define CRC_CR_RESET_Pos                    (0U)
4655 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)             /*!< 0x00000001 */
4656 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                        /*!< RESET the CRC computation unit bit */
4657 #define CRC_CR_POLYSIZE_Pos                 (3U)
4658 #define CRC_CR_POLYSIZE_Msk                 (0x3UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000018 */
4659 #define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                     /*!< Polynomial size bits */
4660 #define CRC_CR_POLYSIZE_0                   (0x1UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000008 */
4661 #define CRC_CR_POLYSIZE_1                   (0x2UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000010 */
4662 #define CRC_CR_REV_IN_Pos                   (5U)
4663 #define CRC_CR_REV_IN_Msk                   (0x3UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000060 */
4664 #define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                       /*!< REV_IN Reverse Input Data bits */
4665 #define CRC_CR_REV_IN_0                     (0x1UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000020 */
4666 #define CRC_CR_REV_IN_1                     (0x2UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000040 */
4667 #define CRC_CR_REV_OUT_Pos                  (7U)
4668 #define CRC_CR_REV_OUT_Msk                  (0x1UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000080 */
4669 #define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                      /*!< REV_OUT Reverse Output Data bits */
4670 
4671 /*******************  Bit definition for CRC_INIT register  *******************/
4672 #define CRC_INIT_INIT_Pos                   (0U)
4673 #define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
4674 #define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */
4675 
4676 /*******************  Bit definition for CRC_POL register  ********************/
4677 #define CRC_POL_POL_Pos                     (0U)
4678 #define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
4679 #define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */
4680 
4681 
4682 /******************************************************************************/
4683 /*                                                                            */
4684 /*                          CRS Clock Recovery System                         */
4685 /******************************************************************************/
4686 /*******************  Bit definition for CRS_CR register  *********************/
4687 #define CRS_CR_SYNCOKIE_Pos                 (0U)
4688 #define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
4689 #define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
4690 #define CRS_CR_SYNCWARNIE_Pos               (1U)
4691 #define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
4692 #define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
4693 #define CRS_CR_ERRIE_Pos                    (2U)
4694 #define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
4695 #define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
4696 #define CRS_CR_ESYNCIE_Pos                  (3U)
4697 #define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
4698 #define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
4699 #define CRS_CR_CEN_Pos                      (5U)
4700 #define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
4701 #define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
4702 #define CRS_CR_AUTOTRIMEN_Pos               (6U)
4703 #define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
4704 #define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
4705 #define CRS_CR_SWSYNC_Pos                   (7U)
4706 #define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
4707 #define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
4708 #define CRS_CR_TRIM_Pos                     (8U)
4709 #define CRS_CR_TRIM_Msk                     (0x3FUL << CRS_CR_TRIM_Pos)             /*!< 0x00003F00 */
4710 #define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI48 oscillator smooth trimming */
4711 
4712 /*******************  Bit definition for CRS_CFGR register  *********************/
4713 #define CRS_CFGR_RELOAD_Pos                 (0U)
4714 #define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
4715 #define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
4716 #define CRS_CFGR_FELIM_Pos                  (16U)
4717 #define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
4718 #define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
4719 #define CRS_CFGR_SYNCDIV_Pos                (24U)
4720 #define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
4721 #define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
4722 #define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
4723 #define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
4724 #define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
4725 #define CRS_CFGR_SYNCSRC_Pos                (28U)
4726 #define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
4727 #define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
4728 #define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
4729 #define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
4730 #define CRS_CFGR_SYNCPOL_Pos                (31U)
4731 #define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
4732 #define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */
4733 
4734 /*******************  Bit definition for CRS_ISR register  *********************/
4735 #define CRS_ISR_SYNCOKF_Pos                 (0U)
4736 #define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
4737 #define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
4738 #define CRS_ISR_SYNCWARNF_Pos               (1U)
4739 #define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
4740 #define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
4741 #define CRS_ISR_ERRF_Pos                    (2U)
4742 #define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
4743 #define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
4744 #define CRS_ISR_ESYNCF_Pos                  (3U)
4745 #define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
4746 #define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
4747 #define CRS_ISR_SYNCERR_Pos                 (8U)
4748 #define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
4749 #define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
4750 #define CRS_ISR_SYNCMISS_Pos                (9U)
4751 #define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
4752 #define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
4753 #define CRS_ISR_TRIMOVF_Pos                 (10U)
4754 #define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
4755 #define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
4756 #define CRS_ISR_FEDIR_Pos                   (15U)
4757 #define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
4758 #define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
4759 #define CRS_ISR_FECAP_Pos                   (16U)
4760 #define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
4761 #define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */
4762 
4763 /*******************  Bit definition for CRS_ICR register  *********************/
4764 #define CRS_ICR_SYNCOKC_Pos                 (0U)
4765 #define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
4766 #define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
4767 #define CRS_ICR_SYNCWARNC_Pos               (1U)
4768 #define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
4769 #define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
4770 #define CRS_ICR_ERRC_Pos                    (2U)
4771 #define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
4772 #define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
4773 #define CRS_ICR_ESYNCC_Pos                  (3U)
4774 #define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
4775 #define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */
4776 
4777 
4778 /******************************************************************************/
4779 /*                                                                            */
4780 /*                                    RNG                                     */
4781 /*                                                                            */
4782 /******************************************************************************/
4783 /********************  Bits definition for RNG_CR register  *******************/
4784 #define RNG_CR_RNGEN_Pos                    (2U)
4785 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
4786 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
4787 #define RNG_CR_IE_Pos                       (3U)
4788 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
4789 #define RNG_CR_IE                           RNG_CR_IE_Msk
4790 #define RNG_CR_CED_Pos                      (5U)
4791 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
4792 #define RNG_CR_CED                          RNG_CR_CED_Msk
4793 #define RNG_CR_ARDIS_Pos                    (7U)
4794 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
4795 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
4796 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
4797 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
4798 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
4799 #define RNG_CR_NISTC_Pos                    (12U)
4800 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
4801 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
4802 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
4803 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
4804 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
4805 #define RNG_CR_CLKDIV_Pos                   (16U)
4806 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
4807 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
4808 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
4809 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
4810 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
4811 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
4812 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
4813 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
4814 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
4815 #define RNG_CR_CONDRST_Pos                  (30U)
4816 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
4817 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
4818 #define RNG_CR_CONFIGLOCK_Pos               (31U)
4819 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
4820 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
4821 
4822 /********************  Bits definition for RNG_SR register  *******************/
4823 #define RNG_SR_DRDY_Pos                     (0U)
4824 #define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
4825 #define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
4826 #define RNG_SR_CECS_Pos                     (1U)
4827 #define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
4828 #define RNG_SR_CECS                         RNG_SR_CECS_Msk
4829 #define RNG_SR_SECS_Pos                     (2U)
4830 #define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
4831 #define RNG_SR_SECS                         RNG_SR_SECS_Msk
4832 #define RNG_SR_CEIS_Pos                     (5U)
4833 #define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
4834 #define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
4835 #define RNG_SR_SEIS_Pos                     (6U)
4836 #define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
4837 #define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
4838 
4839 /********************  Bits definition for RNG_HTCR register  *******************/
4840 #define RNG_HTCR_HTCFG_Pos                  (0U)
4841 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
4842 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
4843 
4844 /******************************************************************************/
4845 /*                                                                            */
4846 /*                      Digital to Analog Converter                           */
4847 /*                                                                            */
4848 /******************************************************************************/
4849 #define DAC_CHANNEL2_SUPPORT                                                        /*!< DAC feature available only on specific devices: DAC channel 2 available */
4850 
4851 /********************  Bit definition for DAC_CR register  ********************/
4852 #define DAC_CR_EN1_Pos                      (0U)
4853 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
4854 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                          /*!<DAC channel1 enable */
4855 #define DAC_CR_TEN1_Pos                     (1U)
4856 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
4857 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                         /*!<DAC channel1 Trigger enable */
4858 #define DAC_CR_TSEL1_Pos                    (2U)
4859 #define DAC_CR_TSEL1_Msk                    (0xFUL << DAC_CR_TSEL1_Pos)             /*!< 0x0000003C */
4860 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                        /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
4861 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
4862 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
4863 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
4864 #define DAC_CR_TSEL1_3                      (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
4865 #define DAC_CR_WAVE1_Pos                    (6U)
4866 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
4867 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
4868 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
4869 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
4870 #define DAC_CR_MAMP1_Pos                    (8U)
4871 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
4872 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
4873 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
4874 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
4875 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
4876 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
4877 #define DAC_CR_DMAEN1_Pos                   (12U)
4878 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
4879 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                       /*!<DAC channel1 DMA enable */
4880 #define DAC_CR_DMAUDRIE1_Pos                (13U)
4881 #define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
4882 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk                    /*!<DAC channel 1 DMA underrun interrupt enable  >*/
4883 #define DAC_CR_CEN1_Pos                     (14U)
4884 #define DAC_CR_CEN1_Msk                     (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
4885 #define DAC_CR_CEN1                         DAC_CR_CEN1_Msk                         /*!<DAC channel 1 calibration enable >*/
4886 #define DAC_CR_EN2_Pos                      (16U)
4887 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)               /*!< 0x00010000 */
4888 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                          /*!<DAC channel2 enable */
4889 #define DAC_CR_TEN2_Pos                     (17U)
4890 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)              /*!< 0x00020000 */
4891 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                         /*!<DAC channel2 Trigger enable */
4892 #define DAC_CR_TSEL2_Pos                    (18U)
4893 #define DAC_CR_TSEL2_Msk                    (0xFUL << DAC_CR_TSEL2_Pos)             /*!< 0x003C0000 */
4894 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                        /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
4895 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)             /*!< 0x00040000 */
4896 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)             /*!< 0x00080000 */
4897 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)             /*!< 0x00100000 */
4898 #define DAC_CR_TSEL2_3                      (0x8UL << DAC_CR_TSEL2_Pos)             /*!< 0x00200000 */
4899 #define DAC_CR_WAVE2_Pos                    (22U)
4900 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)             /*!< 0x00C00000 */
4901 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
4902 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)             /*!< 0x00400000 */
4903 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)             /*!< 0x00800000 */
4904 #define DAC_CR_MAMP2_Pos                    (24U)
4905 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)             /*!< 0x0F000000 */
4906 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
4907 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)             /*!< 0x01000000 */
4908 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)             /*!< 0x02000000 */
4909 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)             /*!< 0x04000000 */
4910 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)             /*!< 0x08000000 */
4911 #define DAC_CR_DMAEN2_Pos                   (28U)
4912 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)            /*!< 0x10000000 */
4913 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                       /*!<DAC channel2 DMA enabled */
4914 #define DAC_CR_DMAUDRIE2_Pos                (29U)
4915 #define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)         /*!< 0x20000000 */
4916 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk                    /*!<DAC channel2 DMA underrun interrupt enable  >*/
4917 #define DAC_CR_CEN2_Pos                     (30U)
4918 #define DAC_CR_CEN2_Msk                     (0x1UL << DAC_CR_CEN2_Pos)              /*!< 0x40000000 */
4919 #define DAC_CR_CEN2                         DAC_CR_CEN2_Msk                         /*!<DAC channel2 calibration enable >*/
4920 
4921 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
4922 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
4923 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)      /*!< 0x00000001 */
4924 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk                 /*!<DAC channel1 software trigger */
4925 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
4926 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)      /*!< 0x00000002 */
4927 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk                 /*!<DAC channel2 software trigger */
4928 #define DAC_SWTRIGR_SWTRIGB1_Pos            (16U)
4929 #define DAC_SWTRIGR_SWTRIGB1_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)     /*!< 0x00010000 */
4930 #define DAC_SWTRIGR_SWTRIGB1                DAC_SWTRIGR_SWTRIGB1_Msk                /*!<DAC channel1 software trigger B */
4931 #define DAC_SWTRIGR_SWTRIGB2_Pos            (17U)
4932 #define DAC_SWTRIGR_SWTRIGB2_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)     /*!< 0x00020000 */
4933 #define DAC_SWTRIGR_SWTRIGB2                DAC_SWTRIGR_SWTRIGB2_Msk                /*!<DAC channel2 software trigger B */
4934 
4935 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
4936 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
4937 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
4938 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
4939 #define DAC_DHR12R1_DACC1DHRB_Pos           (16U)
4940 #define DAC_DHR12R1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
4941 #define DAC_DHR12R1_DACC1DHRB               DAC_DHR12R1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Right-aligned data B */
4942 
4943 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
4944 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
4945 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
4946 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
4947 #define DAC_DHR12L1_DACC1DHRB_Pos           (20U)
4948 #define DAC_DHR12L1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
4949 #define DAC_DHR12L1_DACC1DHRB               DAC_DHR12L1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Left aligned data B */
4950 
4951 /******************  Bit definition for DAC_DHR8R1 register  ******************/
4952 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
4953 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
4954 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
4955 #define DAC_DHR8R1_DACC1DHRB_Pos            (8U)
4956 #define DAC_DHR8R1_DACC1DHRB_Msk            (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
4957 #define DAC_DHR8R1_DACC1DHRB                DAC_DHR8R1_DACC1DHRB_Msk                /*!<DAC channel1 8-bit Right aligned data B */
4958 
4959 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
4960 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
4961 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)   /*!< 0x00000FFF */
4962 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
4963 #define DAC_DHR12R2_DACC2DHRB_Pos           (16U)
4964 #define DAC_DHR12R2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)  /*!< 0x0FFF0000 */
4965 #define DAC_DHR12R2_DACC2DHRB               DAC_DHR12R2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Right-aligned data B */
4966 
4967 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
4968 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
4969 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)   /*!< 0x0000FFF0 */
4970 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
4971 #define DAC_DHR12L2_DACC2DHRB_Pos           (20U)
4972 #define DAC_DHR12L2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)  /*!< 0xFFF00000 */
4973 #define DAC_DHR12L2_DACC2DHRB               DAC_DHR12L2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Left aligned data B */
4974 
4975 /******************  Bit definition for DAC_DHR8R2 register  ******************/
4976 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
4977 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)     /*!< 0x000000FF */
4978 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
4979 #define DAC_DHR8R2_DACC2DHRB_Pos            (8U)
4980 #define DAC_DHR8R2_DACC2DHRB_Msk            (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)    /*!< 0x0000FF00 */
4981 #define DAC_DHR8R2_DACC2DHRB                DAC_DHR8R2_DACC2DHRB_Msk                /*!<DAC channel2 8-bit Right aligned data B */
4982 
4983 /*****************  Bit definition for DAC_DHR12RD register  ******************/
4984 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
4985 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)   /*!< 0x00000FFF */
4986 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
4987 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
4988 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)   /*!< 0x0FFF0000 */
4989 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
4990 
4991 /*****************  Bit definition for DAC_DHR12LD register  ******************/
4992 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
4993 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
4994 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
4995 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
4996 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)   /*!< 0xFFF00000 */
4997 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
4998 
4999 /******************  Bit definition for DAC_DHR8RD register  ******************/
5000 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
5001 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)     /*!< 0x000000FF */
5002 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
5003 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
5004 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)     /*!< 0x0000FF00 */
5005 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
5006 
5007 /*******************  Bit definition for DAC_DOR1 register  *******************/
5008 #define DAC_DOR1_DACC1DOR_Pos               (0U)
5009 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
5010 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk                   /*!<DAC channel1 data output */
5011 #define DAC_DOR1_DACC1DORB_Pos              (16U)
5012 #define DAC_DOR1_DACC1DORB_Msk              (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
5013 #define DAC_DOR1_DACC1DORB                  DAC_DOR1_DACC1DORB_Msk                  /*!<DAC channel1 data output B */
5014 
5015 /*******************  Bit definition for DAC_DOR2 register  *******************/
5016 #define DAC_DOR2_DACC2DOR_Pos               (0U)
5017 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)      /*!< 0x00000FFF */
5018 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk                   /*!<DAC channel2 data output */
5019 #define DAC_DOR2_DACC2DORB_Pos              (16U)
5020 #define DAC_DOR2_DACC2DORB_Msk              (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)     /*!< 0x0FFF0000 */
5021 #define DAC_DOR2_DACC2DORB                  DAC_DOR2_DACC2DORB_Msk                  /*!<DAC channel2 data output B */
5022 
5023 /********************  Bit definition for DAC_SR register  ********************/
5024 #define DAC_SR_DAC1RDY_Pos                  (11U)
5025 #define DAC_SR_DAC1RDY_Msk                  (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
5026 #define DAC_SR_DAC1RDY                      DAC_SR_DAC1RDY_Msk                      /*!<DAC channel 1 ready status bit */
5027 #define DAC_SR_DORSTAT1_Pos                 (12U)
5028 #define DAC_SR_DORSTAT1_Msk                 (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
5029 #define DAC_SR_DORSTAT1                     DAC_SR_DORSTAT1_Msk                     /*!<DAC channel 1 output register status bit */
5030 #define DAC_SR_DMAUDR1_Pos                  (13U)
5031 #define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
5032 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                      /*!<DAC channel1 DMA underrun flag */
5033 #define DAC_SR_CAL_FLAG1_Pos                (14U)
5034 #define DAC_SR_CAL_FLAG1_Msk                (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
5035 #define DAC_SR_CAL_FLAG1                    DAC_SR_CAL_FLAG1_Msk                    /*!<DAC channel1 calibration offset status */
5036 #define DAC_SR_BWST1_Pos                    (15U)
5037 #define DAC_SR_BWST1_Msk                    (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
5038 #define DAC_SR_BWST1                        DAC_SR_BWST1_Msk                        /*!<DAC channel1 busy writing sample time flag */
5039 
5040 #define DAC_SR_DAC2RDY_Pos                  (27U)
5041 #define DAC_SR_DAC2RDY_Msk                  (0x1UL << DAC_SR_DAC2RDY_Pos)           /*!< 0x08000000 */
5042 #define DAC_SR_DAC2RDY                      DAC_SR_DAC2RDY_Msk                      /*!<DAC channel 2 ready status bit */
5043 #define DAC_SR_DORSTAT2_Pos                 (28U)
5044 #define DAC_SR_DORSTAT2_Msk                 (0x1UL << DAC_SR_DORSTAT2_Pos)          /*!< 0x10000000 */
5045 #define DAC_SR_DORSTAT2                     DAC_SR_DORSTAT2_Msk                     /*!<DAC channel 2 output register status bit */
5046 #define DAC_SR_DMAUDR2_Pos                  (29U)
5047 #define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)           /*!< 0x20000000 */
5048 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                      /*!<DAC channel2 DMA underrun flag */
5049 #define DAC_SR_CAL_FLAG2_Pos                (30U)
5050 #define DAC_SR_CAL_FLAG2_Msk                (0x1UL << DAC_SR_CAL_FLAG2_Pos)         /*!< 0x40000000 */
5051 #define DAC_SR_CAL_FLAG2                    DAC_SR_CAL_FLAG2_Msk                    /*!<DAC channel2 calibration offset status */
5052 #define DAC_SR_BWST2_Pos                    (31U)
5053 #define DAC_SR_BWST2_Msk                    (0x1UL << DAC_SR_BWST2_Pos)             /*!< 0x80000000 */
5054 #define DAC_SR_BWST2                        DAC_SR_BWST2_Msk                        /*!<DAC channel2 busy writing sample time flag */
5055 
5056 /*******************  Bit definition for DAC_CCR register  ********************/
5057 #define DAC_CCR_OTRIM1_Pos                  (0U)
5058 #define DAC_CCR_OTRIM1_Msk                  (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
5059 #define DAC_CCR_OTRIM1                      DAC_CCR_OTRIM1_Msk                      /*!<DAC channel1 offset trimming value */
5060 #define DAC_CCR_OTRIM2_Pos                  (16U)
5061 #define DAC_CCR_OTRIM2_Msk                  (0x1FUL << DAC_CCR_OTRIM2_Pos)          /*!< 0x001F0000 */
5062 #define DAC_CCR_OTRIM2                      DAC_CCR_OTRIM2_Msk                      /*!<DAC channel2 offset trimming value */
5063 
5064 /*******************  Bit definition for DAC_MCR register  *******************/
5065 #define DAC_MCR_MODE1_Pos                   (0U)
5066 #define DAC_MCR_MODE1_Msk                   (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
5067 #define DAC_MCR_MODE1                       DAC_MCR_MODE1_Msk                       /*!<MODE1[2:0] (DAC channel1 mode) */
5068 #define DAC_MCR_MODE1_0                     (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
5069 #define DAC_MCR_MODE1_1                     (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
5070 #define DAC_MCR_MODE1_2                     (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
5071 #define DAC_MCR_DMADOUBLE1_Pos              (8U)
5072 #define DAC_MCR_DMADOUBLE1_Msk              (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
5073 #define DAC_MCR_DMADOUBLE1                  DAC_MCR_DMADOUBLE1_Msk                  /*!<DAC Channel 1 DMA double data mode */
5074 #define DAC_MCR_SINFORMAT1_Pos              (9U)
5075 #define DAC_MCR_SINFORMAT1_Msk              (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
5076 #define DAC_MCR_SINFORMAT1                  DAC_MCR_SINFORMAT1_Msk                  /*!<DAC Channel 1 enable signed format */
5077 #define DAC_MCR_HFSEL_Pos                   (14U)
5078 #define DAC_MCR_HFSEL_Msk                   (0x3UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000C000 */
5079 #define DAC_MCR_HFSEL                       DAC_MCR_HFSEL_Msk                       /*!<HFSEL[1:0] (High Frequency interface mode selection) */
5080 #define DAC_MCR_HFSEL_0                     (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
5081 #define DAC_MCR_HFSEL_1                     (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */
5082 #define DAC_MCR_MODE2_Pos                   (16U)
5083 #define DAC_MCR_MODE2_Msk                   (0x7UL << DAC_MCR_MODE2_Pos)            /*!< 0x00070000 */
5084 #define DAC_MCR_MODE2                       DAC_MCR_MODE2_Msk                       /*!<MODE2[2:0] (DAC channel2 mode) */
5085 #define DAC_MCR_MODE2_0                     (0x1UL << DAC_MCR_MODE2_Pos)            /*!< 0x00010000 */
5086 #define DAC_MCR_MODE2_1                     (0x2UL << DAC_MCR_MODE2_Pos)            /*!< 0x00020000 */
5087 #define DAC_MCR_MODE2_2                     (0x4UL << DAC_MCR_MODE2_Pos)            /*!< 0x00040000 */
5088 #define DAC_MCR_DMADOUBLE2_Pos              (24U)
5089 #define DAC_MCR_DMADOUBLE2_Msk              (0x1UL << DAC_MCR_DMADOUBLE2_Pos)       /*!< 0x01000000 */
5090 #define DAC_MCR_DMADOUBLE2                  DAC_MCR_DMADOUBLE2_Msk                  /*!<DAC Channel 2 DMA double data mode */
5091 #define DAC_MCR_SINFORMAT2_Pos              (25U)
5092 #define DAC_MCR_SINFORMAT2_Msk              (0x1UL << DAC_MCR_SINFORMAT2_Pos)       /*!< 0x02000000 */
5093 #define DAC_MCR_SINFORMAT2                  DAC_MCR_SINFORMAT2_Msk                  /*!<DAC Channel 2 enable signed format */
5094 
5095 /******************  Bit definition for DAC_SHSR1 register  ******************/
5096 #define DAC_SHSR1_TSAMPLE1_Pos              (0U)
5097 #define DAC_SHSR1_TSAMPLE1_Msk              (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
5098 #define DAC_SHSR1_TSAMPLE1                  DAC_SHSR1_TSAMPLE1_Msk                  /*!<DAC channel1 sample time */
5099 
5100 /******************  Bit definition for DAC_SHSR2 register  ******************/
5101 #define DAC_SHSR2_TSAMPLE2_Pos              (0U)
5102 #define DAC_SHSR2_TSAMPLE2_Msk              (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)     /*!< 0x000003FF */
5103 #define DAC_SHSR2_TSAMPLE2                  DAC_SHSR2_TSAMPLE2_Msk                  /*!<DAC channel2 sample time */
5104 
5105 /******************  Bit definition for DAC_SHHR register  ******************/
5106 #define DAC_SHHR_THOLD1_Pos                 (0U)
5107 #define DAC_SHHR_THOLD1_Msk                 (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
5108 #define DAC_SHHR_THOLD1                     DAC_SHHR_THOLD1_Msk                     /*!<DAC channel1 hold time */
5109 #define DAC_SHHR_THOLD2_Pos                 (16U)
5110 #define DAC_SHHR_THOLD2_Msk                 (0x3FFUL << DAC_SHHR_THOLD2_Pos)        /*!< 0x03FF0000 */
5111 #define DAC_SHHR_THOLD2                     DAC_SHHR_THOLD2_Msk                     /*!<DAC channel2 hold time */
5112 
5113 /******************  Bit definition for DAC_SHRR register  ******************/
5114 #define DAC_SHRR_TREFRESH1_Pos              (0U)
5115 #define DAC_SHRR_TREFRESH1_Msk              (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
5116 #define DAC_SHRR_TREFRESH1                  DAC_SHRR_TREFRESH1_Msk                  /*!<DAC channel1 refresh time */
5117 #define DAC_SHRR_TREFRESH2_Pos              (16U)
5118 #define DAC_SHRR_TREFRESH2_Msk              (0xFFUL << DAC_SHRR_TREFRESH2_Pos)      /*!< 0x00FF0000 */
5119 #define DAC_SHRR_TREFRESH2                  DAC_SHRR_TREFRESH2_Msk                  /*!<DAC channel2 refresh time */
5120 
5121 /******************  Bit definition for DAC_AUTOCR register  ******************/
5122 #define DAC_AUTOCR_AUTOMODE_Pos             (22U)
5123 #define DAC_AUTOCR_AUTOMODE_Msk             (0x1UL << DAC_AUTOCR_AUTOMODE_Pos)      /*!< 0x00400000 */
5124 #define DAC_AUTOCR_AUTOMODE                 DAC_AUTOCR_AUTOMODE_Msk                 /*!< AUTOCR Enable */
5125 
5126 
5127 /******************************************************************************/
5128 /*                                                                            */
5129 /*                       Advanced Encryption Standard (AES)                   */
5130 /*                                                                            */
5131 /******************************************************************************/
5132 /*******************  Bit definition for AES_CR register  *********************/
5133 #define AES_CR_EN_Pos                       (0U)
5134 #define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)                /*!< 0x00000001 */
5135 #define AES_CR_EN                           AES_CR_EN_Msk                           /*!< AES Enable */
5136 #define AES_CR_DATATYPE_Pos                 (1U)
5137 #define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
5138 #define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                     /*!< Data type selection */
5139 #define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
5140 #define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
5141 #define AES_CR_MODE_Pos                     (3U)
5142 #define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)              /*!< 0x00000018 */
5143 #define AES_CR_MODE                         AES_CR_MODE_Msk                         /*!< AES Mode Of Operation */
5144 #define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)              /*!< 0x00000008 */
5145 #define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)              /*!< 0x00000010 */
5146 #define AES_CR_CHMOD_Pos                    (5U)
5147 #define AES_CR_CHMOD_Msk                    (0x803UL << AES_CR_CHMOD_Pos)           /*!< 0x00010060 */
5148 #define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                        /*!< AES Chaining Mode */
5149 #define AES_CR_CHMOD_0                      (0x001UL << AES_CR_CHMOD_Pos)           /*!< 0x00000020 */
5150 #define AES_CR_CHMOD_1                      (0x002UL << AES_CR_CHMOD_Pos)           /*!< 0x00000040 */
5151 #define AES_CR_CHMOD_2                      (0x800UL << AES_CR_CHMOD_Pos)           /*!< 0x00010000 */
5152 #define AES_CR_DMAINEN_Pos                  (11U)
5153 #define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
5154 #define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
5155 #define AES_CR_DMAOUTEN_Pos                 (12U)
5156 #define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
5157 #define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
5158 #define AES_CR_GCMPH_Pos                    (13U)
5159 #define AES_CR_GCMPH_Msk                    (0x3UL << AES_CR_GCMPH_Pos)             /*!< 0x00006000 */
5160 #define AES_CR_GCMPH                        AES_CR_GCMPH_Msk                        /*!< GCM Phase */
5161 #define AES_CR_GCMPH_0                      (0x1UL << AES_CR_GCMPH_Pos)             /*!< 0x00002000 */
5162 #define AES_CR_GCMPH_1                      (0x2UL << AES_CR_GCMPH_Pos)             /*!< 0x00004000 */
5163 #define AES_CR_KEYSIZE_Pos                  (18U)
5164 #define AES_CR_KEYSIZE_Msk                  (0x1UL << AES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
5165 #define AES_CR_KEYSIZE                      AES_CR_KEYSIZE_Msk                      /*!< Key size selection */
5166 #define AES_CR_KEYPROT_Pos                 (19U)
5167 #define AES_CR_KEYPROT_Msk                 (0x1UL << AES_CR_KEYPROT_Pos)          /*!< 0x00040000 */
5168 #define AES_CR_KEYPROT                     AES_CR_KEYPROT_Msk                     /*!<  Key protection */
5169 #define AES_CR_NPBLB_Pos                    (20U)
5170 #define AES_CR_NPBLB_Msk                    (0xFUL << AES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
5171 #define AES_CR_NPBLB                        AES_CR_NPBLB_Msk                        /*!< Number of padding bytes in payload last block */
5172 #define AES_CR_NPBLB_0                      (0x1UL << AES_CR_NPBLB_Pos)             /*!< 0x00100000 */
5173 #define AES_CR_NPBLB_1                      (0x2UL << AES_CR_NPBLB_Pos)             /*!< 0x00200000 */
5174 #define AES_CR_NPBLB_2                      (0x4UL << AES_CR_NPBLB_Pos)             /*!< 0x00400000 */
5175 #define AES_CR_NPBLB_3                      (0x8UL << AES_CR_NPBLB_Pos)             /*!< 0x00800000 */
5176 #define AES_CR_KMOD_Pos                     (24U)
5177 #define AES_CR_KMOD_Msk                     (0x3UL << AES_CR_KMOD_Pos)              /*!< 0x00000006 */
5178 #define AES_CR_KMOD                         AES_CR_KMOD_Msk                         /*!< Key mode selection */
5179 #define AES_CR_KMOD_0                       (0x1UL << AES_CR_KMOD_Pos)             /*!< 0x01000000 */
5180 #define AES_CR_KMOD_1                       (0x2UL << AES_CR_KMOD_Pos)              /*!< 0x02000000 */
5181 #define AES_CR_KSHAREID_Pos                (26U)
5182 #define AES_CR_KSHAREID_Msk                (0x3UL << AES_CR_KSHAREID_Pos)         /*!< 0x00000006 */
5183 #define AES_CR_KSHAREID                    AES_CR_KSHAREID_Msk                    /*!< Key Shared ID */
5184 #define AES_CR_KEYSEL_Pos                  (28U)
5185 #define AES_CR_KEYSEL_Msk                  (0x7UL << AES_CR_KEYSEL_Pos)           /*!< 0x00000006 */
5186 #define AES_CR_KEYSEL                      AES_CR_KEYSEL_Msk                      /*!< Key Selection */
5187 #define AES_CR_KEYSEL_0                    (0x1UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
5188 #define AES_CR_KEYSEL_1                    (0x2UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
5189 #define AES_CR_KEYSEL_2                    (0x4UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
5190 #define AES_CR_IPRST_Pos                    (31U)
5191 #define AES_CR_IPRST_Msk                    (0x1UL << AES_CR_IPRST_Pos)             /*!< 0x80000001 */
5192 #define AES_CR_IPRST                        AES_CR_IPRST_Msk                        /*!< AES IP software reset */
5193 
5194 /*******************  Bit definition for AES_SR register  *********************/
5195 #define AES_SR_CCF_Pos                      (0U)
5196 #define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)               /*!< 0x00000001 */
5197 #define AES_SR_CCF                          AES_SR_CCF_Msk                          /*!< Computation Complete Flag */
5198 #define AES_SR_RDERR_Pos                    (1U)
5199 #define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)             /*!< 0x00000002 */
5200 #define AES_SR_RDERR                        AES_SR_RDERR_Msk                        /*!< Read Error Flag */
5201 #define AES_SR_WRERR_Pos                    (2U)
5202 #define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)             /*!< 0x00000004 */
5203 #define AES_SR_WRERR                        AES_SR_WRERR_Msk                        /*!< Write Error Flag */
5204 #define AES_SR_BUSY_Pos                     (3U)
5205 #define AES_SR_BUSY_Msk                     (0x1UL << AES_SR_BUSY_Pos)              /*!< 0x00000008 */
5206 #define AES_SR_BUSY                         AES_SR_BUSY_Msk                         /*!< Busy Flag */
5207 #define AES_SR_KEYVALID_Pos                 (7U)
5208 #define AES_SR_KEYVALID_Msk                 (0x1UL << AES_SR_KEYVALID_Pos)          /*!< 0x00000008 */
5209 #define AES_SR_KEYVALID                     AES_SR_KEYVALID_Msk                     /*!< KEYVALID Flag */
5210 
5211 /*******************  Bit definition for AES_DINR register  *******************/
5212 #define AES_DINR_Pos                        (0U)
5213 #define AES_DINR_Msk                        (0xFFFFFFFFUL << AES_DINR_Pos)          /*!< 0xFFFFFFFF */
5214 #define AES_DINR                            AES_DINR_Msk                            /*!< AES Data Input Register */
5215 
5216 /*******************  Bit definition for AES_DOUTR register  ******************/
5217 #define AES_DOUTR_Pos                       (0U)
5218 #define AES_DOUTR_Msk                       (0xFFFFFFFFUL << AES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
5219 #define AES_DOUTR                           AES_DOUTR_Msk                           /*!< AES Data Output Register */
5220 
5221 /*******************  Bit definition for AES_KEYR0 register  ******************/
5222 #define AES_KEYR0_Pos                       (0U)
5223 #define AES_KEYR0_Msk                       (0xFFFFFFFFUL << AES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
5224 #define AES_KEYR0                           AES_KEYR0_Msk                           /*!< AES Key Register 0 */
5225 
5226 /*******************  Bit definition for AES_KEYR1 register  ******************/
5227 #define AES_KEYR1_Pos                       (0U)
5228 #define AES_KEYR1_Msk                       (0xFFFFFFFFUL << AES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
5229 #define AES_KEYR1                           AES_KEYR1_Msk                           /*!< AES Key Register 1 */
5230 
5231 /*******************  Bit definition for AES_KEYR2 register  ******************/
5232 #define AES_KEYR2_Pos                       (0U)
5233 #define AES_KEYR2_Msk                       (0xFFFFFFFFUL << AES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
5234 #define AES_KEYR2                           AES_KEYR2_Msk                           /*!< AES Key Register 2 */
5235 
5236 /*******************  Bit definition for AES_KEYR3 register  ******************/
5237 #define AES_KEYR3_Pos                       (0U)
5238 #define AES_KEYR3_Msk                       (0xFFFFFFFFUL << AES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
5239 #define AES_KEYR3                           AES_KEYR3_Msk                           /*!< AES Key Register 3 */
5240 
5241 /*******************  Bit definition for AES_KEYR4 register  ******************/
5242 #define AES_KEYR4_Pos                       (0U)
5243 #define AES_KEYR4_Msk                       (0xFFFFFFFFUL << AES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
5244 #define AES_KEYR4                           AES_KEYR4_Msk                           /*!< AES Key Register 4 */
5245 
5246 /*******************  Bit definition for AES_KEYR5 register  ******************/
5247 #define AES_KEYR5_Pos                       (0U)
5248 #define AES_KEYR5_Msk                       (0xFFFFFFFFUL << AES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
5249 #define AES_KEYR5                           AES_KEYR5_Msk                           /*!< AES Key Register 5 */
5250 
5251 /*******************  Bit definition for AES_KEYR6 register  ******************/
5252 #define AES_KEYR6_Pos                       (0U)
5253 #define AES_KEYR6_Msk                       (0xFFFFFFFFUL << AES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
5254 #define AES_KEYR6                           AES_KEYR6_Msk                           /*!< AES Key Register 6 */
5255 
5256 /*******************  Bit definition for AES_KEYR7 register  ******************/
5257 #define AES_KEYR7_Pos                       (0U)
5258 #define AES_KEYR7_Msk                       (0xFFFFFFFFUL << AES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
5259 #define AES_KEYR7                           AES_KEYR7_Msk                           /*!< AES Key Register 7 */
5260 
5261 /*******************  Bit definition for AES_IVR0 register   ******************/
5262 #define AES_IVR0_Pos                        (0U)
5263 #define AES_IVR0_Msk                        (0xFFFFFFFFUL << AES_IVR0_Pos)          /*!< 0xFFFFFFFF */
5264 #define AES_IVR0                            AES_IVR0_Msk                            /*!< AES Initialization Vector Register 0 */
5265 
5266 /*******************  Bit definition for AES_IVR1 register   ******************/
5267 #define AES_IVR1_Pos                        (0U)
5268 #define AES_IVR1_Msk                        (0xFFFFFFFFUL << AES_IVR1_Pos)          /*!< 0xFFFFFFFF */
5269 #define AES_IVR1                            AES_IVR1_Msk                            /*!< AES Initialization Vector Register 1 */
5270 
5271 /*******************  Bit definition for AES_IVR2 register   ******************/
5272 #define AES_IVR2_Pos                        (0U)
5273 #define AES_IVR2_Msk                        (0xFFFFFFFFUL << AES_IVR2_Pos)          /*!< 0xFFFFFFFF */
5274 #define AES_IVR2                            AES_IVR2_Msk                            /*!< AES Initialization Vector Register 2 */
5275 
5276 /*******************  Bit definition for AES_IVR3 register   ******************/
5277 #define AES_IVR3_Pos                        (0U)
5278 #define AES_IVR3_Msk                        (0xFFFFFFFFUL << AES_IVR3_Pos)          /*!< 0xFFFFFFFF */
5279 #define AES_IVR3                            AES_IVR3_Msk                            /*!< AES Initialization Vector Register 3 */
5280 
5281 /*******************  Bit definition for AES_SUSP0R register  ******************/
5282 #define AES_SUSP0R_Pos                      (0U)
5283 #define AES_SUSP0R_Msk                      (0xFFFFFFFFUL << AES_SUSP0R_Pos)        /*!< 0xFFFFFFFF */
5284 #define AES_SUSP0R                          AES_SUSP0R_Msk                          /*!< AES Suspend registers 0 */
5285 
5286 /*******************  Bit definition for AES_SUSP1R register  ******************/
5287 #define AES_SUSP1R_Pos                      (0U)
5288 #define AES_SUSP1R_Msk                      (0xFFFFFFFFUL << AES_SUSP1R_Pos)        /*!< 0xFFFFFFFF */
5289 #define AES_SUSP1R                          AES_SUSP1R_Msk                          /*!< AES Suspend registers 1 */
5290 
5291 /*******************  Bit definition for AES_SUSP2R register  ******************/
5292 #define AES_SUSP2R_Pos                      (0U)
5293 #define AES_SUSP2R_Msk                      (0xFFFFFFFFUL << AES_SUSP2R_Pos)        /*!< 0xFFFFFFFF */
5294 #define AES_SUSP2R                          AES_SUSP2R_Msk                          /*!< AES Suspend registers 2 */
5295 
5296 /*******************  Bit definition for AES_SUSP3R register  ******************/
5297 #define AES_SUSP3R_Pos                      (0U)
5298 #define AES_SUSP3R_Msk                      (0xFFFFFFFFUL << AES_SUSP3R_Pos)        /*!< 0xFFFFFFFF */
5299 #define AES_SUSP3R                          AES_SUSP3R_Msk                          /*!< AES Suspend registers 3 */
5300 
5301 /*******************  Bit definition for AES_SUSP4R register  ******************/
5302 #define AES_SUSP4R_Pos                      (0U)
5303 #define AES_SUSP4R_Msk                      (0xFFFFFFFFUL << AES_SUSP4R_Pos)        /*!< 0xFFFFFFFF */
5304 #define AES_SUSP4R                          AES_SUSP4R_Msk                          /*!< AES Suspend registers 4 */
5305 
5306 /*******************  Bit definition for AES_SUSP5R register  ******************/
5307 #define AES_SUSP5R_Pos                      (0U)
5308 #define AES_SUSP5R_Msk                      (0xFFFFFFFFUL << AES_SUSP5R_Pos)        /*!< 0xFFFFFFFF */
5309 #define AES_SUSP5R                          AES_SUSP5R_Msk                          /*!< AES Suspend registers 5 */
5310 
5311 /*******************  Bit definition for AES_SUSP6R register  ******************/
5312 #define AES_SUSP6R_Pos                      (0U)
5313 #define AES_SUSP6R_Msk                      (0xFFFFFFFFUL << AES_SUSP6R_Pos)        /*!< 0xFFFFFFFF */
5314 #define AES_SUSP6R                          AES_SUSP6R_Msk                          /*!< AES Suspend registers 6 */
5315 
5316 /*******************  Bit definition for AES_SUSP7R register  ******************/
5317 #define AES_SUSP7R_Pos                      (0U)
5318 #define AES_SUSP7R_Msk                      (0xFFFFFFFFUL << AES_SUSP7R_Pos)        /*!< 0xFFFFFFFF */
5319 #define AES_SUSP7R                          AES_SUSP7R_Msk                          /*!< AES Suspend registers 7 */
5320 
5321 /*******************  Bit definition for AES_IER register     ******************/
5322 #define AES_IER_CCFIE_Pos                   (0U)
5323 #define AES_IER_CCFIE_Msk                   (0x1UL << AES_IER_CCFIE_Pos)            /*!< 0x00000001 */
5324 #define AES_IER_CCFIE                       AES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
5325 #define AES_IER_RWEIE_Pos                   (1U)
5326 #define AES_IER_RWEIE_Msk                   (0x1UL << AES_IER_RWEIE_Pos)            /*!< 0x00000002 */
5327 #define AES_IER_RWEIE                       AES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
5328 #define AES_IER_KEIE_Pos                    (2U)
5329 #define AES_IER_KEIE_Msk                    (0x1UL << AES_IER_KEIE_Pos)             /*!< 0x00000004 */
5330 #define AES_IER_KEIE                        AES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
5331 #define AES_IER_RNGEIE_Pos                  (3U)
5332 #define AES_IER_RNGEIE_Msk                  (0x1UL << AES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
5333 #define AES_IER_RNGEIE                      AES_IER_RNGEIE_Msk                      /*!< Rng error interrupt enable */
5334 
5335 /*******************  Bit definition for AES_ISR register     ******************/
5336 #define AES_ISR_CCF_Pos                     (0U)
5337 #define AES_ISR_CCF_Msk                     (0x1UL << AES_ISR_CCF_Pos)              /*!< 0x00000001 */
5338 #define AES_ISR_CCF                         AES_ISR_CCF_Msk                         /*!< Computation complete flag */
5339 #define AES_ISR_RWEIF_Pos                   (1U)
5340 #define AES_ISR_RWEIF_Msk                   (0x1UL << AES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
5341 #define AES_ISR_RWEIF                       AES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
5342 #define AES_ISR_KEIF_Pos                    (2U)
5343 #define AES_ISR_KEIF_Msk                    (0x1UL << AES_ISR_KEIF_Pos)             /*!< 0x00000004 */
5344 #define AES_ISR_KEIF                        AES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
5345 #define AES_ISR_RNGEIF_Pos                  (3U)
5346 #define AES_ISR_RNGEIF_Msk                  (0x1UL << AES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
5347 #define AES_ISR_RNGEIF                      AES_ISR_RNGEIF_Msk                      /*!< Rng error interrupt flag */
5348 
5349 /*******************  Bit definition for AES_ICR register     ******************/
5350 #define AES_ICR_CCF_Pos                     (0U)
5351 #define AES_ICR_CCF_Msk                     (0x1UL << AES_ICR_CCF_Pos)              /*!< 0x00000001 */
5352 #define AES_ICR_CCF                         AES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
5353 #define AES_ICR_RWEIF_Pos                   (1U)
5354 #define AES_ICR_RWEIF_Msk                   (0x1UL << AES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
5355 #define AES_ICR_RWEIF                       AES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
5356 #define AES_ICR_KEIF_Pos                    (2U)
5357 #define AES_ICR_KEIF_Msk                    (0x1UL << AES_ICR_KEIF_Pos)             /*!< 0x00000004 */
5358 #define AES_ICR_KEIF                        AES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
5359 #define AES_ICR_RNGEIF_Pos                  (3U)
5360 #define AES_ICR_RNGEIF_Msk                  (0x1UL << AES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
5361 #define AES_ICR_RNGEIF                       AES_ICR_RNGEIF_Msk                     /*!< Rng error interrupt flag clear */
5362 
5363 /*******************  Bit definition for AES_DPACFGR register     ******************/
5364 #define AES_DPACFGR_REDCFG_Pos              (0U)
5365 #define AES_DPACFGR_REDCFG_Msk              (0x3UL << AES_DPACFGR_REDCFG_Pos)       /*!< 0x00000003 */
5366 #define AES_DPACFGR_REDCFG                   AES_DPACFGR_REDCFG_Msk                 /*!< Redundancy configuration */
5367 #define AES_DPACFGR_RESEED_Pos              (2U)
5368 #define AES_DPACFGR_RESEED_Msk              (0x1UL << AES_DPACFGR_RESEED_Pos)       /*!< 0x00000004 */
5369 #define AES_DPACFGR_RESEED                   AES_DPACFGR_RESEED_Msk                 /*!< Automatic reseed */
5370 #define AES_DPACFGR_TRIMCFG_Pos             (3U)
5371 #define AES_DPACFGR_TRIMCFG_Msk             (0x3UL << AES_DPACFGR_TRIMCFG_Pos)       /*!< 0x00000001 */
5372 #define AES_DPACFGR_TRIMCFG                  AES_DPACFGR_TRIMCFG_Msk                 /*!< Redundancy configuration */
5373 #define AES_DPACFGR_CONFIGLOCK_Pos          (31U)
5374 #define AES_DPACFGR_CONFIGLOCK_Msk          (0x1UL << AES_DPACFGR_CONFIGLOCK_Pos)    /*!< 0x80000000 */
5375 #define AES_DPACFGR_CONFIGLOCK               AES_DPACFGR_CONFIGLOCK_Msk              /*!< DPA configuration lock */
5376 
5377 /******************************************************************************/
5378 /*                                                                            */
5379 /*                                    HASH                                    */
5380 /*                                                                            */
5381 /******************************************************************************/
5382 /******************  Bits definition for HASH_CR register  ********************/
5383 #define HASH_CR_INIT_Pos                    (2U)
5384 #define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
5385 #define HASH_CR_INIT                        HASH_CR_INIT_Msk
5386 #define HASH_CR_DMAE_Pos                    (3U)
5387 #define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
5388 #define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
5389 #define HASH_CR_DATATYPE_Pos                (4U)
5390 #define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
5391 #define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
5392 #define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
5393 #define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
5394 #define HASH_CR_MODE_Pos                    (6U)
5395 #define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
5396 #define HASH_CR_MODE                        HASH_CR_MODE_Msk
5397 #define HASH_CR_NBW_Pos                     (8U)
5398 #define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
5399 #define HASH_CR_NBW                         HASH_CR_NBW_Msk
5400 #define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
5401 #define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
5402 #define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
5403 #define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
5404 #define HASH_CR_DINNE_Pos                   (12U)
5405 #define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
5406 #define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
5407 #define HASH_CR_MDMAT_Pos                   (13U)
5408 #define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
5409 #define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
5410 #define HASH_CR_LKEY_Pos                    (16U)
5411 #define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
5412 #define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
5413 #define HASH_CR_ALGO_Pos                    (17U)
5414 #define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
5415 #define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
5416 #define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
5417 #define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
5418 #define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
5419 #define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
5420 
5421 /******************  Bits definition for HASH_STR register  *******************/
5422 #define HASH_STR_NBLW_Pos                   (0U)
5423 #define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
5424 #define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
5425 #define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
5426 #define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
5427 #define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
5428 #define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
5429 #define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
5430 #define HASH_STR_DCAL_Pos                   (8U)
5431 #define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
5432 #define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
5433 
5434 /******************  Bits definition for HASH_IMR register  *******************/
5435 #define HASH_IMR_DINIE_Pos                  (0U)
5436 #define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
5437 #define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
5438 #define HASH_IMR_DCIE_Pos                   (1U)
5439 #define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
5440 #define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
5441 
5442 /******************  Bits definition for HASH_SR register  ********************/
5443 #define HASH_SR_DINIS_Pos                   (0U)
5444 #define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
5445 #define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
5446 #define HASH_SR_DCIS_Pos                    (1U)
5447 #define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
5448 #define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
5449 #define HASH_SR_DMAS_Pos                    (2U)
5450 #define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
5451 #define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
5452 #define HASH_SR_BUSY_Pos                    (3U)
5453 #define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
5454 #define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
5455 #define HASH_SR_NBWE_Pos                    (16U)
5456 #define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
5457 #define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
5458 #define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
5459 #define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
5460 #define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
5461 #define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
5462 #define HASH_SR_DINNE_Pos                   (15U)
5463 #define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
5464 #define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
5465 #define HASH_SR_NBWP_Pos                    (9U)
5466 #define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
5467 #define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
5468 #define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
5469 #define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
5470 #define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
5471 #define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
5472 
5473 
5474 /******************************************************************************/
5475 /*                                                                            */
5476 /*                                 Debug MCU                                  */
5477 /*                                                                            */
5478 /******************************************************************************/
5479 /********************  Bit definition for DBGMCU_IDCODE register  *************/
5480 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
5481 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)   /*!< 0x00000FFF */
5482 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk
5483 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
5484 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)  /*!< 0xFFFF0000 */
5485 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk
5486 
5487 /********************  Bit definition for DBGMCU_CR register  *****************/
5488 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
5489 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)       /*!< 0x00000002 */
5490 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk
5491 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
5492 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)    /*!< 0x00000004 */
5493 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk
5494 #define DBGMCU_CR_TRACE_IOEN_Pos            (4U)
5495 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)     /*!< 0x00000010 */
5496 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk
5497 #define DBGMCU_CR_TRACE_CLKEN_Pos           (5U)
5498 #define DBGMCU_CR_TRACE_CLKEN_Msk           (0x1UL << DBGMCU_CR_TRACE_CLKEN_Pos)    /*!< 0x00000020 */
5499 #define DBGMCU_CR_TRACE_CLKEN               DBGMCU_CR_TRACE_CLKEN_Msk
5500 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
5501 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x000000C0 */
5502 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk
5503 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000040 */
5504 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000080 */
5505 #define DBGMCU_CR_DCRT_Pos                  (16U)
5506 #define DBGMCU_CR_DCRT_Msk                  (0x1UL << DBGMCU_CR_DCRT_Pos)           /*!< 0x00010000 */
5507 #define DBGMCU_CR_DCRT                      DBGMCU_CR_DCRT_Msk
5508 
5509 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
5510 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0U)
5511 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
5512 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
5513 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1U)
5514 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
5515 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
5516 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos   (2U)
5517 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
5518 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP       DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
5519 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos   (3U)
5520 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
5521 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP       DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
5522 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4U)
5523 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
5524 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
5525 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5U)
5526 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
5527 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
5528 #define DBGMCU_APB1FZR1_DBG_TIM12_STOP_Pos  (6U)
5529 #define DBGMCU_APB1FZR1_DBG_TIM12_STOP_Msk  (0x1UL << DBGMCU_APB1FZR1_DBG_TIM12_STOP_Pos)
5530 #define DBGMCU_APB1FZR1_DBG_TIM12_STOP      DBGMCU_APB1FZR1_DBG_TIM12_STOP_Msk
5531 #define DBGMCU_APB1FZR1_DBG_TIM13_STOP_Pos  (7U)
5532 #define DBGMCU_APB1FZR1_DBG_TIM13_STOP_Msk  (0x1UL << DBGMCU_APB1FZR1_DBG_TIM13_STOP_Pos)
5533 #define DBGMCU_APB1FZR1_DBG_TIM13_STOP      DBGMCU_APB1FZR1_DBG_TIM13_STOP_Msk
5534 #define DBGMCU_APB1FZR1_DBG_TIM14_STOP_Pos  (8U)
5535 #define DBGMCU_APB1FZR1_DBG_TIM14_STOP_Msk  (0x1UL << DBGMCU_APB1FZR1_DBG_TIM14_STOP_Pos)
5536 #define DBGMCU_APB1FZR1_DBG_TIM14_STOP      DBGMCU_APB1FZR1_DBG_TIM14_STOP_Msk
5537 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11U)
5538 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
5539 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
5540 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12U)
5541 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
5542 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
5543 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21U)
5544 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
5545 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
5546 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22U)
5547 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
5548 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
5549 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos   (23U)
5550 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos)
5551 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP       DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk
5552 
5553 /********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
5554 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
5555 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
5556 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
5557 
5558 /********************  Bit definition for DBGMCU_APB2FZR register  ***********/
5559 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos    (11U)
5560 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)
5561 #define DBGMCU_APB2FZR_DBG_TIM1_STOP        DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
5562 #define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos    (13U)
5563 #define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)
5564 #define DBGMCU_APB2FZR_DBG_TIM8_STOP        DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk
5565 #define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos   (16U)
5566 #define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)
5567 #define DBGMCU_APB2FZR_DBG_TIM15_STOP       DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk
5568 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos   (17U)
5569 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)
5570 #define DBGMCU_APB2FZR_DBG_TIM16_STOP       DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
5571 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos   (18U)
5572 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)
5573 #define DBGMCU_APB2FZR_DBG_TIM17_STOP       DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
5574 
5575 /********************  Bit definition for DBGMCU_APB3FZR register  ***********/
5576 #define DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos    (10U)
5577 #define DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos)
5578 #define DBGMCU_APB3FZR_DBG_I2C3_STOP        DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk
5579 #define DBGMCU_APB3FZR_DBG_I2C4_STOP_Pos    (11U)
5580 #define DBGMCU_APB3FZR_DBG_I2C4_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I2C4_STOP_Pos)
5581 #define DBGMCU_APB3FZR_DBG_I2C4_STOP        DBGMCU_APB3FZR_DBG_I2C4_STOP_Msk
5582 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos  (17U)
5583 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)
5584 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP      DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk
5585 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos  (18U)
5586 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos)
5587 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP      DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk
5588 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos  (19U)
5589 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos)
5590 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP      DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk
5591 #define DBGMCU_APB3FZR_DBG_LPTIM5_STOP_Pos  (20U)
5592 #define DBGMCU_APB3FZR_DBG_LPTIM5_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM5_STOP_Pos)
5593 #define DBGMCU_APB3FZR_DBG_LPTIM5_STOP      DBGMCU_APB3FZR_DBG_LPTIM5_STOP_Msk
5594 #define DBGMCU_APB3FZR_DBG_LPTIM6_STOP_Pos  (21U)
5595 #define DBGMCU_APB3FZR_DBG_LPTIM6_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM6_STOP_Pos)
5596 #define DBGMCU_APB3FZR_DBG_LPTIM6_STOP      DBGMCU_APB3FZR_DBG_LPTIM6_STOP_Msk
5597 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos     (30U)
5598 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk     (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos)
5599 #define DBGMCU_APB3FZR_DBG_RTC_STOP         DBGMCU_APB3FZR_DBG_RTC_STOP_Msk
5600 
5601 /********************  Bit definition for DBGMCU_AHB1FZR register  ***********/
5602 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos  (0U)
5603 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos)
5604 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk
5605 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos  (1U)
5606 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos)
5607 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk
5608 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos  (2U)
5609 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos)
5610 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk
5611 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos  (3U)
5612 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos)
5613 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk
5614 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos  (4U)
5615 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos)
5616 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk
5617 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos  (5U)
5618 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos)
5619 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk
5620 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos  (6U)
5621 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos)
5622 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk
5623 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos  (7U)
5624 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos)
5625 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk
5626 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos  (8U)
5627 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos)
5628 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk
5629 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos  (9U)
5630 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos)
5631 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk
5632 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos (10U)
5633 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos)
5634 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk
5635 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos (11U)
5636 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos)
5637 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk
5638 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos (12U)
5639 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos)
5640 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk
5641 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos (13U)
5642 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos)
5643 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk
5644 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos (14U)
5645 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos)
5646 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk
5647 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos (15U)
5648 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos)
5649 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk
5650 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos  (16U)
5651 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos)
5652 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk
5653 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos (17U)
5654 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos)
5655 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk
5656 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos (18U)
5657 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos)
5658 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk
5659 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos (19U)
5660 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos)
5661 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk
5662 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos (20U)
5663 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos)
5664 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk
5665 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos (21U)
5666 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos)
5667 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk
5668 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos (22U)
5669 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos)
5670 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk
5671 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos (23U)
5672 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos)
5673 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk
5674 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos (24U)
5675 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos)
5676 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk
5677 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos (25U)
5678 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos)
5679 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk
5680 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos (26U)
5681 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos)
5682 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk
5683 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos (27U)
5684 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos)
5685 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk
5686 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos (28U)
5687 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos)
5688 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk
5689 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos (29U)
5690 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos)
5691 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk
5692 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos (30U)
5693 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos)
5694 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk
5695 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos (31U)
5696 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos)
5697 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk
5698 
5699 /********************  Bit definition for DBGMCU_SR register  ***********/
5700 #define DBGMCU_SR_ACC_PORT_PRES_Pos          (0U)
5701 #define DBGMCU_SR_ACC_PORT_PRES_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_PRES_Pos)   /*!< 0x0000FFFF */
5702 #define DBGMCU_SR_ACC_PORT_PRES              DBGMCU_SR_ACC_PORT_PRES_Msk
5703 #define DBGMCU_SR_ACC_PORT_ENBL_Pos          (16U)
5704 #define DBGMCU_SR_ACC_PORT_ENBL_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_ENBL_Pos)   /*!< 0xFFFF0000 */
5705 #define DBGMCU_SR_ACC_PORT_ENBL              DBGMCU_SR_ACC_PORT_ENBL_Msk
5706 
5707 /********************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ***********/
5708 #define DBGMCU_DBG_AUTH_HOST_Pos             (0U)
5709 #define DBGMCU_DBG_AUTH_HOST_Msk             (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_Pos)  /*!< 0xFFFFFFFF */
5710 #define DBGMCU_DBG_AUTH_HOST                 DBGMCU_DBG_AUTH_HOST_Msk
5711 
5712 /********************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
5713 #define DBGMCU_DBG_AUTH_DEV_Pos              (0U)
5714 #define DBGMCU_DBG_AUTH_DEV_Msk              (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_Pos)   /*!< 0xFFFFFFFF */
5715 #define DBGMCU_DBG_AUTH_DEV                  DBGMCU_DBG_AUTH_DEV_Msk
5716 
5717 /********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***********/
5718 #define DBGMCU_DBG_AUTH_ACK_HOST_Pos         (0U)
5719 #define DBGMCU_DBG_AUTH_ACK_HOST_Msk         (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_Pos)     /*!< 0x00000001 */
5720 #define DBGMCU_DBG_AUTH_ACK_HOST             DBGMCU_DBG_AUTH_ACK_HOST_Msk
5721 #define DBGMCU_DBG_AUTH_ACK_DEV_Pos          (1U)
5722 #define DBGMCU_DBG_AUTH_ACK_DEV_Msk          (0x1UL << DBGMCU_DBG_AUTH_ACK_DEV_Pos)      /*!< 0x00000002 */
5723 #define DBGMCU_DBG_AUTH_ACK_DEV              DBGMCU_DBG_AUTH_ACK_DEV_Msk
5724 
5725 /********************  Bit definition for DBGMCU_PIDR4 register  ************/
5726 #define DBGMCU_PIDR4_JEP106CON_Pos           (0U)
5727 #define DBGMCU_PIDR4_JEP106CON_Msk           (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)    /*!< 0x0000000F */
5728 #define DBGMCU_PIDR4_JEP106CON               DBGMCU_PIDR4_JEP106CON_Msk
5729 #define DBGMCU_PIDR4_4KCOUNT_Pos             (4U)
5730 #define DBGMCU_PIDR4_4KCOUNT_Msk             (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)      /*!< 0x000000F0 */
5731 #define DBGMCU_PIDR4_4KCOUNT                 DBGMCU_PIDR4_4KCOUNT_Msk
5732 
5733 /********************  Bit definition for DBGMCU_PIDR0 register  ************/
5734 #define DBGMCU_PIDR0_PARTNUM_Pos             (0U)
5735 #define DBGMCU_PIDR0_PARTNUM_Msk             (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)     /*!< 0x000000FF */
5736 #define DBGMCU_PIDR0_PARTNUM                 DBGMCU_PIDR0_PARTNUM_Msk
5737 
5738 /********************  Bit definition for DBGMCU_PIDR1 register  ************/
5739 #define DBGMCU_PIDR1_PARTNUM_Pos             (0U)
5740 #define DBGMCU_PIDR1_PARTNUM_Msk             (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)      /*!< 0x0000000F */
5741 #define DBGMCU_PIDR1_PARTNUM                 DBGMCU_PIDR1_PARTNUM_Msk
5742 #define DBGMCU_PIDR1_JEP106ID_Pos            (4U)
5743 #define DBGMCU_PIDR1_JEP106ID_Msk            (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)     /*!< 0x000000F0 */
5744 #define DBGMCU_PIDR1_JEP106ID                DBGMCU_PIDR1_JEP106ID_Msk
5745 
5746 /********************  Bit definition for DBGMCU_PIDR2 register  ************/
5747 #define DBGMCU_PIDR2_JEP106ID_Pos            (0U)
5748 #define DBGMCU_PIDR2_JEP106ID_Msk            (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)     /*!< 0x00000007 */
5749 #define DBGMCU_PIDR2_JEP106ID                DBGMCU_PIDR2_JEP106ID_Msk
5750 #define DBGMCU_PIDR2_JEDEC_Pos               (3U)
5751 #define DBGMCU_PIDR2_JEDEC_Msk               (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)        /*!< 0x00000008 */
5752 #define DBGMCU_PIDR2_JEDEC                   DBGMCU_PIDR2_JEDEC_Msk
5753 #define DBGMCU_PIDR2_REVISION_Pos            (4U)
5754 #define DBGMCU_PIDR2_REVISION_Msk            (0xFUL << DBGMCU_PIDR2_REVISION_Pos)     /*!< 0x000000F0 */
5755 #define DBGMCU_PIDR2_REVISION                DBGMCU_PIDR2_REVISION_Msk
5756 
5757 /********************  Bit definition for DBGMCU_PIDR3 register  ************/
5758 #define DBGMCU_PIDR3_CMOD_Pos                (0U)
5759 #define DBGMCU_PIDR3_CMOD_Msk                (0xFUL << DBGMCU_PIDR3_CMOD_Pos)         /*!< 0x0000000F */
5760 #define DBGMCU_PIDR3_CMOD                    DBGMCU_PIDR3_CMOD_Msk
5761 #define DBGMCU_PIDR3_REVAND_Pos              (4U)
5762 #define DBGMCU_PIDR3_REVAND_Msk              (0xFUL << DBGMCU_PIDR3_REVAND_Pos)       /*!< 0x000000F0 */
5763 #define DBGMCU_PIDR3_REVAND                  DBGMCU_PIDR3_REVAND_Msk
5764 
5765 /********************  Bit definition for DBGMCU_CIDR0 register  ************/
5766 #define DBGMCU_CIDR0_PREAMBLE_Pos            (0U)
5767 #define DBGMCU_CIDR0_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)    /*!< 0x000000FF */
5768 #define DBGMCU_CIDR0_PREAMBLE                DBGMCU_CIDR0_PREAMBLE_Msk
5769 
5770 /********************  Bit definition for DBGMCU_CIDR1 register  ************/
5771 #define DBGMCU_CIDR1_PREAMBLE_Pos            (0U)
5772 #define DBGMCU_CIDR1_PREAMBLE_Msk            (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)     /*!< 0x0000000F */
5773 #define DBGMCU_CIDR1_PREAMBLE                DBGMCU_CIDR1_PREAMBLE_Msk
5774 #define DBGMCU_CIDR1_CLASS_Pos               (4U)
5775 #define DBGMCU_CIDR1_CLASS_Msk               (0xFUL << DBGMCU_CIDR1_CLASS_Pos)        /*!< 0x000000F0 */
5776 #define DBGMCU_CIDR1_CLASS                   DBGMCU_CIDR1_CLASS_Msk
5777 
5778 /********************  Bit definition for DBGMCU_CIDR2 register  ************/
5779 #define DBGMCU_CIDR2_PREAMBLE_Pos            (0U)
5780 #define DBGMCU_CIDR2_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)    /*!< 0x000000FF */
5781 #define DBGMCU_CIDR2_PREAMBLE                DBGMCU_CIDR2_PREAMBLE_Msk
5782 
5783 /********************  Bit definition for DBGMCU_CIDR3 register  ************/
5784 #define DBGMCU_CIDR3_PREAMBLE_Pos            (0U)
5785 #define DBGMCU_CIDR3_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)    /*!< 0x000000FF */
5786 #define DBGMCU_CIDR3_PREAMBLE                DBGMCU_CIDR3_PREAMBLE_Msk
5787 /******************************************************************************/
5788 /*                                                                            */
5789 /*                                    DCMI                                    */
5790 /*                                                                            */
5791 /******************************************************************************/
5792 /********************  Bits definition for DCMI_CR register  ******************/
5793 #define DCMI_CR_CAPTURE_Pos                 (0U)
5794 #define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
5795 #define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
5796 #define DCMI_CR_CM_Pos                      (1U)
5797 #define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
5798 #define DCMI_CR_CM                          DCMI_CR_CM_Msk
5799 #define DCMI_CR_CROP_Pos                    (2U)
5800 #define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
5801 #define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
5802 #define DCMI_CR_JPEG_Pos                    (3U)
5803 #define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
5804 #define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
5805 #define DCMI_CR_ESS_Pos                     (4U)
5806 #define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
5807 #define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
5808 #define DCMI_CR_PCKPOL_Pos                  (5U)
5809 #define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
5810 #define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
5811 #define DCMI_CR_HSPOL_Pos                   (6U)
5812 #define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
5813 #define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
5814 #define DCMI_CR_VSPOL_Pos                   (7U)
5815 #define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
5816 #define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
5817 #define DCMI_CR_FCRC_Pos                    (8U)
5818 #define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
5819 #define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
5820 #define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
5821 #define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
5822 #define DCMI_CR_EDM_Pos                     (10U)
5823 #define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
5824 #define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
5825 #define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
5826 #define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
5827 #define DCMI_CR_ENABLE_Pos                  (14U)
5828 #define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
5829 #define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
5830 #define DCMI_CR_BSM_Pos                     (16U)
5831 #define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
5832 #define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
5833 #define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
5834 #define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
5835 #define DCMI_CR_OEBS_Pos                    (18U)
5836 #define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
5837 #define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
5838 #define DCMI_CR_LSM_Pos                     (19U)
5839 #define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
5840 #define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
5841 #define DCMI_CR_OELS_Pos                    (20U)
5842 #define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
5843 #define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
5844 #define DCMI_CR_PSDM_Pos                    (31U)
5845 #define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
5846 #define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
5847 
5848 /********************  Bits definition for DCMI_SR register  ******************/
5849 #define DCMI_SR_HSYNC_Pos                   (0U)
5850 #define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
5851 #define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
5852 #define DCMI_SR_VSYNC_Pos                   (1U)
5853 #define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
5854 #define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
5855 #define DCMI_SR_FNE_Pos                     (2U)
5856 #define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
5857 #define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
5858 
5859 /********************  Bits definition for DCMI_RIS register   ****************/
5860 #define DCMI_RIS_FRAME_RIS_Pos              (0U)
5861 #define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
5862 #define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
5863 #define DCMI_RIS_OVR_RIS_Pos                (1U)
5864 #define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
5865 #define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
5866 #define DCMI_RIS_ERR_RIS_Pos                (2U)
5867 #define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
5868 #define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
5869 #define DCMI_RIS_VSYNC_RIS_Pos              (3U)
5870 #define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
5871 #define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
5872 #define DCMI_RIS_LINE_RIS_Pos               (4U)
5873 #define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
5874 #define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
5875 
5876 /********************  Bits definition for DCMI_IER register  *****************/
5877 #define DCMI_IER_FRAME_IE_Pos               (0U)
5878 #define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
5879 #define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
5880 #define DCMI_IER_OVR_IE_Pos                 (1U)
5881 #define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
5882 #define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
5883 #define DCMI_IER_ERR_IE_Pos                 (2U)
5884 #define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
5885 #define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
5886 #define DCMI_IER_VSYNC_IE_Pos               (3U)
5887 #define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
5888 #define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
5889 #define DCMI_IER_LINE_IE_Pos                (4U)
5890 #define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
5891 #define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
5892 
5893 
5894 /********************  Bits definition for DCMI_MIS register  *****************/
5895 #define DCMI_MIS_FRAME_MIS_Pos              (0U)
5896 #define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
5897 #define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
5898 #define DCMI_MIS_OVR_MIS_Pos                (1U)
5899 #define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
5900 #define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
5901 #define DCMI_MIS_ERR_MIS_Pos                (2U)
5902 #define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
5903 #define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
5904 #define DCMI_MIS_VSYNC_MIS_Pos              (3U)
5905 #define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
5906 #define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
5907 #define DCMI_MIS_LINE_MIS_Pos               (4U)
5908 #define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
5909 #define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
5910 
5911 
5912 /********************  Bits definition for DCMI_ICR register  *****************/
5913 #define DCMI_ICR_FRAME_ISC_Pos              (0U)
5914 #define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
5915 #define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
5916 #define DCMI_ICR_OVR_ISC_Pos                (1U)
5917 #define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
5918 #define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
5919 #define DCMI_ICR_ERR_ISC_Pos                (2U)
5920 #define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
5921 #define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
5922 #define DCMI_ICR_VSYNC_ISC_Pos              (3U)
5923 #define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
5924 #define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
5925 #define DCMI_ICR_LINE_ISC_Pos               (4U)
5926 #define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
5927 #define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
5928 
5929 
5930 /********************  Bits definition for DCMI_ESCR register  ******************/
5931 #define DCMI_ESCR_FSC_Pos                   (0U)
5932 #define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
5933 #define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
5934 #define DCMI_ESCR_LSC_Pos                   (8U)
5935 #define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
5936 #define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
5937 #define DCMI_ESCR_LEC_Pos                   (16U)
5938 #define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
5939 #define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
5940 #define DCMI_ESCR_FEC_Pos                   (24U)
5941 #define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
5942 #define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
5943 
5944 /********************  Bits definition for DCMI_ESUR register  ******************/
5945 #define DCMI_ESUR_FSU_Pos                   (0U)
5946 #define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
5947 #define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
5948 #define DCMI_ESUR_LSU_Pos                   (8U)
5949 #define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
5950 #define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
5951 #define DCMI_ESUR_LEU_Pos                   (16U)
5952 #define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
5953 #define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
5954 #define DCMI_ESUR_FEU_Pos                   (24U)
5955 #define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
5956 #define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
5957 
5958 /********************  Bits definition for DCMI_CWSTRT register  ******************/
5959 #define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
5960 #define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
5961 #define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
5962 #define DCMI_CWSTRT_VST_Pos                 (16U)
5963 #define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
5964 #define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
5965 
5966 /********************  Bits definition for DCMI_CWSIZE register  ******************/
5967 #define DCMI_CWSIZE_CAPCNT_Pos              (0U)
5968 #define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
5969 #define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
5970 #define DCMI_CWSIZE_VLINE_Pos               (16U)
5971 #define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
5972 #define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
5973 
5974 /********************  Bits definition for DCMI_DR register  ******************/
5975 #define DCMI_DR_BYTE0_Pos                   (0U)
5976 #define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
5977 #define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
5978 #define DCMI_DR_BYTE1_Pos                   (8U)
5979 #define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
5980 #define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
5981 #define DCMI_DR_BYTE2_Pos                   (16U)
5982 #define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
5983 #define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
5984 #define DCMI_DR_BYTE3_Pos                   (24U)
5985 #define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
5986 #define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
5987 /******************************************************************************/
5988 /*                                                                            */
5989 /*                Ethernet MAC Registers bits definitions                     */
5990 /*                                                                            */
5991 /******************************************************************************/
5992 /* Bit definition for Ethernet MAC Configuration Register register */
5993 #define ETH_MACCR_ARP_Pos                             (31U)
5994 #define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
5995 #define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
5996 #define ETH_MACCR_SARC_Pos                            (28U)
5997 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
5998 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
5999 #define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6000 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
6001 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
6002 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6003 #define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
6004 #define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
6005 #define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6006 #define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
6007 #define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
6008 #define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6009 #define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
6010 #define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
6011 #define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6012 #define ETH_MACCR_IPC_Pos                             (27U)
6013 #define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
6014 #define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
6015 #define ETH_MACCR_IPG_Pos                             (24U)
6016 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
6017 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
6018 #define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
6019 #define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
6020 #define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
6021 #define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
6022 #define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
6023 #define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
6024 #define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
6025 #define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
6026 #define ETH_MACCR_GPSLCE_Pos                          (23U)
6027 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
6028 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
6029 #define ETH_MACCR_S2KP_Pos                            (22U)
6030 #define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
6031 #define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
6032 #define ETH_MACCR_CST_Pos                             (21U)
6033 #define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
6034 #define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
6035 #define ETH_MACCR_ACS_Pos                             (20U)
6036 #define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
6037 #define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
6038 #define ETH_MACCR_WD_Pos                              (19U)
6039 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
6040 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
6041 #define ETH_MACCR_JD_Pos                              (17U)
6042 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
6043 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
6044 #define ETH_MACCR_JE_Pos                              (16U)
6045 #define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
6046 #define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
6047 #define ETH_MACCR_FES_Pos                             (14U)
6048 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
6049 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
6050 #define ETH_MACCR_DM_Pos                              (13U)
6051 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
6052 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
6053 #define ETH_MACCR_LM_Pos                              (12U)
6054 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
6055 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
6056 #define ETH_MACCR_ECRSFD_Pos                          (11U)
6057 #define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
6058 #define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6059 #define ETH_MACCR_DO_Pos                              (10U)
6060 #define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
6061 #define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
6062 #define ETH_MACCR_DCRS_Pos                            (9U)
6063 #define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
6064 #define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
6065 #define ETH_MACCR_DR_Pos                              (8U)
6066 #define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
6067 #define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
6068 #define ETH_MACCR_BL_Pos                              (5U)
6069 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6070 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
6071 #define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
6072 #define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
6073 #define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
6074 #define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6075 #define ETH_MACCR_DC_Pos                              (4U)
6076 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
6077 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
6078 #define ETH_MACCR_PRELEN_Pos                          (2U)
6079 #define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
6080 #define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
6081 #define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
6082 #define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
6083 #define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
6084 #define ETH_MACCR_TE_Pos                              (1U)
6085 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
6086 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
6087 #define ETH_MACCR_RE_Pos                              (0U)
6088 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
6089 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
6090 
6091 /* Bit definition for Ethernet MAC Extended Configuration Register register */
6092 #define ETH_MACECR_EIPG_Pos                           (25U)
6093 #define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
6094 #define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
6095 #define ETH_MACECR_EIPGEN_Pos                         (24U)
6096 #define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
6097 #define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
6098 #define ETH_MACECR_USP_Pos                            (18U)
6099 #define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
6100 #define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
6101 #define ETH_MACECR_SPEN_Pos                           (17U)
6102 #define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
6103 #define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
6104 #define ETH_MACECR_DCRCC_Pos                          (16U)
6105 #define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
6106 #define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
6107 #define ETH_MACECR_GPSL_Pos                           (0U)
6108 #define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
6109 #define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
6110 
6111 /* Bit definition for Ethernet MAC Packet Filter Register */
6112 #define ETH_MACPFR_RA_Pos                             (31U)
6113 #define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
6114 #define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
6115 #define ETH_MACPFR_DNTU_Pos                           (21U)
6116 #define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
6117 #define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
6118 #define ETH_MACPFR_IPFE_Pos                           (20U)
6119 #define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
6120 #define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
6121 #define ETH_MACPFR_VTFE_Pos                           (16U)
6122 #define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
6123 #define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
6124 #define ETH_MACPFR_HPF_Pos                            (10U)
6125 #define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
6126 #define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
6127 #define ETH_MACPFR_SAF_Pos                            (9U)
6128 #define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
6129 #define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
6130 #define ETH_MACPFR_SAIF_Pos                           (8U)
6131 #define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
6132 #define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
6133 #define ETH_MACPFR_PCF_Pos                            (6U)
6134 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
6135 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
6136 #define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
6137 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
6138 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
6139 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6140 #define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
6141 #define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
6142 #define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6143 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
6144 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
6145 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6146 #define ETH_MACPFR_DBF_Pos                            (5U)
6147 #define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
6148 #define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
6149 #define ETH_MACPFR_PM_Pos                             (4U)
6150 #define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
6151 #define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
6152 #define ETH_MACPFR_DAIF_Pos                           (3U)
6153 #define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
6154 #define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
6155 #define ETH_MACPFR_HMC_Pos                            (2U)
6156 #define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
6157 #define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
6158 #define ETH_MACPFR_HUC_Pos                            (1U)
6159 #define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
6160 #define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
6161 #define ETH_MACPFR_PR_Pos                             (0U)
6162 #define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
6163 #define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
6164 
6165 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
6166 #define ETH_MACWTR_PWE_Pos                            (8U)
6167 #define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
6168 #define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
6169 #define ETH_MACWTR_WTO_Pos                            (0U)
6170 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
6171 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
6172 #define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
6173 #define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
6174 #define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
6175 #define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
6176 #define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
6177 #define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
6178 #define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
6179 #define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
6180 #define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
6181 #define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
6182 #define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
6183 #define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
6184 #define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
6185 #define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
6186 #define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
6187 
6188 /* Bit definition for Ethernet MAC Hash Table High Register */
6189 #define ETH_MACHTHR_HTH_Pos                           (0U)
6190 #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
6191 #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
6192 
6193 /* Bit definition for Ethernet MAC Hash Table Low Register */
6194 #define ETH_MACHTLR_HTL_Pos                           (0U)
6195 #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
6196 #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
6197 
6198 /* Bit definition for Ethernet MAC VLAN Tag Register */
6199 #define ETH_MACVTR_EIVLRXS_Pos                        (31U)
6200 #define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
6201 #define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
6202 #define ETH_MACVTR_EIVLS_Pos                          (28U)
6203 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
6204 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
6205 #define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
6206 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
6207 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
6208 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6209 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
6210 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
6211 #define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6212 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
6213 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
6214 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
6215 #define ETH_MACVTR_ERIVLT_Pos                         (27U)
6216 #define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
6217 #define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
6218 #define ETH_MACVTR_EDVLP_Pos                          (26U)
6219 #define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
6220 #define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
6221 #define ETH_MACVTR_VTHM_Pos                           (25U)
6222 #define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
6223 #define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
6224 #define ETH_MACVTR_EVLRXS_Pos                         (24U)
6225 #define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
6226 #define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
6227 #define ETH_MACVTR_EVLS_Pos                           (21U)
6228 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
6229 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
6230 #define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
6231 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
6232 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
6233 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6234 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
6235 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
6236 #define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6237 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
6238 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
6239 #define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
6240 #define ETH_MACVTR_DOVLTC_Pos                         (20U)
6241 #define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
6242 #define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
6243 #define ETH_MACVTR_ERSVLM_Pos                         (19U)
6244 #define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
6245 #define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
6246 #define ETH_MACVTR_ESVL_Pos                           (18U)
6247 #define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
6248 #define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
6249 #define ETH_MACVTR_VTIM_Pos                           (17U)
6250 #define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
6251 #define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
6252 #define ETH_MACVTR_ETV_Pos                            (16U)
6253 #define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
6254 #define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
6255 #define ETH_MACVTR_VL_Pos                             (0U)
6256 #define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
6257 #define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
6258 #define ETH_MACVTR_VL_UP_Pos                          (13U)
6259 #define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
6260 #define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
6261 #define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
6262 #define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
6263 #define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6264 #define ETH_MACVTR_VL_VID_Pos                         (0U)
6265 #define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
6266 #define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
6267 
6268 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
6269 #define ETH_MACVHTR_VLHT_Pos                          (0U)
6270 #define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
6271 #define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
6272 
6273 /* Bit definition for Ethernet MAC VLAN Incl Register */
6274 #define ETH_MACVIR_VLTI_Pos                           (20U)
6275 #define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
6276 #define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
6277 #define ETH_MACVIR_CSVL_Pos                           (19U)
6278 #define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
6279 #define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
6280 #define ETH_MACVIR_VLP_Pos                            (18U)
6281 #define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
6282 #define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
6283 #define ETH_MACVIR_VLC_Pos                            (16U)
6284 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
6285 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
6286 #define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
6287 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
6288 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6289 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6290 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
6291 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6292 #define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6293 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
6294 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6295 #define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6296 #define ETH_MACVIR_VLT_Pos                            (0U)
6297 #define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
6298 #define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
6299 #define ETH_MACVIR_VLT_UP_Pos                         (13U)
6300 #define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6301 #define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
6302 #define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
6303 #define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6304 #define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6305 #define ETH_MACVIR_VLT_VID_Pos                        (0U)
6306 #define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6307 #define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
6308 
6309 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
6310 #define ETH_MACIVIR_VLTI_Pos                          (20U)
6311 #define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
6312 #define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
6313 #define ETH_MACIVIR_CSVL_Pos                          (19U)
6314 #define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
6315 #define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
6316 #define ETH_MACIVIR_VLP_Pos                           (18U)
6317 #define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
6318 #define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
6319 #define ETH_MACIVIR_VLC_Pos                           (16U)
6320 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
6321 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
6322 #define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
6323 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
6324 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6325 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6326 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
6327 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6328 #define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6329 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
6330 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6331 #define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6332 #define ETH_MACIVIR_VLT_Pos                           (0U)
6333 #define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
6334 #define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
6335 #define ETH_MACIVIR_VLT_UP_Pos                        (13U)
6336 #define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6337 #define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
6338 #define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
6339 #define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6340 #define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6341 #define ETH_MACIVIR_VLT_VID_Pos                       (0U)
6342 #define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6343 #define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
6344 
6345 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
6346 #define ETH_MACTFCR_PT_Pos                            (16U)
6347 #define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
6348 #define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
6349 #define ETH_MACTFCR_DZPQ_Pos                          (7U)
6350 #define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
6351 #define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
6352 #define ETH_MACTFCR_PLT_Pos                           (4U)
6353 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
6354 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
6355 #define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
6356 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
6357 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
6358 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
6359 #define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
6360 #define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
6361 #define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
6362 #define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
6363 #define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
6364 #define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
6365 #define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
6366 #define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
6367 #define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
6368 #define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
6369 #define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
6370 #define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
6371 #define ETH_MACTFCR_TFE_Pos                           (1U)
6372 #define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
6373 #define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
6374 #define ETH_MACTFCR_FCB_Pos                           (0U)
6375 #define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
6376 #define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
6377 
6378 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
6379 #define ETH_MACRFCR_UP_Pos                            (1U)
6380 #define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
6381 #define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
6382 #define ETH_MACRFCR_RFE_Pos                           (0U)
6383 #define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
6384 #define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
6385 
6386 /* Bit definition for Ethernet MAC Interrupt Status Register */
6387 #define ETH_MACISR_RXSTSIS_Pos                        (14U)
6388 #define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
6389 #define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
6390 #define ETH_MACISR_TXSTSIS_Pos                        (13U)
6391 #define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
6392 #define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
6393 #define ETH_MACISR_TSIS_Pos                           (12U)
6394 #define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
6395 #define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
6396 #define ETH_MACISR_MMCTXIS_Pos                        (10U)
6397 #define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
6398 #define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
6399 #define ETH_MACISR_MMCRXIS_Pos                        (9U)
6400 #define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
6401 #define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
6402 #define ETH_MACISR_MMCIS_Pos                          (8U)
6403 #define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
6404 #define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
6405 #define ETH_MACISR_LPIIS_Pos                          (5U)
6406 #define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
6407 #define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
6408 #define ETH_MACISR_PMTIS_Pos                          (4U)
6409 #define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
6410 #define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
6411 #define ETH_MACISR_PHYIS_Pos                          (3U)
6412 #define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
6413 #define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
6414 
6415 /* Bit definition for Ethernet MAC Interrupt Enable Register */
6416 #define ETH_MACIER_RXSTSIE_Pos                        (14U)
6417 #define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
6418 #define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
6419 #define ETH_MACIER_TXSTSIE_Pos                        (13U)
6420 #define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
6421 #define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
6422 #define ETH_MACIER_TSIE_Pos                           (12U)
6423 #define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
6424 #define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
6425 #define ETH_MACIER_LPIIE_Pos                          (5U)
6426 #define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
6427 #define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
6428 #define ETH_MACIER_PMTIE_Pos                          (4U)
6429 #define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
6430 #define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
6431 #define ETH_MACIER_PHYIE_Pos                          (3U)
6432 #define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
6433 #define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
6434 
6435 /* Bit definition for Ethernet MAC Rx Tx Status Register */
6436 #define ETH_MACRXTXSR_RWT_Pos                         (8U)
6437 #define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
6438 #define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
6439 #define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
6440 #define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
6441 #define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
6442 #define ETH_MACRXTXSR_LCOL_Pos                        (4U)
6443 #define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
6444 #define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
6445 #define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
6446 #define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
6447 #define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
6448 #define ETH_MACRXTXSR_LCARR_Pos                       (2U)
6449 #define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
6450 #define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
6451 #define ETH_MACRXTXSR_NCARR_Pos                       (1U)
6452 #define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
6453 #define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
6454 #define ETH_MACRXTXSR_TJT_Pos                         (0U)
6455 #define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
6456 #define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
6457 
6458 /* Bit definition for Ethernet MAC PMT Control Status Register */
6459 #define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
6460 #define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
6461 #define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
6462 #define ETH_MACPCSR_RWKPTR_Pos                        (24U)
6463 #define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
6464 #define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
6465 #define ETH_MACPCSR_RWKPFE_Pos                        (10U)
6466 #define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
6467 #define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
6468 #define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
6469 #define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
6470 #define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
6471 #define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
6472 #define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
6473 #define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
6474 #define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
6475 #define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
6476 #define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
6477 #define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
6478 #define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
6479 #define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
6480 #define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
6481 #define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
6482 #define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
6483 #define ETH_MACPCSR_PWRDWN_Pos                        (0U)
6484 #define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
6485 #define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
6486 
6487 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
6488 #define ETH_MACRWUPFR_D_Pos                           (0U)
6489 #define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
6490 #define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
6491 
6492 /* Bit definition for Ethernet MAC LPI Control Status Register */
6493 #define ETH_MACLCSR_LPITCSE_Pos                       (21U)
6494 #define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
6495 #define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
6496 #define ETH_MACLCSR_LPITE_Pos                         (20U)
6497 #define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
6498 #define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
6499 #define ETH_MACLCSR_LPITXA_Pos                        (19U)
6500 #define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
6501 #define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
6502 #define ETH_MACLCSR_PLS_Pos                           (17U)
6503 #define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
6504 #define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
6505 #define ETH_MACLCSR_LPIEN_Pos                         (16U)
6506 #define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
6507 #define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
6508 #define ETH_MACLCSR_RLPIST_Pos                        (9U)
6509 #define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
6510 #define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
6511 #define ETH_MACLCSR_TLPIST_Pos                        (8U)
6512 #define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
6513 #define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
6514 #define ETH_MACLCSR_RLPIEX_Pos                        (3U)
6515 #define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
6516 #define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
6517 #define ETH_MACLCSR_RLPIEN_Pos                        (2U)
6518 #define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
6519 #define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
6520 #define ETH_MACLCSR_TLPIEX_Pos                        (1U)
6521 #define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
6522 #define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
6523 #define ETH_MACLCSR_TLPIEN_Pos                        (0U)
6524 #define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
6525 #define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
6526 
6527 /* Bit definition for Ethernet MAC LPI Timers Control Register */
6528 #define ETH_MACLTCR_LST_Pos                           (16U)
6529 #define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
6530 #define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
6531 #define ETH_MACLTCR_TWT_Pos                           (0U)
6532 #define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
6533 #define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
6534 
6535 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
6536 #define ETH_MACLETR_LPIET_Pos                         (0U)
6537 #define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
6538 #define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
6539 
6540 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
6541 #define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
6542 #define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
6543 #define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
6544 
6545 /* Bit definition for Ethernet MAC Version Register */
6546 #define ETH_MACVR_USERVER_Pos                         (8U)
6547 #define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
6548 #define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
6549 #define ETH_MACVR_SNPSVER_Pos                         (0U)
6550 #define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
6551 #define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
6552 
6553 /* Bit definition for Ethernet MAC Debug Register */
6554 #define ETH_MACDR_TFCSTS_Pos                          (17U)
6555 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
6556 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
6557 #define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
6558 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
6559 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
6560 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
6561 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
6562 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
6563 #define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
6564 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
6565 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
6566 #define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
6567 #define ETH_MACDR_TPESTS_Pos                          (16U)
6568 #define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
6569 #define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
6570 #define ETH_MACDR_RFCFCSTS_Pos                        (1U)
6571 #define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
6572 #define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
6573 #define ETH_MACDR_RPESTS_Pos                          (0U)
6574 #define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
6575 #define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
6576 
6577 /* Bit definition for Ethernet MAC HW Feature0 Register */
6578 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
6579 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
6580 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
6581 #define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
6582 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
6583 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
6584 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
6585 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
6586 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
6587 #define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
6588 #define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
6589 #define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
6590 #define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
6591 #define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
6592 #define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
6593 #define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
6594 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
6595 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
6596 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
6597 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
6598 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
6599 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
6600 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
6601 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
6602 #define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
6603 #define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
6604 #define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
6605 #define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
6606 #define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
6607 #define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
6608 #define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
6609 #define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
6610 #define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
6611 #define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
6612 #define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
6613 #define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
6614 #define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
6615 #define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
6616 #define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
6617 #define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
6618 #define ETH_MACHWF0R_EEESEL_Pos                       (13U)
6619 #define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
6620 #define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
6621 #define ETH_MACHWF0R_TSSEL_Pos                        (12U)
6622 #define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
6623 #define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
6624 #define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
6625 #define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
6626 #define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
6627 #define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
6628 #define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
6629 #define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
6630 #define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
6631 #define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
6632 #define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
6633 #define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
6634 #define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
6635 #define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
6636 #define ETH_MACHWF0R_SMASEL_Pos                       (5U)
6637 #define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
6638 #define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
6639 #define ETH_MACHWF0R_VLHASH_Pos                       (4U)
6640 #define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
6641 #define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
6642 #define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
6643 #define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
6644 #define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
6645 #define ETH_MACHWF0R_HDSEL_Pos                        (2U)
6646 #define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
6647 #define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
6648 #define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
6649 #define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
6650 #define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
6651 #define ETH_MACHWF0R_MIISEL_Pos                       (0U)
6652 #define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
6653 #define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
6654 
6655 /* Bit definition for Ethernet MAC HW Feature1 Register */
6656 #define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
6657 #define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
6658 #define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
6659 #define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
6660 #define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
6661 #define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
6662 #define ETH_MACHWF1R_AVSEL_Pos                        (20U)
6663 #define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
6664 #define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
6665 #define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
6666 #define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
6667 #define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
6668 #define ETH_MACHWF1R_TSOEN_Pos                        (18U)
6669 #define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
6670 #define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
6671 #define ETH_MACHWF1R_SPHEN_Pos                        (17U)
6672 #define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
6673 #define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
6674 #define ETH_MACHWF1R_DCBEN_Pos                        (16U)
6675 #define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
6676 #define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
6677 #define ETH_MACHWF1R_ADDR64_Pos                       (14U)
6678 #define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
6679 #define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
6680 #define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
6681 #define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
6682 #define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
6683 #define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
6684 #define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
6685 #define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
6686 #define ETH_MACHWF1R_PTOEN_Pos                        (12U)
6687 #define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
6688 #define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
6689 #define ETH_MACHWF1R_OSTEN_Pos                        (11U)
6690 #define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
6691 #define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
6692 #define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
6693 #define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
6694 #define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
6695 #define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
6696 #define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
6697 #define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
6698 
6699 /* Bit definition for Ethernet MAC HW Feature2 Register */
6700 #define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
6701 #define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
6702 #define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
6703 #define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
6704 #define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
6705 #define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
6706 #define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
6707 #define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
6708 #define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
6709 #define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
6710 #define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
6711 #define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
6712 #define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
6713 #define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
6714 #define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
6715 #define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
6716 #define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
6717 #define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
6718 
6719 /* Bit definition for Ethernet MAC MDIO Address Register */
6720 #define ETH_MACMDIOAR_PSE_Pos                         (27U)
6721 #define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
6722 #define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
6723 #define ETH_MACMDIOAR_BTB_Pos                         (26U)
6724 #define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
6725 #define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
6726 #define ETH_MACMDIOAR_PA_Pos                          (21U)
6727 #define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
6728 #define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
6729 #define ETH_MACMDIOAR_RDA_Pos                         (16U)
6730 #define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
6731 #define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
6732 #define ETH_MACMDIOAR_NTC_Pos                         (12U)
6733 #define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
6734 #define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
6735 #define ETH_MACMDIOAR_CR_Pos                          (8U)
6736 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
6737 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
6738 #define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
6739 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
6740 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
6741 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
6742 #define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
6743 #define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
6744 #define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
6745 #define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
6746 #define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
6747 #define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
6748 #define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
6749 #define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
6750 #define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
6751 #define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
6752 #define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
6753 #define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
6754 #define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
6755 #define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
6756 #define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
6757 #define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
6758 #define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
6759 #define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
6760 #define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
6761 #define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
6762 #define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
6763 #define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
6764 #define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
6765 #define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
6766 #define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
6767 #define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
6768 #define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
6769 #define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
6770 #define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
6771 #define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
6772 #define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
6773 #define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
6774 #define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
6775 #define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
6776 #define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
6777 #define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
6778 #define ETH_MACMDIOAR_SKAP_Pos                        (4U)
6779 #define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
6780 #define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
6781 #define ETH_MACMDIOAR_MOC_Pos                         (2U)
6782 #define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
6783 #define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
6784 #define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
6785 #define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
6786 #define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
6787 #define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
6788 #define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
6789 #define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
6790 #define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
6791 #define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
6792 #define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
6793 #define ETH_MACMDIOAR_C45E_Pos                        (1U)
6794 #define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
6795 #define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
6796 #define ETH_MACMDIOAR_MB_Pos                          (0U)
6797 #define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
6798 #define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
6799 
6800 /* Bit definition for Ethernet MAC MDIO Data Register */
6801 #define ETH_MACMDIODR_RA_Pos                          (16U)
6802 #define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
6803 #define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
6804 #define ETH_MACMDIODR_MD_Pos                          (0U)
6805 #define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
6806 #define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
6807 
6808 /* Bit definition for Ethernet ARP Address Register */
6809 #define ETH_MACARPAR_ARPPA_Pos                         (0U)
6810 #define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
6811 #define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
6812 
6813 /* Bit definition for Ethernet MAC Address 0 High Register */
6814 #define ETH_MACA0HR_AE_Pos                            (31U)
6815 #define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
6816 #define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
6817 #define ETH_MACA0HR_ADDRHI_Pos                        (0U)
6818 #define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
6819 #define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
6820 
6821 /* Bit definition for Ethernet MAC Address 0 Low Register */
6822 #define ETH_MACA0LR_ADDRLO_Pos                        (0U)
6823 #define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
6824 #define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
6825 
6826 /* Bit definition for Ethernet MAC Address 1 High Register */
6827 #define ETH_MACA1HR_AE_Pos                            (31U)
6828 #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
6829 #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
6830 #define ETH_MACA1HR_SA_Pos                            (30U)
6831 #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
6832 #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
6833 #define ETH_MACA1HR_MBC_Pos                           (24U)
6834 #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
6835 #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
6836 #define ETH_MACA1HR_ADDRHI_Pos                        (0U)
6837 #define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
6838 #define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
6839 
6840 /* Bit definition for Ethernet MAC Address 1 Low Register */
6841 #define ETH_MACA1LR_ADDRLO_Pos                        (0U)
6842 #define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
6843 #define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
6844 
6845 /* Bit definition for Ethernet MAC Address 2 High Register */
6846 #define ETH_MACA2HR_AE_Pos                            (31U)
6847 #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
6848 #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
6849 #define ETH_MACA2HR_SA_Pos                            (30U)
6850 #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
6851 #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
6852 #define ETH_MACA2HR_MBC_Pos                           (24U)
6853 #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
6854 #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
6855 #define ETH_MACA2HR_ADDRHI_Pos                        (0U)
6856 #define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
6857 #define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
6858 
6859 /* Bit definition for Ethernet MAC Address 2 Low Register */
6860 #define ETH_MACA2LR_ADDRLO_Pos                        (0U)
6861 #define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
6862 #define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
6863 
6864 /* Bit definition for Ethernet MAC Address 3 High Register */
6865 #define ETH_MACA3HR_AE_Pos                            (31U)
6866 #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
6867 #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
6868 #define ETH_MACA3HR_SA_Pos                            (30U)
6869 #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
6870 #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
6871 #define ETH_MACA3HR_MBC_Pos                           (24U)
6872 #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
6873 #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
6874 #define ETH_MACA3HR_ADDRHI_Pos                        (0U)
6875 #define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
6876 #define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
6877 
6878 /* Bit definition for Ethernet MAC Address 3 Low Register */
6879 #define ETH_MACA3LR_ADDRLO_Pos                        (0U)
6880 #define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
6881 #define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
6882 
6883 /* Bit definition for Ethernet MAC Address High Register */
6884 #define ETH_MACAHR_AE_Pos                             (31U)
6885 #define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
6886 #define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
6887 #define ETH_MACAHR_SA_Pos                             (30U)
6888 #define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
6889 #define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
6890 #define ETH_MACAHR_MBC_Pos                            (24U)
6891 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
6892 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6893 #define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
6894 #define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
6895 #define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
6896 #define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
6897 #define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
6898 #define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
6899 #define ETH_MACAHR_MACAH_Pos                          (0U)
6900 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
6901 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
6902 
6903 /* Bit definition for Ethernet MAC Address Low Register */
6904 #define ETH_MACALR_MACAL_Pos                          (0U)
6905 #define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
6906 #define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
6907 
6908 /* Bit definition for Ethernet MMC Control Register */
6909 #define ETH_MMCCR_UCDBC_Pos                           (8U)
6910 #define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
6911 #define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
6912 #define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
6913 #define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
6914 #define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
6915 #define ETH_MMCCR_CNTPRST_Pos                         (4U)
6916 #define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
6917 #define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
6918 #define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
6919 #define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
6920 #define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
6921 #define ETH_MMCCR_RSTONRD_Pos                         (2U)
6922 #define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
6923 #define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
6924 #define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
6925 #define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
6926 #define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
6927 #define ETH_MMCCR_CNTRST_Pos                          (0U)
6928 #define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
6929 #define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
6930 
6931 /* Bit definition for Ethernet MMC Rx Interrupt Register */
6932 #define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
6933 #define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
6934 #define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
6935 #define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
6936 #define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
6937 #define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
6938 #define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
6939 #define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
6940 #define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
6941 #define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
6942 #define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
6943 #define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
6944 #define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
6945 #define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
6946 #define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
6947 
6948 /* Bit definition for Ethernet MMC Tx Interrupt Register */
6949 #define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
6950 #define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
6951 #define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
6952 #define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
6953 #define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
6954 #define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
6955 #define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
6956 #define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
6957 #define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
6958 #define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
6959 #define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
6960 #define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
6961 #define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
6962 #define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
6963 #define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
6964 
6965 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
6966 #define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
6967 #define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
6968 #define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
6969 #define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
6970 #define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
6971 #define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
6972 #define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
6973 #define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
6974 #define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
6975 #define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
6976 #define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
6977 #define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
6978 #define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
6979 #define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
6980 #define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
6981 
6982 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
6983 #define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
6984 #define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
6985 #define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
6986 #define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
6987 #define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
6988 #define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
6989 #define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
6990 #define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
6991 #define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
6992 #define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
6993 #define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
6994 #define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
6995 #define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
6996 #define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
6997 #define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
6998 
6999 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7000 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
7001 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
7002 #define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7003 
7004 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7005 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
7006 #define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
7007 #define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7008 
7009 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7010 #define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
7011 #define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
7012 #define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7013 
7014 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7015 #define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
7016 #define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
7017 #define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7018 
7019 /* Bit definition for Ethernet MMC Rx alignment error packets register */
7020 #define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
7021 #define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
7022 #define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7023 
7024 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7025 #define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
7026 #define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
7027 #define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7028 
7029 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7030 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
7031 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7032 #define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7033 
7034 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7035 #define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
7036 #define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
7037 #define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7038 
7039 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7040 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
7041 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7042 #define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7043 
7044 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7045 #define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
7046 #define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
7047 #define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7048 
7049 /* Bit definition for Ethernet MAC L3 L4 Control Register */
7050 #define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
7051 #define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
7052 #define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7053 #define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
7054 #define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
7055 #define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
7056 #define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
7057 #define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
7058 #define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7059 #define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
7060 #define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
7061 #define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
7062 #define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
7063 #define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
7064 #define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
7065 #define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
7066 #define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
7067 #define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7068 #define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
7069 #define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
7070 #define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7071 #define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
7072 #define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
7073 #define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7074 #define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
7075 #define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
7076 #define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
7077 #define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
7078 #define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
7079 #define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7080 #define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
7081 #define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
7082 #define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
7083 #define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
7084 #define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
7085 #define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
7086 
7087 /* Bit definition for Ethernet MAC L4 Address Register */
7088 #define ETH_MACL4AR_L4DP_Pos                          (16U)
7089 #define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
7090 #define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
7091 #define ETH_MACL4AR_L4SP_Pos                          (0U)
7092 #define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
7093 #define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
7094 
7095 /* Bit definition for Ethernet MAC L3 Address0 Register */
7096 #define ETH_MACL3A0R_L3A0_Pos                         (0U)
7097 #define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
7098 #define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
7099 
7100 /* Bit definition for Ethernet MAC L4 Address1 Register */
7101 #define ETH_MACL3A1R_L3A1_Pos                         (0U)
7102 #define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
7103 #define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
7104 
7105 /* Bit definition for Ethernet MAC L4 Address2 Register */
7106 #define ETH_MACL3A2R_L3A2_Pos                         (0U)
7107 #define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
7108 #define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
7109 
7110 /* Bit definition for Ethernet MAC L4 Address3 Register */
7111 #define ETH_MACL3A3R_L3A3_Pos                         (0U)
7112 #define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
7113 #define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
7114 
7115 /* Bit definition for Ethernet MAC Timestamp Control Register */
7116 #define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
7117 #define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
7118 #define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
7119 #define ETH_MACTSCR_CSC_Pos                           (19U)
7120 #define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
7121 #define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7122 #define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
7123 #define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
7124 #define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
7125 #define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
7126 #define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
7127 #define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
7128 #define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
7129 #define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
7130 #define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
7131 #define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
7132 #define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
7133 #define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
7134 #define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
7135 #define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
7136 #define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7137 #define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
7138 #define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
7139 #define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7140 #define ETH_MACTSCR_TSIPENA_Pos                       (11U)
7141 #define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
7142 #define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
7143 #define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
7144 #define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
7145 #define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
7146 #define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
7147 #define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
7148 #define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
7149 #define ETH_MACTSCR_TSENALL_Pos                       (8U)
7150 #define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
7151 #define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
7152 #define ETH_MACTSCR_TSADDREG_Pos                      (5U)
7153 #define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
7154 #define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
7155 #define ETH_MACTSCR_TSUPDT_Pos                        (3U)
7156 #define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
7157 #define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
7158 #define ETH_MACTSCR_TSINIT_Pos                        (2U)
7159 #define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
7160 #define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
7161 #define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
7162 #define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
7163 #define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
7164 #define ETH_MACTSCR_TSENA_Pos                         (0U)
7165 #define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
7166 #define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
7167 
7168 /* Bit definition for Ethernet MAC Sub-second Increment Register */
7169 #define ETH_MACMACSSIR_SSINC_Pos                      (16U)
7170 #define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
7171 #define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
7172 #define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
7173 #define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
7174 #define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
7175 
7176 /* Bit definition for Ethernet MAC System Time Seconds Register */
7177 #define ETH_MACSTSR_TSS_Pos                           (0U)
7178 #define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
7179 #define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
7180 
7181 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
7182 #define ETH_MACSTNR_TSSS_Pos                          (0U)
7183 #define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
7184 #define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
7185 
7186 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
7187 #define ETH_MACSTSUR_TSS_Pos                          (0U)
7188 #define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
7189 #define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
7190 
7191 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
7192 #define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
7193 #define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
7194 #define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
7195 #define ETH_MACSTNUR_TSSS_Pos                         (0U)
7196 #define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
7197 #define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
7198 
7199 /* Bit definition for Ethernet MAC Timestamp Addend Register */
7200 #define ETH_MACTSAR_TSAR_Pos                          (0U)
7201 #define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
7202 #define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
7203 
7204 /* Bit definition for Ethernet MAC Timestamp Status Register */
7205 #define ETH_MACTSSR_ATSNS_Pos                         (25U)
7206 #define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
7207 #define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
7208 #define ETH_MACTSSR_ATSSTM_Pos                        (24U)
7209 #define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
7210 #define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
7211 #define ETH_MACTSSR_ATSSTN_Pos                        (16U)
7212 #define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
7213 #define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
7214 #define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
7215 #define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
7216 #define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
7217 #define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
7218 #define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
7219 #define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
7220 #define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
7221 #define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
7222 #define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
7223 #define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
7224 #define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
7225 #define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
7226 #define ETH_MACTSSR_TSSOVF_Pos                        (0U)
7227 #define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
7228 #define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
7229 
7230 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
7231 #define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
7232 #define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
7233 #define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
7234 #define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
7235 #define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
7236 #define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
7237 
7238 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
7239 #define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
7240 #define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
7241 #define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
7242 
7243 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
7244 #define ETH_MACACR_ATSEN3_Pos                         (7U)
7245 #define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
7246 #define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
7247 #define ETH_MACACR_ATSEN2_Pos                         (6U)
7248 #define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
7249 #define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
7250 #define ETH_MACACR_ATSEN1_Pos                         (5U)
7251 #define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
7252 #define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
7253 #define ETH_MACACR_ATSEN0_Pos                         (4U)
7254 #define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
7255 #define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
7256 #define ETH_MACACR_ATSFC_Pos                          (0U)
7257 #define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
7258 #define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
7259 
7260 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
7261 #define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
7262 #define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
7263 #define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
7264 
7265 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
7266 #define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
7267 #define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
7268 #define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
7269 
7270 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
7271 #define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
7272 #define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
7273 #define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
7274 
7275 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
7276 #define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
7277 #define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
7278 #define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
7279 
7280 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
7281 #define ETH_MACTSICNR_TSIC_Pos                        (0U)
7282 #define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
7283 #define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
7284 
7285 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
7286 #define ETH_MACTSECNR_TSEC_Pos                        (0U)
7287 #define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
7288 #define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
7289 
7290 /* Bit definition for Ethernet MAC PPS Control Register */
7291 #define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
7292 #define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
7293 #define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
7294 #define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
7295 #define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
7296 #define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
7297 #define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
7298 #define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
7299 #define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
7300 
7301 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
7302 #define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
7303 #define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
7304 #define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
7305 
7306 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
7307 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
7308 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
7309 #define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
7310 #define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
7311 #define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
7312 #define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
7313 
7314 /* Bit definition for Ethernet MAC PPS Interval Register */
7315 #define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
7316 #define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
7317 #define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
7318 
7319 /* Bit definition for Ethernet MAC PPS Width Register */
7320 #define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
7321 #define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
7322 #define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
7323 
7324 /* Bit definition for Ethernet MAC PTP Offload Control Register */
7325 #define ETH_MACPOCR_DN_Pos                            (8U)
7326 #define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
7327 #define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
7328 #define ETH_MACPOCR_DRRDIS_Pos                        (6U)
7329 #define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
7330 #define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
7331 #define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
7332 #define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
7333 #define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
7334 #define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
7335 #define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
7336 #define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
7337 #define ETH_MACPOCR_APDREQEN_Pos                      (2U)
7338 #define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
7339 #define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
7340 #define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
7341 #define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
7342 #define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
7343 #define ETH_MACPOCR_PTOEN_Pos                         (0U)
7344 #define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
7345 #define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
7346 
7347 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
7348 #define ETH_MACSPI0R_SPI0_Pos                         (0U)
7349 #define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
7350 #define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
7351 
7352 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
7353 #define ETH_MACSPI1R_SPI1_Pos                         (0U)
7354 #define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
7355 #define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
7356 
7357 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
7358 #define ETH_MACSPI2R_SPI2_Pos                         (0U)
7359 #define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
7360 #define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
7361 
7362 /* Bit definition for Ethernet MAC Log Message Interval Register */
7363 #define ETH_MACLMIR_LMPDRI_Pos                        (24U)
7364 #define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
7365 #define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
7366 #define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
7367 #define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
7368 #define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
7369 #define ETH_MACLMIR_LSI_Pos                           (0U)
7370 #define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
7371 #define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
7372 
7373 /* Bit definition for Ethernet MTL Operation Mode Register */
7374 #define ETH_MTLOMR_CNTCLR_Pos                         (9U)
7375 #define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
7376 #define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
7377 #define ETH_MTLOMR_CNTPRST_Pos                        (8U)
7378 #define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
7379 #define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
7380 #define ETH_MTLOMR_DTXSTS_Pos                         (1U)
7381 #define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
7382 #define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
7383 
7384 /* Bit definition for Ethernet MTL Interrupt Status Register */
7385 #define ETH_MTLISR_MACIS_Pos                          (16U)
7386 #define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
7387 #define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
7388 #define ETH_MTLISR_QIS_Pos                            (0U)
7389 #define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
7390 #define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
7391 
7392 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
7393 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
7394 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
7395 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
7396 #define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
7397 #define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
7398 #define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
7399 #define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
7400 #define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
7401 #define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
7402 #define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
7403 #define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
7404 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
7405 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
7406 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
7407 #define ETH_MTLTQOMR_FTQ_Pos                          (0U)
7408 #define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
7409 #define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
7410 
7411 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
7412 #define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
7413 #define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
7414 #define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
7415 #define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
7416 #define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
7417 #define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
7418 
7419 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
7420 #define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
7421 #define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
7422 #define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
7423 #define ETH_MTLTQDR_PTXQ_Pos                          (16U)
7424 #define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
7425 #define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
7426 #define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
7427 #define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
7428 #define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
7429 #define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
7430 #define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
7431 #define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
7432 #define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
7433 #define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
7434 #define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
7435 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
7436 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
7437 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
7438 #define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
7439 #define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
7440 #define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
7441 #define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
7442 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
7443 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
7444 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
7445 
7446 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
7447 #define ETH_MTLQICSR_RXOIE_Pos                        (24U)
7448 #define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
7449 #define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
7450 #define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
7451 #define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
7452 #define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
7453 #define ETH_MTLQICSR_TXUIE_Pos                        (8U)
7454 #define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
7455 #define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
7456 #define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
7457 #define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
7458 #define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
7459 
7460 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
7461 #define ETH_MTLRQOMR_RQS_Pos                          (20U)
7462 #define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
7463 #define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
7464 #define ETH_MTLRQOMR_RFD_Pos                          (14U)
7465 #define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
7466 #define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
7467 #define ETH_MTLRQOMR_RFA_Pos                          (8U)
7468 #define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
7469 #define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
7470 #define ETH_MTLRQOMR_EHFC_Pos                         (7U)
7471 #define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
7472 #define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
7473 #define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
7474 #define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
7475 #define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
7476 #define ETH_MTLRQOMR_RSF_Pos                          (5U)
7477 #define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
7478 #define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
7479 #define ETH_MTLRQOMR_FEP_Pos                          (4U)
7480 #define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
7481 #define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
7482 #define ETH_MTLRQOMR_FUP_Pos                          (3U)
7483 #define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
7484 #define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
7485 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
7486 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
7487 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
7488 #define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
7489 #define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
7490 #define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
7491 #define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
7492 
7493 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
7494 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
7495 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
7496 #define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
7497 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
7498 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
7499 #define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
7500 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
7501 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
7502 #define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
7503 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
7504 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
7505 #define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
7506 
7507 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
7508 #define ETH_MTLRQDR_PRXQ_Pos                          (16U)
7509 #define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
7510 #define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
7511 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
7512 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
7513 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
7514 #define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
7515 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
7516 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
7517 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
7518 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
7519 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
7520 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
7521 #define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
7522 #define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
7523 #define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
7524 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
7525 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
7526 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
7527 #define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
7528 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
7529 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
7530 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
7531 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
7532 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
7533 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
7534 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
7535 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
7536 #define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
7537 #define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
7538 #define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
7539 #define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
7540 
7541 /* Bit definition for Ethernet MTL Rx Queue Control Register */
7542 #define ETH_MTLRQCR_RQPA_Pos                          (3U)
7543 #define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
7544 #define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
7545 #define ETH_MTLRQCR_RQW_Pos                           (0U)
7546 #define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
7547 #define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
7548 
7549 /* Bit definition for Ethernet DMA Mode Register */
7550 #define ETH_DMAMR_INTM_Pos                            (16U)
7551 #define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
7552 #define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
7553 #define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
7554 #define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
7555 #define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
7556 #define ETH_DMAMR_PR_Pos                              (12U)
7557 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
7558 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
7559 #define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
7560 #define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
7561 #define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
7562 #define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
7563 #define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
7564 #define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
7565 #define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
7566 #define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
7567 #define ETH_DMAMR_TXPR_Pos                            (11U)
7568 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
7569 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
7570 #define ETH_DMAMR_DA_Pos                              (1U)
7571 #define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
7572 #define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
7573 #define ETH_DMAMR_SWR_Pos                             (0U)
7574 #define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
7575 #define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
7576 
7577 /* Bit definition for Ethernet DMA SysBus Mode Register */
7578 #define ETH_DMASBMR_RB_Pos                            (15U)
7579 #define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
7580 #define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
7581 #define ETH_DMASBMR_MB_Pos                            (14U)
7582 #define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
7583 #define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
7584 #define ETH_DMASBMR_AAL_Pos                           (12U)
7585 #define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
7586 #define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
7587 #define ETH_DMASBMR_FB_Pos                            (0U)
7588 #define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
7589 #define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
7590 
7591 /* Bit definition for Ethernet DMA Interrupt Status Register */
7592 #define ETH_DMAISR_MACIS_Pos                          (17U)
7593 #define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
7594 #define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
7595 #define ETH_DMAISR_MTLIS_Pos                          (16U)
7596 #define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
7597 #define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
7598 #define ETH_DMAISR_DMACIS_Pos                         (0U)
7599 #define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
7600 #define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
7601 
7602 /* Bit definition for Ethernet DMA Debug Status Register */
7603 #define ETH_DMADSR_TPS_Pos                            (12U)
7604 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
7605 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
7606 #define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
7607 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
7608 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
7609 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
7610 #define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
7611 #define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
7612 #define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
7613 #define ETH_DMADSR_TPS_READING_Pos                    (12U)
7614 #define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
7615 #define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
7616 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
7617 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
7618 #define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
7619 #define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
7620 #define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
7621 #define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
7622 #define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
7623 #define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
7624 #define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
7625 #define ETH_DMADSR_RPS_Pos                            (8U)
7626 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
7627 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
7628 #define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
7629 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
7630 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
7631 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
7632 #define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
7633 #define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
7634 #define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
7635 #define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
7636 #define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
7637 #define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
7638 #define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
7639 #define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
7640 #define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
7641 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
7642 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
7643 #define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
7644 #define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
7645 #define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
7646 #define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
7647 
7648 /* Bit definition for Ethernet DMA Channel Control Register */
7649 #define ETH_DMACCR_DSL_Pos                            (18U)
7650 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
7651 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
7652 #define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
7653 #define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
7654 #define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
7655 #define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
7656 #define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
7657 #define ETH_DMACCR_MSS_Pos                            (0U)
7658 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
7659 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
7660 
7661 /* Bit definition for Ethernet DMA Channel Tx Control Register */
7662 #define ETH_DMACTCR_TPBL_Pos                          (16U)
7663 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
7664 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
7665 #define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
7666 #define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
7667 #define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
7668 #define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
7669 #define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
7670 #define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
7671 #define ETH_DMACTCR_TSE_Pos                           (12U)
7672 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
7673 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
7674 #define ETH_DMACTCR_OSP_Pos                           (4U)
7675 #define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
7676 #define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
7677 #define ETH_DMACTCR_ST_Pos                            (0U)
7678 #define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
7679 #define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
7680 
7681 /* Bit definition for Ethernet DMA Channel Rx Control Register */
7682 #define ETH_DMACRCR_RPF_Pos                           (31U)
7683 #define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
7684 #define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
7685 #define ETH_DMACRCR_RPBL_Pos                          (16U)
7686 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
7687 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
7688 #define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
7689 #define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
7690 #define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
7691 #define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
7692 #define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
7693 #define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
7694 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
7695 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
7696 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
7697 #define ETH_DMACRCR_SR_Pos                            (0U)
7698 #define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
7699 #define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
7700 
7701 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
7702 #define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
7703 #define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
7704 #define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
7705 
7706 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
7707 #define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
7708 #define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
7709 #define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
7710 
7711 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
7712 #define ETH_DMACTDTPR_TDT_Pos                         (2U)
7713 #define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
7714 #define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
7715 
7716 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
7717 #define ETH_DMACRDTPR_RDT_Pos                         (2U)
7718 #define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
7719 #define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
7720 
7721 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
7722 #define ETH_DMACTDRLR_TDRL_Pos                        (0U)
7723 #define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
7724 #define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
7725 
7726 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
7727 #define ETH_DMACRDRLR_RDRL_Pos                        (0U)
7728 #define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
7729 #define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
7730 
7731 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
7732 #define ETH_DMACIER_NIE_Pos                           (15U)
7733 #define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
7734 #define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
7735 #define ETH_DMACIER_AIE_Pos                           (14U)
7736 #define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
7737 #define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
7738 #define ETH_DMACIER_CDEE_Pos                          (13U)
7739 #define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
7740 #define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
7741 #define ETH_DMACIER_FBEE_Pos                          (12U)
7742 #define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
7743 #define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
7744 #define ETH_DMACIER_ERIE_Pos                          (11U)
7745 #define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
7746 #define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
7747 #define ETH_DMACIER_ETIE_Pos                          (10U)
7748 #define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
7749 #define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
7750 #define ETH_DMACIER_RWTE_Pos                          (9U)
7751 #define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
7752 #define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
7753 #define ETH_DMACIER_RSE_Pos                           (8U)
7754 #define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
7755 #define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
7756 #define ETH_DMACIER_RBUE_Pos                          (7U)
7757 #define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
7758 #define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
7759 #define ETH_DMACIER_RIE_Pos                           (6U)
7760 #define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
7761 #define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
7762 #define ETH_DMACIER_TBUE_Pos                          (2U)
7763 #define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
7764 #define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
7765 #define ETH_DMACIER_TXSE_Pos                          (1U)
7766 #define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
7767 #define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
7768 #define ETH_DMACIER_TIE_Pos                           (0U)
7769 #define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
7770 #define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
7771 
7772 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
7773 #define ETH_DMACRIWTR_RWT_Pos                         (0U)
7774 #define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
7775 #define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
7776 
7777 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
7778 #define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
7779 #define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
7780 #define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
7781 
7782 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
7783 #define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
7784 #define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
7785 #define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
7786 
7787 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
7788 #define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
7789 #define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
7790 #define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
7791 
7792 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
7793 #define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
7794 #define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
7795 #define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
7796 
7797 /* Bit definition for Ethernet DMA Channel Status Register */
7798 #define ETH_DMACSR_REB_Pos                            (19U)
7799 #define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
7800 #define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
7801 #define ETH_DMACSR_TEB_Pos                            (16U)
7802 #define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
7803 #define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
7804 #define ETH_DMACSR_NIS_Pos                            (15U)
7805 #define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
7806 #define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
7807 #define ETH_DMACSR_AIS_Pos                            (14U)
7808 #define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
7809 #define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
7810 #define ETH_DMACSR_CDE_Pos                            (13U)
7811 #define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
7812 #define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
7813 #define ETH_DMACSR_FBE_Pos                            (12U)
7814 #define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
7815 #define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
7816 #define ETH_DMACSR_ERI_Pos                            (11U)
7817 #define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
7818 #define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
7819 #define ETH_DMACSR_ETI_Pos                            (10U)
7820 #define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
7821 #define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
7822 #define ETH_DMACSR_RWT_Pos                            (9U)
7823 #define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
7824 #define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
7825 #define ETH_DMACSR_RPS_Pos                            (8U)
7826 #define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
7827 #define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
7828 #define ETH_DMACSR_RBU_Pos                            (7U)
7829 #define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
7830 #define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
7831 #define ETH_DMACSR_RI_Pos                             (6U)
7832 #define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
7833 #define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
7834 #define ETH_DMACSR_TBU_Pos                            (2U)
7835 #define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
7836 #define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
7837 #define ETH_DMACSR_TPS_Pos                            (1U)
7838 #define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
7839 #define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
7840 #define ETH_DMACSR_TI_Pos                             (0U)
7841 #define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
7842 #define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
7843 
7844 /* Bit definition for Ethernet DMA Channel missed frame count register */
7845 #define ETH_DMACMFCR_MFCO_Pos                         (15U)
7846 #define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
7847 #define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
7848 #define ETH_DMACMFCR_MFC_Pos                          (0U)
7849 #define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
7850 #define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
7851 /******************************************************************************/
7852 /*                                                                            */
7853 /*                           DMA Controller (DMA)                             */
7854 /*                                                                            */
7855 /******************************************************************************/
7856 /*******************  Bit definition for DMA_SECCFGR register  ****************/
7857 #define DMA_SECCFGR_SEC0_Pos                (0U)
7858 #define DMA_SECCFGR_SEC0_Msk                (0x1UL << DMA_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
7859 #define DMA_SECCFGR_SEC0                    DMA_SECCFGR_SEC0_Msk                    /*!< Secure State of Channel 0  */
7860 #define DMA_SECCFGR_SEC1_Pos                (1U)
7861 #define DMA_SECCFGR_SEC1_Msk                (0x1UL << DMA_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
7862 #define DMA_SECCFGR_SEC1                    DMA_SECCFGR_SEC1_Msk                    /*!< Secure State of Channel 1  */
7863 #define DMA_SECCFGR_SEC2_Pos                (2U)
7864 #define DMA_SECCFGR_SEC2_Msk                (0x1UL << DMA_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
7865 #define DMA_SECCFGR_SEC2                    DMA_SECCFGR_SEC2_Msk                    /*!< Secure State of Channel 2  */
7866 #define DMA_SECCFGR_SEC3_Pos                (3U)
7867 #define DMA_SECCFGR_SEC3_Msk                (0x1UL << DMA_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
7868 #define DMA_SECCFGR_SEC3                    DMA_SECCFGR_SEC3_Msk                    /*!< Secure State of Channel 3  */
7869 #define DMA_SECCFGR_SEC4_Pos                (4U)
7870 #define DMA_SECCFGR_SEC4_Msk                (0x1UL << DMA_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
7871 #define DMA_SECCFGR_SEC4                    DMA_SECCFGR_SEC4_Msk                    /*!< Secure State of Channel 4  */
7872 #define DMA_SECCFGR_SEC5_Pos                (5U)
7873 #define DMA_SECCFGR_SEC5_Msk                (0x1UL << DMA_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
7874 #define DMA_SECCFGR_SEC5                    DMA_SECCFGR_SEC5_Msk                    /*!< Secure State of Channel 5  */
7875 #define DMA_SECCFGR_SEC6_Pos                (6U)
7876 #define DMA_SECCFGR_SEC6_Msk                (0x1UL << DMA_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
7877 #define DMA_SECCFGR_SEC6                    DMA_SECCFGR_SEC6_Msk                    /*!< Secure State of Channel 6  */
7878 #define DMA_SECCFGR_SEC7_Pos                (7U)
7879 #define DMA_SECCFGR_SEC7_Msk                (0x1UL << DMA_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
7880 #define DMA_SECCFGR_SEC7                    DMA_SECCFGR_SEC7_Msk                    /*!< Secure State of Channel 7  */
7881 
7882 /*******************  Bit definition for DMA_PRIVCFGR register  ****************/
7883 #define DMA_PRIVCFGR_PRIV0_Pos              (0U)
7884 #define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
7885 #define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0  */
7886 #define DMA_PRIVCFGR_PRIV1_Pos              (1U)
7887 #define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
7888 #define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1  */
7889 #define DMA_PRIVCFGR_PRIV2_Pos              (2U)
7890 #define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
7891 #define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2  */
7892 #define DMA_PRIVCFGR_PRIV3_Pos              (3U)
7893 #define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
7894 #define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3  */
7895 #define DMA_PRIVCFGR_PRIV4_Pos              (4U)
7896 #define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
7897 #define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4  */
7898 #define DMA_PRIVCFGR_PRIV5_Pos              (5U)
7899 #define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
7900 #define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5  */
7901 #define DMA_PRIVCFGR_PRIV6_Pos              (6U)
7902 #define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
7903 #define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6  */
7904 #define DMA_PRIVCFGR_PRIV7_Pos              (7U)
7905 #define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
7906 #define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7  */
7907 
7908 /*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
7909 #define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
7910 #define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
7911 #define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
7912 #define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
7913 #define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
7914 #define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
7915 #define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
7916 #define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
7917 #define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
7918 #define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
7919 #define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
7920 #define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
7921 #define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
7922 #define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
7923 #define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
7924 #define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
7925 #define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
7926 #define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
7927 #define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
7928 #define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
7929 #define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
7930 #define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
7931 #define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
7932 #define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
7933 
7934 /*******************  Bit definition for DMA_MISR register  ****************/
7935 #define DMA_MISR_MIS0_Pos                   (0U)
7936 #define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
7937 #define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0  */
7938 #define DMA_MISR_MIS1_Pos                   (1U)
7939 #define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
7940 #define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1  */
7941 #define DMA_MISR_MIS2_Pos                   (2U)
7942 #define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
7943 #define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2  */
7944 #define DMA_MISR_MIS3_Pos                   (3U)
7945 #define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
7946 #define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3  */
7947 #define DMA_MISR_MIS4_Pos                   (4U)
7948 #define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
7949 #define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4  */
7950 #define DMA_MISR_MIS5_Pos                   (5U)
7951 #define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
7952 #define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5  */
7953 #define DMA_MISR_MIS6_Pos                   (6U)
7954 #define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
7955 #define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6  */
7956 #define DMA_MISR_MIS7_Pos                   (7U)
7957 #define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
7958 #define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7  */
7959 
7960 /*******************  Bit definition for DMA_SMISR register  ****************/
7961 #define DMA_SMISR_MIS0_Pos                  (0U)
7962 #define DMA_SMISR_MIS0_Msk                  (0x1UL << DMA_SMISR_MIS0_Pos)           /*!< 0x00000001 */
7963 #define DMA_SMISR_MIS0                      DMA_SMISR_MIS0_Msk                      /*!< Masked Interrupt State of Secure Channel 0  */
7964 #define DMA_SMISR_MIS1_Pos                  (1U)
7965 #define DMA_SMISR_MIS1_Msk                  (0x1UL << DMA_SMISR_MIS1_Pos)           /*!< 0x00000002 */
7966 #define DMA_SMISR_MIS1                      DMA_SMISR_MIS1_Msk                      /*!< Masked Interrupt State of Secure Channel 1  */
7967 #define DMA_SMISR_MIS2_Pos                  (2U)
7968 #define DMA_SMISR_MIS2_Msk                  (0x1UL << DMA_SMISR_MIS2_Pos)           /*!< 0x00000004 */
7969 #define DMA_SMISR_MIS2                      DMA_SMISR_MIS2_Msk                      /*!< Masked Interrupt State of Secure Channel 2  */
7970 #define DMA_SMISR_MIS3_Pos                  (3U)
7971 #define DMA_SMISR_MIS3_Msk                  (0x1UL << DMA_SMISR_MIS3_Pos)           /*!< 0x00000008 */
7972 #define DMA_SMISR_MIS3                      DMA_SMISR_MIS3_Msk                      /*!< Masked Interrupt State of Secure Channel 3  */
7973 #define DMA_SMISR_MIS4_Pos                  (4U)
7974 #define DMA_SMISR_MIS4_Msk                  (0x1UL << DMA_SMISR_MIS4_Pos)           /*!< 0x00000010 */
7975 #define DMA_SMISR_MIS4                      DMA_SMISR_MIS4_Msk                      /*!< Masked Interrupt State of Secure Channel 4  */
7976 #define DMA_SMISR_MIS5_Pos                  (5U)
7977 #define DMA_SMISR_MIS5_Msk                  (0x1UL << DMA_SMISR_MIS5_Pos)           /*!< 0x00000020 */
7978 #define DMA_SMISR_MIS5                      DMA_SMISR_MIS5_Msk                      /*!< Masked Interrupt State of Secure Channel 5  */
7979 #define DMA_SMISR_MIS6_Pos                  (6U)
7980 #define DMA_SMISR_MIS6_Msk                  (0x1UL << DMA_SMISR_MIS6_Pos)           /*!< 0x00000040 */
7981 #define DMA_SMISR_MIS6                      DMA_SMISR_MIS6_Msk                      /*!< Masked Interrupt State of Secure Channel 6  */
7982 #define DMA_SMISR_MIS7_Pos                  (7U)
7983 #define DMA_SMISR_MIS7_Msk                  (0x1UL << DMA_SMISR_MIS7_Pos)           /*!< 0x00000080 */
7984 #define DMA_SMISR_MIS7                      DMA_SMISR_MIS7_Msk                      /*!< Masked Interrupt State of Secure Channel 7  */
7985 
7986 /*******************  Bit definition for DMA_CLBAR register  ****************/
7987 #define DMA_CLBAR_LBA_Pos                   (16U)
7988 #define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
7989 #define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
7990 
7991 /*******************  Bit definition for DMA_CFCR register  *******************/
7992 #define DMA_CFCR_TCF_Pos                    (8U)
7993 #define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
7994 #define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear             */
7995 #define DMA_CFCR_HTF_Pos                    (9U)
7996 #define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
7997 #define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear        */
7998 #define DMA_CFCR_DTEF_Pos                   (10U)
7999 #define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
8000 #define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear           */
8001 #define DMA_CFCR_ULEF_Pos                   (11U)
8002 #define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
8003 #define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
8004 #define DMA_CFCR_USEF_Pos                   (12U)
8005 #define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
8006 #define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear            */
8007 #define DMA_CFCR_SUSPF_Pos                  (13U)
8008 #define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
8009 #define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear          */
8010 #define DMA_CFCR_TOF_Pos                    (14U)
8011 #define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
8012 #define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun flag clear               */
8013 
8014 /*******************  Bit definition for DMA_CSR register  *******************/
8015 #define DMA_CSR_IDLEF_Pos                   (0U)
8016 #define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
8017 #define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag                          */
8018 #define DMA_CSR_TCF_Pos                     (8U)
8019 #define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
8020 #define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag             */
8021 #define DMA_CSR_HTF_Pos                     (9U)
8022 #define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
8023 #define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag        */
8024 #define DMA_CSR_DTEF_Pos                    (10U)
8025 #define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
8026 #define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag           */
8027 #define DMA_CSR_ULEF_Pos                    (11U)
8028 #define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
8029 #define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
8030 #define DMA_CSR_USEF_Pos                    (12U)
8031 #define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
8032 #define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag            */
8033 #define DMA_CSR_SUSPF_Pos                   (13U)
8034 #define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
8035 #define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag            */
8036 #define DMA_CSR_TOF_Pos                     (14U)
8037 #define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
8038 #define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag               */
8039 #define DMA_CSR_FIFOL_Pos                   (16U)
8040 #define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
8041 #define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes      */
8042 
8043 /*******************  Bit definition for DMA_CCR register  ********************/
8044 #define DMA_CCR_EN_Pos                      (0U)
8045 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
8046 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable                                 */
8047 #define DMA_CCR_RESET_Pos                   (1U)
8048 #define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
8049 #define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset                                  */
8050 #define DMA_CCR_SUSP_Pos                    (2U)
8051 #define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
8052 #define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend                                */
8053 #define DMA_CCR_TCIE_Pos                    (8U)
8054 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
8055 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable             */
8056 #define DMA_CCR_HTIE_Pos                    (9U)
8057 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
8058 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable        */
8059 #define DMA_CCR_DTEIE_Pos                   (10U)
8060 #define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
8061 #define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable           */
8062 #define DMA_CCR_ULEIE_Pos                   (11U)
8063 #define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
8064 #define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
8065 #define DMA_CCR_USEIE_Pos                   (12U)
8066 #define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
8067 #define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable            */
8068 #define DMA_CCR_SUSPIE_Pos                  (13U)
8069 #define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
8070 #define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable          */
8071 #define DMA_CCR_TOIE_Pos                    (14U)
8072 #define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
8073 #define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable               */
8074 #define DMA_CCR_LSM_Pos                     (16U)
8075 #define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
8076 #define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode                                 */
8077 #define DMA_CCR_LAP_Pos                     (17U)
8078 #define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
8079 #define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port                     */
8080 #define DMA_CCR_PRIO_Pos                    (22U)
8081 #define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
8082 #define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level                                 */
8083 #define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
8084 #define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
8085 
8086 /*******************  Bit definition for DMA_CTR1 register  *******************/
8087 #define DMA_CTR1_SDW_LOG2_Pos               (0U)
8088 #define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
8089 #define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst                    */
8090 #define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
8091 #define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
8092 #define DMA_CTR1_SINC_Pos                   (3U)
8093 #define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
8094 #define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst                                               */
8095 #define DMA_CTR1_SBL_1_Pos                  (4U)
8096 #define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
8097 #define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1                                             */
8098 #define DMA_CTR1_PAM_Pos                    (11U)
8099 #define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
8100 #define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode                                                */
8101 #define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
8102 #define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
8103 #define DMA_CTR1_SBX_Pos                    (13U)
8104 #define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
8105 #define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
8106 #define DMA_CTR1_SAP_Pos                    (14U)
8107 #define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
8108 #define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port                                                   */
8109 #define DMA_CTR1_SSEC_Pos                   (15U)
8110 #define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
8111 #define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source                  */
8112 #define DMA_CTR1_DDW_LOG2_Pos               (16U)
8113 #define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
8114 #define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst               */
8115 #define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
8116 #define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
8117 #define DMA_CTR1_DINC_Pos                   (19U)
8118 #define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
8119 #define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst                                          */
8120 #define DMA_CTR1_DBL_1_Pos                  (20U)
8121 #define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
8122 #define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1                                        */
8123 #define DMA_CTR1_DBX_Pos                    (26U)
8124 #define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
8125 #define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange                                               */
8126 #define DMA_CTR1_DHX_Pos                    (27U)
8127 #define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
8128 #define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange                                          */
8129 #define DMA_CTR1_DAP_Pos                    (30U)
8130 #define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
8131 #define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port                                              */
8132 #define DMA_CTR1_DSEC_Pos                   (31U)
8133 #define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
8134 #define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination             */
8135 
8136 /******************  Bit definition for DMA_CTR2 register  *******************/
8137 #define DMA_CTR2_REQSEL_Pos                 (0U)
8138 #define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
8139 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
8140 #define DMA_CTR2_SWREQ_Pos                  (9U)
8141 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
8142 #define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request               */
8143 #define DMA_CTR2_DREQ_Pos                   (10U)
8144 #define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
8145 #define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request   */
8146 #define DMA_CTR2_BREQ_Pos                   (11U)
8147 #define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
8148 #define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request         */
8149 #define DMA_CTR2_TRIGM_Pos                  (14U)
8150 #define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
8151 #define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode                   */
8152 #define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
8153 #define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
8154 #define DMA_CTR2_TRIGSEL_Pos                (16U)
8155 #define DMA_CTR2_TRIGSEL_Msk                (0x3FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x003F0000 */
8156 #define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection  */
8157 #define DMA_CTR2_TRIGPOL_Pos                (24U)
8158 #define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
8159 #define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity         */
8160 #define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
8161 #define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
8162 #define DMA_CTR2_TCEM_Pos                   (30U)
8163 #define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
8164 #define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode   */
8165 #define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
8166 #define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
8167 
8168 /******************  Bit definition for DMA_CBR1 register  *******************/
8169 #define DMA_CBR1_BNDT_Pos                   (0U)
8170 #define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
8171 #define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
8172 #define DMA_CBR1_BRC_Pos                    (16U)
8173 #define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
8174 #define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter                                   */
8175 #define DMA_CBR1_SDEC_Pos                   (28U)
8176 #define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
8177 #define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement                               */
8178 #define DMA_CBR1_DDEC_Pos                   (29U)
8179 #define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
8180 #define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement                          */
8181 #define DMA_CBR1_BRSDEC_Pos                 (30U)
8182 #define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
8183 #define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement                  */
8184 #define DMA_CBR1_BRDDEC_Pos                 (31U)
8185 #define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
8186 #define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement             */
8187 
8188 /******************  Bit definition for DMA_CSAR register  ********************/
8189 #define DMA_CSAR_SA_Pos                     (0U)
8190 #define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
8191 #define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
8192 
8193 /******************  Bit definition for DMA_CDAR register  *******************/
8194 #define DMA_CDAR_DA_Pos                     (0U)
8195 #define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
8196 #define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
8197 
8198 /******************  Bit definition for DMA_CTR3 register  *******************/
8199 #define DMA_CTR3_SAO_Pos                    (0U)
8200 #define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
8201 #define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment      */
8202 #define DMA_CTR3_DAO_Pos                    (16U)
8203 #define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
8204 #define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
8205 
8206 /******************  Bit definition for DMA_CBR2 register  *******************/
8207 #define DMA_CBR2_BRSAO_Pos                  (0U)
8208 #define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
8209 #define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset      */
8210 #define DMA_CBR2_BRDAO_Pos                  (16U)
8211 #define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
8212 #define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
8213 
8214 /******************  Bit definition for DMA_CLLR register  *******************/
8215 #define DMA_CLLR_LA_Pos                     (2U)
8216 #define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
8217 #define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
8218 #define DMA_CLLR_ULL_Pos                    (16U)
8219 #define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
8220 #define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory       */
8221 #define DMA_CLLR_UB2_Pos                    (25U)
8222 #define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
8223 #define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory            */
8224 #define DMA_CLLR_UT3_Pos                    (26U)
8225 #define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
8226 #define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM           */
8227 #define DMA_CLLR_UDA_Pos                    (27U)
8228 #define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
8229 #define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM  */
8230 #define DMA_CLLR_USA_Pos                    (28U)
8231 #define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
8232 #define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM       */
8233 #define DMA_CLLR_UB1_Pos                    (29U)
8234 #define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
8235 #define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM              */
8236 #define DMA_CLLR_UT2_Pos                    (30U)
8237 #define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
8238 #define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM           */
8239 #define DMA_CLLR_UT1_Pos                    (31U)
8240 #define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
8241 #define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM           */
8242 
8243 /******************************************************************************/
8244 /*                                                                            */
8245 /*                    External Interrupt/Event Controller                     */
8246 /*                                                                            */
8247 /******************************************************************************/
8248 /******************  Bit definition for EXTI_RTSR1 register  ******************/
8249 #define EXTI_RTSR1_RT0_Pos                  (0U)
8250 #define EXTI_RTSR1_RT0_Msk                  (0x1UL << EXTI_RTSR1_RT0_Pos)           /*!< 0x00000001 */
8251 #define EXTI_RTSR1_RT0                      EXTI_RTSR1_RT0_Msk                      /*!< Rising trigger configuration for input line 0 */
8252 #define EXTI_RTSR1_RT1_Pos                  (1U)
8253 #define EXTI_RTSR1_RT1_Msk                  (0x1UL << EXTI_RTSR1_RT1_Pos)           /*!< 0x00000002 */
8254 #define EXTI_RTSR1_RT1                      EXTI_RTSR1_RT1_Msk                      /*!< Rising trigger configuration for input line 1 */
8255 #define EXTI_RTSR1_RT2_Pos                  (2U)
8256 #define EXTI_RTSR1_RT2_Msk                  (0x1UL << EXTI_RTSR1_RT2_Pos)           /*!< 0x00000004 */
8257 #define EXTI_RTSR1_RT2                      EXTI_RTSR1_RT2_Msk                      /*!< Rising trigger configuration for input line 2 */
8258 #define EXTI_RTSR1_RT3_Pos                  (3U)
8259 #define EXTI_RTSR1_RT3_Msk                  (0x1UL << EXTI_RTSR1_RT3_Pos)           /*!< 0x00000008 */
8260 #define EXTI_RTSR1_RT3                      EXTI_RTSR1_RT3_Msk                      /*!< Rising trigger configuration for input line 3 */
8261 #define EXTI_RTSR1_RT4_Pos                  (4U)
8262 #define EXTI_RTSR1_RT4_Msk                  (0x1UL << EXTI_RTSR1_RT4_Pos)           /*!< 0x00000010 */
8263 #define EXTI_RTSR1_RT4                      EXTI_RTSR1_RT4_Msk                      /*!< Rising trigger configuration for input line 4 */
8264 #define EXTI_RTSR1_RT5_Pos                  (5U)
8265 #define EXTI_RTSR1_RT5_Msk                  (0x1UL << EXTI_RTSR1_RT5_Pos)           /*!< 0x00000020 */
8266 #define EXTI_RTSR1_RT5                      EXTI_RTSR1_RT5_Msk                      /*!< Rising trigger configuration for input line 5 */
8267 #define EXTI_RTSR1_RT6_Pos                  (6U)
8268 #define EXTI_RTSR1_RT6_Msk                  (0x1UL << EXTI_RTSR1_RT6_Pos)           /*!< 0x00000040 */
8269 #define EXTI_RTSR1_RT6                      EXTI_RTSR1_RT6_Msk                      /*!< Rising trigger configuration for input line 6 */
8270 #define EXTI_RTSR1_RT7_Pos                  (7U)
8271 #define EXTI_RTSR1_RT7_Msk                  (0x1UL << EXTI_RTSR1_RT7_Pos)           /*!< 0x00000080 */
8272 #define EXTI_RTSR1_RT7                      EXTI_RTSR1_RT7_Msk                      /*!< Rising trigger configuration for input line 7 */
8273 #define EXTI_RTSR1_RT8_Pos                  (8U)
8274 #define EXTI_RTSR1_RT8_Msk                  (0x1UL << EXTI_RTSR1_RT8_Pos)           /*!< 0x00000100 */
8275 #define EXTI_RTSR1_RT8                      EXTI_RTSR1_RT8_Msk                      /*!< Rising trigger configuration for input line 8 */
8276 #define EXTI_RTSR1_RT9_Pos                  (9U)
8277 #define EXTI_RTSR1_RT9_Msk                  (0x1UL << EXTI_RTSR1_RT9_Pos)           /*!< 0x00000200 */
8278 #define EXTI_RTSR1_RT9                      EXTI_RTSR1_RT9_Msk                      /*!< Rising trigger configuration for input line 9 */
8279 #define EXTI_RTSR1_RT10_Pos                 (10U)
8280 #define EXTI_RTSR1_RT10_Msk                 (0x1UL << EXTI_RTSR1_RT10_Pos)          /*!< 0x00000400 */
8281 #define EXTI_RTSR1_RT10                     EXTI_RTSR1_RT10_Msk                     /*!< Rising trigger configuration for input line 10 */
8282 #define EXTI_RTSR1_RT11_Pos                 (11U)
8283 #define EXTI_RTSR1_RT11_Msk                 (0x1UL << EXTI_RTSR1_RT11_Pos)          /*!< 0x00000800 */
8284 #define EXTI_RTSR1_RT11                     EXTI_RTSR1_RT11_Msk                     /*!< Rising trigger configuration for input line 11 */
8285 #define EXTI_RTSR1_RT12_Pos                 (12U)
8286 #define EXTI_RTSR1_RT12_Msk                 (0x1UL << EXTI_RTSR1_RT12_Pos)          /*!< 0x00001000 */
8287 #define EXTI_RTSR1_RT12                     EXTI_RTSR1_RT12_Msk                     /*!< Rising trigger configuration for input line 12 */
8288 #define EXTI_RTSR1_RT13_Pos                 (13U)
8289 #define EXTI_RTSR1_RT13_Msk                 (0x1UL << EXTI_RTSR1_RT13_Pos)          /*!< 0x00002000 */
8290 #define EXTI_RTSR1_RT13                     EXTI_RTSR1_RT13_Msk                     /*!< Rising trigger configuration for input line 13 */
8291 #define EXTI_RTSR1_RT14_Pos                 (14U)
8292 #define EXTI_RTSR1_RT14_Msk                 (0x1UL << EXTI_RTSR1_RT14_Pos)          /*!< 0x00004000 */
8293 #define EXTI_RTSR1_RT14                     EXTI_RTSR1_RT14_Msk                     /*!< Rising trigger configuration for input line 14 */
8294 #define EXTI_RTSR1_RT15_Pos                 (15U)
8295 #define EXTI_RTSR1_RT15_Msk                 (0x1UL << EXTI_RTSR1_RT15_Pos)          /*!< 0x00008000 */
8296 #define EXTI_RTSR1_RT15                     EXTI_RTSR1_RT15_Msk                     /*!< Rising trigger configuration for input line 15 */
8297 #define EXTI_RTSR1_RT16_Pos                 (16U)
8298 #define EXTI_RTSR1_RT16_Msk                 (0x1UL << EXTI_RTSR1_RT16_Pos)          /*!< 0x00010000 */
8299 #define EXTI_RTSR1_RT16                     EXTI_RTSR1_RT16_Msk                     /*!< Rising trigger configuration for input line 16 */
8300 
8301 /******************  Bit definition for EXTI_FTSR1 register  ******************/
8302 #define EXTI_FTSR1_FT0_Pos                  (0U)
8303 #define EXTI_FTSR1_FT0_Msk                  (0x1UL << EXTI_FTSR1_FT0_Pos)           /*!< 0x00000001 */
8304 #define EXTI_FTSR1_FT0                      EXTI_FTSR1_FT0_Msk                      /*!< Falling trigger configuration for input line 0 */
8305 #define EXTI_FTSR1_FT1_Pos                  (1U)
8306 #define EXTI_FTSR1_FT1_Msk                  (0x1UL << EXTI_FTSR1_FT1_Pos)           /*!< 0x00000002 */
8307 #define EXTI_FTSR1_FT1                      EXTI_FTSR1_FT1_Msk                      /*!< Falling trigger configuration for input line 1 */
8308 #define EXTI_FTSR1_FT2_Pos                  (2U)
8309 #define EXTI_FTSR1_FT2_Msk                  (0x1UL << EXTI_FTSR1_FT2_Pos)           /*!< 0x00000004 */
8310 #define EXTI_FTSR1_FT2                      EXTI_FTSR1_FT2_Msk                      /*!< Falling trigger configuration for input line 2 */
8311 #define EXTI_FTSR1_FT3_Pos                  (3U)
8312 #define EXTI_FTSR1_FT3_Msk                  (0x1UL << EXTI_FTSR1_FT3_Pos)           /*!< 0x00000008 */
8313 #define EXTI_FTSR1_FT3                      EXTI_FTSR1_FT3_Msk                      /*!< Falling trigger configuration for input line 3 */
8314 #define EXTI_FTSR1_FT4_Pos                  (4U)
8315 #define EXTI_FTSR1_FT4_Msk                  (0x1UL << EXTI_FTSR1_FT4_Pos)           /*!< 0x00000010 */
8316 #define EXTI_FTSR1_FT4                      EXTI_FTSR1_FT4_Msk                      /*!< Falling trigger configuration for input line 4 */
8317 #define EXTI_FTSR1_FT5_Pos                  (5U)
8318 #define EXTI_FTSR1_FT5_Msk                  (0x1UL << EXTI_FTSR1_FT5_Pos)           /*!< 0x00000020 */
8319 #define EXTI_FTSR1_FT5                      EXTI_FTSR1_FT5_Msk                      /*!< Falling trigger configuration for input line 5 */
8320 #define EXTI_FTSR1_FT6_Pos                  (6U)
8321 #define EXTI_FTSR1_FT6_Msk                  (0x1UL << EXTI_FTSR1_FT6_Pos)           /*!< 0x00000040 */
8322 #define EXTI_FTSR1_FT6                      EXTI_FTSR1_FT6_Msk                      /*!< Falling trigger configuration for input line 6 */
8323 #define EXTI_FTSR1_FT7_Pos                  (7U)
8324 #define EXTI_FTSR1_FT7_Msk                  (0x1UL << EXTI_FTSR1_FT7_Pos)           /*!< 0x00000080 */
8325 #define EXTI_FTSR1_FT7                      EXTI_FTSR1_FT7_Msk                      /*!< Falling trigger configuration for input line 7 */
8326 #define EXTI_FTSR1_FT8_Pos                  (8U)
8327 #define EXTI_FTSR1_FT8_Msk                  (0x1UL << EXTI_FTSR1_FT8_Pos)           /*!< 0x00000100 */
8328 #define EXTI_FTSR1_FT8                      EXTI_FTSR1_FT8_Msk                      /*!< Falling trigger configuration for input line 8 */
8329 #define EXTI_FTSR1_FT9_Pos                  (9U)
8330 #define EXTI_FTSR1_FT9_Msk                  (0x1UL << EXTI_FTSR1_FT9_Pos)           /*!< 0x00000200 */
8331 #define EXTI_FTSR1_FT9                      EXTI_FTSR1_FT9_Msk                      /*!< Falling trigger configuration for input line 9 */
8332 #define EXTI_FTSR1_FT10_Pos                 (10U)
8333 #define EXTI_FTSR1_FT10_Msk                 (0x1UL << EXTI_FTSR1_FT10_Pos)          /*!< 0x00000400 */
8334 #define EXTI_FTSR1_FT10                     EXTI_FTSR1_FT10_Msk                     /*!< Falling trigger configuration for input line 10 */
8335 #define EXTI_FTSR1_FT11_Pos                 (11U)
8336 #define EXTI_FTSR1_FT11_Msk                 (0x1UL << EXTI_FTSR1_FT11_Pos)          /*!< 0x00000800 */
8337 #define EXTI_FTSR1_FT11                     EXTI_FTSR1_FT11_Msk                     /*!< Falling trigger configuration for input line 11 */
8338 #define EXTI_FTSR1_FT12_Pos                 (12U)
8339 #define EXTI_FTSR1_FT12_Msk                 (0x1UL << EXTI_FTSR1_FT12_Pos)          /*!< 0x00001000 */
8340 #define EXTI_FTSR1_FT12                     EXTI_FTSR1_FT12_Msk                     /*!< Falling trigger configuration for input line 12 */
8341 #define EXTI_FTSR1_FT13_Pos                 (13U)
8342 #define EXTI_FTSR1_FT13_Msk                 (0x1UL << EXTI_FTSR1_FT13_Pos)          /*!< 0x00002000 */
8343 #define EXTI_FTSR1_FT13                     EXTI_FTSR1_FT13_Msk                     /*!< Falling trigger configuration for input line 13 */
8344 #define EXTI_FTSR1_FT14_Pos                 (14U)
8345 #define EXTI_FTSR1_FT14_Msk                 (0x1UL << EXTI_FTSR1_FT14_Pos)          /*!< 0x00004000 */
8346 #define EXTI_FTSR1_FT14                     EXTI_FTSR1_FT14_Msk                     /*!< Falling trigger configuration for input line 14 */
8347 #define EXTI_FTSR1_FT15_Pos                 (15U)
8348 #define EXTI_FTSR1_FT15_Msk                 (0x1UL << EXTI_FTSR1_FT15_Pos)          /*!< 0x00008000 */
8349 #define EXTI_FTSR1_FT15                     EXTI_FTSR1_FT15_Msk                     /*!< Falling trigger configuration for input line 15 */
8350 #define EXTI_FTSR1_FT16_Pos                 (16U)
8351 #define EXTI_FTSR1_FT16_Msk                 (0x1UL << EXTI_FTSR1_FT16_Pos)          /*!< 0x00010000 */
8352 #define EXTI_FTSR1_FT16                     EXTI_FTSR1_FT16_Msk                     /*!< Falling trigger configuration for input line 16 */
8353 
8354 /******************  Bit definition for EXTI_SWIER1 register  *****************/
8355 #define EXTI_SWIER1_SWI0_Pos                (0U)
8356 #define EXTI_SWIER1_SWI0_Msk                (0x1UL << EXTI_SWIER1_SWI0_Pos)         /*!< 0x00000001 */
8357 #define EXTI_SWIER1_SWI0                    EXTI_SWIER1_SWI0_Msk                    /*!< Software Interrupt on line 0 */
8358 #define EXTI_SWIER1_SWI1_Pos                (1U)
8359 #define EXTI_SWIER1_SWI1_Msk                (0x1UL << EXTI_SWIER1_SWI1_Pos)         /*!< 0x00000002 */
8360 #define EXTI_SWIER1_SWI1                    EXTI_SWIER1_SWI1_Msk                    /*!< Software Interrupt on line 1 */
8361 #define EXTI_SWIER1_SWI2_Pos                (2U)
8362 #define EXTI_SWIER1_SWI2_Msk                (0x1UL << EXTI_SWIER1_SWI2_Pos)         /*!< 0x00000004 */
8363 #define EXTI_SWIER1_SWI2                    EXTI_SWIER1_SWI2_Msk                    /*!< Software Interrupt on line 2 */
8364 #define EXTI_SWIER1_SWI3_Pos                (3U)
8365 #define EXTI_SWIER1_SWI3_Msk                (0x1UL << EXTI_SWIER1_SWI3_Pos)         /*!< 0x00000008 */
8366 #define EXTI_SWIER1_SWI3                    EXTI_SWIER1_SWI3_Msk                    /*!< Software Interrupt on line 3 */
8367 #define EXTI_SWIER1_SWI4_Pos                (4U)
8368 #define EXTI_SWIER1_SWI4_Msk                (0x1UL << EXTI_SWIER1_SWI4_Pos)         /*!< 0x00000010 */
8369 #define EXTI_SWIER1_SWI4                    EXTI_SWIER1_SWI4_Msk                    /*!< Software Interrupt on line 4 */
8370 #define EXTI_SWIER1_SWI5_Pos                (5U)
8371 #define EXTI_SWIER1_SWI5_Msk                (0x1UL << EXTI_SWIER1_SWI5_Pos)         /*!< 0x00000020 */
8372 #define EXTI_SWIER1_SWI5                    EXTI_SWIER1_SWI5_Msk                    /*!< Software Interrupt on line 5 */
8373 #define EXTI_SWIER1_SWI6_Pos                (6U)
8374 #define EXTI_SWIER1_SWI6_Msk                (0x1UL << EXTI_SWIER1_SWI6_Pos)         /*!< 0x00000040 */
8375 #define EXTI_SWIER1_SWI6                    EXTI_SWIER1_SWI6_Msk                    /*!< Software Interrupt on line 6 */
8376 #define EXTI_SWIER1_SWI7_Pos                (7U)
8377 #define EXTI_SWIER1_SWI7_Msk                (0x1UL << EXTI_SWIER1_SWI7_Pos)         /*!< 0x00000080 */
8378 #define EXTI_SWIER1_SWI7                    EXTI_SWIER1_SWI7_Msk                    /*!< Software Interrupt on line 7 */
8379 #define EXTI_SWIER1_SWI8_Pos                (8U)
8380 #define EXTI_SWIER1_SWI8_Msk                (0x1UL << EXTI_SWIER1_SWI8_Pos)         /*!< 0x00000100 */
8381 #define EXTI_SWIER1_SWI8                    EXTI_SWIER1_SWI8_Msk                    /*!< Software Interrupt on line 8 */
8382 #define EXTI_SWIER1_SWI9_Pos                (9U)
8383 #define EXTI_SWIER1_SWI9_Msk                (0x1UL << EXTI_SWIER1_SWI9_Pos)         /*!< 0x00000200 */
8384 #define EXTI_SWIER1_SWI9                    EXTI_SWIER1_SWI9_Msk                    /*!< Software Interrupt on line 9 */
8385 #define EXTI_SWIER1_SWI10_Pos               (10U)
8386 #define EXTI_SWIER1_SWI10_Msk               (0x1UL << EXTI_SWIER1_SWI10_Pos)        /*!< 0x00000400 */
8387 #define EXTI_SWIER1_SWI10                   EXTI_SWIER1_SWI10_Msk                   /*!< Software Interrupt on line 10 */
8388 #define EXTI_SWIER1_SWI11_Pos               (11U)
8389 #define EXTI_SWIER1_SWI11_Msk               (0x1UL << EXTI_SWIER1_SWI11_Pos)        /*!< 0x00000800 */
8390 #define EXTI_SWIER1_SWI11                   EXTI_SWIER1_SWI11_Msk                   /*!< Software Interrupt on line 11 */
8391 #define EXTI_SWIER1_SWI12_Pos               (12U)
8392 #define EXTI_SWIER1_SWI12_Msk               (0x1UL << EXTI_SWIER1_SWI12_Pos)        /*!< 0x00001000 */
8393 #define EXTI_SWIER1_SWI12                   EXTI_SWIER1_SWI12_Msk                   /*!< Software Interrupt on line 12 */
8394 #define EXTI_SWIER1_SWI13_Pos               (13U)
8395 #define EXTI_SWIER1_SWI13_Msk               (0x1UL << EXTI_SWIER1_SWI13_Pos)        /*!< 0x00002000 */
8396 #define EXTI_SWIER1_SWI13                   EXTI_SWIER1_SWI13_Msk                   /*!< Software Interrupt on line 13 */
8397 #define EXTI_SWIER1_SWI14_Pos               (14U)
8398 #define EXTI_SWIER1_SWI14_Msk               (0x1UL << EXTI_SWIER1_SWI14_Pos)        /*!< 0x00004000 */
8399 #define EXTI_SWIER1_SWI14                   EXTI_SWIER1_SWI14_Msk                   /*!< Software Interrupt on line 14 */
8400 #define EXTI_SWIER1_SWI15_Pos               (15U)
8401 #define EXTI_SWIER1_SWI15_Msk               (0x1UL << EXTI_SWIER1_SWI15_Pos)        /*!< 0x00008000 */
8402 #define EXTI_SWIER1_SWI15                   EXTI_SWIER1_SWI15_Msk                   /*!< Software Interrupt on line 15 */
8403 #define EXTI_SWIER1_SWI16_Pos               (16U)
8404 #define EXTI_SWIER1_SWI16_Msk               (0x1UL << EXTI_SWIER1_SWI16_Pos)        /*!< 0x00010000 */
8405 #define EXTI_SWIER1_SWI16                   EXTI_SWIER1_SWI16_Msk                   /*!< Software Interrupt on line 16 */
8406 
8407 
8408 /*******************  Bit definition for EXTI_RPR1 register  ******************/
8409 #define EXTI_RPR1_RPIF0_Pos                 (0U)
8410 #define EXTI_RPR1_RPIF0_Msk                 (0x1UL << EXTI_RPR1_RPIF0_Pos)          /*!< 0x00000001 */
8411 #define EXTI_RPR1_RPIF0                     EXTI_RPR1_RPIF0_Msk                     /*!< Rising Pending Interrupt Flag on line 0 */
8412 #define EXTI_RPR1_RPIF1_Pos                 (1U)
8413 #define EXTI_RPR1_RPIF1_Msk                 (0x1UL << EXTI_RPR1_RPIF1_Pos)          /*!< 0x00000002 */
8414 #define EXTI_RPR1_RPIF1                     EXTI_RPR1_RPIF1_Msk                     /*!< Rising Pending Interrupt Flag on line 1 */
8415 #define EXTI_RPR1_RPIF2_Pos                 (2U)
8416 #define EXTI_RPR1_RPIF2_Msk                 (0x1UL << EXTI_RPR1_RPIF2_Pos)          /*!< 0x00000004 */
8417 #define EXTI_RPR1_RPIF2                     EXTI_RPR1_RPIF2_Msk                     /*!< Rising Pending Interrupt Flag on line 2 */
8418 #define EXTI_RPR1_RPIF3_Pos                 (3U)
8419 #define EXTI_RPR1_RPIF3_Msk                 (0x1UL << EXTI_RPR1_RPIF3_Pos)          /*!< 0x00000008 */
8420 #define EXTI_RPR1_RPIF3                     EXTI_RPR1_RPIF3_Msk                     /*!< Rising Pending Interrupt Flag on line 3 */
8421 #define EXTI_RPR1_RPIF4_Pos                 (4U)
8422 #define EXTI_RPR1_RPIF4_Msk                 (0x1UL << EXTI_RPR1_RPIF4_Pos)          /*!< 0x00000010 */
8423 #define EXTI_RPR1_RPIF4                     EXTI_RPR1_RPIF4_Msk                     /*!< Rising Pending Interrupt Flag on line 4 */
8424 #define EXTI_RPR1_RPIF5_Pos                 (5U)
8425 #define EXTI_RPR1_RPIF5_Msk                 (0x1UL << EXTI_RPR1_RPIF5_Pos)          /*!< 0x00000020 */
8426 #define EXTI_RPR1_RPIF5                     EXTI_RPR1_RPIF5_Msk                     /*!< Rising Pending Interrupt Flag on line 5 */
8427 #define EXTI_RPR1_RPIF6_Pos                 (6U)
8428 #define EXTI_RPR1_RPIF6_Msk                 (0x1UL << EXTI_RPR1_RPIF6_Pos)          /*!< 0x00000040 */
8429 #define EXTI_RPR1_RPIF6                     EXTI_RPR1_RPIF6_Msk                     /*!< Rising Pending Interrupt Flag on line 6 */
8430 #define EXTI_RPR1_RPIF7_Pos                 (7U)
8431 #define EXTI_RPR1_RPIF7_Msk                 (0x1UL << EXTI_RPR1_RPIF7_Pos)          /*!< 0x00000080 */
8432 #define EXTI_RPR1_RPIF7                     EXTI_RPR1_RPIF7_Msk                     /*!< Rising Pending Interrupt Flag on line 7 */
8433 #define EXTI_RPR1_RPIF8_Pos                 (8U)
8434 #define EXTI_RPR1_RPIF8_Msk                 (0x1UL << EXTI_RPR1_RPIF8_Pos)          /*!< 0x00000100 */
8435 #define EXTI_RPR1_RPIF8                     EXTI_RPR1_RPIF8_Msk                     /*!< Rising Pending Interrupt Flag on line 8 */
8436 #define EXTI_RPR1_RPIF9_Pos                 (9U)
8437 #define EXTI_RPR1_RPIF9_Msk                 (0x1UL << EXTI_RPR1_RPIF9_Pos)          /*!< 0x00000200 */
8438 #define EXTI_RPR1_RPIF9                     EXTI_RPR1_RPIF9_Msk                     /*!< Rising Pending Interrupt Flag on line 9 */
8439 #define EXTI_RPR1_RPIF10_Pos                (10U)
8440 #define EXTI_RPR1_RPIF10_Msk                (0x1UL << EXTI_RPR1_RPIF10_Pos)         /*!< 0x00000400 */
8441 #define EXTI_RPR1_RPIF10                    EXTI_RPR1_RPIF10_Msk                    /*!< Rising Pending Interrupt Flag on line 10 */
8442 #define EXTI_RPR1_RPIF11_Pos                (11U)
8443 #define EXTI_RPR1_RPIF11_Msk                (0x1UL << EXTI_RPR1_RPIF11_Pos)         /*!< 0x00000800 */
8444 #define EXTI_RPR1_RPIF11                    EXTI_RPR1_RPIF11_Msk                    /*!< Rising Pending Interrupt Flag on line 11 */
8445 #define EXTI_RPR1_RPIF12_Pos                (12U)
8446 #define EXTI_RPR1_RPIF12_Msk                (0x1UL << EXTI_RPR1_RPIF12_Pos)         /*!< 0x00001000 */
8447 #define EXTI_RPR1_RPIF12                    EXTI_RPR1_RPIF12_Msk                    /*!< Rising Pending Interrupt Flag on line 12 */
8448 #define EXTI_RPR1_RPIF13_Pos                (13U)
8449 #define EXTI_RPR1_RPIF13_Msk                (0x1UL << EXTI_RPR1_RPIF13_Pos)         /*!< 0x00002000 */
8450 #define EXTI_RPR1_RPIF13                    EXTI_RPR1_RPIF13_Msk                    /*!< Rising Pending Interrupt Flag on line 13 */
8451 #define EXTI_RPR1_RPIF14_Pos                (14U)
8452 #define EXTI_RPR1_RPIF14_Msk                (0x1UL << EXTI_RPR1_RPIF14_Pos)         /*!< 0x00004000 */
8453 #define EXTI_RPR1_RPIF14                    EXTI_RPR1_RPIF14_Msk                    /*!< Rising Pending Interrupt Flag on line 14 */
8454 #define EXTI_RPR1_RPIF15_Pos                (15U)
8455 #define EXTI_RPR1_RPIF15_Msk                (0x1UL << EXTI_RPR1_RPIF15_Pos)         /*!< 0x00008000 */
8456 #define EXTI_RPR1_RPIF15                    EXTI_RPR1_RPIF15_Msk                    /*!< Rising Pending Interrupt Flag on line 15 */
8457 #define EXTI_RPR1_RPIF16_Pos                (16U)
8458 #define EXTI_RPR1_RPIF16_Msk                (0x1UL << EXTI_RPR1_RPIF16_Pos)         /*!< 0x00010000 */
8459 #define EXTI_RPR1_RPIF16                    EXTI_RPR1_RPIF16_Msk                    /*!< Rising Pending Interrupt Flag on line 16 */
8460 
8461 /*******************  Bit definition for EXTI_FPR1 register  ******************/
8462 #define EXTI_FPR1_FPIF0_Pos                 (0U)
8463 #define EXTI_FPR1_FPIF0_Msk                 (0x1UL << EXTI_FPR1_FPIF0_Pos)          /*!< 0x00000001 */
8464 #define EXTI_FPR1_FPIF0                     EXTI_FPR1_FPIF0_Msk                     /*!< Falling Pending Interrupt Flag on line 0 */
8465 #define EXTI_FPR1_FPIF1_Pos                 (1U)
8466 #define EXTI_FPR1_FPIF1_Msk                 (0x1UL << EXTI_FPR1_FPIF1_Pos)          /*!< 0x00000002 */
8467 #define EXTI_FPR1_FPIF1                     EXTI_FPR1_FPIF1_Msk                     /*!< Falling Pending Interrupt Flag on line 1 */
8468 #define EXTI_FPR1_FPIF2_Pos                 (2U)
8469 #define EXTI_FPR1_FPIF2_Msk                 (0x1UL << EXTI_FPR1_FPIF2_Pos)          /*!< 0x00000004 */
8470 #define EXTI_FPR1_FPIF2                     EXTI_FPR1_FPIF2_Msk                     /*!< Falling Pending Interrupt Flag on line 2 */
8471 #define EXTI_FPR1_FPIF3_Pos                 (3U)
8472 #define EXTI_FPR1_FPIF3_Msk                 (0x1UL << EXTI_FPR1_FPIF3_Pos)          /*!< 0x00000008 */
8473 #define EXTI_FPR1_FPIF3                     EXTI_FPR1_FPIF3_Msk                     /*!< Falling Pending Interrupt Flag on line 3 */
8474 #define EXTI_FPR1_FPIF4_Pos                 (4U)
8475 #define EXTI_FPR1_FPIF4_Msk                 (0x1UL << EXTI_FPR1_FPIF4_Pos)          /*!< 0x00000010 */
8476 #define EXTI_FPR1_FPIF4                     EXTI_FPR1_FPIF4_Msk                     /*!< Falling Pending Interrupt Flag on line 4 */
8477 #define EXTI_FPR1_FPIF5_Pos                 (5U)
8478 #define EXTI_FPR1_FPIF5_Msk                 (0x1UL << EXTI_FPR1_FPIF5_Pos)          /*!< 0x00000020 */
8479 #define EXTI_FPR1_FPIF5                     EXTI_FPR1_FPIF5_Msk                     /*!< Falling Pending Interrupt Flag on line 5 */
8480 #define EXTI_FPR1_FPIF6_Pos                 (6U)
8481 #define EXTI_FPR1_FPIF6_Msk                 (0x1UL << EXTI_FPR1_FPIF6_Pos)          /*!< 0x00000040 */
8482 #define EXTI_FPR1_FPIF6                     EXTI_FPR1_FPIF6_Msk                     /*!< Falling Pending Interrupt Flag on line 6 */
8483 #define EXTI_FPR1_FPIF7_Pos                 (7U)
8484 #define EXTI_FPR1_FPIF7_Msk                 (0x1UL << EXTI_FPR1_FPIF7_Pos)          /*!< 0x00000080 */
8485 #define EXTI_FPR1_FPIF7                     EXTI_FPR1_FPIF7_Msk                     /*!< Falling Pending Interrupt Flag on line 7 */
8486 #define EXTI_FPR1_FPIF8_Pos                 (8U)
8487 #define EXTI_FPR1_FPIF8_Msk                 (0x1UL << EXTI_FPR1_FPIF8_Pos)          /*!< 0x00000100 */
8488 #define EXTI_FPR1_FPIF8                     EXTI_FPR1_FPIF8_Msk                     /*!< Falling Pending Interrupt Flag on line 8 */
8489 #define EXTI_FPR1_FPIF9_Pos                 (9U)
8490 #define EXTI_FPR1_FPIF9_Msk                 (0x1UL << EXTI_FPR1_FPIF9_Pos)          /*!< 0x00000200 */
8491 #define EXTI_FPR1_FPIF9                     EXTI_FPR1_FPIF9_Msk                     /*!< Falling Pending Interrupt Flag on line 9 */
8492 #define EXTI_FPR1_FPIF10_Pos                (10U)
8493 #define EXTI_FPR1_FPIF10_Msk                (0x1UL << EXTI_FPR1_FPIF10_Pos)         /*!< 0x00000400 */
8494 #define EXTI_FPR1_FPIF10                    EXTI_FPR1_FPIF10_Msk                    /*!< Falling Pending Interrupt Flag on line 10 */
8495 #define EXTI_FPR1_FPIF11_Pos                (11U)
8496 #define EXTI_FPR1_FPIF11_Msk                (0x1UL << EXTI_FPR1_FPIF11_Pos)         /*!< 0x00000800 */
8497 #define EXTI_FPR1_FPIF11                    EXTI_FPR1_FPIF11_Msk                    /*!< Falling Pending Interrupt Flag on line 11 */
8498 #define EXTI_FPR1_FPIF12_Pos                (12U)
8499 #define EXTI_FPR1_FPIF12_Msk                (0x1UL << EXTI_FPR1_FPIF12_Pos)         /*!< 0x00001000 */
8500 #define EXTI_FPR1_FPIF12                    EXTI_FPR1_FPIF12_Msk                    /*!< Falling Pending Interrupt Flag on line 12 */
8501 #define EXTI_FPR1_FPIF13_Pos                (13U)
8502 #define EXTI_FPR1_FPIF13_Msk                (0x1UL << EXTI_FPR1_FPIF13_Pos)         /*!< 0x00002000 */
8503 #define EXTI_FPR1_FPIF13                    EXTI_FPR1_FPIF13_Msk                    /*!< Falling Pending Interrupt Flag on line 13 */
8504 #define EXTI_FPR1_FPIF14_Pos                (14U)
8505 #define EXTI_FPR1_FPIF14_Msk                (0x1UL << EXTI_FPR1_FPIF14_Pos)         /*!< 0x00004000 */
8506 #define EXTI_FPR1_FPIF14                    EXTI_FPR1_FPIF14_Msk                    /*!< Falling Pending Interrupt Flag on line 14 */
8507 #define EXTI_FPR1_FPIF15_Pos                (15U)
8508 #define EXTI_FPR1_FPIF15_Msk                (0x1UL << EXTI_FPR1_FPIF15_Pos)         /*!< 0x00008000 */
8509 #define EXTI_FPR1_FPIF15                    EXTI_FPR1_FPIF15_Msk                    /*!< Falling Pending Interrupt Flag on line 15 */
8510 #define EXTI_FPR1_FPIF16_Pos                (16U)
8511 #define EXTI_FPR1_FPIF16_Msk                (0x1UL << EXTI_FPR1_FPIF16_Pos)         /*!< 0x00010000 */
8512 #define EXTI_FPR1_FPIF16                    EXTI_FPR1_FPIF16_Msk                    /*!< Falling Pending Interrupt Flag on line 16 */
8513 
8514 /*******************  Bit definition for EXTI_SECENR1 register  ******************/
8515 #define EXTI_SECENR1_SEC0_Pos              (0U)
8516 #define EXTI_SECENR1_SEC0_Msk              (0x1UL << EXTI_SECENR1_SEC0_Pos)       /*!< 0x00000001 */
8517 #define EXTI_SECENR1_SEC0                  EXTI_SECENR1_SEC0_Msk                  /*!< Security enable on line 0 */
8518 #define EXTI_SECENR1_SEC1_Pos              (1U)
8519 #define EXTI_SECENR1_SEC1_Msk              (0x1UL << EXTI_SECENR1_SEC1_Pos)       /*!< 0x00000002 */
8520 #define EXTI_SECENR1_SEC1                  EXTI_SECENR1_SEC1_Msk                  /*!< Security enable on line 1 */
8521 #define EXTI_SECENR1_SEC2_Pos              (2U)
8522 #define EXTI_SECENR1_SEC2_Msk              (0x1UL << EXTI_SECENR1_SEC2_Pos)       /*!< 0x00000004 */
8523 #define EXTI_SECENR1_SEC2                  EXTI_SECENR1_SEC2_Msk                  /*!< Security enable on line 2 */
8524 #define EXTI_SECENR1_SEC3_Pos              (3U)
8525 #define EXTI_SECENR1_SEC3_Msk              (0x1UL << EXTI_SECENR1_SEC3_Pos)       /*!< 0x00000008 */
8526 #define EXTI_SECENR1_SEC3                  EXTI_SECENR1_SEC3_Msk                  /*!< Security enable on line 3 */
8527 #define EXTI_SECENR1_SEC4_Pos              (4U)
8528 #define EXTI_SECENR1_SEC4_Msk              (0x1UL << EXTI_SECENR1_SEC4_Pos)       /*!< 0x00000010 */
8529 #define EXTI_SECENR1_SEC4                  EXTI_SECENR1_SEC4_Msk                  /*!< Security enable on line 4 */
8530 #define EXTI_SECENR1_SEC5_Pos              (5U)
8531 #define EXTI_SECENR1_SEC5_Msk              (0x1UL << EXTI_SECENR1_SEC5_Pos)       /*!< 0x00000020 */
8532 #define EXTI_SECENR1_SEC5                  EXTI_SECENR1_SEC5_Msk                  /*!< Security enable on line 5 */
8533 #define EXTI_SECENR1_SEC6_Pos              (6U)
8534 #define EXTI_SECENR1_SEC6_Msk              (0x1UL << EXTI_SECENR1_SEC6_Pos)       /*!< 0x00000040 */
8535 #define EXTI_SECENR1_SEC6                  EXTI_SECENR1_SEC6_Msk                  /*!< Security enable on line 6 */
8536 #define EXTI_SECENR1_SEC7_Pos              (7U)
8537 #define EXTI_SECENR1_SEC7_Msk              (0x1UL << EXTI_SECENR1_SEC7_Pos)       /*!< 0x00000080 */
8538 #define EXTI_SECENR1_SEC7                  EXTI_SECENR1_SEC7_Msk                  /*!< Security enable on line 7 */
8539 #define EXTI_SECENR1_SEC8_Pos              (8U)
8540 #define EXTI_SECENR1_SEC8_Msk              (0x1UL << EXTI_SECENR1_SEC8_Pos)       /*!< 0x00000100 */
8541 #define EXTI_SECENR1_SEC8                  EXTI_SECENR1_SEC8_Msk                  /*!< Security enable on line 8 */
8542 #define EXTI_SECENR1_SEC9_Pos              (9U)
8543 #define EXTI_SECENR1_SEC9_Msk              (0x1UL << EXTI_SECENR1_SEC9_Pos)       /*!< 0x00000200 */
8544 #define EXTI_SECENR1_SEC9                  EXTI_SECENR1_SEC9_Msk                  /*!< Security enable on line 9 */
8545 #define EXTI_SECENR1_SEC10_Pos             (10U)
8546 #define EXTI_SECENR1_SEC10_Msk             (0x1UL << EXTI_SECENR1_SEC10_Pos)      /*!< 0x00000400 */
8547 #define EXTI_SECENR1_SEC10                 EXTI_SECENR1_SEC10_Msk                 /*!< Security enable on line 10 */
8548 #define EXTI_SECENR1_SEC11_Pos             (11U)
8549 #define EXTI_SECENR1_SEC11_Msk             (0x1UL << EXTI_SECENR1_SEC11_Pos)      /*!< 0x00000800 */
8550 #define EXTI_SECENR1_SEC11                 EXTI_SECENR1_SEC11_Msk                 /*!< Security enable on line 11 */
8551 #define EXTI_SECENR1_SEC12_Pos             (12U)
8552 #define EXTI_SECENR1_SEC12_Msk             (0x1UL << EXTI_SECENR1_SEC12_Pos)      /*!< 0x00001000 */
8553 #define EXTI_SECENR1_SEC12                 EXTI_SECENR1_SEC12_Msk                 /*!< Security enable on line 12 */
8554 #define EXTI_SECENR1_SEC13_Pos             (13U)
8555 #define EXTI_SECENR1_SEC13_Msk             (0x1UL << EXTI_SECENR1_SEC13_Pos)      /*!< 0x00002000 */
8556 #define EXTI_SECENR1_SEC13                 EXTI_SECENR1_SEC13_Msk                 /*!< Security enable on line 13 */
8557 #define EXTI_SECENR1_SEC14_Pos             (14U)
8558 #define EXTI_SECENR1_SEC14_Msk             (0x1UL << EXTI_SECENR1_SEC14_Pos)      /*!< 0x00004000 */
8559 #define EXTI_SECENR1_SEC14                 EXTI_SECENR1_SEC14_Msk                 /*!< Security enable on line 14 */
8560 #define EXTI_SECENR1_SEC15_Pos             (15U)
8561 #define EXTI_SECENR1_SEC15_Msk             (0x1UL << EXTI_SECENR1_SEC15_Pos)      /*!< 0x00008000 */
8562 #define EXTI_SECENR1_SEC15                 EXTI_SECENR1_SEC15_Msk                 /*!< Security enable on line 15 */
8563 #define EXTI_SECENR1_SEC16_Pos             (16U)
8564 #define EXTI_SECENR1_SEC16_Msk             (0x1UL << EXTI_SECENR1_SEC16_Pos)      /*!< 0x00010000 */
8565 #define EXTI_SECENR1_SEC16                 EXTI_SECENR1_SEC16_Msk                 /*!< Security enable on line 16 */
8566 #define EXTI_SECENR1_SEC17_Pos             (17U)
8567 #define EXTI_SECENR1_SEC17_Msk             (0x1UL << EXTI_SECENR1_SEC17_Pos)      /*!< 0x00020000 */
8568 #define EXTI_SECENR1_SEC17                 EXTI_SECENR1_SEC17_Msk                 /*!< Security enable on line 17 */
8569 #define EXTI_SECENR1_SEC18_Pos             (18U)
8570 #define EXTI_SECENR1_SEC18_Msk             (0x1UL << EXTI_SECENR1_SEC18_Pos)      /*!< 0x00040000 */
8571 #define EXTI_SECENR1_SEC18                 EXTI_SECENR1_SEC18_Msk                 /*!< Security enable on line 18 */
8572 #define EXTI_SECENR1_SEC19_Pos             (19U)
8573 #define EXTI_SECENR1_SEC19_Msk             (0x1UL << EXTI_SECENR1_SEC19_Pos)      /*!< 0x00080000 */
8574 #define EXTI_SECENR1_SEC19                 EXTI_SECENR1_SEC19_Msk                 /*!< Security enable on line 19 */
8575 #define EXTI_SECENR1_SEC20_Pos             (20U)
8576 #define EXTI_SECENR1_SEC20_Msk             (0x1UL << EXTI_SECENR1_SEC20_Pos)      /*!< 0x00100000 */
8577 #define EXTI_SECENR1_SEC20                 EXTI_SECENR1_SEC20_Msk                 /*!< Security enable on line 20 */
8578 #define EXTI_SECENR1_SEC21_Pos             (21U)
8579 #define EXTI_SECENR1_SEC21_Msk             (0x1UL << EXTI_SECENR1_SEC21_Pos)      /*!< 0x00200000 */
8580 #define EXTI_SECENR1_SEC21                 EXTI_SECENR1_SEC21_Msk                 /*!< Security enable on line 21 */
8581 #define EXTI_SECENR1_SEC22_Pos             (22U)
8582 #define EXTI_SECENR1_SEC22_Msk             (0x1UL << EXTI_SECENR1_SEC22_Pos)      /*!< 0x00400000 */
8583 #define EXTI_SECENR1_SEC22                 EXTI_SECENR1_SEC22_Msk                 /*!< Security enable on line 22 */
8584 #define EXTI_SECENR1_SEC23_Pos             (23U)
8585 #define EXTI_SECENR1_SEC23_Msk             (0x1UL << EXTI_SECENR1_SEC23_Pos)      /*!< 0x00800000 */
8586 #define EXTI_SECENR1_SEC23                 EXTI_SECENR1_SEC23_Msk                 /*!< Security enable on line 23 */
8587 #define EXTI_SECENR1_SEC24_Pos             (24U)
8588 #define EXTI_SECENR1_SEC24_Msk             (0x1UL << EXTI_SECENR1_SEC24_Pos)      /*!< 0x01000000 */
8589 #define EXTI_SECENR1_SEC24                 EXTI_SECENR1_SEC24_Msk                 /*!< Security enable on line 24 */
8590 #define EXTI_SECENR1_SEC25_Pos             (25U)
8591 #define EXTI_SECENR1_SEC25_Msk             (0x1UL << EXTI_SECENR1_SEC25_Pos)      /*!< 0x02000000 */
8592 #define EXTI_SECENR1_SEC25                 EXTI_SECENR1_SEC25_Msk                 /*!< Security enable on line 25 */
8593 #define EXTI_SECENR1_SEC26_Pos             (26U)
8594 #define EXTI_SECENR1_SEC26_Msk             (0x1UL << EXTI_SECENR1_SEC26_Pos)      /*!< 0x04000000 */
8595 #define EXTI_SECENR1_SEC26                 EXTI_SECENR1_SEC26_Msk                 /*!< Security enable on line 26 */
8596 #define EXTI_SECENR1_SEC27_Pos             (27U)
8597 #define EXTI_SECENR1_SEC27_Msk             (0x1UL << EXTI_SECENR1_SEC27_Pos)      /*!< 0x08000000 */
8598 #define EXTI_SECENR1_SEC27                 EXTI_SECENR1_SEC27_Msk                 /*!< Security enable on line 27 */
8599 #define EXTI_SECENR1_SEC28_Pos             (28U)
8600 #define EXTI_SECENR1_SEC28_Msk             (0x1UL << EXTI_SECENR1_SEC28_Pos)      /*!< 0x10000000 */
8601 #define EXTI_SECENR1_SEC28                 EXTI_SECENR1_SEC28_Msk                 /*!< Security enable on line 28 */
8602 #define EXTI_SECENR1_SEC29_Pos             (29U)
8603 #define EXTI_SECENR1_SEC29_Msk             (0x1UL << EXTI_SECENR1_SEC29_Pos)      /*!< 0x20000000 */
8604 #define EXTI_SECENR1_SEC29                 EXTI_SECENR1_SEC29_Msk                 /*!< Security enable on line 29 */
8605 #define EXTI_SECENR1_SEC30_Pos             (30U)
8606 #define EXTI_SECENR1_SEC30_Msk             (0x1UL << EXTI_SECENR1_SEC30_Pos)      /*!< 0x40000000 */
8607 #define EXTI_SECENR1_SEC30                 EXTI_SECENR1_SEC30_Msk                 /*!< Security enable on line 30 */
8608 #define EXTI_SECENR1_SEC31_Pos             (31U)
8609 #define EXTI_SECENR1_SEC31_Msk             (0x1UL << EXTI_SECENR1_SEC31_Pos)      /*!< 0x80000000 */
8610 #define EXTI_SECENR1_SEC31                 EXTI_SECENR1_SEC31_Msk                 /*!< Security enable on line 31 */
8611 
8612 
8613 /*******************  Bit definition for EXTI_PRIVENR1 register  ******************/
8614 #define EXTI_PRIVENR1_PRIV0_Pos             (0U)
8615 #define EXTI_PRIVENR1_PRIV0_Msk             (0x1UL << EXTI_PRIVENR1_PRIV0_Pos)      /*!< 0x00000001 */
8616 #define EXTI_PRIVENR1_PRIV0                 EXTI_PRIVENR1_PRIV0_Msk                 /*!< Privilege enable on line 0 */
8617 #define EXTI_PRIVENR1_PRIV1_Pos             (1U)
8618 #define EXTI_PRIVENR1_PRIV1_Msk             (0x1UL << EXTI_PRIVENR1_PRIV1_Pos)      /*!< 0x00000002 */
8619 #define EXTI_PRIVENR1_PRIV1                 EXTI_PRIVENR1_PRIV1_Msk                 /*!< Privilege enable on line 1 */
8620 #define EXTI_PRIVENR1_PRIV2_Pos             (2U)
8621 #define EXTI_PRIVENR1_PRIV2_Msk             (0x1UL << EXTI_PRIVENR1_PRIV2_Pos)      /*!< 0x00000004 */
8622 #define EXTI_PRIVENR1_PRIV2                 EXTI_PRIVENR1_PRIV2_Msk                 /*!< Privilege enable on line 2 */
8623 #define EXTI_PRIVENR1_PRIV3_Pos             (3U)
8624 #define EXTI_PRIVENR1_PRIV3_Msk             (0x1UL << EXTI_PRIVENR1_PRIV3_Pos)      /*!< 0x00000008 */
8625 #define EXTI_PRIVENR1_PRIV3                 EXTI_PRIVENR1_PRIV3_Msk                 /*!< Privilege enable on line 3 */
8626 #define EXTI_PRIVENR1_PRIV4_Pos             (4U)
8627 #define EXTI_PRIVENR1_PRIV4_Msk             (0x1UL << EXTI_PRIVENR1_PRIV4_Pos)      /*!< 0x00000010 */
8628 #define EXTI_PRIVENR1_PRIV4                 EXTI_PRIVENR1_PRIV4_Msk                 /*!< Privilege enable on line 4 */
8629 #define EXTI_PRIVENR1_PRIV5_Pos             (5U)
8630 #define EXTI_PRIVENR1_PRIV5_Msk             (0x1UL << EXTI_PRIVENR1_PRIV5_Pos)      /*!< 0x00000020 */
8631 #define EXTI_PRIVENR1_PRIV5                 EXTI_PRIVENR1_PRIV5_Msk                 /*!< Privilege enable on line 5 */
8632 #define EXTI_PRIVENR1_PRIV6_Pos             (6U)
8633 #define EXTI_PRIVENR1_PRIV6_Msk             (0x1UL << EXTI_PRIVENR1_PRIV6_Pos)      /*!< 0x00000040 */
8634 #define EXTI_PRIVENR1_PRIV6                 EXTI_PRIVENR1_PRIV6_Msk                 /*!< Privilege enable on line 6 */
8635 #define EXTI_PRIVENR1_PRIV7_Pos             (7U)
8636 #define EXTI_PRIVENR1_PRIV7_Msk             (0x1UL << EXTI_PRIVENR1_PRIV7_Pos)      /*!< 0x00000080 */
8637 #define EXTI_PRIVENR1_PRIV7                 EXTI_PRIVENR1_PRIV7_Msk                 /*!< Privilege enable on line 7 */
8638 #define EXTI_PRIVENR1_PRIV8_Pos             (8U)
8639 #define EXTI_PRIVENR1_PRIV8_Msk             (0x1UL << EXTI_PRIVENR1_PRIV8_Pos)      /*!< 0x00000100 */
8640 #define EXTI_PRIVENR1_PRIV8                 EXTI_PRIVENR1_PRIV8_Msk                 /*!< Privilege enable on line 8 */
8641 #define EXTI_PRIVENR1_PRIV9_Pos             (9U)
8642 #define EXTI_PRIVENR1_PRIV9_Msk             (0x1UL << EXTI_PRIVENR1_PRIV9_Pos)      /*!< 0x00000200 */
8643 #define EXTI_PRIVENR1_PRIV9                 EXTI_PRIVENR1_PRIV9_Msk                 /*!< Privilege enable on line 9 */
8644 #define EXTI_PRIVENR1_PRIV10_Pos            (10U)
8645 #define EXTI_PRIVENR1_PRIV10_Msk            (0x1UL << EXTI_PRIVENR1_PRIV10_Pos)     /*!< 0x00000400 */
8646 #define EXTI_PRIVENR1_PRIV10                EXTI_PRIVENR1_PRIV10_Msk                /*!< Privilege enable on line 10 */
8647 #define EXTI_PRIVENR1_PRIV11_Pos            (11U)
8648 #define EXTI_PRIVENR1_PRIV11_Msk            (0x1UL << EXTI_PRIVENR1_PRIV11_Pos)     /*!< 0x00000800 */
8649 #define EXTI_PRIVENR1_PRIV11                EXTI_PRIVENR1_PRIV11_Msk                /*!< Privilege enable on line 11 */
8650 #define EXTI_PRIVENR1_PRIV12_Pos            (12U)
8651 #define EXTI_PRIVENR1_PRIV12_Msk            (0x1UL << EXTI_PRIVENR1_PRIV12_Pos)     /*!< 0x00001000 */
8652 #define EXTI_PRIVENR1_PRIV12                EXTI_PRIVENR1_PRIV12_Msk                /*!< Privilege enable on line 12 */
8653 #define EXTI_PRIVENR1_PRIV13_Pos            (13U)
8654 #define EXTI_PRIVENR1_PRIV13_Msk            (0x1UL << EXTI_PRIVENR1_PRIV13_Pos)     /*!< 0x00002000 */
8655 #define EXTI_PRIVENR1_PRIV13                EXTI_PRIVENR1_PRIV13_Msk                /*!< Privilege enable on line 13 */
8656 #define EXTI_PRIVENR1_PRIV14_Pos            (14U)
8657 #define EXTI_PRIVENR1_PRIV14_Msk            (0x1UL << EXTI_PRIVENR1_PRIV14_Pos)     /*!< 0x00004000 */
8658 #define EXTI_PRIVENR1_PRIV14                EXTI_PRIVENR1_PRIV14_Msk                /*!< Privilege enable on line 14 */
8659 #define EXTI_PRIVENR1_PRIV15_Pos            (15U)
8660 #define EXTI_PRIVENR1_PRIV15_Msk            (0x1UL << EXTI_PRIVENR1_PRIV15_Pos)     /*!< 0x00008000 */
8661 #define EXTI_PRIVENR1_PRIV15                EXTI_PRIVENR1_PRIV15_Msk                /*!< Privilege enable on line 15 */
8662 #define EXTI_PRIVENR1_PRIV16_Pos            (16U)
8663 #define EXTI_PRIVENR1_PRIV16_Msk            (0x1UL << EXTI_PRIVENR1_PRIV16_Pos)     /*!< 0x00010000 */
8664 #define EXTI_PRIVENR1_PRIV16                EXTI_PRIVENR1_PRIV16_Msk                /*!< Privilege enable on line 16 */
8665 #define EXTI_PRIVENR1_PRIV17_Pos            (17U)
8666 #define EXTI_PRIVENR1_PRIV17_Msk            (0x1UL << EXTI_PRIVENR1_PRIV17_Pos)     /*!< 0x00020000 */
8667 #define EXTI_PRIVENR1_PRIV17                EXTI_PRIVENR1_PRIV17_Msk                /*!< Privilege enable on line 17 */
8668 #define EXTI_PRIVENR1_PRIV18_Pos            (18U)
8669 #define EXTI_PRIVENR1_PRIV18_Msk            (0x1UL << EXTI_PRIVENR1_PRIV18_Pos)     /*!< 0x00040000 */
8670 #define EXTI_PRIVENR1_PRIV18                EXTI_PRIVENR1_PRIV18_Msk                /*!< Privilege enable on line 18 */
8671 #define EXTI_PRIVENR1_PRIV19_Pos            (19U)
8672 #define EXTI_PRIVENR1_PRIV19_Msk            (0x1UL << EXTI_PRIVENR1_PRIV19_Pos)     /*!< 0x00080000 */
8673 #define EXTI_PRIVENR1_PRIV19                EXTI_PRIVENR1_PRIV19_Msk                /*!< Privilege enable on line 19 */
8674 #define EXTI_PRIVENR1_PRIV20_Pos            (20U)
8675 #define EXTI_PRIVENR1_PRIV20_Msk            (0x1UL << EXTI_PRIVENR1_PRIV20_Pos)     /*!< 0x00100000 */
8676 #define EXTI_PRIVENR1_PRIV20                EXTI_PRIVENR1_PRIV20_Msk                /*!< Privilege enable on line 20 */
8677 #define EXTI_PRIVENR1_PRIV21_Pos            (21U)
8678 #define EXTI_PRIVENR1_PRIV21_Msk            (0x1UL << EXTI_PRIVENR1_PRIV21_Pos)     /*!< 0x00200000 */
8679 #define EXTI_PRIVENR1_PRIV21                EXTI_PRIVENR1_PRIV21_Msk                /*!< Privilege enable on line 21 */
8680 #define EXTI_PRIVENR1_PRIV22_Pos            (22U)
8681 #define EXTI_PRIVENR1_PRIV22_Msk            (0x1UL << EXTI_PRIVENR1_PRIV22_Pos)     /*!< 0x00400000 */
8682 #define EXTI_PRIVENR1_PRIV22                EXTI_PRIVENR1_PRIV22_Msk                /*!< Privilege enable on line 22 */
8683 #define EXTI_PRIVENR1_PRIV23_Pos            (23U)
8684 #define EXTI_PRIVENR1_PRIV23_Msk            (0x1UL << EXTI_PRIVENR1_PRIV23_Pos)     /*!< 0x00800000 */
8685 #define EXTI_PRIVENR1_PRIV23                EXTI_PRIVENR1_PRIV23_Msk                /*!< Privilege enable on line 23 */
8686 #define EXTI_PRIVENR1_PRIV24_Pos            (24U)
8687 #define EXTI_PRIVENR1_PRIV24_Msk            (0x1UL << EXTI_PRIVENR1_PRIV24_Pos)     /*!< 0x01000000 */
8688 #define EXTI_PRIVENR1_PRIV24                EXTI_PRIVENR1_PRIV24_Msk                /*!< Privilege enable on line 24 */
8689 #define EXTI_PRIVENR1_PRIV25_Pos            (25U)
8690 #define EXTI_PRIVENR1_PRIV25_Msk            (0x1UL << EXTI_PRIVENR1_PRIV25_Pos)      /*!< 0x02000000 */
8691 #define EXTI_PRIVENR1_PRIV25                EXTI_PRIVENR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
8692 #define EXTI_PRIVENR1_PRIV26_Pos            (26U)
8693 #define EXTI_PRIVENR1_PRIV26_Msk            (0x1UL << EXTI_PRIVENR1_PRIV26_Pos)      /*!< 0x04000000 */
8694 #define EXTI_PRIVENR1_PRIV26                EXTI_PRIVENR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
8695 #define EXTI_PRIVENR1_PRIV27_Pos            (27U)
8696 #define EXTI_PRIVENR1_PRIV27_Msk            (0x1UL << EXTI_PRIVENR1_PRIV27_Pos)      /*!< 0x08000000 */
8697 #define EXTI_PRIVENR1_PRIV27                EXTI_PRIVENR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
8698 #define EXTI_PRIVENR1_PRIV28_Pos            (28U)
8699 #define EXTI_PRIVENR1_PRIV28_Msk            (0x1UL << EXTI_PRIVENR1_PRIV28_Pos)      /*!< 0x10000000 */
8700 #define EXTI_PRIVENR1_PRIV28                EXTI_PRIVENR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
8701 #define EXTI_PRIVENR1_PRIV29_Pos            (29U)
8702 #define EXTI_PRIVENR1_PRIV29_Msk            (0x1UL << EXTI_PRIVENR1_PRIV29_Pos)      /*!< 0x20000000 */
8703 #define EXTI_PRIVENR1_PRIV29                EXTI_PRIVENR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
8704 #define EXTI_PRIVENR1_PRIV30_Pos            (30U)
8705 #define EXTI_PRIVENR1_PRIV30_Msk            (0x1UL << EXTI_PRIVENR1_PRIV30_Pos)      /*!< 0x40000000 */
8706 #define EXTI_PRIVENR1_PRIV30                EXTI_PRIVENR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
8707 #define EXTI_PRIVENR1_PRIV31_Pos            (31U)
8708 #define EXTI_PRIVENR1_PRIV31_Msk            (0x1UL << EXTI_PRIVENR1_PRIV31_Pos)      /*!< 0x80000000 */
8709 #define EXTI_PRIVENR1_PRIV31                EXTI_PRIVENR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
8710 
8711 /******************  Bit definition for EXTI_RTSR2 register  *******************/
8712 #define EXTI_RTSR2_TR_Pos                   (14U)
8713 #define EXTI_RTSR2_TR_Msk                   (0x244UL << EXTI_RTSR2_TR_Pos)              /*!< 0x00244000 */
8714 #define EXTI_RTSR2_TR                       EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
8715 #define EXTI_RTSR2_TR46_Pos                 (14U)
8716 #define EXTI_RTSR2_TR46_Msk                 (0x1UL << EXTI_RTSR2_TR46_Pos)              /*!< 0x00004000 */
8717 #define EXTI_RTSR2_TR46                     EXTI_RTSR2_TR46_Msk                         /*!< Rising trigger event configuration bit of line 46 */
8718 #define EXTI_RTSR2_TR50_Pos                 (18U)
8719 #define EXTI_RTSR2_TR50_Msk                 (0x1UL << EXTI_RTSR2_TR50_Pos)              /*!< 0x00040000 */
8720 #define EXTI_RTSR2_TR50                     EXTI_RTSR2_TR50_Msk                         /*!< Rising trigger event configuration bit of line 50 */
8721 #define EXTI_RTSR2_TR53_Pos                 (21U)
8722 #define EXTI_RTSR2_TR53_Msk                 (0x1UL << EXTI_RTSR2_TR53_Pos)              /*!< 0x00200000 */
8723 #define EXTI_RTSR2_TR53                     EXTI_RTSR2_TR53_Msk                         /*!< Rising trigger event configuration bit of line 53 */
8724 
8725 /******************  Bit definition for EXTI_FTSR2 register  *******************/
8726 #define EXTI_FTSR2_TR_Pos                   (14U)
8727 #define EXTI_FTSR2_TR_Msk                   (0x244 << EXTI_FTSR2_TR_Pos)                /*!< 0x00244000 */
8728 #define EXTI_FTSR2_TR                       EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
8729 #define EXTI_FTSR2_TR46_Pos                 (14U)
8730 #define EXTI_FTSR2_TR46_Msk                 (0x1UL << EXTI_FTSR2_TR46_Pos)              /*!< 0x00004000 */
8731 #define EXTI_FTSR2_TR46                     EXTI_FTSR2_TR46_Msk                         /*!< Falling trigger event configuration bit of line 46 */
8732 #define EXTI_FTSR2_TR50_Pos                 (18U)
8733 #define EXTI_FTSR2_TR50_Msk                 (0x1UL << EXTI_FTSR2_TR50_Pos)              /*!< 0x00040000 */
8734 #define EXTI_FTSR2_TR50                     EXTI_FTSR2_TR50_Msk                         /*!< Falling trigger event configuration bit of line 50 */
8735 #define EXTI_FTSR2_TR53_Pos                 (21U)
8736 #define EXTI_FTSR2_TR53_Msk                 (0x1UL << EXTI_FTSR2_TR53_Pos)              /*!< 0x00200000 */
8737 #define EXTI_FTSR2_TR53                     EXTI_FTSR2_TR53_Msk                         /*!< Falling trigger event configuration bit of line 53 */
8738 
8739 /******************  Bit definition for EXTI_SWIER2 register  ******************/
8740 #define EXTI_SWIER2_SWIER46_Pos            (14U)
8741 #define EXTI_SWIER2_SWIER46_Msk            (0x1UL << EXTI_SWIER2_SWIER46_Pos)          /*!< 0x00004000 */
8742 #define EXTI_SWIER2_SWIER46                EXTI_SWIER2_SWIER46_Msk                     /*!< Software Interrupt on line 46 */
8743 #define EXTI_SWIER2_SWIER50_Pos            (18U)
8744 #define EXTI_SWIER2_SWIER50_Msk            (0x1UL << EXTI_SWIER2_SWIER50_Pos)          /*!< 0x00040000 */
8745 #define EXTI_SWIER2_SWIER50                EXTI_SWIER2_SWIER50_Msk                     /*!< Software Interrupt on line 50 */
8746 #define EXTI_SWIER2_SWIER53_Pos            (21U)
8747 #define EXTI_SWIER2_SWIER53_Msk            (0x1UL << EXTI_SWIER2_SWIER53_Pos)          /*!< 0x00200000 */
8748 #define EXTI_SWIER2_SWIER53                EXTI_SWIER2_SWIER53_Msk                     /*!< Software Interrupt on line 53 */
8749 
8750 /******************  Bit definition for EXTI_RPR2 register  *******************/
8751 #define EXTI_RPR2_RPIF_Pos                   (14U)
8752 #define EXTI_RPR2_RPIF_Msk                   (0x244UL << EXTI_RPR2_RPIF_Pos)        /*!< 0x00244000 */
8753 #define EXTI_RPR2_RPIF                       EXTI_RPR2_RPIF_Msk                     /*!< Rising pending edge configuration bits */
8754 #define EXTI_RPR2_RPIF46_Pos                 (14U)
8755 #define EXTI_RPR2_RPIF46_Msk                 (0x1UL << EXTI_RPR2_RPIF46_Pos)        /*!< 0x00004000 */
8756 #define EXTI_RPR2_RPIF46                     EXTI_RPR2_RPIF46_Msk                   /*!< Rising pending edge configuration bit of line 46 */
8757 #define EXTI_RPR2_RPIF50_Pos                 (18U)
8758 #define EXTI_RPR2_RPIF50_Msk                 (0x1UL << EXTI_RPR2_RPIF50_Pos)        /*!< 0x00040000 */
8759 #define EXTI_RPR2_RPIF50                     EXTI_RPR2_RPIF50_Msk                   /*!< Rising pending edge configuration bit of line 50 */
8760 #define EXTI_RPR2_RPIF53_Pos                 (21U)
8761 #define EXTI_RPR2_RPIF53_Msk                 (0x1UL << EXTI_RPR2_RPIF53_Pos)        /*!< 0x00200000 */
8762 #define EXTI_RPR2_RPIF53                     EXTI_RPR2_RPIF53_Msk                   /*!< Rising pending edge configuration bit of line 53 */
8763 
8764 /******************  Bit definition for EXTI_FPR2 register  *******************/
8765 #define EXTI_FPR2_FPIF_Pos                   (14U)
8766 #define EXTI_FPR2_FPIF_Msk                   (0x244UL << EXTI_FPR2_FPIF_Pos)        /*!< 0x00244000 */
8767 #define EXTI_FPR2_FPIF                       EXTI_FPR2_FPIF_Msk                     /*!< Rising falling edge configuration bits */
8768 #define EXTI_FPR2_FPIF46_Pos                 (14U)
8769 #define EXTI_FPR2_FPIF46_Msk                 (0x1UL << EXTI_FPR2_FPIF46_Pos)        /*!< 0x00004000 */
8770 #define EXTI_FPR2_FPIF46                     EXTI_FPR2_FPIF46_Msk                   /*!< Rising falling edge configuration bit of line 46 */
8771 #define EXTI_FPR2_FPIF50_Pos                 (18U)
8772 #define EXTI_FPR2_FPIF50_Msk                 (0x1UL << EXTI_FPR2_FPIF50_Pos)        /*!< 0x00040000 */
8773 #define EXTI_FPR2_FPIF50                     EXTI_FPR2_FPIF50_Msk                   /*!< Rising falling edge configuration bit of line 50 */
8774 #define EXTI_FPR2_FPIF53_Pos                 (21U)
8775 #define EXTI_FPR2_FPIF53_Msk                 (0x1UL << EXTI_FPR2_FPIF53_Pos)        /*!< 0x00200000 */
8776 #define EXTI_FPR2_FPIF53                     EXTI_FPR2_FPIF53_Msk                   /*!< Rising falling edge configuration bit of line 53 */
8777 
8778 /*******************  Bit definition for EXTI_SECENR2 register  ******************/
8779 #define EXTI_SECENR2_SEC32_Pos              (0U)
8780 #define EXTI_SECENR2_SEC32_Msk              (0x1UL << EXTI_SECENR2_SEC32_Pos)       /*!< 0x00000001 */
8781 #define EXTI_SECENR2_SEC32                  EXTI_SECENR2_SEC32_Msk                  /*!< Security enable on line 32 */
8782 #define EXTI_SECENR2_SEC33_Pos              (1U)
8783 #define EXTI_SECENR2_SEC33_Msk              (0x1UL << EXTI_SECENR2_SEC33_Pos)       /*!< 0x00000002 */
8784 #define EXTI_SECENR2_SEC33                  EXTI_SECENR2_SEC33_Msk                  /*!< Security enable on line 33 */
8785 #define EXTI_SECENR2_SEC34_Pos              (2U)
8786 #define EXTI_SECENR2_SEC34_Msk              (0x1UL << EXTI_SECENR2_SEC34_Pos)       /*!< 0x00000004 */
8787 #define EXTI_SECENR2_SEC34                  EXTI_SECENR2_SEC34_Msk                  /*!< Security enable on line 2 */
8788 #define EXTI_SECENR2_SEC35_Pos              (3U)
8789 #define EXTI_SECENR2_SEC35_Msk              (0x1UL << EXTI_SECENR2_SEC35_Pos)       /*!< 0x00000008 */
8790 #define EXTI_SECENR2_SEC35                  EXTI_SECENR2_SEC35_Msk                  /*!< Security enable on line 3 */
8791 #define EXTI_SECENR2_SEC36_Pos              (4U)
8792 #define EXTI_SECENR2_SEC36_Msk              (0x1UL << EXTI_SECENR2_SEC36_Pos)       /*!< 0x00000010 */
8793 #define EXTI_SECENR2_SEC36                  EXTI_SECENR2_SEC36_Msk                  /*!< Security enable on line 4 */
8794 #define EXTI_SECENR2_SEC37_Pos              (5U)
8795 #define EXTI_SECENR2_SEC37_Msk              (0x1UL << EXTI_SECENR2_SEC37_Pos)       /*!< 0x00000020 */
8796 #define EXTI_SECENR2_SEC37                  EXTI_SECENR2_SEC37_Msk                  /*!< Security enable on line 5 */
8797 #define EXTI_SECENR2_SEC38_Pos              (6U)
8798 #define EXTI_SECENR2_SEC38_Msk              (0x1UL << EXTI_SECENR2_SEC38_Pos)       /*!< 0x00000040 */
8799 #define EXTI_SECENR2_SEC38                  EXTI_SECENR2_SEC38_Msk                  /*!< Security enable on line 6 */
8800 #define EXTI_SECENR2_SEC39_Pos              (7U)
8801 #define EXTI_SECENR2_SEC39_Msk              (0x1UL << EXTI_SECENR2_SEC39_Pos)       /*!< 0x00000080 */
8802 #define EXTI_SECENR2_SEC39                  EXTI_SECENR2_SEC39_Msk                  /*!< Security enable on line 7 */
8803 #define EXTI_SECENR2_SEC40_Pos              (8U)
8804 #define EXTI_SECENR2_SEC40_Msk              (0x1UL << EXTI_SECENR2_SEC40_Pos)       /*!< 0x00000100 */
8805 #define EXTI_SECENR2_SEC40                  EXTI_SECENR2_SEC40_Msk                  /*!< Security enable on line 8 */
8806 #define EXTI_SECENR2_SEC41_Pos              (9U)
8807 #define EXTI_SECENR2_SEC41_Msk              (0x1UL << EXTI_SECENR2_SEC41_Pos)       /*!< 0x00000200 */
8808 #define EXTI_SECENR2_SEC41                  EXTI_SECENR2_SEC41_Msk                  /*!< Security enable on line 9 */
8809 #define EXTI_SECENR2_SEC42_Pos             (10U)
8810 #define EXTI_SECENR2_SEC42_Msk             (0x1UL << EXTI_SECENR2_SEC42_Pos)        /*!< 0x00000400 */
8811 #define EXTI_SECENR2_SEC42                 EXTI_SECENR2_SEC42_Msk                   /*!< Security enable on line 10 */
8812 #define EXTI_SECENR2_SEC43_Pos             (11U)
8813 #define EXTI_SECENR2_SEC43_Msk             (0x1UL << EXTI_SECENR2_SEC43_Pos)        /*!< 0x00000800 */
8814 #define EXTI_SECENR2_SEC43                 EXTI_SECENR2_SEC43_Msk                   /*!< Security enable on line 11 */
8815 #define EXTI_SECENR2_SEC44_Pos             (12U)
8816 #define EXTI_SECENR2_SEC44_Msk             (0x1UL << EXTI_SECENR2_SEC44_Pos)        /*!< 0x00001000 */
8817 #define EXTI_SECENR2_SEC44                 EXTI_SECENR2_SEC44_Msk                   /*!< Security enable on line 12 */
8818 #define EXTI_SECENR2_SEC45_Pos             (13U)
8819 #define EXTI_SECENR2_SEC45_Msk             (0x1UL << EXTI_SECENR2_SEC45_Pos)        /*!< 0x00002000 */
8820 #define EXTI_SECENR2_SEC45                 EXTI_SECENR2_SEC45_Msk                   /*!< Security enable on line 13 */
8821 #define EXTI_SECENR2_SEC46_Pos             (14U)
8822 #define EXTI_SECENR2_SEC46_Msk             (0x1UL << EXTI_SECENR2_SEC46_Pos)        /*!< 0x00004000 */
8823 #define EXTI_SECENR2_SEC46                 EXTI_SECENR2_SEC46_Msk                   /*!< Security enable on line 14 */
8824 #define EXTI_SECENR2_SEC47_Pos             (15U)
8825 #define EXTI_SECENR2_SEC47_Msk             (0x1UL << EXTI_SECENR2_SEC47_Pos)        /*!< 0x00008000 */
8826 #define EXTI_SECENR2_SEC47                 EXTI_SECENR2_SEC47_Msk                   /*!< Security enable on line 15 */
8827 #define EXTI_SECENR2_SEC48_Pos             (16U)
8828 #define EXTI_SECENR2_SEC48_Msk             (0x1UL << EXTI_SECENR2_SEC48_Pos)        /*!< 0x00010000 */
8829 #define EXTI_SECENR2_SEC48                 EXTI_SECENR2_SEC48_Msk                   /*!< Security enable on line 16 */
8830 #define EXTI_SECENR2_SEC49_Pos             (17U)
8831 #define EXTI_SECENR2_SEC49_Msk             (0x1UL << EXTI_SECENR2_SEC49_Pos)        /*!< 0x00020000 */
8832 #define EXTI_SECENR2_SEC49                 EXTI_SECENR2_SEC49_Msk                   /*!< Security enable on line 17 */
8833 #define EXTI_SECENR2_SEC50_Pos             (18U)
8834 #define EXTI_SECENR2_SEC50_Msk             (0x1UL << EXTI_SECENR2_SEC50_Pos)        /*!< 0x00040000 */
8835 #define EXTI_SECENR2_SEC50                 EXTI_SECENR2_SEC50_Msk                   /*!< Security enable on line 18 */
8836 #define EXTI_SECENR2_SEC51_Pos             (19U)
8837 #define EXTI_SECENR2_SEC51_Msk             (0x1UL << EXTI_SECENR2_SEC51_Pos)        /*!< 0x00080000 */
8838 #define EXTI_SECENR2_SEC51                 EXTI_SECENR2_SEC51_Msk                   /*!< Security enable on line 19 */
8839 #define EXTI_SECENR2_SEC52_Pos             (20U)
8840 #define EXTI_SECENR2_SEC52_Msk             (0x1UL << EXTI_SECENR2_SEC52_Pos)        /*!< 0x00100000 */
8841 #define EXTI_SECENR2_SEC52                 EXTI_SECENR2_SEC52_Msk                   /*!< Security enable on line 20 */
8842 #define EXTI_SECENR2_SEC53_Pos             (21U)
8843 #define EXTI_SECENR2_SEC53_Msk             (0x1UL << EXTI_SECENR2_SEC53_Pos)        /*!< 0x00200000 */
8844 #define EXTI_SECENR2_SEC53                 EXTI_SECENR2_SEC53_Msk                   /*!< Security enable on line 21 */
8845 #define EXTI_SECENR2_SEC54_Pos             (22U)
8846 #define EXTI_SECENR2_SEC54_Msk             (0x1UL << EXTI_SECENR2_SEC54_Pos)        /*!< 0x00400000 */
8847 #define EXTI_SECENR2_SEC54                 EXTI_SECENR2_SEC54_Msk                   /*!< Security enable on line 22 */
8848 #define EXTI_SECENR2_SEC55_Pos             (23U)
8849 #define EXTI_SECENR2_SEC55_Msk             (0x1UL << EXTI_SECENR2_SEC55_Pos)        /*!< 0x00800000 */
8850 #define EXTI_SECENR2_SEC55                 EXTI_SECENR2_SEC55_Msk                   /*!< Security enable on line 23 */
8851 #define EXTI_SECENR2_SEC56_Pos             (24U)
8852 #define EXTI_SECENR2_SEC56_Msk             (0x1UL << EXTI_SECENR2_SEC56_Pos)        /*!< 0x01000000 */
8853 #define EXTI_SECENR2_SEC56                 EXTI_SECENR2_SEC56_Msk                   /*!< Security enable on line 24 */
8854 #define EXTI_SECENR2_SEC57_Pos             (25U)
8855 #define EXTI_SECENR2_SEC57_Msk             (0x1UL << EXTI_SECENR2_SEC57_Pos)        /*!< 0x02000000 */
8856 #define EXTI_SECENR2_SEC57                 EXTI_SECENR2_SEC57_Msk                   /*!< Security enable on line 25 */
8857 
8858 /*******************  Bit definition for EXTI_PRIVENR2 register  ******************/
8859 #define EXTI_PRIVENR2_PRIV32_Pos              (0U)
8860 #define EXTI_PRIVENR2_PRIV32_Msk              (0x1UL << EXTI_PRIVENR2_PRIV32_Pos)       /*!< 0x00000001 */
8861 #define EXTI_PRIVENR2_PRIV32                  EXTI_PRIVENR2_PRIV32_Msk                  /*!< Security enable on line 32 */
8862 #define EXTI_PRIVENR2_PRIV33_Pos              (1U)
8863 #define EXTI_PRIVENR2_PRIV33_Msk              (0x1UL << EXTI_PRIVENR2_PRIV33_Pos)       /*!< 0x00000002 */
8864 #define EXTI_PRIVENR2_PRIV33                  EXTI_PRIVENR2_PRIV33_Msk                  /*!< Security enable on line 33 */
8865 #define EXTI_PRIVENR2_PRIV34_Pos              (2U)
8866 #define EXTI_PRIVENR2_PRIV34_Msk              (0x1UL << EXTI_PRIVENR2_PRIV34_Pos)       /*!< 0x00000004 */
8867 #define EXTI_PRIVENR2_PRIV34                  EXTI_PRIVENR2_PRIV34_Msk                  /*!< Security enable on line 2 */
8868 #define EXTI_PRIVENR2_PRIV35_Pos              (3U)
8869 #define EXTI_PRIVENR2_PRIV35_Msk              (0x1UL << EXTI_PRIVENR2_PRIV35_Pos)       /*!< 0x00000008 */
8870 #define EXTI_PRIVENR2_PRIV35                  EXTI_PRIVENR2_PRIV35_Msk                  /*!< Security enable on line 3 */
8871 #define EXTI_PRIVENR2_PRIV36_Pos              (4U)
8872 #define EXTI_PRIVENR2_PRIV36_Msk              (0x1UL << EXTI_PRIVENR2_PRIV36_Pos)       /*!< 0x00000010 */
8873 #define EXTI_PRIVENR2_PRIV36                  EXTI_PRIVENR2_PRIV36_Msk                  /*!< Security enable on line 4 */
8874 #define EXTI_PRIVENR2_PRIV37_Pos              (5U)
8875 #define EXTI_PRIVENR2_PRIV37_Msk              (0x1UL << EXTI_PRIVENR2_PRIV37_Pos)       /*!< 0x00000020 */
8876 #define EXTI_PRIVENR2_PRIV37                  EXTI_PRIVENR2_PRIV37_Msk                  /*!< Security enable on line 5 */
8877 #define EXTI_PRIVENR2_PRIV38_Pos              (6U)
8878 #define EXTI_PRIVENR2_PRIV38_Msk              (0x1UL << EXTI_PRIVENR2_PRIV38_Pos)       /*!< 0x00000040 */
8879 #define EXTI_PRIVENR2_PRIV38                  EXTI_PRIVENR2_PRIV38_Msk                  /*!< Security enable on line 6 */
8880 #define EXTI_PRIVENR2_PRIV39_Pos              (7U)
8881 #define EXTI_PRIVENR2_PRIV39_Msk              (0x1UL << EXTI_PRIVENR2_PRIV39_Pos)       /*!< 0x00000080 */
8882 #define EXTI_PRIVENR2_PRIV39                  EXTI_PRIVENR2_PRIV39_Msk                  /*!< Security enable on line 7 */
8883 #define EXTI_PRIVENR2_PRIV40_Pos              (8U)
8884 #define EXTI_PRIVENR2_PRIV40_Msk              (0x1UL << EXTI_PRIVENR2_PRIV40_Pos)       /*!< 0x00000100 */
8885 #define EXTI_PRIVENR2_PRIV40                  EXTI_PRIVENR2_PRIV40_Msk                  /*!< Security enable on line 8 */
8886 #define EXTI_PRIVENR2_PRIV41_Pos              (9U)
8887 #define EXTI_PRIVENR2_PRIV41_Msk              (0x1UL << EXTI_PRIVENR2_PRIV41_Pos)       /*!< 0x00000200 */
8888 #define EXTI_PRIVENR2_PRIV41                  EXTI_PRIVENR2_PRIV41_Msk                  /*!< Security enable on line 9 */
8889 #define EXTI_PRIVENR2_PRIV42_Pos             (10U)
8890 #define EXTI_PRIVENR2_PRIV42_Msk             (0x1UL << EXTI_PRIVENR2_PRIV42_Pos)        /*!< 0x00000400 */
8891 #define EXTI_PRIVENR2_PRIV42                 EXTI_PRIVENR2_PRIV42_Msk                   /*!< Security enable on line 10 */
8892 #define EXTI_PRIVENR2_PRIV43_Pos             (11U)
8893 #define EXTI_PRIVENR2_PRIV43_Msk             (0x1UL << EXTI_PRIVENR2_PRIV43_Pos)        /*!< 0x00000800 */
8894 #define EXTI_PRIVENR2_PRIV43                 EXTI_PRIVENR2_PRIV43_Msk                   /*!< Security enable on line 11 */
8895 #define EXTI_PRIVENR2_PRIV44_Pos             (12U)
8896 #define EXTI_PRIVENR2_PRIV44_Msk             (0x1UL << EXTI_PRIVENR2_PRIV44_Pos)        /*!< 0x00001000 */
8897 #define EXTI_PRIVENR2_PRIV44                 EXTI_PRIVENR2_PRIV44_Msk                   /*!< Security enable on line 12 */
8898 #define EXTI_PRIVENR2_PRIV45_Pos             (13U)
8899 #define EXTI_PRIVENR2_PRIV45_Msk             (0x1UL << EXTI_PRIVENR2_PRIV45_Pos)        /*!< 0x00002000 */
8900 #define EXTI_PRIVENR2_PRIV45                 EXTI_PRIVENR2_PRIV45_Msk                   /*!< Security enable on line 13 */
8901 #define EXTI_PRIVENR2_PRIV46_Pos             (14U)
8902 #define EXTI_PRIVENR2_PRIV46_Msk             (0x1UL << EXTI_PRIVENR2_PRIV46_Pos)        /*!< 0x00004000 */
8903 #define EXTI_PRIVENR2_PRIV46                 EXTI_PRIVENR2_PRIV46_Msk                   /*!< Security enable on line 14 */
8904 #define EXTI_PRIVENR2_PRIV47_Pos             (15U)
8905 #define EXTI_PRIVENR2_PRIV47_Msk             (0x1UL << EXTI_PRIVENR2_PRIV47_Pos)        /*!< 0x00008000 */
8906 #define EXTI_PRIVENR2_PRIV47                 EXTI_PRIVENR2_PRIV47_Msk                   /*!< Security enable on line 15 */
8907 #define EXTI_PRIVENR2_PRIV48_Pos             (16U)
8908 #define EXTI_PRIVENR2_PRIV48_Msk             (0x1UL << EXTI_PRIVENR2_PRIV48_Pos)        /*!< 0x00010000 */
8909 #define EXTI_PRIVENR2_PRIV48                 EXTI_PRIVENR2_PRIV48_Msk                   /*!< Security enable on line 16 */
8910 #define EXTI_PRIVENR2_PRIV49_Pos             (17U)
8911 #define EXTI_PRIVENR2_PRIV49_Msk             (0x1UL << EXTI_PRIVENR2_PRIV49_Pos)        /*!< 0x00020000 */
8912 #define EXTI_PRIVENR2_PRIV49                 EXTI_PRIVENR2_PRIV49_Msk                   /*!< Security enable on line 17 */
8913 #define EXTI_PRIVENR2_PRIV50_Pos             (18U)
8914 #define EXTI_PRIVENR2_PRIV50_Msk             (0x1UL << EXTI_PRIVENR2_PRIV50_Pos)        /*!< 0x00040000 */
8915 #define EXTI_PRIVENR2_PRIV50                 EXTI_PRIVENR2_PRIV50_Msk                   /*!< Security enable on line 18 */
8916 #define EXTI_PRIVENR2_PRIV51_Pos             (19U)
8917 #define EXTI_PRIVENR2_PRIV51_Msk             (0x1UL << EXTI_PRIVENR2_PRIV51_Pos)        /*!< 0x00080000 */
8918 #define EXTI_PRIVENR2_PRIV51                 EXTI_PRIVENR2_PRIV51_Msk                   /*!< Security enable on line 19 */
8919 #define EXTI_PRIVENR2_PRIV52_Pos             (20U)
8920 #define EXTI_PRIVENR2_PRIV52_Msk             (0x1UL << EXTI_PRIVENR2_PRIV52_Pos)        /*!< 0x00100000 */
8921 #define EXTI_PRIVENR2_PRIV52                 EXTI_PRIVENR2_PRIV52_Msk                   /*!< Security enable on line 20 */
8922 #define EXTI_PRIVENR2_PRIV53_Pos             (21U)
8923 #define EXTI_PRIVENR2_PRIV53_Msk             (0x1UL << EXTI_PRIVENR2_PRIV53_Pos)        /*!< 0x00200000 */
8924 #define EXTI_PRIVENR2_PRIV53                 EXTI_PRIVENR2_PRIV53_Msk                   /*!< Security enable on line 21 */
8925 #define EXTI_PRIVENR2_PRIV54_Pos             (22U)
8926 #define EXTI_PRIVENR2_PRIV54_Msk             (0x1UL << EXTI_PRIVENR2_PRIV54_Pos)        /*!< 0x00400000 */
8927 #define EXTI_PRIVENR2_PRIV54                 EXTI_PRIVENR2_PRIV54_Msk                   /*!< Security enable on line 22 */
8928 #define EXTI_PRIVENR2_PRIV55_Pos             (23U)
8929 #define EXTI_PRIVENR2_PRIV55_Msk             (0x1UL << EXTI_PRIVENR2_PRIV55_Pos)        /*!< 0x00800000 */
8930 #define EXTI_PRIVENR2_PRIV55                 EXTI_PRIVENR2_PRIV55_Msk                   /*!< Security enable on line 23 */
8931 #define EXTI_PRIVENR2_PRIV56_Pos             (24U)
8932 #define EXTI_PRIVENR2_PRIV56_Msk             (0x1UL << EXTI_PRIVENR2_PRIV56_Pos)        /*!< 0x01000000 */
8933 #define EXTI_PRIVENR2_PRIV56                 EXTI_PRIVENR2_PRIV56_Msk                   /*!< Security enable on line 24 */
8934 #define EXTI_PRIVENR2_PRIV57_Pos             (25U)
8935 #define EXTI_PRIVENR2_PRIV57_Msk             (0x1UL << EXTI_PRIVENR2_PRIV57_Pos)        /*!< 0x02000000 */
8936 #define EXTI_PRIVENR2_PRIV57                 EXTI_PRIVENR2_PRIV57_Msk                   /*!< Security enable on line 25 */
8937 
8938 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
8939 #define EXTI_EXTICR1_EXTI0_Pos              (0U)
8940 #define EXTI_EXTICR1_EXTI0_Msk              (0xFUL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000007 */
8941 #define EXTI_EXTICR1_EXTI0                  EXTI_EXTICR1_EXTI0_Msk                  /*!< EXTI 0 configuration */
8942 #define EXTI_EXTICR1_EXTI0_0                (0x1UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000001 */
8943 #define EXTI_EXTICR1_EXTI0_1                (0x2UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000002 */
8944 #define EXTI_EXTICR1_EXTI0_2                (0x4UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000004 */
8945 #define EXTI_EXTICR1_EXTI0_3                (0x8UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000008 */
8946 #define EXTI_EXTICR1_EXTI1_Pos              (8U)
8947 #define EXTI_EXTICR1_EXTI1_Msk              (0xFUL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000700 */
8948 #define EXTI_EXTICR1_EXTI1                  EXTI_EXTICR1_EXTI1_Msk                  /*!< EXTI 1 configuration */
8949 #define EXTI_EXTICR1_EXTI1_0                (0x1UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000100 */
8950 #define EXTI_EXTICR1_EXTI1_1                (0x2UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000200 */
8951 #define EXTI_EXTICR1_EXTI1_2                (0x4UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000400 */
8952 #define EXTI_EXTICR1_EXTI1_3                (0x8UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000800 */
8953 #define EXTI_EXTICR1_EXTI2_Pos              (16U)
8954 #define EXTI_EXTICR1_EXTI2_Msk              (0xFUL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00070000 */
8955 #define EXTI_EXTICR1_EXTI2                  EXTI_EXTICR1_EXTI2_Msk                  /*!< EXTI 2 configuration */
8956 #define EXTI_EXTICR1_EXTI2_0                (0x1UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00010000 */
8957 #define EXTI_EXTICR1_EXTI2_1                (0x2UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00020000 */
8958 #define EXTI_EXTICR1_EXTI2_2                (0x4UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00040000 */
8959 #define EXTI_EXTICR1_EXTI2_3                (0x8UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00080000 */
8960 #define EXTI_EXTICR1_EXTI3_Pos              (24U)
8961 #define EXTI_EXTICR1_EXTI3_Msk              (0xFUL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x07000000 */
8962 #define EXTI_EXTICR1_EXTI3                  EXTI_EXTICR1_EXTI3_Msk                  /*!< EXTI 3 configuration */
8963 #define EXTI_EXTICR1_EXTI3_0                (0x1UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x01000000 */
8964 #define EXTI_EXTICR1_EXTI3_1                (0x2UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x02000000 */
8965 #define EXTI_EXTICR1_EXTI3_2                (0x4UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x04000000 */
8966 #define EXTI_EXTICR1_EXTI3_3                (0x8UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x08000000 */
8967 
8968 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
8969 #define EXTI_EXTICR2_EXTI4_Pos              (0U)
8970 #define EXTI_EXTICR2_EXTI4_Msk              (0xFUL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000007 */
8971 #define EXTI_EXTICR2_EXTI4                  EXTI_EXTICR2_EXTI4_Msk                  /*!< EXTI 4 configuration */
8972 #define EXTI_EXTICR2_EXTI4_0                (0x1UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000001 */
8973 #define EXTI_EXTICR2_EXTI4_1                (0x2UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000002 */
8974 #define EXTI_EXTICR2_EXTI4_2                (0x4UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000004 */
8975 #define EXTI_EXTICR2_EXTI4_3                (0x8UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000008 */
8976 #define EXTI_EXTICR2_EXTI5_Pos              (8U)
8977 #define EXTI_EXTICR2_EXTI5_Msk              (0xFUL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000700 */
8978 #define EXTI_EXTICR2_EXTI5                  EXTI_EXTICR2_EXTI5_Msk                  /*!< EXTI 5 configuration */
8979 #define EXTI_EXTICR2_EXTI5_0                (0x1UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000100 */
8980 #define EXTI_EXTICR2_EXTI5_1                (0x2UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000200 */
8981 #define EXTI_EXTICR2_EXTI5_2                (0x4UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000400 */
8982 #define EXTI_EXTICR2_EXTI5_3                (0x8UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000800 */
8983 #define EXTI_EXTICR2_EXTI6_Pos              (16U)
8984 #define EXTI_EXTICR2_EXTI6_Msk              (0xFUL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00070000 */
8985 #define EXTI_EXTICR2_EXTI6                  EXTI_EXTICR2_EXTI6_Msk                  /*!< EXTI 6 configuration */
8986 #define EXTI_EXTICR2_EXTI6_0                (0x1UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00010000 */
8987 #define EXTI_EXTICR2_EXTI6_1                (0x2UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00020000 */
8988 #define EXTI_EXTICR2_EXTI6_2                (0x4UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00040000 */
8989 #define EXTI_EXTICR2_EXTI6_3                (0x8UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00080000 */
8990 #define EXTI_EXTICR2_EXTI7_Pos              (24U)
8991 #define EXTI_EXTICR2_EXTI7_Msk              (0xFUL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x07000000 */
8992 #define EXTI_EXTICR2_EXTI7                  EXTI_EXTICR2_EXTI7_Msk                  /*!< EXTI 7 configuration */
8993 #define EXTI_EXTICR2_EXTI7_0                (0x1UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x01000000 */
8994 #define EXTI_EXTICR2_EXTI7_1                (0x2UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x02000000 */
8995 #define EXTI_EXTICR2_EXTI7_2                (0x4UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x04000000 */
8996 #define EXTI_EXTICR2_EXTI7_3                (0x8UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x08000000 */
8997 
8998 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
8999 #define EXTI_EXTICR3_EXTI8_Pos              (0U)
9000 #define EXTI_EXTICR3_EXTI8_Msk              (0xFUL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000007 */
9001 #define EXTI_EXTICR3_EXTI8                  EXTI_EXTICR3_EXTI8_Msk                  /*!< EXTI 8 configuration */
9002 #define EXTI_EXTICR3_EXTI8_0                (0x1UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000001 */
9003 #define EXTI_EXTICR3_EXTI8_1                (0x2UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000002 */
9004 #define EXTI_EXTICR3_EXTI8_2                (0x4UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000004 */
9005 #define EXTI_EXTICR3_EXTI8_3                (0x8UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000008 */
9006 #define EXTI_EXTICR3_EXTI9_Pos              (8U)
9007 #define EXTI_EXTICR3_EXTI9_Msk              (0xFUL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000700 */
9008 #define EXTI_EXTICR3_EXTI9                  EXTI_EXTICR3_EXTI9_Msk                  /*!< EXTI 9 configuration */
9009 #define EXTI_EXTICR3_EXTI9_0                (0x1UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000100 */
9010 #define EXTI_EXTICR3_EXTI9_1                (0x2UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000200 */
9011 #define EXTI_EXTICR3_EXTI9_2                (0x4UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000400 */
9012 #define EXTI_EXTICR3_EXTI9_3                (0x8UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000800 */
9013 #define EXTI_EXTICR3_EXTI10_Pos             (16U)
9014 #define EXTI_EXTICR3_EXTI10_Msk             (0xFUL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00070000 */
9015 #define EXTI_EXTICR3_EXTI10                 EXTI_EXTICR3_EXTI10_Msk                 /*!< EXTI 10 configuration */
9016 #define EXTI_EXTICR3_EXTI10_0               (0x1UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00010000 */
9017 #define EXTI_EXTICR3_EXTI10_1               (0x2UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00020000 */
9018 #define EXTI_EXTICR3_EXTI10_2               (0x4UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00040000 */
9019 #define EXTI_EXTICR3_EXTI10_3               (0x8UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00080000 */
9020 #define EXTI_EXTICR3_EXTI11_Pos             (24U)
9021 #define EXTI_EXTICR3_EXTI11_Msk             (0xFUL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x07000000 */
9022 #define EXTI_EXTICR3_EXTI11                 EXTI_EXTICR3_EXTI11_Msk                 /*!< EXTI 11 configuration */
9023 #define EXTI_EXTICR3_EXTI11_0               (0x1UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x01000000 */
9024 #define EXTI_EXTICR3_EXTI11_1               (0x2UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x02000000 */
9025 #define EXTI_EXTICR3_EXTI11_2               (0x4UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x04000000 */
9026 #define EXTI_EXTICR3_EXTI11_3               (0x8UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x08000000 */
9027 
9028 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
9029 #define EXTI_EXTICR4_EXTI12_Pos             (0U)
9030 #define EXTI_EXTICR4_EXTI12_Msk             (0xFUL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000007 */
9031 #define EXTI_EXTICR4_EXTI12                 EXTI_EXTICR4_EXTI12_Msk                 /*!< EXTI 12 configuration */
9032 #define EXTI_EXTICR4_EXTI12_0               (0x1UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000001 */
9033 #define EXTI_EXTICR4_EXTI12_1               (0x2UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000002 */
9034 #define EXTI_EXTICR4_EXTI12_2               (0x4UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000004 */
9035 #define EXTI_EXTICR4_EXTI12_3               (0x8UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000008 */
9036 #define EXTI_EXTICR4_EXTI13_Pos             (8U)
9037 #define EXTI_EXTICR4_EXTI13_Msk             (0xFUL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000700 */
9038 #define EXTI_EXTICR4_EXTI13                 EXTI_EXTICR4_EXTI13_Msk                 /*!< EXTI 13 configuration */
9039 #define EXTI_EXTICR4_EXTI13_0               (0x1UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000100 */
9040 #define EXTI_EXTICR4_EXTI13_1               (0x2UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000200 */
9041 #define EXTI_EXTICR4_EXTI13_2               (0x4UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000400 */
9042 #define EXTI_EXTICR4_EXTI13_3               (0x8UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000800 */
9043 #define EXTI_EXTICR4_EXTI14_Pos             (16U)
9044 #define EXTI_EXTICR4_EXTI14_Msk             (0xFUL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00070000 */
9045 #define EXTI_EXTICR4_EXTI14                 EXTI_EXTICR4_EXTI14_Msk                 /*!< EXTI 14 configuration */
9046 #define EXTI_EXTICR4_EXTI14_0               (0x1UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00010000 */
9047 #define EXTI_EXTICR4_EXTI14_1               (0x2UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00020000 */
9048 #define EXTI_EXTICR4_EXTI14_2               (0x4UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00040000 */
9049 #define EXTI_EXTICR4_EXTI14_3               (0x8UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00080000 */
9050 #define EXTI_EXTICR4_EXTI15_Pos             (24U)
9051 #define EXTI_EXTICR4_EXTI15_Msk             (0xFUL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x07000000 */
9052 #define EXTI_EXTICR4_EXTI15                 EXTI_EXTICR4_EXTI15_Msk                 /*!< EXTI 15 configuration */
9053 #define EXTI_EXTICR4_EXTI15_0               (0x1UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x01000000 */
9054 #define EXTI_EXTICR4_EXTI15_1               (0x2UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x02000000 */
9055 #define EXTI_EXTICR4_EXTI15_2               (0x4UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x04000000 */
9056 #define EXTI_EXTICR4_EXTI15_3               (0x8UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x08000000 */
9057 
9058 /*******************  Bit definition for EXTI_LOCKR register  ******************/
9059 #define EXTI_LOCKR_LOCK_Pos                 (0U)
9060 #define EXTI_LOCKR_LOCK_Msk                 (0x1UL << EXTI_LOCKR_LOCK_Pos)          /*!< 0x00000001 */
9061 #define EXTI_LOCKR_LOCK                     EXTI_LOCKR_LOCK_Msk                     /*!< Lock Mask  */
9062 
9063 /*******************  Bit definition for EXTI_IMR1 register  ******************/
9064 #define EXTI_IMR1_IM_Pos                    (0U)
9065 #define EXTI_IMR1_IM_Msk                    (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)      /*!< 0xFFFFFFFF */
9066 #define EXTI_IMR1_IM                        EXTI_IMR1_IM_Msk                        /*!< Interrupt Mask */
9067 #define EXTI_IMR1_IM0_Pos                   (0U)
9068 #define EXTI_IMR1_IM0_Msk                   (0x1UL << EXTI_IMR1_IM0_Pos)            /*!< 0x00000001 */
9069 #define EXTI_IMR1_IM0                       EXTI_IMR1_IM0_Msk                       /*!< Interrupt Mask on line 0 */
9070 #define EXTI_IMR1_IM1_Pos                   (1U)
9071 #define EXTI_IMR1_IM1_Msk                   (0x1UL << EXTI_IMR1_IM1_Pos)            /*!< 0x00000002 */
9072 #define EXTI_IMR1_IM1                       EXTI_IMR1_IM1_Msk                       /*!< Interrupt Mask on line 1 */
9073 #define EXTI_IMR1_IM2_Pos                   (2U)
9074 #define EXTI_IMR1_IM2_Msk                   (0x1UL << EXTI_IMR1_IM2_Pos)            /*!< 0x00000004 */
9075 #define EXTI_IMR1_IM2                       EXTI_IMR1_IM2_Msk                       /*!< Interrupt Mask on line 2 */
9076 #define EXTI_IMR1_IM3_Pos                   (3U)
9077 #define EXTI_IMR1_IM3_Msk                   (0x1UL << EXTI_IMR1_IM3_Pos)            /*!< 0x00000008 */
9078 #define EXTI_IMR1_IM3                       EXTI_IMR1_IM3_Msk                       /*!< Interrupt Mask on line 3 */
9079 #define EXTI_IMR1_IM4_Pos                   (4U)
9080 #define EXTI_IMR1_IM4_Msk                   (0x1UL << EXTI_IMR1_IM4_Pos)            /*!< 0x00000010 */
9081 #define EXTI_IMR1_IM4                       EXTI_IMR1_IM4_Msk                       /*!< Interrupt Mask on line 4 */
9082 #define EXTI_IMR1_IM5_Pos                   (5U)
9083 #define EXTI_IMR1_IM5_Msk                   (0x1UL << EXTI_IMR1_IM5_Pos)            /*!< 0x00000020 */
9084 #define EXTI_IMR1_IM5                       EXTI_IMR1_IM5_Msk                       /*!< Interrupt Mask on line 5 */
9085 #define EXTI_IMR1_IM6_Pos                   (6U)
9086 #define EXTI_IMR1_IM6_Msk                   (0x1UL << EXTI_IMR1_IM6_Pos)            /*!< 0x00000040 */
9087 #define EXTI_IMR1_IM6                       EXTI_IMR1_IM6_Msk                       /*!< Interrupt Mask on line 6 */
9088 #define EXTI_IMR1_IM7_Pos                   (7U)
9089 #define EXTI_IMR1_IM7_Msk                   (0x1UL << EXTI_IMR1_IM7_Pos)            /*!< 0x00000080 */
9090 #define EXTI_IMR1_IM7                       EXTI_IMR1_IM7_Msk                       /*!< Interrupt Mask on line 7 */
9091 #define EXTI_IMR1_IM8_Pos                   (8U)
9092 #define EXTI_IMR1_IM8_Msk                   (0x1UL << EXTI_IMR1_IM8_Pos)            /*!< 0x00000100 */
9093 #define EXTI_IMR1_IM8                       EXTI_IMR1_IM8_Msk                       /*!< Interrupt Mask on line 8 */
9094 #define EXTI_IMR1_IM9_Pos                   (9U)
9095 #define EXTI_IMR1_IM9_Msk                   (0x1UL << EXTI_IMR1_IM9_Pos)            /*!< 0x00000200 */
9096 #define EXTI_IMR1_IM9                       EXTI_IMR1_IM9_Msk                       /*!< Interrupt Mask on line 9 */
9097 #define EXTI_IMR1_IM10_Pos                  (10U)
9098 #define EXTI_IMR1_IM10_Msk                  (0x1UL << EXTI_IMR1_IM10_Pos)           /*!< 0x00000400 */
9099 #define EXTI_IMR1_IM10                      EXTI_IMR1_IM10_Msk                      /*!< Interrupt Mask on line 10 */
9100 #define EXTI_IMR1_IM11_Pos                  (11U)
9101 #define EXTI_IMR1_IM11_Msk                  (0x1UL << EXTI_IMR1_IM11_Pos)           /*!< 0x00000800 */
9102 #define EXTI_IMR1_IM11                      EXTI_IMR1_IM11_Msk                      /*!< Interrupt Mask on line 11 */
9103 #define EXTI_IMR1_IM12_Pos                  (12U)
9104 #define EXTI_IMR1_IM12_Msk                  (0x1UL << EXTI_IMR1_IM12_Pos)           /*!< 0x00001000 */
9105 #define EXTI_IMR1_IM12                      EXTI_IMR1_IM12_Msk                      /*!< Interrupt Mask on line 12 */
9106 #define EXTI_IMR1_IM13_Pos                  (13U)
9107 #define EXTI_IMR1_IM13_Msk                  (0x1UL << EXTI_IMR1_IM13_Pos)           /*!< 0x00002000 */
9108 #define EXTI_IMR1_IM13                      EXTI_IMR1_IM13_Msk                      /*!< Interrupt Mask on line 13 */
9109 #define EXTI_IMR1_IM14_Pos                  (14U)
9110 #define EXTI_IMR1_IM14_Msk                  (0x1UL << EXTI_IMR1_IM14_Pos)           /*!< 0x00004000 */
9111 #define EXTI_IMR1_IM14                      EXTI_IMR1_IM14_Msk                      /*!< Interrupt Mask on line 14 */
9112 #define EXTI_IMR1_IM15_Pos                  (15U)
9113 #define EXTI_IMR1_IM15_Msk                  (0x1UL << EXTI_IMR1_IM15_Pos)           /*!< 0x00008000 */
9114 #define EXTI_IMR1_IM15                      EXTI_IMR1_IM15_Msk                      /*!< Interrupt Mask on line 15 */
9115 #define EXTI_IMR1_IM16_Pos                  (16U)
9116 #define EXTI_IMR1_IM16_Msk                  (0x1UL << EXTI_IMR1_IM16_Pos)           /*!< 0x00010000 */
9117 #define EXTI_IMR1_IM16                      EXTI_IMR1_IM16_Msk                      /*!< Interrupt Mask on line 16 */
9118 #define EXTI_IMR1_IM17_Pos                  (17U)
9119 #define EXTI_IMR1_IM17_Msk                  (0x1UL << EXTI_IMR1_IM17_Pos)           /*!< 0x00020000 */
9120 #define EXTI_IMR1_IM17                      EXTI_IMR1_IM17_Msk                      /*!< Interrupt Mask on line 17 */
9121 #define EXTI_IMR1_IM18_Pos                  (18U)
9122 #define EXTI_IMR1_IM18_Msk                  (0x1UL << EXTI_IMR1_IM18_Pos)           /*!< 0x00040000 */
9123 #define EXTI_IMR1_IM18                      EXTI_IMR1_IM18_Msk                      /*!< Interrupt Mask on line 18 */
9124 #define EXTI_IMR1_IM19_Pos                  (19U)
9125 #define EXTI_IMR1_IM19_Msk                  (0x1UL << EXTI_IMR1_IM19_Pos)           /*!< 0x00080000 */
9126 #define EXTI_IMR1_IM19                      EXTI_IMR1_IM19_Msk                      /*!< Interrupt Mask on line 19 */
9127 #define EXTI_IMR1_IM20_Pos                  (20U)
9128 #define EXTI_IMR1_IM20_Msk                  (0x1UL << EXTI_IMR1_IM20_Pos)           /*!< 0x00100000 */
9129 #define EXTI_IMR1_IM20                      EXTI_IMR1_IM20_Msk                      /*!< Interrupt Mask on line 20 */
9130 #define EXTI_IMR1_IM21_Pos                  (21U)
9131 #define EXTI_IMR1_IM21_Msk                  (0x1UL << EXTI_IMR1_IM21_Pos)           /*!< 0x00200000 */
9132 #define EXTI_IMR1_IM21                      EXTI_IMR1_IM21_Msk                      /*!< Interrupt Mask on line 21 */
9133 #define EXTI_IMR1_IM22_Pos                  (22U)
9134 #define EXTI_IMR1_IM22_Msk                  (0x1UL << EXTI_IMR1_IM22_Pos)           /*!< 0x00400000 */
9135 #define EXTI_IMR1_IM22                      EXTI_IMR1_IM22_Msk                      /*!< Interrupt Mask on line 22 */
9136 #define EXTI_IMR1_IM23_Pos                  (23U)
9137 #define EXTI_IMR1_IM23_Msk                  (0x1UL << EXTI_IMR1_IM23_Pos)           /*!< 0x00800000 */
9138 #define EXTI_IMR1_IM23                      EXTI_IMR1_IM23_Msk                      /*!< Interrupt Mask on line 23 */
9139 #define EXTI_IMR1_IM24_Pos                  (24U)
9140 #define EXTI_IMR1_IM24_Msk                  (0x1UL << EXTI_IMR1_IM24_Pos)           /*!< 0x01000000 */
9141 #define EXTI_IMR1_IM24                      EXTI_IMR1_IM24_Msk                      /*!< Interrupt Mask on line 24 */
9142 #define EXTI_IMR1_IM25_Pos                  (25U)
9143 #define EXTI_IMR1_IM25_Msk                  (0x1UL << EXTI_IMR1_IM25_Pos)           /*!< 0x02000000 */
9144 #define EXTI_IMR1_IM25                      EXTI_IMR1_IM25_Msk                      /*!< Interrupt Mask on line 25 */
9145 #define EXTI_IMR1_IM26_Pos                  (26U)
9146 #define EXTI_IMR1_IM26_Msk                  (0x1UL << EXTI_IMR1_IM26_Pos)           /*!< 0x04000000 */
9147 #define EXTI_IMR1_IM26                      EXTI_IMR1_IM26_Msk                      /*!< Interrupt Mask on line 26 */
9148 #define EXTI_IMR1_IM27_Pos                  (27U)
9149 #define EXTI_IMR1_IM27_Msk                  (0x1UL << EXTI_IMR1_IM27_Pos)           /*!< 0x08000000 */
9150 #define EXTI_IMR1_IM27                      EXTI_IMR1_IM27_Msk                      /*!< Interrupt Mask on line 27 */
9151 #define EXTI_IMR1_IM28_Pos                  (28U)
9152 #define EXTI_IMR1_IM28_Msk                  (0x1UL << EXTI_IMR1_IM28_Pos)           /*!< 0x10000000 */
9153 #define EXTI_IMR1_IM28                      EXTI_IMR1_IM28_Msk                      /*!< Interrupt Mask on line 28 */
9154 #define EXTI_IMR1_IM29_Pos                  (29U)
9155 #define EXTI_IMR1_IM29_Msk                  (0x1UL << EXTI_IMR1_IM29_Pos)           /*!< 0x20000000 */
9156 #define EXTI_IMR1_IM29                      EXTI_IMR1_IM29_Msk                      /*!< Interrupt Mask on line 29 */
9157 #define EXTI_IMR1_IM30_Pos                  (30U)
9158 #define EXTI_IMR1_IM30_Msk                  (0x1UL << EXTI_IMR1_IM30_Pos)           /*!< 0x40000000 */
9159 #define EXTI_IMR1_IM30                      EXTI_IMR1_IM30_Msk                      /*!< Interrupt Mask on line 30 */
9160 #define EXTI_IMR1_IM31_Pos                  (31U)
9161 #define EXTI_IMR1_IM31_Msk                  (0x1UL << EXTI_IMR1_IM31_Pos)           /*!< 0x80000000 */
9162 #define EXTI_IMR1_IM31                      EXTI_IMR1_IM31_Msk                      /*!< Interrupt Mask on line 31 */
9163 
9164 /*******************  Bit definition for EXTI_EMR1 register  ******************/
9165 #define EXTI_EMR1_EM_Pos                    (0U)
9166 #define EXTI_EMR1_EM_Msk                    (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)      /*!< 0xFFFFFFFF */
9167 #define EXTI_EMR1_EM                        EXTI_EMR1_EM_Msk                        /*!< Event Mask */
9168 #define EXTI_EMR1_EM0_Pos                   (0U)
9169 #define EXTI_EMR1_EM0_Msk                   (0x1UL << EXTI_EMR1_EM0_Pos)            /*!< 0x00000001 */
9170 #define EXTI_EMR1_EM0                       EXTI_EMR1_EM0_Msk                       /*!< Event Mask on line 0 */
9171 #define EXTI_EMR1_EM1_Pos                   (1U)
9172 #define EXTI_EMR1_EM1_Msk                   (0x1UL << EXTI_EMR1_EM1_Pos)            /*!< 0x00000002 */
9173 #define EXTI_EMR1_EM1                       EXTI_EMR1_EM1_Msk                       /*!< Event Mask on line 1 */
9174 #define EXTI_EMR1_EM2_Pos                   (2U)
9175 #define EXTI_EMR1_EM2_Msk                   (0x1UL << EXTI_EMR1_EM2_Pos)            /*!< 0x00000004 */
9176 #define EXTI_EMR1_EM2                       EXTI_EMR1_EM2_Msk                       /*!< Event Mask on line 2 */
9177 #define EXTI_EMR1_EM3_Pos                   (3U)
9178 #define EXTI_EMR1_EM3_Msk                   (0x1UL << EXTI_EMR1_EM3_Pos)            /*!< 0x00000008 */
9179 #define EXTI_EMR1_EM3                       EXTI_EMR1_EM3_Msk                       /*!< Event Mask on line 3 */
9180 #define EXTI_EMR1_EM4_Pos                   (4U)
9181 #define EXTI_EMR1_EM4_Msk                   (0x1UL << EXTI_EMR1_EM4_Pos)            /*!< 0x00000010 */
9182 #define EXTI_EMR1_EM4                       EXTI_EMR1_EM4_Msk                       /*!< Event Mask on line 4 */
9183 #define EXTI_EMR1_EM5_Pos                   (5U)
9184 #define EXTI_EMR1_EM5_Msk                   (0x1UL << EXTI_EMR1_EM5_Pos)            /*!< 0x00000020 */
9185 #define EXTI_EMR1_EM5                       EXTI_EMR1_EM5_Msk                       /*!< Event Mask on line 5 */
9186 #define EXTI_EMR1_EM6_Pos                   (6U)
9187 #define EXTI_EMR1_EM6_Msk                   (0x1UL << EXTI_EMR1_EM6_Pos)            /*!< 0x00000040 */
9188 #define EXTI_EMR1_EM6                       EXTI_EMR1_EM6_Msk                       /*!< Event Mask on line 6 */
9189 #define EXTI_EMR1_EM7_Pos                   (7U)
9190 #define EXTI_EMR1_EM7_Msk                   (0x1UL << EXTI_EMR1_EM7_Pos)            /*!< 0x00000080 */
9191 #define EXTI_EMR1_EM7                       EXTI_EMR1_EM7_Msk                       /*!< Event Mask on line 7 */
9192 #define EXTI_EMR1_EM8_Pos                   (8U)
9193 #define EXTI_EMR1_EM8_Msk                   (0x1UL << EXTI_EMR1_EM8_Pos)            /*!< 0x00000100 */
9194 #define EXTI_EMR1_EM8                       EXTI_EMR1_EM8_Msk                       /*!< Event Mask on line 8 */
9195 #define EXTI_EMR1_EM9_Pos                   (9U)
9196 #define EXTI_EMR1_EM9_Msk                   (0x1UL << EXTI_EMR1_EM9_Pos)            /*!< 0x00000200 */
9197 #define EXTI_EMR1_EM9                       EXTI_EMR1_EM9_Msk                       /*!< Event Mask on line 9 */
9198 #define EXTI_EMR1_EM10_Pos                  (10U)
9199 #define EXTI_EMR1_EM10_Msk                  (0x1UL << EXTI_EMR1_EM10_Pos)           /*!< 0x00000400 */
9200 #define EXTI_EMR1_EM10                      EXTI_EMR1_EM10_Msk                      /*!< Event Mask on line 10 */
9201 #define EXTI_EMR1_EM11_Pos                  (11U)
9202 #define EXTI_EMR1_EM11_Msk                  (0x1UL << EXTI_EMR1_EM11_Pos)           /*!< 0x00000800 */
9203 #define EXTI_EMR1_EM11                      EXTI_EMR1_EM11_Msk                      /*!< Event Mask on line 11 */
9204 #define EXTI_EMR1_EM12_Pos                  (12U)
9205 #define EXTI_EMR1_EM12_Msk                  (0x1UL << EXTI_EMR1_EM12_Pos)           /*!< 0x00001000 */
9206 #define EXTI_EMR1_EM12                      EXTI_EMR1_EM12_Msk                      /*!< Event Mask on line 12 */
9207 #define EXTI_EMR1_EM13_Pos                  (13U)
9208 #define EXTI_EMR1_EM13_Msk                  (0x1UL << EXTI_EMR1_EM13_Pos)           /*!< 0x00002000 */
9209 #define EXTI_EMR1_EM13                      EXTI_EMR1_EM13_Msk                      /*!< Event Mask on line 13 */
9210 #define EXTI_EMR1_EM14_Pos                  (14U)
9211 #define EXTI_EMR1_EM14_Msk                  (0x1UL << EXTI_EMR1_EM14_Pos)           /*!< 0x00004000 */
9212 #define EXTI_EMR1_EM14                      EXTI_EMR1_EM14_Msk                      /*!< Event Mask on line 14 */
9213 #define EXTI_EMR1_EM15_Pos                  (15U)
9214 #define EXTI_EMR1_EM15_Msk                  (0x1UL << EXTI_EMR1_EM15_Pos)           /*!< 0x00008000 */
9215 #define EXTI_EMR1_EM15                      EXTI_EMR1_EM15_Msk                      /*!< Event Mask on line 15 */
9216 #define EXTI_EMR1_EM16_Pos                  (16U)
9217 #define EXTI_EMR1_EM16_Msk                  (0x1UL << EXTI_EMR1_EM16_Pos)           /*!< 0x00010000 */
9218 #define EXTI_EMR1_EM16                      EXTI_EMR1_EM16_Msk                      /*!< Event Mask on line 16 */
9219 #define EXTI_EMR1_EM17_Pos                  (17U)
9220 #define EXTI_EMR1_EM17_Msk                  (0x1UL << EXTI_EMR1_EM17_Pos)           /*!< 0x00020000 */
9221 #define EXTI_EMR1_EM17                      EXTI_EMR1_EM17_Msk                      /*!< Event Mask on line 17 */
9222 #define EXTI_EMR1_EM18_Pos                  (18U)
9223 #define EXTI_EMR1_EM18_Msk                  (0x1UL << EXTI_EMR1_EM18_Pos)           /*!< 0x00040000 */
9224 #define EXTI_EMR1_EM18                      EXTI_EMR1_EM18_Msk                      /*!< Event Mask on line 18 */
9225 #define EXTI_EMR1_EM19_Pos                  (19U)
9226 #define EXTI_EMR1_EM19_Msk                  (0x1UL << EXTI_EMR1_EM19_Pos)           /*!< 0x00080000 */
9227 #define EXTI_EMR1_EM19                      EXTI_EMR1_EM19_Msk                      /*!< Event Mask on line 19 */
9228 #define EXTI_EMR1_EM20_Pos                  (20U)
9229 #define EXTI_EMR1_EM20_Msk                  (0x1UL << EXTI_EMR1_EM20_Pos)           /*!< 0x00100000 */
9230 #define EXTI_EMR1_EM20                      EXTI_EMR1_EM20_Msk                      /*!< Event Mask on line 20 */
9231 #define EXTI_EMR1_EM21_Pos                  (21U)
9232 #define EXTI_EMR1_EM21_Msk                  (0x1UL << EXTI_EMR1_EM21_Pos)           /*!< 0x00200000 */
9233 #define EXTI_EMR1_EM21                      EXTI_EMR1_EM21_Msk                      /*!< Event Mask on line 21 */
9234 #define EXTI_EMR1_EM22_Pos                  (22U)
9235 #define EXTI_EMR1_EM22_Msk                  (0x1UL << EXTI_EMR1_EM22_Pos)           /*!< 0x00400000 */
9236 #define EXTI_EMR1_EM22                      EXTI_EMR1_EM22_Msk                      /*!< Event Mask on line 22 */
9237 #define EXTI_EMR1_EM23_Pos                  (23U)
9238 #define EXTI_EMR1_EM23_Msk                  (0x1UL << EXTI_EMR1_EM23_Pos)           /*!< 0x00800000 */
9239 #define EXTI_EMR1_EM23                      EXTI_EMR1_EM23_Msk                      /*!< Event Mask on line 23 */
9240 #define EXTI_EMR1_EM24_Pos                  (24U)
9241 #define EXTI_EMR1_EM24_Msk                  (0x1UL << EXTI_EMR1_EM24_Pos)           /*!< 0x01000000 */
9242 #define EXTI_EMR1_EM24                      EXTI_EMR1_EM24_Msk                      /*!< Event Mask on line 24 */
9243 #define EXTI_EMR1_EM25_Pos                  (25U)
9244 #define EXTI_EMR1_EM25_Msk                  (0x1UL << EXTI_EMR1_EM25_Pos)           /*!< 0x02000000 */
9245 #define EXTI_EMR1_EM25                      EXTI_EMR1_EM25_Msk                      /*!< Event Mask on line 25 */
9246 #define EXTI_EMR1_EM26_Pos                  (26U)
9247 #define EXTI_EMR1_EM26_Msk                  (0x1UL << EXTI_EMR1_EM26_Pos)           /*!< 0x04000000 */
9248 #define EXTI_EMR1_EM26                      EXTI_EMR1_EM26_Msk                      /*!< Event Mask on line 26 */
9249 #define EXTI_EMR1_EM27_Pos                  (27U)
9250 #define EXTI_EMR1_EM27_Msk                  (0x1UL << EXTI_EMR1_EM27_Pos)           /*!< 0x08000000 */
9251 #define EXTI_EMR1_EM27                      EXTI_EMR1_EM27_Msk                      /*!< Event Mask on line 27 */
9252 #define EXTI_EMR1_EM28_Pos                  (28U)
9253 #define EXTI_EMR1_EM28_Msk                  (0x1UL << EXTI_EMR1_EM28_Pos)           /*!< 0x10000000 */
9254 #define EXTI_EMR1_EM28                      EXTI_EMR1_EM28_Msk                      /*!< Event Mask on line 28 */
9255 #define EXTI_EMR1_EM29_Pos                  (29U)
9256 #define EXTI_EMR1_EM29_Msk                  (0x1UL << EXTI_EMR1_EM29_Pos)           /*!< 0x20000000 */
9257 #define EXTI_EMR1_EM29                      EXTI_EMR1_EM29_Msk                      /*!< Event Mask on line 29 */
9258 #define EXTI_EMR1_EM30_Pos                  (30U)
9259 #define EXTI_EMR1_EM30_Msk                  (0x1UL << EXTI_EMR1_EM30_Pos)           /*!< 0x40000000 */
9260 #define EXTI_EMR1_EM30                      EXTI_EMR1_EM30_Msk                      /*!< Event Mask on line 30 */
9261 #define EXTI_EMR1_EM31_Pos                  (31U)
9262 #define EXTI_EMR1_EM31_Msk                  (0x1UL << EXTI_EMR1_EM31_Pos)           /*!< 0x80000000 */
9263 #define EXTI_EMR1_EM31                      EXTI_EMR1_EM31_Msk                      /*!< Event Mask on line 31 */
9264 
9265 /*******************  Bit definition for EXTI_IMR2 register  *******************/
9266 #define EXTI_IMR2_IM_Pos                    (0U)
9267 #define EXTI_IMR2_IM_Msk                    (0x03FFFFFFUL << EXTI_IMR2_IM_Pos)      /*!< 0x03FFFFFF */
9268 #define EXTI_IMR2_IM                        EXTI_IMR2_IM_Msk                        /*!< Interrupt Mask */
9269 #define EXTI_IMR2_IM32_Pos                  (0U)
9270 #define EXTI_IMR2_IM32_Msk                  (0x1UL << EXTI_IMR2_IM32_Pos)           /*!< 0x00000001 */
9271 #define EXTI_IMR2_IM32                      EXTI_IMR2_IM32_Msk                      /*!< Interrupt Mask on line 32 */
9272 #define EXTI_IMR2_IM33_Pos                  (1U)
9273 #define EXTI_IMR2_IM33_Msk                  (0x1UL << EXTI_IMR2_IM33_Pos)           /*!< 0x00000002 */
9274 #define EXTI_IMR2_IM33                      EXTI_IMR2_IM33_Msk                      /*!< Interrupt Mask on line 33 */
9275 #define EXTI_IMR2_IM34_Pos                  (2U)
9276 #define EXTI_IMR2_IM34_Msk                  (0x1UL << EXTI_IMR2_IM34_Pos)           /*!< 0x00000004 */
9277 #define EXTI_IMR2_IM34                      EXTI_IMR2_IM34_Msk                      /*!< Interrupt Mask on line 34 */
9278 #define EXTI_IMR2_IM35_Pos                  (3U)
9279 #define EXTI_IMR2_IM35_Msk                  (0x1UL << EXTI_IMR2_IM35_Pos)           /*!< 0x00000008 */
9280 #define EXTI_IMR2_IM35                      EXTI_IMR2_IM35_Msk                      /*!< Interrupt Mask on line 35 */
9281 #define EXTI_IMR2_IM36_Pos                  (4U)
9282 #define EXTI_IMR2_IM36_Msk                  (0x1UL << EXTI_IMR2_IM36_Pos)           /*!< 0x00000010 */
9283 #define EXTI_IMR2_IM36                      EXTI_IMR2_IM36_Msk                      /*!< Interrupt Mask on line 36 */
9284 #define EXTI_IMR2_IM37_Pos                  (5U)
9285 #define EXTI_IMR2_IM37_Msk                  (0x1UL << EXTI_IMR2_IM37_Pos)           /*!< 0x00000020 */
9286 #define EXTI_IMR2_IM37                      EXTI_IMR2_IM37_Msk                      /*!< Interrupt Mask on line 37 */
9287 #define EXTI_IMR2_IM38_Pos                  (6U)
9288 #define EXTI_IMR2_IM38_Msk                  (0x1UL << EXTI_IMR2_IM38_Pos)           /*!< 0x00000040 */
9289 #define EXTI_IMR2_IM38                      EXTI_IMR2_IM38_Msk                      /*!< Interrupt Mask on line 38 */
9290 #define EXTI_IMR2_IM39_Pos                  (7U)
9291 #define EXTI_IMR2_IM39_Msk                  (0x1UL << EXTI_IMR2_IM39_Pos)           /*!< 0x00000080 */
9292 #define EXTI_IMR2_IM39                      EXTI_IMR2_IM39_Msk                      /*!< Interrupt Mask on line 39 */
9293 #define EXTI_IMR2_IM40_Pos                  (8U)
9294 #define EXTI_IMR2_IM40_Msk                  (0x1UL << EXTI_IMR2_IM40_Pos)           /*!< 0x00000100 */
9295 #define EXTI_IMR2_IM40                      EXTI_IMR2_IM40_Msk                      /*!< Interrupt Mask on line 40 */
9296 #define EXTI_IMR2_IM41_Pos                  (9U)
9297 #define EXTI_IMR2_IM41_Msk                  (0x1UL << EXTI_IMR2_IM41_Pos)           /*!< 0x00000200 */
9298 #define EXTI_IMR2_IM41                      EXTI_IMR2_IM41_Msk                      /*!< Interrupt Mask on line 41 */
9299 #define EXTI_IMR2_IM42_Pos                  (10U)
9300 #define EXTI_IMR2_IM42_Msk                  (0x1UL << EXTI_IMR2_IM42_Pos)           /*!< 0x00000400 */
9301 #define EXTI_IMR2_IM42                      EXTI_IMR2_IM42_Msk                      /*!< Interrupt Mask on line 42 */
9302 #define EXTI_IMR2_IM43_Pos                  (11U)
9303 #define EXTI_IMR2_IM43_Msk                  (0x1UL << EXTI_IMR2_IM43_Pos)           /*!< 0x00000800 */
9304 #define EXTI_IMR2_IM43                      EXTI_IMR2_IM43_Msk                      /*!< Interrupt Mask on line 43 */
9305 #define EXTI_IMR2_IM44_Pos                  (12U)
9306 #define EXTI_IMR2_IM44_Msk                  (0x1UL << EXTI_IMR2_IM44_Pos)           /*!< 0x00001000 */
9307 #define EXTI_IMR2_IM44                      EXTI_IMR2_IM44_Msk                      /*!< Interrupt Mask on line 44 */
9308 #define EXTI_IMR2_IM46_Pos                  (14U)
9309 #define EXTI_IMR2_IM46_Msk                  (0x1UL << EXTI_IMR2_IM46_Pos)           /*!< 0x00004000 */
9310 #define EXTI_IMR2_IM46                      EXTI_IMR2_IM46_Msk                      /*!< Interrupt Mask on line 46 */
9311 #define EXTI_IMR2_IM47_Pos                  (15U)
9312 #define EXTI_IMR2_IM47_Msk                  (0x1UL << EXTI_IMR2_IM47_Pos)           /*!< 0x00008000 */
9313 #define EXTI_IMR2_IM47                      EXTI_IMR2_IM47_Msk                      /*!< Interrupt Mask on line 47 */
9314 #define EXTI_IMR2_IM48_Pos                  (16U)
9315 #define EXTI_IMR2_IM48_Msk                  (0x1UL << EXTI_IMR2_IM48_Pos)           /*!< 0x00010000 */
9316 #define EXTI_IMR2_IM48                      EXTI_IMR2_IM48_Msk                      /*!< Interrupt Mask on line 48 */
9317 #define EXTI_IMR2_IM49_Pos                  (17U)
9318 #define EXTI_IMR2_IM49_Msk                  (0x1UL << EXTI_IMR2_IM49_Pos)           /*!< 0x00020000 */
9319 #define EXTI_IMR2_IM49                      EXTI_IMR2_IM49_Msk                      /*!< Interrupt Mask on line 49 */
9320 #define EXTI_IMR2_IM50_Pos                  (18U)
9321 #define EXTI_IMR2_IM50_Msk                  (0x1UL << EXTI_IMR2_IM50_Pos)           /*!< 0x00040000 */
9322 #define EXTI_IMR2_IM50                      EXTI_IMR2_IM50_Msk                      /*!< Interrupt Mask on line 50 */
9323 #define EXTI_IMR2_IM51_Pos                  (19U)
9324 #define EXTI_IMR2_IM51_Msk                  (0x1UL << EXTI_IMR2_IM51_Pos)           /*!< 0x00080000 */
9325 #define EXTI_IMR2_IM51                      EXTI_IMR2_IM51_Msk                      /*!< Interrupt Mask on line 51 */
9326 #define EXTI_IMR2_IM52_Pos                  (20U)
9327 #define EXTI_IMR2_IM52_Msk                  (0x1UL << EXTI_IMR2_IM52_Pos)           /*!< 0x00100000 */
9328 #define EXTI_IMR2_IM52                      EXTI_IMR2_IM52_Msk                      /*!< Interrupt Mask on line 52 */
9329 #define EXTI_IMR2_IM53_Pos                  (21U)
9330 #define EXTI_IMR2_IM53_Msk                  (0x1UL << EXTI_IMR2_IM53_Pos)           /*!< 0x00200000 */
9331 #define EXTI_IMR2_IM53                      EXTI_IMR2_IM53_Msk                      /*!< Interrupt Mask on line 53 */
9332 #define EXTI_IMR2_IM54_Pos                  (22U)
9333 #define EXTI_IMR2_IM54_Msk                  (0x1UL << EXTI_IMR2_IM54_Pos)           /*!< 0x00400000 */
9334 #define EXTI_IMR2_IM54                      EXTI_IMR2_IM54_Msk                      /*!< Interrupt Mask on line 54 */
9335 #define EXTI_IMR2_IM55_Pos                  (23U)
9336 #define EXTI_IMR2_IM55_Msk                  (0x1UL << EXTI_IMR2_IM55_Pos)           /*!< 0x00800000 */
9337 #define EXTI_IMR2_IM55                      EXTI_IMR2_IM55_Msk                      /*!< Interrupt Mask on line 55 */
9338 #define EXTI_IMR2_IM56_Pos                  (24U)
9339 #define EXTI_IMR2_IM56_Msk                  (0x1UL << EXTI_IMR2_IM56_Pos)           /*!< 0x01000000 */
9340 #define EXTI_IMR2_IM56                      EXTI_IMR2_IM56_Msk                      /*!< Interrupt Mask on line 56 */
9341 #define EXTI_IMR2_IM57_Pos                  (25U)
9342 #define EXTI_IMR2_IM57_Msk                  (0x1UL << EXTI_IMR2_IM57_Pos)           /*!< 0x02000000 */
9343 #define EXTI_IMR2_IM57                      EXTI_IMR2_IM57_Msk                      /*!< Interrupt Mask on line 57 */
9344 
9345 
9346 /*******************  Bit definition for EXTI_EMR2 register  *******************/
9347 #define EXTI_EMR2_EM_Pos                    (0U)
9348 #define EXTI_EMR2_EM_Msk                    (0x03FFFFFFUL << EXTI_EMR2_EM_Pos)      /*!< 0x03FFFFFF */
9349 #define EXTI_EMR2_EM                        EXTI_EMR2_EM_Msk                        /*!< Event Mask */
9350 #define EXTI_EMR2_EM32_Pos                  (0U)
9351 #define EXTI_EMR2_EM32_Msk                  (0x1UL << EXTI_EMR2_EM32_Pos)           /*!< 0x00000001 */
9352 #define EXTI_EMR2_EM32                      EXTI_EMR2_EM32_Msk                      /*!< Event Mask on line 32*/
9353 #define EXTI_EMR2_EM33_Pos                  (1U)
9354 #define EXTI_EMR2_EM33_Msk                  (0x1UL << EXTI_EMR2_EM33_Pos)           /*!< 0x00000002 */
9355 #define EXTI_EMR2_EM33                      EXTI_EMR2_EM33_Msk                      /*!< Event Mask on line 33*/
9356 #define EXTI_EMR2_EM34_Pos                  (2U)
9357 #define EXTI_EMR2_EM34_Msk                  (0x1UL << EXTI_EMR2_EM34_Pos)           /*!< 0x00000004 */
9358 #define EXTI_EMR2_EM34                      EXTI_EMR2_EM34_Msk                      /*!< Event Mask on line 34*/
9359 #define EXTI_EMR2_EM35_Pos                  (3U)
9360 #define EXTI_EMR2_EM35_Msk                  (0x1UL << EXTI_EMR2_EM35_Pos)           /*!< 0x00000008 */
9361 #define EXTI_EMR2_EM35                      EXTI_EMR2_EM35_Msk                      /*!< Event Mask on line 35*/
9362 #define EXTI_EMR2_EM36_Pos                  (4U)
9363 #define EXTI_EMR2_EM36_Msk                  (0x1UL << EXTI_EMR2_EM36_Pos)           /*!< 0x00000010 */
9364 #define EXTI_EMR2_EM36                      EXTI_EMR2_EM36_Msk                      /*!< Event Mask on line 36*/
9365 #define EXTI_EMR2_EM37_Pos                  (5U)
9366 #define EXTI_EMR2_EM37_Msk                  (0x1UL << EXTI_EMR2_EM37_Pos)           /*!< 0x00000020 */
9367 #define EXTI_EMR2_EM37                      EXTI_EMR2_EM37_Msk                      /*!< Event Mask on line 37*/
9368 #define EXTI_EMR2_EM38_Pos                  (6U)
9369 #define EXTI_EMR2_EM38_Msk                  (0x1UL << EXTI_EMR2_EM38_Pos)           /*!< 0x00000040 */
9370 #define EXTI_EMR2_EM38                      EXTI_EMR2_EM38_Msk                      /*!< Event Mask on line 38*/
9371 #define EXTI_EMR2_EM39_Pos                  (7U)
9372 #define EXTI_EMR2_EM39_Msk                  (0x1UL << EXTI_EMR2_EM39_Pos)           /*!< 0x00000080 */
9373 #define EXTI_EMR2_EM39                      EXTI_EMR2_EM39_Msk                      /*!< Event Mask on line 39*/
9374 #define EXTI_EMR2_EM40_Pos                  (8U)
9375 #define EXTI_EMR2_EM40_Msk                  (0x1UL << EXTI_EMR2_EM40_Pos)           /*!< 0x00000100 */
9376 #define EXTI_EMR2_EM40                      EXTI_EMR2_EM40_Msk                      /*!< Event Mask on line 40*/
9377 #define EXTI_EMR2_EM41_Pos                  (9U)
9378 #define EXTI_EMR2_EM41_Msk                  (0x1UL << EXTI_EMR2_EM41_Pos)           /*!< 0x00000200 */
9379 #define EXTI_EMR2_EM41                      EXTI_EMR2_EM41_Msk                      /*!< Event Mask on line 41*/
9380 #define EXTI_EMR2_EM42_Pos                  (10U)
9381 #define EXTI_EMR2_EM42_Msk                  (0x1UL << EXTI_EMR2_EM42_Pos)           /*!< 0x00000400 */
9382 #define EXTI_EMR2_EM42                      EXTI_EMR2_EM42_Msk                      /*!< Event Mask on line 42 */
9383 #define EXTI_EMR2_EM43_Pos                  (11U)
9384 #define EXTI_EMR2_EM43_Msk                  (0x1UL << EXTI_EMR2_EM43_Pos)           /*!< 0x00000800 */
9385 #define EXTI_EMR2_EM43                      EXTI_EMR2_EM43_Msk                      /*!< Event Mask on line 43 */
9386 #define EXTI_EMR2_EM44_Pos                  (12U)
9387 #define EXTI_EMR2_EM44_Msk                  (0x1UL << EXTI_EMR2_EM44_Pos)           /*!< 0x00001000 */
9388 #define EXTI_EMR2_EM44                      EXTI_EMR2_EM44_Msk                      /*!< Event Mask on line 44 */
9389 #define EXTI_EMR2_EM46_Pos                  (14U)
9390 #define EXTI_EMR2_EM46_Msk                  (0x1UL << EXTI_EMR2_EM46_Pos)           /*!< 0x00004000 */
9391 #define EXTI_EMR2_EM46                      EXTI_EMR2_EM46_Msk                      /*!< Event Mask on line 46 */
9392 #define EXTI_EMR2_EM47_Pos                  (15U)
9393 #define EXTI_EMR2_EM47_Msk                  (0x1UL << EXTI_EMR2_EM47_Pos)           /*!< 0x00008000 */
9394 #define EXTI_EMR2_EM47                      EXTI_EMR2_EM47_Msk                      /*!< Event Mask on line 47 */
9395 #define EXTI_EMR2_EM48_Pos                  (16U)
9396 #define EXTI_EMR2_EM48_Msk                  (0x1UL << EXTI_EMR2_EM48_Pos)           /*!< 0x00010000 */
9397 #define EXTI_EMR2_EM48                      EXTI_EMR2_EM48_Msk                      /*!< Event Mask on line 48 */
9398 #define EXTI_EMR2_EM49_Pos                  (17U)
9399 #define EXTI_EMR2_EM49_Msk                  (0x1UL << EXTI_EMR2_EM49_Pos)           /*!< 0x00020000 */
9400 #define EXTI_EMR2_EM49                      EXTI_EMR2_EM49_Msk                      /*!< Event Mask on line 49 */
9401 #define EXTI_EMR2_EM50_Pos                  (18U)
9402 #define EXTI_EMR2_EM50_Msk                  (0x1UL << EXTI_EMR2_EM50_Pos)           /*!< 0x00040000 */
9403 #define EXTI_EMR2_EM50                      EXTI_EMR2_EM50_Msk                      /*!< Event Mask on line 50 */
9404 #define EXTI_EMR2_EM51_Pos                  (19U)
9405 #define EXTI_EMR2_EM51_Msk                  (0x1UL << EXTI_EMR2_EM51_Pos)           /*!< 0x00080000 */
9406 #define EXTI_EMR2_EM51                      EXTI_EMR2_EM51_Msk                      /*!< Event Mask on line 51 */
9407 #define EXTI_EMR2_EM52_Pos                  (20U)
9408 #define EXTI_EMR2_EM52_Msk                  (0x1UL << EXTI_EMR2_EM52_Pos)           /*!< 0x00100000 */
9409 #define EXTI_EMR2_EM52                      EXTI_EMR2_EM52_Msk                      /*!< Event Mask on line 52 */
9410 #define EXTI_EMR2_EM53_Pos                  (21U)
9411 #define EXTI_EMR2_EM53_Msk                  (0x1UL << EXTI_EMR2_EM53_Pos)           /*!< 0x00200000 */
9412 #define EXTI_EMR2_EM53                      EXTI_EMR2_EM53_Msk                      /*!< Event Mask on line 53 */
9413 #define EXTI_EMR2_EM54_Pos                  (22U)
9414 #define EXTI_EMR2_EM54_Msk                  (0x1UL << EXTI_EMR2_EM54_Pos)           /*!< 0x00400000 */
9415 #define EXTI_EMR2_EM54                      EXTI_EMR2_EM54_Msk                      /*!< Event Mask on line 54 */
9416 #define EXTI_EMR2_EM55_Pos                  (23U)
9417 #define EXTI_EMR2_EM55_Msk                  (0x1UL << EXTI_EMR2_EM55_Pos)           /*!< 0x00800000 */
9418 #define EXTI_EMR2_EM55                      EXTI_EMR2_EM55_Msk                      /*!< Event Mask on line 55 */
9419 #define EXTI_EMR2_EM56_Pos                  (24U)
9420 #define EXTI_EMR2_EM56_Msk                  (0x1UL << EXTI_EMR2_EM56_Pos)           /*!< 0x01000000 */
9421 #define EXTI_EMR2_EM56                      EXTI_EMR2_EM56_Msk                      /*!< Event Mask on line 56 */
9422 #define EXTI_EMR2_EM57_Pos                  (25U)
9423 #define EXTI_EMR2_EM57_Msk                  (0x1UL << EXTI_EMR2_EM57_Pos)           /*!< 0x02000000 */
9424 #define EXTI_EMR2_EM57                      EXTI_EMR2_EM57_Msk                      /*!< Event Mask on line 57 */
9425 
9426 /******************************************************************************/
9427 /*                                                                            */
9428 /*                 Flexible Datarate Controller Area Network                  */
9429 /*                                                                            */
9430 /******************************************************************************/
9431 /*!<FDCAN control and status registers */
9432 /*****************  Bit definition for FDCAN_CREL register  *******************/
9433 #define FDCAN_CREL_DAY_Pos                  (0U)
9434 #define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
9435 #define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
9436 #define FDCAN_CREL_MON_Pos                  (8U)
9437 #define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
9438 #define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
9439 #define FDCAN_CREL_YEAR_Pos                 (16U)
9440 #define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
9441 #define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
9442 #define FDCAN_CREL_SUBSTEP_Pos              (20U)
9443 #define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
9444 #define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
9445 #define FDCAN_CREL_STEP_Pos                 (24U)
9446 #define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
9447 #define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
9448 #define FDCAN_CREL_REL_Pos                  (28U)
9449 #define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
9450 #define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */
9451 
9452 /*****************  Bit definition for FDCAN_ENDN register  *******************/
9453 #define FDCAN_ENDN_ETV_Pos                  (0U)
9454 #define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
9455 #define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                   */
9456 
9457 /*****************  Bit definition for FDCAN_DBTP register  *******************/
9458 #define FDCAN_DBTP_DSJW_Pos                 (0U)
9459 #define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
9460 #define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
9461 #define FDCAN_DBTP_DTSEG2_Pos               (4U)
9462 #define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
9463 #define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
9464 #define FDCAN_DBTP_DTSEG1_Pos               (8U)
9465 #define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
9466 #define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
9467 #define FDCAN_DBTP_DBRP_Pos                 (16U)
9468 #define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
9469 #define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
9470 #define FDCAN_DBTP_TDC_Pos                  (23U)
9471 #define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
9472 #define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */
9473 
9474 /*****************  Bit definition for FDCAN_TEST register  *******************/
9475 #define FDCAN_TEST_LBCK_Pos                 (4U)
9476 #define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
9477 #define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
9478 #define FDCAN_TEST_TX_Pos                   (5U)
9479 #define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
9480 #define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
9481 #define FDCAN_TEST_RX_Pos                   (7U)
9482 #define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
9483 #define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */
9484 
9485 /*****************  Bit definition for FDCAN_RWD register  ********************/
9486 #define FDCAN_RWD_WDC_Pos                   (0U)
9487 #define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
9488 #define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
9489 #define FDCAN_RWD_WDV_Pos                   (8U)
9490 #define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
9491 #define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */
9492 
9493 /*****************  Bit definition for FDCAN_CCCR register  ********************/
9494 #define FDCAN_CCCR_INIT_Pos                 (0U)
9495 #define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
9496 #define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
9497 #define FDCAN_CCCR_CCE_Pos                  (1U)
9498 #define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
9499 #define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
9500 #define FDCAN_CCCR_ASM_Pos                  (2U)
9501 #define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
9502 #define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
9503 #define FDCAN_CCCR_CSA_Pos                  (3U)
9504 #define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
9505 #define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
9506 #define FDCAN_CCCR_CSR_Pos                  (4U)
9507 #define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
9508 #define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
9509 #define FDCAN_CCCR_MON_Pos                  (5U)
9510 #define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
9511 #define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
9512 #define FDCAN_CCCR_DAR_Pos                  (6U)
9513 #define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
9514 #define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
9515 #define FDCAN_CCCR_TEST_Pos                 (7U)
9516 #define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
9517 #define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
9518 #define FDCAN_CCCR_FDOE_Pos                 (8U)
9519 #define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
9520 #define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
9521 #define FDCAN_CCCR_BRSE_Pos                 (9U)
9522 #define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
9523 #define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
9524 #define FDCAN_CCCR_PXHD_Pos                 (12U)
9525 #define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
9526 #define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
9527 #define FDCAN_CCCR_EFBI_Pos                 (13U)
9528 #define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
9529 #define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
9530 #define FDCAN_CCCR_TXP_Pos                  (14U)
9531 #define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
9532 #define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
9533 #define FDCAN_CCCR_NISO_Pos                 (15U)
9534 #define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
9535 #define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */
9536 
9537 /*****************  Bit definition for FDCAN_NBTP register  ******************* */
9538 #define FDCAN_NBTP_NTSEG2_Pos               (0U)
9539 #define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
9540 #define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
9541 #define FDCAN_NBTP_NTSEG1_Pos               (8U)
9542 #define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
9543 #define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
9544 #define FDCAN_NBTP_NBRP_Pos                 (16U)
9545 #define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
9546 #define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
9547 #define FDCAN_NBTP_NSJW_Pos                 (25U)
9548 #define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
9549 #define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */
9550 
9551 /*****************  Bit definition for FDCAN_TSCC register  ********************/
9552 #define FDCAN_TSCC_TSS_Pos                  (0U)
9553 #define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
9554 #define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
9555 #define FDCAN_TSCC_TCP_Pos                  (16U)
9556 #define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
9557 #define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */
9558 
9559 /*****************  Bit definition for FDCAN_TSCV register  ********************/
9560 #define FDCAN_TSCV_TSC_Pos                  (0U)
9561 #define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
9562 #define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */
9563 
9564 /*****************  Bit definition for FDCAN_TOCC register  ********************/
9565 #define FDCAN_TOCC_ETOC_Pos                 (0U)
9566 #define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
9567 #define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
9568 #define FDCAN_TOCC_TOS_Pos                  (1U)
9569 #define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
9570 #define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
9571 #define FDCAN_TOCC_TOP_Pos                  (16U)
9572 #define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
9573 #define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */
9574 
9575 /*****************  Bit definition for FDCAN_TOCV register  ******************* */
9576 #define FDCAN_TOCV_TOC_Pos                  (0U)
9577 #define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
9578 #define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */
9579 
9580 /*****************  Bit definition for FDCAN_ECR register  ******************** */
9581 #define FDCAN_ECR_TEC_Pos                   (0U)
9582 #define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
9583 #define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
9584 #define FDCAN_ECR_REC_Pos                   (8U)
9585 #define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
9586 #define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
9587 #define FDCAN_ECR_RP_Pos                    (15U)
9588 #define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
9589 #define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
9590 #define FDCAN_ECR_CEL_Pos                   (16U)
9591 #define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
9592 #define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */
9593 
9594 /*****************  Bit definition for FDCAN_PSR register  ******************** */
9595 #define FDCAN_PSR_LEC_Pos                   (0U)
9596 #define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
9597 #define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
9598 #define FDCAN_PSR_ACT_Pos                   (3U)
9599 #define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
9600 #define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
9601 #define FDCAN_PSR_EP_Pos                    (5U)
9602 #define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
9603 #define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
9604 #define FDCAN_PSR_EW_Pos                    (6U)
9605 #define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
9606 #define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
9607 #define FDCAN_PSR_BO_Pos                    (7U)
9608 #define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
9609 #define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
9610 #define FDCAN_PSR_DLEC_Pos                  (8U)
9611 #define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
9612 #define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
9613 #define FDCAN_PSR_RESI_Pos                  (11U)
9614 #define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
9615 #define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
9616 #define FDCAN_PSR_RBRS_Pos                  (12U)
9617 #define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
9618 #define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
9619 #define FDCAN_PSR_REDL_Pos                  (13U)
9620 #define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
9621 #define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
9622 #define FDCAN_PSR_PXE_Pos                   (14U)
9623 #define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
9624 #define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
9625 #define FDCAN_PSR_TDCV_Pos                  (16U)
9626 #define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
9627 #define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */
9628 
9629 /*****************  Bit definition for FDCAN_TDCR register  ******************* */
9630 #define FDCAN_TDCR_TDCF_Pos                 (0U)
9631 #define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
9632 #define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
9633 #define FDCAN_TDCR_TDCO_Pos                 (8U)
9634 #define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
9635 #define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */
9636 
9637 /*****************  Bit definition for FDCAN_IR register  ********************* */
9638 #define FDCAN_IR_RF0N_Pos                   (0U)
9639 #define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
9640 #define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
9641 #define FDCAN_IR_RF0F_Pos                   (1U)
9642 #define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
9643 #define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
9644 #define FDCAN_IR_RF0L_Pos                   (2U)
9645 #define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
9646 #define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
9647 #define FDCAN_IR_RF1N_Pos                   (3U)
9648 #define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
9649 #define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
9650 #define FDCAN_IR_RF1F_Pos                   (4U)
9651 #define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
9652 #define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
9653 #define FDCAN_IR_RF1L_Pos                   (5U)
9654 #define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
9655 #define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
9656 #define FDCAN_IR_HPM_Pos                    (6U)
9657 #define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
9658 #define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
9659 #define FDCAN_IR_TC_Pos                     (7U)
9660 #define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
9661 #define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
9662 #define FDCAN_IR_TCF_Pos                    (8U)
9663 #define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
9664 #define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
9665 #define FDCAN_IR_TFE_Pos                    (9U)
9666 #define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
9667 #define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
9668 #define FDCAN_IR_TEFN_Pos                   (10U)
9669 #define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
9670 #define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
9671 #define FDCAN_IR_TEFF_Pos                   (11U)
9672 #define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
9673 #define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
9674 #define FDCAN_IR_TEFL_Pos                   (12U)
9675 #define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
9676 #define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
9677 #define FDCAN_IR_TSW_Pos                    (13U)
9678 #define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
9679 #define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
9680 #define FDCAN_IR_MRAF_Pos                   (14U)
9681 #define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
9682 #define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
9683 #define FDCAN_IR_TOO_Pos                    (15U)
9684 #define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
9685 #define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
9686 #define FDCAN_IR_ELO_Pos                    (16U)
9687 #define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
9688 #define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
9689 #define FDCAN_IR_EP_Pos                     (17U)
9690 #define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
9691 #define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
9692 #define FDCAN_IR_EW_Pos                     (18U)
9693 #define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
9694 #define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
9695 #define FDCAN_IR_BO_Pos                     (19U)
9696 #define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
9697 #define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
9698 #define FDCAN_IR_WDI_Pos                    (20U)
9699 #define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
9700 #define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
9701 #define FDCAN_IR_PEA_Pos                    (21U)
9702 #define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
9703 #define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
9704 #define FDCAN_IR_PED_Pos                    (22U)
9705 #define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
9706 #define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
9707 #define FDCAN_IR_ARA_Pos                    (23U)
9708 #define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
9709 #define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */
9710 
9711 /*****************  Bit definition for FDCAN_IE register  ********************* */
9712 #define FDCAN_IE_RF0NE_Pos                  (0U)
9713 #define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
9714 #define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
9715 #define FDCAN_IE_RF0FE_Pos                  (1U)
9716 #define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
9717 #define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
9718 #define FDCAN_IE_RF0LE_Pos                  (2U)
9719 #define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
9720 #define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
9721 #define FDCAN_IE_RF1NE_Pos                  (3U)
9722 #define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
9723 #define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
9724 #define FDCAN_IE_RF1FE_Pos                  (4U)
9725 #define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
9726 #define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
9727 #define FDCAN_IE_RF1LE_Pos                  (5U)
9728 #define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
9729 #define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
9730 #define FDCAN_IE_HPME_Pos                   (6U)
9731 #define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
9732 #define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
9733 #define FDCAN_IE_TCE_Pos                    (7U)
9734 #define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
9735 #define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
9736 #define FDCAN_IE_TCFE_Pos                   (8U)
9737 #define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
9738 #define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
9739 #define FDCAN_IE_TFEE_Pos                   (9U)
9740 #define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
9741 #define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
9742 #define FDCAN_IE_TEFNE_Pos                  (10U)
9743 #define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
9744 #define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
9745 #define FDCAN_IE_TEFFE_Pos                  (11U)
9746 #define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
9747 #define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
9748 #define FDCAN_IE_TEFLE_Pos                  (12U)
9749 #define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
9750 #define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
9751 #define FDCAN_IE_TSWE_Pos                   (13U)
9752 #define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
9753 #define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
9754 #define FDCAN_IE_MRAFE_Pos                  (14U)
9755 #define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
9756 #define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
9757 #define FDCAN_IE_TOOE_Pos                   (15U)
9758 #define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
9759 #define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
9760 #define FDCAN_IE_ELOE_Pos                   (16U)
9761 #define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
9762 #define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
9763 #define FDCAN_IE_EPE_Pos                    (17U)
9764 #define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
9765 #define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
9766 #define FDCAN_IE_EWE_Pos                    (18U)
9767 #define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
9768 #define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
9769 #define FDCAN_IE_BOE_Pos                    (19U)
9770 #define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
9771 #define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
9772 #define FDCAN_IE_WDIE_Pos                   (20U)
9773 #define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
9774 #define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
9775 #define FDCAN_IE_PEAE_Pos                   (21U)
9776 #define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
9777 #define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
9778 #define FDCAN_IE_PEDE_Pos                   (22U)
9779 #define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
9780 #define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
9781 #define FDCAN_IE_ARAE_Pos                   (23U)
9782 #define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
9783 #define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */
9784 
9785 /*****************  Bit definition for FDCAN_ILS register  ******************** **/
9786 #define FDCAN_ILS_RXFIFO0_Pos               (0U)
9787 #define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
9788 #define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
9789                                                                                         Rx FIFO 0 is Full
9790                                                                                         Rx FIFO 0 Has New Message                */
9791 #define FDCAN_ILS_RXFIFO1_Pos               (1U)
9792 #define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
9793 #define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
9794                                                                                         Rx FIFO 1 is Full
9795                                                                                         Rx FIFO 1 Has New Message                */
9796 #define FDCAN_ILS_SMSG_Pos                  (2U)
9797 #define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
9798 #define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
9799                                                                                         Transmission Completed
9800                                                                                         High Priority Message                    */
9801 #define FDCAN_ILS_TFERR_Pos                 (3U)
9802 #define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
9803 #define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
9804                                                                                         Tx Event FIFO Full
9805                                                                                         Tx Event FIFO New Entry
9806                                                                                         Tx FIFO Empty Interrupt Line             */
9807 #define FDCAN_ILS_MISC_Pos                  (4U)
9808 #define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
9809 #define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
9810                                                                                         Message RAM Access Failure
9811                                                                                         Timestamp Wraparound                    */
9812 #define FDCAN_ILS_BERR_Pos                  (5U)
9813 #define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
9814 #define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
9815                                                                                         Error Logging Overflow                   */
9816 #define FDCAN_ILS_PERR_Pos                  (6U)
9817 #define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
9818 #define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
9819                                                                                         Protocol Error in Data Phase Line
9820                                                                                         Protocol Error in Arbitration Phase Line
9821                                                                                         Watchdog Interrupt Line
9822                                                                                         Bus_Off Status
9823                                                                                         Warning Status                           */
9824 
9825 /*****************  Bit definition for FDCAN_ILE register  ******************** **/
9826 #define FDCAN_ILE_EINT0_Pos                 (0U)
9827 #define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
9828 #define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0                  */
9829 #define FDCAN_ILE_EINT1_Pos                 (1U)
9830 #define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
9831 #define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1                  */
9832 
9833 /*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
9834 #define FDCAN_RXGFC_RRFE_Pos                (0U)
9835 #define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
9836 #define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended            */
9837 #define FDCAN_RXGFC_RRFS_Pos                (1U)
9838 #define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
9839 #define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard            */
9840 #define FDCAN_RXGFC_ANFE_Pos                (2U)
9841 #define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
9842 #define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
9843 #define FDCAN_RXGFC_ANFS_Pos                (4U)
9844 #define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
9845 #define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
9846 #define FDCAN_RXGFC_F1OM_Pos                (8U)
9847 #define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
9848 #define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
9849 #define FDCAN_RXGFC_F0OM_Pos                (9U)
9850 #define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
9851 #define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
9852 #define FDCAN_RXGFC_LSS_Pos                 (16U)
9853 #define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
9854 #define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
9855 #define FDCAN_RXGFC_LSE_Pos                 (24U)
9856 #define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
9857 #define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */
9858 
9859 /*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
9860 #define FDCAN_XIDAM_EIDM_Pos                (0U)
9861 #define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
9862 #define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */
9863 
9864 /*****************  Bit definition for FDCAN_HPMS register  ******************* **/
9865 #define FDCAN_HPMS_BIDX_Pos                 (0U)
9866 #define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
9867 #define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
9868 #define FDCAN_HPMS_MSI_Pos                  (6U)
9869 #define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
9870 #define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
9871 #define FDCAN_HPMS_FIDX_Pos                 (8U)
9872 #define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
9873 #define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
9874 #define FDCAN_HPMS_FLST_Pos                 (15U)
9875 #define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
9876 #define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */
9877 
9878 /*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
9879 #define FDCAN_RXF0S_F0FL_Pos                (0U)
9880 #define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
9881 #define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
9882 #define FDCAN_RXF0S_F0GI_Pos                (8U)
9883 #define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
9884 #define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
9885 #define FDCAN_RXF0S_F0PI_Pos                (16U)
9886 #define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
9887 #define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
9888 #define FDCAN_RXF0S_F0F_Pos                 (24U)
9889 #define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
9890 #define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
9891 #define FDCAN_RXF0S_RF0L_Pos                (25U)
9892 #define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
9893 #define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */
9894 
9895 /*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
9896 #define FDCAN_RXF0A_F0AI_Pos                (0U)
9897 #define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
9898 #define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */
9899 
9900 /*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
9901 #define FDCAN_RXF1S_F1FL_Pos                (0U)
9902 #define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
9903 #define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
9904 #define FDCAN_RXF1S_F1GI_Pos                (8U)
9905 #define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
9906 #define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
9907 #define FDCAN_RXF1S_F1PI_Pos                (16U)
9908 #define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
9909 #define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
9910 #define FDCAN_RXF1S_F1F_Pos                 (24U)
9911 #define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
9912 #define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
9913 #define FDCAN_RXF1S_RF1L_Pos                (25U)
9914 #define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
9915 #define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */
9916 
9917 /*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
9918 #define FDCAN_RXF1A_F1AI_Pos                (0U)
9919 #define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
9920 #define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */
9921 
9922 /*****************  Bit definition for FDCAN_TXBC register  ******************* **/
9923 #define FDCAN_TXBC_TFQM_Pos                 (24U)
9924 #define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
9925 #define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */
9926 
9927 /*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
9928 #define FDCAN_TXFQS_TFFL_Pos                (0U)
9929 #define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
9930 #define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
9931 #define FDCAN_TXFQS_TFGI_Pos                (8U)
9932 #define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
9933 #define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
9934 #define FDCAN_TXFQS_TFQPI_Pos               (16U)
9935 #define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
9936 #define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
9937 #define FDCAN_TXFQS_TFQF_Pos                (21U)
9938 #define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
9939 #define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */
9940 
9941 /*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
9942 #define FDCAN_TXBRP_TRP_Pos                 (0U)
9943 #define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
9944 #define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */
9945 
9946 /*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
9947 #define FDCAN_TXBAR_AR_Pos                  (0U)
9948 #define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
9949 #define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */
9950 
9951 /*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
9952 #define FDCAN_TXBCR_CR_Pos                  (0U)
9953 #define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
9954 #define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */
9955 
9956 /*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
9957 #define FDCAN_TXBTO_TO_Pos                  (0U)
9958 #define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
9959 #define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */
9960 
9961 /*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
9962 #define FDCAN_TXBCF_CF_Pos                  (0U)
9963 #define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
9964 #define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */
9965 
9966 /*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
9967 #define FDCAN_TXBTIE_TIE_Pos                (0U)
9968 #define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
9969 #define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */
9970 
9971 /*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
9972 #define FDCAN_TXBCIE_CFIE_Pos               (0U)
9973 #define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
9974 #define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */
9975 
9976 /*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
9977 #define FDCAN_TXEFS_EFFL_Pos                (0U)
9978 #define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
9979 #define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
9980 #define FDCAN_TXEFS_EFGI_Pos                (8U)
9981 #define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
9982 #define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
9983 #define FDCAN_TXEFS_EFPI_Pos                (16U)
9984 #define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
9985 #define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
9986 #define FDCAN_TXEFS_EFF_Pos                 (24U)
9987 #define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
9988 #define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
9989 #define FDCAN_TXEFS_TEFL_Pos                (25U)
9990 #define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
9991 #define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */
9992 
9993 /*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
9994 #define FDCAN_TXEFA_EFAI_Pos                (0U)
9995 #define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
9996 #define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */
9997 
9998 /*!<FDCAN config registers */
9999 /*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
10000 #define FDCAN_CKDIV_PDIV_Pos                (0U)
10001 #define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
10002 #define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */
10003 
10004 /******************************************************************************/
10005 /*                                                                            */
10006 /*                          HDMI-CEC (CEC)                                    */
10007 /*                                                                            */
10008 /******************************************************************************/
10009 
10010 /*******************  Bit definition for CEC_CR register  *********************/
10011 #define CEC_CR_CECEN_Pos         (0U)
10012 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
10013 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
10014 #define CEC_CR_TXSOM_Pos         (1U)
10015 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
10016 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
10017 #define CEC_CR_TXEOM_Pos         (2U)
10018 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
10019 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
10020 
10021 /*******************  Bit definition for CEC_CFGR register  *******************/
10022 #define CEC_CFGR_SFT_Pos         (0U)
10023 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
10024 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
10025 #define CEC_CFGR_RXTOL_Pos       (3U)
10026 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
10027 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
10028 #define CEC_CFGR_BRESTP_Pos      (4U)
10029 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
10030 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
10031 #define CEC_CFGR_BREGEN_Pos      (5U)
10032 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
10033 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
10034 #define CEC_CFGR_LBPEGEN_Pos     (6U)
10035 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
10036 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
10037 #define CEC_CFGR_SFTOPT_Pos      (8U)
10038 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
10039 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
10040 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
10041 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
10042 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
10043 #define CEC_CFGR_OAR_Pos         (16U)
10044 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
10045 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
10046 #define CEC_CFGR_LSTN_Pos        (31U)
10047 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
10048 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
10049 
10050 /*******************  Bit definition for CEC_TXDR register  *******************/
10051 #define CEC_TXDR_TXD_Pos         (0U)
10052 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
10053 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
10054 
10055 /*******************  Bit definition for CEC_RXDR register  *******************/
10056 #define CEC_RXDR_RXD_Pos         (0U)
10057 #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
10058 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
10059 
10060 /*******************  Bit definition for CEC_ISR register  ********************/
10061 #define CEC_ISR_RXBR_Pos         (0U)
10062 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
10063 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
10064 #define CEC_ISR_RXEND_Pos        (1U)
10065 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
10066 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
10067 #define CEC_ISR_RXOVR_Pos        (2U)
10068 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
10069 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
10070 #define CEC_ISR_BRE_Pos          (3U)
10071 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
10072 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
10073 #define CEC_ISR_SBPE_Pos         (4U)
10074 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
10075 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
10076 #define CEC_ISR_LBPE_Pos         (5U)
10077 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
10078 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
10079 #define CEC_ISR_RXACKE_Pos       (6U)
10080 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
10081 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
10082 #define CEC_ISR_ARBLST_Pos       (7U)
10083 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
10084 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
10085 #define CEC_ISR_TXBR_Pos         (8U)
10086 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
10087 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
10088 #define CEC_ISR_TXEND_Pos        (9U)
10089 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
10090 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
10091 #define CEC_ISR_TXUDR_Pos        (10U)
10092 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
10093 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
10094 #define CEC_ISR_TXERR_Pos        (11U)
10095 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
10096 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
10097 #define CEC_ISR_TXACKE_Pos       (12U)
10098 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
10099 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
10100 
10101 /*******************  Bit definition for CEC_IER register  ********************/
10102 #define CEC_IER_RXBRIE_Pos       (0U)
10103 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
10104 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
10105 #define CEC_IER_RXENDIE_Pos      (1U)
10106 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
10107 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
10108 #define CEC_IER_RXOVRIE_Pos      (2U)
10109 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
10110 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
10111 #define CEC_IER_BREIE_Pos        (3U)
10112 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
10113 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
10114 #define CEC_IER_SBPEIE_Pos       (4U)
10115 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
10116 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
10117 #define CEC_IER_LBPEIE_Pos       (5U)
10118 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
10119 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
10120 #define CEC_IER_RXACKEIE_Pos     (6U)
10121 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
10122 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
10123 #define CEC_IER_ARBLSTIE_Pos     (7U)
10124 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
10125 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
10126 #define CEC_IER_TXBRIE_Pos       (8U)
10127 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
10128 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
10129 #define CEC_IER_TXENDIE_Pos      (9U)
10130 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
10131 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
10132 #define CEC_IER_TXUDRIE_Pos      (10U)
10133 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
10134 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
10135 #define CEC_IER_TXERRIE_Pos      (11U)
10136 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
10137 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
10138 #define CEC_IER_TXACKEIE_Pos     (12U)
10139 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
10140 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
10141 
10142 /******************************************************************************/
10143 /*                                                                            */
10144 /*                                    FLASH                                   */
10145 /*                                                                            */
10146 /******************************************************************************/
10147 #define FLASH_LATENCY_DEFAULT               FLASH_ACR_LATENCY_3WS                   /* FLASH Three Latency cycle */
10148 /* To be used with Silicon samples *:
10149 #define FLASH_SIZE                          ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x200000U : \
10150                                             ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x200000U : \
10151                                             (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))*/
10152 #define FLASH_BLOCKBASED_NB_REG             (4U)                                    /*!< 4 Block-based registers for each Flash bank */
10153 #define FLASH_SIZE                          (0x200000U)                             /*!< FLASH Size */
10154 #define FLASH_BANK_SIZE                     (FLASH_SIZE >> 1U)                      /*!< FLASH Bank Size */
10155 #define FLASH_SECTOR_SIZE                   0x2000U                                 /*!< Flash Sector Size: 8 KB */
10156 #define FLASH_SECTOR_NB                     (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)   /*!< Flash Sector number */
10157 
10158 /*******************  Bits definition for FLASH_ACR register  *****************/
10159 #define FLASH_ACR_LATENCY_Pos               (0U)
10160 #define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)        /*!< 0x0000000F */
10161 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                   /*!< Latency    */
10162 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
10163 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
10164 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
10165 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
10166 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
10167 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
10168 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
10169 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
10170 #define FLASH_ACR_LATENCY_8WS               (0x00000008U)
10171 #define FLASH_ACR_LATENCY_9WS               (0x00000009U)
10172 #define FLASH_ACR_LATENCY_10WS              (0x0000000AU)
10173 #define FLASH_ACR_LATENCY_11WS              (0x0000000BU)
10174 #define FLASH_ACR_LATENCY_12WS              (0x0000000CU)
10175 #define FLASH_ACR_LATENCY_13WS              (0x0000000DU)
10176 #define FLASH_ACR_LATENCY_14WS              (0x0000000EU)
10177 #define FLASH_ACR_LATENCY_15WS              (0x0000000FU)
10178 #define FLASH_ACR_WRHIGHFREQ_Pos            (4U)
10179 #define FLASH_ACR_WRHIGHFREQ_Msk            (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000030 */
10180 #define FLASH_ACR_WRHIGHFREQ                FLASH_ACR_WRHIGHFREQ_Msk                /*!< Flash signal delay */
10181 #define FLASH_ACR_WRHIGHFREQ_0              (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000010 */
10182 #define FLASH_ACR_WRHIGHFREQ_1              (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000020 */
10183 #define FLASH_ACR_PRFTEN_Pos                (8U)
10184 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)         /*!< 0x00000100 */
10185 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                    /*!< Prefetch enable */
10186 
10187 /*******************  Bits definition for FLASH_OPSR register  ***************/
10188 #define FLASH_OPSR_ADDR_OP_Pos              (0U)
10189 #define FLASH_OPSR_ADDR_OP_Msk              (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos)   /*!< 0x000FFFFF */
10190 #define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                  /*!< Interrupted operation address */
10191 #define FLASH_OPSR_DATA_OP_Pos              (21U)
10192 #define FLASH_OPSR_DATA_OP_Msk              (0x1UL << FLASH_OPSR_DATA_OP_Pos)       /*!< 0x00200000 */
10193 #define FLASH_OPSR_DATA_OP                  FLASH_OPSR_DATA_OP_Msk                  /*!< Operation in Flash high-cycle data area interrupted */
10194 #define FLASH_OPSR_BK_OP_Pos                (22U)
10195 #define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)         /*!< 0x00400000 */
10196 #define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                    /*!< Interrupted operation bank */
10197 #define FLASH_OPSR_SYSF_OP_Pos              (23U)
10198 #define FLASH_OPSR_SYSF_OP_Msk              (0x1UL << FLASH_OPSR_SYSF_OP_Pos)       /*!< 0x00800000 */
10199 #define FLASH_OPSR_SYSF_OP                  FLASH_OPSR_SYSF_OP_Msk                  /*!< Operation in System Flash interrupted */
10200 #define FLASH_OPSR_OTP_OP_Pos               (24U)
10201 #define FLASH_OPSR_OTP_OP_Msk               (0x1UL << FLASH_OPSR_OTP_OP_Pos)        /*!< 0x01000000 */
10202 #define FLASH_OPSR_OTP_OP                   FLASH_OPSR_OTP_OP_Msk                   /*!< Operation in OTP area interrupted */
10203 #define FLASH_OPSR_CODE_OP_Pos              (29U)
10204 #define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0xE0000000 */
10205 #define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                  /*!< Flash memory operation code */
10206 #define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x20000000 */
10207 #define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x40000000 */
10208 #define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x80000000 */
10209 
10210 /*******************  Bits definition for FLASH_OPTCR register  *******************/
10211 #define FLASH_OPTCR_OPTLOCK_Pos             (0U)
10212 #define FLASH_OPTCR_OPTLOCK_Msk             (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)      /*!< 0x00000001 */
10213 #define FLASH_OPTCR_OPTLOCK                 FLASH_OPTCR_OPTLOCK_Msk                 /*!< FLASH_OPTCR lock option configuration bit */
10214 #define FLASH_OPTCR_OPTSTART_Pos            (1U)
10215 #define FLASH_OPTCR_OPTSTART_Msk            (0x1UL << FLASH_OPTCR_OPTSTART_Pos)     /*!< 0x00000002 */
10216 #define FLASH_OPTCR_OPTSTART                FLASH_OPTCR_OPTSTART_Msk                /*!< Option byte start change option configuration bit */
10217 #define FLASH_OPTCR_SWAP_BANK_Pos           (31U)
10218 #define FLASH_OPTCR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)    /*!< 0x80000000 */
10219 #define FLASH_OPTCR_SWAP_BANK               FLASH_OPTCR_SWAP_BANK_Msk               /*!< Bank swapping option configuration bit */
10220 
10221 /*******************  Bits definition for FLASH_SR register  ***********************/
10222 #define FLASH_SR_BSY_Pos                    (0U)
10223 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)             /*!< 0x00000001 */
10224 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                        /*!< Busy flag */
10225 #define FLASH_SR_WBNE_Pos                   (1U)
10226 #define FLASH_SR_WBNE_Msk                   (0x1UL << FLASH_SR_WBNE_Pos)            /*!< 0x00000002 */
10227 #define FLASH_SR_WBNE                       FLASH_SR_WBNE_Msk                       /*!< Write buffer not empty flag */
10228 #define FLASH_SR_PUF_STATE_Pos              (2U)
10229 #define FLASH_SR_PUF_STATE_Msk              (0x1UL << FLASH_SR_PUF_STATE_Pos)       /*!< 0x00000004 */
10230 #define FLASH_SR_PUF_STATE                  FLASH_SR_PUF_STATE_Msk                  /*!< PUF readiness flag */
10231 #define FLASH_SR_DBNE_Pos                   (3U)
10232 #define FLASH_SR_DBNE_Msk                   (0x1UL << FLASH_SR_DBNE_Pos)            /*!< 0x00000008 */
10233 #define FLASH_SR_DBNE                       FLASH_SR_DBNE_Msk                       /*!< Data buffer not empty flag */
10234 #define FLASH_SR_EOP_Pos                    (16U)
10235 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00010000 */
10236 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                        /*!< End-of-program flag */
10237 #define FLASH_SR_WRPERR_Pos                 (17U)
10238 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00020000 */
10239 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                     /*!< Write protection error flag */
10240 #define FLASH_SR_PGSERR_Pos                 (18U)
10241 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00040000 */
10242 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                     /*!< Programming sequence error flag */
10243 #define FLASH_SR_STRBERR_Pos                (19U)
10244 #define FLASH_SR_STRBERR_Msk                (0x1UL << FLASH_SR_STRBERR_Pos)         /*!< 0x00080000 */
10245 #define FLASH_SR_STRBERR                    FLASH_SR_STRBERR_Msk                    /*!< Strobe error flag */
10246 #define FLASH_SR_INCERR_Pos                 (20U)
10247 #define FLASH_SR_INCERR_Msk                 (0x1UL << FLASH_SR_INCERR_Pos)          /*!< 0x00100000 */
10248 #define FLASH_SR_INCERR                     FLASH_SR_INCERR_Msk                     /*!< Inconsistency error flag */
10249 #define FLASH_SR_OBKERR_Pos                 (21U)
10250 #define FLASH_SR_OBKERR_Msk                 (0x1UL << FLASH_SR_OBKERR_Pos)          /*!< 0x00200000 */
10251 #define FLASH_SR_OBKERR                     FLASH_SR_OBKERR_Msk                     /*!< OBK general error flag */
10252 #define FLASH_SR_OBKWERR_Pos                (22U)
10253 #define FLASH_SR_OBKWERR_Msk                (0x1UL << FLASH_SR_OBKWERR_Pos)         /*!< 0x00400000 */
10254 #define FLASH_SR_OBKWERR                    FLASH_SR_OBKWERR_Msk                    /*!< OBK write error flag */
10255 #define FLASH_SR_OPTCHANGEERR_Pos           (23U)
10256 #define FLASH_SR_OPTCHANGEERR_Msk           (0x1UL << FLASH_SR_OPTCHANGEERR_Pos)    /*!< 0x00800000 */
10257 #define FLASH_SR_OPTCHANGEERR               FLASH_SR_OPTCHANGEERR_Msk               /*!< Option byte change error flag */
10258 
10259 /*******************  Bits definition for FLASH_CR register  ***********************/
10260 #define FLASH_CR_LOCK_Pos                   (0U)
10261 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x00000001 */
10262 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                       /*!< Configuration lock bit */
10263 #define FLASH_CR_PG_Pos                     (1U)
10264 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000002 */
10265 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                         /*!< Programming control bit */
10266 #define FLASH_CR_SER_Pos                    (2U)
10267 #define FLASH_CR_SER_Msk                    (0x1UL << FLASH_CR_SER_Pos)             /*!< 0x00000004 */
10268 #define FLASH_CR_SER                        FLASH_CR_SER_Msk                        /*!< Sector erase request */
10269 #define FLASH_CR_BER_Pos                    (3U)
10270 #define FLASH_CR_BER_Msk                    (0x1UL << FLASH_CR_BER_Pos)             /*!< 0x00000008 */
10271 #define FLASH_CR_BER                        FLASH_CR_BER_Msk                        /*!< Bank erase request */
10272 #define FLASH_CR_FW_Pos                     (4U)
10273 #define FLASH_CR_FW_Msk                     (0x1UL << FLASH_CR_FW_Pos)              /*!< 0x00000010 */
10274 #define FLASH_CR_FW                         FLASH_CR_FW_Msk                         /*!< Write forcing control bit */
10275 #define FLASH_CR_START_Pos                  (5U)
10276 #define FLASH_CR_START_Msk                  (0x1UL << FLASH_CR_START_Pos)           /*!< 0x00000020 */
10277 #define FLASH_CR_START                      FLASH_CR_START_Msk                      /*!< Erase start control bit */
10278 #define FLASH_CR_SNB_Pos                    (6U)
10279 #define FLASH_CR_SNB_Msk                    (0x7FUL << FLASH_CR_SNB_Pos)            /*!< 0x00001FC0 */
10280 #define FLASH_CR_SNB                        FLASH_CR_SNB_Msk                        /*!< Sector erase selection number */
10281 #define FLASH_CR_SNB_0                      (0x01UL << FLASH_CR_SNB_Pos)            /*!< 0x00000040 */
10282 #define FLASH_CR_SNB_1                      (0x02UL << FLASH_CR_SNB_Pos)            /*!< 0x00000080 */
10283 #define FLASH_CR_SNB_2                      (0x04UL << FLASH_CR_SNB_Pos)            /*!< 0x00000100 */
10284 #define FLASH_CR_SNB_3                      (0x08UL << FLASH_CR_SNB_Pos)            /*!< 0x00000200 */
10285 #define FLASH_CR_SNB_4                      (0x10UL << FLASH_CR_SNB_Pos)            /*!< 0x00000400 */
10286 #define FLASH_CR_SNB_5                      (0x20UL << FLASH_CR_SNB_Pos)            /*!< 0x00000800 */
10287 #define FLASH_CR_SNB_6                      (0x40UL << FLASH_CR_SNB_Pos)            /*!< 0x00001000 */
10288 #define FLASH_CR_PUF_LAUNCH_Pos             (13U)
10289 #define FLASH_CR_PUF_LAUNCH_Msk             (0x1UL << FLASH_CR_PUF_LAUNCH_Pos)      /*!< 0x00002000 */
10290 #define FLASH_CR_PUF_LAUNCH                 FLASH_CR_PUF_LAUNCH_Msk                 /*!< PUF preparation start control bit */
10291 #define FLASH_CR_MER_Pos                    (15U)
10292 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)             /*!< 0x00008000 */
10293 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                        /*!< Mass erase */
10294 #define FLASH_CR_EOPIE_Pos                  (16U)
10295 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x00010000 */
10296 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                      /*!< End-of-operation interrupt control bit */
10297 #define FLASH_CR_WRPERRIE_Pos               (17U)
10298 #define FLASH_CR_WRPERRIE_Msk               (0x1UL << FLASH_CR_WRPERRIE_Pos)        /*!< 0x00020000 */
10299 #define FLASH_CR_WRPERRIE                   FLASH_CR_WRPERRIE_Msk                   /*!< Write protection error interrupt enable bit */
10300 #define FLASH_CR_PGSERRIE_Pos               (18U)
10301 #define FLASH_CR_PGSERRIE_Msk               (0x1UL << FLASH_CR_PGSERRIE_Pos)        /*!< 0x00040000 */
10302 #define FLASH_CR_PGSERRIE                   FLASH_CR_PGSERRIE_Msk                   /*!< Programming sequence error interrupt enable bit */
10303 #define FLASH_CR_STRBERRIE_Pos              (19U)
10304 #define FLASH_CR_STRBERRIE_Msk              (0x1UL << FLASH_CR_STRBERRIE_Pos)       /*!< 0x00080000 */
10305 #define FLASH_CR_STRBERRIE                  FLASH_CR_STRBERRIE_Msk                  /*!< Strobe error interrupt enable bit */
10306 #define FLASH_CR_INCERRIE_Pos               (20U)
10307 #define FLASH_CR_INCERRIE_Msk               (0x1UL << FLASH_CR_INCERRIE_Pos)        /*!< 0x00100000 */
10308 #define FLASH_CR_INCERRIE                   FLASH_CR_INCERRIE_Msk                   /*!< Inconsistency error interrupt enable bit */
10309 #define FLASH_CR_OBKERRIE_Pos               (21U)
10310 #define FLASH_CR_OBKERRIE_Msk               (0x1UL << FLASH_CR_OBKERRIE_Pos)        /*!< 0x00200000 */
10311 #define FLASH_CR_OBKERRIE                   FLASH_CR_OBKERRIE_Msk                   /*!< OBK general error interrupt enable bitt */
10312 #define FLASH_CR_OBKWERRIE_Pos              (22U)
10313 #define FLASH_CR_OBKWERRIE_Msk              (0x1UL << FLASH_CR_OBKWERRIE_Pos)       /*!< 0x00400000 */
10314 #define FLASH_CR_OBKWERRIE                  FLASH_CR_OBKWERRIE_Msk                  /*!< OBK write error interrupt enable bit */
10315 #define FLASH_CR_OPTCHANGEERRIE_Pos         (23U)
10316 #define FLASH_CR_OPTCHANGEERRIE_Msk         (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos)  /*!< 0x00800000 */
10317 #define FLASH_CR_OPTCHANGEERRIE             FLASH_CR_OPTCHANGEERRIE_Msk             /*!< Option byte change error interrupt enable bit */
10318 #define FLASH_CR_INV_Pos                    (29U)
10319 #define FLASH_CR_INV_Msk                    (0x1UL << FLASH_CR_INV_Pos)             /*!< 0x20000000 */
10320 #define FLASH_CR_INV                        FLASH_CR_INV_Msk                        /*!< Flash Security State Invert */
10321 #define FLASH_CR_BKSEL_Pos                  (31U)
10322 #define FLASH_CR_BKSEL_Msk                  (0x1UL << FLASH_CR_BKSEL_Pos)           /*!< 0x10000000 */
10323 #define FLASH_CR_BKSEL                      FLASH_CR_BKSEL_Msk                      /*!< Bank selector */
10324 
10325 /*******************  Bits definition for FLASH_CCR register  *******************/
10326 #define FLASH_CCR_CLR_EOP_Pos               (16U)
10327 #define FLASH_CCR_CLR_EOP_Msk               (0x1UL << FLASH_CCR_CLR_EOP_Pos)        /*!< 0x00010000 */
10328 #define FLASH_CCR_CLR_EOP                   FLASH_CCR_CLR_EOP_Msk                   /*!< EOP flag clear bit */
10329 #define FLASH_CCR_CLR_WRPERR_Pos            (17U)
10330 #define FLASH_CCR_CLR_WRPERR_Msk            (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)     /*!< 0x00020000 */
10331 #define FLASH_CCR_CLR_WRPERR                FLASH_CCR_CLR_WRPERR_Msk                /*!< WRPERR flag clear bit */
10332 #define FLASH_CCR_CLR_PGSERR_Pos            (18U)
10333 #define FLASH_CCR_CLR_PGSERR_Msk            (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)     /*!< 0x00040000 */
10334 #define FLASH_CCR_CLR_PGSERR                FLASH_CCR_CLR_PGSERR_Msk                /*!< PGSERR flag clear bit */
10335 #define FLASH_CCR_CLR_STRBERR_Pos           (19U)
10336 #define FLASH_CCR_CLR_STRBERR_Msk           (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)    /*!< 0x00080000 */
10337 #define FLASH_CCR_CLR_STRBERR               FLASH_CCR_CLR_STRBERR_Msk               /*!< STRBERR flag clear bit */
10338 #define FLASH_CCR_CLR_INCERR_Pos            (20U)
10339 #define FLASH_CCR_CLR_INCERR_Msk            (0x1UL << FLASH_CCR_CLR_INCERR_Pos)     /*!< 0x00100000 */
10340 #define FLASH_CCR_CLR_INCERR                FLASH_CCR_CLR_INCERR_Msk                /*!< INCERR flag clear bit */
10341 #define FLASH_CCR_CLR_OBKERR_Pos            (21U)
10342 #define FLASH_CCR_CLR_OBKERR_Msk            (0x1UL << FLASH_CCR_CLR_OBKERR_Pos)     /*!< 0x00200000 */
10343 #define FLASH_CCR_CLR_OBKERR                FLASH_CCR_CLR_OBKERR_Msk                /*!< OBKERR flag clear bit */
10344 #define FLASH_CCR_CLR_OBKWERR_Pos           (22U)
10345 #define FLASH_CCR_CLR_OBKWERR_Msk           (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos)    /*!< 0x00400000 */
10346 #define FLASH_CCR_CLR_OBKWERR               FLASH_CCR_CLR_OBKWERR_Msk               /*!< OBKWERR flag clear bit */
10347 #define FLASH_CCR_CLR_OPTCHANGEERR_Pos      (23U)
10348 #define FLASH_CCR_CLR_OPTCHANGEERR_Msk      (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */
10349 #define FLASH_CCR_CLR_OPTCHANGEERR          FLASH_CCR_CLR_OPTCHANGEERR_Msk            /*!< Option byte change error clear bit */
10350 
10351 /******************  Bits definition for FLASH_PRIVCFGR register  ***********/
10352 #define FLASH_PRIVCFGR_SPRIV_Pos            (0U)
10353 #define FLASH_PRIVCFGR_SPRIV_Msk            (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos)     /*!< 0x00000001 */
10354 #define FLASH_PRIVCFGR_SPRIV                FLASH_PRIVCFGR_SPRIV_Msk                /*!< Privilege protection for secure registers */
10355 #define FLASH_PRIVCFGR_NSPRIV_Pos           (1U)
10356 #define FLASH_PRIVCFGR_NSPRIV_Msk           (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos)    /*!< 0x00000002 */
10357 #define FLASH_PRIVCFGR_NSPRIV               FLASH_PRIVCFGR_NSPRIV_Msk               /*!< Privilege protection for non-secure registers */
10358 
10359 /******************  Bits definition for FLASH_OBKCFGR register  *****************/
10360 #define FLASH_OBKCFGR_LOCK_Pos              (0U)
10361 #define FLASH_OBKCFGR_LOCK_Msk              (0x1UL << FLASH_OBKCFGR_LOCK_Pos)       /*!< 0x00000001 */
10362 #define FLASH_OBKCFGR_LOCK                  FLASH_OBKCFGR_LOCK_Msk                  /*!< OBKCFGR lock */
10363 #define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos     (1U)
10364 #define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk     (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */
10365 #define FLASH_OBKCFGR_SWAP_SECT_REQ         FLASH_OBKCFGR_SWAP_SECT_REQ_Msk            /*!< OBK swap sector request */
10366 #define FLASH_OBKCFGR_ALT_SECT_Pos          (2U)
10367 #define FLASH_OBKCFGR_ALT_SECT_Msk          (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos)   /*!< 0x00000004 */
10368 #define FLASH_OBKCFGR_ALT_SECT              FLASH_OBKCFGR_ALT_SECT_Msk              /*!< Alternate sector */
10369 #define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos    (3U)
10370 #define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk    (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */
10371 #define FLASH_OBKCFGR_ALT_SECT_ERASE        FLASH_OBKCFGR_ALT_SECT_ERASE_Msk            /*!< Alternate sector erase */
10372 #define FLASH_OBKCFGR_SWAP_OFFSET_Pos       (16U)
10373 #define FLASH_OBKCFGR_SWAP_OFFSET_Msk       (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */
10374 #define FLASH_OBKCFGR_SWAP_OFFSET           FLASH_OBKCFGR_SWAP_OFFSET_Msk              /*!< Swap offset */
10375 
10376 /******************  Bits definition for FLASH_HDPEXTR register  *****************/
10377 #define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
10378 #define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos)  /*!< 0x0000007F */
10379 #define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 1 */
10380 #define FLASH_HDPEXTR_HDP2_EXT_Pos          (16U)
10381 #define FLASH_HDPEXTR_HDP2_EXT_Msk          (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos)  /*!< 0x007F0000 */
10382 #define FLASH_HDPEXTR_HDP2_EXT              FLASH_HDPEXTR_HDP2_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 2 */
10383 
10384 /*******************  Bits definition for FLASH_OPTSR register  ***************/
10385 #define FLASH_OPTSR_BOR_LEV_Pos             (0U)
10386 #define FLASH_OPTSR_BOR_LEV_Msk             (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000003 */
10387 #define FLASH_OPTSR_BOR_LEV                 FLASH_OPTSR_BOR_LEV_Msk                 /*!< Brownout level option bit */
10388 #define FLASH_OPTSR_BOR_LEV_0               (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000001 */
10389 #define FLASH_OPTSR_BOR_LEV_1               (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000002 */
10390 #define FLASH_OPTSR_BORH_EN_Pos             (2U)
10391 #define FLASH_OPTSR_BORH_EN_Msk             (0x1UL << FLASH_OPTSR_BORH_EN_Pos)      /*!< 0x00000004 */
10392 #define FLASH_OPTSR_BORH_EN                 FLASH_OPTSR_BORH_EN_Msk                 /*!< Brownout high enable configuration bit */
10393 #define FLASH_OPTSR_IWDG_SW_Pos             (3U)
10394 #define FLASH_OPTSR_IWDG_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG_SW_Pos)      /*!< 0x00000008 */
10395 #define FLASH_OPTSR_IWDG_SW                 FLASH_OPTSR_IWDG_SW_Msk                 /*!< IWDG control mode option bit */
10396 #define FLASH_OPTSR_WWDG_SW_Pos             (4U)
10397 #define FLASH_OPTSR_WWDG_SW_Msk             (0x1UL << FLASH_OPTSR_WWDG_SW_Pos)      /*!< 0x00000010 */
10398 #define FLASH_OPTSR_WWDG_SW                 FLASH_OPTSR_WWDG_SW_Msk                 /*!< WWDG control mode option bit */
10399 #define FLASH_OPTSR_NRST_STOP_Pos           (6U)
10400 #define FLASH_OPTSR_NRST_STOP_Msk           (0x1UL << FLASH_OPTSR_NRST_STOP_Pos)    /*!< 0x00000040 */
10401 #define FLASH_OPTSR_NRST_STOP               FLASH_OPTSR_NRST_STOP_Msk               /*!< Stop mode entry reset option bit */
10402 #define FLASH_OPTSR_NRST_STDBY_Pos          (7U)
10403 #define FLASH_OPTSR_NRST_STDBY_Msk          (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos)   /*!< 0x00000080 */
10404 #define FLASH_OPTSR_NRST_STDBY              FLASH_OPTSR_NRST_STDBY_Msk              /*!< Standby mode entry reset option bit */
10405 #define FLASH_OPTSR_PRODUCT_STATE_Pos       (8U)
10406 #define FLASH_OPTSR_PRODUCT_STATE_Msk       (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */
10407 #define FLASH_OPTSR_PRODUCT_STATE           FLASH_OPTSR_PRODUCT_STATE_Msk             /*!< Life state code option byte */
10408 #define FLASH_OPTSR_IO_VDD_HSLV_Pos         (16U)
10409 #define FLASH_OPTSR_IO_VDD_HSLV_Msk         (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos)  /*!< 0x00010000 */
10410 #define FLASH_OPTSR_IO_VDD_HSLV             FLASH_OPTSR_IO_VDD_HSLV_Msk             /*!< VDD I/O high-speed at low-voltage option bit */
10411 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos      (17U)
10412 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk      (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */
10413 #define FLASH_OPTSR_IO_VDDIO2_HSLV          FLASH_OPTSR_IO_VDDIO2_HSLV_Msk            /*!< VDDIO2 I/O high-speed at low-voltage option bit */
10414 #define FLASH_OPTSR_IWDG_STOP_Pos           (20U)
10415 #define FLASH_OPTSR_IWDG_STOP_Msk           (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos)    /*!< 0x00100000 */
10416 #define FLASH_OPTSR_IWDG_STOP               FLASH_OPTSR_IWDG_STOP_Msk               /*!< Independent watchdog counter freeze in Stop mode */
10417 #define FLASH_OPTSR_IWDG_STDBY_Pos          (21U)
10418 #define FLASH_OPTSR_IWDG_STDBY_Msk          (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos)   /*!< 0x00200000 */
10419 #define FLASH_OPTSR_IWDG_STDBY              FLASH_OPTSR_IWDG_STDBY_Msk              /*!< Independent watchdog counter freeze in Standby mode */
10420 #define FLASH_OPTSR_BOOT_UBE_Pos            (22U)
10421 #define FLASH_OPTSR_BOOT_UBE_Msk            (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos)    /*!< 0x3FC00000 */
10422 #define FLASH_OPTSR_BOOT_UBE                FLASH_OPTSR_BOOT_UBE_Msk                /*!< Unique boot entry option byte */
10423 #define FLASH_OPTSR_SWAP_BANK_Pos           (31U)
10424 #define FLASH_OPTSR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos)    /*!< 0x80000000 */
10425 #define FLASH_OPTSR_SWAP_BANK               FLASH_OPTSR_SWAP_BANK_Msk               /*!< Bank swapping option bit */
10426 
10427 /*******************  Bits definition for FLASH_EPOCHR register  ***************/
10428 #define FLASH_EPOCHR_EPOCH_Pos              (0U)
10429 #define FLASH_EPOCHR_EPOCH_Msk              (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos)  /*!< 0x00FFFFFF */
10430 #define FLASH_EPOCHR_EPOCH                  FLASH_EPOCHR_EPOCH_Msk                  /*!< EPOCH counter */
10431 
10432 /*******************  Bits definition for FLASH_OPTSR2 register  ***************/
10433 #define FLASH_OPTSR2_SRAM1_3_RST_Pos        (2U)
10434 #define FLASH_OPTSR2_SRAM1_3_RST_Msk        (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos)  /*!< 0x00000004 */
10435 #define FLASH_OPTSR2_SRAM1_3_RST            FLASH_OPTSR2_SRAM1_3_RST_Msk             /*!< SRAM1 and SRAM3 erased when a system reset occurs */
10436 #define FLASH_OPTSR2_SRAM2_RST_Pos          (3U)
10437 #define FLASH_OPTSR2_SRAM2_RST_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos)   /*!< 0x00000008 */
10438 #define FLASH_OPTSR2_SRAM2_RST              FLASH_OPTSR2_SRAM2_RST_Msk              /*!< SRAM2 erased when a system reset occurs*/
10439 #define FLASH_OPTSR2_BKPRAM_ECC_Pos         (4U)
10440 #define FLASH_OPTSR2_BKPRAM_ECC_Msk         (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos)  /*!< 0x00000010 */
10441 #define FLASH_OPTSR2_BKPRAM_ECC             FLASH_OPTSR2_BKPRAM_ECC_Msk             /*!< Backup RAM ECC detection and correction enable */
10442 #define FLASH_OPTSR2_SRAM3_ECC_Pos          (5U)
10443 #define FLASH_OPTSR2_SRAM3_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos)   /*!< 0x00000020 */
10444 #define FLASH_OPTSR2_SRAM3_ECC              FLASH_OPTSR2_SRAM3_ECC_Msk              /*!< SRAM3 ECC detection and correction enable */
10445 #define FLASH_OPTSR2_SRAM2_ECC_Pos          (6U)
10446 #define FLASH_OPTSR2_SRAM2_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos)   /*!< 0x00000040 */
10447 #define FLASH_OPTSR2_SRAM2_ECC              FLASH_OPTSR2_SRAM2_ECC_Msk              /*!< SRAM2 ECC detection and correction disable */
10448 #define FLASH_OPTSR2_HUK_PUF_Pos            (15U)
10449 #define FLASH_OPTSR2_HUK_PUF_Msk            (0x1UL << FLASH_OPTSR2_HUK_PUF_Pos)     /*!< 0x00008000 */
10450 #define FLASH_OPTSR2_HUK_PUF                FLASH_OPTSR2_HUK_PUF_Msk                /*!< HUK enable */
10451 #define FLASH_OPTSR2_TZEN_Pos               (24U)
10452 #define FLASH_OPTSR2_TZEN_Msk               (0xFFUL << FLASH_OPTSR2_TZEN_Pos)       /*!< 0xFF000000 */
10453 #define FLASH_OPTSR2_TZEN                   FLASH_OPTSR2_TZEN_Msk                   /*!< TrustZone enable */
10454 
10455 /****************  Bits definition for FLASH_BOOTR register  **********************/
10456 #define FLASH_BOOTR_BOOT_LOCK_Pos           (0U)
10457 #define FLASH_BOOTR_BOOT_LOCK_Msk           (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos)   /*!< 0x000000FF */
10458 #define FLASH_BOOTR_BOOT_LOCK               FLASH_BOOTR_BOOT_LOCK_Msk               /*!< Boot Lock */
10459 #define FLASH_BOOTR_BOOTADD_Pos             (8U)
10460 #define FLASH_BOOTR_BOOTADD_Msk             (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */
10461 #define FLASH_BOOTR_BOOTADD                 FLASH_BOOTR_BOOTADD_Msk                 /*!< Boot address */
10462 
10463 /****************  Bits definition for FLASH_PRIVBBR register  *******************/
10464 #define FLASH_PRIVBBR_PRIVBB_Pos            (0U)
10465 #define FLASH_PRIVBBR_PRIVBB_Msk            (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */
10466 #define FLASH_PRIVBBR_PRIVBB                FLASH_PRIVBBR_PRIVBB_Msk                   /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */
10467 
10468 /*****************  Bits definition for FLASH_SECWMR register  ********************/
10469 #define FLASH_SECWMR_SECWM_STRT_Pos         (0U)
10470 #define FLASH_SECWMR_SECWM_STRT_Msk         (0x7FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000007F */
10471 #define FLASH_SECWMR_SECWM_STRT             FLASH_SECWMR_SECWM_STRT_Msk             /*!< Start sector of secure area */
10472 #define FLASH_SECWMR_SECWM_END_Pos          (16U)
10473 #define FLASH_SECWMR_SECWM_END_Msk          (0x7FUL << FLASH_SECWMR_SECWM_END_Pos)  /*!< 0x007F0000 */
10474 #define FLASH_SECWMR_SECWM_END              FLASH_SECWMR_SECWM_END_Msk              /*!< End sector of secure area */
10475 
10476 /*****************  Bits definition for FLASH_WRPR register  *********************/
10477 #define FLASH_WRPR_WRPSG_Pos                (0U)
10478 #define FLASH_WRPR_WRPSG_Msk                (0xFFFFFFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0xFFFFFFFF */
10479 #define FLASH_WRPR_WRPSG                    FLASH_WRPR_WRPSG_Msk  /*!< Sector group protection option status */
10480 
10481 /*****************  Bits definition for FLASH_EDATA register  ********************/
10482 #define FLASH_EDATAR_EDATA_STRT_Pos         (0U)
10483 #define FLASH_EDATAR_EDATA_STRT_Msk         (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos)  /*!< 0x00000003 */
10484 #define FLASH_EDATAR_EDATA_STRT             FLASH_EDATAR_EDATA_STRT_Msk             /*!< Flash high-cycle data start sector */
10485 #define FLASH_EDATAR_EDATA_EN_Pos           (15U)
10486 #define FLASH_EDATAR_EDATA_EN_Msk           (0x1UL << FLASH_EDATAR_EDATA_EN_Pos)    /*!< 0x00008000 */
10487 #define FLASH_EDATAR_EDATA_EN               FLASH_EDATAR_EDATA_EN_Msk               /*!< Flash high-cycle data enable */
10488 
10489 /*****************  Bits definition for FLASH_HDPR register  ********************/
10490 #define FLASH_HDPR_HDP_STRT_Pos             (0U)
10491 #define FLASH_HDPR_HDP_STRT_Msk             (0x7FUL << FLASH_HDPR_HDP_STRT_Pos)     /*!< 0x0000007F */
10492 #define FLASH_HDPR_HDP_STRT                 FLASH_HDPR_HDP_STRT_Msk                 /*!< Start sector of hide protection area */
10493 #define FLASH_HDPR_HDP_END_Pos              (16U)
10494 #define FLASH_HDPR_HDP_END_Msk              (0x7FUL << FLASH_HDPR_HDP_END_Pos)      /*!< 0x007F0000 */
10495 #define FLASH_HDPR_HDP_END                  FLASH_HDPR_HDP_END_Msk                  /*!< End sector of hide protection area */
10496 
10497 /*******************  Bits definition for FLASH_ECCR register  ***************/
10498 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
10499 #define FLASH_ECCR_ADDR_ECC_Msk             (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos)   /*!< 0x0000FFFF */
10500 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk                 /*!< ECC fail address */
10501 #define FLASH_ECCR_OBK_ECC_Pos              (20U)
10502 #define FLASH_ECCR_OBK_ECC_Msk              (0x1UL << FLASH_ECCR_OBK_ECC_Pos)       /*!< 0x00200000 */
10503 #define FLASH_ECCR_OBK_ECC                  FLASH_ECCR_OBK_ECC_Msk                  /*!< Flash OB Keys storage area ECC fail */
10504 #define FLASH_ECCR_DATA_ECC_Pos             (21U)
10505 #define FLASH_ECCR_DATA_ECC_Msk             (0x1UL << FLASH_ECCR_DATA_ECC_Pos)      /*!< 0x00400000 */
10506 #define FLASH_ECCR_DATA_ECC                 FLASH_ECCR_DATA_ECC_Msk                 /*!< Flash high-cycle data ECC fail */
10507 #define FLASH_ECCR_BK_ECC_Pos               (22U)
10508 #define FLASH_ECCR_BK_ECC_Msk               (0x1UL << FLASH_ECCR_BK_ECC_Pos)        /*!< 0x00400000 */
10509 #define FLASH_ECCR_BK_ECC                   FLASH_ECCR_BK_ECC_Msk                   /*!< ECC fail bank */
10510 #define FLASH_ECCR_SYSF_ECC_Pos             (23U)
10511 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00800000 */
10512 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk                 /*!< System Flash ECC fail */
10513 #define FLASH_ECCR_OTP_ECC_Pos              (24U)
10514 #define FLASH_ECCR_OTP_ECC_Msk              (0x1UL << FLASH_ECCR_OTP_ECC_Pos)       /*!< 0x01000000 */
10515 #define FLASH_ECCR_OTP_ECC                  FLASH_ECCR_OTP_ECC_Msk                  /*!< Flash OTP ECC fail */
10516 #define FLASH_ECCR_ECCIE_Pos                (25U)
10517 #define FLASH_ECCR_ECCIE_Msk                (0x1UL << FLASH_ECCR_ECCIE_Pos)         /*!< 0x02000000 */
10518 #define FLASH_ECCR_ECCIE                    FLASH_ECCR_ECCIE_Msk                    /*!< ECC correction interrupt enable */
10519 #define FLASH_ECCR_ECCC_Pos                 (30U)
10520 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
10521 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                     /*!< ECC correction */
10522 #define FLASH_ECCR_ECCD_Pos                 (31U)
10523 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
10524 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                     /*!< ECC detection */
10525 
10526 /*******************  Bits definition for FLASH_ECCDR register  ***************/
10527 #define FLASH_ECCDR_FAIL_DATA_Pos           (0U)
10528 #define FLASH_ECCDR_FAIL_DATA_Msk           (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
10529 #define FLASH_ECCDR_FAIL_DATA               FLASH_ECCDR_FAIL_DATA_Msk               /*!< ECC fail data */
10530 
10531 
10532 /******************************************************************************/
10533 /*                                                                            */
10534 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
10535 /*                                                                            */
10536 /******************************************************************************/
10537 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
10538 #define FMAC_X1BUFCFG_X1_BASE_Pos           (0U)
10539 #define FMAC_X1BUFCFG_X1_BASE_Msk           (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)   /*!< 0x000000FF */
10540 #define FMAC_X1BUFCFG_X1_BASE               FMAC_X1BUFCFG_X1_BASE_Msk               /*!< Base address of X1 buffer */
10541 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos       (8U)
10542 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk       (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */
10543 #define FMAC_X1BUFCFG_X1_BUF_SIZE           FMAC_X1BUFCFG_X1_BUF_SIZE_Msk           /*!< Allocated size of X1 buffer in 16-bit words */
10544 #define FMAC_X1BUFCFG_FULL_WM_Pos           (24U)
10545 #define FMAC_X1BUFCFG_FULL_WM_Msk           (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
10546 #define FMAC_X1BUFCFG_FULL_WM               FMAC_X1BUFCFG_FULL_WM_Msk               /*!< Watermark for buffer full flag */
10547 
10548 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
10549 #define FMAC_X2BUFCFG_X2_BASE_Pos           (0U)
10550 #define FMAC_X2BUFCFG_X2_BASE_Msk           (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)   /*!< 0x000000FF */
10551 #define FMAC_X2BUFCFG_X2_BASE               FMAC_X2BUFCFG_X2_BASE_Msk               /*!< Base address of X2 buffer */
10552 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos       (8U)
10553 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk       (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */
10554 #define FMAC_X2BUFCFG_X2_BUF_SIZE           FMAC_X2BUFCFG_X2_BUF_SIZE_Msk           /*!< Size of X2 buffer in 16-bit words */
10555 
10556 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
10557 #define FMAC_YBUFCFG_Y_BASE_Pos             (0U)
10558 #define FMAC_YBUFCFG_Y_BASE_Msk             (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)     /*!< 0x000000FF */
10559 #define FMAC_YBUFCFG_Y_BASE                 FMAC_YBUFCFG_Y_BASE_Msk                 /*!< Base address of Y buffer */
10560 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos         (8U)
10561 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk         (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
10562 #define FMAC_YBUFCFG_Y_BUF_SIZE             FMAC_YBUFCFG_Y_BUF_SIZE_Msk             /*!< Size of Y buffer in 16-bit words */
10563 #define FMAC_YBUFCFG_EMPTY_WM_Pos           (24U)
10564 #define FMAC_YBUFCFG_EMPTY_WM_Msk           (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
10565 #define FMAC_YBUFCFG_EMPTY_WM               FMAC_YBUFCFG_EMPTY_WM_Msk               /*!< Watermark for buffer empty flag */
10566 
10567 /******************  Bit definition for FMAC_PARAM register  ******************/
10568 #define FMAC_PARAM_P_Pos                    (0U)
10569 #define FMAC_PARAM_P_Msk                    (0xFFUL << FMAC_PARAM_P_Pos)            /*!< 0x000000FF */
10570 #define FMAC_PARAM_P                        FMAC_PARAM_P_Msk                        /*!< Input parameter P */
10571 #define FMAC_PARAM_Q_Pos                    (8U)
10572 #define FMAC_PARAM_Q_Msk                    (0xFFUL << FMAC_PARAM_Q_Pos)            /*!< 0x0000FF00 */
10573 #define FMAC_PARAM_Q                        FMAC_PARAM_Q_Msk                        /*!< Input parameter Q */
10574 #define FMAC_PARAM_R_Pos                    (16U)
10575 #define FMAC_PARAM_R_Msk                    (0xFFUL << FMAC_PARAM_R_Pos)            /*!< 0x00FF0000 */
10576 #define FMAC_PARAM_R                        FMAC_PARAM_R_Msk                        /*!< Input parameter R */
10577 #define FMAC_PARAM_FUNC_Pos                 (24U)
10578 #define FMAC_PARAM_FUNC_Msk                 (0x7FUL << FMAC_PARAM_FUNC_Pos)         /*!< 0x7F000000 */
10579 #define FMAC_PARAM_FUNC                     FMAC_PARAM_FUNC_Msk                     /*!< Function */
10580 #define FMAC_PARAM_FUNC_0                   (0x1UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
10581 #define FMAC_PARAM_FUNC_1                   (0x2UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
10582 #define FMAC_PARAM_FUNC_2                   (0x4UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
10583 #define FMAC_PARAM_FUNC_3                   (0x8UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
10584 #define FMAC_PARAM_FUNC_4                   (0x10UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x10000000 */
10585 #define FMAC_PARAM_FUNC_5                   (0x20UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x20000000 */
10586 #define FMAC_PARAM_FUNC_6                   (0x40UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x40000000 */
10587 #define FMAC_PARAM_START_Pos                (31U)
10588 #define FMAC_PARAM_START_Msk                (0x1UL << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
10589 #define FMAC_PARAM_START                    FMAC_PARAM_START_Msk                    /*!< Enable execution */
10590 
10591 /********************  Bit definition for FMAC_CR register  *******************/
10592 #define FMAC_CR_RIEN_Pos                    (0U)
10593 #define FMAC_CR_RIEN_Msk                    (0x1UL << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
10594 #define FMAC_CR_RIEN                        FMAC_CR_RIEN_Msk                        /*!< Enable read interrupt */
10595 #define FMAC_CR_WIEN_Pos                    (1U)
10596 #define FMAC_CR_WIEN_Msk                    (0x1UL << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
10597 #define FMAC_CR_WIEN                        FMAC_CR_WIEN_Msk                        /*!< Enable write interrupt */
10598 #define FMAC_CR_OVFLIEN_Pos                 (2U)
10599 #define FMAC_CR_OVFLIEN_Msk                 (0x1UL << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
10600 #define FMAC_CR_OVFLIEN                     FMAC_CR_OVFLIEN_Msk                     /*!< Enable overflow error interrupts */
10601 #define FMAC_CR_UNFLIEN_Pos                 (3U)
10602 #define FMAC_CR_UNFLIEN_Msk                 (0x1UL << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
10603 #define FMAC_CR_UNFLIEN                     FMAC_CR_UNFLIEN_Msk                     /*!< Enable underflow error interrupts */
10604 #define FMAC_CR_SATIEN_Pos                  (4U)
10605 #define FMAC_CR_SATIEN_Msk                  (0x1UL << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
10606 #define FMAC_CR_SATIEN                      FMAC_CR_SATIEN_Msk                      /*!< Enable saturation error interrupts */
10607 #define FMAC_CR_DMAREN_Pos                  (8U)
10608 #define FMAC_CR_DMAREN_Msk                  (0x1UL << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
10609 #define FMAC_CR_DMAREN                      FMAC_CR_DMAREN_Msk                      /*!< Enable DMA read channel requests */
10610 #define FMAC_CR_DMAWEN_Pos                  (9U)
10611 #define FMAC_CR_DMAWEN_Msk                  (0x1UL << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
10612 #define FMAC_CR_DMAWEN                      FMAC_CR_DMAWEN_Msk                      /*!< Enable DMA write channel requests */
10613 #define FMAC_CR_CLIPEN_Pos                  (15U)
10614 #define FMAC_CR_CLIPEN_Msk                  (0x1UL << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
10615 #define FMAC_CR_CLIPEN                      FMAC_CR_CLIPEN_Msk                      /*!< Enable clipping */
10616 #define FMAC_CR_RESET_Pos                   (16U)
10617 #define FMAC_CR_RESET_Msk                   (0x1UL << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
10618 #define FMAC_CR_RESET                       FMAC_CR_RESET_Msk                       /*!< Reset filter mathematical accelerator unit */
10619 
10620 /*******************  Bit definition for FMAC_SR register  ********************/
10621 #define FMAC_SR_YEMPTY_Pos                  (0U)
10622 #define FMAC_SR_YEMPTY_Msk                  (0x1UL << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
10623 #define FMAC_SR_YEMPTY                      FMAC_SR_YEMPTY_Msk                      /*!< Y buffer empty flag */
10624 #define FMAC_SR_X1FULL_Pos                  (1U)
10625 #define FMAC_SR_X1FULL_Msk                  (0x1UL << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
10626 #define FMAC_SR_X1FULL                      FMAC_SR_X1FULL_Msk                      /*!< X1 buffer full flag */
10627 #define FMAC_SR_OVFL_Pos                    (8U)
10628 #define FMAC_SR_OVFL_Msk                    (0x1UL << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
10629 #define FMAC_SR_OVFL                        FMAC_SR_OVFL_Msk                        /*!< Overflow error flag */
10630 #define FMAC_SR_UNFL_Pos                    (9U)
10631 #define FMAC_SR_UNFL_Msk                    (0x1UL << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
10632 #define FMAC_SR_UNFL                        FMAC_SR_UNFL_Msk                        /*!< Underflow error flag */
10633 #define FMAC_SR_SAT_Pos                     (10U)
10634 #define FMAC_SR_SAT_Msk                     (0x1UL << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
10635 #define FMAC_SR_SAT                         FMAC_SR_SAT_Msk                         /*!< Saturation error flag */
10636 
10637 /******************  Bit definition for FMAC_WDATA register  ******************/
10638 #define FMAC_WDATA_WDATA_Pos                (0U)
10639 #define FMAC_WDATA_WDATA_Msk                (0xFFFFUL << FMAC_WDATA_WDATA_Pos)      /*!< 0x0000FFFF */
10640 #define FMAC_WDATA_WDATA                    FMAC_WDATA_WDATA_Msk                    /*!< Write data */
10641 
10642 /******************  Bit definition for FMACX_RDATA register  *****************/
10643 #define FMAC_RDATA_RDATA_Pos                (0U)
10644 #define FMAC_RDATA_RDATA_Msk                (0xFFFFUL << FMAC_RDATA_RDATA_Pos)      /*!< 0x0000FFFF */
10645 #define FMAC_RDATA_RDATA                    FMAC_RDATA_RDATA_Msk                    /*!< Read data */
10646 
10647 
10648 /******************************************************************************/
10649 /*                                                                            */
10650 /*                          Flexible Memory Controller                        */
10651 /*                                                                            */
10652 /******************************************************************************/
10653 /******************  Bit definition for FMC_BCR1 register  *******************/
10654 #define FMC_BCR1_CCLKEN_Pos                 (20U)
10655 #define FMC_BCR1_CCLKEN_Msk                 (0x1UL << FMC_BCR1_CCLKEN_Pos)          /*!< 0x00100000 */
10656 #define FMC_BCR1_CCLKEN                     FMC_BCR1_CCLKEN_Msk                     /*!<Continuous clock enable    */
10657 #define FMC_BCR1_WFDIS_Pos                  (21U)
10658 #define FMC_BCR1_WFDIS_Msk                  (0x1UL << FMC_BCR1_WFDIS_Pos)           /*!< 0x00200000 */
10659 #define FMC_BCR1_WFDIS                      FMC_BCR1_WFDIS_Msk                      /*!<Write FIFO Disable         */
10660 #define FMC_BCR1_FMCEN_Pos                  (31U)
10661 #define FMC_BCR1_FMCEN_Msk                  (0x1UL << FMC_BCR1_FMCEN_Pos)           /*!< 0x80000000 */
10662 #define FMC_BCR1_FMCEN                      FMC_BCR1_FMCEN_Msk                      /*!<FMC controller Enable */
10663 
10664 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
10665 #define FMC_BCRx_MBKEN_Pos                  (0U)
10666 #define FMC_BCRx_MBKEN_Msk                  (0x1UL << FMC_BCRx_MBKEN_Pos)           /*!< 0x00000001 */
10667 #define FMC_BCRx_MBKEN                      FMC_BCRx_MBKEN_Msk                      /*!<Memory bank enable bit                 */
10668 #define FMC_BCRx_MUXEN_Pos                  (1U)
10669 #define FMC_BCRx_MUXEN_Msk                  (0x1UL << FMC_BCRx_MUXEN_Pos)           /*!< 0x00000002 */
10670 #define FMC_BCRx_MUXEN                      FMC_BCRx_MUXEN_Msk                      /*!<Address/data multiplexing enable bit   */
10671 #define FMC_BCRx_MTYP_Pos                   (2U)
10672 #define FMC_BCRx_MTYP_Msk                   (0x3UL << FMC_BCRx_MTYP_Pos)            /*!< 0x0000000C */
10673 #define FMC_BCRx_MTYP                       FMC_BCRx_MTYP_Msk                       /*!<MTYP[1:0] bits (Memory type)           */
10674 #define FMC_BCRx_MTYP_0                     (0x1UL << FMC_BCRx_MTYP_Pos)            /*!< 0x00000004 */
10675 #define FMC_BCRx_MTYP_1                     (0x2UL << FMC_BCRx_MTYP_Pos)            /*!< 0x00000008 */
10676 #define FMC_BCRx_MWID_Pos                   (4U)
10677 #define FMC_BCRx_MWID_Msk                   (0x3UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000030 */
10678 #define FMC_BCRx_MWID                       FMC_BCRx_MWID_Msk                       /*!<MWID[1:0] bits (Memory data bus width) */
10679 #define FMC_BCRx_MWID_0                     (0x1UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000010 */
10680 #define FMC_BCRx_MWID_1                     (0x2UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000020 */
10681 #define FMC_BCRx_FACCEN_Pos                 (6U)
10682 #define FMC_BCRx_FACCEN_Msk                 (0x1UL << FMC_BCRx_FACCEN_Pos)          /*!< 0x00000040 */
10683 #define FMC_BCRx_FACCEN                     FMC_BCRx_FACCEN_Msk                     /*!<Flash access enable        */
10684 #define FMC_BCRx_BURSTEN_Pos                (8U)
10685 #define FMC_BCRx_BURSTEN_Msk                (0x1UL << FMC_BCRx_BURSTEN_Pos)         /*!< 0x00000100 */
10686 #define FMC_BCRx_BURSTEN                    FMC_BCRx_BURSTEN_Msk                    /*!<Burst enable bit           */
10687 #define FMC_BCRx_WAITPOL_Pos                (9U)
10688 #define FMC_BCRx_WAITPOL_Msk                (0x1UL << FMC_BCRx_WAITPOL_Pos)         /*!< 0x00000200 */
10689 #define FMC_BCRx_WAITPOL                    FMC_BCRx_WAITPOL_Msk                    /*!<Wait signal polarity bit   */
10690 #define FMC_BCRx_WAITCFG_Pos                (11U)
10691 #define FMC_BCRx_WAITCFG_Msk                (0x1UL << FMC_BCRx_WAITCFG_Pos)         /*!< 0x00000800 */
10692 #define FMC_BCRx_WAITCFG                    FMC_BCRx_WAITCFG_Msk                    /*!<Wait timing configuration  */
10693 #define FMC_BCRx_WREN_Pos                   (12U)
10694 #define FMC_BCRx_WREN_Msk                   (0x1UL << FMC_BCRx_WREN_Pos)            /*!< 0x00001000 */
10695 #define FMC_BCRx_WREN                       FMC_BCRx_WREN_Msk                       /*!<Write enable bit           */
10696 #define FMC_BCRx_WAITEN_Pos                 (13U)
10697 #define FMC_BCRx_WAITEN_Msk                 (0x1UL << FMC_BCRx_WAITEN_Pos)          /*!< 0x00002000 */
10698 #define FMC_BCRx_WAITEN                     FMC_BCRx_WAITEN_Msk                     /*!<Wait enable bit            */
10699 #define FMC_BCRx_EXTMOD_Pos                 (14U)
10700 #define FMC_BCRx_EXTMOD_Msk                 (0x1UL << FMC_BCRx_EXTMOD_Pos)          /*!< 0x00004000 */
10701 #define FMC_BCRx_EXTMOD                     FMC_BCRx_EXTMOD_Msk                     /*!<Extended mode enable       */
10702 #define FMC_BCRx_ASYNCWAIT_Pos              (15U)
10703 #define FMC_BCRx_ASYNCWAIT_Msk              (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)       /*!< 0x00008000 */
10704 #define FMC_BCRx_ASYNCWAIT                  FMC_BCRx_ASYNCWAIT_Msk                  /*!<Asynchronous wait          */
10705 #define FMC_BCRx_CPSIZE_Pos                 (16U)
10706 #define FMC_BCRx_CPSIZE_Msk                 (0x7UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00070000 */
10707 #define FMC_BCRx_CPSIZE                     FMC_BCRx_CPSIZE_Msk                     /*!<PSIZE[2:0] bits CRAM Page Size */
10708 #define FMC_BCRx_CPSIZE_0                   (0x1UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00010000 */
10709 #define FMC_BCRx_CPSIZE_1                   (0x2UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00020000 */
10710 #define FMC_BCRx_CPSIZE_2                   (0x4UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00040000 */
10711 #define FMC_BCRx_CBURSTRW_Pos               (19U)
10712 #define FMC_BCRx_CBURSTRW_Msk               (0x1UL << FMC_BCRx_CBURSTRW_Pos)        /*!< 0x00080000 */
10713 #define FMC_BCRx_CBURSTRW                   FMC_BCRx_CBURSTRW_Msk                   /*!<Write burst enable         */
10714 #define FMC_BCRx_NBLSET_Pos                 (22U)
10715 #define FMC_BCRx_NBLSET_Msk                 (0x3UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00C00000 */
10716 #define FMC_BCRx_NBLSET                     FMC_BCRx_NBLSET_Msk                     /*!<Byte lane (NBL) setup      */
10717 #define FMC_BCRx_NBLSET_0                   (0x1UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00400000 */
10718 #define FMC_BCRx_NBLSET_1                   (0x2UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00800000 */
10719 
10720 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
10721 #define FMC_BTRx_ADDSET_Pos                 (0U)
10722 #define FMC_BTRx_ADDSET_Msk                 (0xFUL << FMC_BTRx_ADDSET_Pos)          /*!< 0x0000000F */
10723 #define FMC_BTRx_ADDSET                     FMC_BTRx_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
10724 #define FMC_BTRx_ADDSET_0                   (0x1UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000001 */
10725 #define FMC_BTRx_ADDSET_1                   (0x2UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000002 */
10726 #define FMC_BTRx_ADDSET_2                   (0x4UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000004 */
10727 #define FMC_BTRx_ADDSET_3                   (0x8UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000008 */
10728 #define FMC_BTRx_ADDHLD_Pos                 (4U)
10729 #define FMC_BTRx_ADDHLD_Msk                 (0xFUL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x000000F0 */
10730 #define FMC_BTRx_ADDHLD                     FMC_BTRx_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
10731 #define FMC_BTRx_ADDHLD_0                   (0x1UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000010 */
10732 #define FMC_BTRx_ADDHLD_1                   (0x2UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000020 */
10733 #define FMC_BTRx_ADDHLD_2                   (0x4UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000040 */
10734 #define FMC_BTRx_ADDHLD_3                   (0x8UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000080 */
10735 #define FMC_BTRx_DATAST_Pos                 (8U)
10736 #define FMC_BTRx_DATAST_Msk                 (0xFFUL << FMC_BTRx_DATAST_Pos)         /*!< 0x0000FF00 */
10737 #define FMC_BTRx_DATAST                     FMC_BTRx_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
10738 #define FMC_BTRx_DATAST_0                   (0x01UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000100 */
10739 #define FMC_BTRx_DATAST_1                   (0x02UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000200 */
10740 #define FMC_BTRx_DATAST_2                   (0x04UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000400 */
10741 #define FMC_BTRx_DATAST_3                   (0x08UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000800 */
10742 #define FMC_BTRx_DATAST_4                   (0x10UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00001000 */
10743 #define FMC_BTRx_DATAST_5                   (0x20UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00002000 */
10744 #define FMC_BTRx_DATAST_6                   (0x40UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00004000 */
10745 #define FMC_BTRx_DATAST_7                   (0x80UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00008000 */
10746 #define FMC_BTRx_BUSTURN_Pos                (16U)
10747 #define FMC_BTRx_BUSTURN_Msk                (0xFUL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x000F0000 */
10748 #define FMC_BTRx_BUSTURN                    FMC_BTRx_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10749 #define FMC_BTRx_BUSTURN_0                  (0x1UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00010000 */
10750 #define FMC_BTRx_BUSTURN_1                  (0x2UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00020000 */
10751 #define FMC_BTRx_BUSTURN_2                  (0x4UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00040000 */
10752 #define FMC_BTRx_BUSTURN_3                  (0x8UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00080000 */
10753 #define FMC_BTRx_CLKDIV_Pos                 (20U)
10754 #define FMC_BTRx_CLKDIV_Msk                 (0xFUL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00F00000 */
10755 #define FMC_BTRx_CLKDIV                     FMC_BTRx_CLKDIV_Msk                     /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10756 #define FMC_BTRx_CLKDIV_0                   (0x1UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00100000 */
10757 #define FMC_BTRx_CLKDIV_1                   (0x2UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00200000 */
10758 #define FMC_BTRx_CLKDIV_2                   (0x4UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00400000 */
10759 #define FMC_BTRx_CLKDIV_3                   (0x8UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00800000 */
10760 #define FMC_BTRx_DATLAT_Pos                 (24U)
10761 #define FMC_BTRx_DATLAT_Msk                 (0xFUL << FMC_BTRx_DATLAT_Pos)          /*!< 0x0F000000 */
10762 #define FMC_BTRx_DATLAT                     FMC_BTRx_DATLAT_Msk                     /*!<DATLA[3:0] bits (Data latency) */
10763 #define FMC_BTRx_DATLAT_0                   (0x1UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x01000000 */
10764 #define FMC_BTRx_DATLAT_1                   (0x2UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x02000000 */
10765 #define FMC_BTRx_DATLAT_2                   (0x4UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x04000000 */
10766 #define FMC_BTRx_DATLAT_3                   (0x8UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x08000000 */
10767 #define FMC_BTRx_ACCMOD_Pos                 (28U)
10768 #define FMC_BTRx_ACCMOD_Msk                 (0x3UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x30000000 */
10769 #define FMC_BTRx_ACCMOD                     FMC_BTRx_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
10770 #define FMC_BTRx_ACCMOD_0                   (0x1UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x10000000 */
10771 #define FMC_BTRx_ACCMOD_1                   (0x2UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x20000000 */
10772 #define FMC_BTRx_DATAHLD_Pos                (30U)
10773 #define FMC_BTRx_DATAHLD_Msk                (0x3UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0xC0000000 */
10774 #define FMC_BTRx_DATAHLD                    FMC_BTRx_DATAHLD_Msk                    /*!<DATAHLD[1:0] bits (Data hold phase duration) */
10775 #define FMC_BTRx_DATAHLD_0                  (0x1UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0x40000000 */
10776 #define FMC_BTRx_DATAHLD_1                  (0x2UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0x80000000 */
10777 
10778 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
10779 #define FMC_BWTRx_ADDSET_Pos                (0U)
10780 #define FMC_BWTRx_ADDSET_Msk                (0xFUL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x0000000F */
10781 #define FMC_BWTRx_ADDSET                    FMC_BWTRx_ADDSET_Msk                    /*!<ADDSET[3:0] bits (Address setup phase duration) */
10782 #define FMC_BWTRx_ADDSET_0                  (0x1UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000001 */
10783 #define FMC_BWTRx_ADDSET_1                  (0x2UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000002 */
10784 #define FMC_BWTRx_ADDSET_2                  (0x4UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000004 */
10785 #define FMC_BWTRx_ADDSET_3                  (0x8UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000008 */
10786 #define FMC_BWTRx_ADDHLD_Pos                (4U)
10787 #define FMC_BWTRx_ADDHLD_Msk                (0xFUL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x000000F0 */
10788 #define FMC_BWTRx_ADDHLD                    FMC_BWTRx_ADDHLD_Msk                    /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10789 #define FMC_BWTRx_ADDHLD_0                  (0x1UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000010 */
10790 #define FMC_BWTRx_ADDHLD_1                  (0x2UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000020 */
10791 #define FMC_BWTRx_ADDHLD_2                  (0x4UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000040 */
10792 #define FMC_BWTRx_ADDHLD_3                  (0x8UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000080 */
10793 #define FMC_BWTRx_DATAST_Pos                (8U)
10794 #define FMC_BWTRx_DATAST_Msk                (0xFFUL << FMC_BWTRx_DATAST_Pos)        /*!< 0x0000FF00 */
10795 #define FMC_BWTRx_DATAST                    FMC_BWTRx_DATAST_Msk                    /*!<DATAST [3:0] bits (Data-phase duration) */
10796 #define FMC_BWTRx_DATAST_0                  (0x01UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000100 */
10797 #define FMC_BWTRx_DATAST_1                  (0x02UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000200 */
10798 #define FMC_BWTRx_DATAST_2                  (0x04UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000400 */
10799 #define FMC_BWTRx_DATAST_3                  (0x08UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000800 */
10800 #define FMC_BWTRx_DATAST_4                  (0x10UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00001000 */
10801 #define FMC_BWTRx_DATAST_5                  (0x20UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00002000 */
10802 #define FMC_BWTRx_DATAST_6                  (0x40UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00004000 */
10803 #define FMC_BWTRx_DATAST_7                  (0x80UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00008000 */
10804 #define FMC_BWTRx_BUSTURN_Pos               (16U)
10805 #define FMC_BWTRx_BUSTURN_Msk               (0xFUL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x000F0000 */
10806 #define FMC_BWTRx_BUSTURN                   FMC_BWTRx_BUSTURN_Msk                   /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10807 #define FMC_BWTRx_BUSTURN_0                 (0x1UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00010000 */
10808 #define FMC_BWTRx_BUSTURN_1                 (0x2UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00020000 */
10809 #define FMC_BWTRx_BUSTURN_2                 (0x4UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00040000 */
10810 #define FMC_BWTRx_BUSTURN_3                 (0x8UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00080000 */
10811 #define FMC_BWTRx_ACCMOD_Pos                (28U)
10812 #define FMC_BWTRx_ACCMOD_Msk                (0x3UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x30000000 */
10813 #define FMC_BWTRx_ACCMOD                    FMC_BWTRx_ACCMOD_Msk                    /*!<ACCMOD[1:0] bits (Access mode) */
10814 #define FMC_BWTRx_ACCMOD_0                  (0x1UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x10000000 */
10815 #define FMC_BWTRx_ACCMOD_1                  (0x2UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x20000000 */
10816 #define FMC_BWTRx_DATAHLD_Pos               (30U)
10817 #define FMC_BWTRx_DATAHLD_Msk               (0x3UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0xC0000000 */
10818 #define FMC_BWTRx_DATAHLD                   FMC_BWTRx_DATAHLD_Msk                   /*!<DATAHLD[1:0] bits (Data hold phase duration) */
10819 #define FMC_BWTRx_DATAHLD_0                 (0x1UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0x40000000 */
10820 #define FMC_BWTRx_DATAHLD_1                 (0x2UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0x80000000 */
10821 
10822 /******************  Bit definition for FMC_PCSCNTR register ******************/
10823 #define FMC_PCSCNTR_CSCOUNT_Pos             (0U)
10824 #define FMC_PCSCNTR_CSCOUNT_Msk             (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos)   /*!< 0x0000FFFF */
10825 #define FMC_PCSCNTR_CSCOUNT                 FMC_PCSCNTR_CSCOUNT_Msk                 /*!<CSCOUNT[15:0] bits (Chip select counter) */
10826 #define FMC_PCSCNTR_CNTB1EN_Pos             (16U)
10827 #define FMC_PCSCNTR_CNTB1EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos)      /*!< 0x00010000 */
10828 #define FMC_PCSCNTR_CNTB1EN                 FMC_PCSCNTR_CNTB1EN_Msk                 /*!<Counter PSRAM/NOR Bank1_1 enable */
10829 #define FMC_PCSCNTR_CNTB2EN_Pos             (17U)
10830 #define FMC_PCSCNTR_CNTB2EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos)      /*!< 0x00020000 */
10831 #define FMC_PCSCNTR_CNTB2EN                 FMC_PCSCNTR_CNTB2EN_Msk                 /*!<Counter PSRAM/NOR Bank1_2 enable */
10832 #define FMC_PCSCNTR_CNTB3EN_Pos             (18U)
10833 #define FMC_PCSCNTR_CNTB3EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos)      /*!< 0x00040000 */
10834 #define FMC_PCSCNTR_CNTB3EN                 FMC_PCSCNTR_CNTB3EN_Msk                 /*!<Counter PSRAM/NOR Bank1_3 enable */
10835 #define FMC_PCSCNTR_CNTB4EN_Pos             (19U)
10836 #define FMC_PCSCNTR_CNTB4EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos)      /*!< 0x00080000 */
10837 #define FMC_PCSCNTR_CNTB4EN                 FMC_PCSCNTR_CNTB4EN_Msk                 /*!<Counter PSRAM/NOR Bank1_4 enable */
10838 
10839 /******************  Bit definition for FMC_PCR register  *******************/
10840 #define FMC_PCR_PWAITEN_Pos                 (1U)
10841 #define FMC_PCR_PWAITEN_Msk                 (0x1UL << FMC_PCR_PWAITEN_Pos)          /*!< 0x00000002 */
10842 #define FMC_PCR_PWAITEN                     FMC_PCR_PWAITEN_Msk                     /*!<Wait feature enable bit                   */
10843 #define FMC_PCR_PBKEN_Pos                   (2U)
10844 #define FMC_PCR_PBKEN_Msk                   (0x1UL << FMC_PCR_PBKEN_Pos)            /*!< 0x00000004 */
10845 #define FMC_PCR_PBKEN                       FMC_PCR_PBKEN_Msk                       /*!<NAND Flash memory bank enable bit */
10846 #define FMC_PCR_PTYP_Pos                    (3U)
10847 #define FMC_PCR_PTYP_Msk                    (0x1UL << FMC_PCR_PTYP_Pos)             /*!< 0x00000008 */
10848 #define FMC_PCR_PTYP                        FMC_PCR_PTYP_Msk                        /*!<Memory type                               */
10849 #define FMC_PCR_PWID_Pos                    (4U)
10850 #define FMC_PCR_PWID_Msk                    (0x3UL << FMC_PCR_PWID_Pos)             /*!< 0x00000030 */
10851 #define FMC_PCR_PWID                        FMC_PCR_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
10852 #define FMC_PCR_PWID_0                      (0x1UL << FMC_PCR_PWID_Pos)             /*!< 0x00000010 */
10853 #define FMC_PCR_PWID_1                      (0x2UL << FMC_PCR_PWID_Pos)             /*!< 0x00000020 */
10854 #define FMC_PCR_ECCEN_Pos                   (6U)
10855 #define FMC_PCR_ECCEN_Msk                   (0x1UL << FMC_PCR_ECCEN_Pos)            /*!< 0x00000040 */
10856 #define FMC_PCR_ECCEN                       FMC_PCR_ECCEN_Msk                       /*!<ECC computation logic enable bit          */
10857 #define FMC_PCR_TCLR_Pos                    (9U)
10858 #define FMC_PCR_TCLR_Msk                    (0xFUL << FMC_PCR_TCLR_Pos)             /*!< 0x00001E00 */
10859 #define FMC_PCR_TCLR                        FMC_PCR_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay)          */
10860 #define FMC_PCR_TCLR_0                      (0x1UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000200 */
10861 #define FMC_PCR_TCLR_1                      (0x2UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000400 */
10862 #define FMC_PCR_TCLR_2                      (0x4UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000800 */
10863 #define FMC_PCR_TCLR_3                      (0x8UL << FMC_PCR_TCLR_Pos)             /*!< 0x00001000 */
10864 #define FMC_PCR_TAR_Pos                     (13U)
10865 #define FMC_PCR_TAR_Msk                     (0xFUL << FMC_PCR_TAR_Pos)              /*!< 0x0001E000 */
10866 #define FMC_PCR_TAR                         FMC_PCR_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay)           */
10867 #define FMC_PCR_TAR_0                       (0x1UL << FMC_PCR_TAR_Pos)              /*!< 0x00002000 */
10868 #define FMC_PCR_TAR_1                       (0x2UL << FMC_PCR_TAR_Pos)              /*!< 0x00004000 */
10869 #define FMC_PCR_TAR_2                       (0x4UL << FMC_PCR_TAR_Pos)              /*!< 0x00008000 */
10870 #define FMC_PCR_TAR_3                       (0x8UL << FMC_PCR_TAR_Pos)              /*!< 0x00010000 */
10871 #define FMC_PCR_ECCPS_Pos                   (17U)
10872 #define FMC_PCR_ECCPS_Msk                   (0x7UL << FMC_PCR_ECCPS_Pos)            /*!< 0x000E0000 */
10873 #define FMC_PCR_ECCPS                       FMC_PCR_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size)           */
10874 #define FMC_PCR_ECCPS_0                     (0x1UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00020000 */
10875 #define FMC_PCR_ECCPS_1                     (0x2UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00040000 */
10876 #define FMC_PCR_ECCPS_2                     (0x4UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00080000 */
10877 
10878 /*******************  Bit definition for FMC_SR register  *******************/
10879 #define FMC_SR_IRS_Pos                      (0U)
10880 #define FMC_SR_IRS_Msk                      (0x1UL << FMC_SR_IRS_Pos)               /*!< 0x00000001 */
10881 #define FMC_SR_IRS                          FMC_SR_IRS_Msk                          /*!<Interrupt Rising Edge status                */
10882 #define FMC_SR_ILS_Pos                      (1U)
10883 #define FMC_SR_ILS_Msk                      (0x1UL << FMC_SR_ILS_Pos)               /*!< 0x00000002 */
10884 #define FMC_SR_ILS                          FMC_SR_ILS_Msk                          /*!<Interrupt Level status                      */
10885 #define FMC_SR_IFS_Pos                      (2U)
10886 #define FMC_SR_IFS_Msk                      (0x1UL << FMC_SR_IFS_Pos)               /*!< 0x00000004 */
10887 #define FMC_SR_IFS                          FMC_SR_IFS_Msk                          /*!<Interrupt Falling Edge status               */
10888 #define FMC_SR_IREN_Pos                     (3U)
10889 #define FMC_SR_IREN_Msk                     (0x1UL << FMC_SR_IREN_Pos)              /*!< 0x00000008 */
10890 #define FMC_SR_IREN                         FMC_SR_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
10891 #define FMC_SR_ILEN_Pos                     (4U)
10892 #define FMC_SR_ILEN_Msk                     (0x1UL << FMC_SR_ILEN_Pos)              /*!< 0x00000010 */
10893 #define FMC_SR_ILEN                         FMC_SR_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
10894 #define FMC_SR_IFEN_Pos                     (5U)
10895 #define FMC_SR_IFEN_Msk                     (0x1UL << FMC_SR_IFEN_Pos)              /*!< 0x00000020 */
10896 #define FMC_SR_IFEN                         FMC_SR_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
10897 #define FMC_SR_FEMPT_Pos                    (6U)
10898 #define FMC_SR_FEMPT_Msk                    (0x1UL << FMC_SR_FEMPT_Pos)             /*!< 0x00000040 */
10899 #define FMC_SR_FEMPT                        FMC_SR_FEMPT_Msk                        /*!<FIFO empty                                  */
10900 
10901 /******************  Bit definition for FMC_PMEM register  ******************/
10902 #define FMC_PMEM_MEMSET_Pos                 (0U)
10903 #define FMC_PMEM_MEMSET_Msk                 (0xFFUL << FMC_PMEM_MEMSET_Pos)         /*!< 0x000000FF */
10904 #define FMC_PMEM_MEMSET                     FMC_PMEM_MEMSET_Msk                     /*!<MEMSET[7:0] bits (Common memory setup time) */
10905 #define FMC_PMEM_MEMSET_0                   (0x01UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000001 */
10906 #define FMC_PMEM_MEMSET_1                   (0x02UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000002 */
10907 #define FMC_PMEM_MEMSET_2                   (0x04UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000004 */
10908 #define FMC_PMEM_MEMSET_3                   (0x08UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000008 */
10909 #define FMC_PMEM_MEMSET_4                   (0x10UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000010 */
10910 #define FMC_PMEM_MEMSET_5                   (0x20UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000020 */
10911 #define FMC_PMEM_MEMSET_6                   (0x40UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000040 */
10912 #define FMC_PMEM_MEMSET_7                   (0x80UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000080 */
10913 #define FMC_PMEM_MEMWAIT_Pos                (8U)
10914 #define FMC_PMEM_MEMWAIT_Msk                (0xFFUL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x0000FF00 */
10915 #define FMC_PMEM_MEMWAIT                    FMC_PMEM_MEMWAIT_Msk                    /*!<MEMWAIT[7:0] bits (Common memory wait time) */
10916 #define FMC_PMEM_MEMWAIT_0                  (0x01UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000100 */
10917 #define FMC_PMEM_MEMWAIT_1                  (0x02UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000200 */
10918 #define FMC_PMEM_MEMWAIT_2                  (0x04UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000400 */
10919 #define FMC_PMEM_MEMWAIT_3                  (0x08UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000800 */
10920 #define FMC_PMEM_MEMWAIT_4                  (0x10UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00001000 */
10921 #define FMC_PMEM_MEMWAIT_5                  (0x20UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00002000 */
10922 #define FMC_PMEM_MEMWAIT_6                  (0x40UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00004000 */
10923 #define FMC_PMEM_MEMWAIT_7                  (0x80UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00008000 */
10924 #define FMC_PMEM_MEMHOLD_Pos                (16U)
10925 #define FMC_PMEM_MEMHOLD_Msk                (0xFFUL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00FF0000 */
10926 #define FMC_PMEM_MEMHOLD                    FMC_PMEM_MEMHOLD_Msk                    /*!<MEMHOLD[7:0] bits (Common memory hold time) */
10927 #define FMC_PMEM_MEMHOLD_0                  (0x01UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00010000 */
10928 #define FMC_PMEM_MEMHOLD_1                  (0x02UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00020000 */
10929 #define FMC_PMEM_MEMHOLD_2                  (0x04UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00040000 */
10930 #define FMC_PMEM_MEMHOLD_3                  (0x08UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00080000 */
10931 #define FMC_PMEM_MEMHOLD_4                  (0x10UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00100000 */
10932 #define FMC_PMEM_MEMHOLD_5                  (0x20UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00200000 */
10933 #define FMC_PMEM_MEMHOLD_6                  (0x40UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00400000 */
10934 #define FMC_PMEM_MEMHOLD_7                  (0x80UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00800000 */
10935 #define FMC_PMEM_MEMHIZ_Pos                 (24U)
10936 #define FMC_PMEM_MEMHIZ_Msk                 (0xFFUL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0xFF000000 */
10937 #define FMC_PMEM_MEMHIZ                     FMC_PMEM_MEMHIZ_Msk                     /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
10938 #define FMC_PMEM_MEMHIZ_0                   (0x01UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x01000000 */
10939 #define FMC_PMEM_MEMHIZ_1                   (0x02UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x02000000 */
10940 #define FMC_PMEM_MEMHIZ_2                   (0x04UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x04000000 */
10941 #define FMC_PMEM_MEMHIZ_3                   (0x08UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x08000000 */
10942 #define FMC_PMEM_MEMHIZ_4                   (0x10UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x10000000 */
10943 #define FMC_PMEM_MEMHIZ_5                   (0x20UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x20000000 */
10944 #define FMC_PMEM_MEMHIZ_6                   (0x40UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x40000000 */
10945 #define FMC_PMEM_MEMHIZ_7                   (0x80UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x80000000 */
10946 
10947 /******************  Bit definition for FMC_PATT register  ******************/
10948 #define FMC_PATT_ATTSET_Pos                 (0U)
10949 #define FMC_PATT_ATTSET_Msk                 (0xFFUL << FMC_PATT_ATTSET_Pos)         /*!< 0x000000FF */
10950 #define FMC_PATT_ATTSET                     FMC_PATT_ATTSET_Msk                     /*!<ATTSET[7:0] bits (Attribute memory setup time) */
10951 #define FMC_PATT_ATTSET_0                   (0x01UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000001 */
10952 #define FMC_PATT_ATTSET_1                   (0x02UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000002 */
10953 #define FMC_PATT_ATTSET_2                   (0x04UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000004 */
10954 #define FMC_PATT_ATTSET_3                   (0x08UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000008 */
10955 #define FMC_PATT_ATTSET_4                   (0x10UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000010 */
10956 #define FMC_PATT_ATTSET_5                   (0x20UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000020 */
10957 #define FMC_PATT_ATTSET_6                   (0x40UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000040 */
10958 #define FMC_PATT_ATTSET_7                   (0x80UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000080 */
10959 #define FMC_PATT_ATTWAIT_Pos                (8U)
10960 #define FMC_PATT_ATTWAIT_Msk                (0xFFUL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x0000FF00 */
10961 #define FMC_PATT_ATTWAIT                    FMC_PATT_ATTWAIT_Msk                    /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
10962 #define FMC_PATT_ATTWAIT_0                  (0x01UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000100 */
10963 #define FMC_PATT_ATTWAIT_1                  (0x02UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000200 */
10964 #define FMC_PATT_ATTWAIT_2                  (0x04UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000400 */
10965 #define FMC_PATT_ATTWAIT_3                  (0x08UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000800 */
10966 #define FMC_PATT_ATTWAIT_4                  (0x10UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00001000 */
10967 #define FMC_PATT_ATTWAIT_5                  (0x20UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00002000 */
10968 #define FMC_PATT_ATTWAIT_6                  (0x40UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00004000 */
10969 #define FMC_PATT_ATTWAIT_7                  (0x80UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00008000 */
10970 #define FMC_PATT_ATTHOLD_Pos                (16U)
10971 #define FMC_PATT_ATTHOLD_Msk                (0xFFUL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00FF0000 */
10972 #define FMC_PATT_ATTHOLD                    FMC_PATT_ATTHOLD_Msk                    /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
10973 #define FMC_PATT_ATTHOLD_0                  (0x01UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00010000 */
10974 #define FMC_PATT_ATTHOLD_1                  (0x02UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00020000 */
10975 #define FMC_PATT_ATTHOLD_2                  (0x04UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00040000 */
10976 #define FMC_PATT_ATTHOLD_3                  (0x08UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00080000 */
10977 #define FMC_PATT_ATTHOLD_4                  (0x10UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00100000 */
10978 #define FMC_PATT_ATTHOLD_5                  (0x20UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00200000 */
10979 #define FMC_PATT_ATTHOLD_6                  (0x40UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00400000 */
10980 #define FMC_PATT_ATTHOLD_7                  (0x80UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00800000 */
10981 #define FMC_PATT_ATTHIZ_Pos                 (24U)
10982 #define FMC_PATT_ATTHIZ_Msk                 (0xFFUL << FMC_PATT_ATTHIZ_Pos)         /*!< 0xFF000000 */
10983 #define FMC_PATT_ATTHIZ                     FMC_PATT_ATTHIZ_Msk                     /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
10984 #define FMC_PATT_ATTHIZ_0                   (0x01UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x01000000 */
10985 #define FMC_PATT_ATTHIZ_1                   (0x02UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x02000000 */
10986 #define FMC_PATT_ATTHIZ_2                   (0x04UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x04000000 */
10987 #define FMC_PATT_ATTHIZ_3                   (0x08UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x08000000 */
10988 #define FMC_PATT_ATTHIZ_4                   (0x10UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x10000000 */
10989 #define FMC_PATT_ATTHIZ_5                   (0x20UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x20000000 */
10990 #define FMC_PATT_ATTHIZ_6                   (0x40UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x40000000 */
10991 #define FMC_PATT_ATTHIZ_7                   (0x80UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x80000000 */
10992 
10993 /******************  Bit definition for FMC_ECCR3 register  ******************/
10994 #define FMC_ECCR3_ECC3_Pos                  (0U)
10995 #define FMC_ECCR3_ECC3_Msk                  (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)    /*!< 0xFFFFFFFF */
10996 #define FMC_ECCR3_ECC3                      FMC_ECCR3_ECC3_Msk                      /*!<ECC result */
10997 
10998 /******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
10999 #define FMC_SDCRx_NC_Pos           (0U)
11000 #define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
11001 #define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
11002 #define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
11003 #define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
11004 
11005 #define FMC_SDCRx_NR_Pos           (2U)
11006 #define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
11007 #define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
11008 #define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
11009 #define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
11010 
11011 #define FMC_SDCRx_MWID_Pos         (4U)
11012 #define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
11013 #define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
11014 #define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
11015 #define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
11016 
11017 #define FMC_SDCRx_NB_Pos           (6U)
11018 #define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
11019 #define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
11020 
11021 #define FMC_SDCRx_CAS_Pos          (7U)
11022 #define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
11023 #define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
11024 #define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
11025 #define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
11026 
11027 #define FMC_SDCRx_WP_Pos           (9U)
11028 #define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
11029 #define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
11030 
11031 #define FMC_SDCRx_SDCLK_Pos        (10U)
11032 #define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
11033 #define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
11034 #define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
11035 #define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
11036 
11037 #define FMC_SDCRx_RBURST_Pos       (12U)
11038 #define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
11039 #define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
11040 
11041 #define FMC_SDCRx_RPIPE_Pos        (13U)
11042 #define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
11043 #define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
11044 #define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
11045 #define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
11046 
11047 /******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
11048 #define FMC_SDTRx_TMRD_Pos         (0U)
11049 #define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
11050 #define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
11051 #define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
11052 #define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
11053 #define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
11054 #define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
11055 
11056 #define FMC_SDTRx_TXSR_Pos         (4U)
11057 #define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
11058 #define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
11059 #define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
11060 #define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
11061 #define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
11062 #define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
11063 
11064 #define FMC_SDTRx_TRAS_Pos         (8U)
11065 #define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
11066 #define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
11067 #define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
11068 #define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
11069 #define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
11070 #define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
11071 
11072 #define FMC_SDTRx_TRC_Pos          (12U)
11073 #define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
11074 #define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
11075 #define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
11076 #define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
11077 #define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
11078 
11079 #define FMC_SDTRx_TWR_Pos          (16U)
11080 #define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
11081 #define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
11082 #define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
11083 #define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
11084 #define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
11085 
11086 #define FMC_SDTRx_TRP_Pos          (20U)
11087 #define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
11088 #define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
11089 #define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
11090 #define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
11091 #define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
11092 
11093 #define FMC_SDTRx_TRCD_Pos         (24U)
11094 #define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
11095 #define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
11096 #define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
11097 #define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
11098 #define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
11099 
11100 /******************  Bit definition for FMC_SDCMR register  ******************/
11101 #define FMC_SDCMR_MODE_Pos         (0U)
11102 #define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
11103 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
11104 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
11105 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
11106 #define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
11107 
11108 #define FMC_SDCMR_CTB2_Pos         (3U)
11109 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
11110 #define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
11111 
11112 #define FMC_SDCMR_CTB1_Pos         (4U)
11113 #define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
11114 #define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
11115 
11116 #define FMC_SDCMR_NRFS_Pos         (5U)
11117 #define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
11118 #define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
11119 #define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
11120 #define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
11121 #define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
11122 #define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
11123 
11124 #define FMC_SDCMR_MRD_Pos          (9U)
11125 #define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
11126 #define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
11127 
11128 /******************  Bit definition for FMC_SDRTR register  ******************/
11129 #define FMC_SDRTR_CRE_Pos          (0U)
11130 #define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
11131 #define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
11132 
11133 #define FMC_SDRTR_COUNT_Pos        (1U)
11134 #define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
11135 #define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
11136 
11137 #define FMC_SDRTR_REIE_Pos         (14U)
11138 #define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
11139 #define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */
11140 
11141 /******************  Bit definition for FMC_SDSR register  ******************/
11142 #define FMC_SDSR_RE_Pos            (0U)
11143 #define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
11144 #define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
11145 
11146 #define FMC_SDSR_MODES1_Pos        (1U)
11147 #define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
11148 #define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
11149 #define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
11150 #define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
11151 
11152 #define FMC_SDSR_MODES2_Pos        (3U)
11153 #define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
11154 #define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
11155 #define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
11156 #define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
11157 
11158 /******************************************************************************/
11159 /*                                                                            */
11160 /*                       General Purpose IOs (GPIO)                           */
11161 /*                                                                            */
11162 /******************************************************************************/
11163 /******************  Bits definition for GPIO_MODER register  *****************/
11164 #define GPIO_MODER_MODE0_Pos                (0U)
11165 #define GPIO_MODER_MODE0_Msk                (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
11166 #define GPIO_MODER_MODE0                    GPIO_MODER_MODE0_Msk
11167 #define GPIO_MODER_MODE0_0                  (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
11168 #define GPIO_MODER_MODE0_1                  (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
11169 #define GPIO_MODER_MODE1_Pos                (2U)
11170 #define GPIO_MODER_MODE1_Msk                (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
11171 #define GPIO_MODER_MODE1                    GPIO_MODER_MODE1_Msk
11172 #define GPIO_MODER_MODE1_0                  (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
11173 #define GPIO_MODER_MODE1_1                  (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
11174 #define GPIO_MODER_MODE2_Pos                (4U)
11175 #define GPIO_MODER_MODE2_Msk                (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
11176 #define GPIO_MODER_MODE2                    GPIO_MODER_MODE2_Msk
11177 #define GPIO_MODER_MODE2_0                  (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
11178 #define GPIO_MODER_MODE2_1                  (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
11179 #define GPIO_MODER_MODE3_Pos                (6U)
11180 #define GPIO_MODER_MODE3_Msk                (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
11181 #define GPIO_MODER_MODE3                    GPIO_MODER_MODE3_Msk
11182 #define GPIO_MODER_MODE3_0                  (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
11183 #define GPIO_MODER_MODE3_1                  (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
11184 #define GPIO_MODER_MODE4_Pos                (8U)
11185 #define GPIO_MODER_MODE4_Msk                (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
11186 #define GPIO_MODER_MODE4                    GPIO_MODER_MODE4_Msk
11187 #define GPIO_MODER_MODE4_0                  (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
11188 #define GPIO_MODER_MODE4_1                  (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
11189 #define GPIO_MODER_MODE5_Pos                (10U)
11190 #define GPIO_MODER_MODE5_Msk                (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
11191 #define GPIO_MODER_MODE5                    GPIO_MODER_MODE5_Msk
11192 #define GPIO_MODER_MODE5_0                  (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
11193 #define GPIO_MODER_MODE5_1                  (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
11194 #define GPIO_MODER_MODE6_Pos                (12U)
11195 #define GPIO_MODER_MODE6_Msk                (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
11196 #define GPIO_MODER_MODE6                    GPIO_MODER_MODE6_Msk
11197 #define GPIO_MODER_MODE6_0                  (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
11198 #define GPIO_MODER_MODE6_1                  (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
11199 #define GPIO_MODER_MODE7_Pos                (14U)
11200 #define GPIO_MODER_MODE7_Msk                (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
11201 #define GPIO_MODER_MODE7                    GPIO_MODER_MODE7_Msk
11202 #define GPIO_MODER_MODE7_0                  (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
11203 #define GPIO_MODER_MODE7_1                  (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
11204 #define GPIO_MODER_MODE8_Pos                (16U)
11205 #define GPIO_MODER_MODE8_Msk                (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
11206 #define GPIO_MODER_MODE8                    GPIO_MODER_MODE8_Msk
11207 #define GPIO_MODER_MODE8_0                  (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
11208 #define GPIO_MODER_MODE8_1                  (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
11209 #define GPIO_MODER_MODE9_Pos                (18U)
11210 #define GPIO_MODER_MODE9_Msk                (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
11211 #define GPIO_MODER_MODE9                    GPIO_MODER_MODE9_Msk
11212 #define GPIO_MODER_MODE9_0                  (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
11213 #define GPIO_MODER_MODE9_1                  (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
11214 #define GPIO_MODER_MODE10_Pos               (20U)
11215 #define GPIO_MODER_MODE10_Msk               (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
11216 #define GPIO_MODER_MODE10                   GPIO_MODER_MODE10_Msk
11217 #define GPIO_MODER_MODE10_0                 (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
11218 #define GPIO_MODER_MODE10_1                 (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
11219 #define GPIO_MODER_MODE11_Pos               (22U)
11220 #define GPIO_MODER_MODE11_Msk               (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
11221 #define GPIO_MODER_MODE11                   GPIO_MODER_MODE11_Msk
11222 #define GPIO_MODER_MODE11_0                 (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
11223 #define GPIO_MODER_MODE11_1                 (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
11224 #define GPIO_MODER_MODE12_Pos               (24U)
11225 #define GPIO_MODER_MODE12_Msk               (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
11226 #define GPIO_MODER_MODE12                   GPIO_MODER_MODE12_Msk
11227 #define GPIO_MODER_MODE12_0                 (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
11228 #define GPIO_MODER_MODE12_1                 (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
11229 #define GPIO_MODER_MODE13_Pos               (26U)
11230 #define GPIO_MODER_MODE13_Msk               (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
11231 #define GPIO_MODER_MODE13                   GPIO_MODER_MODE13_Msk
11232 #define GPIO_MODER_MODE13_0                 (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
11233 #define GPIO_MODER_MODE13_1                 (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
11234 #define GPIO_MODER_MODE14_Pos               (28U)
11235 #define GPIO_MODER_MODE14_Msk               (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
11236 #define GPIO_MODER_MODE14                   GPIO_MODER_MODE14_Msk
11237 #define GPIO_MODER_MODE14_0                 (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
11238 #define GPIO_MODER_MODE14_1                 (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
11239 #define GPIO_MODER_MODE15_Pos               (30U)
11240 #define GPIO_MODER_MODE15_Msk               (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
11241 #define GPIO_MODER_MODE15                   GPIO_MODER_MODE15_Msk
11242 #define GPIO_MODER_MODE15_0                 (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
11243 #define GPIO_MODER_MODE15_1                 (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
11244 
11245 /******************  Bits definition for GPIO_OTYPER register  ****************/
11246 #define GPIO_OTYPER_OT0_Pos                 (0U)
11247 #define GPIO_OTYPER_OT0_Msk                 (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
11248 #define GPIO_OTYPER_OT0                     GPIO_OTYPER_OT0_Msk
11249 #define GPIO_OTYPER_OT1_Pos                 (1U)
11250 #define GPIO_OTYPER_OT1_Msk                 (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
11251 #define GPIO_OTYPER_OT1                     GPIO_OTYPER_OT1_Msk
11252 #define GPIO_OTYPER_OT2_Pos                 (2U)
11253 #define GPIO_OTYPER_OT2_Msk                 (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
11254 #define GPIO_OTYPER_OT2                     GPIO_OTYPER_OT2_Msk
11255 #define GPIO_OTYPER_OT3_Pos                 (3U)
11256 #define GPIO_OTYPER_OT3_Msk                 (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
11257 #define GPIO_OTYPER_OT3                     GPIO_OTYPER_OT3_Msk
11258 #define GPIO_OTYPER_OT4_Pos                 (4U)
11259 #define GPIO_OTYPER_OT4_Msk                 (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
11260 #define GPIO_OTYPER_OT4                     GPIO_OTYPER_OT4_Msk
11261 #define GPIO_OTYPER_OT5_Pos                 (5U)
11262 #define GPIO_OTYPER_OT5_Msk                 (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
11263 #define GPIO_OTYPER_OT5                     GPIO_OTYPER_OT5_Msk
11264 #define GPIO_OTYPER_OT6_Pos                 (6U)
11265 #define GPIO_OTYPER_OT6_Msk                 (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
11266 #define GPIO_OTYPER_OT6                     GPIO_OTYPER_OT6_Msk
11267 #define GPIO_OTYPER_OT7_Pos                 (7U)
11268 #define GPIO_OTYPER_OT7_Msk                 (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
11269 #define GPIO_OTYPER_OT7                     GPIO_OTYPER_OT7_Msk
11270 #define GPIO_OTYPER_OT8_Pos                 (8U)
11271 #define GPIO_OTYPER_OT8_Msk                 (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
11272 #define GPIO_OTYPER_OT8                     GPIO_OTYPER_OT8_Msk
11273 #define GPIO_OTYPER_OT9_Pos                 (9U)
11274 #define GPIO_OTYPER_OT9_Msk                 (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
11275 #define GPIO_OTYPER_OT9                     GPIO_OTYPER_OT9_Msk
11276 #define GPIO_OTYPER_OT10_Pos                (10U)
11277 #define GPIO_OTYPER_OT10_Msk                (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
11278 #define GPIO_OTYPER_OT10                    GPIO_OTYPER_OT10_Msk
11279 #define GPIO_OTYPER_OT11_Pos                (11U)
11280 #define GPIO_OTYPER_OT11_Msk                (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
11281 #define GPIO_OTYPER_OT11                    GPIO_OTYPER_OT11_Msk
11282 #define GPIO_OTYPER_OT12_Pos                (12U)
11283 #define GPIO_OTYPER_OT12_Msk                (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
11284 #define GPIO_OTYPER_OT12                    GPIO_OTYPER_OT12_Msk
11285 #define GPIO_OTYPER_OT13_Pos                (13U)
11286 #define GPIO_OTYPER_OT13_Msk                (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
11287 #define GPIO_OTYPER_OT13                    GPIO_OTYPER_OT13_Msk
11288 #define GPIO_OTYPER_OT14_Pos                (14U)
11289 #define GPIO_OTYPER_OT14_Msk                (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
11290 #define GPIO_OTYPER_OT14                    GPIO_OTYPER_OT14_Msk
11291 #define GPIO_OTYPER_OT15_Pos                (15U)
11292 #define GPIO_OTYPER_OT15_Msk                (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
11293 #define GPIO_OTYPER_OT15                    GPIO_OTYPER_OT15_Msk
11294 
11295 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
11296 #define GPIO_OSPEEDR_OSPEED0_Pos            (0U)
11297 #define GPIO_OSPEEDR_OSPEED0_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
11298 #define GPIO_OSPEEDR_OSPEED0                GPIO_OSPEEDR_OSPEED0_Msk
11299 #define GPIO_OSPEEDR_OSPEED0_0              (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
11300 #define GPIO_OSPEEDR_OSPEED0_1              (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
11301 #define GPIO_OSPEEDR_OSPEED1_Pos            (2U)
11302 #define GPIO_OSPEEDR_OSPEED1_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
11303 #define GPIO_OSPEEDR_OSPEED1                GPIO_OSPEEDR_OSPEED1_Msk
11304 #define GPIO_OSPEEDR_OSPEED1_0              (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
11305 #define GPIO_OSPEEDR_OSPEED1_1              (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
11306 #define GPIO_OSPEEDR_OSPEED2_Pos            (4U)
11307 #define GPIO_OSPEEDR_OSPEED2_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
11308 #define GPIO_OSPEEDR_OSPEED2                GPIO_OSPEEDR_OSPEED2_Msk
11309 #define GPIO_OSPEEDR_OSPEED2_0              (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
11310 #define GPIO_OSPEEDR_OSPEED2_1              (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
11311 #define GPIO_OSPEEDR_OSPEED3_Pos            (6U)
11312 #define GPIO_OSPEEDR_OSPEED3_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
11313 #define GPIO_OSPEEDR_OSPEED3                GPIO_OSPEEDR_OSPEED3_Msk
11314 #define GPIO_OSPEEDR_OSPEED3_0              (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
11315 #define GPIO_OSPEEDR_OSPEED3_1              (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
11316 #define GPIO_OSPEEDR_OSPEED4_Pos            (8U)
11317 #define GPIO_OSPEEDR_OSPEED4_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
11318 #define GPIO_OSPEEDR_OSPEED4                GPIO_OSPEEDR_OSPEED4_Msk
11319 #define GPIO_OSPEEDR_OSPEED4_0              (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
11320 #define GPIO_OSPEEDR_OSPEED4_1              (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
11321 #define GPIO_OSPEEDR_OSPEED5_Pos            (10U)
11322 #define GPIO_OSPEEDR_OSPEED5_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
11323 #define GPIO_OSPEEDR_OSPEED5                GPIO_OSPEEDR_OSPEED5_Msk
11324 #define GPIO_OSPEEDR_OSPEED5_0              (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
11325 #define GPIO_OSPEEDR_OSPEED5_1              (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
11326 #define GPIO_OSPEEDR_OSPEED6_Pos            (12U)
11327 #define GPIO_OSPEEDR_OSPEED6_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
11328 #define GPIO_OSPEEDR_OSPEED6                GPIO_OSPEEDR_OSPEED6_Msk
11329 #define GPIO_OSPEEDR_OSPEED6_0              (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
11330 #define GPIO_OSPEEDR_OSPEED6_1              (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
11331 #define GPIO_OSPEEDR_OSPEED7_Pos            (14U)
11332 #define GPIO_OSPEEDR_OSPEED7_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
11333 #define GPIO_OSPEEDR_OSPEED7                GPIO_OSPEEDR_OSPEED7_Msk
11334 #define GPIO_OSPEEDR_OSPEED7_0              (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
11335 #define GPIO_OSPEEDR_OSPEED7_1              (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
11336 #define GPIO_OSPEEDR_OSPEED8_Pos            (16U)
11337 #define GPIO_OSPEEDR_OSPEED8_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
11338 #define GPIO_OSPEEDR_OSPEED8                GPIO_OSPEEDR_OSPEED8_Msk
11339 #define GPIO_OSPEEDR_OSPEED8_0              (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
11340 #define GPIO_OSPEEDR_OSPEED8_1              (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
11341 #define GPIO_OSPEEDR_OSPEED9_Pos            (18U)
11342 #define GPIO_OSPEEDR_OSPEED9_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
11343 #define GPIO_OSPEEDR_OSPEED9                GPIO_OSPEEDR_OSPEED9_Msk
11344 #define GPIO_OSPEEDR_OSPEED9_0              (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
11345 #define GPIO_OSPEEDR_OSPEED9_1              (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
11346 #define GPIO_OSPEEDR_OSPEED10_Pos           (20U)
11347 #define GPIO_OSPEEDR_OSPEED10_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
11348 #define GPIO_OSPEEDR_OSPEED10               GPIO_OSPEEDR_OSPEED10_Msk
11349 #define GPIO_OSPEEDR_OSPEED10_0             (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
11350 #define GPIO_OSPEEDR_OSPEED10_1             (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
11351 #define GPIO_OSPEEDR_OSPEED11_Pos           (22U)
11352 #define GPIO_OSPEEDR_OSPEED11_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
11353 #define GPIO_OSPEEDR_OSPEED11               GPIO_OSPEEDR_OSPEED11_Msk
11354 #define GPIO_OSPEEDR_OSPEED11_0             (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
11355 #define GPIO_OSPEEDR_OSPEED11_1             (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
11356 #define GPIO_OSPEEDR_OSPEED12_Pos           (24U)
11357 #define GPIO_OSPEEDR_OSPEED12_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
11358 #define GPIO_OSPEEDR_OSPEED12               GPIO_OSPEEDR_OSPEED12_Msk
11359 #define GPIO_OSPEEDR_OSPEED12_0             (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
11360 #define GPIO_OSPEEDR_OSPEED12_1             (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
11361 #define GPIO_OSPEEDR_OSPEED13_Pos           (26U)
11362 #define GPIO_OSPEEDR_OSPEED13_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
11363 #define GPIO_OSPEEDR_OSPEED13               GPIO_OSPEEDR_OSPEED13_Msk
11364 #define GPIO_OSPEEDR_OSPEED13_0             (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
11365 #define GPIO_OSPEEDR_OSPEED13_1             (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
11366 #define GPIO_OSPEEDR_OSPEED14_Pos           (28U)
11367 #define GPIO_OSPEEDR_OSPEED14_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
11368 #define GPIO_OSPEEDR_OSPEED14               GPIO_OSPEEDR_OSPEED14_Msk
11369 #define GPIO_OSPEEDR_OSPEED14_0             (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
11370 #define GPIO_OSPEEDR_OSPEED14_1             (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
11371 #define GPIO_OSPEEDR_OSPEED15_Pos           (30U)
11372 #define GPIO_OSPEEDR_OSPEED15_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
11373 #define GPIO_OSPEEDR_OSPEED15               GPIO_OSPEEDR_OSPEED15_Msk
11374 #define GPIO_OSPEEDR_OSPEED15_0             (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
11375 #define GPIO_OSPEEDR_OSPEED15_1             (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
11376 
11377 /******************  Bits definition for GPIO_PUPDR register  *****************/
11378 #define GPIO_PUPDR_PUPD0_Pos                (0U)
11379 #define GPIO_PUPDR_PUPD0_Msk                (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
11380 #define GPIO_PUPDR_PUPD0                    GPIO_PUPDR_PUPD0_Msk
11381 #define GPIO_PUPDR_PUPD0_0                  (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
11382 #define GPIO_PUPDR_PUPD0_1                  (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
11383 #define GPIO_PUPDR_PUPD1_Pos                (2U)
11384 #define GPIO_PUPDR_PUPD1_Msk                (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
11385 #define GPIO_PUPDR_PUPD1                    GPIO_PUPDR_PUPD1_Msk
11386 #define GPIO_PUPDR_PUPD1_0                  (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
11387 #define GPIO_PUPDR_PUPD1_1                  (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
11388 #define GPIO_PUPDR_PUPD2_Pos                (4U)
11389 #define GPIO_PUPDR_PUPD2_Msk                (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
11390 #define GPIO_PUPDR_PUPD2                    GPIO_PUPDR_PUPD2_Msk
11391 #define GPIO_PUPDR_PUPD2_0                  (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
11392 #define GPIO_PUPDR_PUPD2_1                  (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
11393 #define GPIO_PUPDR_PUPD3_Pos                (6U)
11394 #define GPIO_PUPDR_PUPD3_Msk                (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
11395 #define GPIO_PUPDR_PUPD3                    GPIO_PUPDR_PUPD3_Msk
11396 #define GPIO_PUPDR_PUPD3_0                  (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
11397 #define GPIO_PUPDR_PUPD3_1                  (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
11398 #define GPIO_PUPDR_PUPD4_Pos                (8U)
11399 #define GPIO_PUPDR_PUPD4_Msk                (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
11400 #define GPIO_PUPDR_PUPD4                    GPIO_PUPDR_PUPD4_Msk
11401 #define GPIO_PUPDR_PUPD4_0                  (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
11402 #define GPIO_PUPDR_PUPD4_1                  (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
11403 #define GPIO_PUPDR_PUPD5_Pos                (10U)
11404 #define GPIO_PUPDR_PUPD5_Msk                (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
11405 #define GPIO_PUPDR_PUPD5                    GPIO_PUPDR_PUPD5_Msk
11406 #define GPIO_PUPDR_PUPD5_0                  (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
11407 #define GPIO_PUPDR_PUPD5_1                  (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
11408 #define GPIO_PUPDR_PUPD6_Pos                (12U)
11409 #define GPIO_PUPDR_PUPD6_Msk                (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
11410 #define GPIO_PUPDR_PUPD6                    GPIO_PUPDR_PUPD6_Msk
11411 #define GPIO_PUPDR_PUPD6_0                  (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
11412 #define GPIO_PUPDR_PUPD6_1                  (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
11413 #define GPIO_PUPDR_PUPD7_Pos                (14U)
11414 #define GPIO_PUPDR_PUPD7_Msk                (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
11415 #define GPIO_PUPDR_PUPD7                    GPIO_PUPDR_PUPD7_Msk
11416 #define GPIO_PUPDR_PUPD7_0                  (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
11417 #define GPIO_PUPDR_PUPD7_1                  (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
11418 #define GPIO_PUPDR_PUPD8_Pos                (16U)
11419 #define GPIO_PUPDR_PUPD8_Msk                (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
11420 #define GPIO_PUPDR_PUPD8                    GPIO_PUPDR_PUPD8_Msk
11421 #define GPIO_PUPDR_PUPD8_0                  (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
11422 #define GPIO_PUPDR_PUPD8_1                  (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
11423 #define GPIO_PUPDR_PUPD9_Pos                (18U)
11424 #define GPIO_PUPDR_PUPD9_Msk                (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
11425 #define GPIO_PUPDR_PUPD9                    GPIO_PUPDR_PUPD9_Msk
11426 #define GPIO_PUPDR_PUPD9_0                  (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
11427 #define GPIO_PUPDR_PUPD9_1                  (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
11428 #define GPIO_PUPDR_PUPD10_Pos               (20U)
11429 #define GPIO_PUPDR_PUPD10_Msk               (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
11430 #define GPIO_PUPDR_PUPD10                   GPIO_PUPDR_PUPD10_Msk
11431 #define GPIO_PUPDR_PUPD10_0                 (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
11432 #define GPIO_PUPDR_PUPD10_1                 (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
11433 #define GPIO_PUPDR_PUPD11_Pos               (22U)
11434 #define GPIO_PUPDR_PUPD11_Msk               (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
11435 #define GPIO_PUPDR_PUPD11                   GPIO_PUPDR_PUPD11_Msk
11436 #define GPIO_PUPDR_PUPD11_0                 (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
11437 #define GPIO_PUPDR_PUPD11_1                 (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
11438 #define GPIO_PUPDR_PUPD12_Pos               (24U)
11439 #define GPIO_PUPDR_PUPD12_Msk               (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
11440 #define GPIO_PUPDR_PUPD12                   GPIO_PUPDR_PUPD12_Msk
11441 #define GPIO_PUPDR_PUPD12_0                 (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
11442 #define GPIO_PUPDR_PUPD12_1                 (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
11443 #define GPIO_PUPDR_PUPD13_Pos               (26U)
11444 #define GPIO_PUPDR_PUPD13_Msk               (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
11445 #define GPIO_PUPDR_PUPD13                   GPIO_PUPDR_PUPD13_Msk
11446 #define GPIO_PUPDR_PUPD13_0                 (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
11447 #define GPIO_PUPDR_PUPD13_1                 (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
11448 #define GPIO_PUPDR_PUPD14_Pos               (28U)
11449 #define GPIO_PUPDR_PUPD14_Msk               (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
11450 #define GPIO_PUPDR_PUPD14                   GPIO_PUPDR_PUPD14_Msk
11451 #define GPIO_PUPDR_PUPD14_0                 (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
11452 #define GPIO_PUPDR_PUPD14_1                 (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
11453 #define GPIO_PUPDR_PUPD15_Pos               (30U)
11454 #define GPIO_PUPDR_PUPD15_Msk               (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
11455 #define GPIO_PUPDR_PUPD15                   GPIO_PUPDR_PUPD15_Msk
11456 #define GPIO_PUPDR_PUPD15_0                 (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
11457 #define GPIO_PUPDR_PUPD15_1                 (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
11458 
11459 /******************  Bits definition for GPIO_IDR register  *******************/
11460 #define GPIO_IDR_ID0_Pos                    (0U)
11461 #define GPIO_IDR_ID0_Msk                    (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
11462 #define GPIO_IDR_ID0                        GPIO_IDR_ID0_Msk
11463 #define GPIO_IDR_ID1_Pos                    (1U)
11464 #define GPIO_IDR_ID1_Msk                    (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
11465 #define GPIO_IDR_ID1                        GPIO_IDR_ID1_Msk
11466 #define GPIO_IDR_ID2_Pos                    (2U)
11467 #define GPIO_IDR_ID2_Msk                    (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
11468 #define GPIO_IDR_ID2                        GPIO_IDR_ID2_Msk
11469 #define GPIO_IDR_ID3_Pos                    (3U)
11470 #define GPIO_IDR_ID3_Msk                    (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
11471 #define GPIO_IDR_ID3                        GPIO_IDR_ID3_Msk
11472 #define GPIO_IDR_ID4_Pos                    (4U)
11473 #define GPIO_IDR_ID4_Msk                    (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
11474 #define GPIO_IDR_ID4                        GPIO_IDR_ID4_Msk
11475 #define GPIO_IDR_ID5_Pos                    (5U)
11476 #define GPIO_IDR_ID5_Msk                    (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
11477 #define GPIO_IDR_ID5                        GPIO_IDR_ID5_Msk
11478 #define GPIO_IDR_ID6_Pos                    (6U)
11479 #define GPIO_IDR_ID6_Msk                    (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
11480 #define GPIO_IDR_ID6                        GPIO_IDR_ID6_Msk
11481 #define GPIO_IDR_ID7_Pos                    (7U)
11482 #define GPIO_IDR_ID7_Msk                    (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
11483 #define GPIO_IDR_ID7                        GPIO_IDR_ID7_Msk
11484 #define GPIO_IDR_ID8_Pos                    (8U)
11485 #define GPIO_IDR_ID8_Msk                    (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
11486 #define GPIO_IDR_ID8                        GPIO_IDR_ID8_Msk
11487 #define GPIO_IDR_ID9_Pos                    (9U)
11488 #define GPIO_IDR_ID9_Msk                    (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
11489 #define GPIO_IDR_ID9                        GPIO_IDR_ID9_Msk
11490 #define GPIO_IDR_ID10_Pos                   (10U)
11491 #define GPIO_IDR_ID10_Msk                   (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
11492 #define GPIO_IDR_ID10                       GPIO_IDR_ID10_Msk
11493 #define GPIO_IDR_ID11_Pos                   (11U)
11494 #define GPIO_IDR_ID11_Msk                   (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
11495 #define GPIO_IDR_ID11                       GPIO_IDR_ID11_Msk
11496 #define GPIO_IDR_ID12_Pos                   (12U)
11497 #define GPIO_IDR_ID12_Msk                   (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
11498 #define GPIO_IDR_ID12                       GPIO_IDR_ID12_Msk
11499 #define GPIO_IDR_ID13_Pos                   (13U)
11500 #define GPIO_IDR_ID13_Msk                   (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
11501 #define GPIO_IDR_ID13                       GPIO_IDR_ID13_Msk
11502 #define GPIO_IDR_ID14_Pos                   (14U)
11503 #define GPIO_IDR_ID14_Msk                   (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
11504 #define GPIO_IDR_ID14                       GPIO_IDR_ID14_Msk
11505 #define GPIO_IDR_ID15_Pos                   (15U)
11506 #define GPIO_IDR_ID15_Msk                   (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
11507 #define GPIO_IDR_ID15                       GPIO_IDR_ID15_Msk
11508 
11509 /******************  Bits definition for GPIO_ODR register  *******************/
11510 #define GPIO_ODR_OD0_Pos                    (0U)
11511 #define GPIO_ODR_OD0_Msk                    (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
11512 #define GPIO_ODR_OD0                        GPIO_ODR_OD0_Msk
11513 #define GPIO_ODR_OD1_Pos                    (1U)
11514 #define GPIO_ODR_OD1_Msk                    (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
11515 #define GPIO_ODR_OD1                        GPIO_ODR_OD1_Msk
11516 #define GPIO_ODR_OD2_Pos                    (2U)
11517 #define GPIO_ODR_OD2_Msk                    (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
11518 #define GPIO_ODR_OD2                        GPIO_ODR_OD2_Msk
11519 #define GPIO_ODR_OD3_Pos                    (3U)
11520 #define GPIO_ODR_OD3_Msk                    (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
11521 #define GPIO_ODR_OD3                        GPIO_ODR_OD3_Msk
11522 #define GPIO_ODR_OD4_Pos                    (4U)
11523 #define GPIO_ODR_OD4_Msk                    (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
11524 #define GPIO_ODR_OD4                        GPIO_ODR_OD4_Msk
11525 #define GPIO_ODR_OD5_Pos                    (5U)
11526 #define GPIO_ODR_OD5_Msk                    (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
11527 #define GPIO_ODR_OD5                        GPIO_ODR_OD5_Msk
11528 #define GPIO_ODR_OD6_Pos                    (6U)
11529 #define GPIO_ODR_OD6_Msk                    (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
11530 #define GPIO_ODR_OD6                        GPIO_ODR_OD6_Msk
11531 #define GPIO_ODR_OD7_Pos                    (7U)
11532 #define GPIO_ODR_OD7_Msk                    (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
11533 #define GPIO_ODR_OD7                        GPIO_ODR_OD7_Msk
11534 #define GPIO_ODR_OD8_Pos                    (8U)
11535 #define GPIO_ODR_OD8_Msk                    (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
11536 #define GPIO_ODR_OD8                        GPIO_ODR_OD8_Msk
11537 #define GPIO_ODR_OD9_Pos                    (9U)
11538 #define GPIO_ODR_OD9_Msk                    (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
11539 #define GPIO_ODR_OD9                        GPIO_ODR_OD9_Msk
11540 #define GPIO_ODR_OD10_Pos                   (10U)
11541 #define GPIO_ODR_OD10_Msk                   (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
11542 #define GPIO_ODR_OD10                       GPIO_ODR_OD10_Msk
11543 #define GPIO_ODR_OD11_Pos                   (11U)
11544 #define GPIO_ODR_OD11_Msk                   (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
11545 #define GPIO_ODR_OD11                       GPIO_ODR_OD11_Msk
11546 #define GPIO_ODR_OD12_Pos                   (12U)
11547 #define GPIO_ODR_OD12_Msk                   (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
11548 #define GPIO_ODR_OD12                       GPIO_ODR_OD12_Msk
11549 #define GPIO_ODR_OD13_Pos                   (13U)
11550 #define GPIO_ODR_OD13_Msk                   (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
11551 #define GPIO_ODR_OD13                       GPIO_ODR_OD13_Msk
11552 #define GPIO_ODR_OD14_Pos                   (14U)
11553 #define GPIO_ODR_OD14_Msk                   (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
11554 #define GPIO_ODR_OD14                       GPIO_ODR_OD14_Msk
11555 #define GPIO_ODR_OD15_Pos                   (15U)
11556 #define GPIO_ODR_OD15_Msk                   (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
11557 #define GPIO_ODR_OD15                       GPIO_ODR_OD15_Msk
11558 
11559 /******************  Bits definition for GPIO_BSRR register  ******************/
11560 #define GPIO_BSRR_BS0_Pos                   (0U)
11561 #define GPIO_BSRR_BS0_Msk                   (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
11562 #define GPIO_BSRR_BS0                       GPIO_BSRR_BS0_Msk
11563 #define GPIO_BSRR_BS1_Pos                   (1U)
11564 #define GPIO_BSRR_BS1_Msk                   (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
11565 #define GPIO_BSRR_BS1                       GPIO_BSRR_BS1_Msk
11566 #define GPIO_BSRR_BS2_Pos                   (2U)
11567 #define GPIO_BSRR_BS2_Msk                   (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
11568 #define GPIO_BSRR_BS2                       GPIO_BSRR_BS2_Msk
11569 #define GPIO_BSRR_BS3_Pos                   (3U)
11570 #define GPIO_BSRR_BS3_Msk                   (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
11571 #define GPIO_BSRR_BS3                       GPIO_BSRR_BS3_Msk
11572 #define GPIO_BSRR_BS4_Pos                   (4U)
11573 #define GPIO_BSRR_BS4_Msk                   (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
11574 #define GPIO_BSRR_BS4                       GPIO_BSRR_BS4_Msk
11575 #define GPIO_BSRR_BS5_Pos                   (5U)
11576 #define GPIO_BSRR_BS5_Msk                   (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
11577 #define GPIO_BSRR_BS5                       GPIO_BSRR_BS5_Msk
11578 #define GPIO_BSRR_BS6_Pos                   (6U)
11579 #define GPIO_BSRR_BS6_Msk                   (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
11580 #define GPIO_BSRR_BS6                       GPIO_BSRR_BS6_Msk
11581 #define GPIO_BSRR_BS7_Pos                   (7U)
11582 #define GPIO_BSRR_BS7_Msk                   (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
11583 #define GPIO_BSRR_BS7                       GPIO_BSRR_BS7_Msk
11584 #define GPIO_BSRR_BS8_Pos                   (8U)
11585 #define GPIO_BSRR_BS8_Msk                   (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
11586 #define GPIO_BSRR_BS8                       GPIO_BSRR_BS8_Msk
11587 #define GPIO_BSRR_BS9_Pos                   (9U)
11588 #define GPIO_BSRR_BS9_Msk                   (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
11589 #define GPIO_BSRR_BS9                       GPIO_BSRR_BS9_Msk
11590 #define GPIO_BSRR_BS10_Pos                  (10U)
11591 #define GPIO_BSRR_BS10_Msk                  (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
11592 #define GPIO_BSRR_BS10                      GPIO_BSRR_BS10_Msk
11593 #define GPIO_BSRR_BS11_Pos                  (11U)
11594 #define GPIO_BSRR_BS11_Msk                  (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
11595 #define GPIO_BSRR_BS11                      GPIO_BSRR_BS11_Msk
11596 #define GPIO_BSRR_BS12_Pos                  (12U)
11597 #define GPIO_BSRR_BS12_Msk                  (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
11598 #define GPIO_BSRR_BS12                      GPIO_BSRR_BS12_Msk
11599 #define GPIO_BSRR_BS13_Pos                  (13U)
11600 #define GPIO_BSRR_BS13_Msk                  (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
11601 #define GPIO_BSRR_BS13                      GPIO_BSRR_BS13_Msk
11602 #define GPIO_BSRR_BS14_Pos                  (14U)
11603 #define GPIO_BSRR_BS14_Msk                  (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
11604 #define GPIO_BSRR_BS14                      GPIO_BSRR_BS14_Msk
11605 #define GPIO_BSRR_BS15_Pos                  (15U)
11606 #define GPIO_BSRR_BS15_Msk                  (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
11607 #define GPIO_BSRR_BS15                      GPIO_BSRR_BS15_Msk
11608 #define GPIO_BSRR_BR0_Pos                   (16U)
11609 #define GPIO_BSRR_BR0_Msk                   (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
11610 #define GPIO_BSRR_BR0                       GPIO_BSRR_BR0_Msk
11611 #define GPIO_BSRR_BR1_Pos                   (17U)
11612 #define GPIO_BSRR_BR1_Msk                   (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
11613 #define GPIO_BSRR_BR1                       GPIO_BSRR_BR1_Msk
11614 #define GPIO_BSRR_BR2_Pos                   (18U)
11615 #define GPIO_BSRR_BR2_Msk                   (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
11616 #define GPIO_BSRR_BR2                       GPIO_BSRR_BR2_Msk
11617 #define GPIO_BSRR_BR3_Pos                   (19U)
11618 #define GPIO_BSRR_BR3_Msk                   (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
11619 #define GPIO_BSRR_BR3                       GPIO_BSRR_BR3_Msk
11620 #define GPIO_BSRR_BR4_Pos                   (20U)
11621 #define GPIO_BSRR_BR4_Msk                   (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
11622 #define GPIO_BSRR_BR4                       GPIO_BSRR_BR4_Msk
11623 #define GPIO_BSRR_BR5_Pos                   (21U)
11624 #define GPIO_BSRR_BR5_Msk                   (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
11625 #define GPIO_BSRR_BR5                       GPIO_BSRR_BR5_Msk
11626 #define GPIO_BSRR_BR6_Pos                   (22U)
11627 #define GPIO_BSRR_BR6_Msk                   (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
11628 #define GPIO_BSRR_BR6                       GPIO_BSRR_BR6_Msk
11629 #define GPIO_BSRR_BR7_Pos                   (23U)
11630 #define GPIO_BSRR_BR7_Msk                   (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
11631 #define GPIO_BSRR_BR7                       GPIO_BSRR_BR7_Msk
11632 #define GPIO_BSRR_BR8_Pos                   (24U)
11633 #define GPIO_BSRR_BR8_Msk                   (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
11634 #define GPIO_BSRR_BR8                       GPIO_BSRR_BR8_Msk
11635 #define GPIO_BSRR_BR9_Pos                   (25U)
11636 #define GPIO_BSRR_BR9_Msk                   (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
11637 #define GPIO_BSRR_BR9                       GPIO_BSRR_BR9_Msk
11638 #define GPIO_BSRR_BR10_Pos                  (26U)
11639 #define GPIO_BSRR_BR10_Msk                  (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
11640 #define GPIO_BSRR_BR10                      GPIO_BSRR_BR10_Msk
11641 #define GPIO_BSRR_BR11_Pos                  (27U)
11642 #define GPIO_BSRR_BR11_Msk                  (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
11643 #define GPIO_BSRR_BR11                      GPIO_BSRR_BR11_Msk
11644 #define GPIO_BSRR_BR12_Pos                  (28U)
11645 #define GPIO_BSRR_BR12_Msk                  (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
11646 #define GPIO_BSRR_BR12                      GPIO_BSRR_BR12_Msk
11647 #define GPIO_BSRR_BR13_Pos                  (29U)
11648 #define GPIO_BSRR_BR13_Msk                  (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
11649 #define GPIO_BSRR_BR13                      GPIO_BSRR_BR13_Msk
11650 #define GPIO_BSRR_BR14_Pos                  (30U)
11651 #define GPIO_BSRR_BR14_Msk                  (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
11652 #define GPIO_BSRR_BR14                      GPIO_BSRR_BR14_Msk
11653 #define GPIO_BSRR_BR15_Pos                  (31U)
11654 #define GPIO_BSRR_BR15_Msk                  (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
11655 #define GPIO_BSRR_BR15                      GPIO_BSRR_BR15_Msk
11656 
11657 /****************** Bit definition for GPIO_LCKR register *********************/
11658 #define GPIO_LCKR_LCK0_Pos                  (0U)
11659 #define GPIO_LCKR_LCK0_Msk                  (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
11660 #define GPIO_LCKR_LCK0                      GPIO_LCKR_LCK0_Msk
11661 #define GPIO_LCKR_LCK1_Pos                  (1U)
11662 #define GPIO_LCKR_LCK1_Msk                  (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
11663 #define GPIO_LCKR_LCK1                      GPIO_LCKR_LCK1_Msk
11664 #define GPIO_LCKR_LCK2_Pos                  (2U)
11665 #define GPIO_LCKR_LCK2_Msk                  (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
11666 #define GPIO_LCKR_LCK2                      GPIO_LCKR_LCK2_Msk
11667 #define GPIO_LCKR_LCK3_Pos                  (3U)
11668 #define GPIO_LCKR_LCK3_Msk                  (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
11669 #define GPIO_LCKR_LCK3                      GPIO_LCKR_LCK3_Msk
11670 #define GPIO_LCKR_LCK4_Pos                  (4U)
11671 #define GPIO_LCKR_LCK4_Msk                  (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
11672 #define GPIO_LCKR_LCK4                      GPIO_LCKR_LCK4_Msk
11673 #define GPIO_LCKR_LCK5_Pos                  (5U)
11674 #define GPIO_LCKR_LCK5_Msk                  (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
11675 #define GPIO_LCKR_LCK5                      GPIO_LCKR_LCK5_Msk
11676 #define GPIO_LCKR_LCK6_Pos                  (6U)
11677 #define GPIO_LCKR_LCK6_Msk                  (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
11678 #define GPIO_LCKR_LCK6                      GPIO_LCKR_LCK6_Msk
11679 #define GPIO_LCKR_LCK7_Pos                  (7U)
11680 #define GPIO_LCKR_LCK7_Msk                  (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
11681 #define GPIO_LCKR_LCK7                      GPIO_LCKR_LCK7_Msk
11682 #define GPIO_LCKR_LCK8_Pos                  (8U)
11683 #define GPIO_LCKR_LCK8_Msk                  (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
11684 #define GPIO_LCKR_LCK8                      GPIO_LCKR_LCK8_Msk
11685 #define GPIO_LCKR_LCK9_Pos                  (9U)
11686 #define GPIO_LCKR_LCK9_Msk                  (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
11687 #define GPIO_LCKR_LCK9                      GPIO_LCKR_LCK9_Msk
11688 #define GPIO_LCKR_LCK10_Pos                 (10U)
11689 #define GPIO_LCKR_LCK10_Msk                 (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
11690 #define GPIO_LCKR_LCK10                     GPIO_LCKR_LCK10_Msk
11691 #define GPIO_LCKR_LCK11_Pos                 (11U)
11692 #define GPIO_LCKR_LCK11_Msk                 (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
11693 #define GPIO_LCKR_LCK11                     GPIO_LCKR_LCK11_Msk
11694 #define GPIO_LCKR_LCK12_Pos                 (12U)
11695 #define GPIO_LCKR_LCK12_Msk                 (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
11696 #define GPIO_LCKR_LCK12                     GPIO_LCKR_LCK12_Msk
11697 #define GPIO_LCKR_LCK13_Pos                 (13U)
11698 #define GPIO_LCKR_LCK13_Msk                 (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
11699 #define GPIO_LCKR_LCK13                     GPIO_LCKR_LCK13_Msk
11700 #define GPIO_LCKR_LCK14_Pos                 (14U)
11701 #define GPIO_LCKR_LCK14_Msk                 (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
11702 #define GPIO_LCKR_LCK14                     GPIO_LCKR_LCK14_Msk
11703 #define GPIO_LCKR_LCK15_Pos                 (15U)
11704 #define GPIO_LCKR_LCK15_Msk                 (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
11705 #define GPIO_LCKR_LCK15                     GPIO_LCKR_LCK15_Msk
11706 #define GPIO_LCKR_LCKK_Pos                  (16U)
11707 #define GPIO_LCKR_LCKK_Msk                  (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
11708 #define GPIO_LCKR_LCKK                      GPIO_LCKR_LCKK_Msk
11709 
11710 /****************** Bit definition for GPIO_AFRL register *********************/
11711 #define GPIO_AFRL_AFSEL0_Pos                (0U)
11712 #define GPIO_AFRL_AFSEL0_Msk                (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
11713 #define GPIO_AFRL_AFSEL0                    GPIO_AFRL_AFSEL0_Msk
11714 #define GPIO_AFRL_AFSEL0_0                  (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
11715 #define GPIO_AFRL_AFSEL0_1                  (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
11716 #define GPIO_AFRL_AFSEL0_2                  (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
11717 #define GPIO_AFRL_AFSEL0_3                  (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
11718 #define GPIO_AFRL_AFSEL1_Pos                (4U)
11719 #define GPIO_AFRL_AFSEL1_Msk                (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
11720 #define GPIO_AFRL_AFSEL1                    GPIO_AFRL_AFSEL1_Msk
11721 #define GPIO_AFRL_AFSEL1_0                  (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
11722 #define GPIO_AFRL_AFSEL1_1                  (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
11723 #define GPIO_AFRL_AFSEL1_2                  (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
11724 #define GPIO_AFRL_AFSEL1_3                  (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
11725 #define GPIO_AFRL_AFSEL2_Pos                (8U)
11726 #define GPIO_AFRL_AFSEL2_Msk                (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
11727 #define GPIO_AFRL_AFSEL2                    GPIO_AFRL_AFSEL2_Msk
11728 #define GPIO_AFRL_AFSEL2_0                  (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
11729 #define GPIO_AFRL_AFSEL2_1                  (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
11730 #define GPIO_AFRL_AFSEL2_2                  (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
11731 #define GPIO_AFRL_AFSEL2_3                  (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
11732 #define GPIO_AFRL_AFSEL3_Pos                (12U)
11733 #define GPIO_AFRL_AFSEL3_Msk                (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
11734 #define GPIO_AFRL_AFSEL3                    GPIO_AFRL_AFSEL3_Msk
11735 #define GPIO_AFRL_AFSEL3_0                  (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
11736 #define GPIO_AFRL_AFSEL3_1                  (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
11737 #define GPIO_AFRL_AFSEL3_2                  (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
11738 #define GPIO_AFRL_AFSEL3_3                  (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
11739 #define GPIO_AFRL_AFSEL4_Pos                (16U)
11740 #define GPIO_AFRL_AFSEL4_Msk                (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
11741 #define GPIO_AFRL_AFSEL4                    GPIO_AFRL_AFSEL4_Msk
11742 #define GPIO_AFRL_AFSEL4_0                  (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
11743 #define GPIO_AFRL_AFSEL4_1                  (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
11744 #define GPIO_AFRL_AFSEL4_2                  (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
11745 #define GPIO_AFRL_AFSEL4_3                  (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
11746 #define GPIO_AFRL_AFSEL5_Pos                (20U)
11747 #define GPIO_AFRL_AFSEL5_Msk                (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
11748 #define GPIO_AFRL_AFSEL5                    GPIO_AFRL_AFSEL5_Msk
11749 #define GPIO_AFRL_AFSEL5_0                  (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
11750 #define GPIO_AFRL_AFSEL5_1                  (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
11751 #define GPIO_AFRL_AFSEL5_2                  (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
11752 #define GPIO_AFRL_AFSEL5_3                  (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
11753 #define GPIO_AFRL_AFSEL6_Pos                (24U)
11754 #define GPIO_AFRL_AFSEL6_Msk                (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
11755 #define GPIO_AFRL_AFSEL6                    GPIO_AFRL_AFSEL6_Msk
11756 #define GPIO_AFRL_AFSEL6_0                  (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
11757 #define GPIO_AFRL_AFSEL6_1                  (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
11758 #define GPIO_AFRL_AFSEL6_2                  (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
11759 #define GPIO_AFRL_AFSEL6_3                  (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
11760 #define GPIO_AFRL_AFSEL7_Pos                (28U)
11761 #define GPIO_AFRL_AFSEL7_Msk                (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
11762 #define GPIO_AFRL_AFSEL7                    GPIO_AFRL_AFSEL7_Msk
11763 #define GPIO_AFRL_AFSEL7_0                  (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
11764 #define GPIO_AFRL_AFSEL7_1                  (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
11765 #define GPIO_AFRL_AFSEL7_2                  (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
11766 #define GPIO_AFRL_AFSEL7_3                  (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
11767 
11768 /****************** Bit definition for GPIO_AFRH register *********************/
11769 #define GPIO_AFRH_AFSEL8_Pos                (0U)
11770 #define GPIO_AFRH_AFSEL8_Msk                (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
11771 #define GPIO_AFRH_AFSEL8                    GPIO_AFRH_AFSEL8_Msk
11772 #define GPIO_AFRH_AFSEL8_0                  (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
11773 #define GPIO_AFRH_AFSEL8_1                  (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
11774 #define GPIO_AFRH_AFSEL8_2                  (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
11775 #define GPIO_AFRH_AFSEL8_3                  (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
11776 #define GPIO_AFRH_AFSEL9_Pos                (4U)
11777 #define GPIO_AFRH_AFSEL9_Msk                (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
11778 #define GPIO_AFRH_AFSEL9                    GPIO_AFRH_AFSEL9_Msk
11779 #define GPIO_AFRH_AFSEL9_0                  (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
11780 #define GPIO_AFRH_AFSEL9_1                  (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
11781 #define GPIO_AFRH_AFSEL9_2                  (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
11782 #define GPIO_AFRH_AFSEL9_3                  (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
11783 #define GPIO_AFRH_AFSEL10_Pos               (8U)
11784 #define GPIO_AFRH_AFSEL10_Msk               (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
11785 #define GPIO_AFRH_AFSEL10                   GPIO_AFRH_AFSEL10_Msk
11786 #define GPIO_AFRH_AFSEL10_0                 (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
11787 #define GPIO_AFRH_AFSEL10_1                 (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
11788 #define GPIO_AFRH_AFSEL10_2                 (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
11789 #define GPIO_AFRH_AFSEL10_3                 (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
11790 #define GPIO_AFRH_AFSEL11_Pos               (12U)
11791 #define GPIO_AFRH_AFSEL11_Msk               (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
11792 #define GPIO_AFRH_AFSEL11                   GPIO_AFRH_AFSEL11_Msk
11793 #define GPIO_AFRH_AFSEL11_0                 (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
11794 #define GPIO_AFRH_AFSEL11_1                 (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
11795 #define GPIO_AFRH_AFSEL11_2                 (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
11796 #define GPIO_AFRH_AFSEL11_3                 (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
11797 #define GPIO_AFRH_AFSEL12_Pos               (16U)
11798 #define GPIO_AFRH_AFSEL12_Msk               (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
11799 #define GPIO_AFRH_AFSEL12                   GPIO_AFRH_AFSEL12_Msk
11800 #define GPIO_AFRH_AFSEL12_0                 (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
11801 #define GPIO_AFRH_AFSEL12_1                 (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
11802 #define GPIO_AFRH_AFSEL12_2                 (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
11803 #define GPIO_AFRH_AFSEL12_3                 (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
11804 #define GPIO_AFRH_AFSEL13_Pos               (20U)
11805 #define GPIO_AFRH_AFSEL13_Msk               (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
11806 #define GPIO_AFRH_AFSEL13                   GPIO_AFRH_AFSEL13_Msk
11807 #define GPIO_AFRH_AFSEL13_0                 (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
11808 #define GPIO_AFRH_AFSEL13_1                 (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
11809 #define GPIO_AFRH_AFSEL13_2                 (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
11810 #define GPIO_AFRH_AFSEL13_3                 (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
11811 #define GPIO_AFRH_AFSEL14_Pos               (24U)
11812 #define GPIO_AFRH_AFSEL14_Msk               (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
11813 #define GPIO_AFRH_AFSEL14                   GPIO_AFRH_AFSEL14_Msk
11814 #define GPIO_AFRH_AFSEL14_0                 (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
11815 #define GPIO_AFRH_AFSEL14_1                 (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
11816 #define GPIO_AFRH_AFSEL14_2                 (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
11817 #define GPIO_AFRH_AFSEL14_3                 (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
11818 #define GPIO_AFRH_AFSEL15_Pos               (28U)
11819 #define GPIO_AFRH_AFSEL15_Msk               (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
11820 #define GPIO_AFRH_AFSEL15                   GPIO_AFRH_AFSEL15_Msk
11821 #define GPIO_AFRH_AFSEL15_0                 (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
11822 #define GPIO_AFRH_AFSEL15_1                 (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
11823 #define GPIO_AFRH_AFSEL15_2                 (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
11824 #define GPIO_AFRH_AFSEL15_3                 (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
11825 
11826 /******************  Bits definition for GPIO_BRR register  ******************/
11827 #define GPIO_BRR_BR0_Pos                    (0U)
11828 #define GPIO_BRR_BR0_Msk                    (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
11829 #define GPIO_BRR_BR0                        GPIO_BRR_BR0_Msk
11830 #define GPIO_BRR_BR1_Pos                    (1U)
11831 #define GPIO_BRR_BR1_Msk                    (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
11832 #define GPIO_BRR_BR1                        GPIO_BRR_BR1_Msk
11833 #define GPIO_BRR_BR2_Pos                    (2U)
11834 #define GPIO_BRR_BR2_Msk                    (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
11835 #define GPIO_BRR_BR2                        GPIO_BRR_BR2_Msk
11836 #define GPIO_BRR_BR3_Pos                    (3U)
11837 #define GPIO_BRR_BR3_Msk                    (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
11838 #define GPIO_BRR_BR3                        GPIO_BRR_BR3_Msk
11839 #define GPIO_BRR_BR4_Pos                    (4U)
11840 #define GPIO_BRR_BR4_Msk                    (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
11841 #define GPIO_BRR_BR4                        GPIO_BRR_BR4_Msk
11842 #define GPIO_BRR_BR5_Pos                    (5U)
11843 #define GPIO_BRR_BR5_Msk                    (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
11844 #define GPIO_BRR_BR5                        GPIO_BRR_BR5_Msk
11845 #define GPIO_BRR_BR6_Pos                    (6U)
11846 #define GPIO_BRR_BR6_Msk                    (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
11847 #define GPIO_BRR_BR6                        GPIO_BRR_BR6_Msk
11848 #define GPIO_BRR_BR7_Pos                    (7U)
11849 #define GPIO_BRR_BR7_Msk                    (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
11850 #define GPIO_BRR_BR7                        GPIO_BRR_BR7_Msk
11851 #define GPIO_BRR_BR8_Pos                    (8U)
11852 #define GPIO_BRR_BR8_Msk                    (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
11853 #define GPIO_BRR_BR8                        GPIO_BRR_BR8_Msk
11854 #define GPIO_BRR_BR9_Pos                    (9U)
11855 #define GPIO_BRR_BR9_Msk                    (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
11856 #define GPIO_BRR_BR9                        GPIO_BRR_BR9_Msk
11857 #define GPIO_BRR_BR10_Pos                   (10U)
11858 #define GPIO_BRR_BR10_Msk                   (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
11859 #define GPIO_BRR_BR10                       GPIO_BRR_BR10_Msk
11860 #define GPIO_BRR_BR11_Pos                   (11U)
11861 #define GPIO_BRR_BR11_Msk                   (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
11862 #define GPIO_BRR_BR11                       GPIO_BRR_BR11_Msk
11863 #define GPIO_BRR_BR12_Pos                   (12U)
11864 #define GPIO_BRR_BR12_Msk                   (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
11865 #define GPIO_BRR_BR12                       GPIO_BRR_BR12_Msk
11866 #define GPIO_BRR_BR13_Pos                   (13U)
11867 #define GPIO_BRR_BR13_Msk                   (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
11868 #define GPIO_BRR_BR13                       GPIO_BRR_BR13_Msk
11869 #define GPIO_BRR_BR14_Pos                   (14U)
11870 #define GPIO_BRR_BR14_Msk                   (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
11871 #define GPIO_BRR_BR14                       GPIO_BRR_BR14_Msk
11872 #define GPIO_BRR_BR15_Pos                   (15U)
11873 #define GPIO_BRR_BR15_Msk                   (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
11874 #define GPIO_BRR_BR15                       GPIO_BRR_BR15_Msk
11875 
11876 /******************  Bits definition for GPIO_HSLVR register  ******************/
11877 #define GPIO_HSLVR_HSLV0_Pos                (0U)
11878 #define GPIO_HSLVR_HSLV0_Msk                (0x1UL << GPIO_HSLVR_HSLV0_Pos)         /*!< 0x00000001 */
11879 #define GPIO_HSLVR_HSLV0                    GPIO_HSLVR_HSLV0_Msk
11880 #define GPIO_HSLVR_HSLV1_Pos                (1U)
11881 #define GPIO_HSLVR_HSLV1_Msk                (0x1UL << GPIO_HSLVR_HSLV1_Pos)         /*!< 0x00000002 */
11882 #define GPIO_HSLVR_HSLV1                    GPIO_HSLVR_HSLV1_Msk
11883 #define GPIO_HSLVR_HSLV2_Pos                (2U)
11884 #define GPIO_HSLVR_HSLV2_Msk                (0x1UL << GPIO_HSLVR_HSLV2_Pos)         /*!< 0x00000004 */
11885 #define GPIO_HSLVR_HSLV2                    GPIO_HSLVR_HSLV2_Msk
11886 #define GPIO_HSLVR_HSLV3_Pos                (3U)
11887 #define GPIO_HSLVR_HSLV3_Msk                (0x1UL << GPIO_HSLVR_HSLV3_Pos)         /*!< 0x00000008 */
11888 #define GPIO_HSLVR_HSLV3                    GPIO_HSLVR_HSLV3_Msk
11889 #define GPIO_HSLVR_HSLV4_Pos                (4U)
11890 #define GPIO_HSLVR_HSLV4_Msk                (0x1UL << GPIO_HSLVR_HSLV4_Pos)         /*!< 0x00000010 */
11891 #define GPIO_HSLVR_HSLV4                    GPIO_HSLVR_HSLV4_Msk
11892 #define GPIO_HSLVR_HSLV5_Pos                (5U)
11893 #define GPIO_HSLVR_HSLV5_Msk                (0x1UL << GPIO_HSLVR_HSLV5_Pos)         /*!< 0x00000020 */
11894 #define GPIO_HSLVR_HSLV5                    GPIO_HSLVR_HSLV5_Msk
11895 #define GPIO_HSLVR_HSLV6_Pos                (6U)
11896 #define GPIO_HSLVR_HSLV6_Msk                (0x1UL << GPIO_HSLVR_HSLV6_Pos)         /*!< 0x00000040 */
11897 #define GPIO_HSLVR_HSLV6                    GPIO_HSLVR_HSLV6_Msk
11898 #define GPIO_HSLVR_HSLV7_Pos                (7U)
11899 #define GPIO_HSLVR_HSLV7_Msk                (0x1UL << GPIO_HSLVR_HSLV7_Pos)         /*!< 0x00000080 */
11900 #define GPIO_HSLVR_HSLV7                    GPIO_HSLVR_HSLV7_Msk
11901 #define GPIO_HSLVR_HSLV8_Pos                (8U)
11902 #define GPIO_HSLVR_HSLV8_Msk                (0x1UL << GPIO_HSLVR_HSLV8_Pos)         /*!< 0x00000100 */
11903 #define GPIO_HSLVR_HSLV8                    GPIO_HSLVR_HSLV8_Msk
11904 #define GPIO_HSLVR_HSLV9_Pos                (9U)
11905 #define GPIO_HSLVR_HSLV9_Msk                (0x1UL << GPIO_HSLVR_HSLV9_Pos)         /*!< 0x00000200 */
11906 #define GPIO_HSLVR_HSLV9                    GPIO_HSLVR_HSLV9_Msk
11907 #define GPIO_HSLVR_HSLV10_Pos               (10U)
11908 #define GPIO_HSLVR_HSLV10_Msk               (0x1UL << GPIO_HSLVR_HSLV10_Pos)        /*!< 0x00000400 */
11909 #define GPIO_HSLVR_HSLV10                   GPIO_HSLVR_HSLV10_Msk
11910 #define GPIO_HSLVR_HSLV11_Pos               (11U)
11911 #define GPIO_HSLVR_HSLV11_Msk               (x1UL << GPIO_HSLVR_HSLV11_Pos)         /*!< 0x00000800 */
11912 #define GPIO_HSLVR_HSLV11                   GPIO_HSLVR_HSLV11_Msk
11913 #define GPIO_HSLVR_HSLV12_Pos               (12U)
11914 #define GPIO_HSLVR_HSLV12_Msk               (0x1UL << GPIO_HSLVR_HSLV12_Pos)        /*!< 0x00001000 */
11915 #define GPIO_HSLVR_HSLV12                   GPIO_HSLVR_HSLV12_Msk
11916 #define GPIO_HSLVR_HSLV13_Pos               (13U)
11917 #define GPIO_HSLVR_HSLV13_Msk               (0x1UL << GPIO_HSLVR_HSLV13_Pos)        /*!< 0x00002000 */
11918 #define GPIO_HSLVR_HSLV13                   GPIO_HSLVR_HSLV13_Msk
11919 #define GPIO_HSLVR_HSLV14_Pos               (14U)
11920 #define GPIO_HSLVR_HSLV14_Msk               (0x1UL << GPIO_HSLVR_HSLV14_Pos)        /*!< 0x00004000 */
11921 #define GPIO_HSLVR_HSLV14                   GPIO_HSLVR_HSLV14_Msk
11922 #define GPIO_HSLVR_HSLV15_Pos               (15U)
11923 #define GPIO_HSLVR_HSLV15_Msk               (0x1UL << GPIO_HSLVR_HSLV15_Pos)        /*!< 0x00008000 */
11924 #define GPIO_HSLVR_HSLV15                   GPIO_HSLVR_HSLV15_Msk
11925 
11926 /******************  Bits definition for GPIO_SECCFGR register  ******************/
11927 #define GPIO_SECCFGR_SEC0_Pos               (0U)
11928 #define GPIO_SECCFGR_SEC0_Msk               (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
11929 #define GPIO_SECCFGR_SEC0                   GPIO_SECCFGR_SEC0_Msk
11930 #define GPIO_SECCFGR_SEC1_Pos               (1U)
11931 #define GPIO_SECCFGR_SEC1_Msk               (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
11932 #define GPIO_SECCFGR_SEC1                   GPIO_SECCFGR_SEC1_Msk
11933 #define GPIO_SECCFGR_SEC2_Pos               (2U)
11934 #define GPIO_SECCFGR_SEC2_Msk               (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
11935 #define GPIO_SECCFGR_SEC2                   GPIO_SECCFGR_SEC2_Msk
11936 #define GPIO_SECCFGR_SEC3_Pos               (3U)
11937 #define GPIO_SECCFGR_SEC3_Msk               (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
11938 #define GPIO_SECCFGR_SEC3                   GPIO_SECCFGR_SEC3_Msk
11939 #define GPIO_SECCFGR_SEC4_Pos               (4U)
11940 #define GPIO_SECCFGR_SEC4_Msk               (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
11941 #define GPIO_SECCFGR_SEC4                   GPIO_SECCFGR_SEC4_Msk
11942 #define GPIO_SECCFGR_SEC5_Pos               (5U)
11943 #define GPIO_SECCFGR_SEC5_Msk               (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
11944 #define GPIO_SECCFGR_SEC5                   GPIO_SECCFGR_SEC5_Msk
11945 #define GPIO_SECCFGR_SEC6_Pos               (6U)
11946 #define GPIO_SECCFGR_SEC6_Msk               (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
11947 #define GPIO_SECCFGR_SEC6                   GPIO_SECCFGR_SEC6_Msk
11948 #define GPIO_SECCFGR_SEC7_Pos               (7U)
11949 #define GPIO_SECCFGR_SEC7_Msk               (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
11950 #define GPIO_SECCFGR_SEC7                   GPIO_SECCFGR_SEC7_Msk
11951 #define GPIO_SECCFGR_SEC8_Pos               (8U)
11952 #define GPIO_SECCFGR_SEC8_Msk               (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
11953 #define GPIO_SECCFGR_SEC8                   GPIO_SECCFGR_SEC8_Msk
11954 #define GPIO_SECCFGR_SEC9_Pos               (9U)
11955 #define GPIO_SECCFGR_SEC9_Msk               (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
11956 #define GPIO_SECCFGR_SEC9                   GPIO_SECCFGR_SEC9_Msk
11957 #define GPIO_SECCFGR_SEC10_Pos              (10U)
11958 #define GPIO_SECCFGR_SEC10_Msk              (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
11959 #define GPIO_SECCFGR_SEC10                  GPIO_SECCFGR_SEC10_Msk
11960 #define GPIO_SECCFGR_SEC11_Pos              (11U)
11961 #define GPIO_SECCFGR_SEC11_Msk              (x1UL << GPIO_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
11962 #define GPIO_SECCFGR_SEC11                  GPIO_SECCFGR_SEC11_Msk
11963 #define GPIO_SECCFGR_SEC12_Pos              (12U)
11964 #define GPIO_SECCFGR_SEC12_Msk              (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
11965 #define GPIO_SECCFGR_SEC12                  GPIO_SECCFGR_SEC12_Msk
11966 #define GPIO_SECCFGR_SEC13_Pos              (13U)
11967 #define GPIO_SECCFGR_SEC13_Msk              (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
11968 #define GPIO_SECCFGR_SEC13                  GPIO_SECCFGR_SEC13_Msk
11969 #define GPIO_SECCFGR_SEC14_Pos              (14U)
11970 #define GPIO_SECCFGR_SEC14_Msk              (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
11971 #define GPIO_SECCFGR_SEC14                  GPIO_SECCFGR_SEC14_Msk
11972 #define GPIO_SECCFGR_SEC15_Pos              (15U)
11973 #define GPIO_SECCFGR_SEC15_Msk              (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
11974 #define GPIO_SECCFGR_SEC15                  GPIO_SECCFGR_SEC15_Msk
11975 
11976 /******************************************************************************/
11977 /*                                                                            */
11978 /*                                 ICACHE                                     */
11979 /*                                                                            */
11980 /******************************************************************************/
11981 /******************  Bit definition for ICACHE_CR register  *******************/
11982 #define ICACHE_CR_EN_Pos                    (0U)
11983 #define ICACHE_CR_EN_Msk                    (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
11984 #define ICACHE_CR_EN                        ICACHE_CR_EN_Msk                        /*!< Enable */
11985 #define ICACHE_CR_CACHEINV_Pos              (1U)
11986 #define ICACHE_CR_CACHEINV_Msk              (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
11987 #define ICACHE_CR_CACHEINV                  ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
11988 #define ICACHE_CR_WAYSEL_Pos                (2U)
11989 #define ICACHE_CR_WAYSEL_Msk                (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
11990 #define ICACHE_CR_WAYSEL                    ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
11991 #define ICACHE_CR_HITMEN_Pos                (16U)
11992 #define ICACHE_CR_HITMEN_Msk                (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
11993 #define ICACHE_CR_HITMEN                    ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
11994 #define ICACHE_CR_MISSMEN_Pos               (17U)
11995 #define ICACHE_CR_MISSMEN_Msk               (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
11996 #define ICACHE_CR_MISSMEN                   ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
11997 #define ICACHE_CR_HITMRST_Pos               (18U)
11998 #define ICACHE_CR_HITMRST_Msk               (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
11999 #define ICACHE_CR_HITMRST                   ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
12000 #define ICACHE_CR_MISSMRST_Pos              (19U)
12001 #define ICACHE_CR_MISSMRST_Msk              (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
12002 #define ICACHE_CR_MISSMRST                  ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
12003 
12004 /******************  Bit definition for ICACHE_SR register  *******************/
12005 #define ICACHE_SR_BUSYF_Pos                 (0U)
12006 #define ICACHE_SR_BUSYF_Msk                 (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
12007 #define ICACHE_SR_BUSYF                     ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
12008 #define ICACHE_SR_BSYENDF_Pos               (1U)
12009 #define ICACHE_SR_BSYENDF_Msk               (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
12010 #define ICACHE_SR_BSYENDF                   ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
12011 #define ICACHE_SR_ERRF_Pos                  (2U)
12012 #define ICACHE_SR_ERRF_Msk                  (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
12013 #define ICACHE_SR_ERRF                      ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
12014 
12015 /******************  Bit definition for ICACHE_IER register  ******************/
12016 #define ICACHE_IER_BSYENDIE_Pos             (1U)
12017 #define ICACHE_IER_BSYENDIE_Msk             (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
12018 #define ICACHE_IER_BSYENDIE                 ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
12019 #define ICACHE_IER_ERRIE_Pos                (2U)
12020 #define ICACHE_IER_ERRIE_Msk                (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
12021 #define ICACHE_IER_ERRIE                    ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
12022 
12023 /******************  Bit definition for ICACHE_FCR register  ******************/
12024 #define ICACHE_FCR_CBSYENDF_Pos             (1U)
12025 #define ICACHE_FCR_CBSYENDF_Msk             (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
12026 #define ICACHE_FCR_CBSYENDF                 ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
12027 #define ICACHE_FCR_CERRF_Pos                (2U)
12028 #define ICACHE_FCR_CERRF_Msk                (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
12029 #define ICACHE_FCR_CERRF                    ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
12030 
12031 /******************  Bit definition for ICACHE_HMONR register  ****************/
12032 #define ICACHE_HMONR_HITMON_Pos             (0U)
12033 #define ICACHE_HMONR_HITMON_Msk             (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */
12034 #define ICACHE_HMONR_HITMON                 ICACHE_HMONR_HITMON_Msk                 /*!< Cache hit monitor register */
12035 
12036 /******************  Bit definition for ICACHE_MMONR register  ****************/
12037 #define ICACHE_MMONR_MISSMON_Pos            (0U)
12038 #define ICACHE_MMONR_MISSMON_Msk            (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x0000FFFF */
12039 #define ICACHE_MMONR_MISSMON                ICACHE_MMONR_MISSMON_Msk                /*!< Cache miss monitor register */
12040 
12041 /******************  Bit definition for ICACHE_CRRx register  *****************/
12042 #define ICACHE_CRRx_BASEADDR_Pos            (0U)
12043 #define ICACHE_CRRx_BASEADDR_Msk            (0xFFUL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x000000FF */
12044 #define ICACHE_CRRx_BASEADDR                ICACHE_CRRx_BASEADDR_Msk                /*!< Base address of region X to remap */
12045 #define ICACHE_CRRx_RSIZE_Pos               (9U)
12046 #define ICACHE_CRRx_RSIZE_Msk               (0x7UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000E00 */
12047 #define ICACHE_CRRx_RSIZE                   ICACHE_CRRx_RSIZE_Msk                   /*!< Region X size */
12048 #define ICACHE_CRRx_RSIZE_0                 (0x1UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000200 */
12049 #define ICACHE_CRRx_RSIZE_1                 (0x2UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000400 */
12050 #define ICACHE_CRRx_RSIZE_2                 (0x4UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000800 */
12051 #define ICACHE_CRRx_REN_Pos                 (15U)
12052 #define ICACHE_CRRx_REN_Msk                 (0x1UL << ICACHE_CRRx_REN_Pos)          /*!< 0x00008000 */
12053 #define ICACHE_CRRx_REN                     ICACHE_CRRx_REN_Msk                     /*!< Region X enable */
12054 #define ICACHE_CRRx_REMAPADDR_Pos           (16U)
12055 #define ICACHE_CRRx_REMAPADDR_Msk           (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x07FF0000 */
12056 #define ICACHE_CRRx_REMAPADDR               ICACHE_CRRx_REMAPADDR_Msk               /*!< Remap address of Region X to be remapped */
12057 #define ICACHE_CRRx_MSTSEL_Pos              (28U)
12058 #define ICACHE_CRRx_MSTSEL_Msk              (0x1UL << ICACHE_CRRx_MSTSEL_Pos)       /*!< 0x10000000 */
12059 #define ICACHE_CRRx_MSTSEL                  ICACHE_CRRx_MSTSEL_Msk                  /*!< Region X AHB cache master selection */
12060 #define ICACHE_CRRx_HBURST_Pos              (31U)
12061 #define ICACHE_CRRx_HBURST_Msk              (0x1UL << ICACHE_CRRx_HBURST_Pos)       /*!< 0x80000000 */
12062 #define ICACHE_CRRx_HBURST                  ICACHE_CRRx_HBURST_Msk                  /*!< Region X output burst type */
12063 
12064 
12065 /******************************************************************************/
12066 /*                                                                            */
12067 /*                                 DCACHE                                     */
12068 /*                                                                            */
12069 /******************************************************************************/
12070 /******************  Bit definition for DCACHE_CR register  *******************/
12071 #define DCACHE_CR_EN_Pos                    (0U)
12072 #define DCACHE_CR_EN_Msk                    (0x1UL << DCACHE_CR_EN_Pos)             /*!< 0x00000001 */
12073 #define DCACHE_CR_EN                        DCACHE_CR_EN_Msk                        /*!< Enable */
12074 #define DCACHE_CR_CACHEINV_Pos              (1U)
12075 #define DCACHE_CR_CACHEINV_Msk              (0x1UL << DCACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
12076 #define DCACHE_CR_CACHEINV                  DCACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
12077 #define DCACHE_CR_CACHECMD_Pos              (8U)
12078 #define DCACHE_CR_CACHECMD_Msk              (0x7UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000700 */
12079 #define DCACHE_CR_CACHECMD                  DCACHE_CR_CACHECMD_Msk                  /*!< Cache command */
12080 #define DCACHE_CR_CACHECMD_0                (0x1UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000100 */
12081 #define DCACHE_CR_CACHECMD_1                (0x2UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000200 */
12082 #define DCACHE_CR_CACHECMD_2                (0x4UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000400 */
12083 #define DCACHE_CR_STARTCMD_Pos              (11U)
12084 #define DCACHE_CR_STARTCMD_Msk              (0x1UL << DCACHE_CR_STARTCMD_Pos)       /*!< 0x00000800 */
12085 #define DCACHE_CR_STARTCMD                  DCACHE_CR_STARTCMD_Msk                  /*!< Start command */
12086 #define DCACHE_CR_RHITMEN_Pos               (16U)
12087 #define DCACHE_CR_RHITMEN_Msk               (0x1UL << DCACHE_CR_RHITMEN_Pos)        /*!< 0x00010000 */
12088 #define DCACHE_CR_RHITMEN                   DCACHE_CR_RHITMEN_Msk                   /*!< Read Hit monitor enable */
12089 #define DCACHE_CR_RMISSMEN_Pos              (17U)
12090 #define DCACHE_CR_RMISSMEN_Msk              (0x1UL << DCACHE_CR_RMISSMEN_Pos)       /*!< 0x00020000 */
12091 #define DCACHE_CR_RMISSMEN                  DCACHE_CR_RMISSMEN_Msk                  /*!< Read Miss monitor enable */
12092 #define DCACHE_CR_RHITMRST_Pos              (18U)
12093 #define DCACHE_CR_RHITMRST_Msk              (0x1UL << DCACHE_CR_RHITMRST_Pos)       /*!< 0x00040000 */
12094 #define DCACHE_CR_RHITMRST                  DCACHE_CR_RHITMRST_Msk                  /*!< Read Hit monitor reset */
12095 #define DCACHE_CR_RMISSMRST_Pos             (19U)
12096 #define DCACHE_CR_RMISSMRST_Msk             (0x1UL << DCACHE_CR_RMISSMRST_Pos)      /*!< 0x00080000 */
12097 #define DCACHE_CR_RMISSMRST                 DCACHE_CR_RMISSMRST_Msk                 /*!< Read Miss monitor reset */
12098 #define DCACHE_CR_WHITMEN_Pos               (20U)
12099 #define DCACHE_CR_WHITMEN_Msk               (0x1UL << DCACHE_CR_WHITMEN_Pos)        /*!< 0x00100000 */
12100 #define DCACHE_CR_WHITMEN                   DCACHE_CR_WHITMEN_Msk                   /*!< Write Hit monitor enable */
12101 #define DCACHE_CR_WMISSMEN_Pos              (21U)
12102 #define DCACHE_CR_WMISSMEN_Msk              (0x1UL << DCACHE_CR_WMISSMEN_Pos)       /*!< 0x00200000 */
12103 #define DCACHE_CR_WMISSMEN                  DCACHE_CR_WMISSMEN_Msk                  /*!< Write Miss monitor enable */
12104 #define DCACHE_CR_WHITMRST_Pos              (22U)
12105 #define DCACHE_CR_WHITMRST_Msk              (0x1UL << DCACHE_CR_WHITMRST_Pos)       /*!< 0x00400000 */
12106 #define DCACHE_CR_WHITMRST                  DCACHE_CR_WHITMRST_Msk                  /*!< Write Hit monitor reset */
12107 #define DCACHE_CR_WMISSMRST_Pos             (23U)
12108 #define DCACHE_CR_WMISSMRST_Msk             (0x1UL << DCACHE_CR_WMISSMRST_Pos)      /*!< 0x00800000 */
12109 #define DCACHE_CR_WMISSMRST                 DCACHE_CR_WMISSMRST_Msk                 /*!< Write Miss monitor reset */
12110 #define DCACHE_CR_HBURST_Pos                (31U)
12111 #define DCACHE_CR_HBURST_Msk                (0x1UL << DCACHE_CR_HBURST_Pos)         /*!< 0x80000000 */
12112 #define DCACHE_CR_HBURST                    DCACHE_CR_HBURST_Msk                    /*!< Read burst type */
12113 
12114 /******************  Bit definition for DCACHE_SR register  *******************/
12115 #define DCACHE_SR_BUSYF_Pos                 (0U)
12116 #define DCACHE_SR_BUSYF_Msk                 (0x1UL << DCACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
12117 #define DCACHE_SR_BUSYF                     DCACHE_SR_BUSYF_Msk                     /*!< Busy flag */
12118 #define DCACHE_SR_BSYENDF_Pos               (1U)
12119 #define DCACHE_SR_BSYENDF_Msk               (0x1UL << DCACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
12120 #define DCACHE_SR_BSYENDF                   DCACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
12121 #define DCACHE_SR_ERRF_Pos                  (2U)
12122 #define DCACHE_SR_ERRF_Msk                  (0x1UL << DCACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
12123 #define DCACHE_SR_ERRF                      DCACHE_SR_ERRF_Msk                      /*!< Cache error flag */
12124 #define DCACHE_SR_BUSYCMDF_Pos              (3U)
12125 #define DCACHE_SR_BUSYCMDF_Msk              (0x1UL << DCACHE_SR_BUSYCMDF_Pos)       /*!< 0x00000008 */
12126 #define DCACHE_SR_BUSYCMDF                  DCACHE_SR_BUSYCMDF_Msk                  /*!< Busy command flag */
12127 #define DCACHE_SR_CMDENDF_Pos               (4U)
12128 #define DCACHE_SR_CMDENDF_Msk               (0x1UL << DCACHE_SR_CMDENDF_Pos)        /*!< 0x00000010 */
12129 #define DCACHE_SR_CMDENDF                   DCACHE_SR_CMDENDF_Msk                   /*!< Command end flag */
12130 
12131 /******************  Bit definition for DCACHE_IER register  ******************/
12132 #define DCACHE_IER_BSYENDIE_Pos             (1U)
12133 #define DCACHE_IER_BSYENDIE_Msk             (0x1UL << DCACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
12134 #define DCACHE_IER_BSYENDIE                 DCACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
12135 #define DCACHE_IER_ERRIE_Pos                (2U)
12136 #define DCACHE_IER_ERRIE_Msk                (0x1UL << DCACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
12137 #define DCACHE_IER_ERRIE                    DCACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
12138 #define DCACHE_IER_CMDENDIE_Pos             (4U)
12139 #define DCACHE_IER_CMDENDIE_Msk             (0x1UL << DCACHE_IER_CMDENDIE_Pos)      /*!< 0x00000010 */
12140 #define DCACHE_IER_CMDENDIE                 DCACHE_IER_CMDENDIE_Msk                 /*!< Command end interrupt enable */
12141 
12142 /******************  Bit definition for DCACHE_FCR register  ******************/
12143 #define DCACHE_FCR_CBSYENDF_Pos             (1U)
12144 #define DCACHE_FCR_CBSYENDF_Msk             (0x1UL << DCACHE_FCR_CBSYENDF_Pos)       /*!< 0x00000002 */
12145 #define DCACHE_FCR_CBSYENDF                 DCACHE_FCR_CBSYENDF_Msk                  /*!< Busy end flag clear */
12146 #define DCACHE_FCR_CERRF_Pos                (2U)
12147 #define DCACHE_FCR_CERRF_Msk                (0x1UL << DCACHE_FCR_CERRF_Pos)          /*!< 0x00000004 */
12148 #define DCACHE_FCR_CERRF                    DCACHE_FCR_CERRF_Msk                     /*!< Cache error flag clear */
12149 #define DCACHE_FCR_CCMDENDF_Pos             (4U)
12150 #define DCACHE_FCR_CCMDENDF_Msk             (0x1UL << DCACHE_FCR_CCMDENDF_Pos)       /*!< 0x00000010 */
12151 #define DCACHE_FCR_CCMDENDF                 DCACHE_FCR_CCMDENDF_Msk                  /*!< Command end flag clear */
12152 
12153 /******************  Bit definition for DCACHE_RHMONR register  ****************/
12154 #define DCACHE_RHMONR_RHITMON_Pos           (0U)
12155 #define DCACHE_RHMONR_RHITMON_Msk           (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */
12156 #define DCACHE_RHMONR_RHITMON               DCACHE_RHMONR_RHITMON_Msk               /*!< Cache Read hit monitor register */
12157 
12158 /******************  Bit definition for DCACHE_RMMONR register  ****************/
12159 #define DCACHE_RMMONR_RMISSMON_Pos          (0U)
12160 #define DCACHE_RMMONR_RMISSMON_Msk          (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */
12161 #define DCACHE_RMMONR_RMISSMON              DCACHE_RMMONR_RMISSMON_Msk              /*!< Cache Read miss monitor register */
12162 
12163 /******************  Bit definition for DCACHE_WHMONR register  ****************/
12164 #define DCACHE_WHMONR_WHITMON_Pos           (0U)
12165 #define DCACHE_WHMONR_WHITMON_Msk           (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */
12166 #define DCACHE_WHMONR_WHITMON               DCACHE_WHMONR_WHITMON_Msk               /*!< Cache Read hit monitor register */
12167 
12168 /******************  Bit definition for DCACHE_WMMONR register  ****************/
12169 #define DCACHE_WMMONR_WMISSMON_Pos          (0U)
12170 #define DCACHE_WMMONR_WMISSMON_Msk          (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */
12171 #define DCACHE_WMMONR_WMISSMON              DCACHE_WMMONR_WMISSMON_Msk              /*!< Cache Read miss monitor register */
12172 
12173 /******************  Bit definition for DCACHE_CMDRSADDRR register  ****************/
12174 #define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos  (0U)
12175 #define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk  (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */
12176 #define DCACHE_CMDRSADDRR_CMDSTARTADDR      DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk      /*!< Command start address */
12177 
12178 /******************  Bit definition for DCACHE_CMDREADDRR register  ****************/
12179 #define DCACHE_CMDREADDRR_CMDENDADDR_Pos    (0U)
12180 #define DCACHE_CMDREADDRR_CMDENDADDR_Msk    (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */
12181 #define DCACHE_CMDREADDRR_CMDENDADDR        DCACHE_CMDREADDRR_CMDENDADDR_Msk        /*!< Command end address */
12182 
12183 /******************************************************************************/
12184 /*                                                                            */
12185 /*                    Digital Temperature Sensor (DTS)                        */
12186 /*                                                                            */
12187 /******************************************************************************/
12188 
12189 /******************  Bit definition for DTS_CFGR1 register  ******************/
12190 #define DTS_CFGR1_TS1_EN_Pos               (0U)
12191 #define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
12192 #define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */
12193 #define DTS_CFGR1_TS1_START_Pos            (4U)
12194 #define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
12195 #define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */
12196 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
12197 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
12198 #define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
12199 #define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
12200 #define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
12201 #define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
12202 #define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
12203 #define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
12204 #define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
12205 #define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */
12206 #define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
12207 #define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
12208 #define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
12209 #define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
12210 #define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
12211 #define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
12212 #define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
12213 #define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
12214 #define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
12215 #define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
12216 #define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
12217 #define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
12218 #define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
12219 
12220 /******************  Bit definition for DTS_T0VALR1 register  ******************/
12221 #define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
12222 #define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
12223 #define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */
12224 #define DTS_T0VALR1_TS1_T0_Pos             (16U)
12225 #define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
12226 #define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */
12227 
12228 /******************  Bit definition for DTS_RAMPVALR register  ******************/
12229 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
12230 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
12231 #define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
12232 
12233 /******************  Bit definition for DTS_ITR1 register      ******************/
12234 #define DTS_ITR1_TS1_LITTHD_Pos            (0U)
12235 #define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
12236 #define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */
12237 #define DTS_ITR1_TS1_HITTHD_Pos            (16U)
12238 #define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
12239 #define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */
12240 
12241 /******************  Bit definition for DTS_DR register        ******************/
12242 #define DTS_DR_TS1_MFREQ_Pos               (0U)
12243 #define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
12244 #define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */
12245 
12246 /******************  Bit definition for DTS_SR register        ******************/
12247 #define DTS_SR_TS1_ITEF_Pos                (0U)
12248 #define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
12249 #define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */
12250 #define DTS_SR_TS1_ITLF_Pos                (1U)
12251 #define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
12252 #define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */
12253 #define DTS_SR_TS1_ITHF_Pos                (2U)
12254 #define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
12255 #define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */
12256 #define DTS_SR_TS1_AITEF_Pos               (4U)
12257 #define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
12258 #define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */
12259 #define DTS_SR_TS1_AITLF_Pos               (5U)
12260 #define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
12261 #define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */
12262 #define DTS_SR_TS1_AITHF_Pos               (6U)
12263 #define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
12264 #define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */
12265 #define DTS_SR_TS1_RDY_Pos                 (15U)
12266 #define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
12267 #define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */
12268 
12269 /******************  Bit definition for DTS_ITENR register      ******************/
12270 #define DTS_ITENR_TS1_ITEEN_Pos            (0U)
12271 #define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
12272 #define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */
12273 #define DTS_ITENR_TS1_ITLEN_Pos            (1U)
12274 #define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
12275 #define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */
12276 #define DTS_ITENR_TS1_ITHEN_Pos            (2U)
12277 #define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
12278 #define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */
12279 #define DTS_ITENR_TS1_AITEEN_Pos           (4U)
12280 #define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
12281 #define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */
12282 #define DTS_ITENR_TS1_AITLEN_Pos           (5U)
12283 #define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
12284 #define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */
12285 #define DTS_ITENR_TS1_AITHEN_Pos           (6U)
12286 #define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
12287 #define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */
12288 
12289 /******************  Bit definition for DTS_ICIFR register      ******************/
12290 #define DTS_ICIFR_TS1_CITEF_Pos            (0U)
12291 #define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
12292 #define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */
12293 #define DTS_ICIFR_TS1_CITLF_Pos            (1U)
12294 #define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
12295 #define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */
12296 #define DTS_ICIFR_TS1_CITHF_Pos            (2U)
12297 #define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
12298 #define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */
12299 #define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
12300 #define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
12301 #define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
12302 #define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
12303 #define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
12304 #define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */
12305 #define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
12306 #define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
12307 #define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */
12308 
12309 /******************************************************************************/
12310 /*                                                                            */
12311 /*                                    TIM                                     */
12312 /*                                                                            */
12313 /******************************************************************************/
12314 /*******************  Bit definition for TIM_CR1 register  ********************/
12315 #define TIM_CR1_CEN_Pos                     (0U)
12316 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
12317 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
12318 #define TIM_CR1_UDIS_Pos                    (1U)
12319 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
12320 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
12321 #define TIM_CR1_URS_Pos                     (2U)
12322 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
12323 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
12324 #define TIM_CR1_OPM_Pos                     (3U)
12325 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
12326 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
12327 #define TIM_CR1_DIR_Pos                     (4U)
12328 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
12329 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
12330 #define TIM_CR1_CMS_Pos                     (5U)
12331 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
12332 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
12333 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
12334 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
12335 #define TIM_CR1_ARPE_Pos                    (7U)
12336 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
12337 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
12338 #define TIM_CR1_CKD_Pos                     (8U)
12339 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
12340 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
12341 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
12342 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
12343 #define TIM_CR1_UIFREMAP_Pos                (11U)
12344 #define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
12345 #define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
12346 #define TIM_CR1_DITHEN_Pos                  (12U)
12347 #define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
12348 #define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */
12349 
12350 /*******************  Bit definition for TIM_CR2 register  ********************/
12351 #define TIM_CR2_CCPC_Pos                    (0U)
12352 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
12353 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
12354 #define TIM_CR2_CCUS_Pos                    (2U)
12355 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
12356 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
12357 #define TIM_CR2_CCDS_Pos                    (3U)
12358 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
12359 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
12360 #define TIM_CR2_MMS_Pos                     (4U)
12361 #define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
12362 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
12363 #define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
12364 #define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
12365 #define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
12366 #define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
12367 #define TIM_CR2_TI1S_Pos                    (7U)
12368 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
12369 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
12370 #define TIM_CR2_OIS1_Pos                    (8U)
12371 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
12372 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
12373 #define TIM_CR2_OIS1N_Pos                   (9U)
12374 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
12375 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
12376 #define TIM_CR2_OIS2_Pos                    (10U)
12377 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
12378 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
12379 #define TIM_CR2_OIS2N_Pos                   (11U)
12380 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
12381 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
12382 #define TIM_CR2_OIS3_Pos                    (12U)
12383 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
12384 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
12385 #define TIM_CR2_OIS3N_Pos                   (13U)
12386 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
12387 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
12388 #define TIM_CR2_OIS4_Pos                    (14U)
12389 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
12390 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
12391 #define TIM_CR2_OIS4N_Pos                   (15U)
12392 #define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
12393 #define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
12394 #define TIM_CR2_OIS5_Pos                    (16U)
12395 #define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
12396 #define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
12397 #define TIM_CR2_OIS6_Pos                    (18U)
12398 #define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
12399 #define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
12400 #define TIM_CR2_MMS2_Pos                    (20U)
12401 #define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
12402 #define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
12403 #define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
12404 #define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
12405 #define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
12406 #define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */
12407 
12408 /*******************  Bit definition for TIM_SMCR register  *******************/
12409 #define TIM_SMCR_SMS_Pos                    (0U)
12410 #define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
12411 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
12412 #define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
12413 #define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
12414 #define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
12415 #define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
12416 #define TIM_SMCR_OCCS_Pos                   (3U)
12417 #define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)            /*!< 0x00000008 */
12418 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                       /*!< OCREF clear selection */
12419 #define TIM_SMCR_TS_Pos                     (4U)
12420 #define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
12421 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
12422 #define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
12423 #define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
12424 #define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
12425 #define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
12426 #define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
12427 #define TIM_SMCR_MSM_Pos                    (7U)
12428 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
12429 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
12430 #define TIM_SMCR_ETF_Pos                    (8U)
12431 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
12432 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
12433 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
12434 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
12435 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
12436 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
12437 #define TIM_SMCR_ETPS_Pos                   (12U)
12438 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
12439 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
12440 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
12441 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
12442 #define TIM_SMCR_ECE_Pos                    (14U)
12443 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
12444 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
12445 #define TIM_SMCR_ETP_Pos                    (15U)
12446 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
12447 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
12448 #define TIM_SMCR_SMSPE_Pos                  (24U)
12449 #define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
12450 #define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
12451 #define TIM_SMCR_SMSPS_Pos                  (25U)
12452 #define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
12453 #define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */
12454 
12455 /*******************  Bit definition for TIM_DIER register  *******************/
12456 #define TIM_DIER_UIE_Pos                    (0U)
12457 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
12458 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
12459 #define TIM_DIER_CC1IE_Pos                  (1U)
12460 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
12461 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
12462 #define TIM_DIER_CC2IE_Pos                  (2U)
12463 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
12464 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
12465 #define TIM_DIER_CC3IE_Pos                  (3U)
12466 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
12467 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
12468 #define TIM_DIER_CC4IE_Pos                  (4U)
12469 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
12470 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
12471 #define TIM_DIER_COMIE_Pos                  (5U)
12472 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
12473 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
12474 #define TIM_DIER_TIE_Pos                    (6U)
12475 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
12476 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
12477 #define TIM_DIER_BIE_Pos                    (7U)
12478 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
12479 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
12480 #define TIM_DIER_UDE_Pos                    (8U)
12481 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
12482 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
12483 #define TIM_DIER_CC1DE_Pos                  (9U)
12484 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
12485 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
12486 #define TIM_DIER_CC2DE_Pos                  (10U)
12487 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
12488 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
12489 #define TIM_DIER_CC3DE_Pos                  (11U)
12490 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
12491 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
12492 #define TIM_DIER_CC4DE_Pos                  (12U)
12493 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
12494 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
12495 #define TIM_DIER_COMDE_Pos                  (13U)
12496 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
12497 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
12498 #define TIM_DIER_TDE_Pos                    (14U)
12499 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
12500 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
12501 #define TIM_DIER_IDXIE_Pos                  (20U)
12502 #define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
12503 #define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
12504 #define TIM_DIER_DIRIE_Pos                  (21U)
12505 #define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
12506 #define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
12507 #define TIM_DIER_IERRIE_Pos                 (22U)
12508 #define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
12509 #define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
12510 #define TIM_DIER_TERRIE_Pos                 (23U)
12511 #define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
12512 #define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */
12513 
12514 /********************  Bit definition for TIM_SR register  ********************/
12515 #define TIM_SR_UIF_Pos                      (0U)
12516 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
12517 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
12518 #define TIM_SR_CC1IF_Pos                    (1U)
12519 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
12520 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
12521 #define TIM_SR_CC2IF_Pos                    (2U)
12522 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
12523 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
12524 #define TIM_SR_CC3IF_Pos                    (3U)
12525 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
12526 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
12527 #define TIM_SR_CC4IF_Pos                    (4U)
12528 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
12529 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
12530 #define TIM_SR_COMIF_Pos                    (5U)
12531 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
12532 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
12533 #define TIM_SR_TIF_Pos                      (6U)
12534 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
12535 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
12536 #define TIM_SR_BIF_Pos                      (7U)
12537 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
12538 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
12539 #define TIM_SR_B2IF_Pos                     (8U)
12540 #define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
12541 #define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
12542 #define TIM_SR_CC1OF_Pos                    (9U)
12543 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
12544 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
12545 #define TIM_SR_CC2OF_Pos                    (10U)
12546 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
12547 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
12548 #define TIM_SR_CC3OF_Pos                    (11U)
12549 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
12550 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
12551 #define TIM_SR_CC4OF_Pos                    (12U)
12552 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
12553 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
12554 #define TIM_SR_SBIF_Pos                     (13U)
12555 #define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
12556 #define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
12557 #define TIM_SR_CC5IF_Pos                    (16U)
12558 #define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
12559 #define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
12560 #define TIM_SR_CC6IF_Pos                    (17U)
12561 #define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
12562 #define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
12563 #define TIM_SR_IDXF_Pos                     (20U)
12564 #define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
12565 #define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
12566 #define TIM_SR_DIRF_Pos                     (21U)
12567 #define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
12568 #define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
12569 #define TIM_SR_IERRF_Pos                    (22U)
12570 #define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
12571 #define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
12572 #define TIM_SR_TERRF_Pos                    (23U)
12573 #define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
12574 #define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */
12575 
12576 /*******************  Bit definition for TIM_EGR register  ********************/
12577 #define TIM_EGR_UG_Pos                      (0U)
12578 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
12579 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
12580 #define TIM_EGR_CC1G_Pos                    (1U)
12581 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
12582 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
12583 #define TIM_EGR_CC2G_Pos                    (2U)
12584 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
12585 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
12586 #define TIM_EGR_CC3G_Pos                    (3U)
12587 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
12588 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
12589 #define TIM_EGR_CC4G_Pos                    (4U)
12590 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
12591 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
12592 #define TIM_EGR_COMG_Pos                    (5U)
12593 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
12594 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
12595 #define TIM_EGR_TG_Pos                      (6U)
12596 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
12597 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
12598 #define TIM_EGR_BG_Pos                      (7U)
12599 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
12600 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
12601 #define TIM_EGR_B2G_Pos                     (8U)
12602 #define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
12603 #define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */
12604 
12605 
12606 /******************  Bit definition for TIM_CCMR1 register  *******************/
12607 #define TIM_CCMR1_CC1S_Pos                  (0U)
12608 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
12609 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12610 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
12611 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
12612 #define TIM_CCMR1_OC1FE_Pos                 (2U)
12613 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
12614 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
12615 #define TIM_CCMR1_OC1PE_Pos                 (3U)
12616 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
12617 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
12618 #define TIM_CCMR1_OC1M_Pos                  (4U)
12619 #define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
12620 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
12621 #define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
12622 #define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
12623 #define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
12624 #define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
12625 #define TIM_CCMR1_OC1CE_Pos                 (7U)
12626 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
12627 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
12628 #define TIM_CCMR1_CC2S_Pos                  (8U)
12629 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
12630 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12631 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
12632 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
12633 #define TIM_CCMR1_OC2FE_Pos                 (10U)
12634 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
12635 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
12636 #define TIM_CCMR1_OC2PE_Pos                 (11U)
12637 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
12638 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
12639 #define TIM_CCMR1_OC2M_Pos                  (12U)
12640 #define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
12641 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
12642 #define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
12643 #define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
12644 #define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
12645 #define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
12646 #define TIM_CCMR1_OC2CE_Pos                 (15U)
12647 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
12648 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */
12649 
12650 /*----------------------------------------------------------------------------*/
12651 #define TIM_CCMR1_IC1PSC_Pos                (2U)
12652 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
12653 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12654 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
12655 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
12656 #define TIM_CCMR1_IC1F_Pos                  (4U)
12657 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
12658 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
12659 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
12660 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
12661 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
12662 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
12663 #define TIM_CCMR1_IC2PSC_Pos                (10U)
12664 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
12665 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
12666 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
12667 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
12668 #define TIM_CCMR1_IC2F_Pos                  (12U)
12669 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
12670 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
12671 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
12672 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
12673 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
12674 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */
12675 
12676 /******************  Bit definition for TIM_CCMR2 register  *******************/
12677 #define TIM_CCMR2_CC3S_Pos                  (0U)
12678 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
12679 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
12680 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
12681 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
12682 #define TIM_CCMR2_OC3FE_Pos                 (2U)
12683 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
12684 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
12685 #define TIM_CCMR2_OC3PE_Pos                 (3U)
12686 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
12687 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
12688 #define TIM_CCMR2_OC3M_Pos                  (4U)
12689 #define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
12690 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12691 #define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
12692 #define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
12693 #define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
12694 #define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
12695 #define TIM_CCMR2_OC3CE_Pos                 (7U)
12696 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
12697 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
12698 #define TIM_CCMR2_CC4S_Pos                  (8U)
12699 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
12700 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12701 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
12702 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
12703 #define TIM_CCMR2_OC4FE_Pos                 (10U)
12704 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
12705 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
12706 #define TIM_CCMR2_OC4PE_Pos                 (11U)
12707 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
12708 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
12709 #define TIM_CCMR2_OC4M_Pos                  (12U)
12710 #define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
12711 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12712 #define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
12713 #define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
12714 #define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
12715 #define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
12716 #define TIM_CCMR2_OC4CE_Pos                 (15U)
12717 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
12718 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */
12719 
12720 /*----------------------------------------------------------------------------*/
12721 #define TIM_CCMR2_IC3PSC_Pos                (2U)
12722 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
12723 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12724 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
12725 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
12726 #define TIM_CCMR2_IC3F_Pos                  (4U)
12727 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
12728 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12729 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
12730 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
12731 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
12732 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
12733 #define TIM_CCMR2_IC4PSC_Pos                (10U)
12734 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
12735 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12736 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
12737 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
12738 #define TIM_CCMR2_IC4F_Pos                  (12U)
12739 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
12740 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12741 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
12742 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
12743 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
12744 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */
12745 
12746 /******************  Bit definition for TIM_CCMR3 register  *******************/
12747 #define TIM_CCMR3_OC5FE_Pos                 (2U)
12748 #define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
12749 #define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
12750 #define TIM_CCMR3_OC5PE_Pos                 (3U)
12751 #define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
12752 #define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
12753 #define TIM_CCMR3_OC5M_Pos                  (4U)
12754 #define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
12755 #define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
12756 #define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
12757 #define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
12758 #define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
12759 #define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
12760 #define TIM_CCMR3_OC5CE_Pos                 (7U)
12761 #define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
12762 #define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
12763 #define TIM_CCMR3_OC6FE_Pos                 (10U)
12764 #define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
12765 #define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
12766 #define TIM_CCMR3_OC6PE_Pos                 (11U)
12767 #define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
12768 #define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
12769 #define TIM_CCMR3_OC6M_Pos                  (12U)
12770 #define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
12771 #define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
12772 #define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
12773 #define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
12774 #define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
12775 #define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
12776 #define TIM_CCMR3_OC6CE_Pos                 (15U)
12777 #define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
12778 #define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */
12779 
12780 /*******************  Bit definition for TIM_CCER register  *******************/
12781 #define TIM_CCER_CC1E_Pos                   (0U)
12782 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
12783 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
12784 #define TIM_CCER_CC1P_Pos                   (1U)
12785 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
12786 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
12787 #define TIM_CCER_CC1NE_Pos                  (2U)
12788 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
12789 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
12790 #define TIM_CCER_CC1NP_Pos                  (3U)
12791 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
12792 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
12793 #define TIM_CCER_CC2E_Pos                   (4U)
12794 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
12795 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
12796 #define TIM_CCER_CC2P_Pos                   (5U)
12797 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
12798 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
12799 #define TIM_CCER_CC2NE_Pos                  (6U)
12800 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
12801 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
12802 #define TIM_CCER_CC2NP_Pos                  (7U)
12803 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
12804 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
12805 #define TIM_CCER_CC3E_Pos                   (8U)
12806 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
12807 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
12808 #define TIM_CCER_CC3P_Pos                   (9U)
12809 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
12810 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
12811 #define TIM_CCER_CC3NE_Pos                  (10U)
12812 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
12813 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
12814 #define TIM_CCER_CC3NP_Pos                  (11U)
12815 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
12816 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
12817 #define TIM_CCER_CC4E_Pos                   (12U)
12818 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
12819 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
12820 #define TIM_CCER_CC4P_Pos                   (13U)
12821 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
12822 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
12823 #define TIM_CCER_CC4NE_Pos                  (14U)
12824 #define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
12825 #define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
12826 #define TIM_CCER_CC4NP_Pos                  (15U)
12827 #define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
12828 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
12829 #define TIM_CCER_CC5E_Pos                   (16U)
12830 #define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
12831 #define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
12832 #define TIM_CCER_CC5P_Pos                   (17U)
12833 #define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
12834 #define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
12835 #define TIM_CCER_CC6E_Pos                   (20U)
12836 #define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
12837 #define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
12838 #define TIM_CCER_CC6P_Pos                   (21U)
12839 #define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
12840 #define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */
12841 
12842 /*******************  Bit definition for TIM_CNT register  ********************/
12843 #define TIM_CNT_CNT_Pos                     (0U)
12844 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
12845 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
12846 #define TIM_CNT_UIFCPY_Pos                  (31U)
12847 #define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
12848 #define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */
12849 
12850 /*******************  Bit definition for TIM_PSC register  ********************/
12851 #define TIM_PSC_PSC_Pos                     (0U)
12852 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
12853 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */
12854 
12855 /*******************  Bit definition for TIM_ARR register  ********************/
12856 #define TIM_ARR_ARR_Pos                     (0U)
12857 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
12858 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */
12859 
12860 /*******************  Bit definition for TIM_RCR register  ********************/
12861 #define TIM_RCR_REP_Pos                     (0U)
12862 #define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
12863 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */
12864 
12865 /*******************  Bit definition for TIM_CCR1 register  *******************/
12866 #define TIM_CCR1_CCR1_Pos                   (0U)
12867 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)         /*!< 0x0000FFFF */
12868 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */
12869 
12870 /*******************  Bit definition for TIM_CCR2 register  *******************/
12871 #define TIM_CCR2_CCR2_Pos                   (0U)
12872 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)         /*!< 0x0000FFFF */
12873 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */
12874 
12875 /*******************  Bit definition for TIM_CCR3 register  *******************/
12876 #define TIM_CCR3_CCR3_Pos                   (0U)
12877 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)         /*!< 0x0000FFFF */
12878 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */
12879 
12880 /*******************  Bit definition for TIM_CCR4 register  *******************/
12881 #define TIM_CCR4_CCR4_Pos                   (0U)
12882 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)         /*!< 0x0000FFFF */
12883 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */
12884 
12885 /*******************  Bit definition for TIM_CCR5 register  *******************/
12886 #define TIM_CCR5_CCR5_Pos                   (0U)
12887 #define TIM_CCR5_CCR5_Msk                   (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)     /*!< 0xFFFFFFFF */
12888 #define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
12889 #define TIM_CCR5_GC5C1_Pos                  (29U)
12890 #define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
12891 #define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
12892 #define TIM_CCR5_GC5C2_Pos                  (30U)
12893 #define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
12894 #define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
12895 #define TIM_CCR5_GC5C3_Pos                  (31U)
12896 #define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
12897 #define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */
12898 
12899 /*******************  Bit definition for TIM_CCR6 register  *******************/
12900 #define TIM_CCR6_CCR6_Pos                   (0U)
12901 #define TIM_CCR6_CCR6_Msk                   (0xFFFFUL << TIM_CCR6_CCR6_Pos)         /*!< 0x0000FFFF */
12902 #define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */
12903 
12904 /*******************  Bit definition for TIM_BDTR register  *******************/
12905 #define TIM_BDTR_DTG_Pos                    (0U)
12906 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
12907 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12908 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
12909 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
12910 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
12911 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
12912 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
12913 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
12914 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
12915 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
12916 #define TIM_BDTR_LOCK_Pos                   (8U)
12917 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
12918 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
12919 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
12920 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
12921 #define TIM_BDTR_OSSI_Pos                   (10U)
12922 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
12923 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
12924 #define TIM_BDTR_OSSR_Pos                   (11U)
12925 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
12926 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
12927 #define TIM_BDTR_BKE_Pos                    (12U)
12928 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
12929 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
12930 #define TIM_BDTR_BKP_Pos                    (13U)
12931 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
12932 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
12933 #define TIM_BDTR_AOE_Pos                    (14U)
12934 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
12935 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
12936 #define TIM_BDTR_MOE_Pos                    (15U)
12937 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
12938 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
12939 #define TIM_BDTR_BKF_Pos                    (16U)
12940 #define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
12941 #define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
12942 #define TIM_BDTR_BK2F_Pos                   (20U)
12943 #define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
12944 #define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
12945 #define TIM_BDTR_BK2E_Pos                   (24U)
12946 #define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
12947 #define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
12948 #define TIM_BDTR_BK2P_Pos                   (25U)
12949 #define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
12950 #define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
12951 #define TIM_BDTR_BKDSRM_Pos                 (26U)
12952 #define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
12953 #define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
12954 #define TIM_BDTR_BK2DSRM_Pos                (27U)
12955 #define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
12956 #define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
12957 #define TIM_BDTR_BKBID_Pos                  (28U)
12958 #define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
12959 #define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
12960 #define TIM_BDTR_BK2BID_Pos                 (29U)
12961 #define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
12962 #define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */
12963 
12964 /*******************  Bit definition for TIM_DCR register  ********************/
12965 #define TIM_DCR_DBA_Pos                     (0U)
12966 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
12967 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
12968 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
12969 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
12970 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
12971 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
12972 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
12973 #define TIM_DCR_DBL_Pos                     (8U)
12974 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
12975 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
12976 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
12977 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
12978 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
12979 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
12980 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
12981 #define TIM_DCR_DBSS_Pos                    (16U)
12982 #define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x00000F00 */
12983 #define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
12984 #define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000100 */
12985 #define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000200 */
12986 #define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000400 */
12987 #define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000800 */
12988 
12989 /*******************  Bit definition for TIM1_AF1 register  *******************/
12990 #define TIM1_AF1_BKINE_Pos                  (0U)
12991 #define TIM1_AF1_BKINE_Msk                  (0x1UL << TIM1_AF1_BKINE_Pos)           /*!< 0x00000001 */
12992 #define TIM1_AF1_BKINE                      TIM1_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
12993 #define TIM1_AF1_BKCMP1E_Pos                (1U)
12994 #define TIM1_AF1_BKCMP1E_Msk                (0x1UL << TIM1_AF1_BKCMP1E_Pos)         /*!< 0x00000002 */
12995 #define TIM1_AF1_BKCMP1E                    TIM1_AF1_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
12996 #define TIM1_AF1_BKCMP2E_Pos                (2U)
12997 #define TIM1_AF1_BKCMP2E_Msk                (0x1UL << TIM1_AF1_BKCMP2E_Pos)         /*!< 0x00000004 */
12998 #define TIM1_AF1_BKCMP2E                    TIM1_AF1_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
12999 #define TIM1_AF1_BKDF1BK0E_Pos              (8U)
13000 #define TIM1_AF1_BKDF1BK0E_Msk              (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)       /*!< 0x00000100 */
13001 #define TIM1_AF1_BKDF1BK0E                  TIM1_AF1_BKDF1BK0E_Msk                  /*!<BRK mdf1_break[0](TIM1) or mdf1_break[2](TIM2) enable */
13002 #define TIM1_AF1_BKINP_Pos                  (9U)
13003 #define TIM1_AF1_BKINP_Msk                  (0x1UL << TIM1_AF1_BKINP_Pos)           /*!< 0x00000200 */
13004 #define TIM1_AF1_BKINP                      TIM1_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
13005 #define TIM1_AF1_BKCMP1P_Pos                (10U)
13006 #define TIM1_AF1_BKCMP1P_Msk                (0x1UL << TIM1_AF1_BKCMP1P_Pos)         /*!< 0x00000400 */
13007 #define TIM1_AF1_BKCMP1P                    TIM1_AF1_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
13008 #define TIM1_AF1_BKCMP2P_Pos                (11U)
13009 #define TIM1_AF1_BKCMP2P_Msk                (0x1UL << TIM1_AF1_BKCMP2P_Pos)         /*!< 0x00000800 */
13010 #define TIM1_AF1_BKCMP2P                    TIM1_AF1_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
13011 #define TIM1_AF1_ETRSEL_Pos                 (14U)
13012 #define TIM1_AF1_ETRSEL_Msk                 (0xFUL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x0003C000 */
13013 #define TIM1_AF1_ETRSEL                     TIM1_AF1_ETRSEL_Msk                     /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
13014 #define TIM1_AF1_ETRSEL_0                   (0x1UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00004000 */
13015 #define TIM1_AF1_ETRSEL_1                   (0x2UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00008000 */
13016 #define TIM1_AF1_ETRSEL_2                   (0x4UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00010000 */
13017 #define TIM1_AF1_ETRSEL_3                   (0x8UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00020000 */
13018 
13019 /*******************  Bit definition for TIM1_AF2 register  *********************/
13020 #define TIM1_AF2_BK2INE_Pos                 (0U)
13021 #define TIM1_AF2_BK2INE_Msk                 (0x1UL << TIM1_AF2_BK2INE_Pos)          /*!< 0x00000001 */
13022 #define TIM1_AF2_BK2INE                     TIM1_AF2_BK2INE_Msk                     /*!<BRK2 BKIN input enable */
13023 #define TIM1_AF2_BK2CMP1E_Pos               (1U)
13024 #define TIM1_AF2_BK2CMP1E_Msk               (0x1UL << TIM1_AF2_BK2CMP1E_Pos)        /*!< 0x00000002 */
13025 #define TIM1_AF2_BK2CMP1E                   TIM1_AF2_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
13026 #define TIM1_AF2_BK2CMP2E_Pos               (2U)
13027 #define TIM1_AF2_BK2CMP2E_Msk               (0x1UL << TIM1_AF2_BK2CMP2E_Pos)        /*!< 0x00000004 */
13028 #define TIM1_AF2_BK2CMP2E                   TIM1_AF2_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
13029 #define TIM1_AF2_BK2DF1BK1E_Pos             (8U)
13030 #define TIM1_AF2_BK2DF1BK1E_Msk             (0x1UL << TIM1_AF2_BK2DF1BK1E_Pos)      /*!< 0x00000100 */
13031 #define TIM1_AF2_BK2DF1BK1E                 TIM1_AF2_BK2DF1BK1E_Msk                 /*!<BRK2 mdf1_break[1](TIM1) or mdf1_break[3](TIM8) enable */
13032 #define TIM1_AF2_BK2INP_Pos                 (9U)
13033 #define TIM1_AF2_BK2INP_Msk                 (0x1UL << TIM1_AF2_BK2INP_Pos)          /*!< 0x00000200 */
13034 #define TIM1_AF2_BK2INP                     TIM1_AF2_BK2INP_Msk                     /*!<BRK2 BKIN input polarity */
13035 #define TIM1_AF2_BK2CMP1P_Pos               (10U)
13036 #define TIM1_AF2_BK2CMP1P_Msk               (0x1UL << TIM1_AF2_BK2CMP1P_Pos)        /*!< 0x00000400 */
13037 #define TIM1_AF2_BK2CMP1P                   TIM1_AF2_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
13038 #define TIM1_AF2_BK2CMP2P_Pos               (11U)
13039 #define TIM1_AF2_BK2CMP2P_Msk               (0x1UL << TIM1_AF2_BK2CMP2P_Pos)        /*!< 0x00000800 */
13040 #define TIM1_AF2_BK2CMP2P                   TIM1_AF2_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
13041 #define TIM1_AF2_OCRSEL_Pos                 (16U)
13042 #define TIM1_AF2_OCRSEL_Msk                 (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
13043 #define TIM1_AF2_OCRSEL                     TIM1_AF2_OCRSEL_Msk                     /*!<OCREF_CLR source selection */
13044 #define TIM1_AF2_OCRSEL_0                   (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
13045 
13046 /*******************  Bit definition for TIM_TISEL register  *********************/
13047 #define TIM_TISEL_TI1SEL_Pos                (0U)
13048 #define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
13049 #define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
13050 #define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
13051 #define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
13052 #define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
13053 #define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
13054 #define TIM_TISEL_TI2SEL_Pos                (8U)
13055 #define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
13056 #define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
13057 #define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
13058 #define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
13059 #define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
13060 #define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
13061 #define TIM_TISEL_TI3SEL_Pos                (16U)
13062 #define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
13063 #define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
13064 #define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
13065 #define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
13066 #define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
13067 #define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
13068 #define TIM_TISEL_TI4SEL_Pos                (24U)
13069 #define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
13070 #define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
13071 #define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
13072 #define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
13073 #define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
13074 #define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */
13075 
13076 /*******************  Bit definition for TIM_DTR2 register  *********************/
13077 #define TIM_DTR2_DTGF_Pos                   (0U)
13078 #define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
13079 #define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
13080 #define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
13081 #define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
13082 #define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
13083 #define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
13084 #define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
13085 #define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
13086 #define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
13087 #define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
13088 #define TIM_DTR2_DTAE_Pos                   (16U)
13089 #define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
13090 #define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
13091 #define TIM_DTR2_DTPE_Pos                   (17U)
13092 #define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
13093 #define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */
13094 
13095 /*******************  Bit definition for TIM_ECR register  *********************/
13096 #define TIM_ECR_IE_Pos                      (0U)
13097 #define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
13098 #define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
13099 #define TIM_ECR_IDIR_Pos                    (1U)
13100 #define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
13101 #define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
13102 #define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
13103 #define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
13104 #define TIM_ECR_IBLK_Pos                    (3U)
13105 #define TIM_ECR_IBLK_Msk                    (0x5UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
13106 #define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
13107 #define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
13108 #define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
13109 #define TIM_ECR_FIDX_Pos                    (5U)
13110 #define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
13111 #define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
13112 #define TIM_ECR_IPOS_Pos                    (6U)
13113 #define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x0000000C0 */
13114 #define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
13115 #define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000001 */
13116 #define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000002 */
13117 #define TIM_ECR_PW_Pos                      (16U)
13118 #define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
13119 #define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
13120 #define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
13121 #define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
13122 #define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
13123 #define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
13124 #define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
13125 #define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
13126 #define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
13127 #define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
13128 #define TIM_ECR_PWPRSC_Pos                  (24U)
13129 #define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
13130 #define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
13131 #define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
13132 #define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
13133 #define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */
13134 
13135 /*******************  Bit definition for TIM_DMAR register  *******************/
13136 #define TIM_DMAR_DMAB_Pos                   (0U)
13137 #define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
13138 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
13139 
13140 
13141 /******************************************************************************/
13142 /*                                                                            */
13143 /*                         Low Power Timer (LPTIM)                            */
13144 /*                                                                            */
13145 /******************************************************************************/
13146 /******************  Bit definition for LPTIM_ISR register  *******************/
13147 #define LPTIM_ISR_CC1IF_Pos                 (0U)
13148 #define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)          /*!< 0x00000001 */
13149 #define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                     /*!< Capture/Compare 1 interrupt flag */
13150 #define LPTIM_ISR_ARRM_Pos                  (1U)
13151 #define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
13152 #define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
13153 #define LPTIM_ISR_EXTTRIG_Pos               (2U)
13154 #define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
13155 #define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
13156 #define LPTIM_ISR_CMP1OK_Pos                (3U)
13157 #define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
13158 #define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
13159 #define LPTIM_ISR_ARROK_Pos                 (4U)
13160 #define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
13161 #define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
13162 #define LPTIM_ISR_UP_Pos                    (5U)
13163 #define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
13164 #define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
13165 #define LPTIM_ISR_DOWN_Pos                  (6U)
13166 #define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
13167 #define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
13168 #define LPTIM_ISR_UE_Pos                    (7U)
13169 #define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
13170 #define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
13171 #define LPTIM_ISR_REPOK_Pos                 (8U)
13172 #define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
13173 #define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
13174 #define LPTIM_ISR_CC2IF_Pos                 (9U)
13175 #define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
13176 #define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
13177 #define LPTIM_ISR_CC1OF_Pos                 (12U)
13178 #define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
13179 #define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
13180 #define LPTIM_ISR_CC2OF_Pos                 (13U)
13181 #define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
13182 #define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
13183 #define LPTIM_ISR_CMP2OK_Pos                (19U)
13184 #define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
13185 #define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
13186 #define LPTIM_ISR_DIEROK_Pos                (24U)
13187 #define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
13188 #define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */
13189 
13190 /******************  Bit definition for LPTIM_ICR register  *******************/
13191 #define LPTIM_ICR_CC1CF_Pos                 (0U)
13192 #define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
13193 #define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
13194 #define LPTIM_ICR_ARRMCF_Pos                (1U)
13195 #define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
13196 #define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
13197 #define LPTIM_ICR_EXTTRIGCF_Pos             (2U)
13198 #define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
13199 #define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
13200 #define LPTIM_ICR_CMP1OKCF_Pos              (3U)
13201 #define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
13202 #define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
13203 #define LPTIM_ICR_ARROKCF_Pos               (4U)
13204 #define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
13205 #define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
13206 #define LPTIM_ICR_UPCF_Pos                  (5U)
13207 #define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
13208 #define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
13209 #define LPTIM_ICR_DOWNCF_Pos                (6U)
13210 #define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
13211 #define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
13212 #define LPTIM_ICR_UECF_Pos                  (7U)
13213 #define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
13214 #define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
13215 #define LPTIM_ICR_REPOKCF_Pos               (8U)
13216 #define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
13217 #define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
13218 #define LPTIM_ICR_CC2CF_Pos                 (9U)
13219 #define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
13220 #define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
13221 #define LPTIM_ICR_CC1OCF_Pos                (12U)
13222 #define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
13223 #define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
13224 #define LPTIM_ICR_CC2OCF_Pos                (13U)
13225 #define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
13226 #define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
13227 #define LPTIM_ICR_CMP2OKCF_Pos              (19U)
13228 #define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
13229 #define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
13230 #define LPTIM_ICR_DIEROKCF_Pos              (24U)
13231 #define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
13232 #define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
13233 
13234 /******************  Bit definition for LPTIM_DIER register *******************/
13235 #define LPTIM_DIER_CC1IE_Pos                (0U)
13236 #define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
13237 #define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
13238 #define LPTIM_DIER_ARRMIE_Pos               (1U)
13239 #define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
13240 #define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
13241 #define LPTIM_DIER_EXTTRIGIE_Pos            (2U)
13242 #define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
13243 #define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
13244 #define LPTIM_DIER_CMP1OKIE_Pos             (3U)
13245 #define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
13246 #define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
13247 #define LPTIM_DIER_ARROKIE_Pos              (4U)
13248 #define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
13249 #define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
13250 #define LPTIM_DIER_UPIE_Pos                 (5U)
13251 #define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
13252 #define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
13253 #define LPTIM_DIER_DOWNIE_Pos               (6U)
13254 #define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
13255 #define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
13256 #define LPTIM_DIER_UEIE_Pos                 (7U)
13257 #define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
13258 #define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
13259 #define LPTIM_DIER_REPOKIE_Pos              (8U)
13260 #define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
13261 #define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
13262 #define LPTIM_DIER_CC2IE_Pos                (9U)
13263 #define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
13264 #define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
13265 #define LPTIM_DIER_CC1OIE_Pos               (12U)
13266 #define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
13267 #define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
13268 #define LPTIM_DIER_CC2OIE_Pos               (13U)
13269 #define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
13270 #define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
13271 #define LPTIM_DIER_CC1DE_Pos                (16U)
13272 #define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
13273 #define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
13274 #define LPTIM_DIER_CMP2OKIE_Pos             (19U)
13275 #define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
13276 #define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
13277 #define LPTIM_DIER_UEDE_Pos                 (23U)
13278 #define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
13279 #define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
13280 #define LPTIM_DIER_CC2DE_Pos                (25U)
13281 #define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
13282 #define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */
13283 
13284 /******************  Bit definition for LPTIM_CFGR register *******************/
13285 #define LPTIM_CFGR_CKSEL_Pos                (0U)
13286 #define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
13287 #define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
13288 #define LPTIM_CFGR_CKPOL_Pos                (1U)
13289 #define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
13290 #define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
13291 #define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
13292 #define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
13293 #define LPTIM_CFGR_CKFLT_Pos                (3U)
13294 #define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
13295 #define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
13296 #define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
13297 #define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
13298 #define LPTIM_CFGR_TRGFLT_Pos               (6U)
13299 #define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
13300 #define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
13301 #define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
13302 #define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
13303 #define LPTIM_CFGR_PRESC_Pos                (9U)
13304 #define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
13305 #define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
13306 #define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
13307 #define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
13308 #define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
13309 #define LPTIM_CFGR_TRIGSEL_Pos              (13U)
13310 #define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
13311 #define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
13312 #define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
13313 #define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
13314 #define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
13315 #define LPTIM_CFGR_TRIGEN_Pos               (17U)
13316 #define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
13317 #define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
13318 #define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
13319 #define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
13320 #define LPTIM_CFGR_TIMOUT_Pos               (19U)
13321 #define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
13322 #define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
13323 #define LPTIM_CFGR_WAVE_Pos                 (20U)
13324 #define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
13325 #define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
13326 #define LPTIM_CFGR_WAVPOL_Pos               (21U)
13327 #define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
13328 #define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
13329 #define LPTIM_CFGR_PRELOAD_Pos              (22U)
13330 #define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
13331 #define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
13332 #define LPTIM_CFGR_COUNTMODE_Pos            (23U)
13333 #define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
13334 #define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
13335 #define LPTIM_CFGR_ENC_Pos                  (24U)
13336 #define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
13337 #define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */
13338 
13339 /******************  Bit definition for LPTIM_CR register  ********************/
13340 #define LPTIM_CR_ENABLE_Pos                 (0U)
13341 #define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
13342 #define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
13343 #define LPTIM_CR_SNGSTRT_Pos                (1U)
13344 #define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
13345 #define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
13346 #define LPTIM_CR_CNTSTRT_Pos                (2U)
13347 #define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
13348 #define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
13349 #define LPTIM_CR_COUNTRST_Pos               (3U)
13350 #define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
13351 #define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
13352 #define LPTIM_CR_RSTARE_Pos                 (4U)
13353 #define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
13354 #define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/
13355 
13356 
13357 /******************  Bit definition for LPTIM_CCR1 register  ******************/
13358 #define LPTIM_CCR1_CCR1_Pos                 (0U)
13359 #define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
13360 #define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */
13361 
13362 /******************  Bit definition for LPTIM_ARR register  *******************/
13363 #define LPTIM_ARR_ARR_Pos                   (0U)
13364 #define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
13365 #define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */
13366 
13367 /******************  Bit definition for LPTIM_CNT register  *******************/
13368 #define LPTIM_CNT_CNT_Pos                   (0U)
13369 #define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
13370 #define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */
13371 
13372 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
13373 #define LPTIM_CFGR2_IN1SEL_Pos              (0U)
13374 #define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
13375 #define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
13376 #define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
13377 #define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
13378 #define LPTIM_CFGR2_IN2SEL_Pos              (4U)
13379 #define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
13380 #define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
13381 #define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
13382 #define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
13383 #define LPTIM_CFGR2_IC1SEL_Pos              (16U)
13384 #define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
13385 #define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
13386 #define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
13387 #define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
13388 #define LPTIM_CFGR2_IC2SEL_Pos              (20U)
13389 #define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
13390 #define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
13391 #define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
13392 #define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */
13393 
13394 /******************  Bit definition for LPTIM_RCR register  *******************/
13395 #define LPTIM_RCR_REP_Pos                   (0U)
13396 #define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
13397 #define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */
13398 
13399 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
13400 #define LPTIM_CCMR1_CC1SEL_Pos              (0U)
13401 #define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
13402 #define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
13403 #define LPTIM_CCMR1_CC1E_Pos                (1U)
13404 #define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
13405 #define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
13406 #define LPTIM_CCMR1_CC1P_Pos                (2U)
13407 #define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
13408 #define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
13409 #define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
13410 #define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
13411 #define LPTIM_CCMR1_IC1PSC_Pos              (8U)
13412 #define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
13413 #define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
13414 #define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
13415 #define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
13416 #define LPTIM_CCMR1_IC1F_Pos                (12U)
13417 #define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
13418 #define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
13419 #define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
13420 #define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
13421 #define LPTIM_CCMR1_CC2SEL_Pos              (16U)
13422 #define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
13423 #define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
13424 #define LPTIM_CCMR1_CC2E_Pos                (17U)
13425 #define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
13426 #define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
13427 #define LPTIM_CCMR1_CC2P_Pos                (18U)
13428 #define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
13429 #define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
13430 #define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
13431 #define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
13432 #define LPTIM_CCMR1_IC2PSC_Pos              (24U)
13433 #define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
13434 #define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
13435 #define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
13436 #define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
13437 #define LPTIM_CCMR1_IC2F_Pos                (28U)
13438 #define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
13439 #define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
13440 #define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
13441 #define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */
13442 
13443 /******************  Bit definition for LPTIM_CCR2 register  ******************/
13444 #define LPTIM_CCR2_CCR2_Pos                 (0U)
13445 #define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
13446 #define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */
13447 
13448 /******************************************************************************/
13449 /*                                                                            */
13450 /*                Parallel Synchronous Slave Interface (PSSI )                */
13451 /*                                                                            */
13452 /******************************************************************************/
13453 /********************  Bit definition for PSSI_CR register  *******************/
13454 #define PSSI_CR_CKPOL_Pos                   (5U)
13455 #define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
13456 #define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
13457 #define PSSI_CR_DEPOL_Pos                   (6U)
13458 #define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
13459 #define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
13460 #define PSSI_CR_RDYPOL_Pos                  (8U)
13461 #define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
13462 #define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
13463 #define PSSI_CR_EDM_Pos                     (10U)
13464 #define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
13465 #define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
13466 #define PSSI_CR_ENABLE_Pos                  (14U)
13467 #define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
13468 #define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
13469 #define PSSI_CR_DERDYCFG_Pos                (18U)
13470 #define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
13471 #define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
13472 #define PSSI_CR_DMAEN_Pos                   (30U)
13473 #define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
13474 #define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
13475 #define PSSI_CR_OUTEN_Pos                   (31U)
13476 #define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
13477 #define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
13478 
13479 /********************  Bit definition for PSSI_SR register  *******************/
13480 #define PSSI_SR_RTT4B_Pos                   (2U)
13481 #define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
13482 #define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
13483 #define PSSI_SR_RTT1B_Pos                   (3U)
13484 #define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
13485 #define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
13486 
13487 /********************  Bit definition for PSSI_RIS register  *******************/
13488 #define PSSI_RIS_OVR_RIS_Pos                (1U)
13489 #define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
13490 #define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
13491 
13492 /********************  Bit definition for PSSI_IER register  *******************/
13493 #define PSSI_IER_OVR_IE_Pos                 (1U)
13494 #define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
13495 #define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
13496 
13497 /********************  Bit definition for PSSI_MIS register  *******************/
13498 #define PSSI_MIS_OVR_MIS_Pos                (1U)
13499 #define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
13500 #define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
13501 
13502 /********************  Bit definition for PSSI_ICR register  *******************/
13503 #define PSSI_ICR_OVR_ISC_Pos                (1U)
13504 #define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
13505 #define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
13506 
13507 /********************  Bit definition for PSSI_DR register  *******************/
13508 #define PSSI_DR_DR_Pos                      (0U)
13509 #define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
13510 #define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
13511 
13512 
13513 /******************************************************************************/
13514 /*                                                                            */
13515 /*                           SDMMC Interface                                  */
13516 /*                                                                            */
13517 /******************************************************************************/
13518 /******************  Bit definition for SDMMC_POWER register  ******************/
13519 #define SDMMC_POWER_PWRCTRL_Pos             (0U)
13520 #define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
13521 #define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
13522 #define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
13523 #define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
13524 #define SDMMC_POWER_VSWITCH_Pos             (2U)
13525 #define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
13526 #define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
13527 #define SDMMC_POWER_VSWITCHEN_Pos           (3U)
13528 #define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
13529 #define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
13530 #define SDMMC_POWER_DIRPOL_Pos              (4U)
13531 #define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
13532 #define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
13533 
13534 /******************  Bit definition for SDMMC_CLKCR register  ******************/
13535 #define SDMMC_CLKCR_CLKDIV_Pos              (0U)
13536 #define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
13537 #define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
13538 #define SDMMC_CLKCR_PWRSAV_Pos              (12U)
13539 #define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
13540 #define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
13541 #define SDMMC_CLKCR_WIDBUS_Pos              (14U)
13542 #define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
13543 #define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
13544 #define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
13545 #define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
13546 #define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
13547 #define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
13548 #define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
13549 #define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
13550 #define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
13551 #define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
13552 #define SDMMC_CLKCR_DDR_Pos                 (18U)
13553 #define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
13554 #define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
13555 #define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
13556 #define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
13557 #define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
13558 #define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
13559 #define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
13560 #define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
13561 #define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
13562 #define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
13563 
13564 /*******************  Bit definition for SDMMC_ARG register  *******************/
13565 #define SDMMC_ARG_CMDARG_Pos                (0U)
13566 #define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
13567 #define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
13568 
13569 /*******************  Bit definition for SDMMC_CMD register  *******************/
13570 #define SDMMC_CMD_CMDINDEX_Pos              (0U)
13571 #define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
13572 #define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
13573 #define SDMMC_CMD_CMDTRANS_Pos              (6U)
13574 #define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
13575 #define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
13576 #define SDMMC_CMD_CMDSTOP_Pos               (7U)
13577 #define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
13578 #define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
13579 #define SDMMC_CMD_WAITRESP_Pos              (8U)
13580 #define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
13581 #define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
13582 #define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
13583 #define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
13584 #define SDMMC_CMD_WAITINT_Pos               (10U)
13585 #define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
13586 #define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
13587 #define SDMMC_CMD_WAITPEND_Pos              (11U)
13588 #define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
13589 #define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
13590 #define SDMMC_CMD_CPSMEN_Pos                (12U)
13591 #define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
13592 #define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
13593 #define SDMMC_CMD_DTHOLD_Pos                (13U)
13594 #define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
13595 #define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
13596 #define SDMMC_CMD_BOOTMODE_Pos              (14U)
13597 #define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
13598 #define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
13599 #define SDMMC_CMD_BOOTEN_Pos                (15U)
13600 #define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
13601 #define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
13602 #define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
13603 #define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
13604 #define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
13605 
13606 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
13607 #define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
13608 #define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
13609 #define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
13610 
13611 /******************  Bit definition for SDMMC_RESP1 register  ******************/
13612 #define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
13613 #define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
13614 #define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
13615 
13616 /******************  Bit definition for SDMMC_RESP2 register  ******************/
13617 #define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
13618 #define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
13619 #define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
13620 
13621 /******************  Bit definition for SDMMC_RESP3 register  ******************/
13622 #define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
13623 #define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
13624 #define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
13625 
13626 /******************  Bit definition for SDMMC_RESP4 register  ******************/
13627 #define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
13628 #define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
13629 #define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
13630 
13631 /******************  Bit definition for SDMMC_DTIMER register  *****************/
13632 #define SDMMC_DTIMER_DATATIME_Pos           (0U)
13633 #define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
13634 #define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
13635 
13636 /******************  Bit definition for SDMMC_DLEN register  *******************/
13637 #define SDMMC_DLEN_DATALENGTH_Pos           (0U)
13638 #define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
13639 #define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
13640 
13641 /******************  Bit definition for SDMMC_DCTRL register  ******************/
13642 #define SDMMC_DCTRL_DTEN_Pos                (0U)
13643 #define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
13644 #define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
13645 #define SDMMC_DCTRL_DTDIR_Pos               (1U)
13646 #define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
13647 #define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
13648 #define SDMMC_DCTRL_DTMODE_Pos              (2U)
13649 #define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
13650 #define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
13651 #define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
13652 #define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
13653 #define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
13654 #define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
13655 #define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
13656 #define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
13657 #define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
13658 #define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
13659 #define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
13660 #define SDMMC_DCTRL_RWSTART_Pos             (8U)
13661 #define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
13662 #define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
13663 #define SDMMC_DCTRL_RWSTOP_Pos              (9U)
13664 #define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
13665 #define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
13666 #define SDMMC_DCTRL_RWMOD_Pos               (10U)
13667 #define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
13668 #define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
13669 #define SDMMC_DCTRL_SDIOEN_Pos              (11U)
13670 #define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
13671 #define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
13672 #define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
13673 #define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
13674 #define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
13675 #define SDMMC_DCTRL_FIFORST_Pos             (13U)
13676 #define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
13677 #define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
13678 
13679 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
13680 #define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
13681 #define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
13682 #define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
13683 
13684 /******************  Bit definition for SDMMC_STA register  ********************/
13685 #define SDMMC_STA_CCRCFAIL_Pos              (0U)
13686 #define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
13687 #define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
13688 #define SDMMC_STA_DCRCFAIL_Pos              (1U)
13689 #define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
13690 #define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
13691 #define SDMMC_STA_CTIMEOUT_Pos              (2U)
13692 #define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
13693 #define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
13694 #define SDMMC_STA_DTIMEOUT_Pos              (3U)
13695 #define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
13696 #define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
13697 #define SDMMC_STA_TXUNDERR_Pos              (4U)
13698 #define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
13699 #define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
13700 #define SDMMC_STA_RXOVERR_Pos               (5U)
13701 #define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
13702 #define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
13703 #define SDMMC_STA_CMDREND_Pos               (6U)
13704 #define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
13705 #define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
13706 #define SDMMC_STA_CMDSENT_Pos               (7U)
13707 #define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
13708 #define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
13709 #define SDMMC_STA_DATAEND_Pos               (8U)
13710 #define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
13711 #define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
13712 #define SDMMC_STA_DHOLD_Pos                 (9U)
13713 #define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
13714 #define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
13715 #define SDMMC_STA_DBCKEND_Pos               (10U)
13716 #define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
13717 #define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
13718 #define SDMMC_STA_DABORT_Pos                (11U)
13719 #define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
13720 #define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
13721 #define SDMMC_STA_DPSMACT_Pos               (12U)
13722 #define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
13723 #define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
13724 #define SDMMC_STA_CPSMACT_Pos               (13U)
13725 #define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
13726 #define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
13727 #define SDMMC_STA_TXFIFOHE_Pos              (14U)
13728 #define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
13729 #define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13730 #define SDMMC_STA_RXFIFOHF_Pos              (15U)
13731 #define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
13732 #define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13733 #define SDMMC_STA_TXFIFOF_Pos               (16U)
13734 #define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
13735 #define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
13736 #define SDMMC_STA_RXFIFOF_Pos               (17U)
13737 #define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
13738 #define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
13739 #define SDMMC_STA_TXFIFOE_Pos               (18U)
13740 #define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
13741 #define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
13742 #define SDMMC_STA_RXFIFOE_Pos               (19U)
13743 #define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
13744 #define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
13745 #define SDMMC_STA_BUSYD0_Pos                (20U)
13746 #define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
13747 #define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
13748 #define SDMMC_STA_BUSYD0END_Pos             (21U)
13749 #define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
13750 #define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
13751 #define SDMMC_STA_SDIOIT_Pos                (22U)
13752 #define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
13753 #define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
13754 #define SDMMC_STA_ACKFAIL_Pos               (23U)
13755 #define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
13756 #define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
13757 #define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
13758 #define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
13759 #define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
13760 #define SDMMC_STA_VSWEND_Pos                (25U)
13761 #define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
13762 #define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
13763 #define SDMMC_STA_CKSTOP_Pos                (26U)
13764 #define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
13765 #define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
13766 #define SDMMC_STA_IDMATE_Pos                (27U)
13767 #define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
13768 #define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
13769 #define SDMMC_STA_IDMABTC_Pos               (28U)
13770 #define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
13771 #define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
13772 
13773 /*******************  Bit definition for SDMMC_ICR register  *******************/
13774 #define SDMMC_ICR_CCRCFAILC_Pos             (0U)
13775 #define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
13776 #define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
13777 #define SDMMC_ICR_DCRCFAILC_Pos             (1U)
13778 #define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
13779 #define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
13780 #define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
13781 #define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
13782 #define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
13783 #define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
13784 #define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
13785 #define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
13786 #define SDMMC_ICR_TXUNDERRC_Pos             (4U)
13787 #define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
13788 #define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
13789 #define SDMMC_ICR_RXOVERRC_Pos              (5U)
13790 #define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
13791 #define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
13792 #define SDMMC_ICR_CMDRENDC_Pos              (6U)
13793 #define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
13794 #define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
13795 #define SDMMC_ICR_CMDSENTC_Pos              (7U)
13796 #define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
13797 #define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
13798 #define SDMMC_ICR_DATAENDC_Pos              (8U)
13799 #define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
13800 #define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
13801 #define SDMMC_ICR_DHOLDC_Pos                (9U)
13802 #define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
13803 #define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
13804 #define SDMMC_ICR_DBCKENDC_Pos              (10U)
13805 #define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
13806 #define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
13807 #define SDMMC_ICR_DABORTC_Pos               (11U)
13808 #define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
13809 #define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
13810 #define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
13811 #define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
13812 #define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
13813 #define SDMMC_ICR_SDIOITC_Pos               (22U)
13814 #define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
13815 #define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
13816 #define SDMMC_ICR_ACKFAILC_Pos              (23U)
13817 #define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
13818 #define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
13819 #define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
13820 #define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
13821 #define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
13822 #define SDMMC_ICR_VSWENDC_Pos               (25U)
13823 #define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
13824 #define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
13825 #define SDMMC_ICR_CKSTOPC_Pos               (26U)
13826 #define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
13827 #define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
13828 #define SDMMC_ICR_IDMATEC_Pos               (27U)
13829 #define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
13830 #define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
13831 #define SDMMC_ICR_IDMABTCC_Pos              (28U)
13832 #define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
13833 #define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
13834 
13835 /******************  Bit definition for SDMMC_MASK register  *******************/
13836 #define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
13837 #define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
13838 #define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
13839 #define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
13840 #define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
13841 #define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
13842 #define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
13843 #define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
13844 #define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
13845 #define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
13846 #define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
13847 #define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
13848 #define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
13849 #define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
13850 #define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
13851 #define SDMMC_MASK_RXOVERRIE_Pos            (5U)
13852 #define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
13853 #define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
13854 #define SDMMC_MASK_CMDRENDIE_Pos            (6U)
13855 #define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
13856 #define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
13857 #define SDMMC_MASK_CMDSENTIE_Pos            (7U)
13858 #define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
13859 #define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
13860 #define SDMMC_MASK_DATAENDIE_Pos            (8U)
13861 #define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
13862 #define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
13863 #define SDMMC_MASK_DHOLDIE_Pos              (9U)
13864 #define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
13865 #define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
13866 #define SDMMC_MASK_DBCKENDIE_Pos            (10U)
13867 #define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
13868 #define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
13869 #define SDMMC_MASK_DABORTIE_Pos             (11U)
13870 #define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
13871 #define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
13872 #define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
13873 #define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
13874 #define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
13875 #define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
13876 #define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
13877 #define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
13878 #define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
13879 #define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
13880 #define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
13881 #define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
13882 #define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
13883 #define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
13884 #define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
13885 #define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
13886 #define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
13887 #define SDMMC_MASK_SDIOITIE_Pos             (22U)
13888 #define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
13889 #define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
13890 #define SDMMC_MASK_ACKFAILIE_Pos            (23U)
13891 #define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
13892 #define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
13893 #define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
13894 #define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
13895 #define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
13896 #define SDMMC_MASK_VSWENDIE_Pos             (25U)
13897 #define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
13898 #define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
13899 #define SDMMC_MASK_CKSTOPIE_Pos             (26U)
13900 #define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
13901 #define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
13902 #define SDMMC_MASK_IDMABTCIE_Pos            (28U)
13903 #define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
13904 #define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
13905 
13906 /*****************  Bit definition for SDMMC_ACKTIME register  *****************/
13907 #define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
13908 #define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
13909 #define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
13910 
13911 /******************  Bit definition for SDMMC_FIFO register  *******************/
13912 #define SDMMC_FIFO_FIFODATA_Pos             (0U)
13913 #define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13914 #define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
13915 
13916 /******************  Bit definition for SDMMC_IDMACTRL register ****************/
13917 #define SDMMC_IDMA_IDMAEN_Pos               (0U)
13918 #define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
13919 #define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
13920 #define SDMMC_IDMA_IDMABMODE_Pos            (1U)
13921 #define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
13922 #define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
13923 
13924 /*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
13925 #define SDMMC_IDMABSIZE_IDMABNDT_Pos        (5U)
13926 #define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0xFFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0000FFE0 */
13927 #define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk            /*!< Number of transfers per buffer */
13928 
13929 /*****************  Bit definition for SDMMC_IDMABASER register  ***************/
13930 #define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
13931 
13932 /*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
13933 #define SDMMC_IDMALAR_IDMALA_Pos            (0U)
13934 #define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
13935 #define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
13936 #define SDMMC_IDMALAR_ABR_Pos               (29U)
13937 #define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
13938 #define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
13939 #define SDMMC_IDMALAR_ULS_Pos               (30U)
13940 #define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
13941 #define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
13942 #define SDMMC_IDMALAR_ULA_Pos               (31U)
13943 #define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
13944 #define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
13945 
13946 
13947 /*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
13948 #define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
13949 
13950 /******************************************************************************/
13951 /*                                                                            */
13952 /*                              XSPI (OCTOSPI)                                */
13953 /*                                                                            */
13954 /******************************************************************************/
13955 /*****************  Bit definition for XSPI_CR register  *******************/
13956 #define XSPI_CR_EN_Pos                      (0U)
13957 #define XSPI_CR_EN_Msk                      (0x1UL << XSPI_CR_EN_Pos)                    /*!< 0x00000001 */
13958 #define XSPI_CR_EN                          XSPI_CR_EN_Msk                               /*!< Enable */
13959 #define XSPI_CR_ABORT_Pos                   (1U)
13960 #define XSPI_CR_ABORT_Msk                   (0x1UL << XSPI_CR_ABORT_Pos)                 /*!< 0x00000002 */
13961 #define XSPI_CR_ABORT                       XSPI_CR_ABORT_Msk                            /*!< Abort request */
13962 #define XSPI_CR_DMAEN_Pos                   (2U)
13963 #define XSPI_CR_DMAEN_Msk                   (0x1UL << XSPI_CR_DMAEN_Pos)                 /*!< 0x00000004 */
13964 #define XSPI_CR_DMAEN                       XSPI_CR_DMAEN_Msk                            /*!< DMA Enable */
13965 #define XSPI_CR_TCEN_Pos                    (3U)
13966 #define XSPI_CR_TCEN_Msk                    (0x1UL << XSPI_CR_TCEN_Pos)                  /*!< 0x00000008 */
13967 #define XSPI_CR_TCEN                        XSPI_CR_TCEN_Msk                             /*!< Timeout Counter Enable */
13968 #define XSPI_CR_DMM_Pos                     (6U)
13969 #define XSPI_CR_DMM_Msk                     (0x1UL << XSPI_CR_DMM_Pos)                   /*!< 0x00000040 */
13970 #define XSPI_CR_DMM                         XSPI_CR_DMM_Msk                              /*!< Dual-memory configuration */
13971 #define XSPI_CR_MSEL_Pos                    (7U)
13972 #define XSPI_CR_MSEL_Msk                    (0x1UL << XSPI_CR_MSEL_Pos)                  /*!< 0x00000080 */
13973 #define XSPI_CR_MSEL                        XSPI_CR_MSEL_Msk                             /*!< Flash Select */
13974 #define XSPI_CR_FTHRES_Pos                  (8U)
13975 #define XSPI_CR_FTHRES_Msk                  (0x1FUL << XSPI_CR_FTHRES_Pos)               /*!< 0x00001F00 */
13976 #define XSPI_CR_FTHRES                      XSPI_CR_FTHRES_Msk                           /*!< FIFO Threshold Level */
13977 #define XSPI_CR_TEIE_Pos                    (16U)
13978 #define XSPI_CR_TEIE_Msk                    (0x1UL << XSPI_CR_TEIE_Pos)                  /*!< 0x00010000 */
13979 #define XSPI_CR_TEIE                        XSPI_CR_TEIE_Msk                             /*!< Transfer Error Interrupt Enable */
13980 #define XSPI_CR_TCIE_Pos                    (17U)
13981 #define XSPI_CR_TCIE_Msk                    (0x1UL << XSPI_CR_TCIE_Pos)                  /*!< 0x00020000 */
13982 #define XSPI_CR_TCIE                        XSPI_CR_TCIE_Msk                             /*!< Transfer Complete Interrupt Enable */
13983 #define XSPI_CR_FTIE_Pos                    (18U)
13984 #define XSPI_CR_FTIE_Msk                    (0x1UL << XSPI_CR_FTIE_Pos)                  /*!< 0x00040000 */
13985 #define XSPI_CR_FTIE                        XSPI_CR_FTIE_Msk                             /*!< FIFO Threshold Interrupt Enable */
13986 #define XSPI_CR_SMIE_Pos                    (19U)
13987 #define XSPI_CR_SMIE_Msk                    (0x1UL << XSPI_CR_SMIE_Pos)                  /*!< 0x00080000 */
13988 #define XSPI_CR_SMIE                        XSPI_CR_SMIE_Msk                             /*!< Status Match Interrupt Enable */
13989 #define XSPI_CR_TOIE_Pos                    (20U)
13990 #define XSPI_CR_TOIE_Msk                    (0x1UL << XSPI_CR_TOIE_Pos)                  /*!< 0x00100000 */
13991 #define XSPI_CR_TOIE                        XSPI_CR_TOIE_Msk                             /*!< TimeOut Interrupt Enable */
13992 #define XSPI_CR_APMS_Pos                    (22U)
13993 #define XSPI_CR_APMS_Msk                    (0x1UL << XSPI_CR_APMS_Pos)                  /*!< 0x00400000 */
13994 #define XSPI_CR_APMS                        XSPI_CR_APMS_Msk                             /*!< Automatic Poll Mode Stop */
13995 #define XSPI_CR_PMM_Pos                     (23U)
13996 #define XSPI_CR_PMM_Msk                     (0x1UL << XSPI_CR_PMM_Pos)                   /*!< 0x00800000 */
13997 #define XSPI_CR_PMM                         XSPI_CR_PMM_Msk                              /*!< Polling Match Mode */
13998 #define XSPI_CR_FMODE_Pos                   (28U)
13999 #define XSPI_CR_FMODE_Msk                   (0x3UL << XSPI_CR_FMODE_Pos)                 /*!< 0x30000000 */
14000 #define XSPI_CR_FMODE                       XSPI_CR_FMODE_Msk                            /*!< Functional Mode */
14001 #define XSPI_CR_FMODE_0                     (0x1UL << XSPI_CR_FMODE_Pos)                 /*!< 0x10000000 */
14002 #define XSPI_CR_FMODE_1                     (0x2UL << XSPI_CR_FMODE_Pos)                 /*!< 0x20000000 */
14003 
14004 /****************  Bit definition for XSPI_DCR1 register  ******************/
14005 #define XSPI_DCR1_CKMODE_Pos                (0U)
14006 #define XSPI_DCR1_CKMODE_Msk                (0x1UL << XSPI_DCR1_CKMODE_Pos)              /*!< 0x00000001 */
14007 #define XSPI_DCR1_CKMODE                    XSPI_DCR1_CKMODE_Msk                         /*!< Mode 0 / Mode 3 */
14008 #define XSPI_DCR1_FRCK_Pos                  (1U)
14009 #define XSPI_DCR1_FRCK_Msk                  (0x1UL << XSPI_DCR1_FRCK_Pos)                /*!< 0x00000002 */
14010 #define XSPI_DCR1_FRCK                      XSPI_DCR1_FRCK_Msk                           /*!< Free Running Clock */
14011 #define XSPI_DCR1_DLYBYP_Pos                (3U)
14012 #define XSPI_DCR1_DLYBYP_Msk                (0x1UL << XSPI_DCR1_DLYBYP_Pos)              /*!< 0x00000008 */
14013 #define XSPI_DCR1_DLYBYP                    XSPI_DCR1_DLYBYP_Msk
14014 #define XSPI_DCR1_CSHT_Pos                  (8U)
14015 #define XSPI_DCR1_CSHT_Msk                  (0x3FUL << XSPI_DCR1_CSHT_Pos)               /*!< 0x00003F00 */
14016 #define XSPI_DCR1_CSHT                      XSPI_DCR1_CSHT_Msk                           /*!< Chip Select High Time */
14017 #define XSPI_DCR1_DEVSIZE_Pos               (16U)
14018 #define XSPI_DCR1_DEVSIZE_Msk               (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)            /*!< 0x001F0000 */
14019 #define XSPI_DCR1_DEVSIZE                   XSPI_DCR1_DEVSIZE_Msk                        /*!< Device Size */
14020 #define XSPI_DCR1_MTYP_Pos                  (24U)
14021 #define XSPI_DCR1_MTYP_Msk                  (0x7UL << XSPI_DCR1_MTYP_Pos)                /*!< 0x07000000 */
14022 #define XSPI_DCR1_MTYP                      XSPI_DCR1_MTYP_Msk                           /*!< Memory Type */
14023 #define XSPI_DCR1_MTYP_0                    (0x1UL << XSPI_DCR1_MTYP_Pos)                /*!< 0x01000000 */
14024 #define XSPI_DCR1_MTYP_1                    (0x2UL << XSPI_DCR1_MTYP_Pos)                /*!< 0x02000000 */
14025 #define XSPI_DCR1_MTYP_2                    (0x4UL << XSPI_DCR1_MTYP_Pos)                /*!< 0x04000000 */
14026 
14027 /****************  Bit definition for XSPI_DCR2 register  ******************/
14028 #define XSPI_DCR2_PRESCALER_Pos             (0U)
14029 #define XSPI_DCR2_PRESCALER_Msk             (0xFFUL << XSPI_DCR2_PRESCALER_Pos)          /*!< 0x000000FF */
14030 #define XSPI_DCR2_PRESCALER                 XSPI_DCR2_PRESCALER_Msk                      /*!< Clock prescaler */
14031 #define XSPI_DCR2_WRAPSIZE_Pos              (16U)
14032 #define XSPI_DCR2_WRAPSIZE_Msk              (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)            /*!< 0x00070000 */
14033 #define XSPI_DCR2_WRAPSIZE                  XSPI_DCR2_WRAPSIZE_Msk                       /*!< Wrap Size */
14034 #define XSPI_DCR2_WRAPSIZE_0                (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)            /*!< 0x00010000 */
14035 #define XSPI_DCR2_WRAPSIZE_1                (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)            /*!< 0x00020000 */
14036 #define XSPI_DCR2_WRAPSIZE_2                (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)            /*!< 0x00040000 */
14037 
14038 /****************  Bit definition for XSPI_DCR3 register  ******************/
14039 #define XSPI_DCR3_CSBOUND_Pos               (16U)
14040 #define XSPI_DCR3_CSBOUND_Msk               (0x1FUL << XSPI_DCR3_CSBOUND_Pos)            /*!< 0x001F0000 */
14041 #define XSPI_DCR3_CSBOUND                   XSPI_DCR3_CSBOUND_Msk                        /*!< Maximum transfer */
14042 
14043 /****************  Bit definition for XSPI_DCR4 register  ******************/
14044 #define XSPI_DCR4_REFRESH_Pos               (0U)
14045 #define XSPI_DCR4_REFRESH_Msk               (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos)      /*!< 0xFFFFFFFF */
14046 #define XSPI_DCR4_REFRESH                   XSPI_DCR4_REFRESH_Msk                        /*!< Refresh rate */
14047 
14048 /*****************  Bit definition for XSPI_SR register  *******************/
14049 #define XSPI_SR_TEF_Pos                     (0U)
14050 #define XSPI_SR_TEF_Msk                     (0x1UL << XSPI_SR_TEF_Pos)                   /*!< 0x00000001 */
14051 #define XSPI_SR_TEF                         XSPI_SR_TEF_Msk                              /*!< Transfer Error Flag */
14052 #define XSPI_SR_TCF_Pos                     (1U)
14053 #define XSPI_SR_TCF_Msk                     (0x1UL << XSPI_SR_TCF_Pos)                   /*!< 0x00000002 */
14054 #define XSPI_SR_TCF                         XSPI_SR_TCF_Msk                              /*!< Transfer Complete Flag */
14055 #define XSPI_SR_FTF_Pos                     (2U)
14056 #define XSPI_SR_FTF_Msk                     (0x1UL << XSPI_SR_FTF_Pos)                   /*!< 0x00000004 */
14057 #define XSPI_SR_FTF                         XSPI_SR_FTF_Msk                              /*!< FIFO Threshold Flag */
14058 #define XSPI_SR_SMF_Pos                     (3U)
14059 #define XSPI_SR_SMF_Msk                     (0x1UL << XSPI_SR_SMF_Pos)                   /*!< 0x00000008 */
14060 #define XSPI_SR_SMF                         XSPI_SR_SMF_Msk                              /*!< Status Match Flag */
14061 #define XSPI_SR_TOF_Pos                     (4U)
14062 #define XSPI_SR_TOF_Msk                     (0x1UL << XSPI_SR_TOF_Pos)                   /*!< 0x00000010 */
14063 #define XSPI_SR_TOF                         XSPI_SR_TOF_Msk                              /*!< Timeout Flag */
14064 #define XSPI_SR_BUSY_Pos                    (5U)
14065 #define XSPI_SR_BUSY_Msk                    (0x1UL << XSPI_SR_BUSY_Pos)                  /*!< 0x00000020 */
14066 #define XSPI_SR_BUSY                        XSPI_SR_BUSY_Msk                             /*!< Busy */
14067 #define XSPI_SR_FLEVEL_Pos                  (8U)
14068 #define XSPI_SR_FLEVEL_Msk                  (0x3FUL << XSPI_SR_FLEVEL_Pos)               /*!< 0x00003F00 */
14069 #define XSPI_SR_FLEVEL                      XSPI_SR_FLEVEL_Msk                           /*!< FIFO Level */
14070 
14071 /****************  Bit definition for XSPI_FCR register  *******************/
14072 #define XSPI_FCR_CTEF_Pos                   (0U)
14073 #define XSPI_FCR_CTEF_Msk                   (0x1UL << XSPI_FCR_CTEF_Pos)                 /*!< 0x00000001 */
14074 #define XSPI_FCR_CTEF                       XSPI_FCR_CTEF_Msk                            /*!< Clear Transfer Error Flag */
14075 #define XSPI_FCR_CTCF_Pos                   (1U)
14076 #define XSPI_FCR_CTCF_Msk                   (0x1UL << XSPI_FCR_CTCF_Pos)                 /*!< 0x00000002 */
14077 #define XSPI_FCR_CTCF                       XSPI_FCR_CTCF_Msk                            /*!< Clear Transfer Complete Flag */
14078 #define XSPI_FCR_CSMF_Pos                   (3U)
14079 #define XSPI_FCR_CSMF_Msk                   (0x1UL << XSPI_FCR_CSMF_Pos)                 /*!< 0x00000008 */
14080 #define XSPI_FCR_CSMF                       XSPI_FCR_CSMF_Msk                            /*!< Clear Status Match Flag */
14081 #define XSPI_FCR_CTOF_Pos                   (4U)
14082 #define XSPI_FCR_CTOF_Msk                   (0x1UL << XSPI_FCR_CTOF_Pos)                 /*!< 0x00000010 */
14083 #define XSPI_FCR_CTOF                       XSPI_FCR_CTOF_Msk                            /*!< Clear Timeout Flag */
14084 
14085 /****************  Bit definition for XSPI_DLR register  *******************/
14086 #define XSPI_DLR_DL_Pos                     (0U)
14087 #define XSPI_DLR_DL_Msk                     (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)            /*!< 0xFFFFFFFF */
14088 #define XSPI_DLR_DL                         XSPI_DLR_DL_Msk                              /*!< Data Length */
14089 
14090 /*****************  Bit definition for XSPI_AR register  *******************/
14091 #define XSPI_AR_ADDRESS_Pos                 (0U)
14092 #define XSPI_AR_ADDRESS_Msk                 (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos)        /*!< 0xFFFFFFFF */
14093 #define XSPI_AR_ADDRESS                     XSPI_AR_ADDRESS_Msk                          /*!< Address */
14094 
14095 /*****************  Bit definition for XSPI_DR register  *******************/
14096 #define XSPI_DR_DATA_Pos                    (0U)
14097 #define XSPI_DR_DATA_Msk                    (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)           /*!< 0xFFFFFFFF */
14098 #define XSPI_DR_DATA                        XSPI_DR_DATA_Msk                             /*!< Data */
14099 
14100 /***************  Bit definition for XSPI_PSMKR register  ******************/
14101 #define XSPI_PSMKR_MASK_Pos                 (0U)
14102 #define XSPI_PSMKR_MASK_Msk                 (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos)        /*!< 0xFFFFFFFF */
14103 #define XSPI_PSMKR_MASK                     XSPI_PSMKR_MASK_Msk                          /*!< Status mask */
14104 
14105 /***************  Bit definition for XSPI_PSMAR register  ******************/
14106 #define XSPI_PSMAR_MATCH_Pos                (0U)
14107 #define XSPI_PSMAR_MATCH_Msk                (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos)       /*!< 0xFFFFFFFF */
14108 #define XSPI_PSMAR_MATCH                    XSPI_PSMAR_MATCH_Msk                         /*!< Status match */
14109 
14110 /****************  Bit definition for XSPI_PIR register  *******************/
14111 #define XSPI_PIR_INTERVAL_Pos               (0U)
14112 #define XSPI_PIR_INTERVAL_Msk               (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)          /*!< 0x0000FFFF */
14113 #define XSPI_PIR_INTERVAL                   XSPI_PIR_INTERVAL_Msk                        /*!< Polling Interval */
14114 
14115 /****************  Bit definition for XSPI_CCR register  *******************/
14116 #define XSPI_CCR_IMODE_Pos                  (0U)
14117 #define XSPI_CCR_IMODE_Msk                  (0x7UL << XSPI_CCR_IMODE_Pos)                /*!< 0x00000007 */
14118 #define XSPI_CCR_IMODE                      XSPI_CCR_IMODE_Msk                           /*!< Instruction Mode */
14119 #define XSPI_CCR_IMODE_0                    (0x1UL << XSPI_CCR_IMODE_Pos)                /*!< 0x00000001 */
14120 #define XSPI_CCR_IMODE_1                    (0x2UL << XSPI_CCR_IMODE_Pos)                /*!< 0x00000002 */
14121 #define XSPI_CCR_IMODE_2                    (0x4UL << XSPI_CCR_IMODE_Pos)                /*!< 0x00000004 */
14122 #define XSPI_CCR_IDTR_Pos                   (3U)
14123 #define XSPI_CCR_IDTR_Msk                   (0x1UL << XSPI_CCR_IDTR_Pos)                 /*!< 0x00000008 */
14124 #define XSPI_CCR_IDTR                       XSPI_CCR_IDTR_Msk                            /*!< Instruction Double Transfer Rate */
14125 #define XSPI_CCR_ISIZE_Pos                  (4U)
14126 #define XSPI_CCR_ISIZE_Msk                  (0x3UL << XSPI_CCR_ISIZE_Pos)                /*!< 0x00000030 */
14127 #define XSPI_CCR_ISIZE                      XSPI_CCR_ISIZE_Msk                           /*!< Instruction Size */
14128 #define XSPI_CCR_ISIZE_0                    (0x1UL << XSPI_CCR_ISIZE_Pos)                /*!< 0x00000010 */
14129 #define XSPI_CCR_ISIZE_1                    (0x2UL << XSPI_CCR_ISIZE_Pos)                /*!< 0x00000020 */
14130 #define XSPI_CCR_ADMODE_Pos                 (8U)
14131 #define XSPI_CCR_ADMODE_Msk                 (0x7UL << XSPI_CCR_ADMODE_Pos)               /*!< 0x00000700 */
14132 #define XSPI_CCR_ADMODE                     XSPI_CCR_ADMODE_Msk                          /*!< Address Mode */
14133 #define XSPI_CCR_ADMODE_0                   (0x1UL << XSPI_CCR_ADMODE_Pos)               /*!< 0x00000100 */
14134 #define XSPI_CCR_ADMODE_1                   (0x2UL << XSPI_CCR_ADMODE_Pos)               /*!< 0x00000200 */
14135 #define XSPI_CCR_ADMODE_2                   (0x4UL << XSPI_CCR_ADMODE_Pos)               /*!< 0x00000400 */
14136 #define XSPI_CCR_ADDTR_Pos                  (11U)
14137 #define XSPI_CCR_ADDTR_Msk                  (0x1UL << XSPI_CCR_ADDTR_Pos)                /*!< 0x00000800 */
14138 #define XSPI_CCR_ADDTR                      XSPI_CCR_ADDTR_Msk                           /*!< Address Double Transfer Rate */
14139 #define XSPI_CCR_ADSIZE_Pos                 (12U)
14140 #define XSPI_CCR_ADSIZE_Msk                 (0x3UL << XSPI_CCR_ADSIZE_Pos)               /*!< 0x00003000 */
14141 #define XSPI_CCR_ADSIZE                     XSPI_CCR_ADSIZE_Msk                          /*!< Address Size */
14142 #define XSPI_CCR_ADSIZE_0                   (0x1UL << XSPI_CCR_ADSIZE_Pos)               /*!< 0x00001000 */
14143 #define XSPI_CCR_ADSIZE_1                   (0x2UL << XSPI_CCR_ADSIZE_Pos)               /*!< 0x00002000 */
14144 #define XSPI_CCR_ABMODE_Pos                 (16U)
14145 #define XSPI_CCR_ABMODE_Msk                 (0x7UL << XSPI_CCR_ABMODE_Pos)               /*!< 0x00070000 */
14146 #define XSPI_CCR_ABMODE                     XSPI_CCR_ABMODE_Msk                          /*!< Alternate Bytes Mode */
14147 #define XSPI_CCR_ABMODE_0                   (0x1UL << XSPI_CCR_ABMODE_Pos)               /*!< 0x00010000 */
14148 #define XSPI_CCR_ABMODE_1                   (0x2UL << XSPI_CCR_ABMODE_Pos)               /*!< 0x00020000 */
14149 #define XSPI_CCR_ABMODE_2                   (0x4UL << XSPI_CCR_ABMODE_Pos)               /*!< 0x00040000 */
14150 #define XSPI_CCR_ABDTR_Pos                  (19U)
14151 #define XSPI_CCR_ABDTR_Msk                  (0x1UL << XSPI_CCR_ABDTR_Pos)                /*!< 0x00080000 */
14152 #define XSPI_CCR_ABDTR                      XSPI_CCR_ABDTR_Msk                           /*!< Alternate Bytes Double Transfer Rate */
14153 #define XSPI_CCR_ABSIZE_Pos                 (20U)
14154 #define XSPI_CCR_ABSIZE_Msk                 (0x3UL << XSPI_CCR_ABSIZE_Pos)               /*!< 0x00300000 */
14155 #define XSPI_CCR_ABSIZE                     XSPI_CCR_ABSIZE_Msk                          /*!< Alternate Bytes Size */
14156 #define XSPI_CCR_ABSIZE_0                   (0x1UL << XSPI_CCR_ABSIZE_Pos)               /*!< 0x00100000 */
14157 #define XSPI_CCR_ABSIZE_1                   (0x2UL << XSPI_CCR_ABSIZE_Pos)               /*!< 0x00200000 */
14158 #define XSPI_CCR_DMODE_Pos                  (24U)
14159 #define XSPI_CCR_DMODE_Msk                  (0x7UL << XSPI_CCR_DMODE_Pos)                /*!< 0x07000000 */
14160 #define XSPI_CCR_DMODE                      XSPI_CCR_DMODE_Msk                           /*!< Data Mode */
14161 #define XSPI_CCR_DMODE_0                    (0x1UL << XSPI_CCR_DMODE_Pos)                /*!< 0x01000000 */
14162 #define XSPI_CCR_DMODE_1                    (0x2UL << XSPI_CCR_DMODE_Pos)                /*!< 0x02000000 */
14163 #define XSPI_CCR_DMODE_2                    (0x4UL << XSPI_CCR_DMODE_Pos)                /*!< 0x04000000 */
14164 #define XSPI_CCR_DDTR_Pos                   (27U)
14165 #define XSPI_CCR_DDTR_Msk                   (0x1UL << XSPI_CCR_DDTR_Pos)                 /*!< 0x08000000 */
14166 #define XSPI_CCR_DDTR                       XSPI_CCR_DDTR_Msk                            /*!< Data Double Transfer Rate */
14167 #define XSPI_CCR_DQSE_Pos                   (29U)
14168 #define XSPI_CCR_DQSE_Msk                   (0x1UL << XSPI_CCR_DQSE_Pos)                 /*!< 0x20000000 */
14169 #define XSPI_CCR_DQSE                       XSPI_CCR_DQSE_Msk                            /*!< DQS Enable */
14170 #define XSPI_CCR_SIOO_Pos                   (31U)
14171 #define XSPI_CCR_SIOO_Msk                   (0x1UL << XSPI_CCR_SIOO_Pos)                 /*!< 0x80000000 */
14172 #define XSPI_CCR_SIOO                       XSPI_CCR_SIOO_Msk                            /*!< Send Instruction Only Once Mode */
14173 
14174 /****************  Bit definition for XSPI_TCR register  *******************/
14175 #define XSPI_TCR_DCYC_Pos                   (0U)
14176 #define XSPI_TCR_DCYC_Msk                   (0x1FUL << XSPI_TCR_DCYC_Pos)                /*!< 0x0000001F */
14177 #define XSPI_TCR_DCYC                       XSPI_TCR_DCYC_Msk                            /*!< Number of Dummy Cycles */
14178 #define XSPI_TCR_DHQC_Pos                   (28U)
14179 #define XSPI_TCR_DHQC_Msk                   (0x1UL << XSPI_TCR_DHQC_Pos)                 /*!< 0x10000000 */
14180 #define XSPI_TCR_DHQC                       XSPI_TCR_DHQC_Msk                            /*!< Delay Hold Quarter Cycle */
14181 #define XSPI_TCR_SSHIFT_Pos                 (30U)
14182 #define XSPI_TCR_SSHIFT_Msk                 (0x1UL << XSPI_TCR_SSHIFT_Pos)               /*!< 0x40000000 */
14183 #define XSPI_TCR_SSHIFT                     XSPI_TCR_SSHIFT_Msk                          /*!< Sample Shift */
14184 
14185 /*****************  Bit definition for XSPI_IR register  *******************/
14186 #define XSPI_IR_INSTRUCTION_Pos             (0U)
14187 #define XSPI_IR_INSTRUCTION_Msk             (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos)    /*!< 0xFFFFFFFF */
14188 #define XSPI_IR_INSTRUCTION                 XSPI_IR_INSTRUCTION_Msk                      /*!< Instruction */
14189 
14190 /****************  Bit definition for XSPI_ABR register  *******************/
14191 #define XSPI_ABR_ALTERNATE_Pos              (0U)
14192 #define XSPI_ABR_ALTERNATE_Msk              (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos)     /*!< 0xFFFFFFFF */
14193 #define XSPI_ABR_ALTERNATE                  XSPI_ABR_ALTERNATE_Msk                       /*!< Alternate Bytes */
14194 
14195 /****************  Bit definition for XSPI_LPTR register  ******************/
14196 #define XSPI_LPTR_TIMEOUT_Pos               (0U)
14197 #define XSPI_LPTR_TIMEOUT_Msk               (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)          /*!< 0x0000FFFF */
14198 #define XSPI_LPTR_TIMEOUT                   XSPI_LPTR_TIMEOUT_Msk                        /*!< Timeout period */
14199 
14200 /****************  Bit definition for XSPI_WPCCR register  *******************/
14201 #define XSPI_WPCCR_IMODE_Pos                (0U)
14202 #define XSPI_WPCCR_IMODE_Msk                (0x7UL << XSPI_WPCCR_IMODE_Pos)              /*!< 0x00000007 */
14203 #define XSPI_WPCCR_IMODE                    XSPI_WPCCR_IMODE_Msk                         /*!< Instruction Mode */
14204 #define XSPI_WPCCR_IMODE_0                  (0x1UL << XSPI_WPCCR_IMODE_Pos)              /*!< 0x00000001 */
14205 #define XSPI_WPCCR_IMODE_1                  (0x2UL << XSPI_WPCCR_IMODE_Pos)              /*!< 0x00000002 */
14206 #define XSPI_WPCCR_IMODE_2                  (0x4UL << XSPI_WPCCR_IMODE_Pos)              /*!< 0x00000004 */
14207 #define XSPI_WPCCR_IDTR_Pos                 (3U)
14208 #define XSPI_WPCCR_IDTR_Msk                 (0x1UL << XSPI_WPCCR_IDTR_Pos)               /*!< 0x00000008 */
14209 #define XSPI_WPCCR_IDTR                     XSPI_WPCCR_IDTR_Msk                          /*!< Instruction Double Transfer Rate */
14210 #define XSPI_WPCCR_ISIZE_Pos                (4U)
14211 #define XSPI_WPCCR_ISIZE_Msk                (0x3UL << XSPI_WPCCR_ISIZE_Pos)              /*!< 0x00000030 */
14212 #define XSPI_WPCCR_ISIZE                    XSPI_WPCCR_ISIZE_Msk                         /*!< Instruction Size */
14213 #define XSPI_WPCCR_ISIZE_0                  (0x1UL << XSPI_WPCCR_ISIZE_Pos)              /*!< 0x00000010 */
14214 #define XSPI_WPCCR_ISIZE_1                  (0x2UL << XSPI_WPCCR_ISIZE_Pos)              /*!< 0x00000020 */
14215 #define XSPI_WPCCR_ADMODE_Pos               (8U)
14216 #define XSPI_WPCCR_ADMODE_Msk               (0x7UL << XSPI_WPCCR_ADMODE_Pos)             /*!< 0x00000700 */
14217 #define XSPI_WPCCR_ADMODE                   XSPI_WPCCR_ADMODE_Msk                        /*!< Address Mode */
14218 #define XSPI_WPCCR_ADMODE_0                 (0x1UL << XSPI_WPCCR_ADMODE_Pos)             /*!< 0x00000100 */
14219 #define XSPI_WPCCR_ADMODE_1                 (0x2UL << XSPI_WPCCR_ADMODE_Pos)             /*!< 0x00000200 */
14220 #define XSPI_WPCCR_ADMODE_2                 (0x4UL << XSPI_WPCCR_ADMODE_Pos)             /*!< 0x00000400 */
14221 #define XSPI_WPCCR_ADDTR_Pos                (11U)
14222 #define XSPI_WPCCR_ADDTR_Msk                (0x1UL << XSPI_WPCCR_ADDTR_Pos)              /*!< 0x00000800 */
14223 #define XSPI_WPCCR_ADDTR                    XSPI_WPCCR_ADDTR_Msk                         /*!< Address Double Transfer Rate */
14224 #define XSPI_WPCCR_ADSIZE_Pos               (12U)
14225 #define XSPI_WPCCR_ADSIZE_Msk               (0x3UL << XSPI_WPCCR_ADSIZE_Pos)             /*!< 0x00003000 */
14226 #define XSPI_WPCCR_ADSIZE                   XSPI_WPCCR_ADSIZE_Msk                        /*!< Address Size */
14227 #define XSPI_WPCCR_ADSIZE_0                 (0x1UL << XSPI_WPCCR_ADSIZE_Pos)             /*!< 0x00001000 */
14228 #define XSPI_WPCCR_ADSIZE_1                 (0x2UL << XSPI_WPCCR_ADSIZE_Pos)             /*!< 0x00002000 */
14229 #define XSPI_WPCCR_ABMODE_Pos               (16U)
14230 #define XSPI_WPCCR_ABMODE_Msk               (0x7UL << XSPI_WPCCR_ABMODE_Pos)             /*!< 0x00070000 */
14231 #define XSPI_WPCCR_ABMODE                   XSPI_WPCCR_ABMODE_Msk                        /*!< Alternate Bytes Mode */
14232 #define XSPI_WPCCR_ABMODE_0                 (0x1UL << XSPI_WPCCR_ABMODE_Pos)             /*!< 0x00010000 */
14233 #define XSPI_WPCCR_ABMODE_1                 (0x2UL << XSPI_WPCCR_ABMODE_Pos)             /*!< 0x00020000 */
14234 #define XSPI_WPCCR_ABMODE_2                 (0x4UL << XSPI_WPCCR_ABMODE_Pos)             /*!< 0x00040000 */
14235 #define XSPI_WPCCR_ABDTR_Pos                (19U)
14236 #define XSPI_WPCCR_ABDTR_Msk                (0x1UL << XSPI_WPCCR_ABDTR_Pos)              /*!< 0x00080000 */
14237 #define XSPI_WPCCR_ABDTR                    XSPI_WPCCR_ABDTR_Msk                         /*!< Alternate Bytes Double Transfer Rate */
14238 #define XSPI_WPCCR_ABSIZE_Pos               (20U)
14239 #define XSPI_WPCCR_ABSIZE_Msk               (0x3UL << XSPI_WPCCR_ABSIZE_Pos)             /*!< 0x00300000 */
14240 #define XSPI_WPCCR_ABSIZE                   XSPI_WPCCR_ABSIZE_Msk                        /*!< Alternate Bytes Size */
14241 #define XSPI_WPCCR_ABSIZE_0                 (0x1UL << XSPI_WPCCR_ABSIZE_Pos)             /*!< 0x00100000 */
14242 #define XSPI_WPCCR_ABSIZE_1                 (0x2UL << XSPI_WPCCR_ABSIZE_Pos)             /*!< 0x00200000 */
14243 #define XSPI_WPCCR_DMODE_Pos                (24U)
14244 #define XSPI_WPCCR_DMODE_Msk                (0x7UL << XSPI_WPCCR_DMODE_Pos)              /*!< 0x07000000 */
14245 #define XSPI_WPCCR_DMODE                    XSPI_WPCCR_DMODE_Msk                         /*!< Data Mode */
14246 #define XSPI_WPCCR_DMODE_0                  (0x1UL << XSPI_WPCCR_DMODE_Pos)              /*!< 0x01000000 */
14247 #define XSPI_WPCCR_DMODE_1                  (0x2UL << XSPI_WPCCR_DMODE_Pos)              /*!< 0x02000000 */
14248 #define XSPI_WPCCR_DMODE_2                  (0x4UL << XSPI_WPCCR_DMODE_Pos)              /*!< 0x04000000 */
14249 #define XSPI_WPCCR_DDTR_Pos                 (27U)
14250 #define XSPI_WPCCR_DDTR_Msk                 (0x1UL << XSPI_WPCCR_DDTR_Pos)               /*!< 0x08000000 */
14251 #define XSPI_WPCCR_DDTR                     XSPI_WPCCR_DDTR_Msk                          /*!< Data Double Transfer Rate */
14252 #define XSPI_WPCCR_DQSE_Pos                 (29U)
14253 #define XSPI_WPCCR_DQSE_Msk                 (0x1UL << XSPI_WPCCR_DQSE_Pos)               /*!< 0x20000000 */
14254 #define XSPI_WPCCR_DQSE                     XSPI_WPCCR_DQSE_Msk                          /*!< DQS Enable */
14255 
14256 /****************  Bit definition for XSPI_WPTCR register  *******************/
14257 #define XSPI_WPTCR_DCYC_Pos                 (0U)
14258 #define XSPI_WPTCR_DCYC_Msk                 (0x1FUL << XSPI_WPTCR_DCYC_Pos)              /*!< 0x0000001F */
14259 #define XSPI_WPTCR_DCYC                     XSPI_WPTCR_DCYC_Msk                          /*!< Number of Dummy Cycles */
14260 #define XSPI_WPTCR_DHQC_Pos                 (28U)
14261 #define XSPI_WPTCR_DHQC_Msk                 (0x1UL << XSPI_WPTCR_DHQC_Pos)               /*!< 0x10000000 */
14262 #define XSPI_WPTCR_DHQC                     XSPI_WPTCR_DHQC_Msk                          /*!< Delay Hold Quarter Cycle */
14263 #define XSPI_WPTCR_SSHIFT_Pos               (30U)
14264 #define XSPI_WPTCR_SSHIFT_Msk               (0x1UL << XSPI_WPTCR_SSHIFT_Pos)             /*!< 0x40000000 */
14265 #define XSPI_WPTCR_SSHIFT                   XSPI_WPTCR_SSHIFT_Msk                        /*!< Sample Shift */
14266 
14267 /*****************  Bit definition for XSPI_WPIR register  *******************/
14268 #define XSPI_WPIR_INSTRUCTION_Pos           (0U)
14269 #define XSPI_WPIR_INSTRUCTION_Msk           (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos)  /*!< 0xFFFFFFFF */
14270 #define XSPI_WPIR_INSTRUCTION               XSPI_WPIR_INSTRUCTION_Msk                    /*!< Instruction */
14271 
14272 /****************  Bit definition for XSPI_WPABR register  *******************/
14273 #define XSPI_WPABR_ALTERNATE_Pos            (0U)
14274 #define XSPI_WPABR_ALTERNATE_Msk            (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos)   /*!< 0xFFFFFFFF */
14275 #define XSPI_WPABR_ALTERNATE                XSPI_WPABR_ALTERNATE_Msk                     /*!< Alternate Bytes */
14276 
14277 /****************  Bit definition for XSPI_WCCR register  ******************/
14278 #define XSPI_WCCR_IMODE_Pos                 (0U)
14279 #define XSPI_WCCR_IMODE_Msk                 (0x7UL << XSPI_WCCR_IMODE_Pos)               /*!< 0x00000007 */
14280 #define XSPI_WCCR_IMODE                     XSPI_WCCR_IMODE_Msk                          /*!< Instruction Mode */
14281 #define XSPI_WCCR_IMODE_0                   (0x1UL << XSPI_WCCR_IMODE_Pos)               /*!< 0x00000001 */
14282 #define XSPI_WCCR_IMODE_1                   (0x2UL << XSPI_WCCR_IMODE_Pos)               /*!< 0x00000002 */
14283 #define XSPI_WCCR_IMODE_2                   (0x4UL << XSPI_WCCR_IMODE_Pos)               /*!< 0x00000004 */
14284 #define XSPI_WCCR_IDTR_Pos                  (3U)
14285 #define XSPI_WCCR_IDTR_Msk                  (0x1UL << XSPI_WCCR_IDTR_Pos)                /*!< 0x00000008 */
14286 #define XSPI_WCCR_IDTR                      XSPI_WCCR_IDTR_Msk                           /*!< Instruction Double Transfer Rate */
14287 #define XSPI_WCCR_ISIZE_Pos                 (4U)
14288 #define XSPI_WCCR_ISIZE_Msk                 (0x3UL << XSPI_WCCR_ISIZE_Pos)               /*!< 0x00000030 */
14289 #define XSPI_WCCR_ISIZE                     XSPI_WCCR_ISIZE_Msk                          /*!< Instruction Size */
14290 #define XSPI_WCCR_ISIZE_0                   (0x1UL << XSPI_WCCR_ISIZE_Pos)               /*!< 0x00000010 */
14291 #define XSPI_WCCR_ISIZE_1                   (0x2UL << XSPI_WCCR_ISIZE_Pos)               /*!< 0x00000020 */
14292 #define XSPI_WCCR_ADMODE_Pos                (8U)
14293 #define XSPI_WCCR_ADMODE_Msk                (0x7UL << XSPI_WCCR_ADMODE_Pos)              /*!< 0x00000700 */
14294 #define XSPI_WCCR_ADMODE                    XSPI_WCCR_ADMODE_Msk                         /*!< Address Mode */
14295 #define XSPI_WCCR_ADMODE_0                  (0x1UL << XSPI_WCCR_ADMODE_Pos)              /*!< 0x00000100 */
14296 #define XSPI_WCCR_ADMODE_1                  (0x2UL << XSPI_WCCR_ADMODE_Pos)              /*!< 0x00000200 */
14297 #define XSPI_WCCR_ADMODE_2                  (0x4UL << XSPI_WCCR_ADMODE_Pos)              /*!< 0x00000400 */
14298 #define XSPI_WCCR_ADDTR_Pos                 (11U)
14299 #define XSPI_WCCR_ADDTR_Msk                 (0x1UL << XSPI_WCCR_ADDTR_Pos)               /*!< 0x00000800 */
14300 #define XSPI_WCCR_ADDTR                     XSPI_WCCR_ADDTR_Msk                          /*!< Address Double Transfer Rate */
14301 #define XSPI_WCCR_ADSIZE_Pos                (12U)
14302 #define XSPI_WCCR_ADSIZE_Msk                (0x3UL << XSPI_WCCR_ADSIZE_Pos)              /*!< 0x00003000 */
14303 #define XSPI_WCCR_ADSIZE                    XSPI_WCCR_ADSIZE_Msk                         /*!< Address Size */
14304 #define XSPI_WCCR_ADSIZE_0                  (0x1UL << XSPI_WCCR_ADSIZE_Pos)              /*!< 0x00001000 */
14305 #define XSPI_WCCR_ADSIZE_1                  (0x2UL << XSPI_WCCR_ADSIZE_Pos)              /*!< 0x00002000 */
14306 #define XSPI_WCCR_ABMODE_Pos                (16U)
14307 #define XSPI_WCCR_ABMODE_Msk                (0x7UL << XSPI_WCCR_ABMODE_Pos)              /*!< 0x00070000 */
14308 #define XSPI_WCCR_ABMODE                    XSPI_WCCR_ABMODE_Msk                         /*!< Alternate Bytes Mode */
14309 #define XSPI_WCCR_ABMODE_0                  (0x1UL << XSPI_WCCR_ABMODE_Pos)              /*!< 0x00010000 */
14310 #define XSPI_WCCR_ABMODE_1                  (0x2UL << XSPI_WCCR_ABMODE_Pos)              /*!< 0x00020000 */
14311 #define XSPI_WCCR_ABMODE_2                  (0x4UL << XSPI_WCCR_ABMODE_Pos)              /*!< 0x00040000 */
14312 #define XSPI_WCCR_ABDTR_Pos                 (19U)
14313 #define XSPI_WCCR_ABDTR_Msk                 (0x1UL << XSPI_WCCR_ABDTR_Pos)               /*!< 0x00080000 */
14314 #define XSPI_WCCR_ABDTR                     XSPI_WCCR_ABDTR_Msk                          /*!< Alternate Bytes Double Transfer Rate */
14315 #define XSPI_WCCR_ABSIZE_Pos                (20U)
14316 #define XSPI_WCCR_ABSIZE_Msk                (0x3UL << XSPI_WCCR_ABSIZE_Pos)              /*!< 0x00300000 */
14317 #define XSPI_WCCR_ABSIZE                    XSPI_WCCR_ABSIZE_Msk                         /*!< Alternate Bytes Size */
14318 #define XSPI_WCCR_ABSIZE_0                  (0x1UL << XSPI_WCCR_ABSIZE_Pos)              /*!< 0x00100000 */
14319 #define XSPI_WCCR_ABSIZE_1                  (0x2UL << XSPI_WCCR_ABSIZE_Pos)              /*!< 0x00200000 */
14320 #define XSPI_WCCR_DMODE_Pos                 (24U)
14321 #define XSPI_WCCR_DMODE_Msk                 (0x7UL << XSPI_WCCR_DMODE_Pos)               /*!< 0x07000000 */
14322 #define XSPI_WCCR_DMODE                     XSPI_WCCR_DMODE_Msk                          /*!< Data Mode */
14323 #define XSPI_WCCR_DMODE_0                   (0x1UL << XSPI_WCCR_DMODE_Pos)               /*!< 0x01000000 */
14324 #define XSPI_WCCR_DMODE_1                   (0x2UL << XSPI_WCCR_DMODE_Pos)               /*!< 0x02000000 */
14325 #define XSPI_WCCR_DMODE_2                   (0x4UL << XSPI_WCCR_DMODE_Pos)               /*!< 0x04000000 */
14326 #define XSPI_WCCR_DDTR_Pos                  (27U)
14327 #define XSPI_WCCR_DDTR_Msk                  (0x1UL << XSPI_WCCR_DDTR_Pos)                /*!< 0x08000000 */
14328 #define XSPI_WCCR_DDTR                      XSPI_WCCR_DDTR_Msk                           /*!< Data Double Transfer Rate */
14329 #define XSPI_WCCR_DQSE_Pos                  (29U)
14330 #define XSPI_WCCR_DQSE_Msk                  (0x1UL << XSPI_WCCR_DQSE_Pos)                /*!< 0x20000000 */
14331 #define XSPI_WCCR_DQSE                      XSPI_WCCR_DQSE_Msk                           /*!< DQS Enable */
14332 
14333 /****************  Bit definition for XSPI_WTCR register  ******************/
14334 #define XSPI_WTCR_DCYC_Pos                  (0U)
14335 #define XSPI_WTCR_DCYC_Msk                  (0x1FUL << XSPI_WTCR_DCYC_Pos)               /*!< 0x0000001F */
14336 #define XSPI_WTCR_DCYC                      XSPI_WTCR_DCYC_Msk                           /*!< Number of Dummy Cycles */
14337 
14338 /****************  Bit definition for XSPI_WIR register  *******************/
14339 #define XSPI_WIR_INSTRUCTION_Pos            (0U)
14340 #define XSPI_WIR_INSTRUCTION_Msk            (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos)   /*!< 0xFFFFFFFF */
14341 #define XSPI_WIR_INSTRUCTION                XSPI_WIR_INSTRUCTION_Msk                     /*!< Instruction */
14342 
14343 /****************  Bit definition for XSPI_WABR register  ******************/
14344 #define XSPI_WABR_ALTERNATE_Pos             (0U)
14345 #define XSPI_WABR_ALTERNATE_Msk             (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos)    /*!< 0xFFFFFFFF */
14346 #define XSPI_WABR_ALTERNATE                 XSPI_WABR_ALTERNATE_Msk                      /*!< Alternate Bytes */
14347 
14348 /****************  Bit definition for XSPI_HLCR register  ******************/
14349 #define XSPI_HLCR_LM_Pos                    (0U)
14350 #define XSPI_HLCR_LM_Msk                    (0x1UL << XSPI_HLCR_LM_Pos)                  /*!< 0x00000001 */
14351 #define XSPI_HLCR_LM                        XSPI_HLCR_LM_Msk                             /*!< Latency Mode */
14352 #define XSPI_HLCR_WZL_Pos                   (1U)
14353 #define XSPI_HLCR_WZL_Msk                   (0x1UL << XSPI_HLCR_WZL_Pos)                 /*!< 0x00000002 */
14354 #define XSPI_HLCR_WZL                       XSPI_HLCR_WZL_Msk                            /*!< Write Zero Latency */
14355 #define XSPI_HLCR_TACC_Pos                  (8U)
14356 #define XSPI_HLCR_TACC_Msk                  (0xFFUL << XSPI_HLCR_TACC_Pos)               /*!< 0x0000FF00 */
14357 #define XSPI_HLCR_TACC                      XSPI_HLCR_TACC_Msk                           /*!< Access Time */
14358 #define XSPI_HLCR_TRWR_Pos                  (16U)
14359 #define XSPI_HLCR_TRWR_Msk                  (0xFFUL << XSPI_HLCR_TRWR_Pos)               /*!< 0x00FF0000 */
14360 #define XSPI_HLCR_TRWR                      XSPI_HLCR_TRWR_Msk                           /*!< Read Write Recovery Time */
14361 
14362 /******************************************************************************/
14363 /*                                                                            */
14364 /*                                    OCTOSPI                                 */
14365 /*                                                                            */
14366 /******************************************************************************/
14367 /*****************  Bit definition for OCTOSPI_CR register  *******************/
14368 #define OCTOSPI_CR_EN_Pos                   XSPI_CR_EN_Pos
14369 #define OCTOSPI_CR_EN_Msk                   XSPI_CR_EN_Msk                                /*!< 0x00000001 */
14370 #define OCTOSPI_CR_EN                       XSPI_CR_EN                                    /*!< Enable */
14371 #define OCTOSPI_CR_ABORT_Pos                XSPI_CR_ABORT_Pos
14372 #define OCTOSPI_CR_ABORT_Msk                XSPI_CR_ABORT_Msk                             /*!< 0x00000002 */
14373 #define OCTOSPI_CR_ABORT                    XSPI_CR_ABORT                                 /*!< Abort request */
14374 #define OCTOSPI_CR_DMAEN_Pos                XSPI_CR_DMAEN_Pos
14375 #define OCTOSPI_CR_DMAEN_Msk                XSPI_CR_DMAEN_Msk                             /*!< 0x00000004 */
14376 #define OCTOSPI_CR_DMAEN                    XSPI_CR_DMAEN                                 /*!< DMA Enable */
14377 #define OCTOSPI_CR_TCEN_Pos                 XSPI_CR_TCEN_Pos
14378 #define OCTOSPI_CR_TCEN_Msk                 XSPI_CR_TCEN_Msk                              /*!< 0x00000008 */
14379 #define OCTOSPI_CR_TCEN                     XSPI_CR_TCEN                                  /*!< Timeout Counter Enable */
14380 #define OCTOSPI_CR_DMM_Pos                  XSPI_CR_DMM_Pos
14381 #define OCTOSPI_CR_DMM_Msk                  XSPI_CR_DMM_Msk                               /*!< 0x00000040 */
14382 #define OCTOSPI_CR_DMM                      XSPI_CR_DMM                                   /*!< Dual Memory Mode */
14383 #define OCTOSPI_CR_MSEL_Pos                 XSPI_CR_MSEL_Pos
14384 #define OCTOSPI_CR_MSEL_Msk                 XSPI_CR_MSEL_Msk                              /*!< 0x00000080 */
14385 #define OCTOSPI_CR_MSEL                     XSPI_CR_MSEL                                  /*!< Flash Select */
14386 #define OCTOSPI_CR_FTHRES_Pos               XSPI_CR_FTHRES_Pos
14387 #define OCTOSPI_CR_FTHRES_Msk               XSPI_CR_FTHRES_Msk                            /*!< 0x00001F00 */
14388 #define OCTOSPI_CR_FTHRES                   XSPI_CR_FTHRES                                /*!< FIFO Threshold Level */
14389 #define OCTOSPI_CR_TEIE_Pos                 XSPI_CR_TEIE_Pos
14390 #define OCTOSPI_CR_TEIE_Msk                 XSPI_CR_TEIE_Msk                              /*!< 0x00010000 */
14391 #define OCTOSPI_CR_TEIE                     XSPI_CR_TEIE                                  /*!< Transfer Error Interrupt Enable */
14392 #define OCTOSPI_CR_TCIE_Pos                 XSPI_CR_TCIE_Pos
14393 #define OCTOSPI_CR_TCIE_Msk                 XSPI_CR_TCIE_Msk                              /*!< 0x00020000 */
14394 #define OCTOSPI_CR_TCIE                     XSPI_CR_TCIE                                  /*!< Transfer Complete Interrupt Enable */
14395 #define OCTOSPI_CR_FTIE_Pos                 XSPI_CR_FTIE_Pos
14396 #define OCTOSPI_CR_FTIE_Msk                 XSPI_CR_FTIE_Msk)                             /*!< 0x00040000 */
14397 #define OCTOSPI_CR_FTIE                     XSPI_CR_FTIE                                  /*!< FIFO Threshold Interrupt Enable */
14398 #define OCTOSPI_CR_SMIE_Pos                 XSPI_CR_SMIE_Pos
14399 #define OCTOSPI_CR_SMIE_Msk                 XSPI_CR_SMIE_Msk                              /*!< 0x00080000 */
14400 #define OCTOSPI_CR_SMIE                     XSPI_CR_SMIE                                  /*!< Status Match Interrupt Enable */
14401 #define OCTOSPI_CR_TOIE_Pos                 XSPI_CR_TOIE_Pos
14402 #define OCTOSPI_CR_TOIE_Msk                 XSPI_CR_TOIE_Msk                              /*!< 0x00100000 */
14403 #define OCTOSPI_CR_TOIE                     XSPI_CR_TOIE                                  /*!< TimeOut Interrupt Enable */
14404 #define OCTOSPI_CR_APMS_Pos                 XSPI_CR_APMS_Pos
14405 #define OCTOSPI_CR_APMS_Msk                 XSPI_CR_APMS_Msk                              /*!< 0x00400000 */
14406 #define OCTOSPI_CR_APMS                     XSPI_CR_APMS                                  /*!< Automatic Poll Mode Stop */
14407 #define OCTOSPI_CR_PMM_Pos                  XSPI_CR_PMM_Pos
14408 #define OCTOSPI_CR_PMM_Msk                  XSPI_CR_PMM_Msk                               /*!< 0x00800000 */
14409 #define OCTOSPI_CR_PMM                      XSPI_CR_PMM                                   /*!< Polling Match Mode */
14410 #define OCTOSPI_CR_FMODE_Pos                XSPI_CR_FMODE_Pos
14411 #define OCTOSPI_CR_FMODE_Msk                XSPI_CR_FMODE_Msk                             /*!< 0x30000000 */
14412 #define OCTOSPI_CR_FMODE                    XSPI_CR_FMODE                                 /*!< Functional Mode */
14413 #define OCTOSPI_CR_FMODE_0                  XSPI_CR_FMODE_0                               /*!< 0x10000000 */
14414 #define OCTOSPI_CR_FMODE_1                  XSPI_CR_FMODE_1                               /*!< 0x20000000 */
14415 
14416 /****************  Bit definition for OCTOSPI_DCR1 register  ******************/
14417 #define OCTOSPI_DCR1_CKMODE_Pos             XSPI_DCR1_CKMODE_Pos
14418 #define OCTOSPI_DCR1_CKMODE_Msk             XSPI_DCR1_CKMODE_Msk                          /*!< 0x00000001 */
14419 #define OCTOSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE                              /*!< Mode 0 / Mode 3 */
14420 #define OCTOSPI_DCR1_FRCK_Pos               XSPI_DCR1_FRCK_Pos
14421 #define OCTOSPI_DCR1_FRCK_Msk               XSPI_DCR1_FRCK_Msk                            /*!< 0x00000002 */
14422 #define OCTOSPI_DCR1_FRCK                   XSPI_DCR1_FRCK                                /*!< Free Running Clock */
14423 #define OCTOSPI_DCR1_DLYBYP_Pos             XSPI_DCR1_DLYBYP_Pos
14424 #define OCTOSPI_DCR1_DLYBYP_Msk             XSPI_DCR1_DLYBYP_Msk                          /*!< 0x00000008 */
14425 #define OCTOSPI_DCR1_DLYBYP                 XSPI_DCR1_DLYBYP                              /*!< Delay Block Bypass */
14426 #define OCTOSPI_DCR1_CSHT_Pos               XSPI_DCR1_CSHT_Pos
14427 #define OCTOSPI_DCR1_CSHT_Msk               XSPI_DCR1_CSHT_Msk                            /*!< 0x00003F00 */
14428 #define OCTOSPI_DCR1_CSHT                   XSPI_DCR1_CSHT                                /*!< Chip Select High Time */
14429 #define OCTOSPI_DCR1_DEVSIZE_Pos            XSPI_DCR1_DEVSIZE_Pos
14430 #define OCTOSPI_DCR1_DEVSIZE_Msk            XSPI_DCR1_DEVSIZE_Msk                         /*!< 0x001F0000 */
14431 #define OCTOSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE                             /*!< Device Size */
14432 #define OCTOSPI_DCR1_MTYP_Pos               XSPI_DCR1_MTYP_Pos
14433 #define OCTOSPI_DCR1_MTYP_Msk               XSPI_DCR1_MTYP_Msk                            /*!< 0x07000000 */
14434 #define OCTOSPI_DCR1_MTYP                   XSPI_DCR1_MTYP                                /*!< Memory Type */
14435 #define OCTOSPI_DCR1_MTYP_0                 XSPI_DCR1_MTYP_0                              /*!< 0x01000000 */
14436 #define OCTOSPI_DCR1_MTYP_1                 XSPI_DCR1_MTYP_1                              /*!< 0x02000000 */
14437 #define OCTOSPI_DCR1_MTYP_2                 XSPI_DCR1_MTYP_2                              /*!< 0x04000000 */
14438 
14439 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
14440 #define OCTOSPI_DCR2_PRESCALER_Pos          XSPI_DCR2_PRESCALER_Pos
14441 #define OCTOSPI_DCR2_PRESCALER_Msk          XSPI_DCR2_PRESCALER_Msk                       /*!< 0x000000FF */
14442 #define OCTOSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER                           /*!< Clock prescaler */
14443 #define OCTOSPI_DCR2_WRAPSIZE_Pos           XSPI_DCR2_WRAPSIZE_Pos
14444 #define OCTOSPI_DCR2_WRAPSIZE_Msk           XSPI_DCR2_WRAPSIZE_Msk                        /*!< 0x00070000 */
14445 #define OCTOSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE                            /*!< Wrap Size */
14446 #define OCTOSPI_DCR2_WRAPSIZE_0             XSPI_DCR2_WRAPSIZE_0                          /*!< 0x00010000 */
14447 #define OCTOSPI_DCR2_WRAPSIZE_1             XSPI_DCR2_WRAPSIZE_1                          /*!< 0x00020000 */
14448 #define OCTOSPI_DCR2_WRAPSIZE_2             XSPI_DCR2_WRAPSIZE_2                          /*!< 0x00040000 */
14449 
14450 /****************  Bit definition for OCTOSPI_DCR3 register  ******************/
14451 #define OCTOSPI_DCR3_CSBOUND_Pos            XSPI_DCR3_CSBOUND_Pos
14452 #define OCTOSPI_DCR3_CSBOUND_Msk            XSPI_DCR3_CSBOUND_Msk                         /*!< 0x001F0000 */
14453 #define OCTOSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND                             /*!< Maximum transfer */
14454 
14455 /****************  Bit definition for OCTOSPI_DCR4 register  ******************/
14456 #define OCTOSPI_DCR4_REFRESH_Pos            XSPI_DCR4_REFRESH_Pos
14457 #define OCTOSPI_DCR4_REFRESH_Msk            XSPI_DCR4_REFRESH_Msk                         /*!< 0xFFFFFFFF */
14458 #define OCTOSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH                             /*!< Refresh rate */
14459 
14460 /*****************  Bit definition for OCTOSPI_SR register  *******************/
14461 #define OCTOSPI_SR_TEF_Pos                  XSPI_SR_TEF_Pos
14462 #define OCTOSPI_SR_TEF_Msk                  XSPI_SR_TEF_Msk                               /*!< 0x00000001 */
14463 #define OCTOSPI_SR_TEF                      XSPI_SR_TEF                                   /*!< Transfer Error Flag */
14464 #define OCTOSPI_SR_TCF_Pos                  XSPI_SR_TCF_Pos
14465 #define OCTOSPI_SR_TCF_Msk                  XSPI_SR_TCF_Msk                               /*!< 0x00000002 */
14466 #define OCTOSPI_SR_TCF                      XSPI_SR_TCF                                   /*!< Transfer Complete Flag */
14467 #define OCTOSPI_SR_FTF_Pos                  XSPI_SR_FTF_Pos
14468 #define OCTOSPI_SR_FTF_Msk                  XSPI_SR_FTF_Msk                               /*!< 0x00000004 */
14469 #define OCTOSPI_SR_FTF                      XSPI_SR_FTF                                   /*!< FIFO Threshold Flag */
14470 #define OCTOSPI_SR_SMF_Pos                  XSPI_SR_SMF_Pos
14471 #define OCTOSPI_SR_SMF_Msk                  XSPI_SR_SMF_Msk                               /*!< 0x00000008 */
14472 #define OCTOSPI_SR_SMF                      XSPI_SR_SMF                                   /*!< Status Match Flag */
14473 #define OCTOSPI_SR_TOF_Pos                  XSPI_SR_TOF_Pos
14474 #define OCTOSPI_SR_TOF_Msk                  XSPI_SR_TOF_Msk                               /*!< 0x00000010 */
14475 #define OCTOSPI_SR_TOF                      XSPI_SR_TOF                                   /*!< Timeout Flag */
14476 #define OCTOSPI_SR_BUSY_Pos                 XSPI_SR_BUSY_Pos
14477 #define OCTOSPI_SR_BUSY_Msk                 XSPI_SR_BUSY_Msk                              /*!< 0x00000020 */
14478 #define OCTOSPI_SR_BUSY                     XSPI_SR_BUSY                                  /*!< Busy */
14479 #define OCTOSPI_SR_FLEVEL_Pos               XSPI_SR_FLEVEL_Pos
14480 #define OCTOSPI_SR_FLEVEL_Msk               (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)             /*!< 0x00003F00 */
14481 #define OCTOSPI_SR_FLEVEL                   XSPI_SR_FLEVEL                                /*!< FIFO Level */
14482 
14483 /****************  Bit definition for OCTOSPI_FCR register  *******************/
14484 #define OCTOSPI_FCR_CTEF_Pos                XSPI_FCR_CTEF_Pos
14485 #define OCTOSPI_FCR_CTEF_Msk                XSPI_FCR_CTEF_Msk                             /*!< 0x00000001 */
14486 #define OCTOSPI_FCR_CTEF                    XSPI_FCR_CTEF                                 /*!< Clear Transfer Error Flag */
14487 #define OCTOSPI_FCR_CTCF_Pos                XSPI_FCR_CTCF_Pos
14488 #define OCTOSPI_FCR_CTCF_Msk                XSPI_FCR_CTCF_Msk                             /*!< 0x00000002 */
14489 #define OCTOSPI_FCR_CTCF                    XSPI_FCR_CTCF                                 /*!< Clear Transfer Complete Flag */
14490 #define OCTOSPI_FCR_CSMF_Pos                XSPI_FCR_CSMF_Pos
14491 #define OCTOSPI_FCR_CSMF_Msk                XSPI_FCR_CSMF_Msk                             /*!< 0x00000008 */
14492 #define OCTOSPI_FCR_CSMF                    XSPI_FCR_CSMF                                 /*!< Clear Status Match Flag */
14493 #define OCTOSPI_FCR_CTOF_Pos                XSPI_FCR_CTOF_Pos
14494 #define OCTOSPI_FCR_CTOF_Msk                XSPI_FCR_CTOF_Msk                             /*!< 0x00000010 */
14495 #define OCTOSPI_FCR_CTOF                    XSPI_FCR_CTOF                                 /*!< Clear Timeout Flag */
14496 
14497 /****************  Bit definition for OCTOSPI_DLR register  *******************/
14498 #define OCTOSPI_DLR_DL_Pos                  XSPI_DLR_DL_Pos
14499 #define OCTOSPI_DLR_DL_Msk                  XSPI_DLR_DL_Msk                               /*!< 0xFFFFFFFF */
14500 #define OCTOSPI_DLR_DL                      XSPI_DLR_DL                                   /*!< Data Length */
14501 
14502 /*****************  Bit definition for OCTOSPI_AR register  *******************/
14503 #define OCTOSPI_AR_ADDRESS_Pos              XSPI_AR_ADDRESS_Pos
14504 #define OCTOSPI_AR_ADDRESS_Msk              XSPI_AR_ADDRESS_Msk                           /*!< 0xFFFFFFFF */
14505 #define OCTOSPI_AR_ADDRESS                  XSPI_AR_ADDRESS                               /*!< Address */
14506 
14507 /*****************  Bit definition for OCTOSPI_DR register  *******************/
14508 #define OCTOSPI_DR_DATA_Pos                 XSPI_DR_DATA_Pos
14509 #define OCTOSPI_DR_DATA_Msk                 XSPI_DR_DATA_Msk                              /*!< 0xFFFFFFFF */
14510 #define OCTOSPI_DR_DATA                     XSPI_DR_DATA                                  /*!< Data */
14511 
14512 /***************  Bit definition for OCTOSPI_PSMKR register  ******************/
14513 #define OCTOSPI_PSMKR_MASK_Pos              XSPI_PSMKR_MASK_Pos
14514 #define OCTOSPI_PSMKR_MASK_Msk              XSPI_PSMKR_MASK_Msk                           /*!< 0xFFFFFFFF */
14515 #define OCTOSPI_PSMKR_MASK                  XSPI_PSMKR_MASK                               /*!< Status mask */
14516 
14517 /***************  Bit definition for OCTOSPI_PSMAR register  ******************/
14518 #define OCTOSPI_PSMAR_MATCH_Pos             XSPI_PSMAR_MATCH_Pos
14519 #define OCTOSPI_PSMAR_MATCH_Msk             XSPI_PSMAR_MATCH_Msk                          /*!< 0xFFFFFFFF */
14520 #define OCTOSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH                              /*!< Status match */
14521 
14522 /****************  Bit definition for OCTOSPI_PIR register  *******************/
14523 #define OCTOSPI_PIR_INTERVAL_Pos            XSPI_PIR_INTERVAL_Pos
14524 #define OCTOSPI_PIR_INTERVAL_Msk            XSPI_PIR_INTERVAL_Msk                         /*!< 0x0000FFFF */
14525 #define OCTOSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL                             /*!< Polling Interval */
14526 
14527 /****************  Bit definition for OCTOSPI_CCR register  *******************/
14528 #define OCTOSPI_CCR_IMODE_Pos               XSPI_CCR_IMODE_Pos
14529 #define OCTOSPI_CCR_IMODE_Msk               XSPI_CCR_IMODE_Msk                            /*!< 0x00000007 */
14530 #define OCTOSPI_CCR_IMODE                   XSPI_CCR_IMODE                                /*!< Instruction Mode */
14531 #define OCTOSPI_CCR_IMODE_0                 XSPI_CCR_IMODE_0                              /*!< 0x00000001 */
14532 #define OCTOSPI_CCR_IMODE_1                 XSPI_CCR_IMODE_1                              /*!< 0x00000002 */
14533 #define OCTOSPI_CCR_IMODE_2                 XSPI_CCR_IMODE_2                              /*!< 0x00000004 */
14534 #define OCTOSPI_CCR_IDTR_Pos                XSPI_CCR_IDTR_Pos
14535 #define OCTOSPI_CCR_IDTR_Msk                XSPI_CCR_IDTR_Msk                             /*!< 0x00000008 */
14536 #define OCTOSPI_CCR_IDTR                    XSPI_CCR_IDTR                                 /*!< Instruction Double Transfer Rate */
14537 #define OCTOSPI_CCR_ISIZE_Pos               XSPI_CCR_ISIZE_Pos
14538 #define OCTOSPI_CCR_ISIZE_Msk               XSPI_CCR_ISIZE_Msk                            /*!< 0x00000030 */
14539 #define OCTOSPI_CCR_ISIZE                   XSPI_CCR_ISIZE                                /*!< Instruction Size */
14540 #define OCTOSPI_CCR_ISIZE_0                 XSPI_CCR_ISIZE_0                              /*!< 0x00000010 */
14541 #define OCTOSPI_CCR_ISIZE_1                 XSPI_CCR_ISIZE_1                              /*!< 0x00000020 */
14542 #define OCTOSPI_CCR_ADMODE_Pos              XSPI_CCR_ADMODE_Pos
14543 #define OCTOSPI_CCR_ADMODE_Msk              XSPI_CCR_ADMODE_Msk                           /*!< 0x00000700 */
14544 #define OCTOSPI_CCR_ADMODE                  XSPI_CCR_ADMODE                               /*!< Address Mode */
14545 #define OCTOSPI_CCR_ADMODE_0                XSPI_CCR_ADMODE_0                             /*!< 0x00000100 */
14546 #define OCTOSPI_CCR_ADMODE_1                XSPI_CCR_ADMODE_1                             /*!< 0x00000200 */
14547 #define OCTOSPI_CCR_ADMODE_2                XSPI_CCR_ADMODE_2                             /*!< 0x00000400 */
14548 #define OCTOSPI_CCR_ADDTR_Pos               XSPI_CCR_ADDTR_Pos
14549 #define OCTOSPI_CCR_ADDTR_Msk               XSPI_CCR_ADDTR_Msk                            /*!< 0x00000800 */
14550 #define OCTOSPI_CCR_ADDTR                   XSPI_CCR_ADDTR                                /*!< Address Double Transfer Rate */
14551 #define OCTOSPI_CCR_ADSIZE_Pos              XSPI_CCR_ADSIZE_Pos
14552 #define OCTOSPI_CCR_ADSIZE_Msk              XSPI_CCR_ADSIZE_Msk                           /*!< 0x00003000 */
14553 #define OCTOSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE                               /*!< Address Size */
14554 #define OCTOSPI_CCR_ADSIZE_0                XSPI_CCR_ADSIZE_0                             /*!< 0x00001000 */
14555 #define OCTOSPI_CCR_ADSIZE_1                XSPI_CCR_ADSIZE_1                             /*!< 0x00002000 */
14556 #define OCTOSPI_CCR_ABMODE_Pos              XSPI_CCR_ABMODE_Pos
14557 #define OCTOSPI_CCR_ABMODE_Msk              XSPI_CCR_ABMODE_Msk                           /*!< 0x00070000 */
14558 #define OCTOSPI_CCR_ABMODE                  XSPI_CCR_ABMODE                               /*!< Alternate Bytes Mode */
14559 #define OCTOSPI_CCR_ABMODE_0                XSPI_CCR_ABMODE_0                             /*!< 0x00010000 */
14560 #define OCTOSPI_CCR_ABMODE_1                XSPI_CCR_ABMODE_1                             /*!< 0x00020000 */
14561 #define OCTOSPI_CCR_ABMODE_2                XSPI_CCR_ABMODE_2                             /*!< 0x00040000 */
14562 #define OCTOSPI_CCR_ABDTR_Pos               XSPI_CCR_ABDTR_Pos
14563 #define OCTOSPI_CCR_ABDTR_Msk               XSPI_CCR_ABDTR_Msk                            /*!< 0x00080000 */
14564 #define OCTOSPI_CCR_ABDTR                   XSPI_CCR_ABDTR                                /*!< Alternate Bytes Double Transfer Rate */
14565 #define OCTOSPI_CCR_ABSIZE_Pos              XSPI_CCR_ABSIZE_Pos
14566 #define OCTOSPI_CCR_ABSIZE_Msk              XSPI_CCR_ABSIZE_Msk                           /*!< 0x00300000 */
14567 #define OCTOSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE                               /*!< Alternate Bytes Size */
14568 #define OCTOSPI_CCR_ABSIZE_0                XSPI_CCR_ABSIZE_0                             /*!< 0x00100000 */
14569 #define OCTOSPI_CCR_ABSIZE_1                XSPI_CCR_ABSIZE_1                             /*!< 0x00200000 */
14570 #define OCTOSPI_CCR_DMODE_Pos               XSPI_CCR_DMODE_Pos
14571 #define OCTOSPI_CCR_DMODE_Msk               XSPI_CCR_DMODE_Msk                            /*!< 0x07000000 */
14572 #define OCTOSPI_CCR_DMODE                   XSPI_CCR_DMODE                                /*!< Data Mode */
14573 #define OCTOSPI_CCR_DMODE_0                 XSPI_CCR_DMODE_0                              /*!< 0x01000000 */
14574 #define OCTOSPI_CCR_DMODE_1                 XSPI_CCR_DMODE_1                              /*!< 0x02000000 */
14575 #define OCTOSPI_CCR_DMODE_2                 XSPI_CCR_DMODE_2                              /*!< 0x04000000 */
14576 #define OCTOSPI_CCR_DDTR_Pos                XSPI_CCR_DDTR_Pos
14577 #define OCTOSPI_CCR_DDTR_Msk                XSPI_CCR_DDTR_Msk                             /*!< 0x08000000 */
14578 #define OCTOSPI_CCR_DDTR                    XSPI_CCR_DDTR                                 /*!< Data Double Transfer Rate */
14579 #define OCTOSPI_CCR_DQSE_Pos                XSPI_CCR_DQSE_Pos
14580 #define OCTOSPI_CCR_DQSE_Msk                XSPI_CCR_DQSE_Msk                             /*!< 0x20000000 */
14581 #define OCTOSPI_CCR_DQSE                    XSPI_CCR_DQSE                                 /*!< DQS Enable */
14582 #define OCTOSPI_CCR_SIOO_Pos                XSPI_CCR_SIOO_Pos
14583 #define OCTOSPI_CCR_SIOO_Msk                XSPI_CCR_SIOO_Msk                             /*!< 0x80000000 */
14584 #define OCTOSPI_CCR_SIOO                    XSPI_CCR_SIOO                                 /*!< Send Instruction Only Once Mode */
14585 
14586 /****************  Bit definition for OCTOSPI_TCR register  *******************/
14587 #define OCTOSPI_TCR_DCYC_Pos                XSPI_TCR_DCYC_Pos
14588 #define OCTOSPI_TCR_DCYC_Msk                XSPI_TCR_DCYC_Msk                             /*!< 0x0000001F */
14589 #define OCTOSPI_TCR_DCYC                    XSPI_TCR_DCYC                                 /*!< Number of Dummy Cycles */
14590 #define OCTOSPI_TCR_DHQC_Pos                XSPI_TCR_DHQC_Pos
14591 #define OCTOSPI_TCR_DHQC_Msk                XSPI_TCR_DHQC_Msk                             /*!< 0x10000000 */
14592 #define OCTOSPI_TCR_DHQC                    XSPI_TCR_DHQC                                 /*!< Delay Hold Quarter Cycle */
14593 #define OCTOSPI_TCR_SSHIFT_Pos              XSPI_TCR_SSHIFT_Pos
14594 #define OCTOSPI_TCR_SSHIFT_Msk              XSPI_TCR_SSHIFT_Msk                           /*!< 0x40000000 */
14595 #define OCTOSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT                               /*!< Sample Shift */
14596 
14597 /*****************  Bit definition for OCTOSPI_IR register  *******************/
14598 #define OCTOSPI_IR_INSTRUCTION_Pos          XSPI_IR_INSTRUCTION_Pos
14599 #define OCTOSPI_IR_INSTRUCTION_Msk          XSPI_IR_INSTRUCTION_Msk                       /*!< 0xFFFFFFFF */
14600 #define OCTOSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION                           /*!< Instruction */
14601 
14602 /****************  Bit definition for OCTOSPI_ABR register  *******************/
14603 #define OCTOSPI_ABR_ALTERNATE_Pos           XSPI_ABR_ALTERNATE_Pos
14604 #define OCTOSPI_ABR_ALTERNATE_Msk           XSPI_ABR_ALTERNATE_Msk                        /*!< 0xFFFFFFFF */
14605 #define OCTOSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE                            /*!< Alternate Bytes */
14606 
14607 /****************  Bit definition for OCTOSPI_LPTR register  ******************/
14608 #define OCTOSPI_LPTR_TIMEOUT_Pos            XSPI_LPTR_TIMEOUT_Pos
14609 #define OCTOSPI_LPTR_TIMEOUT_Msk            XSPI_LPTR_TIMEOUT_Msk                         /*!< 0x0000FFFF */
14610 #define OCTOSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT                             /*!< Timeout period */
14611 
14612 /****************  Bit definition for OCTOSPI_WPCCR register  *******************/
14613 #define OCTOSPI_WPCCR_IMODE_Pos             XSPI_WPCCR_IMODE_Pos
14614 #define OCTOSPI_WPCCR_IMODE_Msk             XSPI_WPCCR_IMODE_Msk                          /*!< 0x00000007 */
14615 #define OCTOSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE                              /*!< Instruction Mode */
14616 #define OCTOSPI_WPCCR_IMODE_0               XSPI_WPCCR_IMODE_0                            /*!< 0x00000001 */
14617 #define OCTOSPI_WPCCR_IMODE_1               XSPI_WPCCR_IMODE_1                            /*!< 0x00000002 */
14618 #define OCTOSPI_WPCCR_IMODE_2               XSPI_WPCCR_IMODE_2                            /*!< 0x00000004 */
14619 #define OCTOSPI_WPCCR_IDTR_Pos              XSPI_WPCCR_IDTR_Pos
14620 #define OCTOSPI_WPCCR_IDTR_Msk              XSPI_WPCCR_IDTR_Msk                           /*!< 0x00000008 */
14621 #define OCTOSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR                               /*!< Instruction Double Transfer Rate */
14622 #define OCTOSPI_WPCCR_ISIZE_Pos             XSPI_WPCCR_ISIZE_Pos
14623 #define OCTOSPI_WPCCR_ISIZE_Msk             XSPI_WPCCR_ISIZE_Msk                          /*!< 0x00000030 */
14624 #define OCTOSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE                              /*!< Instruction Size */
14625 #define OCTOSPI_WPCCR_ISIZE_0               XSPI_WPCCR_ISIZE_0                            /*!< 0x00000010 */
14626 #define OCTOSPI_WPCCR_ISIZE_1               XSPI_WPCCR_ISIZE_1                            /*!< 0x00000020 */
14627 #define OCTOSPI_WPCCR_ADMODE_Pos            XSPI_WPCCR_ADMODE_Pos
14628 #define OCTOSPI_WPCCR_ADMODE_Msk            XSPI_WPCCR_ADMODE_Msk                         /*!< 0x00000700 */
14629 #define OCTOSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE                             /*!< Address Mode */
14630 #define OCTOSPI_WPCCR_ADMODE_0              XSPI_WPCCR_ADMODE_0                           /*!< 0x00000100 */
14631 #define OCTOSPI_WPCCR_ADMODE_1              XSPI_WPCCR_ADMODE_1                           /*!< 0x00000200 */
14632 #define OCTOSPI_WPCCR_ADMODE_2              XSPI_WPCCR_ADMODE_2                           /*!< 0x00000400 */
14633 #define OCTOSPI_WPCCR_ADDTR_Pos             XSPI_WPCCR_ADDTR_Pos
14634 #define OCTOSPI_WPCCR_ADDTR_Msk             XSPI_WPCCR_ADDTR_Msk                          /*!< 0x00000800 */
14635 #define OCTOSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR                              /*!< Address Double Transfer Rate */
14636 #define OCTOSPI_WPCCR_ADSIZE_Pos            XSPI_WPCCR_ADSIZE_Pos
14637 #define OCTOSPI_WPCCR_ADSIZE_Msk            XSPI_WPCCR_ADSIZE_Msk                         /*!< 0x00003000 */
14638 #define OCTOSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE                             /*!< Address Size */
14639 #define OCTOSPI_WPCCR_ADSIZE_0              XSPI_WPCCR_ADSIZE_0                           /*!< 0x00001000 */
14640 #define OCTOSPI_WPCCR_ADSIZE_1              XSPI_WPCCR_ADSIZE_1                           /*!< 0x00002000 */
14641 #define OCTOSPI_WPCCR_ABMODE_Pos            XSPI_WPCCR_ABMODE_Pos
14642 #define OCTOSPI_WPCCR_ABMODE_Msk            XSPI_WPCCR_ABMODE_Msk                         /*!< 0x00070000 */
14643 #define OCTOSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE                             /*!< Alternate Bytes Mode */
14644 #define OCTOSPI_WPCCR_ABMODE_0              XSPI_WPCCR_ABMODE_0                           /*!< 0x00010000 */
14645 #define OCTOSPI_WPCCR_ABMODE_1              XSPI_WPCCR_ABMODE_1                           /*!< 0x00020000 */
14646 #define OCTOSPI_WPCCR_ABMODE_2              XSPI_WPCCR_ABMODE_2                           /*!< 0x00040000 */
14647 #define OCTOSPI_WPCCR_ABDTR_Pos             XSPI_WPCCR_ABDTR_Pos
14648 #define OCTOSPI_WPCCR_ABDTR_Msk             XSPI_WPCCR_ABDTR_Msk                          /*!< 0x00080000 */
14649 #define OCTOSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR                              /*!< Alternate Bytes Double Transfer Rate */
14650 #define OCTOSPI_WPCCR_ABSIZE_Pos            XSPI_WPCCR_ABSIZE_Pos
14651 #define OCTOSPI_WPCCR_ABSIZE_Msk            XSPI_WPCCR_ABSIZE_Msk                         /*!< 0x00300000 */
14652 #define OCTOSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE                             /*!< Alternate Bytes Size */
14653 #define OCTOSPI_WPCCR_ABSIZE_0              XSPI_WPCCR_ABSIZE_0                           /*!< 0x00100000 */
14654 #define OCTOSPI_WPCCR_ABSIZE_1              XSPI_WPCCR_ABSIZE_1                           /*!< 0x00200000 */
14655 #define OCTOSPI_WPCCR_DMODE_Pos             XSPI_WPCCR_DMODE_Pos
14656 #define OCTOSPI_WPCCR_DMODE_Msk             XSPI_WPCCR_DMODE_Msk                          /*!< 0x07000000 */
14657 #define OCTOSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE                              /*!< Data Mode */
14658 #define OCTOSPI_WPCCR_DMODE_0               XSPI_WPCCR_DMODE_0                            /*!< 0x01000000 */
14659 #define OCTOSPI_WPCCR_DMODE_1               XSPI_WPCCR_DMODE_1                            /*!< 0x02000000 */
14660 #define OCTOSPI_WPCCR_DMODE_2               XSPI_WPCCR_DMODE_2                            /*!< 0x04000000 */
14661 #define OCTOSPI_WPCCR_DDTR_Pos              XSPI_WPCCR_DDTR_Pos
14662 #define OCTOSPI_WPCCR_DDTR_Msk              XSPI_WPCCR_DDTR_Msk                           /*!< 0x08000000 */
14663 #define OCTOSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR                               /*!< Data Double Transfer Rate */
14664 #define OCTOSPI_WPCCR_DQSE_Pos              XSPI_WPCCR_DQSE_Pos
14665 #define OCTOSPI_WPCCR_DQSE_Msk              XSPI_WPCCR_DQSE_Msk                           /*!< 0x20000000 */
14666 #define OCTOSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE                               /*!< DQS Enable */
14667 
14668 /****************  Bit definition for OCTOSPI_WPTCR register  *******************/
14669 #define OCTOSPI_WPTCR_DCYC_Pos              XSPI_WPTCR_DCYC_Pos
14670 #define OCTOSPI_WPTCR_DCYC_Msk              XSPI_WPTCR_DCYC_Msk                           /*!< 0x0000001F */
14671 #define OCTOSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC                               /*!< Number of Dummy Cycles */
14672 #define OCTOSPI_WPTCR_DHQC_Pos              XSPI_WPTCR_DHQC_Pos
14673 #define OCTOSPI_WPTCR_DHQC_Msk              XSPI_WPTCR_DHQC_Msk                           /*!< 0x10000000 */
14674 #define OCTOSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC                               /*!< Delay Hold Quarter Cycle */
14675 #define OCTOSPI_WPTCR_SSHIFT_Pos            XSPI_WPTCR_SSHIFT_Pos
14676 #define OCTOSPI_WPTCR_SSHIFT_Msk            XSPI_WPTCR_SSHIFT_Msk                         /*!< 0x40000000 */
14677 #define OCTOSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT                             /*!< Sample Shift */
14678 
14679 /*****************  Bit definition for OCTOSPI_WPIR register  *******************/
14680 #define OCTOSPI_WPIR_INSTRUCTION_Pos        XSPI_WPIR_INSTRUCTION_Pos
14681 #define OCTOSPI_WPIR_INSTRUCTION_Msk        XSPI_WPIR_INSTRUCTION_Msk                     /*!< 0xFFFFFFFF */
14682 #define OCTOSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION                         /*!< Instruction */
14683 
14684 /****************  Bit definition for OCTOSPI_WPABR register  *******************/
14685 #define OCTOSPI_WPABR_ALTERNATE_Pos         XSPI_WPABR_ALTERNATE_Pos
14686 #define OCTOSPI_WPABR_ALTERNATE_Msk         XSPI_WPABR_ALTERNATE_Msk                      /*!< 0xFFFFFFFF */
14687 #define OCTOSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE                          /*!< Alternate Bytes */
14688 
14689 /****************  Bit definition for OCTOSPI_WCCR register  ******************/
14690 #define OCTOSPI_WCCR_IMODE_Pos              XSPI_WCCR_IMODE_Pos
14691 #define OCTOSPI_WCCR_IMODE_Msk              XSPI_WCCR_IMODE_Msk                           /*!< 0x00000007 */
14692 #define OCTOSPI_WCCR_IMODE                  XSPI_WCCR_IMODE                               /*!< Instruction Mode */
14693 #define OCTOSPI_WCCR_IMODE_0                XSPI_WCCR_IMODE_0                             /*!< 0x00000001 */
14694 #define OCTOSPI_WCCR_IMODE_1                XSPI_WCCR_IMODE_1                             /*!< 0x00000002 */
14695 #define OCTOSPI_WCCR_IMODE_2                XSPI_WCCR_IMODE_2                             /*!< 0x00000004 */
14696 #define OCTOSPI_WCCR_IDTR_Pos               XSPI_WCCR_IDTR_Pos
14697 #define OCTOSPI_WCCR_IDTR_Msk               XSPI_WCCR_IDTR_Msk                            /*!< 0x00000008 */
14698 #define OCTOSPI_WCCR_IDTR                   XSPI_WCCR_IDTR                                /*!< Instruction Double Transfer Rate */
14699 #define OCTOSPI_WCCR_ISIZE_Pos              XSPI_WCCR_ISIZE_Pos
14700 #define OCTOSPI_WCCR_ISIZE_Msk              XSPI_WCCR_ISIZE_Msk                           /*!< 0x00000030 */
14701 #define OCTOSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE                               /*!< Instruction Size */
14702 #define OCTOSPI_WCCR_ISIZE_0                XSPI_WCCR_ISIZE_0                             /*!< 0x00000010 */
14703 #define OCTOSPI_WCCR_ISIZE_1                XSPI_WCCR_ISIZE_1                             /*!< 0x00000020 */
14704 #define OCTOSPI_WCCR_ADMODE_Pos             XSPI_WCCR_ADMODE_Pos
14705 #define OCTOSPI_WCCR_ADMODE_Msk             XSPI_WCCR_ADMODE_Msk                          /*!< 0x00000700 */
14706 #define OCTOSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE                              /*!< Address Mode */
14707 #define OCTOSPI_WCCR_ADMODE_0               XSPI_WCCR_ADMODE_0                            /*!< 0x00000100 */
14708 #define OCTOSPI_WCCR_ADMODE_1               XSPI_WCCR_ADMODE_1                            /*!< 0x00000200 */
14709 #define OCTOSPI_WCCR_ADMODE_2               XSPI_WCCR_ADMODE_2                            /*!< 0x00000400 */
14710 #define OCTOSPI_WCCR_ADDTR_Pos              XSPI_WCCR_ADDTR_Pos
14711 #define OCTOSPI_WCCR_ADDTR_Msk              XSPI_WCCR_ADDTR_Msk                           /*!< 0x00000800 */
14712 #define OCTOSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR                               /*!< Address Double Transfer Rate */
14713 #define OCTOSPI_WCCR_ADSIZE_Pos             XSPI_WCCR_ADSIZE_Pos
14714 #define OCTOSPI_WCCR_ADSIZE_Msk             XSPI_WCCR_ADSIZE_Msk                          /*!< 0x00003000 */
14715 #define OCTOSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE                              /*!< Address Size */
14716 #define OCTOSPI_WCCR_ADSIZE_0               XSPI_WCCR_ADSIZE_0                            /*!< 0x00001000 */
14717 #define OCTOSPI_WCCR_ADSIZE_1               XSPI_WCCR_ADSIZE_1                            /*!< 0x00002000 */
14718 #define OCTOSPI_WCCR_ABMODE_Pos             XSPI_WCCR_ABMODE_Pos
14719 #define OCTOSPI_WCCR_ABMODE_Msk             XSPI_WCCR_ABMODE_Msk                          /*!< 0x00070000 */
14720 #define OCTOSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE                              /*!< Alternate Bytes Mode */
14721 #define OCTOSPI_WCCR_ABMODE_0               XSPI_WCCR_ABMODE_0                            /*!< 0x00010000 */
14722 #define OCTOSPI_WCCR_ABMODE_1               XSPI_WCCR_ABMODE_1                            /*!< 0x00020000 */
14723 #define OCTOSPI_WCCR_ABMODE_2               XSPI_WCCR_ABMODE_2                            /*!< 0x00040000 */
14724 #define OCTOSPI_WCCR_ABDTR_Pos              XSPI_WCCR_ABDTR_Pos
14725 #define OCTOSPI_WCCR_ABDTR_Msk              XSPI_WCCR_ABDTR_Msk                           /*!< 0x00080000 */
14726 #define OCTOSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR                               /*!< Alternate Bytes Double Transfer Rate */
14727 #define OCTOSPI_WCCR_ABSIZE_Pos             XSPI_WCCR_ABSIZE_Pos
14728 #define OCTOSPI_WCCR_ABSIZE_Msk             XSPI_WCCR_ABSIZE_Msk                          /*!< 0x00300000 */
14729 #define OCTOSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE                              /*!< Alternate Bytes Size */
14730 #define OCTOSPI_WCCR_ABSIZE_0               XSPI_WCCR_ABSIZE_0                            /*!< 0x00100000 */
14731 #define OCTOSPI_WCCR_ABSIZE_1               XSPI_WCCR_ABSIZE_1                            /*!< 0x00200000 */
14732 #define OCTOSPI_WCCR_DMODE_Pos              XSPI_WCCR_DMODE_Pos
14733 #define OCTOSPI_WCCR_DMODE_Msk              XSPI_WCCR_DMODE_Msk                           /*!< 0x07000000 */
14734 #define OCTOSPI_WCCR_DMODE                  XSPI_WCCR_DMODE                               /*!< Data Mode */
14735 #define OCTOSPI_WCCR_DMODE_0                XSPI_WCCR_DMODE_0                             /*!< 0x01000000 */
14736 #define OCTOSPI_WCCR_DMODE_1                XSPI_WCCR_DMODE_1                             /*!< 0x02000000 */
14737 #define OCTOSPI_WCCR_DMODE_2                XSPI_WCCR_DMODE_2                             /*!< 0x04000000 */
14738 #define OCTOSPI_WCCR_DDTR_Pos               XSPI_WCCR_DDTR_Pos
14739 #define OCTOSPI_WCCR_DDTR_Msk               XSPI_WCCR_DDTR_Msk                            /*!< 0x08000000 */
14740 #define OCTOSPI_WCCR_DDTR                   XSPI_WCCR_DDTR                                /*!< Data Double Transfer Rate */
14741 #define OCTOSPI_WCCR_DQSE_Pos               XSPI_WCCR_DQSE_Pos
14742 #define OCTOSPI_WCCR_DQSE_Msk               XSPI_WCCR_DQSE_Msk                            /*!< 0x20000000 */
14743 #define OCTOSPI_WCCR_DQSE                   XSPI_WCCR_DQSE                                /*!< DQS Enable */
14744 
14745 /****************  Bit definition for OCTOSPI_WTCR register  ******************/
14746 #define OCTOSPI_WTCR_DCYC_Pos               XSPI_WTCR_DCYC_Pos
14747 #define OCTOSPI_WTCR_DCYC_Msk               XSPI_WTCR_DCYC_Msk                            /*!< 0x0000001F */
14748 #define OCTOSPI_WTCR_DCYC                   XSPI_WTCR_DCYC                                /*!< Number of Dummy Cycles */
14749 
14750 /****************  Bit definition for OCTOSPI_WIR register  *******************/
14751 #define OCTOSPI_WIR_INSTRUCTION_Pos         XSPI_WIR_INSTRUCTION_Pos
14752 #define OCTOSPI_WIR_INSTRUCTION_Msk         XSPI_WIR_INSTRUCTION_Msk                      /*!< 0xFFFFFFFF */
14753 #define OCTOSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION                          /*!< Instruction */
14754 
14755 /****************  Bit definition for OCTOSPI_WABR register  ******************/
14756 #define OCTOSPI_WABR_ALTERNATE_Pos          XSPI_WABR_ALTERNATE_Pos
14757 #define OCTOSPI_WABR_ALTERNATE_Msk          XSPI_WABR_ALTERNATE_Msk                       /*!< 0xFFFFFFFF */
14758 #define OCTOSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE                           /*!< Alternate Bytes */
14759 
14760 /****************  Bit definition for OCTOSPI_HLCR register  ******************/
14761 #define OCTOSPI_HLCR_LM_Pos                 XSPI_HLCR_LM_Pos
14762 #define OCTOSPI_HLCR_LM_Msk                 XSPI_HLCR_LM_Msk                              /*!< 0x00000001 */
14763 #define OCTOSPI_HLCR_LM                     XSPI_HLCR_LM                                  /*!< Latency Mode */
14764 #define OCTOSPI_HLCR_WZL_Pos                XSPI_HLCR_WZL_Pos
14765 #define OCTOSPI_HLCR_WZL_Msk                XSPI_HLCR_WZL_Msk                             /*!< 0x00000002 */
14766 #define OCTOSPI_HLCR_WZL                    XSPI_HLCR_WZL                                 /*!< Write Zero Latency */
14767 #define OCTOSPI_HLCR_TACC_Pos               XSPI_HLCR_TACC_Pos
14768 #define OCTOSPI_HLCR_TACC_Msk               XSPI_HLCR_TACC_Msk                            /*!< 0x0000FF00 */
14769 #define OCTOSPI_HLCR_TACC                   XSPI_HLCR_TACC                                /*!< Access Time */
14770 #define OCTOSPI_HLCR_TRWR_Pos               XSPI_HLCR_TRWR_Pos
14771 #define OCTOSPI_HLCR_TRWR_Msk               XSPI_HLCR_TRWR_Msk                            /*!< 0x00FF0000 */
14772 #define OCTOSPI_HLCR_TRWR                   XSPI_HLCR_TRWR                                /*!< Read Write Recovery Time */
14773 
14774 /******************************************************************************/
14775 /*                                                                            */
14776 /*                        Delay Block Interface (DLYB)                        */
14777 /*                                                                            */
14778 /******************************************************************************/
14779 /*******************  Bit definition for DLYB_CR register  ********************/
14780 #define DLYB_CR_DEN_Pos                     (0U)
14781 #define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
14782 #define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
14783 #define DLYB_CR_SEN_Pos                     (1U)
14784 #define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
14785 #define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
14786 
14787 /*******************  Bit definition for DLYB_CFGR register  ********************/
14788 #define DLYB_CFGR_SEL_Pos                   (0U)
14789 #define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
14790 #define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
14791 #define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
14792 #define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
14793 #define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
14794 #define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
14795 
14796 #define DLYB_CFGR_UNIT_Pos                  (8U)
14797 #define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
14798 #define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
14799 #define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
14800 #define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
14801 #define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
14802 #define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
14803 #define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
14804 #define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
14805 #define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
14806 
14807 #define DLYB_CFGR_LNG_Pos                   (16U)
14808 #define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
14809 #define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
14810 #define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
14811 #define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
14812 #define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
14813 #define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
14814 #define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
14815 #define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
14816 #define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
14817 #define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
14818 #define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
14819 #define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
14820 #define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
14821 #define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
14822 
14823 #define DLYB_CFGR_LNGF_Pos                  (31U)
14824 #define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
14825 #define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
14826 
14827 /******************************************************************************/
14828 /*                                                                            */
14829 /*                              On The Fly Decryption                         */
14830 /*                                                                            */
14831 /******************************************************************************/
14832 /******************  Bit definition for OTFDEC_CR register  ******************/
14833 #define OTFDEC_CR_ENC_Pos                   (0U)
14834 #define OTFDEC_CR_ENC_Msk                   (0x1UL << OTFDEC_CR_ENC_Pos)            /*!< 0x00000001 */
14835 #define OTFDEC_CR_ENC                       OTFDEC_CR_ENC_Msk                       /*!< Encryption mode bit */
14836 
14837 /******************  Bit definition for OTFDEC_PRIVCFGR register  ************/
14838 #define OTFDEC_PRIVCFGR_PRIV_Pos            (0U)
14839 #define OTFDEC_PRIVCFGR_PRIV_Msk            (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)     /*!< 0x00000001 */
14840 #define OTFDEC_PRIVCFGR_PRIV                OTFDEC_PRIVCFGR_PRIV_Msk                /*!< Privileged access protection */
14841 
14842 /******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/
14843 #define OTFDEC_REG_CONFIGR_REG_EN_Pos       (0U)
14844 #define OTFDEC_REG_CONFIGR_REG_EN_Msk       (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos) /*!< 0x00000001 */
14845 #define OTFDEC_REG_CONFIGR_REG_EN           OTFDEC_REG_CONFIGR_REG_EN_Msk           /*!< Region on-the-fly decryption enable */
14846 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos   (1U)
14847 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk   (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos) /*!< 0x00000002 */
14848 #define OTFDEC_REG_CONFIGR_CONFIGLOCK       OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk       /*!< Region config lock */
14849 #define OTFDEC_REG_CONFIGR_KEYLOCK_Pos      (2U)
14850 #define OTFDEC_REG_CONFIGR_KEYLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos) /*!< 0x00000004 */
14851 #define OTFDEC_REG_CONFIGR_KEYLOCK          OTFDEC_REG_CONFIGR_KEYLOCK_Msk          /*!< Region key lock */
14852 #define OTFDEC_REG_CONFIGR_MODE_Pos         (4U)
14853 #define OTFDEC_REG_CONFIGR_MODE_Msk         (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000030 */
14854 #define OTFDEC_REG_CONFIGR_MODE             OTFDEC_REG_CONFIGR_MODE_Msk             /*!< Region operating mode */
14855 #define OTFDEC_REG_CONFIGR_MODE_0           (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000010 */
14856 #define OTFDEC_REG_CONFIGR_MODE_1           (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000020 */
14857 #define OTFDEC_REG_CONFIGR_KEYCRC_Pos       (8U)
14858 #define OTFDEC_REG_CONFIGR_KEYCRC_Msk       (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos) /*!< 0x0000FF00 */
14859 #define OTFDEC_REG_CONFIGR_KEYCRC           OTFDEC_REG_CONFIGR_KEYCRC_Msk           /*!< Region key 8-bit CRC */
14860 #define OTFDEC_REG_CONFIGR_VERSION_Pos      (16U)
14861 #define OTFDEC_REG_CONFIGR_VERSION_Msk      (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos) /*!< 0xFFFF0000 */
14862 #define OTFDEC_REG_CONFIGR_VERSION          OTFDEC_REG_CONFIGR_VERSION_Msk          /*!< Region firmware version */
14863 
14864 /******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/
14865 #define OTFDEC_REG_START_ADDR_Pos           (0U)
14866 #define OTFDEC_REG_START_ADDR_Msk           (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos) /*!< 0xFFFFFFFF */
14867 #define OTFDEC_REG_START_ADDR               OTFDEC_REG_START_ADDR_Msk               /*!< Region AHB start address */
14868 
14869 /******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/
14870 #define OTFDEC_REG_END_ADDR_Pos             (0U)
14871 #define OTFDEC_REG_END_ADDR_Msk             (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos) /*!< 0xFFFFFFFF */
14872 #define OTFDEC_REG_END_ADDR                 OTFDEC_REG_END_ADDR_Msk                 /*!< Region AHB end address */
14873 
14874 /******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/
14875 #define OTFDEC_REG_NONCER0_Pos              (0U)
14876 #define OTFDEC_REG_NONCER0_Msk              (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos) /*!< 0xFFFFFFFF */
14877 #define OTFDEC_REG_NONCER0                  OTFDEC_REG_NONCER0_Msk                  /*!< Region Nonce Register (LSB nonce[31:0]) */
14878 
14879 /******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/
14880 #define OTFDEC_REG_NONCER1_Pos              (0U)
14881 #define OTFDEC_REG_NONCER1_Msk              (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos) /*!< 0xFFFFFFFF */
14882 #define OTFDEC_REG_NONCER1                  OTFDEC_REG_NONCER1_Msk                  /*!< Region Nonce Register (MSB nonce[63:32]) */
14883 
14884 /******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/
14885 #define OTFDEC_REG_KEYR0_Pos                (0U)
14886 #define OTFDEC_REG_KEYR0_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)  /*!< 0xFFFFFFFF */
14887 #define OTFDEC_REG_KEYR0                    OTFDEC_REG_KEYR0_Msk                    /*!< Region Key Register (LSB key[31:0]) */
14888 
14889 /******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/
14890 #define OTFDEC_REG_KEYR1_Pos                (0U)
14891 #define OTFDEC_REG_KEYR1_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)  /*!< 0xFFFFFFFF */
14892 #define OTFDEC_REG_KEYR1                    OTFDEC_REG_KEYR1_Msk                    /*!< Region Key Register (key[63:32]) */
14893 
14894 /******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/
14895 #define OTFDEC_REG_KEYR2_Pos                (0U)
14896 #define OTFDEC_REG_KEYR2_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)  /*!< 0xFFFFFFFF */
14897 #define OTFDEC_REG_KEYR2                    OTFDEC_REG_KEYR2_Msk                    /*!< Region Key Register (key[95:64]) */
14898 
14899 /******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/
14900 #define OTFDEC_REG_KEYR3_Pos                (0U)
14901 #define OTFDEC_REG_KEYR3_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)  /*!< 0xFFFFFFFF */
14902 #define OTFDEC_REG_KEYR3                    OTFDEC_REG_KEYR3_Msk                    /*!< Region Key Register (key[127:96]) */
14903 
14904 /******************  Bit definition for OTFDEC_ISR register  *****************/
14905 #define OTFDEC_ISR_SEIF_Pos                 (0U)
14906 #define OTFDEC_ISR_SEIF_Msk                 (0x1UL << OTFDEC_ISR_SEIF_Pos)          /*!< 0x00000001 */
14907 #define OTFDEC_ISR_SEIF                     OTFDEC_ISR_SEIF_Msk                     /*!< Security Error Interrupt Flag status bit before enable (mask) */
14908 #define OTFDEC_ISR_XONEIF_Pos               (1U)
14909 #define OTFDEC_ISR_XONEIF_Msk               (0x1UL << OTFDEC_ISR_XONEIF_Pos)        /*!< 0x00000002 */
14910 #define OTFDEC_ISR_XONEIF                   OTFDEC_ISR_XONEIF_Msk                   /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */
14911 #define OTFDEC_ISR_KEIF_Pos                 (2U)
14912 #define OTFDEC_ISR_KEIF_Msk                 (0x1UL << OTFDEC_ISR_KEIF_Pos)          /*!< 0x00000004 */
14913 #define OTFDEC_ISR_KEIF                     OTFDEC_ISR_KEIF_Msk                     /*!< Key Error Interrupt Flag status bit before enable (mask) */
14914 
14915 /******************  Bit definition  for OTFDEC_ICR register  *****************/
14916 #define OTFDEC_ICR_SEIF_Pos                 (0U)
14917 #define OTFDEC_ICR_SEIF_Msk                 (0x1UL << OTFDEC_ICR_SEIF_Pos)          /*!< 0x00000001 */
14918 #define OTFDEC_ICR_SEIF                     OTFDEC_ICR_SEIF_Msk                     /*!< Security Error Interrupt Flag clear bit */
14919 #define OTFDEC_ICR_XONEIF_Pos               (1U)
14920 #define OTFDEC_ICR_XONEIF_Msk               (0x1UL << OTFDEC_ICR_XONEIF_Pos)        /*!< 0x00000002 */
14921 #define OTFDEC_ICR_XONEIF                   OTFDEC_ICR_XONEIF_Msk                   /*!< Execute-only Error Interrupt Flag clear bit */
14922 #define OTFDEC_ICR_KEIF_Pos                 (2U)
14923 #define OTFDEC_ICR_KEIF_Msk                 (0x1UL << OTFDEC_ICR_KEIF_Pos)          /*!< 0x00000004 */
14924 #define OTFDEC_ICR_KEIF                     OTFDEC_ICR_KEIF_Msk                     /*!< Key Error Interrupt Flag clear bit */
14925 
14926 /******************  Bit definition for OTFDEC_IER register  *****************/
14927 #define OTFDEC_IER_SEIE_Pos                 (0U)
14928 #define OTFDEC_IER_SEIE_Msk                 (0x1UL << OTFDEC_IER_SEIE_Pos)          /*!< 0x00000001 */
14929 #define OTFDEC_IER_SEIE                     OTFDEC_IER_SEIE_Msk                     /*!< Security Error Interrupt Enable bit */
14930 #define OTFDEC_IER_XONEIE_Pos               (1U)
14931 #define OTFDEC_IER_XONEIE_Msk               (0x1UL << OTFDEC_IER_XONEIE_Pos)        /*!< 0x00000002 */
14932 #define OTFDEC_IER_XONEIE                   OTFDEC_IER_XONEIE_Msk                   /*!< Execute-only Error Interrupt Enable bit */
14933 #define OTFDEC_IER_KEIE_Pos                 (2U)
14934 #define OTFDEC_IER_KEIE_Msk                 (0x1UL << OTFDEC_IER_KEIE_Pos)          /*!< 0x00000004 */
14935 #define OTFDEC_IER_KEIE                     OTFDEC_IER_KEIE_Msk
14936 
14937 /******************************************************************************/
14938 /*                                                                            */
14939 /*                             Power Control                                  */
14940 /*                                                                            */
14941 /******************************************************************************/
14942 /********************  Bit definition for PWR_PMCR register  ******************/
14943 #define PWR_PMCR_LPMS_Pos                    (0U)
14944 #define PWR_PMCR_LPMS_Msk                    (0x1UL << PWR_PMCR_LPMS_Pos)
14945 #define PWR_PMCR_LPMS                        PWR_PMCR_LPMS_Msk
14946 #define PWR_PMCR_SVOS_Pos                    (2U)
14947 #define PWR_PMCR_SVOS_Msk                    (0x3UL << PWR_PMCR_SVOS_Pos)
14948 #define PWR_PMCR_SVOS                        PWR_PMCR_SVOS_Msk
14949 #define PWR_PMCR_SVOS_0                      (0x1UL << PWR_PMCR_SVOS_Pos)
14950 #define PWR_PMCR_SVOS_1                      (0x2UL << PWR_PMCR_SVOS_Pos)
14951 #define PWR_PMCR_CSSF_Pos                    (7U)
14952 #define PWR_PMCR_CSSF_Msk                    (0x1UL << PWR_PMCR_CSSF_Pos)
14953 #define PWR_PMCR_CSSF                        PWR_PMCR_CSSF_Msk
14954 #define PWR_PMCR_FLPS_Pos                    (9U)
14955 #define PWR_PMCR_FLPS_Msk                    (0x1UL << PWR_PMCR_FLPS_Pos)
14956 #define PWR_PMCR_FLPS                        PWR_PMCR_FLPS_Msk
14957 #define PWR_PMCR_BOOSTE_Pos                  (12U)
14958 #define PWR_PMCR_BOOSTE_Msk                  (0x1UL << PWR_PMCR_BOOSTE_Pos)
14959 #define PWR_PMCR_BOOSTE                      PWR_PMCR_BOOSTE_Msk
14960 #define PWR_PMCR_AVD_READY_Pos               (13U)
14961 #define PWR_PMCR_AVD_READY_Msk               (0x1UL << PWR_PMCR_AVD_READY_Pos)
14962 #define PWR_PMCR_AVD_READY                   PWR_PMCR_AVD_READY_Msk
14963 #define PWR_PMCR_ETHERNETSO_Pos             (16U)
14964 #define PWR_PMCR_ETHERNETSO_Msk             (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
14965 #define PWR_PMCR_ETHERNETSO                 PWR_PMCR_ETHERNETSO_Msk
14966 #define PWR_PMCR_SRAM3SO_Pos                 (23U)
14967 #define PWR_PMCR_SRAM3SO_Msk                 (0x1UL << PWR_PMCR_SRAM3SO_Pos)
14968 #define PWR_PMCR_SRAM3SO                     PWR_PMCR_SRAM3SO_Msk
14969 #define PWR_PMCR_SRAM2_16SO_Pos              (24U)
14970 #define PWR_PMCR_SRAM2_16SO_Msk              (0x1UL << PWR_PMCR_SRAM2_16SO_Pos)
14971 #define PWR_PMCR_SRAM2_16SO                  PWR_PMCR_SRAM2_16SO_Msk
14972 #define PWR_PMCR_SRAM2_48SO_Pos              (25U)
14973 #define PWR_PMCR_SRAM2_48SO_Msk              (0x1UL << PWR_PMCR_SRAM2_48SO_Pos)
14974 #define PWR_PMCR_SRAM2_48SO                  PWR_PMCR_SRAM2_48SO_Msk
14975 #define PWR_PMCR_SRAM1SO_Pos                 (26U)
14976 #define PWR_PMCR_SRAM1SO_Msk                 (0x1UL << PWR_PMCR_SRAM1SO_Pos)
14977 #define PWR_PMCR_SRAM1SO                     PWR_PMCR_SRAM1SO_Msk
14978 
14979 /********************  Bit definition for PWR_PMSR register  *******************/
14980 #define PWR_PMSR_STOPF_Pos                   (5U)
14981 #define PWR_PMSR_STOPF_Msk                   (0x1UL << PWR_PMSR_STOPF_Pos)
14982 #define PWR_PMSR_STOPF                       PWR_PMSR_STOPF_Msk
14983 #define PWR_PMSR_SBF_Pos                     (6U)
14984 #define PWR_PMSR_SBF_Msk                     (0x1UL << PWR_PMSR_SBF_Pos)
14985 #define PWR_PMSR_SBF                         PWR_PMSR_SBF_Msk
14986 
14987 /********************  Bit definition for PWR_VOSCR register  ******************/
14988 #define PWR_VOSCR_VOS_Pos                    (4U)
14989 #define PWR_VOSCR_VOS_Msk                    (0x3UL << PWR_VOSCR_VOS_Pos)
14990 #define PWR_VOSCR_VOS                        PWR_VOSCR_VOS_Msk
14991 #define PWR_VOSCR_VOS_0                      (0x1UL << PWR_VOSCR_VOS_Pos)
14992 #define PWR_VOSCR_VOS_1                      (0x2UL << PWR_VOSCR_VOS_Pos)
14993 
14994 /********************  Bit definition for PWR_VOSSR register  *****************/
14995 #define PWR_VOSSR_VOSRDY_Pos                 (3U)
14996 #define PWR_VOSSR_VOSRDY_Msk                 (0x1UL << PWR_VOSSR_VOSRDY_Pos)
14997 #define PWR_VOSSR_VOSRDY                     PWR_VOSSR_VOSRDY_Msk
14998 #define PWR_VOSSR_ACTVOSRDY_Pos              (13U)
14999 #define PWR_VOSSR_ACTVOSRDY_Msk              (0x1UL << PWR_VOSSR_ACTVOSRDY_Pos)
15000 #define PWR_VOSSR_ACTVOSRDY                  PWR_VOSSR_ACTVOSRDY_Msk
15001 #define PWR_VOSSR_ACTVOS_Pos                 (14U)
15002 #define PWR_VOSSR_ACTVOS_Msk                 (0x3UL << PWR_VOSSR_ACTVOS_Pos)
15003 #define PWR_VOSSR_ACTVOS                     PWR_VOSSR_ACTVOS_Msk
15004 #define PWR_VOSSR_ACTVOS_0                   (0x1UL << PWR_VOSSR_ACTVOS_Pos)
15005 #define PWR_VOSSR_ACTVOS_1                   (0x2UL << PWR_VOSSR_ACTVOS_Pos)
15006 
15007 /********************  Bit definition for PWR_BDCR register  ******************/
15008 #define PWR_BDCR_BREN_Pos                    (0U)
15009 #define PWR_BDCR_BREN_Msk                    (0x1UL << PWR_BDCR_BREN_Pos)
15010 #define PWR_BDCR_BREN                        PWR_BDCR_BREN_Msk
15011 #define PWR_BDCR_MONEN_Pos                   (1U)
15012 #define PWR_BDCR_MONEN_Msk                   (0x1UL << PWR_BDCR_MONEN_Pos)
15013 #define PWR_BDCR_MONEN                       PWR_BDCR_MONEN_Msk
15014 #define PWR_BDCR_VBE_Pos                     (8U)
15015 #define PWR_BDCR_VBE_Msk                     (0x1UL << PWR_BDCR_VBE_Pos)
15016 #define PWR_BDCR_VBE                         PWR_BDCR_VBE_Msk
15017 #define PWR_BDCR_VBRS_Pos                    (9U)
15018 #define PWR_BDCR_VBRS_Msk                    (0x1UL << PWR_BDCR_VBRS_Pos)
15019 #define PWR_BDCR_VBRS                        PWR_BDCR_VBRS_Msk
15020 
15021 /********************  Bit definition for PWR_DBPCR register  *****************/
15022 #define PWR_DBPCR_DBP_Pos                    (0U)
15023 #define PWR_DBPCR_DBP_Msk                    (0x1UL << PWR_DBPCR_DBP_Pos)
15024 #define PWR_DBPCR_DBP                        PWR_DBPCR_DBP_Msk
15025 
15026 /********************  Bit definition for PWR_BDSR register  ******************/
15027 #define PWR_BDSR_BRRDY_Pos                   (16U)
15028 #define PWR_BDSR_BRRDY_Msk                   (0x1UL << PWR_BDSR_BRRDY_Pos)
15029 #define PWR_BDSR_BRRDY                       PWR_BDSR_BRRDY_Msk
15030 #define PWR_BDSR_VBATL_Pos                   (20U)
15031 #define PWR_BDSR_VBATL_Msk                   (0x1UL << PWR_BDSR_VBATL_Pos)
15032 #define PWR_BDSR_VBATL                       PWR_BDSR_VBATL_Msk
15033 #define PWR_BDSR_VBATH_Pos                   (21U)
15034 #define PWR_BDSR_VBATH_Msk                   (0x1UL << PWR_BDSR_VBATH_Pos)
15035 #define PWR_BDSR_VBATH                       PWR_BDSR_VBATH_Msk
15036 #define PWR_BDSR_TEMPL_Pos                   (22U)
15037 #define PWR_BDSR_TEMPL_Msk                   (0x1UL << PWR_BDSR_TEMPL_Pos)
15038 #define PWR_BDSR_TEMPL                       PWR_BDSR_TEMPL_Msk
15039 #define PWR_BDSR_TEMPH_Pos                   (23U)
15040 #define PWR_BDSR_TEMPH_Msk                   (0x1UL << PWR_BDSR_TEMPH_Pos)
15041 #define PWR_BDSR_TEMPH                       PWR_BDSR_TEMPH_Msk
15042 
15043 /********************  Bit definition for PWR_UCPDR register  *****************/
15044 #define PWR_UCPDR_UCPD_DBDIS_Pos             (0U)
15045 #define PWR_UCPDR_UCPD_DBDIS_Msk             (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos)
15046 #define PWR_UCPDR_UCPD_DBDIS                 PWR_UCPDR_UCPD_DBDIS_Msk
15047 #define PWR_UCPDR_UCPD_STBY_Pos              (1U)
15048 #define PWR_UCPDR_UCPD_STBY_Msk              (0x1UL << PWR_UCPDR_UCPD_STBY_Pos)
15049 #define PWR_UCPDR_UCPD_STBY                  PWR_UCPDR_UCPD_STBY_Msk
15050 
15051 /********************  Bit definition for PWR_SCCR register  ******************/
15052 #define PWR_SCCR_BYPASS_Pos                  (0U)
15053 #define PWR_SCCR_BYPASS_Msk                  (0x1UL << PWR_SCCR_BYPASS_Pos)
15054 #define PWR_SCCR_BYPASS                      PWR_SCCR_BYPASS_Msk
15055 #define PWR_SCCR_LDOEN_Pos                   (8U)
15056 #define PWR_SCCR_LDOEN_Msk                   (0x1UL << PWR_SCCR_LDOEN_Pos)
15057 #define PWR_SCCR_LDOEN                       PWR_SCCR_LDOEN_Msk
15058 #define PWR_SCCR_SMPSEN_Pos                  (9U)
15059 #define PWR_SCCR_SMPSEN_Msk                  (0x1UL << PWR_SCCR_SMPSEN_Pos)
15060 #define PWR_SCCR_SMPSEN                      PWR_SCCR_SMPSEN_Msk
15061 
15062 /********************  Bit definition for PWR_VMCR register  ******************/
15063 #define PWR_VMCR_PVDEN_Pos                    (0U)
15064 #define PWR_VMCR_PVDEN_Msk                    (0x1UL << PWR_VMCR_PVDEN_Pos)
15065 #define PWR_VMCR_PVDEN                        PWR_VMCR_PVDEN_Msk
15066 #define PWR_VMCR_PLS_Pos                     (1U)
15067 #define PWR_VMCR_PLS_Msk                     (0x3UL << PWR_VMCR_PLS_Pos)
15068 #define PWR_VMCR_PLS                         PWR_VMCR_PLS_Msk
15069 #define PWR_VMCR_PLS_0                       (0x1UL << PWR_VMCR_PLS_Pos)
15070 #define PWR_VMCR_PLS_1                       (0x2UL << PWR_VMCR_PLS_Pos)
15071 #define PWR_VMCR_PLS_2                       (0x4UL << PWR_VMCR_PLS_Pos)
15072 #define PWR_VMCR_AVDEN_Pos                   (8U)
15073 #define PWR_VMCR_AVDEN_Msk                   (0x1UL << PWR_VMCR_AVDEN_Pos)
15074 #define PWR_VMCR_AVDEN                       PWR_VMCR_AVDEN_Msk
15075 #define PWR_VMCR_ALS_Pos                     (9U)
15076 #define PWR_VMCR_ALS_Msk                     (0x3UL << PWR_VMCR_ALS_Pos)
15077 #define PWR_VMCR_ALS                         PWR_VMCR_ALS_Msk
15078 #define PWR_VMCR_ALS_0                       (0x1UL << PWR_VMCR_ALS_Pos)
15079 #define PWR_VMCR_ALS_1                       (0x2UL << PWR_VMCR_ALS_Pos)
15080 
15081 /********************  Bit definition for PWR_USBSCR register  ******************/
15082 #define PWR_USBSCR_USB33DEN_Pos               (24U)
15083 #define PWR_USBSCR_USB33DEN_Msk               (0x1UL << PWR_USBSCR_USB33DEN_Pos)
15084 #define PWR_USBSCR_USB33DEN                   PWR_USBSCR_USB33DEN_Msk
15085 #define PWR_USBSCR_USB33SV_Pos                (25U)
15086 #define PWR_USBSCR_USB33SV_Msk                (0x1UL << PWR_USBSCR_USB33SV_Pos)
15087 #define PWR_USBSCR_USB33SV                    PWR_USBSCR_USB33SV_Msk
15088 
15089 /********************  Bit definition for PWR_VMSR register  ******************/
15090 #define PWR_VMSR_AVDO_Pos                    (19U)
15091 #define PWR_VMSR_AVDO_Msk                    (0x1UL << PWR_VMSR_AVDO_Pos)
15092 #define PWR_VMSR_AVDO                        PWR_VMSR_AVDO_Msk
15093 #define PWR_VMSR_VDDIO2RDY_Pos               (20U)
15094 #define PWR_VMSR_VDDIO2RDY_Msk               (0x1UL << PWR_VMSR_VDDIO2RDY_Pos)
15095 #define PWR_VMSR_VDDIO2RDY                   PWR_VMSR_VDDIO2RDY_Msk
15096 #define PWR_VMSR_PVDO_Pos                    (22U)
15097 #define PWR_VMSR_PVDO_Msk                    (0x1UL << PWR_VMSR_PVDO_Pos)
15098 #define PWR_VMSR_PVDO                        PWR_VMSR_PVDO_Msk
15099 #define PWR_VMSR_USB33RDY_Pos                (24U)
15100 #define PWR_VMSR_USB33RDY_Msk                (0x1UL << PWR_VMSR_USB33RDY_Pos)
15101 #define PWR_VMSR_USB33RDY                    PWR_VMSR_USB33RDY_Msk
15102 
15103 /********************  Bit definition for PWR_WUSCR register  ****************/
15104 #define PWR_WUSCR_CWUF1_Pos                (0U)
15105 #define PWR_WUSCR_CWUF1_Msk                (0x1UL << PWR_WUSCR_CWUF1_Pos)
15106 #define PWR_WUSCR_CWUF1                    PWR_WUSCR_CWUF1_Msk
15107 #define PWR_WUSCR_CWUF2_Pos                (1U)
15108 #define PWR_WUSCR_CWUF2_Msk                (0x1UL << PWR_WUSCR_CWUF2_Pos)
15109 #define PWR_WUSCR_CWUF2                    PWR_WUSCR_CWUF2_Msk
15110 #define PWR_WUSCR_CWUF3_Pos                (2U)
15111 #define PWR_WUSCR_CWUF3_Msk                (0x1UL << PWR_WUSCR_CWUF3_Pos)
15112 #define PWR_WUSCR_CWUF3                    PWR_WUSCR_CWUF3_Msk
15113 #define PWR_WUSCR_CWUF4_Pos                (3U)
15114 #define PWR_WUSCR_CWUF4_Msk                (0x1UL << PWR_WUSCR_CWUF4_Pos)
15115 #define PWR_WUSCR_CWUF4                    PWR_WUSCR_CWUF4_Msk
15116 #define PWR_WUSCR_CWUF5_Pos                (4U)
15117 #define PWR_WUSCR_CWUF5_Msk                (0x1UL << PWR_WUSCR_CWUF5_Pos)
15118 #define PWR_WUSCR_CWUF5                    PWR_WUSCR_CWUF5_Msk
15119 #define PWR_WUSCR_CWUF6_Pos                (5U)
15120 #define PWR_WUSCR_CWUF6_Msk                (0x1UL << PWR_WUSCR_CWUF6_Pos)
15121 #define PWR_WUSCR_CWUF6                    PWR_WUSCR_CWUF6_Msk
15122 #define PWR_WUSCR_CWUF7_Pos                (6U)
15123 #define PWR_WUSCR_CWUF7_Msk                (0x1UL << PWR_WUSCR_CWUF7_Pos)
15124 #define PWR_WUSCR_CWUF7                    PWR_WUSCR_CWUF7_Msk
15125 #define PWR_WUSCR_CWUF8_Pos                (7U)
15126 #define PWR_WUSCR_CWUF8_Msk                (0x1UL << PWR_WUSCR_CWUF8_Pos)
15127 #define PWR_WUSCR_CWUF8                    PWR_WUSCR_CWUF8_Msk
15128 #define PWR_WUSCR_CWUF_Pos                 (0U)
15129 #define PWR_WUSCR_CWUF_Msk                 (0xFFUL << PWR_WUSCR_CWUF_Pos)
15130 #define PWR_WUSCR_CWUF                     PWR_WUSCR_CWUF_Msk
15131 
15132 /********************  Bit definition for PWR_WUSR register  ****************/
15133 #define PWR_WUSR_WUF1_Pos                (0U)
15134 #define PWR_WUSR_WUF1_Msk                (0x1UL << PWR_WUSR_WUF1_Pos)
15135 #define PWR_WUSR_WUF1                    PWR_WUSR_WUF1_Msk
15136 #define PWR_WUSR_WUF2_Pos                (1U)
15137 #define PWR_WUSR_WUF2_Msk                (0x1UL << PWR_WUSR_WUF2_Pos)
15138 #define PWR_WUSR_WUF2                    PWR_WUSR_WUF2_Msk
15139 #define PWR_WUSR_WUF3_Pos                (2U)
15140 #define PWR_WUSR_WUF3_Msk                (0x1UL << PWR_WUSR_WUF3_Pos)
15141 #define PWR_WUSR_WUF3                    PWR_WUSR_WUF3_Msk
15142 #define PWR_WUSR_WUF4_Pos                (3U)
15143 #define PWR_WUSR_WUF4_Msk                (0x1UL << PWR_WUSR_WUF4_Pos)
15144 #define PWR_WUSR_WUF4                    PWR_WUSR_WUF4_Msk
15145 #define PWR_WUSR_WUF5_Pos                (4U)
15146 #define PWR_WUSR_WUF5_Msk                (0x1UL << PWR_WUSR_WUF5_Pos)
15147 #define PWR_WUSR_WUF5                    PWR_WUSR_WUF5_Msk
15148 #define PWR_WUSR_WUF6_Pos                (5U)
15149 #define PWR_WUSR_WUF6_Msk                (0x1UL << PWR_WUSR_WUF6_Pos)
15150 #define PWR_WUSR_WUF6                    PWR_WUSR_WUF6_Msk
15151 #define PWR_WUSR_WUF7_Pos                (6U)
15152 #define PWR_WUSR_WUF7_Msk                (0x1UL << PWR_WUSR_WUF7_Pos)
15153 #define PWR_WUSR_WUF7                    PWR_WUSR_WUF7_Msk
15154 #define PWR_WUSR_WUF8_Pos                (7U)
15155 #define PWR_WUSR_WUF8_Msk                (0x1UL << PWR_WUSR_WUF8_Pos)
15156 #define PWR_WUSR_WUF8                    PWR_WUSR_WUF8_Msk
15157 
15158 /********************  Bit definition for PWR_WUCR register  ***************/
15159 #define PWR_WUCR_WUPEN1_Pos              (0U)
15160 #define PWR_WUCR_WUPEN1_Msk              (0x1UL << PWR_WUCR_WUPEN1_Pos)
15161 #define PWR_WUCR_WUPEN1                  PWR_WUCR_WUPEN1_Msk
15162 #define PWR_WUCR_WUPEN2_Pos              (1U)
15163 #define PWR_WUCR_WUPEN2_Msk              (0x1UL << PWR_WUCR_WUPEN2_Pos)
15164 #define PWR_WUCR_WUPEN2                  PWR_WUCR_WUPEN2_Msk
15165 #define PWR_WUCR_WUPEN3_Pos              (2U)
15166 #define PWR_WUCR_WUPEN3_Msk              (0x1UL << PWR_WUCR_WUPEN3_Pos)
15167 #define PWR_WUCR_WUPEN3                  PWR_WUCR_WUPEN3_Msk
15168 #define PWR_WUCR_WUPEN4_Pos              (3U)
15169 #define PWR_WUCR_WUPEN4_Msk              (0x1UL << PWR_WUCR_WUPEN4_Pos)
15170 #define PWR_WUCR_WUPEN4                  PWR_WUCR_WUPEN4_Msk
15171 #define PWR_WUCR_WUPEN5_Pos              (4U)
15172 #define PWR_WUCR_WUPEN5_Msk              (0x1UL << PWR_WUCR_WUPEN5_Pos)
15173 #define PWR_WUCR_WUPEN5                  PWR_WUCR_WUPEN5_Msk
15174 #define PWR_WUCR_WUPEN6_Pos              (5U)
15175 #define PWR_WUCR_WUPEN6_Msk              (0x1UL << PWR_WUCR_WUPEN6_Pos)
15176 #define PWR_WUCR_WUPEN6                  PWR_WUCR_WUPEN6_Msk
15177 #define PWR_WUCR_WUPEN7_Pos              (6U)
15178 #define PWR_WUCR_WUPEN7_Msk              (0x1UL << PWR_WUCR_WUPEN7_Pos)
15179 #define PWR_WUCR_WUPEN7                  PWR_WUCR_WUPEN7_Msk
15180 #define PWR_WUCR_WUPEN8_Pos              (7U)
15181 #define PWR_WUCR_WUPEN8_Msk              (0x1UL << PWR_WUCR_WUPEN8_Pos)
15182 #define PWR_WUCR_WUPEN8                  PWR_WUCR_WUPEN8_Msk
15183 #define PWR_WUCR_WUPEN_Pos               (0U)
15184 #define PWR_WUCR_WUPEN_Msk               (0xFFUL << PWR_WUCR_WUPEN_Pos)
15185 #define PWR_WUCR_WUPEN                   PWR_WUCR_WUPEN_Msk
15186 #define PWR_WUCR_WUPP1_Pos               (8U)
15187 #define PWR_WUCR_WUPP1_Msk               (0x1UL << PWR_WUCR_WUPP1_Pos)
15188 #define PWR_WUCR_WUPP1                   PWR_WUCR_WUPP1_Msk
15189 #define PWR_WUCR_WUPP2_Pos               (9U)
15190 #define PWR_WUCR_WUPP2_Msk               (0x1UL << PWR_WUCR_WUPP2_Pos)
15191 #define PWR_WUCR_WUPP2                   PWR_WUCR_WUPP2_Msk
15192 #define PWR_WUCR_WUPP3_Pos               (10U)
15193 #define PWR_WUCR_WUPP3_Msk               (0x1UL << PWR_WUCR_WUPP3_Pos)
15194 #define PWR_WUCR_WUPP3                   PWR_WUCR_WUPP3_Msk
15195 #define PWR_WUCR_WUPP4_Pos               (11U)
15196 #define PWR_WUCR_WUPP4_Msk               (0x1UL << PWR_WUCR_WUPP4_Pos)
15197 #define PWR_WUCR_WUPP4                   PWR_WUCR_WUPP4_Msk
15198 #define PWR_WUCR_WUPP5_Pos               (12U)
15199 #define PWR_WUCR_WUPP5_Msk               (0x1UL << PWR_WUCR_WUPP5_Pos)
15200 #define PWR_WUCR_WUPP5                   PWR_WUCR_WUPP5_Msk
15201 #define PWR_WUCR_WUPP6_Pos               (13U)
15202 #define PWR_WUCR_WUPP6_Msk               (0x1UL << PWR_WUCR_WUPP6_Pos)
15203 #define PWR_WUCR_WUPP6                   PWR_WUCR_WUPP6_Msk
15204 #define PWR_WUCR_WUPP7_Pos               (14U)
15205 #define PWR_WUCR_WUPP7_Msk               (0x1UL << PWR_WUCR_WUPP7_Pos)
15206 #define PWR_WUCR_WUPP7                   PWR_WUCR_WUPP7_Msk
15207 #define PWR_WUCR_WUPP8_Pos               (15U)
15208 #define PWR_WUCR_WUPP8_Msk               (0x1UL << PWR_WUCR_WUPP8_Pos)
15209 #define PWR_WUCR_WUPP8                   PWR_WUCR_WUPP8_Msk
15210 #define PWR_WUCR_WUPPUPD1_Pos            (16U)
15211 #define PWR_WUCR_WUPPUPD1_Msk            (0x3UL << PWR_WUCR_WUPPUPD1_Pos)
15212 #define PWR_WUCR_WUPPUPD1                PWR_WUCR_WUPPUPD1_Msk
15213 #define PWR_WUCR_WUPPUPD1_0              (0x1UL << PWR_WUCR_WUPPUPD1_Pos)
15214 #define PWR_WUCR_WUPPUPD1_1              (0x2UL << PWR_WUCR_WUPPUPD1_Pos)
15215 #define PWR_WUCR_WUPPUPD2_Pos            (18U)
15216 #define PWR_WUCR_WUPPUPD2_Msk            (0x3UL << PWR_WUCR_WUPPUPD2_Pos)
15217 #define PWR_WUCR_WUPPUPD2                PWR_WUCR_WUPPUPD2_Msk
15218 #define PWR_WUCR_WUPPUPD2_0              (0x1UL << PWR_WUCR_WUPPUPD2_Pos)
15219 #define PWR_WUCR_WUPPUPD2_1              (0x2UL << PWR_WUCR_WUPPUPD2_Pos)
15220 #define PWR_WUCR_WUPPUPD3_Pos            (20U)
15221 #define PWR_WUCR_WUPPUPD3_Msk            (0x3UL << PWR_WUCR_WUPPUPD3_Pos)
15222 #define PWR_WUCR_WUPPUPD3                PWR_WUCR_WUPPUPD3_Msk
15223 #define PWR_WUCR_WUPPUPD3_0              (0x1UL << PWR_WUCR_WUPPUPD3_Pos)
15224 #define PWR_WUCR_WUPPUPD3_1              (0x2UL << PWR_WUCR_WUPPUPD3_Pos)
15225 #define PWR_WUCR_WUPPUPD4_Pos            (22U)
15226 #define PWR_WUCR_WUPPUPD4_Msk            (0x3UL << PWR_WUCR_WUPPUPD4_Pos)
15227 #define PWR_WUCR_WUPPUPD4                PWR_WUCR_WUPPUPD4_Msk
15228 #define PWR_WUCR_WUPPUPD4_0              (0x1UL << PWR_WUCR_WUPPUPD4_Pos)
15229 #define PWR_WUCR_WUPPUPD4_1              (0x2UL << PWR_WUCR_WUPPUPD4_Pos)
15230 #define PWR_WUCR_WUPPUPD5_Pos            (24U)
15231 #define PWR_WUCR_WUPPUPD5_Msk            (0x3UL << PWR_WUCR_WUPPUPD5_Pos)
15232 #define PWR_WUCR_WUPPUPD5                PWR_WUCR_WUPPUPD5_Msk
15233 #define PWR_WUCR_WUPPUPD5_0              (0x1UL << PWR_WUCR_WUPPUPD5_Pos)
15234 #define PWR_WUCR_WUPPUPD5_1              (0x2UL << PWR_WUCR_WUPPUPD5_Pos)
15235 #define PWR_WUCR_WUPPUPD6_Pos            (26U)
15236 #define PWR_WUCR_WUPPUPD6_Msk            (0x3UL << PWR_WUCR_WUPPUPD6_Pos)
15237 #define PWR_WUCR_WUPPUPD6                PWR_WUCR_WUPPUPD6_Msk
15238 #define PWR_WUCR_WUPPUPD6_0              (0x1UL << PWR_WUCR_WUPPUPD6_Pos)
15239 #define PWR_WUCR_WUPPUPD6_1              (0x2UL << PWR_WUCR_WUPPUPD6_Pos)
15240 #define PWR_WUCR_WUPPUPD7_Pos            (28U)
15241 #define PWR_WUCR_WUPPUPD7_Msk            (0x3UL << PWR_WUCR_WUPPUPD7_Pos)
15242 #define PWR_WUCR_WUPPUPD7                PWR_WUCR_WUPPUPD7_Msk
15243 #define PWR_WUCR_WUPPUPD7_0              (0x1UL << PWR_WUCR_WUPPUPD7_Pos)
15244 #define PWR_WUCR_WUPPUPD7_1              (0x2UL << PWR_WUCR_WUPPUPD7_Pos)
15245 #define PWR_WUCR_WUPPUPD8_Pos            (30U)
15246 #define PWR_WUCR_WUPPUPD8_Msk            (0x3UL << PWR_WUCR_WUPPUPD8_Pos)
15247 #define PWR_WUCR_WUPPUPD8                PWR_WUCR_WUPPUPD8_Msk
15248 #define PWR_WUCR_WUPPUPD8_0              (0x1UL << PWR_WUCR_WUPPUPD8_Pos)
15249 #define PWR_WUCR_WUPPUPD8_1              (0x2UL << PWR_WUCR_WUPPUPD8_Pos)
15250 
15251 /********************  Bit definition for PWR_IORET register  ****************/
15252 #define PWR_IORETR_IORETREN_Pos          (0U)
15253 #define PWR_IORETR_IORETREN_Msk          (0x1UL << PWR_IORETR_IORETREN_Pos)
15254 #define PWR_IORETR_IORETREN              PWR_IORETR_IORETREN_Msk
15255 #define PWR_IORETR_JTAGIORETEN_Pos       (16U)
15256 #define PWR_IORETR_JTAGIORETEN_Msk       (0x1UL << PWR_IORETR_JTAGIORETEN_Pos)
15257 #define PWR_IORETR_JTAGIORETEN           PWR_IORETR_JTAGIORETEN_Msk
15258 
15259 /********************  Bit definition for PWR_SECCFGR register  ***************/
15260 #define PWR_SECCFGR_WUP1SEC_Pos          (0U)
15261 #define PWR_SECCFGR_WUP1SEC_Msk          (0x1UL << PWR_SECCFGR_WUP1SEC_Pos)
15262 #define PWR_SECCFGR_WUP1SEC              PWR_SECCFGR_WUP1SEC_Msk
15263 #define PWR_SECCFGR_WUP2SEC_Pos          (1U)
15264 #define PWR_SECCFGR_WUP2SEC_Msk          (0x1UL << PWR_SECCFGR_WUP2SEC_Pos)
15265 #define PWR_SECCFGR_WUP2SEC              PWR_SECCFGR_WUP2SEC_Msk
15266 #define PWR_SECCFGR_WUP3SEC_Pos          (2U)
15267 #define PWR_SECCFGR_WUP3SEC_Msk          (0x1UL << PWR_SECCFGR_WUP3SEC_Pos)
15268 #define PWR_SECCFGR_WUP3SEC              PWR_SECCFGR_WUP3SEC_Msk
15269 #define PWR_SECCFGR_WUP4SEC_Pos          (3U)
15270 #define PWR_SECCFGR_WUP4SEC_Msk          (0x1UL << PWR_SECCFGR_WUP4SEC_Pos)
15271 #define PWR_SECCFGR_WUP4SEC              PWR_SECCFGR_WUP4SEC_Msk
15272 #define PWR_SECCFGR_WUP5SEC_Pos          (4U)
15273 #define PWR_SECCFGR_WUP5SEC_Msk          (0x1UL << PWR_SECCFGR_WUP5SEC_Pos)
15274 #define PWR_SECCFGR_WUP5SEC              PWR_SECCFGR_WUP5SEC_Msk
15275 #define PWR_SECCFGR_WUP6SEC_Pos          (5U)
15276 #define PWR_SECCFGR_WUP6SEC_Msk          (0x1UL << PWR_SECCFGR_WUP6SEC_Pos)
15277 #define PWR_SECCFGR_WUP6SEC              PWR_SECCFGR_WUP6SEC_Msk
15278 #define PWR_SECCFGR_WUP7SEC_Pos          (6U)
15279 #define PWR_SECCFGR_WUP7SEC_Msk          (0x1UL << PWR_SECCFGR_WUP7SEC_Pos)
15280 #define PWR_SECCFGR_WUP7SEC              PWR_SECCFGR_WUP7SEC_Msk
15281 #define PWR_SECCFGR_WUP8SEC_Pos          (7U)
15282 #define PWR_SECCFGR_WUP8SEC_Msk          (0x1UL << PWR_SECCFGR_WUP8SEC_Pos)
15283 #define PWR_SECCFGR_WUP8SEC              PWR_SECCFGR_WUP8SEC_Msk
15284 #define PWR_SECCFGR_RETSEC_Pos           (11U)
15285 #define PWR_SECCFGR_RETSEC_Msk           (0x1UL << PWR_SECCFGR_RETSEC_Pos)
15286 #define PWR_SECCFGR_RETSEC               PWR_SECCFGR_RETSEC_Msk
15287 #define PWR_SECCFGR_LPMSEC_Pos           (12U)
15288 #define PWR_SECCFGR_LPMSEC_Msk           (0x1UL << PWR_SECCFGR_LPMSEC_Pos)
15289 #define PWR_SECCFGR_LPMSEC               PWR_SECCFGR_LPMSEC_Msk
15290 #define PWR_SECCFGR_SCMSEC_Pos           (13U)
15291 #define PWR_SECCFGR_SCMSEC_Msk           (0x1UL << PWR_SECCFGR_SCMSEC_Pos)
15292 #define PWR_SECCFGR_SCMSEC               PWR_SECCFGR_SCMSEC_Msk
15293 #define PWR_SECCFGR_VBSEC_Pos            (14U)
15294 #define PWR_SECCFGR_VBSEC_Msk            (0x1UL << PWR_SECCFGR_VBSEC_Pos)
15295 #define PWR_SECCFGR_VBSEC                PWR_SECCFGR_VBSEC_Msk
15296 #define PWR_SECCFGR_VUSBSEC_Pos          (15U)
15297 #define PWR_SECCFGR_VUSBSEC_Msk          (0x1UL << PWR_SECCFGR_VUSBSEC_Pos)
15298 #define PWR_SECCFGR_VUSBSEC              PWR_SECCFGR_VUSBSEC_Msk
15299 
15300 /********************  Bit definition for PWR_PRIVCFGR register  **************/
15301 #define PWR_PRIVCFGR_SPRIV_Pos           (0U)
15302 #define PWR_PRIVCFGR_SPRIV_Msk           (0x1UL << PWR_PRIVCFGR_SPRIV_Pos)
15303 #define PWR_PRIVCFGR_SPRIV               PWR_PRIVCFGR_SPRIV_Msk
15304 #define PWR_PRIVCFGR_NSPRIV_Pos          (1U)
15305 #define PWR_PRIVCFGR_NSPRIV_Msk          (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos)
15306 #define PWR_PRIVCFGR_NSPRIV              PWR_PRIVCFGR_NSPRIV_Msk
15307 
15308 /******************************************************************************/
15309 /*                                                                            */
15310 /*                      SRAMs configuration controller                        */
15311 /*                                                                            */
15312 /******************************************************************************/
15313 /*******************  Bit definition for RAMCFG_CR register  ******************/
15314 #define RAMCFG_CR_ECCE_Pos                  (0U)
15315 #define RAMCFG_CR_ECCE_Msk                  (0x1UL << RAMCFG_CR_ECCE_Pos)           /*!< 0x00000001 */
15316 #define RAMCFG_CR_ECCE                      RAMCFG_CR_ECCE_Msk                      /*!< ECC Enable */
15317 #define RAMCFG_CR_ALE_Pos                   (4U)
15318 #define RAMCFG_CR_ALE_Msk                   (0x1UL << RAMCFG_CR_ALE_Pos)            /*!< 0x00000010 */
15319 #define RAMCFG_CR_ALE                       RAMCFG_CR_ALE_Msk                       /*!< Address Latching Enable */
15320 #define RAMCFG_CR_SRAMER_Pos                (8U)
15321 #define RAMCFG_CR_SRAMER_Msk                (0x1UL << RAMCFG_CR_SRAMER_Pos)         /*!< 0x00000100 */
15322 #define RAMCFG_CR_SRAMER                    RAMCFG_CR_SRAMER_Msk                    /*!< Start Erase */
15323 
15324 /*******************  Bit definition for RAMCFG_IER register  *****************/
15325 #define RAMCFG_IER_SEIE_Pos                 (0U)
15326 #define RAMCFG_IER_SEIE_Msk                 (0x1UL << RAMCFG_IER_SEIE_Pos)          /*!< 0x00000001 */
15327 #define RAMCFG_IER_SEIE                     RAMCFG_IER_SEIE_Msk                     /*!< Single Error Interrupt Enable */
15328 #define RAMCFG_IER_DEIE_Pos                 (1U)
15329 #define RAMCFG_IER_DEIE_Msk                 (0x1UL << RAMCFG_IER_DEIE_Pos)          /*!< 0x00000002 */
15330 #define RAMCFG_IER_DEIE                     RAMCFG_IER_DEIE_Msk                     /*!< Double Error Interrupt Enable */
15331 #define RAMCFG_IER_ECCNMI_Pos               (3U)
15332 #define RAMCFG_IER_ECCNMI_Msk               (0x1UL << RAMCFG_IER_ECCNMI_Pos)        /*!< 0x00000008 */
15333 #define RAMCFG_IER_ECCNMI                   RAMCFG_IER_ECCNMI_Msk                   /*!< NMI redirection interrupt */
15334 
15335 /*******************  Bit definition for RAMCFG_ISR register  *****************/
15336 #define RAMCFG_ISR_SEDC_Pos                 (0U)
15337 #define RAMCFG_ISR_SEDC_Msk                 (0x1UL << RAMCFG_ISR_SEDC_Pos)          /*!< 0x00000001 */
15338 #define RAMCFG_ISR_SEDC                     RAMCFG_ISR_SEDC_Msk                     /*!< Single Error Detected and Corrected flag */
15339 #define RAMCFG_ISR_DED_Pos                  (1U)
15340 #define RAMCFG_ISR_DED_Msk                  (0x1UL << RAMCFG_ISR_DED_Pos)           /*!< 0x00000002 */
15341 #define RAMCFG_ISR_DED                      RAMCFG_ISR_DED_Msk                      /*!< Double Error Detected flag */
15342 #define RAMCFG_ISR_SRAMBUSY_Pos             (8U)
15343 #define RAMCFG_ISR_SRAMBUSY_Msk             (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)      /*!< 0x00000100 */
15344 #define RAMCFG_ISR_SRAMBUSY                 RAMCFG_ISR_SRAMBUSY_Msk                 /*!< SRAM busy flag */
15345 
15346 /*******************  Bit definition for RAMCFG_SEAR register  ****************/
15347 #define RAMCFG_SEAR_ESEA_Pos                (0U)
15348 #define RAMCFG_SEAR_ESEA_Msk                (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos)  /*!< 0xFFFFFFFF */
15349 #define RAMCFG_SEAR_ESEA                    RAMCFG_SEAR_ESEA_Msk                    /*!< ECC Single Error Address */
15350 
15351 /*******************  Bit definition for RAMCFG_DEAR register  ****************/
15352 #define RAMCFG_DEAR_EDEA_Pos                (0U)
15353 #define RAMCFG_DEAR_EDEA_Msk                (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos)  /*!< 0xFFFFFFFF */
15354 #define RAMCFG_DEAR_EDEA                    RAMCFG_DEAR_EDEA_Msk                    /*!< ECC Double Error Address */
15355 
15356 /*******************  Bit definition for RAMCFG_ICR register  *****************/
15357 #define RAMCFG_ICR_CSEDC_Pos                (0U)
15358 #define RAMCFG_ICR_CSEDC_Msk                (0x1UL << RAMCFG_ICR_CSEDC_Pos)         /*!< 0x00000001 */
15359 #define RAMCFG_ICR_CSEDC                    RAMCFG_ICR_CSEDC_Msk                    /*!< Clear ECC Single Error Detected and Corrected Flag */
15360 #define RAMCFG_ICR_CDED_Pos                 (1U)
15361 #define RAMCFG_ICR_CDED_Msk                 (0x1UL << RAMCFG_ICR_CDED_Pos)          /*!< 0x00000002 */
15362 #define RAMCFG_ICR_CDED                     RAMCFG_ICR_CDED_Msk                     /*!< Clear ECC Double Error Detected Flag*/
15363 
15364 /******************  Bit definition for RAMCFG_WPR1 register  *****************/
15365 #define RAMCFG_WPR1_P0WP_Pos                (0U)
15366 #define RAMCFG_WPR1_P0WP_Msk                (0x1UL << RAMCFG_WPR1_P0WP_Pos)         /*!< 0x00000001 */
15367 #define RAMCFG_WPR1_P0WP                    RAMCFG_WPR1_P0WP_Msk                    /*!< Write Protection Page 00 */
15368 #define RAMCFG_WPR1_P1WP_Pos                (1U)
15369 #define RAMCFG_WPR1_P1WP_Msk                (0x1UL << RAMCFG_WPR1_P1WP_Pos)         /*!< 0x00000002 */
15370 #define RAMCFG_WPR1_P1WP                    RAMCFG_WPR1_P1WP_Msk                    /*!< Write Protection Page 01 */
15371 #define RAMCFG_WPR1_P2WP_Pos                (2U)
15372 #define RAMCFG_WPR1_P2WP_Msk                (0x1UL << RAMCFG_WPR1_P2WP_Pos)         /*!< 0x00000004 */
15373 #define RAMCFG_WPR1_P2WP                    RAMCFG_WPR1_P2WP_Msk                    /*!< Write Protection Page 02 */
15374 #define RAMCFG_WPR1_P3WP_Pos                (3U)
15375 #define RAMCFG_WPR1_P3WP_Msk                (0x1UL << RAMCFG_WPR1_P3WP_Pos)         /*!< 0x00000008 */
15376 #define RAMCFG_WPR1_P3WP                    RAMCFG_WPR1_P3WP_Msk                    /*!< Write Protection Page 03 */
15377 #define RAMCFG_WPR1_P4WP_Pos                (4U)
15378 #define RAMCFG_WPR1_P4WP_Msk                (0x1UL << RAMCFG_WPR1_P4WP_Pos)         /*!< 0x00000010 */
15379 #define RAMCFG_WPR1_P4WP                    RAMCFG_WPR1_P4WP_Msk                    /*!< Write Protection Page 04 */
15380 #define RAMCFG_WPR1_P5WP_Pos                (5U)
15381 #define RAMCFG_WPR1_P5WP_Msk                (0x1UL << RAMCFG_WPR1_P5WP_Pos)         /*!< 0x00000020 */
15382 #define RAMCFG_WPR1_P5WP                    RAMCFG_WPR1_P5WP_Msk                    /*!< Write Protection Page 05 */
15383 #define RAMCFG_WPR1_P6WP_Pos                (6U)
15384 #define RAMCFG_WPR1_P6WP_Msk                (0x1UL << RAMCFG_WPR1_P6WP_Pos)         /*!< 0x00000040 */
15385 #define RAMCFG_WPR1_P6WP                    RAMCFG_WPR1_P6WP_Msk                    /*!< Write Protection Page 06 */
15386 #define RAMCFG_WPR1_P7WP_Pos                (7U)
15387 #define RAMCFG_WPR1_P7WP_Msk                (0x1UL << RAMCFG_WPR1_P7WP_Pos)         /*!< 0x00000080 */
15388 #define RAMCFG_WPR1_P7WP                    RAMCFG_WPR1_P7WP_Msk                    /*!< Write Protection Page 07 */
15389 #define RAMCFG_WPR1_P8WP_Pos                (8U)
15390 #define RAMCFG_WPR1_P8WP_Msk                (0x1UL << RAMCFG_WPR1_P8WP_Pos)         /*!< 0x00000100 */
15391 #define RAMCFG_WPR1_P8WP                    RAMCFG_WPR1_P8WP_Msk                    /*!< Write Protection Page 08 */
15392 #define RAMCFG_WPR1_P9WP_Pos                (9U)
15393 #define RAMCFG_WPR1_P9WP_Msk                (0x1UL << RAMCFG_WPR1_P9WP_Pos)         /*!< 0x00000200 */
15394 #define RAMCFG_WPR1_P9WP                    RAMCFG_WPR1_P9WP_Msk                    /*!< Write Protection Page 09 */
15395 #define RAMCFG_WPR1_P10WP_Pos               (10U)
15396 #define RAMCFG_WPR1_P10WP_Msk               (0x1UL << RAMCFG_WPR1_P10WP_Pos)        /*!< 0x00000400 */
15397 #define RAMCFG_WPR1_P10WP                   RAMCFG_WPR1_P10WP_Msk                   /*!< Write Protection Page 10 */
15398 #define RAMCFG_WPR1_P11WP_Pos               (11U)
15399 #define RAMCFG_WPR1_P11WP_Msk               (0x1UL << RAMCFG_WPR1_P11WP_Pos)        /*!< 0x00000800 */
15400 #define RAMCFG_WPR1_P11WP                   RAMCFG_WPR1_P11WP_Msk                   /*!< Write Protection Page 11 */
15401 #define RAMCFG_WPR1_P12WP_Pos               (12U)
15402 #define RAMCFG_WPR1_P12WP_Msk               (0x1UL << RAMCFG_WPR1_P12WP_Pos)        /*!< 0x00001000 */
15403 #define RAMCFG_WPR1_P12WP                   RAMCFG_WPR1_P12WP_Msk                   /*!< Write Protection Page 12 */
15404 #define RAMCFG_WPR1_P13WP_Pos               (13U)
15405 #define RAMCFG_WPR1_P13WP_Msk               (0x1UL << RAMCFG_WPR1_P13WP_Pos)        /*!< 0x00002000 */
15406 #define RAMCFG_WPR1_P13WP                   RAMCFG_WPR1_P13WP_Msk                   /*!< Write Protection Page 13 */
15407 #define RAMCFG_WPR1_P14WP_Pos               (14U)
15408 #define RAMCFG_WPR1_P14WP_Msk               (0x1UL << RAMCFG_WPR1_P14WP_Pos)        /*!< 0x00004000 */
15409 #define RAMCFG_WPR1_P14WP                   RAMCFG_WPR1_P14WP_Msk                   /*!< Write Protection Page 14 */
15410 #define RAMCFG_WPR1_P15WP_Pos               (15U)
15411 #define RAMCFG_WPR1_P15WP_Msk               (0x1UL << RAMCFG_WPR1_P15WP_Pos)        /*!< 0x00008000 */
15412 #define RAMCFG_WPR1_P15WP                   RAMCFG_WPR1_P15WP_Msk                   /*!< Write Protection Page 15 */
15413 #define RAMCFG_WPR1_P16WP_Pos               (16U)
15414 #define RAMCFG_WPR1_P16WP_Msk               (0x1UL << RAMCFG_WPR1_P16WP_Pos)        /*!< 0x00010000 */
15415 #define RAMCFG_WPR1_P16WP                   RAMCFG_WPR1_P16WP_Msk                   /*!< Write Protection Page 16 */
15416 #define RAMCFG_WPR1_P17WP_Pos               (17U)
15417 #define RAMCFG_WPR1_P17WP_Msk               (0x1UL << RAMCFG_WPR1_P17WP_Pos)        /*!< 0x00020000 */
15418 #define RAMCFG_WPR1_P17WP                   RAMCFG_WPR1_P17WP_Msk                   /*!< Write Protection Page 17 */
15419 #define RAMCFG_WPR1_P18WP_Pos               (18U)
15420 #define RAMCFG_WPR1_P18WP_Msk               (0x1UL << RAMCFG_WPR1_P18WP_Pos)        /*!< 0x00040000 */
15421 #define RAMCFG_WPR1_P18WP                   RAMCFG_WPR1_P18WP_Msk                   /*!< Write Protection Page 18 */
15422 #define RAMCFG_WPR1_P19WP_Pos               (19U)
15423 #define RAMCFG_WPR1_P19WP_Msk               (0x1UL << RAMCFG_WPR1_P19WP_Pos)        /*!< 0x00080000 */
15424 #define RAMCFG_WPR1_P19WP                   RAMCFG_WPR1_P19WP_Msk                   /*!< Write Protection Page 19 */
15425 #define RAMCFG_WPR1_P20WP_Pos               (20U)
15426 #define RAMCFG_WPR1_P20WP_Msk               (0x1UL << RAMCFG_WPR1_P20WP_Pos)        /*!< 0x00100000 */
15427 #define RAMCFG_WPR1_P20WP                   RAMCFG_WPR1_P20WP_Msk                   /*!< Write Protection Page 20 */
15428 #define RAMCFG_WPR1_P21WP_Pos               (21U)
15429 #define RAMCFG_WPR1_P21WP_Msk               (0x1UL << RAMCFG_WPR1_P21WP_Pos)        /*!< 0x00200000 */
15430 #define RAMCFG_WPR1_P21WP                   RAMCFG_WPR1_P21WP_Msk                   /*!< Write Protection Page 21 */
15431 #define RAMCFG_WPR1_P22WP_Pos               (22U)
15432 #define RAMCFG_WPR1_P22WP_Msk               (0x1UL << RAMCFG_WPR1_P22WP_Pos)        /*!< 0x00400000 */
15433 #define RAMCFG_WPR1_P22WP                   RAMCFG_WPR1_P22WP_Msk                   /*!< Write Protection Page 22 */
15434 #define RAMCFG_WPR1_P23WP_Pos               (23U)
15435 #define RAMCFG_WPR1_P23WP_Msk               (0x1UL << RAMCFG_WPR1_P23WP_Pos)        /*!< 0x00800000 */
15436 #define RAMCFG_WPR1_P23WP                   RAMCFG_WPR1_P23WP_Msk                   /*!< Write Protection Page 23 */
15437 #define RAMCFG_WPR1_P24WP_Pos               (24U)
15438 #define RAMCFG_WPR1_P24WP_Msk               (0x1UL << RAMCFG_WPR1_P24WP_Pos)        /*!< 0x01000000 */
15439 #define RAMCFG_WPR1_P24WP                   RAMCFG_WPR1_P24WP_Msk                   /*!< Write Protection Page 24 */
15440 #define RAMCFG_WPR1_P25WP_Pos               (25U)
15441 #define RAMCFG_WPR1_P25WP_Msk               (0x1UL << RAMCFG_WPR1_P25WP_Pos)        /*!< 0x02000000 */
15442 #define RAMCFG_WPR1_P25WP                   RAMCFG_WPR1_P25WP_Msk                   /*!< Write Protection Page 25 */
15443 #define RAMCFG_WPR1_P26WP_Pos               (26U)
15444 #define RAMCFG_WPR1_P26WP_Msk               (0x1UL << RAMCFG_WPR1_P26WP_Pos)        /*!< 0x04000000 */
15445 #define RAMCFG_WPR1_P26WP                   RAMCFG_WPR1_P26WP_Msk                   /*!< Write Protection Page 26 */
15446 #define RAMCFG_WPR1_P27WP_Pos               (27U)
15447 #define RAMCFG_WPR1_P27WP_Msk               (0x1UL << RAMCFG_WPR1_P27WP_Pos)        /*!< 0x08000000 */
15448 #define RAMCFG_WPR1_P27WP                   RAMCFG_WPR1_P27WP_Msk                   /*!< Write Protection Page 27 */
15449 #define RAMCFG_WPR1_P28WP_Pos               (28U)
15450 #define RAMCFG_WPR1_P28WP_Msk               (0x1UL << RAMCFG_WPR1_P28WP_Pos)        /*!< 0x10000000 */
15451 #define RAMCFG_WPR1_P28WP                   RAMCFG_WPR1_P28WP_Msk                   /*!< Write Protection Page 28 */
15452 #define RAMCFG_WPR1_P29WP_Pos               (29U)
15453 #define RAMCFG_WPR1_P29WP_Msk               (0x1UL << RAMCFG_WPR1_P29WP_Pos)        /*!< 0x20000000 */
15454 #define RAMCFG_WPR1_P29WP                   RAMCFG_WPR1_P29WP_Msk                   /*!< Write Protection Page 29 */
15455 #define RAMCFG_WPR1_P30WP_Pos               (30U)
15456 #define RAMCFG_WPR1_P30WP_Msk               (0x1UL << RAMCFG_WPR1_P30WP_Pos)        /*!< 0x40000000 */
15457 #define RAMCFG_WPR1_P30WP                   RAMCFG_WPR1_P30WP_Msk                   /*!< Write Protection Page 30 */
15458 #define RAMCFG_WPR1_P31WP_Pos               (31U)
15459 #define RAMCFG_WPR1_P31WP_Msk               (0x1UL << RAMCFG_WPR1_P31WP_Pos)        /*!< 0x80000000 */
15460 #define RAMCFG_WPR1_P31WP                   RAMCFG_WPR1_P31WP_Msk                   /*!< Write Protection Page 31 */
15461 
15462 /******************  Bit definition for RAMCFG_WPR2 register  ****************/
15463 #define RAMCFG_WPR2_P32WP_Pos               (0U)
15464 #define RAMCFG_WPR2_P32WP_Msk               (0x1UL << RAMCFG_WPR2_P32WP_Pos)        /*!< 0x00000001 */
15465 #define RAMCFG_WPR2_P32WP                   RAMCFG_WPR2_P32WP_Msk                   /*!< Write Protection Page 32 */
15466 #define RAMCFG_WPR2_P33WP_Pos               (1U)
15467 #define RAMCFG_WPR2_P33WP_Msk               (0x1UL << RAMCFG_WPR2_P33WP_Pos)        /*!< 0x00000002 */
15468 #define RAMCFG_WPR2_P33WP                   RAMCFG_WPR2_P33WP_Msk                   /*!< Write Protection Page 33 */
15469 #define RAMCFG_WPR2_P34WP_Pos               (2U)
15470 #define RAMCFG_WPR2_P34WP_Msk               (0x1UL << RAMCFG_WPR2_P34WP_Pos)        /*!< 0x00000004 */
15471 #define RAMCFG_WPR2_P34WP                   RAMCFG_WPR2_P34WP_Msk                   /*!< Write Protection Page 34 */
15472 #define RAMCFG_WPR2_P35WP_Pos               (3U)
15473 #define RAMCFG_WPR2_P35WP_Msk               (0x1UL << RAMCFG_WPR2_P35WP_Pos)        /*!< 0x00000008 */
15474 #define RAMCFG_WPR2_P35WP                   RAMCFG_WPR2_P35WP_Msk                   /*!< Write Protection Page 35 */
15475 #define RAMCFG_WPR2_P36WP_Pos               (4U)
15476 #define RAMCFG_WPR2_P36WP_Msk               (0x1UL << RAMCFG_WPR2_P36WP_Pos)        /*!< 0x00000010 */
15477 #define RAMCFG_WPR2_P36WP                   RAMCFG_WPR2_P36WP_Msk                   /*!< Write Protection Page 36 */
15478 #define RAMCFG_WPR2_P37WP_Pos               (5U)
15479 #define RAMCFG_WPR2_P37WP_Msk               (0x1UL << RAMCFG_WPR2_P37WP_Pos)        /*!< 0x00000020 */
15480 #define RAMCFG_WPR2_P37WP                   RAMCFG_WPR2_P37WP_Msk                   /*!< Write Protection Page 37 */
15481 #define RAMCFG_WPR2_P38WP_Pos               (6U)
15482 #define RAMCFG_WPR2_P38WP_Msk               (0x1UL << RAMCFG_WPR2_P38WP_Pos)        /*!< 0x00000040 */
15483 #define RAMCFG_WPR2_P38WP                   RAMCFG_WPR2_P38WP_Msk                   /*!< Write Protection Page 38 */
15484 #define RAMCFG_WPR2_P39WP_Pos               (7U)
15485 #define RAMCFG_WPR2_P39WP_Msk               (0x1UL << RAMCFG_WPR2_P39WP_Pos)        /*!< 0x00000080 */
15486 #define RAMCFG_WPR2_P39WP                   RAMCFG_WPR2_P39WP_Msk                   /*!< Write Protection Page 39 */
15487 #define RAMCFG_WPR2_P40WP_Pos               (8U)
15488 #define RAMCFG_WPR2_P40WP_Msk               (0x1UL << RAMCFG_WPR2_P40WP_Pos)        /*!< 0x00000100 */
15489 #define RAMCFG_WPR2_P40WP                   RAMCFG_WPR2_P40WP_Msk                   /*!< Write Protection Page 40 */
15490 #define RAMCFG_WPR2_P41WP_Pos               (9U)
15491 #define RAMCFG_WPR2_P41WP_Msk               (0x1UL << RAMCFG_WPR2_P41WP_Pos)        /*!< 0x00000200 */
15492 #define RAMCFG_WPR2_P41WP                   RAMCFG_WPR2_P41WP_Msk                   /*!< Write Protection Page 41 */
15493 #define RAMCFG_WPR2_P42WP_Pos               (10U)
15494 #define RAMCFG_WPR2_P42WP_Msk               (0x1UL << RAMCFG_WPR2_P42WP_Pos)        /*!< 0x00000400 */
15495 #define RAMCFG_WPR2_P42WP                   RAMCFG_WPR2_P42WP_Msk                   /*!< Write Protection Page 42 */
15496 #define RAMCFG_WPR2_P43WP_Pos               (11U)
15497 #define RAMCFG_WPR2_P43WP_Msk               (0x1UL << RAMCFG_WPR2_P43WP_Pos)        /*!< 0x00000800 */
15498 #define RAMCFG_WPR2_P43WP                   RAMCFG_WPR2_P43WP_Msk                   /*!< Write Protection Page 43 */
15499 #define RAMCFG_WPR2_P44WP_Pos               (12U)
15500 #define RAMCFG_WPR2_P44WP_Msk               (0x1UL << RAMCFG_WPR2_P44WP_Pos)        /*!< 0x00001000 */
15501 #define RAMCFG_WPR2_P44WP                   RAMCFG_WPR2_P44WP_Msk                   /*!< Write Protection Page 44 */
15502 #define RAMCFG_WPR2_P45WP_Pos               (13U)
15503 #define RAMCFG_WPR2_P45WP_Msk               (0x1UL << RAMCFG_WPR2_P45WP_Pos)        /*!< 0x00002000 */
15504 #define RAMCFG_WPR2_P45WP                   RAMCFG_WPR2_P45WP_Msk                   /*!< Write Protection Page 45 */
15505 #define RAMCFG_WPR2_P46WP_Pos               (14U)
15506 #define RAMCFG_WPR2_P46WP_Msk               (0x1UL << RAMCFG_WPR2_P46WP_Pos)        /*!< 0x00004000 */
15507 #define RAMCFG_WPR2_P46WP                   RAMCFG_WPR2_P46WP_Msk                   /*!< Write Protection Page 46 */
15508 #define RAMCFG_WPR2_P47WP_Pos               (15U)
15509 #define RAMCFG_WPR2_P47WP_Msk               (0x1UL << RAMCFG_WPR2_P47WP_Pos)        /*!< 0x00008000 */
15510 #define RAMCFG_WPR2_P47WP                   RAMCFG_WPR2_P47WP_Msk                   /*!< Write Protection Page 47 */
15511 #define RAMCFG_WPR2_P48WP_Pos               (16U)
15512 #define RAMCFG_WPR2_P48WP_Msk               (0x1UL << RAMCFG_WPR2_P48WP_Pos)        /*!< 0x00010000 */
15513 #define RAMCFG_WPR2_P48WP                   RAMCFG_WPR2_P48WP_Msk                   /*!< Write Protection Page 48 */
15514 #define RAMCFG_WPR2_P49WP_Pos               (17U)
15515 #define RAMCFG_WPR2_P49WP_Msk               (0x1UL << RAMCFG_WPR2_P49WP_Pos)        /*!< 0x00020000 */
15516 #define RAMCFG_WPR2_P49WP                   RAMCFG_WPR2_P49WP_Msk                   /*!< Write Protection Page 49 */
15517 #define RAMCFG_WPR2_P50WP_Pos               (18U)
15518 #define RAMCFG_WPR2_P50WP_Msk               (0x1UL << RAMCFG_WPR2_P50WP_Pos)        /*!< 0x00040000 */
15519 #define RAMCFG_WPR2_P50WP                   RAMCFG_WPR2_P50WP_Msk                   /*!< Write Protection Page 50 */
15520 #define RAMCFG_WPR2_P51WP_Pos               (19U)
15521 #define RAMCFG_WPR2_P51WP_Msk               (0x1UL << RAMCFG_WPR2_P51WP_Pos)        /*!< 0x00080000 */
15522 #define RAMCFG_WPR2_P51WP                   RAMCFG_WPR2_P51WP_Msk                   /*!< Write Protection Page 51 */
15523 #define RAMCFG_WPR2_P52WP_Pos               (20U)
15524 #define RAMCFG_WPR2_P52WP_Msk               (0x1UL << RAMCFG_WPR2_P52WP_Pos)        /*!< 0x00100000 */
15525 #define RAMCFG_WPR2_P52WP                   RAMCFG_WPR2_P52WP_Msk                   /*!< Write Protection Page 52 */
15526 #define RAMCFG_WPR2_P53WP_Pos               (21U)
15527 #define RAMCFG_WPR2_P53WP_Msk               (0x1UL << RAMCFG_WPR2_P53WP_Pos)        /*!< 0x00200000 */
15528 #define RAMCFG_WPR2_P53WP                   RAMCFG_WPR2_P53WP_Msk                   /*!< Write Protection Page 53 */
15529 #define RAMCFG_WPR2_P54WP_Pos               (22U)
15530 #define RAMCFG_WPR2_P54WP_Msk               (0x1UL << RAMCFG_WPR2_P54WP_Pos)        /*!< 0x00400000 */
15531 #define RAMCFG_WPR2_P54WP                   RAMCFG_WPR2_P54WP_Msk                   /*!< Write Protection Page 54 */
15532 #define RAMCFG_WPR2_P55WP_Pos               (23U)
15533 #define RAMCFG_WPR2_P55WP_Msk               (0x1UL << RAMCFG_WPR2_P55WP_Pos)        /*!< 0x00800000 */
15534 #define RAMCFG_WPR2_P55WP                   RAMCFG_WPR2_P55WP_Msk                   /*!< Write Protection Page 55 */
15535 #define RAMCFG_WPR2_P56WP_Pos               (25U)
15536 #define RAMCFG_WPR2_P56WP_Msk               (0x1UL << RAMCFG_WPR2_P56WP_Pos)        /*!< 0x01000000 */
15537 #define RAMCFG_WPR2_P56WP                   RAMCFG_WPR2_P56WP_Msk                   /*!< Write Protection Page 56 */
15538 #define RAMCFG_WPR2_P57WP_Pos               (26U)
15539 #define RAMCFG_WPR2_P57WP_Msk               (0x1UL << RAMCFG_WPR2_P57WP_Pos)        /*!< 0x02000000 */
15540 #define RAMCFG_WPR2_P57WP                   RAMCFG_WPR2_P57WP_Msk                   /*!< Write Protection Page 57 */
15541 #define RAMCFG_WPR2_P58WP_Pos               (27U)
15542 #define RAMCFG_WPR2_P58WP_Msk               (0x1UL << RAMCFG_WPR2_P58WP_Pos)        /*!< 0x04000000 */
15543 #define RAMCFG_WPR2_P58WP                   RAMCFG_WPR2_P58WP_Msk                   /*!< Write Protection Page 58 */
15544 #define RAMCFG_WPR2_P59WP_Pos               (28U)
15545 #define RAMCFG_WPR2_P59WP_Msk               (0x1UL << RAMCFG_WPR2_P59WP_Pos)        /*!< 0x08000000 */
15546 #define RAMCFG_WPR2_P59WP                   RAMCFG_WPR2_P59WP_Msk                   /*!< Write Protection Page 59 */
15547 #define RAMCFG_WPR2_P60WP_Pos               (29U)
15548 #define RAMCFG_WPR2_P60WP_Msk               (0x1UL << RAMCFG_WPR2_P60WP_Pos)        /*!< 0x10000000 */
15549 #define RAMCFG_WPR2_P60WP                   RAMCFG_WPR2_P60WP_Msk                   /*!< Write Protection Page 60 */
15550 #define RAMCFG_WPR2_P61WP_Pos               (30U)
15551 #define RAMCFG_WPR2_P61WP_Msk               (0x1UL << RAMCFG_WPR2_P61WP_Pos)        /*!< 0x20000000 */
15552 #define RAMCFG_WPR2_P61WP                   RAMCFG_WPR2_P61WP_Msk                   /*!< Write Protection Page 61 */
15553 #define RAMCFG_WPR2_P62WP_Pos               (31U)
15554 #define RAMCFG_WPR2_P62WP_Msk               (0x1UL << RAMCFG_WPR2_P62WP_Pos)        /*!< 0x40000000 */
15555 #define RAMCFG_WPR2_P62WP                   RAMCFG_WPR2_P62WP_Msk                   /*!< Write Protection Page 62 */
15556 #define RAMCFG_WPR2_P63WP_Pos               (31U)
15557 #define RAMCFG_WPR2_P63WP_Msk               (0x1UL << RAMCFG_WPR2_P63WP_Pos)        /*!< 0x80000000 */
15558 #define RAMCFG_WPR2_P63WP                   RAMCFG_WPR2_P63WP_Msk                   /*!< Write Protection Page 63 */
15559 
15560 /*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
15561 #define RAMCFG_ECCKEYR_ECCKEY_Pos           (0U)
15562 #define RAMCFG_ECCKEYR_ECCKEY_Msk           (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)   /*!< 0x000000FF */
15563 #define RAMCFG_ECCKEYR_ECCKEY               RAMCFG_ECCKEYR_ECCKEY_Msk               /*!< ECC Write Protection Key */
15564 
15565 /*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
15566 #define RAMCFG_ERKEYR_ERASEKEY_Pos          (0U)
15567 #define RAMCFG_ERKEYR_ERASEKEY_Msk          (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)  /*!< 0x000000FF */
15568 #define RAMCFG_ERKEYR_ERASEKEY              RAMCFG_ERKEYR_ERASEKEY_Msk              /*!< Erase Write Protection Key */
15569 
15570 
15571 /******************************************************************************/
15572 /*                                                                            */
15573 /*                         Reset and Clock Control                            */
15574 /*                                                                            */
15575 /******************************************************************************/
15576 /********************  Bit definition for RCC_CR register  ********************/
15577 #define RCC_CR_HSION_Pos                    (0U)
15578 #define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000001 */
15579 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                        /*!< Internal High Speed oscillator (HSI) clock enable */
15580 #define RCC_CR_HSIRDY_Pos                   (1U)
15581 #define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00000002 */
15582 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed oscillator (HSI) clock ready flag */
15583 #define RCC_CR_HSIKERON_Pos                 (2U)
15584 #define RCC_CR_HSIKERON_Msk                 (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00000004 */
15585 #define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed oscillator (HSI) clock enable for some IPs Kernel */
15586 #define RCC_CR_HSIDIV_Pos                   (3U)
15587 #define RCC_CR_HSIDIV_Msk                   (0x3UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000018 */
15588 #define RCC_CR_HSIDIV                       RCC_CR_HSIDIV_Msk                       /*!< Internal High Speed clock divider selection */
15589 #define RCC_CR_HSIDIV_0                     (0x1UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000008 */
15590 #define RCC_CR_HSIDIV_1                     (0x2UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000010 */
15591 #define RCC_CR_HSIDIVF_Pos                  (5U)
15592 #define RCC_CR_HSIDIVF_Msk                  (0x1UL << RCC_CR_HSIDIVF_Pos)           /*!< 0x00000020 */
15593 #define RCC_CR_HSIDIVF                      RCC_CR_HSIDIVF_Msk                      /*!< HSI Divider flag */
15594 #define RCC_CR_CSION_Pos                    (8U)
15595 #define RCC_CR_CSION_Msk                    (0x1UL << RCC_CR_CSION_Pos)             /*!< 0x00000100 */
15596 #define RCC_CR_CSION                        RCC_CR_CSION_Msk                        /*!< The Internal RC 4MHz oscillator (CSI) clock enable */
15597 #define RCC_CR_CSIRDY_Pos                   (9U)
15598 #define RCC_CR_CSIRDY_Msk                   (0x1UL << RCC_CR_CSIRDY_Pos)            /*!< 0x00000200 */
15599 #define RCC_CR_CSIRDY                       RCC_CR_CSIRDY_Msk                       /*!< The Internal RC 4MHz oscillator (CSI) clock ready */
15600 #define RCC_CR_CSIKERON_Pos                 (10U)
15601 #define RCC_CR_CSIKERON_Msk                 (0x1UL << RCC_CR_CSIKERON_Pos)          /*!< 0x00000400 */
15602 #define RCC_CR_CSIKERON                     RCC_CR_CSIKERON_Msk                     /*!< The Internal RC 4MHz oscillator (CSI) clock enable for some IPs Kernel */
15603 #define RCC_CR_HSI48ON_Pos                  (12U)
15604 #define RCC_CR_HSI48ON_Msk                  (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x00001000 */
15605 #define RCC_CR_HSI48ON                      RCC_CR_HSI48ON_Msk                      /*!< HSI48 clock enable */
15606 #define RCC_CR_HSI48RDY_Pos                 (13U)
15607 #define RCC_CR_HSI48RDY_Msk                 (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x00002000 */
15608 #define RCC_CR_HSI48RDY                     RCC_CR_HSI48RDY_Msk                     /*!< HSI48 clock ready */
15609 #define RCC_CR_HSEON_Pos                    (16U)
15610 #define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
15611 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                        /*!< External High Speed oscillator (HSE) clock enable */
15612 #define RCC_CR_HSERDY_Pos                   (17U)
15613 #define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
15614 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                       /*!< External High Speed oscillator (HSE) clock ready */
15615 #define RCC_CR_HSEBYP_Pos                   (18U)
15616 #define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
15617 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                       /*!< External High Speed oscillator (HSE) clock bypass */
15618 #define RCC_CR_HSECSSON_Pos                 (19U)
15619 #define RCC_CR_HSECSSON_Msk                 (0x1UL << RCC_CR_HSECSSON_Pos)          /*!< 0x00080000 */
15620 #define RCC_CR_HSECSSON                     RCC_CR_HSECSSON_Msk                     /*!< HSE Clock Security System enable */
15621 #define RCC_CR_HSEEXT_Pos                   (20U)
15622 #define RCC_CR_HSEEXT_Msk                   (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
15623 #define RCC_CR_HSEEXT                       RCC_CR_HSEEXT_Msk                       /*!< External High Speed clock type in Bypass mode */
15624 #define RCC_CR_PLL1ON_Pos                   (24U)
15625 #define RCC_CR_PLL1ON_Msk                   (0x1UL << RCC_CR_PLL1ON_Pos)            /*!< 0x01000000 */
15626 #define RCC_CR_PLL1ON                       RCC_CR_PLL1ON_Msk                       /*!< System PLL clock enable */
15627 #define RCC_CR_PLL1RDY_Pos                  (25U)
15628 #define RCC_CR_PLL1RDY_Msk                  (0x1UL << RCC_CR_PLL1RDY_Pos)           /*!< 0x02000000 */
15629 #define RCC_CR_PLL1RDY                      RCC_CR_PLL1RDY_Msk                      /*!< System PLL clock ready */
15630 #define RCC_CR_PLL2ON_Pos                   (26U)
15631 #define RCC_CR_PLL2ON_Msk                   (0x1UL << RCC_CR_PLL2ON_Pos)            /*!< 0x04000000 */
15632 #define RCC_CR_PLL2ON                       RCC_CR_PLL2ON_Msk                       /*!< PLL2 enable */
15633 #define RCC_CR_PLL2RDY_Pos                  (27U)
15634 #define RCC_CR_PLL2RDY_Msk                  (0x1UL << RCC_CR_PLL2RDY_Pos)           /*!< 0x08000000 */
15635 #define RCC_CR_PLL2RDY                      RCC_CR_PLL2RDY_Msk                      /*!< PLL2 ready */
15636 #define RCC_CR_PLL3ON_Pos                   (28U)
15637 #define RCC_CR_PLL3ON_Msk                   (0x1UL << RCC_CR_PLL3ON_Pos)            /*!< 0x10000000 */
15638 #define RCC_CR_PLL3ON                       RCC_CR_PLL3ON_Msk                       /*!< PLL3 enable */
15639 #define RCC_CR_PLL3RDY_Pos                  (29U)
15640 #define RCC_CR_PLL3RDY_Msk                  (0x1UL << RCC_CR_PLL3RDY_Pos)           /*!< 0x20000000 */
15641 #define RCC_CR_PLL3RDY                      RCC_CR_PLL3RDY_Msk                      /*!< PLL3 ready */
15642 
15643 /********************  Bit definition for RCC_HSICFGR register  ***************/
15644 /*!< HSICAL configuration */
15645 #define RCC_HSICFGR_HSICAL_Pos               (0U)
15646 #define RCC_HSICFGR_HSICAL_Msk               (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000FFF */
15647 #define RCC_HSICFGR_HSICAL                   RCC_HSICFGR_HSICAL_Msk                   /*!< HSICAL[11:0] bits */
15648 #define RCC_HSICFGR_HSICAL_0                 (0x01UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000001 */
15649 #define RCC_HSICFGR_HSICAL_1                 (0x02UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000002 */
15650 #define RCC_HSICFGR_HSICAL_2                 (0x04UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000004 */
15651 #define RCC_HSICFGR_HSICAL_3                 (0x08UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000008 */
15652 #define RCC_HSICFGR_HSICAL_4                 (0x10UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000010 */
15653 #define RCC_HSICFGR_HSICAL_5                 (0x20UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000020 */
15654 #define RCC_HSICFGR_HSICAL_6                 (0x40UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000040 */
15655 #define RCC_HSICFGR_HSICAL_7                 (0x80UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000080 */
15656 #define RCC_HSICFGR_HSICAL_8                 (0x100UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000100 */
15657 #define RCC_HSICFGR_HSICAL_9                 (0x200UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000200 */
15658 #define RCC_HSICFGR_HSICAL_10                (0x400UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000400 */
15659 #define RCC_HSICFGR_HSICAL_11                (0x800UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000800 */
15660 
15661 /*!< HSITRIM configuration */
15662 #define RCC_HSICFGR_HSITRIM_Pos              (16U)
15663 #define RCC_HSICFGR_HSITRIM_Msk              (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x007F0000 */
15664 #define RCC_HSICFGR_HSITRIM                  RCC_HSICFGR_HSITRIM_Msk                  /*!< HSITRIM[6:0] bits */
15665 #define RCC_HSICFGR_HSITRIM_0                (0x01UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00010000 */
15666 #define RCC_HSICFGR_HSITRIM_1                (0x02UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00020000 */
15667 #define RCC_HSICFGR_HSITRIM_2                (0x04UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00040000 */
15668 #define RCC_HSICFGR_HSITRIM_3                (0x08UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00080000 */
15669 #define RCC_HSICFGR_HSITRIM_4                (0x10UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00100000 */
15670 #define RCC_HSICFGR_HSITRIM_5                (0x20UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00200000 */
15671 #define RCC_HSICFGR_HSITRIM_6                (0x40UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00400000 */
15672 
15673 /********************  Bit definition for RCC_CRRCR register  *****************/
15674 /*!< HSI48CAL configuration */
15675 #define RCC_CRRCR_HSI48CAL_Pos              (0U)
15676 #define RCC_CRRCR_HSI48CAL_Msk              (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000003FF */
15677 #define RCC_CRRCR_HSI48CAL                  RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[8:0] bits */
15678 #define RCC_CRRCR_HSI48CAL_0                (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
15679 #define RCC_CRRCR_HSI48CAL_1                (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
15680 #define RCC_CRRCR_HSI48CAL_2                (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
15681 #define RCC_CRRCR_HSI48CAL_3                (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
15682 #define RCC_CRRCR_HSI48CAL_4                (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
15683 #define RCC_CRRCR_HSI48CAL_5                (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
15684 #define RCC_CRRCR_HSI48CAL_6                (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
15685 #define RCC_CRRCR_HSI48CAL_7                (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
15686 #define RCC_CRRCR_HSI48CAL_8                (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
15687 #define RCC_CRRCR_HSI48CAL_9                (0x200UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000200 */
15688 
15689 /********************  Bit definition for RCC_CSICFGR register  ***************/
15690 /*!< CSICAL configuration */
15691 #define RCC_CSICFGR_CSICAL_Pos               (0U)
15692 #define RCC_CSICFGR_CSICAL_Msk               (0xFFUL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x000000FF */
15693 #define RCC_CSICFGR_CSICAL                   RCC_CSICFGR_CSICAL_Msk                   /*!< CSICAL[7:0] bits */
15694 #define RCC_CSICFGR_CSICAL_0                 (0x01UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000001 */
15695 #define RCC_CSICFGR_CSICAL_1                 (0x02UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000002 */
15696 #define RCC_CSICFGR_CSICAL_2                 (0x04UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000004 */
15697 #define RCC_CSICFGR_CSICAL_3                 (0x08UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000008 */
15698 #define RCC_CSICFGR_CSICAL_4                 (0x10UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000010 */
15699 #define RCC_CSICFGR_CSICAL_5                 (0x20UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000020 */
15700 #define RCC_CSICFGR_CSICAL_6                 (0x40UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000040 */
15701 #define RCC_CSICFGR_CSICAL_7                 (0x80UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000080 */
15702 
15703 /*!< CSITRIM configuration */
15704 #define RCC_CSICFGR_CSITRIM_Pos              (16U)
15705 #define RCC_CSICFGR_CSITRIM_Msk              (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x003F0000 */
15706 #define RCC_CSICFGR_CSITRIM                  RCC_CSICFGR_CSITRIM_Msk                  /*!< CSITRIM[5:0] bits */
15707 #define RCC_CSICFGR_CSITRIM_0                (0x01UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00010000 */
15708 #define RCC_CSICFGR_CSITRIM_1                (0x02UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00020000 */
15709 #define RCC_CSICFGR_CSITRIM_2                (0x04UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00040000 */
15710 #define RCC_CSICFGR_CSITRIM_3                (0x08UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00080000 */
15711 #define RCC_CSICFGR_CSITRIM_4                (0x10UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00100000 */
15712 #define RCC_CSICFGR_CSITRIM_5                (0x20UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00200000 */
15713 
15714 /********************  Bit definition for RCC_CFGR1 register  ******************/
15715 /*!< SW configuration */
15716 #define RCC_CFGR1_SW_Pos                    (0U)
15717 #define RCC_CFGR1_SW_Msk                    (0x3UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000003 */
15718 #define RCC_CFGR1_SW                        RCC_CFGR1_SW_Msk                        /*!< SW[1:0] bits (System clock Switch) */
15719 #define RCC_CFGR1_SW_0                      (0x1UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000001 */
15720 #define RCC_CFGR1_SW_1                      (0x2UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000002 */
15721 
15722 /*!< SWS configuration */
15723 #define RCC_CFGR1_SWS_Pos                   (3U)
15724 #define RCC_CFGR1_SWS_Msk                   (0x3UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000018 */
15725 #define RCC_CFGR1_SWS                       RCC_CFGR1_SWS_Msk                       /*!< SWS[1:0] bits (System Clock Switch Status) */
15726 #define RCC_CFGR1_SWS_0                     (0x1UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000008 */
15727 #define RCC_CFGR1_SWS_1                     (0x2UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000010 */
15728 
15729 #define RCC_CFGR1_STOPWUCK_Pos              (6U)
15730 #define RCC_CFGR1_STOPWUCK_Msk              (0x1UL << RCC_CFGR1_STOPWUCK_Pos)       /*!< 0x00000040 */
15731 #define RCC_CFGR1_STOPWUCK                  RCC_CFGR1_STOPWUCK_Msk                  /*!< Wake Up from stop and HSE CSS backup clock selection */
15732 #define RCC_CFGR1_STOPKERWUCK_Pos           (7U)
15733 #define RCC_CFGR1_STOPKERWUCK_Msk           (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos)    /*!< 0x00000080 */
15734 #define RCC_CFGR1_STOPKERWUCK               RCC_CFGR1_STOPKERWUCK_Msk               /*!< Kernel Clock Selection after a Wake Up from STOP */
15735 
15736 /*!< RTCPRE configuration */
15737 #define RCC_CFGR1_RTCPRE_Pos                (8U)
15738 #define RCC_CFGR1_RTCPRE_Msk                (0x3FUL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00003F00 */
15739 #define RCC_CFGR1_RTCPRE                    RCC_CFGR1_RTCPRE_Msk                    /*!< HSE division factor for RTC Clock */
15740 #define RCC_CFGR1_RTCPRE_0                  (0x1UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000100 */
15741 #define RCC_CFGR1_RTCPRE_1                  (0x2UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000200 */
15742 #define RCC_CFGR1_RTCPRE_2                  (0x4UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000400 */
15743 #define RCC_CFGR1_RTCPRE_3                  (0x8UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000800 */
15744 #define RCC_CFGR1_RTCPRE_4                  (0x10UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00001000 */
15745 #define RCC_CFGR1_RTCPRE_5                  (0x20UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00002000 */
15746 
15747 /*!< TIMPRE configuration */
15748 #define RCC_CFGR1_TIMPRE_Pos                (15U)
15749 #define RCC_CFGR1_TIMPRE_Msk                (0x1UL << RCC_CFGR1_TIMPRE_Pos)
15750 #define RCC_CFGR1_TIMPRE                    RCC_CFGR1_TIMPRE_Msk                    /*!< 0x00008000 */
15751 
15752 /*!< MCO1 configuration */
15753 #define RCC_CFGR1_MCO1PRE_Pos               (18U)
15754 #define RCC_CFGR1_MCO1PRE_Msk               (0xFUL << RCC_CFGR1_MCO1PRE_Pos)
15755 #define RCC_CFGR1_MCO1PRE                   RCC_CFGR1_MCO1PRE_Msk                   /*!< 0x003C0000 */
15756 #define RCC_CFGR1_MCO1PRE_0                 (0x1UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00040000 */
15757 #define RCC_CFGR1_MCO1PRE_1                 (0x2UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00080000 */
15758 #define RCC_CFGR1_MCO1PRE_2                 (0x4UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00100000 */
15759 #define RCC_CFGR1_MCO1PRE_3                 (0x8UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00200000 */
15760 
15761 #define RCC_CFGR1_MCO1SEL_Pos               (22U)
15762 #define RCC_CFGR1_MCO1SEL_Msk               (0x7UL << RCC_CFGR1_MCO1SEL_Pos)
15763 #define RCC_CFGR1_MCO1SEL                   RCC_CFGR1_MCO1SEL_Msk                   /*!< 0x01C00000 */
15764 #define RCC_CFGR1_MCO1SEL_0                 (0x1UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00400000 */
15765 #define RCC_CFGR1_MCO1SEL_1                 (0x2UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00800000 */
15766 #define RCC_CFGR1_MCO1SEL_2                 (0x4UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x01000000 */
15767 
15768 /*!< MCO2 configuration */
15769 #define RCC_CFGR1_MCO2PRE_Pos               (25U)
15770 #define RCC_CFGR1_MCO2PRE_Msk               (0xFUL << RCC_CFGR1_MCO2PRE_Pos)
15771 #define RCC_CFGR1_MCO2PRE                   RCC_CFGR1_MCO2PRE_Msk                   /*!< 0x1E000000 */
15772 #define RCC_CFGR1_MCO2PRE_0                 (0x1UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x02000000 */
15773 #define RCC_CFGR1_MCO2PRE_1                 (0x2UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x04000000 */
15774 #define RCC_CFGR1_MCO2PRE_2                 (0x4UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x08000000 */
15775 #define RCC_CFGR1_MCO2PRE_3                 (0x8UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x10000000 */
15776 
15777 #define RCC_CFGR1_MCO2SEL_Pos               (29U)
15778 #define RCC_CFGR1_MCO2SEL_Msk               (0x7UL << RCC_CFGR1_MCO2SEL_Pos)
15779 #define RCC_CFGR1_MCO2SEL                   RCC_CFGR1_MCO2SEL_Msk                   /*!< 0xE0000000 */
15780 #define RCC_CFGR1_MCO2SEL_0                 (0x1UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x20000000 */
15781 #define RCC_CFGR1_MCO2SEL_1                 (0x2UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x40000000 */
15782 #define RCC_CFGR1_MCO2SEL_2                 (0x4UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x80000000 */
15783 
15784 /********************  Bit definition for RCC_CFGR2 register  ******************/
15785 /*!< HPRE configuration */
15786 #define RCC_CFGR2_HPRE_Pos                  (0U)
15787 #define RCC_CFGR2_HPRE_Msk                  (0xFUL << RCC_CFGR2_HPRE_Pos)           /*!< 0x0000000F */
15788 #define RCC_CFGR2_HPRE                      RCC_CFGR2_HPRE_Msk                      /*!< HPRE[3:0] bits (AHB prescaler) */
15789 #define RCC_CFGR2_HPRE_0                    (0x1UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000001 */
15790 #define RCC_CFGR2_HPRE_1                    (0x2UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000002 */
15791 #define RCC_CFGR2_HPRE_2                    (0x4UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000004 */
15792 #define RCC_CFGR2_HPRE_3                    (0x8UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000008 */
15793 
15794 /*!< PPRE1 configuration */
15795 #define RCC_CFGR2_PPRE1_Pos                 (4U)
15796 #define RCC_CFGR2_PPRE1_Msk                 (0x7UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000070 */
15797 #define RCC_CFGR2_PPRE1                     RCC_CFGR2_PPRE1_Msk                     /*!< PPRE1[2:0] bits (APB1 prescaler) */
15798 #define RCC_CFGR2_PPRE1_0                   (0x1UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000010 */
15799 #define RCC_CFGR2_PPRE1_1                   (0x2UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000020 */
15800 #define RCC_CFGR2_PPRE1_2                   (0x4UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000040 */
15801 
15802 /*!< PPRE2 configuration */
15803 #define RCC_CFGR2_PPRE2_Pos                 (8U)
15804 #define RCC_CFGR2_PPRE2_Msk                 (0x7UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000700 */
15805 #define RCC_CFGR2_PPRE2                     RCC_CFGR2_PPRE2_Msk                     /*!< PPRE2[2:0] bits (APB2 prescaler) */
15806 #define RCC_CFGR2_PPRE2_0                   (0x1UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000100 */
15807 #define RCC_CFGR2_PPRE2_1                   (0x2UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000200 */
15808 #define RCC_CFGR2_PPRE2_2                   (0x4UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000400 */
15809 
15810 /*!< PPRE3 configuration */
15811 #define RCC_CFGR2_PPRE3_Pos                 (12U)
15812 #define RCC_CFGR2_PPRE3_Msk                 (0x7UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00007000 */
15813 #define RCC_CFGR2_PPRE3                     RCC_CFGR2_PPRE3_Msk                     /*!< PPRE3[2:0] bits (APB3 prescaler) */
15814 #define RCC_CFGR2_PPRE3_0                   (0x1UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00001000 */
15815 #define RCC_CFGR2_PPRE3_1                   (0x2UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00002000 */
15816 #define RCC_CFGR2_PPRE3_2                   (0x4UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00004000 */
15817 
15818 #define RCC_CFGR2_AHB1DIS_Pos               (16U)
15819 #define RCC_CFGR2_AHB1DIS_Msk               (0x1UL << RCC_CFGR2_AHB1DIS_Pos)        /*!< 0x00010000 */
15820 #define RCC_CFGR2_AHB1DIS                   RCC_CFGR2_AHB1DIS_Msk                   /*!< AHB1 clock disable */
15821 #define RCC_CFGR2_AHB2DIS_Pos               (17U)
15822 #define RCC_CFGR2_AHB2DIS_Msk               (0x1UL << RCC_CFGR2_AHB2DIS_Pos)        /*!< 0x00020000 */
15823 #define RCC_CFGR2_AHB2DIS                   RCC_CFGR2_AHB2DIS_Msk                   /*!< AHB2 clock disable */
15824 #define RCC_CFGR2_AHB4DIS_Pos               (19U)
15825 #define RCC_CFGR2_AHB4DIS_Msk               (0x1UL << RCC_CFGR2_AHB4DIS_Pos)        /*!< 0x00080000 */
15826 #define RCC_CFGR2_AHB4DIS                   RCC_CFGR2_AHB4DIS_Msk                   /*!< AHB4 clock disable */
15827 #define RCC_CFGR2_APB1DIS_Pos               (20U)
15828 #define RCC_CFGR2_APB1DIS_Msk               (0x1UL << RCC_CFGR2_APB1DIS_Pos)        /*!< 0x00100000 */
15829 #define RCC_CFGR2_APB1DIS                   RCC_CFGR2_APB1DIS_Msk                   /*!< APB1 clock disable */
15830 #define RCC_CFGR2_APB2DIS_Pos               (21U)
15831 #define RCC_CFGR2_APB2DIS_Msk               (0x1UL << RCC_CFGR2_APB2DIS_Pos)        /*!< 0x00200000 */
15832 #define RCC_CFGR2_APB2DIS                   RCC_CFGR2_APB2DIS_Msk                   /*!< APB2 clock disable */
15833 #define RCC_CFGR2_APB3DIS_Pos               (22U)
15834 #define RCC_CFGR2_APB3DIS_Msk               (0x1UL << RCC_CFGR2_APB3DIS_Pos)        /*!< 0x00400000 */
15835 #define RCC_CFGR2_APB3DIS                   RCC_CFGR2_APB3DIS_Msk                   /*!< APB3 clock disable */
15836 
15837 /********************  Bit definition for RCC_PLL1CFGR register  ***************/
15838 #define RCC_PLL1CFGR_PLL1SRC_Pos            (0U)
15839 #define RCC_PLL1CFGR_PLL1SRC_Msk            (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000003 */
15840 #define RCC_PLL1CFGR_PLL1SRC                RCC_PLL1CFGR_PLL1SRC_Msk
15841 #define RCC_PLL1CFGR_PLL1SRC_0              (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000001 */
15842 #define RCC_PLL1CFGR_PLL1SRC_1              (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000002 */
15843 #define RCC_PLL1CFGR_PLL1RGE_Pos            (2U)
15844 #define RCC_PLL1CFGR_PLL1RGE_Msk            (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x0000000C */
15845 #define RCC_PLL1CFGR_PLL1RGE                RCC_PLL1CFGR_PLL1RGE_Msk
15846 #define RCC_PLL1CFGR_PLL1RGE_0              (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000004 */
15847 #define RCC_PLL1CFGR_PLL1RGE_1              (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000008 */
15848 #define RCC_PLL1CFGR_PLL1FRACEN_Pos         (4U)
15849 #define RCC_PLL1CFGR_PLL1FRACEN_Msk         (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos)  /*!< 0x00000010 */
15850 #define RCC_PLL1CFGR_PLL1FRACEN             RCC_PLL1CFGR_PLL1FRACEN_Msk
15851 #define RCC_PLL1CFGR_PLL1VCOSEL_Pos         (5U)
15852 #define RCC_PLL1CFGR_PLL1VCOSEL_Msk         (0x1UL << RCC_PLL1CFGR_PLL1VCOSEL_Pos) /*!< 0x00000020 */
15853 #define RCC_PLL1CFGR_PLL1VCOSEL             RCC_PLL1CFGR_PLL1VCOSEL_Msk
15854 #define RCC_PLL1CFGR_PLL1M_Pos              (8U)
15855 #define RCC_PLL1CFGR_PLL1M_Msk              (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00003F00 */
15856 #define RCC_PLL1CFGR_PLL1M                  RCC_PLL1CFGR_PLL1M_Msk
15857 #define RCC_PLL1CFGR_PLL1M_0                (0x01UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000100 */
15858 #define RCC_PLL1CFGR_PLL1M_1                (0x02UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000200 */
15859 #define RCC_PLL1CFGR_PLL1M_2                (0x04UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000400 */
15860 #define RCC_PLL1CFGR_PLL1M_3                (0x08UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000800 */
15861 #define RCC_PLL1CFGR_PLL1M_4                (0x10UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00001000 */
15862 #define RCC_PLL1CFGR_PLL1M_5                (0x20UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00002000 */
15863 #define RCC_PLL1CFGR_PLL1PEN_Pos            (16U)
15864 #define RCC_PLL1CFGR_PLL1PEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos)     /*!< 0x00010000 */
15865 #define RCC_PLL1CFGR_PLL1PEN                RCC_PLL1CFGR_PLL1PEN_Msk
15866 #define RCC_PLL1CFGR_PLL1QEN_Pos            (17U)
15867 #define RCC_PLL1CFGR_PLL1QEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos)     /*!< 0x00020000 */
15868 #define RCC_PLL1CFGR_PLL1QEN                RCC_PLL1CFGR_PLL1QEN_Msk
15869 #define RCC_PLL1CFGR_PLL1REN_Pos            (18U)
15870 #define RCC_PLL1CFGR_PLL1REN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos)     /*!< 0x00040000 */
15871 #define RCC_PLL1CFGR_PLL1REN                RCC_PLL1CFGR_PLL1REN_Msk
15872 
15873 /********************  Bit definition for RCC_PLL2CFGR register  ***************/
15874 #define RCC_PLL2CFGR_PLL2SRC_Pos            (0U)
15875 #define RCC_PLL2CFGR_PLL2SRC_Msk            (0x3UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000003 */
15876 #define RCC_PLL2CFGR_PLL2SRC                RCC_PLL2CFGR_PLL2SRC_Msk
15877 #define RCC_PLL2CFGR_PLL2SRC_0              (0x1UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000001 */
15878 #define RCC_PLL2CFGR_PLL2SRC_1              (0x2UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000002 */
15879 #define RCC_PLL2CFGR_PLL2RGE_Pos            (2U)
15880 #define RCC_PLL2CFGR_PLL2RGE_Msk            (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x0000000C */
15881 #define RCC_PLL2CFGR_PLL2RGE                RCC_PLL2CFGR_PLL2RGE_Msk
15882 #define RCC_PLL2CFGR_PLL2RGE_0              (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000004 */
15883 #define RCC_PLL2CFGR_PLL2RGE_1              (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000008 */
15884 #define RCC_PLL2CFGR_PLL2FRACEN_Pos         (4U)
15885 #define RCC_PLL2CFGR_PLL2FRACEN_Msk         (0x1UL << RCC_PLL2CFGR_PLL2FRACEN_Pos)  /*!< 0x00000010 */
15886 #define RCC_PLL2CFGR_PLL2FRACEN             RCC_PLL2CFGR_PLL2FRACEN_Msk
15887 #define RCC_PLL2CFGR_PLL2VCOSEL_Pos         (5U)
15888 #define RCC_PLL2CFGR_PLL2VCOSEL_Msk         (0x1UL << RCC_PLL2CFGR_PLL2VCOSEL_Pos)  /*!< 0x00000020 */
15889 #define RCC_PLL2CFGR_PLL2VCOSEL             RCC_PLL2CFGR_PLL2VCOSEL_Msk
15890 #define RCC_PLL2CFGR_PLL2M_Pos              (8U)
15891 #define RCC_PLL2CFGR_PLL2M_Msk              (0x3FUL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00003F00 */
15892 #define RCC_PLL2CFGR_PLL2M                  RCC_PLL2CFGR_PLL2M_Msk
15893 #define RCC_PLL2CFGR_PLL2M_0                (0x01UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000100 */
15894 #define RCC_PLL2CFGR_PLL2M_1                (0x02UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000200 */
15895 #define RCC_PLL2CFGR_PLL2M_2                (0x04UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000400 */
15896 #define RCC_PLL2CFGR_PLL2M_3                (0x08UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000800 */
15897 #define RCC_PLL2CFGR_PLL2M_4                (0x10UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00001000 */
15898 #define RCC_PLL2CFGR_PLL2M_5                (0x20UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00002000 */
15899 #define RCC_PLL2CFGR_PLL2PEN_Pos            (16U)
15900 #define RCC_PLL2CFGR_PLL2PEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2PEN_Pos)     /*!< 0x00010000 */
15901 #define RCC_PLL2CFGR_PLL2PEN                RCC_PLL2CFGR_PLL2PEN_Msk
15902 #define RCC_PLL2CFGR_PLL2QEN_Pos            (17U)
15903 #define RCC_PLL2CFGR_PLL2QEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2QEN_Pos)     /*!< 0x00020000 */
15904 #define RCC_PLL2CFGR_PLL2QEN                RCC_PLL2CFGR_PLL2QEN_Msk
15905 #define RCC_PLL2CFGR_PLL2REN_Pos            (18U)
15906 #define RCC_PLL2CFGR_PLL2REN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2REN_Pos)     /*!< 0x00040000 */
15907 #define RCC_PLL2CFGR_PLL2REN                RCC_PLL2CFGR_PLL2REN_Msk
15908 
15909 /********************  Bit definition for RCC_PLL3CFGR register  ***************/
15910 #define RCC_PLL3CFGR_PLL3SRC_Pos            (0U)
15911 #define RCC_PLL3CFGR_PLL3SRC_Msk            (0x3UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000003 */
15912 #define RCC_PLL3CFGR_PLL3SRC                RCC_PLL3CFGR_PLL3SRC_Msk
15913 #define RCC_PLL3CFGR_PLL3SRC_0              (0x1UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000001 */
15914 #define RCC_PLL3CFGR_PLL3SRC_1              (0x2UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000002 */
15915 #define RCC_PLL3CFGR_PLL3RGE_Pos            (2U)
15916 #define RCC_PLL3CFGR_PLL3RGE_Msk            (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x0000000C */
15917 #define RCC_PLL3CFGR_PLL3RGE                RCC_PLL3CFGR_PLL3RGE_Msk
15918 #define RCC_PLL3CFGR_PLL3RGE_0              (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x00000004 */
15919 #define RCC_PLL3CFGR_PLL3RGE_1              (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x00000008 */
15920 #define RCC_PLL3CFGR_PLL3FRACEN_Pos         (4U)
15921 #define RCC_PLL3CFGR_PLL3FRACEN_Msk         (0x1UL << RCC_PLL3CFGR_PLL3FRACEN_Pos)  /*!< 0x00000010 */
15922 #define RCC_PLL3CFGR_PLL3FRACEN             RCC_PLL3CFGR_PLL3FRACEN_Msk
15923 #define RCC_PLL3CFGR_PLL3VCOSEL_Pos         (5U)
15924 #define RCC_PLL3CFGR_PLL3VCOSEL_Msk         (0x1UL << RCC_PLL3CFGR_PLL3VCOSEL_Pos)  /*!< 0x00000020 */
15925 #define RCC_PLL3CFGR_PLL3VCOSEL             RCC_PLL3CFGR_PLL3VCOSEL_Msk
15926 #define RCC_PLL3CFGR_PLL3M_Pos              (8U)
15927 #define RCC_PLL3CFGR_PLL3M_Msk              (0x3FUL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00003F00 */
15928 #define RCC_PLL3CFGR_PLL3M                  RCC_PLL3CFGR_PLL3M_Msk
15929 #define RCC_PLL3CFGR_PLL3M_0                (0x01UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000100 */
15930 #define RCC_PLL3CFGR_PLL3M_1                (0x02UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000200 */
15931 #define RCC_PLL3CFGR_PLL3M_2                (0x04UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000400 */
15932 #define RCC_PLL3CFGR_PLL3M_3                (0x08UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000800 */
15933 #define RCC_PLL3CFGR_PLL3M_4                (0x10UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00001000 */
15934 #define RCC_PLL3CFGR_PLL3M_5                (0x20UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00002000 */
15935 #define RCC_PLL3CFGR_PLL3PEN_Pos            (16U)
15936 #define RCC_PLL3CFGR_PLL3PEN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3PEN_Pos)     /*!< 0x00010000 */
15937 #define RCC_PLL3CFGR_PLL3PEN                RCC_PLL3CFGR_PLL3PEN_Msk
15938 #define RCC_PLL3CFGR_PLL3QEN_Pos            (17U)
15939 #define RCC_PLL3CFGR_PLL3QEN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3QEN_Pos)     /*!< 0x00020000 */
15940 #define RCC_PLL3CFGR_PLL3QEN                RCC_PLL3CFGR_PLL3QEN_Msk
15941 #define RCC_PLL3CFGR_PLL3REN_Pos            (18U)
15942 #define RCC_PLL3CFGR_PLL3REN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3REN_Pos)     /*!< 0x00040000 */
15943 #define RCC_PLL3CFGR_PLL3REN                RCC_PLL3CFGR_PLL3REN_Msk
15944 
15945 /********************  Bit definition for RCC_PLL1DIVR register  ***************/
15946 #define RCC_PLL1DIVR_PLL1N_Pos              (0U)
15947 #define RCC_PLL1DIVR_PLL1N_Msk              (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x000001FF */
15948 #define RCC_PLL1DIVR_PLL1N                  RCC_PLL1DIVR_PLL1N_Msk
15949 #define RCC_PLL1DIVR_PLL1N_0                (0x001UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000001 */
15950 #define RCC_PLL1DIVR_PLL1N_1                (0x002UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000002 */
15951 #define RCC_PLL1DIVR_PLL1N_2                (0x004UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000004 */
15952 #define RCC_PLL1DIVR_PLL1N_3                (0x008UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000008 */
15953 #define RCC_PLL1DIVR_PLL1N_4                (0x010UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000010 */
15954 #define RCC_PLL1DIVR_PLL1N_5                (0x020UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000020 */
15955 #define RCC_PLL1DIVR_PLL1N_6                (0x040UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000040 */
15956 #define RCC_PLL1DIVR_PLL1N_7                (0x080UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000080 */
15957 #define RCC_PLL1DIVR_PLL1N_8                (0x100UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000100 */
15958 #define RCC_PLL1DIVR_PLL1P_Pos              (9U)
15959 #define RCC_PLL1DIVR_PLL1P_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos)      /*!< 0x0000FE00 */
15960 #define RCC_PLL1DIVR_PLL1P                  RCC_PLL1DIVR_PLL1P_Msk
15961 #define RCC_PLL1DIVR_PLL1P_0                (0x001UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000200 */
15962 #define RCC_PLL1DIVR_PLL1P_1                (0x002UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000400 */
15963 #define RCC_PLL1DIVR_PLL1P_2                (0x004UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000800 */
15964 #define RCC_PLL1DIVR_PLL1P_3                (0x008UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00001000 */
15965 #define RCC_PLL1DIVR_PLL1P_4                (0x010UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00002000 */
15966 #define RCC_PLL1DIVR_PLL1P_5                (0x020UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00004000 */
15967 #define RCC_PLL1DIVR_PLL1P_6                (0x040UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00008000 */
15968 #define RCC_PLL1DIVR_PLL1Q_Pos              (16U)
15969 #define RCC_PLL1DIVR_PLL1Q_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos)      /*!< 0x007F0000 */
15970 #define RCC_PLL1DIVR_PLL1Q                  RCC_PLL1DIVR_PLL1Q_Msk
15971 #define RCC_PLL1DIVR_PLL1Q_0                (0x001UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00010000 */
15972 #define RCC_PLL1DIVR_PLL1Q_1                (0x002UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00020000 */
15973 #define RCC_PLL1DIVR_PLL1Q_2                (0x004UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00040000 */
15974 #define RCC_PLL1DIVR_PLL1Q_3                (0x008UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00080000 */
15975 #define RCC_PLL1DIVR_PLL1Q_4                (0x010UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00100000 */
15976 #define RCC_PLL1DIVR_PLL1Q_5                (0x020UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00200020 */
15977 #define RCC_PLL1DIVR_PLL1Q_6                (0x040UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00400000 */
15978 #define RCC_PLL1DIVR_PLL1R_Pos              (24U)
15979 #define RCC_PLL1DIVR_PLL1R_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos)      /*!< 0x7F000000 */
15980 #define RCC_PLL1DIVR_PLL1R                  RCC_PLL1DIVR_PLL1R_Msk
15981 #define RCC_PLL1DIVR_PLL1R_0                (0x001UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x01000000 */
15982 #define RCC_PLL1DIVR_PLL1R_1                (0x002UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x02000000 */
15983 #define RCC_PLL1DIVR_PLL1R_2                (0x004UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x04000000 */
15984 #define RCC_PLL1DIVR_PLL1R_3                (0x008UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x08000000 */
15985 #define RCC_PLL1DIVR_PLL1R_4                (0x010UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x10000000 */
15986 #define RCC_PLL1DIVR_PLL1R_5                (0x020UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x20000000 */
15987 #define RCC_PLL1DIVR_PLL1R_6                (0x040UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x40000000 */
15988 
15989 /********************  Bit definition for RCC_PLL1FRACR register  ***************/
15990 #define RCC_PLL1FRACR_PLL1FRACN_Pos         (3U)
15991 #define RCC_PLL1FRACR_PLL1FRACN_Msk         (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */
15992 #define RCC_PLL1FRACR_PLL1FRACN             RCC_PLL1FRACR_PLL1FRACN_Msk
15993 #define RCC_PLL1FRACR_PLL1FRACN_0           (0x0001UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000008 */
15994 #define RCC_PLL1FRACR_PLL1FRACN_1           (0x0002UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000010 */
15995 #define RCC_PLL1FRACR_PLL1FRACN_2           (0x0004UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000020 */
15996 #define RCC_PLL1FRACR_PLL1FRACN_3           (0x0008UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000040 */
15997 #define RCC_PLL1FRACR_PLL1FRACN_4           (0x0010UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000080 */
15998 #define RCC_PLL1FRACR_PLL1FRACN_5           (0x0020UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000100 */
15999 #define RCC_PLL1FRACR_PLL1FRACN_6           (0x0040UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000200 */
16000 #define RCC_PLL1FRACR_PLL1FRACN_7           (0x0080UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000400 */
16001 #define RCC_PLL1FRACR_PLL1FRACN_8           (0x0100UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000800 */
16002 #define RCC_PLL1FRACR_PLL1FRACN_9           (0x0200UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00001000 */
16003 #define RCC_PLL1FRACR_PLL1FRACN_10          (0x0400UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00002000 */
16004 #define RCC_PLL1FRACR_PLL1FRACN_11          (0x0800UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00004000 */
16005 #define RCC_PLL1FRACR_PLL1FRACN_12          (0x1000UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00008000 */
16006 
16007 /********************  Bit definition for RCC_PLL2DIVR register  ***************/
16008 #define RCC_PLL2DIVR_PLL2N_Pos              (0U)
16009 #define RCC_PLL2DIVR_PLL2N_Msk              (0x1FFUL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x000001FF */
16010 #define RCC_PLL2DIVR_PLL2N                  RCC_PLL2DIVR_PLL2N_Msk
16011 #define RCC_PLL2DIVR_PLL2N_0                (0x001UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000001 */
16012 #define RCC_PLL2DIVR_PLL2N_1                (0x002UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000002 */
16013 #define RCC_PLL2DIVR_PLL2N_2                (0x004UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000004 */
16014 #define RCC_PLL2DIVR_PLL2N_3                (0x008UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000008 */
16015 #define RCC_PLL2DIVR_PLL2N_4                (0x010UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000010 */
16016 #define RCC_PLL2DIVR_PLL2N_5                (0x020UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000020 */
16017 #define RCC_PLL2DIVR_PLL2N_6                (0x040UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000040 */
16018 #define RCC_PLL2DIVR_PLL2N_7                (0x080UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000080 */
16019 #define RCC_PLL2DIVR_PLL2N_8                (0x100UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000100 */
16020 #define RCC_PLL2DIVR_PLL2P_Pos              (9U)
16021 #define RCC_PLL2DIVR_PLL2P_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2P_Pos)      /*!< 0x0000FE00 */
16022 #define RCC_PLL2DIVR_PLL2P                  RCC_PLL2DIVR_PLL2P_Msk
16023 #define RCC_PLL2DIVR_PLL2P_0                (0x001UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000200 */
16024 #define RCC_PLL2DIVR_PLL2P_1                (0x002UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000400 */
16025 #define RCC_PLL2DIVR_PLL2P_2                (0x004UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000800 */
16026 #define RCC_PLL2DIVR_PLL2P_3                (0x008UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00001000 */
16027 #define RCC_PLL2DIVR_PLL2P_4                (0x010UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00002000 */
16028 #define RCC_PLL2DIVR_PLL2P_5                (0x020UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00004000 */
16029 #define RCC_PLL2DIVR_PLL2P_6                (0x040UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00008000 */
16030 #define RCC_PLL2DIVR_PLL2Q_Pos              (16U)
16031 #define RCC_PLL2DIVR_PLL2Q_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2Q_Pos)      /*!< 0x007F0000 */
16032 #define RCC_PLL2DIVR_PLL2Q                  RCC_PLL2DIVR_PLL2Q_Msk
16033 #define RCC_PLL2DIVR_PLL2Q_0                (0x001UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00010000 */
16034 #define RCC_PLL2DIVR_PLL2Q_1                (0x002UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00020000 */
16035 #define RCC_PLL2DIVR_PLL2Q_2                (0x004UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00040000 */
16036 #define RCC_PLL2DIVR_PLL2Q_3                (0x008UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00080000 */
16037 #define RCC_PLL2DIVR_PLL2Q_4                (0x010UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00100000 */
16038 #define RCC_PLL2DIVR_PLL2Q_5                (0x020UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00200020 */
16039 #define RCC_PLL2DIVR_PLL2Q_6                (0x040UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00400000 */
16040 #define RCC_PLL2DIVR_PLL2R_Pos              (24U)
16041 #define RCC_PLL2DIVR_PLL2R_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2R_Pos)      /*!< 0x7F000000 */
16042 #define RCC_PLL2DIVR_PLL2R                  RCC_PLL2DIVR_PLL2R_Msk
16043 #define RCC_PLL2DIVR_PLL2R_0                (0x001UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x01000000 */
16044 #define RCC_PLL2DIVR_PLL2R_1                (0x002UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x02000000 */
16045 #define RCC_PLL2DIVR_PLL2R_2                (0x004UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x04000000 */
16046 #define RCC_PLL2DIVR_PLL2R_3                (0x008UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x08000000 */
16047 #define RCC_PLL2DIVR_PLL2R_4                (0x010UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x10000000 */
16048 #define RCC_PLL2DIVR_PLL2R_5                (0x020UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x20000000 */
16049 #define RCC_PLL2DIVR_PLL2R_6                (0x040UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x40000000 */
16050 
16051 /********************  Bit definition for RCC_PLL2FRACR register  ***************/
16052 #define RCC_PLL2FRACR_PLL2FRACN_Pos         (3U)
16053 #define RCC_PLL2FRACR_PLL2FRACN_Msk         (0x1FFFUL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x0000FFF8 */
16054 #define RCC_PLL2FRACR_PLL2FRACN             RCC_PLL2FRACR_PLL2FRACN_Msk
16055 #define RCC_PLL2FRACR_PLL2FRACN_0           (0x0001UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000008 */
16056 #define RCC_PLL2FRACR_PLL2FRACN_1           (0x0002UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000010 */
16057 #define RCC_PLL2FRACR_PLL2FRACN_2           (0x0004UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000020 */
16058 #define RCC_PLL2FRACR_PLL2FRACN_3           (0x0008UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000040 */
16059 #define RCC_PLL2FRACR_PLL2FRACN_4           (0x0010UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000080 */
16060 #define RCC_PLL2FRACR_PLL2FRACN_5           (0x0020UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000100 */
16061 #define RCC_PLL2FRACR_PLL2FRACN_6           (0x0040UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000200 */
16062 #define RCC_PLL2FRACR_PLL2FRACN_7           (0x0080UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000400 */
16063 #define RCC_PLL2FRACR_PLL2FRACN_8           (0x0100UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000800 */
16064 #define RCC_PLL2FRACR_PLL2FRACN_9           (0x0200UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00001000 */
16065 #define RCC_PLL2FRACR_PLL2FRACN_10          (0x0400UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00002000 */
16066 #define RCC_PLL2FRACR_PLL2FRACN_11          (0x0800UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00004000 */
16067 #define RCC_PLL2FRACR_PLL2FRACN_12          (0x1000UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00008000 */
16068 
16069 /********************  Bit definition for RCC_PLL3DIVR register  ***************/
16070 #define RCC_PLL3DIVR_PLL3N_Pos              (0U)
16071 #define RCC_PLL3DIVR_PLL3N_Msk              (0x1FFUL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x000001FF */
16072 #define RCC_PLL3DIVR_PLL3N                  RCC_PLL3DIVR_PLL3N_Msk
16073 #define RCC_PLL3DIVR_PLL3N_0                (0x001UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000001 */
16074 #define RCC_PLL3DIVR_PLL3N_1                (0x002UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000002 */
16075 #define RCC_PLL3DIVR_PLL3N_2                (0x004UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000004 */
16076 #define RCC_PLL3DIVR_PLL3N_3                (0x008UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000008 */
16077 #define RCC_PLL3DIVR_PLL3N_4                (0x010UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000010 */
16078 #define RCC_PLL3DIVR_PLL3N_5                (0x020UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000020 */
16079 #define RCC_PLL3DIVR_PLL3N_6                (0x040UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000040 */
16080 #define RCC_PLL3DIVR_PLL3N_7                (0x080UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000080 */
16081 #define RCC_PLL3DIVR_PLL3N_8                (0x100UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000100 */
16082 #define RCC_PLL3DIVR_PLL3P_Pos              (9U)
16083 #define RCC_PLL3DIVR_PLL3P_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3P_Pos)      /*!< 0x0000FE00 */
16084 #define RCC_PLL3DIVR_PLL3P                  RCC_PLL3DIVR_PLL3P_Msk
16085 #define RCC_PLL3DIVR_PLL3P_0                (0x001UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000200 */
16086 #define RCC_PLL3DIVR_PLL3P_1                (0x002UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000400 */
16087 #define RCC_PLL3DIVR_PLL3P_2                (0x004UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000800 */
16088 #define RCC_PLL3DIVR_PLL3P_3                (0x008UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00001000 */
16089 #define RCC_PLL3DIVR_PLL3P_4                (0x010UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00002000 */
16090 #define RCC_PLL3DIVR_PLL3P_5                (0x020UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00004000 */
16091 #define RCC_PLL3DIVR_PLL3P_6                (0x040UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00008000 */
16092 #define RCC_PLL3DIVR_PLL3Q_Pos              (16U)
16093 #define RCC_PLL3DIVR_PLL3Q_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3Q_Pos)      /*!< 0x007F0000 */
16094 #define RCC_PLL3DIVR_PLL3Q                  RCC_PLL3DIVR_PLL3Q_Msk
16095 #define RCC_PLL3DIVR_PLL3Q_0                (0x001UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00010000 */
16096 #define RCC_PLL3DIVR_PLL3Q_1                (0x002UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00020000 */
16097 #define RCC_PLL3DIVR_PLL3Q_2                (0x004UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00040000 */
16098 #define RCC_PLL3DIVR_PLL3Q_3                (0x008UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00080000 */
16099 #define RCC_PLL3DIVR_PLL3Q_4                (0x010UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00100000 */
16100 #define RCC_PLL3DIVR_PLL3Q_5                (0x020UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00200020 */
16101 #define RCC_PLL3DIVR_PLL3Q_6                (0x040UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00400000 */
16102 #define RCC_PLL3DIVR_PLL3R_Pos              (24U)
16103 #define RCC_PLL3DIVR_PLL3R_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3R_Pos)      /*!< 0x7F000000 */
16104 #define RCC_PLL3DIVR_PLL3R                  RCC_PLL3DIVR_PLL3R_Msk
16105 #define RCC_PLL3DIVR_PLL3R_0                (0x001UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x01000000 */
16106 #define RCC_PLL3DIVR_PLL3R_1                (0x002UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x02000000 */
16107 #define RCC_PLL3DIVR_PLL3R_2                (0x004UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x04000000 */
16108 #define RCC_PLL3DIVR_PLL3R_3                (0x008UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x08000000 */
16109 #define RCC_PLL3DIVR_PLL3R_4                (0x010UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x10000000 */
16110 #define RCC_PLL3DIVR_PLL3R_5                (0x020UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x20000000 */
16111 #define RCC_PLL3DIVR_PLL3R_6                (0x040UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x40000000 */
16112 
16113 /********************  Bit definition for RCC_PLL3FRACR register  ***************/
16114 #define RCC_PLL3FRACR_PLL3FRACN_Pos         (3U)
16115 #define RCC_PLL3FRACR_PLL3FRACN_Msk         (0x1FFFUL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x0000FFF8 */
16116 #define RCC_PLL3FRACR_PLL3FRACN             RCC_PLL3FRACR_PLL3FRACN_Msk
16117 #define RCC_PLL3FRACR_PLL3FRACN_0           (0x0001UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000008 */
16118 #define RCC_PLL3FRACR_PLL3FRACN_1           (0x0002UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000010 */
16119 #define RCC_PLL3FRACR_PLL3FRACN_2           (0x0004UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000020 */
16120 #define RCC_PLL3FRACR_PLL3FRACN_3           (0x0008UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000040 */
16121 #define RCC_PLL3FRACR_PLL3FRACN_4           (0x0010UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000080 */
16122 #define RCC_PLL3FRACR_PLL3FRACN_5           (0x0020UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000100 */
16123 #define RCC_PLL3FRACR_PLL3FRACN_6           (0x0040UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000200 */
16124 #define RCC_PLL3FRACR_PLL3FRACN_7           (0x0080UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000400 */
16125 #define RCC_PLL3FRACR_PLL3FRACN_8           (0x0100UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000800 */
16126 #define RCC_PLL3FRACR_PLL3FRACN_9           (0x0200UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00001000 */
16127 #define RCC_PLL3FRACR_PLL3FRACN_10          (0x0400UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00002000 */
16128 #define RCC_PLL3FRACR_PLL3FRACN_11          (0x0800UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00004000 */
16129 #define RCC_PLL3FRACR_PLL3FRACN_12          (0x1000UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00008000 */
16130 
16131 /********************  Bit definition for RCC_CIER register  ******************/
16132 #define RCC_CIER_LSIRDYIE_Pos               (0U)
16133 #define RCC_CIER_LSIRDYIE_Msk               (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
16134 #define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk
16135 #define RCC_CIER_LSERDYIE_Pos               (1U)
16136 #define RCC_CIER_LSERDYIE_Msk               (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
16137 #define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk
16138 #define RCC_CIER_CSIRDYIE_Pos               (2U)
16139 #define RCC_CIER_CSIRDYIE_Msk               (0x1UL << RCC_CIER_CSIRDYIE_Pos)        /*!< 0x00000004 */
16140 #define RCC_CIER_CSIRDYIE                   RCC_CIER_CSIRDYIE_Msk
16141 #define RCC_CIER_HSIRDYIE_Pos               (3U)
16142 #define RCC_CIER_HSIRDYIE_Msk               (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
16143 #define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk
16144 #define RCC_CIER_HSERDYIE_Pos               (4U)
16145 #define RCC_CIER_HSERDYIE_Msk               (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
16146 #define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk
16147 #define RCC_CIER_HSI48RDYIE_Pos             (5U)
16148 #define RCC_CIER_HSI48RDYIE_Msk             (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
16149 #define RCC_CIER_HSI48RDYIE                 RCC_CIER_HSI48RDYIE_Msk
16150 #define RCC_CIER_PLL1RDYIE_Pos              (6U)
16151 #define RCC_CIER_PLL1RDYIE_Msk              (0x1UL << RCC_CIER_PLL1RDYIE_Pos)       /*!< 0x00000040 */
16152 #define RCC_CIER_PLL1RDYIE                  RCC_CIER_PLL1RDYIE_Msk
16153 #define RCC_CIER_PLL2RDYIE_Pos              (7U)
16154 #define RCC_CIER_PLL2RDYIE_Msk              (0x1UL << RCC_CIER_PLL2RDYIE_Pos)       /*!< 0x00000080 */
16155 #define RCC_CIER_PLL2RDYIE                  RCC_CIER_PLL2RDYIE_Msk
16156 #define RCC_CIER_PLL3RDYIE_Pos              (8U)
16157 #define RCC_CIER_PLL3RDYIE_Msk              (0x1UL << RCC_CIER_PLL3RDYIE_Pos)       /*!< 0x00000100 */
16158 #define RCC_CIER_PLL3RDYIE                  RCC_CIER_PLL3RDYIE_Msk
16159 
16160 /********************  Bit definition for RCC_CIFR register  ****************/
16161 #define RCC_CIFR_LSIRDYF_Pos                (0U)
16162 #define RCC_CIFR_LSIRDYF_Msk                (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
16163 #define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk
16164 #define RCC_CIFR_LSERDYF_Pos                (1U)
16165 #define RCC_CIFR_LSERDYF_Msk                (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
16166 #define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk
16167 #define RCC_CIFR_CSIRDYF_Pos                (2U)
16168 #define RCC_CIFR_CSIRDYF_Msk                (0x1UL << RCC_CIFR_CSIRDYF_Pos)         /*!< 0x00000004 */
16169 #define RCC_CIFR_CSIRDYF                    RCC_CIFR_CSIRDYF_Msk
16170 #define RCC_CIFR_HSIRDYF_Pos                (3U)
16171 #define RCC_CIFR_HSIRDYF_Msk                (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
16172 #define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk
16173 #define RCC_CIFR_HSERDYF_Pos                (4U)
16174 #define RCC_CIFR_HSERDYF_Msk                (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
16175 #define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk
16176 #define RCC_CIFR_HSI48RDYF_Pos              (5U)
16177 #define RCC_CIFR_HSI48RDYF_Msk              (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000020 */
16178 #define RCC_CIFR_HSI48RDYF                  RCC_CIFR_HSI48RDYF_Msk
16179 #define RCC_CIFR_PLL1RDYF_Pos               (6U)
16180 #define RCC_CIFR_PLL1RDYF_Msk               (0x1UL << RCC_CIFR_PLL1RDYF_Pos)        /*!< 0x00000040 */
16181 #define RCC_CIFR_PLL1RDYF                   RCC_CIFR_PLL1RDYF_Msk
16182 #define RCC_CIFR_PLL2RDYF_Pos               (7U)
16183 #define RCC_CIFR_PLL2RDYF_Msk               (0x1UL << RCC_CIFR_PLL2RDYF_Pos)        /*!< 0x00000080 */
16184 #define RCC_CIFR_PLL2RDYF                   RCC_CIFR_PLL2RDYF_Msk
16185 #define RCC_CIFR_PLL3RDYF_Pos               (8U)
16186 #define RCC_CIFR_PLL3RDYF_Msk               (0x1UL << RCC_CIFR_PLL3RDYF_Pos)        /*!< 0x00000100 */
16187 #define RCC_CIFR_PLL3RDYF                   RCC_CIFR_PLL3RDYF_Msk
16188 #define RCC_CIFR_HSECSSF_Pos                (10U)
16189 #define RCC_CIFR_HSECSSF_Msk                (0x1UL << RCC_CIFR_HSECSSF_Pos)         /*!< 0x00000400 */
16190 #define RCC_CIFR_HSECSSF                    RCC_CIFR_HSECSSF_Msk
16191 
16192 /********************  Bit definition for RCC_CICR register  ****************/
16193 #define RCC_CICR_LSIRDYC_Pos                (0U)
16194 #define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
16195 #define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
16196 #define RCC_CICR_LSERDYC_Pos                (1U)
16197 #define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
16198 #define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
16199 #define RCC_CICR_CSIRDYC_Pos                (2U)
16200 #define RCC_CICR_CSIRDYC_Msk                (0x1UL << RCC_CICR_CSIRDYC_Pos)         /*!< 0x00000004 */
16201 #define RCC_CICR_CSIRDYC                    RCC_CICR_CSIRDYC_Msk
16202 #define RCC_CICR_HSIRDYC_Pos                (3U)
16203 #define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
16204 #define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
16205 #define RCC_CICR_HSERDYC_Pos                (4U)
16206 #define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
16207 #define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
16208 #define RCC_CICR_HSI48RDYC_Pos              (5U)
16209 #define RCC_CICR_HSI48RDYC_Msk              (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000020 */
16210 #define RCC_CICR_HSI48RDYC                  RCC_CICR_HSI48RDYC_Msk
16211 #define RCC_CICR_PLL1RDYC_Pos               (6U)
16212 #define RCC_CICR_PLL1RDYC_Msk               (0x1UL << RCC_CICR_PLL1RDYC_Pos)        /*!< 0x00000040 */
16213 #define RCC_CICR_PLL1RDYC                   RCC_CICR_PLL1RDYC_Msk
16214 #define RCC_CICR_PLL2RDYC_Pos               (7U)
16215 #define RCC_CICR_PLL2RDYC_Msk               (0x1UL << RCC_CICR_PLL2RDYC_Pos)        /*!< 0x00000080 */
16216 #define RCC_CICR_PLL2RDYC                   RCC_CICR_PLL2RDYC_Msk
16217 #define RCC_CICR_PLL3RDYC_Pos               (8U)
16218 #define RCC_CICR_PLL3RDYC_Msk               (0x1UL << RCC_CICR_PLL3RDYC_Pos)        /*!< 0x00000100 */
16219 #define RCC_CICR_PLL3RDYC                   RCC_CICR_PLL3RDYC_Msk
16220 #define RCC_CICR_HSECSSC_Pos                (10U)
16221 #define RCC_CICR_HSECSSC_Msk                (0x1UL << RCC_CICR_HSECSSC_Pos)         /*!< 0x00000400 */
16222 #define RCC_CICR_HSECSSC                    RCC_CICR_HSECSSC_Msk
16223 
16224 /********************  Bit definition for RCC_AHB1RSTR register  **************/
16225 #define RCC_AHB1RSTR_GPDMA1RST_Pos          (0U)
16226 #define RCC_AHB1RSTR_GPDMA1RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos)   /*!< 0x00000001 */
16227 #define RCC_AHB1RSTR_GPDMA1RST              RCC_AHB1RSTR_GPDMA1RST_Msk
16228 #define RCC_AHB1RSTR_GPDMA2RST_Pos          (1U)
16229 #define RCC_AHB1RSTR_GPDMA2RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA2RST_Pos)   /*!< 0x00000002 */
16230 #define RCC_AHB1RSTR_GPDMA2RST              RCC_AHB1RSTR_GPDMA2RST_Msk
16231 #define RCC_AHB1RSTR_CRCRST_Pos             (12U)
16232 #define RCC_AHB1RSTR_CRCRST_Msk             (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)      /*!< 0x00001000 */
16233 #define RCC_AHB1RSTR_CRCRST                 RCC_AHB1RSTR_CRCRST_Msk
16234 #define RCC_AHB1RSTR_CORDICRST_Pos          (14U)
16235 #define RCC_AHB1RSTR_CORDICRST_Msk          (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)   /*!< 0x00004000 */
16236 #define RCC_AHB1RSTR_CORDICRST              RCC_AHB1RSTR_CORDICRST_Msk
16237 #define RCC_AHB1RSTR_FMACRST_Pos            (15U)
16238 #define RCC_AHB1RSTR_FMACRST_Msk            (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)     /*!< 0x00008000 */
16239 #define RCC_AHB1RSTR_FMACRST                RCC_AHB1RSTR_FMACRST_Msk
16240 #define RCC_AHB1RSTR_RAMCFGRST_Pos          (17U)
16241 #define RCC_AHB1RSTR_RAMCFGRST_Msk          (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos)   /*!< 0x00020000 */
16242 #define RCC_AHB1RSTR_RAMCFGRST              RCC_AHB1RSTR_RAMCFGRST_Msk
16243 #define RCC_AHB1RSTR_ETHRST_Pos             (19U)
16244 #define RCC_AHB1RSTR_ETHRST_Msk             (0x1UL << RCC_AHB1RSTR_ETHRST_Pos)      /*!< 0x00080000 */
16245 #define RCC_AHB1RSTR_ETHRST                 RCC_AHB1RSTR_ETHRST_Msk
16246 #define RCC_AHB1RSTR_TZSC1RST_Pos           (24U)
16247 #define RCC_AHB1RSTR_TZSC1RST_Msk           (0x1UL << RCC_AHB1RSTR_TZSC1RST_Pos)    /*!< 0x01000000 */
16248 #define RCC_AHB1RSTR_TZSC1RST               RCC_AHB1RSTR_TZSC1RST_Msk
16249 
16250 /********************  Bit definition for RCC_AHB2RSTR register  **************/
16251 #define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
16252 #define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)    /*!< 0x00000001 */
16253 #define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
16254 #define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
16255 #define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)    /*!< 0x00000002 */
16256 #define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
16257 #define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
16258 #define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)    /*!< 0x00000004 */
16259 #define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
16260 #define RCC_AHB2RSTR_GPIODRST_Pos           (3U)
16261 #define RCC_AHB2RSTR_GPIODRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)    /*!< 0x00000008 */
16262 #define RCC_AHB2RSTR_GPIODRST               RCC_AHB2RSTR_GPIODRST_Msk
16263 #define RCC_AHB2RSTR_GPIOERST_Pos           (4U)
16264 #define RCC_AHB2RSTR_GPIOERST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)    /*!< 0x00000010 */
16265 #define RCC_AHB2RSTR_GPIOERST               RCC_AHB2RSTR_GPIOERST_Msk
16266 #define RCC_AHB2RSTR_GPIOFRST_Pos           (5U)
16267 #define RCC_AHB2RSTR_GPIOFRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)    /*!< 0x00000020 */
16268 #define RCC_AHB2RSTR_GPIOFRST               RCC_AHB2RSTR_GPIOFRST_Msk
16269 #define RCC_AHB2RSTR_GPIOGRST_Pos           (6U)
16270 #define RCC_AHB2RSTR_GPIOGRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)    /*!< 0x00000040 */
16271 #define RCC_AHB2RSTR_GPIOGRST               RCC_AHB2RSTR_GPIOGRST_Msk
16272 #define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
16273 #define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)    /*!< 0x00000080 */
16274 #define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
16275 #define RCC_AHB2RSTR_GPIOIRST_Pos           (8U)
16276 #define RCC_AHB2RSTR_GPIOIRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOIRST_Pos)    /*!< 0x00000100 */
16277 #define RCC_AHB2RSTR_GPIOIRST               RCC_AHB2RSTR_GPIOIRST_Msk
16278 #define RCC_AHB2RSTR_ADC12RST_Pos           (10U)
16279 #define RCC_AHB2RSTR_ADC12RST_Msk           (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)     /*!< 0x00000400 */
16280 #define RCC_AHB2RSTR_ADC12RST               RCC_AHB2RSTR_ADC12RST_Msk
16281 #define RCC_AHB2RSTR_DAC12RST_Pos           (11U)
16282 #define RCC_AHB2RSTR_DAC12RST_Msk           (0x1UL << RCC_AHB2RSTR_DAC12RST_Pos)    /*!< 0x00000800 */
16283 #define RCC_AHB2RSTR_DAC12RST               RCC_AHB2RSTR_DAC12RST_Msk
16284 #define RCC_AHB2RSTR_DCMI_PSSIRST_Pos       (12U)
16285 #define RCC_AHB2RSTR_DCMI_PSSIRST_Msk       (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos) /*!< 0x00001000 */
16286 #define RCC_AHB2RSTR_DCMI_PSSIRST           RCC_AHB2RSTR_DCMI_PSSIRST_Msk
16287 #define RCC_AHB2RSTR_AESRST_Pos             (16U)
16288 #define RCC_AHB2RSTR_AESRST_Msk             (0x1UL << RCC_AHB2RSTR_AESRST_Pos)    /*!< 0x00010000 */
16289 #define RCC_AHB2RSTR_AESRST                 RCC_AHB2RSTR_AESRST_Msk
16290 #define RCC_AHB2RSTR_HASHRST_Pos            (17U)
16291 #define RCC_AHB2RSTR_HASHRST_Msk            (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)     /*!< 0x00020000 */
16292 #define RCC_AHB2RSTR_HASHRST                RCC_AHB2RSTR_HASHRST_Msk
16293 #define RCC_AHB2RSTR_RNGRST_Pos             (18U)
16294 #define RCC_AHB2RSTR_RNGRST_Msk             (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)      /*!< 0x00040000 */
16295 #define RCC_AHB2RSTR_RNGRST                 RCC_AHB2RSTR_RNGRST_Msk
16296 #define RCC_AHB2RSTR_PKARST_Pos             (19U)
16297 #define RCC_AHB2RSTR_PKARST_Msk             (0x1UL << RCC_AHB2RSTR_PKARST_Pos)      /*!< 0x00080000 */
16298 #define RCC_AHB2RSTR_PKARST                 RCC_AHB2RSTR_PKARST_Msk
16299 #define RCC_AHB2RSTR_SAESRST_Pos            (20U)
16300 #define RCC_AHB2RSTR_SAESRST_Msk            (0x1UL << RCC_AHB2RSTR_SAESRST_Pos)   /*!< 0x00100000 */
16301 #define RCC_AHB2RSTR_SAESRST                RCC_AHB2RSTR_SAESRST_Msk
16302 
16303 /********************  Bit definition for RCC_AHB4RSTR register  **************/
16304 #define RCC_AHB4RSTR_OTFDEC1RST_Pos         (7U)
16305 #define RCC_AHB4RSTR_OTFDEC1RST_Msk         (0x1UL << RCC_AHB4RSTR_OTFDEC1RST_Pos)  /*!< 0x00000080 */
16306 #define RCC_AHB4RSTR_OTFDEC1RST             RCC_AHB4RSTR_OTFDEC1RST_Msk
16307 #define RCC_AHB4RSTR_SDMMC1RST_Pos          (11U)
16308 #define RCC_AHB4RSTR_SDMMC1RST_Msk          (0x1UL << RCC_AHB4RSTR_SDMMC1RST_Pos)   /*!< 0x00000800 */
16309 #define RCC_AHB4RSTR_SDMMC1RST              RCC_AHB4RSTR_SDMMC1RST_Msk
16310 #define RCC_AHB4RSTR_SDMMC2RST_Pos          (12U)
16311 #define RCC_AHB4RSTR_SDMMC2RST_Msk          (0x1UL << RCC_AHB4RSTR_SDMMC2RST_Pos)   /*!< 0x0001000 */
16312 #define RCC_AHB4RSTR_SDMMC2RST              RCC_AHB4RSTR_SDMMC2RST_Msk
16313 #define RCC_AHB4RSTR_FMCRST_Pos             (16U)
16314 #define RCC_AHB4RSTR_FMCRST_Msk             (0x1UL << RCC_AHB4RSTR_FMCRST_Pos)      /*!< 0x00010000 */
16315 #define RCC_AHB4RSTR_FMCRST                 RCC_AHB4RSTR_FMCRST_Msk
16316 #define RCC_AHB4RSTR_OCTOSPI1RST_Pos        (20U)
16317 #define RCC_AHB4RSTR_OCTOSPI1RST_Msk        (0x1UL << RCC_AHB4RSTR_OCTOSPI1RST_Pos) /*!< 0x00100000 */
16318 #define RCC_AHB4RSTR_OCTOSPI1RST            RCC_AHB4RSTR_OCTOSPI1RST_Msk
16319 
16320 /********************  Bit definition for RCC_APB1LRSTR register  **************/
16321 #define RCC_APB1LRSTR_TIM2RST_Pos           (0U)
16322 #define RCC_APB1LRSTR_TIM2RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)    /*!< 0x00000001 */
16323 #define RCC_APB1LRSTR_TIM2RST               RCC_APB1LRSTR_TIM2RST_Msk
16324 #define RCC_APB1LRSTR_TIM3RST_Pos           (1U)
16325 #define RCC_APB1LRSTR_TIM3RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)    /*!< 0x00000002 */
16326 #define RCC_APB1LRSTR_TIM3RST               RCC_APB1LRSTR_TIM3RST_Msk
16327 #define RCC_APB1LRSTR_TIM4RST_Pos           (2U)
16328 #define RCC_APB1LRSTR_TIM4RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)    /*!< 0x00000004 */
16329 #define RCC_APB1LRSTR_TIM4RST               RCC_APB1LRSTR_TIM4RST_Msk
16330 #define RCC_APB1LRSTR_TIM5RST_Pos           (3U)
16331 #define RCC_APB1LRSTR_TIM5RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)    /*!< 0x00000008 */
16332 #define RCC_APB1LRSTR_TIM5RST               RCC_APB1LRSTR_TIM5RST_Msk
16333 #define RCC_APB1LRSTR_TIM6RST_Pos           (4U)
16334 #define RCC_APB1LRSTR_TIM6RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)    /*!< 0x00000010 */
16335 #define RCC_APB1LRSTR_TIM6RST               RCC_APB1LRSTR_TIM6RST_Msk
16336 #define RCC_APB1LRSTR_TIM7RST_Pos           (5U)
16337 #define RCC_APB1LRSTR_TIM7RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)    /*!< 0x00000020 */
16338 #define RCC_APB1LRSTR_TIM7RST               RCC_APB1LRSTR_TIM7RST_Msk
16339 #define RCC_APB1LRSTR_TIM12RST_Pos          (6U)
16340 #define RCC_APB1LRSTR_TIM12RST_Msk          (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)  /*!< 0x00000040 */
16341 #define RCC_APB1LRSTR_TIM12RST              RCC_APB1LRSTR_TIM12RST_Msk
16342 #define RCC_APB1LRSTR_TIM13RST_Pos          (7U)
16343 #define RCC_APB1LRSTR_TIM13RST_Msk          (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)  /*!< 0x00000080 */
16344 #define RCC_APB1LRSTR_TIM13RST              RCC_APB1LRSTR_TIM13RST_Msk
16345 #define RCC_APB1LRSTR_TIM14RST_Pos          (8U)
16346 #define RCC_APB1LRSTR_TIM14RST_Msk          (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)  /*!< 0x00000100 */
16347 #define RCC_APB1LRSTR_TIM14RST              RCC_APB1LRSTR_TIM14RST_Msk
16348 #define RCC_APB1LRSTR_SPI2RST_Pos           (14U)
16349 #define RCC_APB1LRSTR_SPI2RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)    /*!< 0x00004000 */
16350 #define RCC_APB1LRSTR_SPI2RST               RCC_APB1LRSTR_SPI2RST_Msk
16351 #define RCC_APB1LRSTR_SPI3RST_Pos           (15U)
16352 #define RCC_APB1LRSTR_SPI3RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)    /*!< 0x00008000 */
16353 #define RCC_APB1LRSTR_SPI3RST               RCC_APB1LRSTR_SPI3RST_Msk
16354 #define RCC_APB1LRSTR_USART2RST_Pos         (17U)
16355 #define RCC_APB1LRSTR_USART2RST_Msk         (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)  /*!< 0x00020000 */
16356 #define RCC_APB1LRSTR_USART2RST             RCC_APB1LRSTR_USART2RST_Msk
16357 #define RCC_APB1LRSTR_USART3RST_Pos         (18U)
16358 #define RCC_APB1LRSTR_USART3RST_Msk         (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)  /*!< 0x00040000 */
16359 #define RCC_APB1LRSTR_USART3RST             RCC_APB1LRSTR_USART3RST_Msk
16360 #define RCC_APB1LRSTR_UART4RST_Pos          (19U)
16361 #define RCC_APB1LRSTR_UART4RST_Msk          (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)   /*!< 0x00080000 */
16362 #define RCC_APB1LRSTR_UART4RST              RCC_APB1LRSTR_UART4RST_Msk
16363 #define RCC_APB1LRSTR_UART5RST_Pos          (20U)
16364 #define RCC_APB1LRSTR_UART5RST_Msk          (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)   /*!< 0x00100000 */
16365 #define RCC_APB1LRSTR_UART5RST              RCC_APB1LRSTR_UART5RST_Msk
16366 #define RCC_APB1LRSTR_I2C1RST_Pos           (21U)
16367 #define RCC_APB1LRSTR_I2C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)    /*!< 0x00200000 */
16368 #define RCC_APB1LRSTR_I2C1RST               RCC_APB1LRSTR_I2C1RST_Msk
16369 #define RCC_APB1LRSTR_I2C2RST_Pos           (22U)
16370 #define RCC_APB1LRSTR_I2C2RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)    /*!< 0x00400000 */
16371 #define RCC_APB1LRSTR_I2C2RST               RCC_APB1LRSTR_I2C2RST_Msk
16372 #define RCC_APB1LRSTR_I3C1RST_Pos           (23U)
16373 #define RCC_APB1LRSTR_I3C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos)    /*!< 0x00800000 */
16374 #define RCC_APB1LRSTR_I3C1RST               RCC_APB1LRSTR_I3C1RST_Msk
16375 #define RCC_APB1LRSTR_CRSRST_Pos            (24U)
16376 #define RCC_APB1LRSTR_CRSRST_Msk            (0x1UL << RCC_APB1LRSTR_CRSRST_Pos)     /*!< 0x01000000 */
16377 #define RCC_APB1LRSTR_CRSRST                RCC_APB1LRSTR_CRSRST_Msk
16378 #define RCC_APB1LRSTR_USART6RST_Pos         (25U)
16379 #define RCC_APB1LRSTR_USART6RST_Msk         (0x1UL << RCC_APB1LRSTR_USART6RST_Pos)  /*!< 0x02000000 */
16380 #define RCC_APB1LRSTR_USART6RST             RCC_APB1LRSTR_USART6RST_Msk
16381 #define RCC_APB1LRSTR_USART10RST_Pos        (26U)
16382 #define RCC_APB1LRSTR_USART10RST_Msk        (0x1UL << RCC_APB1LRSTR_USART10RST_Pos) /*!< 0x04000000 */
16383 #define RCC_APB1LRSTR_USART10RST            RCC_APB1LRSTR_USART10RST_Msk
16384 #define RCC_APB1LRSTR_USART11RST_Pos        (27U)
16385 #define RCC_APB1LRSTR_USART11RST_Msk        (0x1UL << RCC_APB1LRSTR_USART11RST_Pos) /*!< 0x08000000 */
16386 #define RCC_APB1LRSTR_USART11RST            RCC_APB1LRSTR_USART11RST_Msk
16387 #define RCC_APB1LRSTR_CECRST_Pos            (28U)
16388 #define RCC_APB1LRSTR_CECRST_Msk            (0x1UL << RCC_APB1LRSTR_CECRST_Pos)      /*!< 0x10000000 */
16389 #define RCC_APB1LRSTR_CECRST                RCC_APB1LRSTR_CECRST_Msk
16390 #define RCC_APB1LRSTR_UART7RST_Pos          (30U)
16391 #define RCC_APB1LRSTR_UART7RST_Msk          (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)    /*!< 0x40000000 */
16392 #define RCC_APB1LRSTR_UART7RST              RCC_APB1LRSTR_UART7RST_Msk
16393 #define RCC_APB1LRSTR_UART8RST_Pos          (31U)
16394 #define RCC_APB1LRSTR_UART8RST_Msk          (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)    /*!< 0x80000000 */
16395 #define RCC_APB1LRSTR_UART8RST              RCC_APB1LRSTR_UART8RST_Msk
16396 
16397 /********************  Bit definition for RCC_APB1HRSTR register  **************/
16398 #define RCC_APB1HRSTR_UART9RST_Pos          (0U)
16399 #define RCC_APB1HRSTR_UART9RST_Msk          (0x1UL << RCC_APB1HRSTR_UART9RST_Pos)    /*!< 0x00000001 */
16400 #define RCC_APB1HRSTR_UART9RST              RCC_APB1HRSTR_UART9RST_Msk
16401 #define RCC_APB1HRSTR_UART12RST_Pos         (1U)
16402 #define RCC_APB1HRSTR_UART12RST_Msk         (0x1UL << RCC_APB1HRSTR_UART12RST_Pos)   /*!< 0x00000002 */
16403 #define RCC_APB1HRSTR_UART12RST             RCC_APB1HRSTR_UART12RST_Msk
16404 #define RCC_APB1HRSTR_DTSRST_Pos            (3U)
16405 #define RCC_APB1HRSTR_DTSRST_Msk            (0x1UL << RCC_APB1HRSTR_DTSRST_Pos)     /*!< 0x00000008 */
16406 #define RCC_APB1HRSTR_DTSRST                RCC_APB1HRSTR_DTSRST_Msk
16407 #define RCC_APB1HRSTR_LPTIM2RST_Pos         (5U)
16408 #define RCC_APB1HRSTR_LPTIM2RST_Msk         (0x1UL << RCC_APB1HRSTR_LPTIM2RST_Pos)  /*!< 0x00000020 */
16409 #define RCC_APB1HRSTR_LPTIM2RST             RCC_APB1HRSTR_LPTIM2RST_Msk
16410 #define RCC_APB1HRSTR_FDCAN12RST_Pos        (9U)
16411 #define RCC_APB1HRSTR_FDCAN12RST_Msk        (0x1UL << RCC_APB1HRSTR_FDCAN12RST_Pos) /*!< 0x00000200 */
16412 #define RCC_APB1HRSTR_FDCAN12RST            RCC_APB1HRSTR_FDCAN12RST_Msk
16413 #define RCC_APB1HRSTR_UCPD1RST_Pos          (23U)
16414 #define RCC_APB1HRSTR_UCPD1RST_Msk          (0x1UL << RCC_APB1HRSTR_UCPD1RST_Pos)    /*!< 0x00800000 */
16415 #define RCC_APB1HRSTR_UCPD1RST              RCC_APB1HRSTR_UCPD1RST_Msk
16416 
16417 /********************  Bit definition for RCC_APB2RSTR register  **************/
16418 #define RCC_APB2RSTR_TIM1RST_Pos            (11U)
16419 #define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)     /*!< 0x00000800 */
16420 #define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
16421 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
16422 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)     /*!< 0x00001000 */
16423 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
16424 #define RCC_APB2RSTR_TIM8RST_Pos            (13U)
16425 #define RCC_APB2RSTR_TIM8RST_Msk            (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)     /*!< 0x00002000 */
16426 #define RCC_APB2RSTR_TIM8RST                RCC_APB2RSTR_TIM8RST_Msk
16427 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
16428 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)   /*!< 0x00004000 */
16429 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
16430 #define RCC_APB2RSTR_TIM15RST_Pos           (16U)
16431 #define RCC_APB2RSTR_TIM15RST_Msk           (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)    /*!< 0x00010000 */
16432 #define RCC_APB2RSTR_TIM15RST               RCC_APB2RSTR_TIM15RST_Msk
16433 #define RCC_APB2RSTR_TIM16RST_Pos           (17U)
16434 #define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)    /*!< 0x00020000 */
16435 #define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk
16436 #define RCC_APB2RSTR_TIM17RST_Pos           (18U)
16437 #define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)    /*!< 0x00040000 */
16438 #define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk
16439 #define RCC_APB2RSTR_SPI4RST_Pos            (19U)
16440 #define RCC_APB2RSTR_SPI4RST_Msk            (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)     /*!< 0x00080000 */
16441 #define RCC_APB2RSTR_SPI4RST                RCC_APB2RSTR_SPI4RST_Msk
16442 #define RCC_APB2RSTR_SPI6RST_Pos            (20U)
16443 #define RCC_APB2RSTR_SPI6RST_Msk            (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)     /*!< 0x00100000 */
16444 #define RCC_APB2RSTR_SPI6RST                RCC_APB2RSTR_SPI6RST_Msk
16445 #define RCC_APB2RSTR_SAI1RST_Pos            (21U)
16446 #define RCC_APB2RSTR_SAI1RST_Msk            (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)     /*!< 0x00200000 */
16447 #define RCC_APB2RSTR_SAI1RST                RCC_APB2RSTR_SAI1RST_Msk
16448 #define RCC_APB2RSTR_SAI2RST_Pos            (22U)
16449 #define RCC_APB2RSTR_SAI2RST_Msk            (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)     /*!< 0x00400000 */
16450 #define RCC_APB2RSTR_SAI2RST                RCC_APB2RSTR_SAI2RST_Msk
16451 #define RCC_APB2RSTR_USBRST_Pos             (24U)
16452 #define RCC_APB2RSTR_USBRST_Msk             (0x1UL << RCC_APB2RSTR_USBRST_Pos)      /*!< 0x01000000 */
16453 #define RCC_APB2RSTR_USBRST                 RCC_APB2RSTR_USBRST_Msk
16454 
16455 /********************  Bit definition for RCC_APB3RSTR register  **************/
16456 #define RCC_APB3RSTR_SBSRST_Pos             (1U)
16457 #define RCC_APB3RSTR_SBSRST_Msk             (0x1UL << RCC_APB3RSTR_SBSRST_Pos)      /*!< 0x00000002 */
16458 #define RCC_APB3RSTR_SBSRST                 RCC_APB3RSTR_SBSRST_Msk
16459 #define RCC_APB3RSTR_SPI5RST_Pos            (5U)
16460 #define RCC_APB3RSTR_SPI5RST_Msk            (0x1UL << RCC_APB3RSTR_SPI5RST_Pos)     /*!< 0x00000020 */
16461 #define RCC_APB3RSTR_SPI5RST                RCC_APB3RSTR_SPI5RST_Msk
16462 #define RCC_APB3RSTR_LPUART1RST_Pos         (6U)
16463 #define RCC_APB3RSTR_LPUART1RST_Msk         (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)  /*!< 0x00000040 */
16464 #define RCC_APB3RSTR_LPUART1RST             RCC_APB3RSTR_LPUART1RST_Msk
16465 #define RCC_APB3RSTR_I2C3RST_Pos            (7U)
16466 #define RCC_APB3RSTR_I2C3RST_Msk            (0x1UL << RCC_APB3RSTR_I2C3RST_Pos)     /*!< 0x00000080 */
16467 #define RCC_APB3RSTR_I2C3RST                RCC_APB3RSTR_I2C3RST_Msk
16468 #define RCC_APB3RSTR_I2C4RST_Pos            (8U)
16469 #define RCC_APB3RSTR_I2C4RST_Msk            (0x1UL << RCC_APB3RSTR_I2C4RST_Pos)     /*!< 0x00000100 */
16470 #define RCC_APB3RSTR_I2C4RST                RCC_APB3RSTR_I2C4RST_Msk
16471 #define RCC_APB3RSTR_LPTIM1RST_Pos          (11U)
16472 #define RCC_APB3RSTR_LPTIM1RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)   /*!< 0x00000800 */
16473 #define RCC_APB3RSTR_LPTIM1RST              RCC_APB3RSTR_LPTIM1RST_Msk
16474 #define RCC_APB3RSTR_LPTIM3RST_Pos          (12U)
16475 #define RCC_APB3RSTR_LPTIM3RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM3RST_Pos)   /*!< 0x00001000 */
16476 #define RCC_APB3RSTR_LPTIM3RST              RCC_APB3RSTR_LPTIM3RST_Msk
16477 #define RCC_APB3RSTR_LPTIM4RST_Pos          (13U)
16478 #define RCC_APB3RSTR_LPTIM4RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM4RST_Pos)   /*!< 0x00002000 */
16479 #define RCC_APB3RSTR_LPTIM4RST              RCC_APB3RSTR_LPTIM4RST_Msk
16480 #define RCC_APB3RSTR_LPTIM5RST_Pos          (14U)
16481 #define RCC_APB3RSTR_LPTIM5RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM5RST_Pos)   /*!< 0x00004000 */
16482 #define RCC_APB3RSTR_LPTIM5RST              RCC_APB3RSTR_LPTIM5RST_Msk
16483 #define RCC_APB3RSTR_LPTIM6RST_Pos          (15U)
16484 #define RCC_APB3RSTR_LPTIM6RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM6RST_Pos)   /*!< 0x00008000 */
16485 #define RCC_APB3RSTR_LPTIM6RST              RCC_APB3RSTR_LPTIM6RST_Msk
16486 #define RCC_APB3RSTR_VREFRST_Pos            (20U)
16487 #define RCC_APB3RSTR_VREFRST_Msk            (0x1UL << RCC_APB3RSTR_VREFRST_Pos)     /*!< 0x00100000 */
16488 #define RCC_APB3RSTR_VREFRST                RCC_APB3RSTR_VREFRST_Msk
16489 
16490 /********************  Bit definition for RCC_AHB1ENR register  **************/
16491 #define RCC_AHB1ENR_GPDMA1EN_Pos            (0U)
16492 #define RCC_AHB1ENR_GPDMA1EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)     /*!< 0x00000001 */
16493 #define RCC_AHB1ENR_GPDMA1EN                RCC_AHB1ENR_GPDMA1EN_Msk
16494 #define RCC_AHB1ENR_GPDMA2EN_Pos            (1U)
16495 #define RCC_AHB1ENR_GPDMA2EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA2EN_Pos)     /*!< 0x00000002 */
16496 #define RCC_AHB1ENR_GPDMA2EN                RCC_AHB1ENR_GPDMA2EN_Msk
16497 #define RCC_AHB1ENR_FLITFEN_Pos             (8U)
16498 #define RCC_AHB1ENR_FLITFEN_Msk             (0x1UL << RCC_AHB1ENR_FLITFEN_Pos)      /*!< 0x00000100 */
16499 #define RCC_AHB1ENR_FLITFEN                 RCC_AHB1ENR_FLITFEN_Msk
16500 #define RCC_AHB1ENR_CRCEN_Pos               (12U)
16501 #define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)        /*!< 0x00001000 */
16502 #define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
16503 #define RCC_AHB1ENR_CORDICEN_Pos            (14U)
16504 #define RCC_AHB1ENR_CORDICEN_Msk            (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)     /*!< 0x00004000 */
16505 #define RCC_AHB1ENR_CORDICEN                RCC_AHB1ENR_CORDICEN_Msk
16506 #define RCC_AHB1ENR_FMACEN_Pos              (15U)
16507 #define RCC_AHB1ENR_FMACEN_Msk              (0x1UL << RCC_AHB1ENR_FMACEN_Pos)       /*!< 0x00008000 */
16508 #define RCC_AHB1ENR_FMACEN                  RCC_AHB1ENR_FMACEN_Msk
16509 #define RCC_AHB1ENR_RAMCFGEN_Pos            (17U)
16510 #define RCC_AHB1ENR_RAMCFGEN_Msk            (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos)     /*!< 0x00020000 */
16511 #define RCC_AHB1ENR_RAMCFGEN                RCC_AHB1ENR_RAMCFGEN_Msk
16512 #define RCC_AHB1ENR_ETHEN_Pos               (19U)
16513 #define RCC_AHB1ENR_ETHEN_Msk               (0x1UL << RCC_AHB1ENR_ETHEN_Pos)        /*!< 0x00080000 */
16514 #define RCC_AHB1ENR_ETHEN                   RCC_AHB1ENR_ETHEN_Msk
16515 #define RCC_AHB1ENR_ETHTXEN_Pos             (20U)
16516 #define RCC_AHB1ENR_ETHTXEN_Msk             (0x1UL << RCC_AHB1ENR_ETHTXEN_Pos)      /*!< 0x00100000 */
16517 #define RCC_AHB1ENR_ETHTXEN                 RCC_AHB1ENR_ETHTXEN_Msk
16518 #define RCC_AHB1ENR_ETHRXEN_Pos             (21U)
16519 #define RCC_AHB1ENR_ETHRXEN_Msk             (0x1UL << RCC_AHB1ENR_ETHRXEN_Pos)      /*!< 0x00200000 */
16520 #define RCC_AHB1ENR_ETHRXEN                 RCC_AHB1ENR_ETHRXEN_Msk
16521 #define RCC_AHB1ENR_TZSC1EN_Pos             (24U)
16522 #define RCC_AHB1ENR_TZSC1EN_Msk             (0x1UL << RCC_AHB1ENR_TZSC1EN_Pos)      /*!< 0x01000000 */
16523 #define RCC_AHB1ENR_TZSC1EN                 RCC_AHB1ENR_TZSC1EN_Msk
16524 #define RCC_AHB1ENR_BKPRAMEN_Pos            (28U)
16525 #define RCC_AHB1ENR_BKPRAMEN_Msk            (0x1UL << RCC_AHB1ENR_BKPRAMEN_Pos)     /*!< 0x10000000 */
16526 #define RCC_AHB1ENR_BKPRAMEN                RCC_AHB1ENR_BKPRAMEN_Msk
16527 #define RCC_AHB1ENR_DCACHE1EN_Pos           (30U)
16528 #define RCC_AHB1ENR_DCACHE1EN_Msk           (0x1UL << RCC_AHB1ENR_DCACHE1EN_Pos)     /*!< 0x40000000 */
16529 #define RCC_AHB1ENR_DCACHE1EN               RCC_AHB1ENR_DCACHE1EN_Msk
16530 #define RCC_AHB1ENR_SRAM1EN_Pos             (31U)
16531 #define RCC_AHB1ENR_SRAM1EN_Msk             (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos)      /*!< 0x80000000 */
16532 #define RCC_AHB1ENR_SRAM1EN                 RCC_AHB1ENR_SRAM1EN_Msk
16533 
16534 /********************  Bit definition for RCC_AHB2ENR register  **************/
16535 #define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
16536 #define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)      /*!< 0x00000001 */
16537 #define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
16538 #define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
16539 #define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)      /*!< 0x00000002 */
16540 #define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
16541 #define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
16542 #define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)      /*!< 0x00000004 */
16543 #define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
16544 #define RCC_AHB2ENR_GPIODEN_Pos             (3U)
16545 #define RCC_AHB2ENR_GPIODEN_Msk             (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)      /*!< 0x00000008 */
16546 #define RCC_AHB2ENR_GPIODEN                 RCC_AHB2ENR_GPIODEN_Msk
16547 #define RCC_AHB2ENR_GPIOEEN_Pos             (4U)
16548 #define RCC_AHB2ENR_GPIOEEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)      /*!< 0x00000010 */
16549 #define RCC_AHB2ENR_GPIOEEN                 RCC_AHB2ENR_GPIOEEN_Msk
16550 #define RCC_AHB2ENR_GPIOFEN_Pos             (5U)
16551 #define RCC_AHB2ENR_GPIOFEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)      /*!< 0x00000020 */
16552 #define RCC_AHB2ENR_GPIOFEN                 RCC_AHB2ENR_GPIOFEN_Msk
16553 #define RCC_AHB2ENR_GPIOGEN_Pos             (6U)
16554 #define RCC_AHB2ENR_GPIOGEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)      /*!< 0x00000040 */
16555 #define RCC_AHB2ENR_GPIOGEN                 RCC_AHB2ENR_GPIOGEN_Msk
16556 #define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
16557 #define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)      /*!< 0x00000080 */
16558 #define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
16559 #define RCC_AHB2ENR_GPIOIEN_Pos             (8U)
16560 #define RCC_AHB2ENR_GPIOIEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOIEN_Pos)      /*!< 0x00000100 */
16561 #define RCC_AHB2ENR_GPIOIEN                 RCC_AHB2ENR_GPIOIEN_Msk
16562 #define RCC_AHB2ENR_ADC12EN_Pos             (10U)
16563 #define RCC_AHB2ENR_ADC12EN_Msk             (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)       /*!< 0x00000400 */
16564 #define RCC_AHB2ENR_ADC12EN                 RCC_AHB2ENR_ADC12EN_Msk
16565 #define RCC_AHB2ENR_DAC12EN_Pos             (11U)
16566 #define RCC_AHB2ENR_DAC12EN_Msk             (0x1UL << RCC_AHB2ENR_DAC12EN_Pos)      /*!< 0x00000800 */
16567 #define RCC_AHB2ENR_DAC12EN                 RCC_AHB2ENR_DAC12EN_Msk
16568 #define RCC_AHB2ENR_DCMI_PSSIEN_Pos         (12U)
16569 #define RCC_AHB2ENR_DCMI_PSSIEN_Msk         (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)  /*!< 0x00001000 */
16570 #define RCC_AHB2ENR_DCMI_PSSIEN             RCC_AHB2ENR_DCMI_PSSIEN_Msk
16571 #define RCC_AHB2ENR_AESEN_Pos               (16U)
16572 #define RCC_AHB2ENR_AESEN_Msk               (0x1UL << RCC_AHB2ENR_AESEN_Pos)        /*!< 0x00010000 */
16573 #define RCC_AHB2ENR_AESEN                   RCC_AHB2ENR_AESEN_Msk
16574 #define RCC_AHB2ENR_HASHEN_Pos              (17U)
16575 #define RCC_AHB2ENR_HASHEN_Msk              (0x1UL << RCC_AHB2ENR_HASHEN_Pos)       /*!< 0x00020000 */
16576 #define RCC_AHB2ENR_HASHEN                  RCC_AHB2ENR_HASHEN_Msk
16577 #define RCC_AHB2ENR_RNGEN_Pos               (18U)
16578 #define RCC_AHB2ENR_RNGEN_Msk               (0x1UL << RCC_AHB2ENR_RNGEN_Pos)        /*!< 0x00040000 */
16579 #define RCC_AHB2ENR_RNGEN                   RCC_AHB2ENR_RNGEN_Msk
16580 #define RCC_AHB2ENR_PKAEN_Pos               (19U)
16581 #define RCC_AHB2ENR_PKAEN_Msk               (0x1UL << RCC_AHB2ENR_PKAEN_Pos)        /*!< 0x00080000 */
16582 #define RCC_AHB2ENR_PKAEN                   RCC_AHB2ENR_PKAEN_Msk
16583 #define RCC_AHB2ENR_SAESEN_Pos              (20U)
16584 #define RCC_AHB2ENR_SAESEN_Msk              (0x1UL << RCC_AHB2ENR_SAESEN_Pos)       /*!< 0x00100000 */
16585 #define RCC_AHB2ENR_SAESEN                  RCC_AHB2ENR_SAESEN_Msk
16586 #define RCC_AHB2ENR_SRAM2EN_Pos             (30U)
16587 #define RCC_AHB2ENR_SRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)      /*!< 0x40000000 */
16588 #define RCC_AHB2ENR_SRAM2EN                 RCC_AHB2ENR_SRAM2EN_Msk
16589 #define RCC_AHB2ENR_SRAM3EN_Pos             (31U)
16590 #define RCC_AHB2ENR_SRAM3EN_Msk             (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)      /*!< 0x80000000 */
16591 #define RCC_AHB2ENR_SRAM3EN                 RCC_AHB2ENR_SRAM3EN_Msk
16592 
16593 /********************  Bit definition for RCC_AHB4ENR register  **************/
16594 #define RCC_AHB4ENR_OTFDEC1EN_Pos           (7U)
16595 #define RCC_AHB4ENR_OTFDEC1EN_Msk           (0x1UL << RCC_AHB4ENR_OTFDEC1EN_Pos)    /*!< 0x00000080 */
16596 #define RCC_AHB4ENR_OTFDEC1EN               RCC_AHB4ENR_OTFDEC1EN_Msk
16597 #define RCC_AHB4ENR_SDMMC1EN_Pos            (11U)
16598 #define RCC_AHB4ENR_SDMMC1EN_Msk            (0x1UL << RCC_AHB4ENR_SDMMC1EN_Pos)     /*!< 0x00000800 */
16599 #define RCC_AHB4ENR_SDMMC1EN                RCC_AHB4ENR_SDMMC1EN_Msk
16600 #define RCC_AHB4ENR_SDMMC2EN_Pos            (12U)
16601 #define RCC_AHB4ENR_SDMMC2EN_Msk            (0x1UL << RCC_AHB4ENR_SDMMC2EN_Pos)     /*!< 0x00000100 */
16602 #define RCC_AHB4ENR_SDMMC2EN                RCC_AHB4ENR_SDMMC2EN_Msk
16603 #define RCC_AHB4ENR_FMCEN_Pos               (16U)
16604 #define RCC_AHB4ENR_FMCEN_Msk               (0x1UL << RCC_AHB4ENR_FMCEN_Pos)        /*!< 0x00010000 */
16605 #define RCC_AHB4ENR_FMCEN                   RCC_AHB4ENR_FMCEN_Msk
16606 #define RCC_AHB4ENR_OCTOSPI1EN_Pos          (20U)
16607 #define RCC_AHB4ENR_OCTOSPI1EN_Msk          (0x1UL << RCC_AHB4ENR_OCTOSPI1EN_Pos)   /*!< 0x00100000 */
16608 #define RCC_AHB4ENR_OCTOSPI1EN              RCC_AHB4ENR_OCTOSPI1EN_Msk
16609 
16610 /********************  Bit definition for RCC_APB1LENR register  **************/
16611 #define RCC_APB1LENR_TIM2EN_Pos             (0U)
16612 #define RCC_APB1LENR_TIM2EN_Msk             (0x1UL << RCC_APB1LENR_TIM2EN_Pos)      /*!< 0x00000001 */
16613 #define RCC_APB1LENR_TIM2EN                 RCC_APB1LENR_TIM2EN_Msk
16614 #define RCC_APB1LENR_TIM3EN_Pos             (1U)
16615 #define RCC_APB1LENR_TIM3EN_Msk             (0x1UL << RCC_APB1LENR_TIM3EN_Pos)      /*!< 0x00000002 */
16616 #define RCC_APB1LENR_TIM3EN                 RCC_APB1LENR_TIM3EN_Msk
16617 #define RCC_APB1LENR_TIM4EN_Pos             (2U)
16618 #define RCC_APB1LENR_TIM4EN_Msk             (0x1UL << RCC_APB1LENR_TIM4EN_Pos)      /*!< 0x00000004 */
16619 #define RCC_APB1LENR_TIM4EN                 RCC_APB1LENR_TIM4EN_Msk
16620 #define RCC_APB1LENR_TIM5EN_Pos             (3U)
16621 #define RCC_APB1LENR_TIM5EN_Msk             (0x1UL << RCC_APB1LENR_TIM5EN_Pos)      /*!< 0x00000008 */
16622 #define RCC_APB1LENR_TIM5EN                 RCC_APB1LENR_TIM5EN_Msk
16623 #define RCC_APB1LENR_TIM6EN_Pos             (4U)
16624 #define RCC_APB1LENR_TIM6EN_Msk             (0x1UL << RCC_APB1LENR_TIM6EN_Pos)      /*!< 0x00000010 */
16625 #define RCC_APB1LENR_TIM6EN                 RCC_APB1LENR_TIM6EN_Msk
16626 #define RCC_APB1LENR_TIM7EN_Pos             (5U)
16627 #define RCC_APB1LENR_TIM7EN_Msk             (0x1UL << RCC_APB1LENR_TIM7EN_Pos)      /*!< 0x00000020 */
16628 #define RCC_APB1LENR_TIM7EN                 RCC_APB1LENR_TIM7EN_Msk
16629 #define RCC_APB1LENR_TIM12EN_Pos            (6U)
16630 #define RCC_APB1LENR_TIM12EN_Msk            (0x1UL << RCC_APB1LENR_TIM12EN_Pos)     /*!< 0x00000040 */
16631 #define RCC_APB1LENR_TIM12EN                RCC_APB1LENR_TIM12EN_Msk
16632 #define RCC_APB1LENR_TIM13EN_Pos            (7U)
16633 #define RCC_APB1LENR_TIM13EN_Msk            (0x1UL << RCC_APB1LENR_TIM13EN_Pos)     /*!< 0x00000080 */
16634 #define RCC_APB1LENR_TIM13EN                RCC_APB1LENR_TIM13EN_Msk
16635 #define RCC_APB1LENR_TIM14EN_Pos            (8U)
16636 #define RCC_APB1LENR_TIM14EN_Msk            (0x1UL << RCC_APB1LENR_TIM14EN_Pos)     /*!< 0x00000100 */
16637 #define RCC_APB1LENR_TIM14EN                RCC_APB1LENR_TIM14EN_Msk
16638 #define RCC_APB1LENR_WWDGEN_Pos             (11U)
16639 #define RCC_APB1LENR_WWDGEN_Msk             (0x1UL << RCC_APB1LENR_WWDGEN_Pos)      /*!< 0x00000800 */
16640 #define RCC_APB1LENR_WWDGEN                 RCC_APB1LENR_WWDGEN_Msk
16641 #define RCC_APB1LENR_SPI2EN_Pos             (14U)
16642 #define RCC_APB1LENR_SPI2EN_Msk             (0x1UL << RCC_APB1LENR_SPI2EN_Pos)      /*!< 0x00004000 */
16643 #define RCC_APB1LENR_SPI2EN                 RCC_APB1LENR_SPI2EN_Msk
16644 #define RCC_APB1LENR_SPI3EN_Pos             (15U)
16645 #define RCC_APB1LENR_SPI3EN_Msk             (0x1UL << RCC_APB1LENR_SPI3EN_Pos)      /*!< 0x00008000 */
16646 #define RCC_APB1LENR_SPI3EN                 RCC_APB1LENR_SPI3EN_Msk
16647 #define RCC_APB1LENR_USART2EN_Pos           (17U)
16648 #define RCC_APB1LENR_USART2EN_Msk           (0x1UL << RCC_APB1LENR_USART2EN_Pos)    /*!< 0x00020000 */
16649 #define RCC_APB1LENR_USART2EN               RCC_APB1LENR_USART2EN_Msk
16650 #define RCC_APB1LENR_USART3EN_Pos           (18U)
16651 #define RCC_APB1LENR_USART3EN_Msk           (0x1UL << RCC_APB1LENR_USART3EN_Pos)    /*!< 0x00040000 */
16652 #define RCC_APB1LENR_USART3EN               RCC_APB1LENR_USART3EN_Msk
16653 #define RCC_APB1LENR_UART4EN_Pos            (19U)
16654 #define RCC_APB1LENR_UART4EN_Msk            (0x1UL << RCC_APB1LENR_UART4EN_Pos)     /*!< 0x00080000 */
16655 #define RCC_APB1LENR_UART4EN                RCC_APB1LENR_UART4EN_Msk
16656 #define RCC_APB1LENR_UART5EN_Pos            (20U)
16657 #define RCC_APB1LENR_UART5EN_Msk            (0x1UL << RCC_APB1LENR_UART5EN_Pos)     /*!< 0x00100000 */
16658 #define RCC_APB1LENR_UART5EN                RCC_APB1LENR_UART5EN_Msk
16659 #define RCC_APB1LENR_I2C1EN_Pos             (21U)
16660 #define RCC_APB1LENR_I2C1EN_Msk             (0x1UL << RCC_APB1LENR_I2C1EN_Pos)      /*!< 0x00200000 */
16661 #define RCC_APB1LENR_I2C1EN                 RCC_APB1LENR_I2C1EN_Msk
16662 #define RCC_APB1LENR_I2C2EN_Pos             (22U)
16663 #define RCC_APB1LENR_I2C2EN_Msk             (0x1UL << RCC_APB1LENR_I2C2EN_Pos)      /*!< 0x00400000 */
16664 #define RCC_APB1LENR_I2C2EN                 RCC_APB1LENR_I2C2EN_Msk
16665 #define RCC_APB1LENR_I3C1EN_Pos             (23U)
16666 #define RCC_APB1LENR_I3C1EN_Msk             (0x1UL << RCC_APB1LENR_I3C1EN_Pos)      /*!< 0x00800000 */
16667 #define RCC_APB1LENR_I3C1EN                 RCC_APB1LENR_I3C1EN_Msk
16668 #define RCC_APB1LENR_CRSEN_Pos              (24U)
16669 #define RCC_APB1LENR_CRSEN_Msk              (0x1UL << RCC_APB1LENR_CRSEN_Pos)       /*!< 0x01000000 */
16670 #define RCC_APB1LENR_CRSEN                   RCC_APB1LENR_CRSEN_Msk
16671 #define RCC_APB1LENR_USART6EN_Pos           (25U)
16672 #define RCC_APB1LENR_USART6EN_Msk           (0x1UL << RCC_APB1LENR_USART6EN_Pos)    /*!< 0x02000000 */
16673 #define RCC_APB1LENR_USART6EN               RCC_APB1LENR_USART6EN_Msk
16674 #define RCC_APB1LENR_USART10EN_Pos          (26U)
16675 #define RCC_APB1LENR_USART10EN_Msk          (0x1UL << RCC_APB1LENR_USART10EN_Pos)   /*!< 0x04000000 */
16676 #define RCC_APB1LENR_USART10EN              RCC_APB1LENR_USART10EN_Msk
16677 #define RCC_APB1LENR_USART11EN_Pos          (27U)
16678 #define RCC_APB1LENR_USART11EN_Msk          (0x1UL << RCC_APB1LENR_USART11EN_Pos)   /*!< 0x08000000 */
16679 #define RCC_APB1LENR_USART11EN              RCC_APB1LENR_USART11EN_Msk
16680 #define RCC_APB1LENR_CECEN_Pos              (28U)
16681 #define RCC_APB1LENR_CECEN_Msk              (0x1UL << RCC_APB1LENR_CECEN_Pos)       /*!< 0x10000000 */
16682 #define RCC_APB1LENR_CECEN                  RCC_APB1LENR_CECEN_Msk
16683 #define RCC_APB1LENR_UART7EN_Pos            (30U)
16684 #define RCC_APB1LENR_UART7EN_Msk            (0x1UL << RCC_APB1LENR_UART7EN_Pos)     /*!< 0x40000000 */
16685 #define RCC_APB1LENR_UART7EN                RCC_APB1LENR_UART7EN_Msk
16686 #define RCC_APB1LENR_UART8EN_Pos            (31U)
16687 #define RCC_APB1LENR_UART8EN_Msk            (0x1UL << RCC_APB1LENR_UART8EN_Pos)     /*!< 0x80000000 */
16688 #define RCC_APB1LENR_UART8EN                RCC_APB1LENR_UART8EN_Msk
16689 
16690 /********************  Bit definition for RCC_APB1HENR register  **************/
16691 #define RCC_APB1HENR_UART9EN_Pos            (0U)
16692 #define RCC_APB1HENR_UART9EN_Msk            (0x1UL << RCC_APB1HENR_UART9EN_Pos)     /*!< 0x00000001 */
16693 #define RCC_APB1HENR_UART9EN                RCC_APB1HENR_UART9EN_Msk
16694 #define RCC_APB1HENR_UART12EN_Pos           (1U)
16695 #define RCC_APB1HENR_UART12EN_Msk           (0x1UL << RCC_APB1HENR_UART12EN_Pos)    /*!< 0x00000002 */
16696 #define RCC_APB1HENR_UART12EN               RCC_APB1HENR_UART12EN_Msk
16697 #define RCC_APB1HENR_DTSEN_Pos              (3U)
16698 #define RCC_APB1HENR_DTSEN_Msk              (0x1UL << RCC_APB1HENR_DTSEN_Pos)       /*!< 0x00000008 */
16699 #define RCC_APB1HENR_DTSEN                  RCC_APB1HENR_DTSEN_Msk
16700 #define RCC_APB1HENR_LPTIM2EN_Pos           (5U)
16701 #define RCC_APB1HENR_LPTIM2EN_Msk           (0x1UL << RCC_APB1HENR_LPTIM2EN_Pos)    /*!< 0x00000020 */
16702 #define RCC_APB1HENR_LPTIM2EN               RCC_APB1HENR_LPTIM2EN_Msk
16703 #define RCC_APB1HENR_FDCAN12EN_Pos          (9U)
16704 #define RCC_APB1HENR_FDCAN12EN_Msk          (0x1UL << RCC_APB1HENR_FDCAN12EN_Pos)   /*!< 0x00000200 */
16705 #define RCC_APB1HENR_FDCAN12EN               RCC_APB1HENR_FDCAN12EN_Msk
16706 #define RCC_APB1HENR_UCPD1EN_Pos            (23U)
16707 #define RCC_APB1HENR_UCPD1EN_Msk            (0x1UL << RCC_APB1HENR_UCPD1EN_Pos)     /*!< 0x00800000 */
16708 #define RCC_APB1HENR_UCPD1EN                RCC_APB1HENR_UCPD1EN_Msk
16709 
16710 /********************  Bit definition for RCC_APB2ENR register  **************/
16711 #define RCC_APB2ENR_TIM1EN_Pos              (11U)
16712 #define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)       /*!< 0x00000800 */
16713 #define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
16714 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
16715 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)       /*!< 0x00001000 */
16716 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
16717 #define RCC_APB2ENR_TIM8EN_Pos              (13U)
16718 #define RCC_APB2ENR_TIM8EN_Msk              (0x1UL << RCC_APB2ENR_TIM8EN_Pos)       /*!< 0x00002000 */
16719 #define RCC_APB2ENR_TIM8EN                  RCC_APB2ENR_TIM8EN_Msk
16720 #define RCC_APB2ENR_USART1EN_Pos            (14U)
16721 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)     /*!< 0x00004000 */
16722 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
16723 #define RCC_APB2ENR_TIM15EN_Pos             (16U)
16724 #define RCC_APB2ENR_TIM15EN_Msk             (0x1UL << RCC_APB2ENR_TIM15EN_Pos)      /*!< 0x00010000 */
16725 #define RCC_APB2ENR_TIM15EN                 RCC_APB2ENR_TIM15EN_Msk
16726 #define RCC_APB2ENR_TIM16EN_Pos             (17U)
16727 #define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos)      /*!< 0x00020000 */
16728 #define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk
16729 #define RCC_APB2ENR_TIM17EN_Pos             (18U)
16730 #define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos)      /*!< 0x00040000 */
16731 #define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk
16732 #define RCC_APB2ENR_SPI4EN_Pos              (19U)
16733 #define RCC_APB2ENR_SPI4EN_Msk              (0x1UL << RCC_APB2ENR_SPI4EN_Pos)       /*!< 0x00080000 */
16734 #define RCC_APB2ENR_SPI4EN                  RCC_APB2ENR_SPI4EN_Msk
16735 #define RCC_APB2ENR_SPI6EN_Pos              (20U)
16736 #define RCC_APB2ENR_SPI6EN_Msk              (0x1UL << RCC_APB2ENR_SPI6EN_Pos)       /*!< 0x00100000 */
16737 #define RCC_APB2ENR_SPI6EN                  RCC_APB2ENR_SPI6EN_Msk
16738 #define RCC_APB2ENR_SAI1EN_Pos              (21U)
16739 #define RCC_APB2ENR_SAI1EN_Msk              (0x1UL << RCC_APB2ENR_SAI1EN_Pos)       /*!< 0x00200000 */
16740 #define RCC_APB2ENR_SAI1EN                  RCC_APB2ENR_SAI1EN_Msk
16741 #define RCC_APB2ENR_SAI2EN_Pos              (22U)
16742 #define RCC_APB2ENR_SAI2EN_Msk              (0x1UL << RCC_APB2ENR_SAI2EN_Pos)       /*!< 0x00400000 */
16743 #define RCC_APB2ENR_SAI2EN                  RCC_APB2ENR_SAI2EN_Msk
16744 #define RCC_APB2ENR_USBEN_Pos               (24U)
16745 #define RCC_APB2ENR_USBEN_Msk               (0x1UL << RCC_APB2ENR_USBEN_Pos)        /*!< 0x01000000 */
16746 #define RCC_APB2ENR_USBEN                   RCC_APB2ENR_USBEN_Msk
16747 
16748 /********************  Bit definition for RCC_APB3ENR register  **************/
16749 #define RCC_APB3ENR_SBSEN_Pos               (1U)
16750 #define RCC_APB3ENR_SBSEN_Msk               (0x1UL << RCC_APB3ENR_SBSEN_Pos)        /*!< 0x00000002 */
16751 #define RCC_APB3ENR_SBSEN                   RCC_APB3ENR_SBSEN_Msk
16752 #define RCC_APB3ENR_SPI5EN_Pos              (5U)
16753 #define RCC_APB3ENR_SPI5EN_Msk              (0x1UL << RCC_APB3ENR_SPI5EN_Pos)       /*!< 0x00000010 */
16754 #define RCC_APB3ENR_SPI5EN                  RCC_APB3ENR_SPI5EN_Msk
16755 #define RCC_APB3ENR_LPUART1EN_Pos           (6U)
16756 #define RCC_APB3ENR_LPUART1EN_Msk           (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)    /*!< 0x00000040 */
16757 #define RCC_APB3ENR_LPUART1EN               RCC_APB3ENR_LPUART1EN_Msk
16758 #define RCC_APB3ENR_I2C3EN_Pos              (7U)
16759 #define RCC_APB3ENR_I2C3EN_Msk              (0x1UL << RCC_APB3ENR_I2C3EN_Pos)       /*!< 0x00000080 */
16760 #define RCC_APB3ENR_I2C3EN                  RCC_APB3ENR_I2C3EN_Msk
16761 #define RCC_APB3ENR_I2C4EN_Pos              (8U)
16762 #define RCC_APB3ENR_I2C4EN_Msk              (0x1UL << RCC_APB3ENR_I2C4EN_Pos)       /*!< 0x00000100 */
16763 #define RCC_APB3ENR_I2C4EN                  RCC_APB3ENR_I2C4EN_Msk
16764 #define RCC_APB3ENR_LPTIM1EN_Pos            (11U)
16765 #define RCC_APB3ENR_LPTIM1EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)     /*!< 0x00000800 */
16766 #define RCC_APB3ENR_LPTIM1EN                RCC_APB3ENR_LPTIM1EN_Msk
16767 #define RCC_APB3ENR_LPTIM3EN_Pos            (12U)
16768 #define RCC_APB3ENR_LPTIM3EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos)     /*!< 0x00001000 */
16769 #define RCC_APB3ENR_LPTIM3EN                RCC_APB3ENR_LPTIM3EN_Msk
16770 #define RCC_APB3ENR_LPTIM4EN_Pos            (13U)
16771 #define RCC_APB3ENR_LPTIM4EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos)     /*!< 0x00002000 */
16772 #define RCC_APB3ENR_LPTIM4EN                RCC_APB3ENR_LPTIM4EN_Msk
16773 #define RCC_APB3ENR_LPTIM5EN_Pos            (14U)
16774 #define RCC_APB3ENR_LPTIM5EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM5EN_Pos)     /*!< 0x00004000 */
16775 #define RCC_APB3ENR_LPTIM5EN                RCC_APB3ENR_LPTIM5EN_Msk
16776 #define RCC_APB3ENR_LPTIM6EN_Pos            (15U)
16777 #define RCC_APB3ENR_LPTIM6EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM6EN_Pos)     /*!< 0x00008000 */
16778 #define RCC_APB3ENR_LPTIM6EN                RCC_APB3ENR_LPTIM6EN_Msk
16779 #define RCC_APB3ENR_VREFEN_Pos              (20U)
16780 #define RCC_APB3ENR_VREFEN_Msk              (0x1UL << RCC_APB3ENR_VREFEN_Pos)       /*!< 0x00100000 */
16781 #define RCC_APB3ENR_VREFEN                  RCC_APB3ENR_VREFEN_Msk
16782 #define RCC_APB3ENR_RTCAPBEN_Pos            (21U)
16783 #define RCC_APB3ENR_RTCAPBEN_Msk            (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos)     /*!< 0x00200000 */
16784 #define RCC_APB3ENR_RTCAPBEN                RCC_APB3ENR_RTCAPBEN_Msk
16785 
16786 /********************  Bit definition for RCC_AHB1LPENR register  **************/
16787 #define RCC_AHB1LPENR_GPDMA1LPEN_Pos        (0U)
16788 #define RCC_AHB1LPENR_GPDMA1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000000*/
16789 #define RCC_AHB1LPENR_GPDMA1LPEN            RCC_AHB1LPENR_GPDMA1LPEN_Msk
16790 #define RCC_AHB1LPENR_GPDMA2LPEN_Pos        (1U)
16791 #define RCC_AHB1LPENR_GPDMA2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA2LPEN_Pos) /*!< 0x00000000*/
16792 #define RCC_AHB1LPENR_GPDMA2LPEN            RCC_AHB1LPENR_GPDMA2LPEN_Msk
16793 #define RCC_AHB1LPENR_FLITFLPEN_Pos         (8U)
16794 #define RCC_AHB1LPENR_FLITFLPEN_Msk         (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)   /*!< 0x00000100*/
16795 #define RCC_AHB1LPENR_FLITFLPEN             RCC_AHB1LPENR_FLITFLPEN_Msk
16796 #define RCC_AHB1LPENR_CRCLPEN_Pos           (12U)
16797 #define RCC_AHB1LPENR_CRCLPEN_Msk           (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)    /*!< 0x00001000 */
16798 #define RCC_AHB1LPENR_CRCLPEN               RCC_AHB1LPENR_CRCLPEN_Msk
16799 #define RCC_AHB1LPENR_CORDICLPEN_Pos        (14U)
16800 #define RCC_AHB1LPENR_CORDICLPEN_Msk        (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000*/
16801 #define RCC_AHB1LPENR_CORDICLPEN            RCC_AHB1LPENR_CORDICLPEN_Msk
16802 #define RCC_AHB1LPENR_FMACLPEN_Pos          (15U)
16803 #define RCC_AHB1LPENR_FMACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_FMACLPEN_Pos)   /*!< 0x00008000*/
16804 #define RCC_AHB1LPENR_FMACLPEN              RCC_AHB1LPENR_FMACLPEN_Msk
16805 #define RCC_AHB1LPENR_RAMCFGLPEN_Pos        (17U)
16806 #define RCC_AHB1LPENR_RAMCFGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */
16807 #define RCC_AHB1LPENR_RAMCFGLPEN            RCC_AHB1LPENR_RAMCFGLPEN_Msk
16808 #define RCC_AHB1LPENR_ETHLPEN_Pos           (19U)
16809 #define RCC_AHB1LPENR_ETHLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETHLPEN_Pos)    /*!< 0x00080000 */
16810 #define RCC_AHB1LPENR_ETHLPEN               RCC_AHB1LPENR_ETHLPEN_Msk
16811 #define RCC_AHB1LPENR_ETHTXLPEN_Pos         (20U)
16812 #define RCC_AHB1LPENR_ETHTXLPEN_Msk         (0x1UL << RCC_AHB1LPENR_ETHTXLPEN_Pos)  /*!< 0x00100000 */
16813 #define RCC_AHB1LPENR_ETHTXLPEN             RCC_AHB1LPENR_ETHTXLPEN_Msk
16814 #define RCC_AHB1LPENR_ETHRXLPEN_Pos         (21U)
16815 #define RCC_AHB1LPENR_ETHRXLPEN_Msk         (0x1UL << RCC_AHB1LPENR_ETHRXLPEN_Pos)  /*!< 0x00200000 */
16816 #define RCC_AHB1LPENR_ETHRXLPEN             RCC_AHB1LPENR_ETHRXLPEN_Msk
16817 #define RCC_AHB1LPENR_TZSC1LPEN_Pos         (24U)
16818 #define RCC_AHB1LPENR_TZSC1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_TZSC1LPEN_Pos)  /*!< 0x01000000 */
16819 #define RCC_AHB1LPENR_TZSC1LPEN             RCC_AHB1LPENR_TZSC1LPEN_Msk
16820 #define RCC_AHB1LPENR_BKPRAMLPEN_Pos        (28U)
16821 #define RCC_AHB1LPENR_BKPRAMLPEN_Msk        (0x1UL << RCC_AHB1LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
16822 #define RCC_AHB1LPENR_BKPRAMLPEN            RCC_AHB1LPENR_BKPRAMLPEN_Msk
16823 #define RCC_AHB1LPENR_ICACHELPEN_Pos        (29U)
16824 #define RCC_AHB1LPENR_ICACHELPEN_Msk        (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x20000000 */
16825 #define RCC_AHB1LPENR_ICACHELPEN            RCC_AHB1LPENR_ICACHELPEN_Msk
16826 #define RCC_AHB1LPENR_DCACHE1LPEN_Pos       (30U)
16827 #define RCC_AHB1LPENR_DCACHE1LPEN_Msk       (0x1UL << RCC_AHB1LPENR_DCACHE1LPEN_Pos) /*!< 0x40000000 */
16828 #define RCC_AHB1LPENR_DCACHE1LPEN           RCC_AHB1LPENR_DCACHE1LPEN_Msk
16829 #define RCC_AHB1LPENR_SRAM1LPEN_Pos         (31U)
16830 #define RCC_AHB1LPENR_SRAM1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)  /*!< 0x80000000 */
16831 #define RCC_AHB1LPENR_SRAM1LPEN             RCC_AHB1LPENR_SRAM1LPEN_Msk
16832 
16833 /********************  Bit definition for RCC_AHB2LPENR register  **************/
16834 #define RCC_AHB2LPENR_GPIOALPEN_Pos         (0U)
16835 #define RCC_AHB2LPENR_GPIOALPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos)  /*!< 0x00000001 */
16836 #define RCC_AHB2LPENR_GPIOALPEN             RCC_AHB2LPENR_GPIOALPEN_Msk
16837 #define RCC_AHB2LPENR_GPIOBLPEN_Pos         (1U)
16838 #define RCC_AHB2LPENR_GPIOBLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos)  /*!< 0x00000002 */
16839 #define RCC_AHB2LPENR_GPIOBLPEN             RCC_AHB2LPENR_GPIOBLPEN_Msk
16840 #define RCC_AHB2LPENR_GPIOCLPEN_Pos         (2U)
16841 #define RCC_AHB2LPENR_GPIOCLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos)  /*!< 0x00000004 */
16842 #define RCC_AHB2LPENR_GPIOCLPEN             RCC_AHB2LPENR_GPIOCLPEN_Msk
16843 #define RCC_AHB2LPENR_GPIODLPEN_Pos         (3U)
16844 #define RCC_AHB2LPENR_GPIODLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos)  /*!< 0x00000008 */
16845 #define RCC_AHB2LPENR_GPIODLPEN             RCC_AHB2LPENR_GPIODLPEN_Msk
16846 #define RCC_AHB2LPENR_GPIOELPEN_Pos         (4U)
16847 #define RCC_AHB2LPENR_GPIOELPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos)  /*!< 0x00000010 */
16848 #define RCC_AHB2LPENR_GPIOELPEN             RCC_AHB2LPENR_GPIOELPEN_Msk
16849 #define RCC_AHB2LPENR_GPIOFLPEN_Pos         (5U)
16850 #define RCC_AHB2LPENR_GPIOFLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOFLPEN_Pos)  /*!< 0x00000020 */
16851 #define RCC_AHB2LPENR_GPIOFLPEN             RCC_AHB2LPENR_GPIOFLPEN_Msk
16852 #define RCC_AHB2LPENR_GPIOGLPEN_Pos         (6U)
16853 #define RCC_AHB2LPENR_GPIOGLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOGLPEN_Pos)  /*!< 0x00000040 */
16854 #define RCC_AHB2LPENR_GPIOGLPEN             RCC_AHB2LPENR_GPIOGLPEN_Msk
16855 #define RCC_AHB2LPENR_GPIOHLPEN_Pos         (7U)
16856 #define RCC_AHB2LPENR_GPIOHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos)  /*!< 0x00000080 */
16857 #define RCC_AHB2LPENR_GPIOHLPEN             RCC_AHB2LPENR_GPIOHLPEN_Msk
16858 #define RCC_AHB2LPENR_GPIOILPEN_Pos         (8U)
16859 #define RCC_AHB2LPENR_GPIOILPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOILPEN_Pos)  /*!< 0x00000100 */
16860 #define RCC_AHB2LPENR_GPIOILPEN             RCC_AHB2LPENR_GPIOILPEN_Msk
16861 #define RCC_AHB2LPENR_ADC12LPEN_Pos         (10U)
16862 #define RCC_AHB2LPENR_ADC12LPEN_Msk         (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos)   /*!< 0x00000400 */
16863 #define RCC_AHB2LPENR_ADC12LPEN             RCC_AHB2LPENR_ADC12LPEN_Msk
16864 #define RCC_AHB2LPENR_DAC12LPEN_Pos         (11U)
16865 #define RCC_AHB2LPENR_DAC12LPEN_Msk         (0x1UL << RCC_AHB2LPENR_DAC12LPEN_Pos)   /*!< 0x00000800 */
16866 #define RCC_AHB2LPENR_DAC12LPEN             RCC_AHB2LPENR_DAC12LPEN_Msk
16867 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos     (12U)
16868 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk     (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00001000 */
16869 #define RCC_AHB2LPENR_DCMI_PSSILPEN         RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
16870 #define RCC_AHB2LPENR_AESLPEN_Pos           (16U)
16871 #define RCC_AHB2LPENR_AESLPEN_Msk           (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos)  /*!< 0x00010000 */
16872 #define RCC_AHB2LPENR_AESLPEN               RCC_AHB2LPENR_AESLPEN_Msk
16873 #define RCC_AHB2LPENR_HASHLPEN_Pos          (17U)
16874 #define RCC_AHB2LPENR_HASHLPEN_Msk          (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)   /*!< 0x00020000 */
16875 #define RCC_AHB2LPENR_HASHLPEN              RCC_AHB2LPENR_HASHLPEN_Msk
16876 #define RCC_AHB2LPENR_RNGLPEN_Pos           (18U)
16877 #define RCC_AHB2LPENR_RNGLPEN_Msk           (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)    /*!< 0x00040000 */
16878 #define RCC_AHB2LPENR_RNGLPEN               RCC_AHB2LPENR_RNGLPEN_Msk
16879 #define RCC_AHB2LPENR_PKALPEN_Pos           (19U)
16880 #define RCC_AHB2LPENR_PKALPEN_Msk           (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos)    /*!< 0x00080000 */
16881 #define RCC_AHB2LPENR_PKALPEN               RCC_AHB2LPENR_PKALPEN_Msk
16882 #define RCC_AHB2LPENR_SAESLPEN_Pos          (20U)
16883 #define RCC_AHB2LPENR_SAESLPEN_Msk          (0x1UL << RCC_AHB2LPENR_SAESLPEN_Pos)   /*!< 0x00100000 */
16884 #define RCC_AHB2LPENR_SAESLPEN              RCC_AHB2LPENR_SAESLPEN_Msk
16885 #define RCC_AHB2LPENR_SRAM2LPEN_Pos         (30U)
16886 #define RCC_AHB2LPENR_SRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)  /*!< 0x40000000 */
16887 #define RCC_AHB2LPENR_SRAM2LPEN             RCC_AHB2LPENR_SRAM2LPEN_Msk
16888 #define RCC_AHB2LPENR_SRAM3LPEN_Pos         (31U)
16889 #define RCC_AHB2LPENR_SRAM3LPEN_Msk         (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos)  /*!< 0x80000000 */
16890 #define RCC_AHB2LPENR_SRAM3LPEN             RCC_AHB2LPENR_SRAM3LPEN_Msk
16891 
16892 /********************  Bit definition for RCC_AHB4LPENR register  **************/
16893 #define RCC_AHB4LPENR_OTFDEC1LPEN_Pos       (7U)
16894 #define RCC_AHB4LPENR_OTFDEC1LPEN_Msk       (0x1UL << RCC_AHB4LPENR_OTFDEC1LPEN_Pos) /*!< 0x00000008 */
16895 #define RCC_AHB4LPENR_OTFDEC1LPEN           RCC_AHB4LPENR_OTFDEC1LPEN_Msk
16896 #define RCC_AHB4LPENR_SDMMC1LPEN_Pos        (11U)
16897 #define RCC_AHB4LPENR_SDMMC1LPEN_Msk        (0x1UL << RCC_AHB4LPENR_SDMMC1LPEN_Pos)  /*!< 0x00000800 */
16898 #define RCC_AHB4LPENR_SDMMC1LPEN            RCC_AHB4LPENR_SDMMC1LPEN_Msk
16899 #define RCC_AHB4LPENR_SDMMC2LPEN_Pos        (12U)
16900 #define RCC_AHB4LPENR_SDMMC2LPEN_Msk        (0x1UL << RCC_AHB4LPENR_SDMMC2LPEN_Pos)  /*!< 0x00001000 */
16901 #define RCC_AHB4LPENR_SDMMC2LPEN            RCC_AHB4LPENR_SDMMC2LPEN_Msk
16902 #define RCC_AHB4LPENR_FMCLPEN_Pos           (16U)
16903 #define RCC_AHB4LPENR_FMCLPEN_Msk           (0x1UL << RCC_AHB4LPENR_FMCLPEN_Pos)     /*!< 0x00010000 */
16904 #define RCC_AHB4LPENR_FMCLPEN               RCC_AHB4LPENR_FMCLPEN_Msk
16905 #define RCC_AHB4LPENR_OCTOSPI1LPEN_Pos      (20U)
16906 #define RCC_AHB4LPENR_OCTOSPI1LPEN_Msk      (0x1UL << RCC_AHB4LPENR_OCTOSPI1LPEN_Pos)  /*!< 0x00100000 */
16907 #define RCC_AHB4LPENR_OCTOSPI1LPEN          RCC_AHB4LPENR_OCTOSPI1LPEN_Msk
16908 
16909 /********************  Bit definition for RCC_APB1LLPENR register  **************/
16910 #define RCC_APB1LLPENR_TIM2LPEN_Pos         (0U)
16911 #define RCC_APB1LLPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)  /*!< 0x00000001 */
16912 #define RCC_APB1LLPENR_TIM2LPEN             RCC_APB1LLPENR_TIM2LPEN_Msk
16913 #define RCC_APB1LLPENR_TIM3LPEN_Pos         (1U)
16914 #define RCC_APB1LLPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)  /*!< 0x00000002 */
16915 #define RCC_APB1LLPENR_TIM3LPEN             RCC_APB1LLPENR_TIM3LPEN_Msk
16916 #define RCC_APB1LLPENR_TIM4LPEN_Pos         (2U)
16917 #define RCC_APB1LLPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)  /*!< 0x00000004 */
16918 #define RCC_APB1LLPENR_TIM4LPEN             RCC_APB1LLPENR_TIM4LPEN_Msk
16919 #define RCC_APB1LLPENR_TIM5LPEN_Pos         (3U)
16920 #define RCC_APB1LLPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)  /*!< 0x00000008 */
16921 #define RCC_APB1LLPENR_TIM5LPEN             RCC_APB1LLPENR_TIM5LPEN_Msk
16922 #define RCC_APB1LLPENR_TIM6LPEN_Pos         (4U)
16923 #define RCC_APB1LLPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)  /*!< 0x00000010 */
16924 #define RCC_APB1LLPENR_TIM6LPEN             RCC_APB1LLPENR_TIM6LPEN_Msk
16925 #define RCC_APB1LLPENR_TIM7LPEN_Pos         (5U)
16926 #define RCC_APB1LLPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)  /*!< 0x00000020 */
16927 #define RCC_APB1LLPENR_TIM7LPEN             RCC_APB1LLPENR_TIM7LPEN_Msk
16928 #define RCC_APB1LLPENR_TIM12LPEN_Pos        (6U)
16929 #define RCC_APB1LLPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
16930 #define RCC_APB1LLPENR_TIM12LPEN            RCC_APB1LLPENR_TIM12LPEN_Msk
16931 #define RCC_APB1LLPENR_TIM13LPEN_Pos        (7U)
16932 #define RCC_APB1LLPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
16933 #define RCC_APB1LLPENR_TIM13LPEN            RCC_APB1LLPENR_TIM13LPEN_Msk
16934 #define RCC_APB1LLPENR_TIM14LPEN_Pos        (8U)
16935 #define RCC_APB1LLPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
16936 #define RCC_APB1LLPENR_TIM14LPEN            RCC_APB1LLPENR_TIM14LPEN_Msk
16937 #define RCC_APB1LLPENR_WWDGLPEN_Pos         (11U)
16938 #define RCC_APB1LLPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos)  /*!< 0x00000800 */
16939 #define RCC_APB1LLPENR_WWDGLPEN             RCC_APB1LLPENR_WWDGLPEN_Msk
16940 #define RCC_APB1LLPENR_SPI2LPEN_Pos         (14U)
16941 #define RCC_APB1LLPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)  /*!< 0x00004000 */
16942 #define RCC_APB1LLPENR_SPI2LPEN             RCC_APB1LLPENR_SPI2LPEN_Msk
16943 #define RCC_APB1LLPENR_SPI3LPEN_Pos         (15U)
16944 #define RCC_APB1LLPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)  /*!< 0x00008000 */
16945 #define RCC_APB1LLPENR_SPI3LPEN             RCC_APB1LLPENR_SPI3LPEN_Msk
16946 #define RCC_APB1LLPENR_USART2LPEN_Pos       (17U)
16947 #define RCC_APB1LLPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
16948 #define RCC_APB1LLPENR_USART2LPEN           RCC_APB1LLPENR_USART2LPEN_Msk
16949 #define RCC_APB1LLPENR_USART3LPEN_Pos       (18U)
16950 #define RCC_APB1LLPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
16951 #define RCC_APB1LLPENR_USART3LPEN           RCC_APB1LLPENR_USART3LPEN_Msk
16952 #define RCC_APB1LLPENR_UART4LPEN_Pos        (19U)
16953 #define RCC_APB1LLPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
16954 #define RCC_APB1LLPENR_UART4LPEN            RCC_APB1LLPENR_UART4LPEN_Msk
16955 #define RCC_APB1LLPENR_UART5LPEN_Pos        (20U)
16956 #define RCC_APB1LLPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
16957 #define RCC_APB1LLPENR_UART5LPEN            RCC_APB1LLPENR_UART5LPEN_Msk
16958 #define RCC_APB1LLPENR_I2C1LPEN_Pos         (21U)
16959 #define RCC_APB1LLPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)  /*!< 0x00200000 */
16960 #define RCC_APB1LLPENR_I2C1LPEN             RCC_APB1LLPENR_I2C1LPEN_Msk
16961 #define RCC_APB1LLPENR_I2C2LPEN_Pos         (22U)
16962 #define RCC_APB1LLPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)  /*!< 0x00400000 */
16963 #define RCC_APB1LLPENR_I2C2LPEN             RCC_APB1LLPENR_I2C2LPEN_Msk
16964 #define RCC_APB1LLPENR_I3C1LPEN_Pos         (23U)
16965 #define RCC_APB1LLPENR_I3C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos)  /*!< 0x00800000 */
16966 #define RCC_APB1LLPENR_I3C1LPEN             RCC_APB1LLPENR_I3C1LPEN_Msk
16967 #define RCC_APB1LLPENR_CRSLPEN_Pos          (24U)
16968 #define RCC_APB1LLPENR_CRSLPEN_Msk          (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos)   /*!< 0x01000000 */
16969 #define RCC_APB1LLPENR_CRSLPEN              RCC_APB1LLPENR_CRSLPEN_Msk
16970 #define RCC_APB1LLPENR_USART6LPEN_Pos       (25U)
16971 #define RCC_APB1LLPENR_USART6LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART6LPEN_Pos) /*!< 0x02000000 */
16972 #define RCC_APB1LLPENR_USART6LPEN           RCC_APB1LLPENR_USART6LPEN_Msk
16973 #define RCC_APB1LLPENR_USART10LPEN_Pos      (26U)
16974 #define RCC_APB1LLPENR_USART10LPEN_Msk      (0x1UL << RCC_APB1LLPENR_USART10LPEN_Pos) /*!< 0x04000000 */
16975 #define RCC_APB1LLPENR_USART10LPEN          RCC_APB1LLPENR_USART10LPEN_Msk
16976 #define RCC_APB1LLPENR_USART11LPEN_Pos      (27U)
16977 #define RCC_APB1LLPENR_USART11LPEN_Msk      (0x1UL << RCC_APB1LLPENR_USART11LPEN_Pos) /*!< 0x08000000 */
16978 #define RCC_APB1LLPENR_USART11LPEN          RCC_APB1LLPENR_USART11LPEN_Msk
16979 #define RCC_APB1LLPENR_CECLPEN_Pos          (28U)
16980 #define RCC_APB1LLPENR_CECLPEN_Msk          (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)    /*!< 0x10000000 */
16981 #define RCC_APB1LLPENR_CECLPEN              RCC_APB1LLPENR_CECLPEN_Msk
16982 #define RCC_APB1LLPENR_UART7LPEN_Pos        (30U)
16983 #define RCC_APB1LLPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)  /*!< 0x40000000 */
16984 #define RCC_APB1LLPENR_UART7LPEN            RCC_APB1LLPENR_UART7LPEN_Msk
16985 #define RCC_APB1LLPENR_UART8LPEN_Pos        (31U)
16986 #define RCC_APB1LLPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)  /*!< 0x80000000 */
16987 #define RCC_APB1LLPENR_UART8LPEN            RCC_APB1LLPENR_UART8LPEN_Msk
16988 
16989 /********************  Bit definition for RCC_APB1HLPENR register  **************/
16990 #define RCC_APB1HLPENR_UART9LPEN_Pos        (0U)
16991 #define RCC_APB1HLPENR_UART9LPEN_Msk        (0x1UL << RCC_APB1HLPENR_UART9LPEN_Pos)  /*!< 0x00000001 */
16992 #define RCC_APB1HLPENR_UART9LPEN            RCC_APB1HLPENR_UART9LPEN_Msk
16993 #define RCC_APB1HLPENR_UART12LPEN_Pos       (1U)
16994 #define RCC_APB1HLPENR_UART12LPEN_Msk       (0x1UL << RCC_APB1HLPENR_UART12LPEN_Pos) /*!< 0x00000002 */
16995 #define RCC_APB1HLPENR_UART12LPEN           RCC_APB1HLPENR_UART12LPEN_Msk
16996 #define RCC_APB1HLPENR_DTSLPEN_Pos          (3U)
16997 #define RCC_APB1HLPENR_DTSLPEN_Msk          (0x1UL << RCC_APB1HLPENR_DTSLPEN_Pos)    /*!< 0x00000008 */
16998 #define RCC_APB1HLPENR_DTSLPEN              RCC_APB1HLPENR_DTSLPEN_Msk
16999 #define RCC_APB1HLPENR_LPTIM2LPEN_Pos       (5U)
17000 #define RCC_APB1HLPENR_LPTIM2LPEN_Msk       (0x1UL << RCC_APB1HLPENR_LPTIM2LPEN_Pos) /*!< 0x00000020 */
17001 #define RCC_APB1HLPENR_LPTIM2LPEN           RCC_APB1HLPENR_LPTIM2LPEN_Msk
17002 #define RCC_APB1HLPENR_FDCAN12LPEN_Pos      (9U)
17003 #define RCC_APB1HLPENR_FDCAN12LPEN_Msk      (0x1UL << RCC_APB1HLPENR_FDCAN12LPEN_Pos) /*!< 0x00000200 */
17004 #define RCC_APB1HLPENR_FDCAN12LPEN          RCC_APB1HLPENR_FDCAN12LPEN_Msk
17005 #define RCC_APB1HLPENR_UCPD1LPEN_Pos        (23U)
17006 #define RCC_APB1HLPENR_UCPD1LPEN_Msk        (0x1UL << RCC_APB1HLPENR_UCPD1LPEN_Pos)   /*!< 0x00800000 */
17007 #define RCC_APB1HLPENR_UCPD1LPEN            RCC_APB1HLPENR_UCPD1LPEN_Msk
17008 
17009 /********************  Bit definition for RCC_APB2LPENR register  **************/
17010 #define RCC_APB2LPENR_TIM1LPEN_Pos          (11U)
17011 #define RCC_APB2LPENR_TIM1LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)   /*!< 0x00000800 */
17012 #define RCC_APB2LPENR_TIM1LPEN              RCC_APB2LPENR_TIM1LPEN_Msk
17013 #define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
17014 #define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)   /*!< 0x00001000 */
17015 #define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk
17016 #define RCC_APB2LPENR_TIM8LPEN_Pos          (13U)
17017 #define RCC_APB2LPENR_TIM8LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)   /*!< 0x00002000 */
17018 #define RCC_APB2LPENR_TIM8LPEN              RCC_APB2LPENR_TIM8LPEN_Msk
17019 #define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
17020 #define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
17021 #define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk
17022 #define RCC_APB2LPENR_TIM15LPEN_Pos         (16U)
17023 #define RCC_APB2LPENR_TIM15LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)  /*!< 0x00010000 */
17024 #define RCC_APB2LPENR_TIM15LPEN             RCC_APB2LPENR_TIM15LPEN_Msk
17025 #define RCC_APB2LPENR_TIM16LPEN_Pos         (17U)
17026 #define RCC_APB2LPENR_TIM16LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)  /*!< 0x00020000 */
17027 #define RCC_APB2LPENR_TIM16LPEN             RCC_APB2LPENR_TIM16LPEN_Msk
17028 #define RCC_APB2LPENR_TIM17LPEN_Pos         (18U)
17029 #define RCC_APB2LPENR_TIM17LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)  /*!< 0x00040000 */
17030 #define RCC_APB2LPENR_TIM17LPEN             RCC_APB2LPENR_TIM17LPEN_Msk
17031 #define RCC_APB2LPENR_SPI4LPEN_Pos          (19U)
17032 #define RCC_APB2LPENR_SPI4LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)   /*!< 0x00080000 */
17033 #define RCC_APB2LPENR_SPI4LPEN              RCC_APB2LPENR_SPI4LPEN_Msk
17034 #define RCC_APB2LPENR_SPI6LPEN_Pos          (20U)
17035 #define RCC_APB2LPENR_SPI6LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)   /*!< 0x00100000 */
17036 #define RCC_APB2LPENR_SPI6LPEN              RCC_APB2LPENR_SPI6LPEN_Msk
17037 #define RCC_APB2LPENR_SAI1LPEN_Pos          (21U)
17038 #define RCC_APB2LPENR_SAI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)   /*!< 0x00200000 */
17039 #define RCC_APB2LPENR_SAI1LPEN              RCC_APB2LPENR_SAI1LPEN_Msk
17040 #define RCC_APB2LPENR_SAI2LPEN_Pos          (22U)
17041 #define RCC_APB2LPENR_SAI2LPEN_Msk          (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)   /*!< 0x00400000 */
17042 #define RCC_APB2LPENR_SAI2LPEN              RCC_APB2LPENR_SAI2LPEN_Msk
17043 #define RCC_APB2LPENR_USBLPEN_Pos           (24U)
17044 #define RCC_APB2LPENR_USBLPEN_Msk           (0x1UL << RCC_APB2LPENR_USBLPEN_Pos)    /*!< 0x01000000 */
17045 #define RCC_APB2LPENR_USBLPEN               RCC_APB2LPENR_USBLPEN_Msk
17046 
17047 /********************  Bit definition for RCC_APB3LPENR register  **************/
17048 #define RCC_APB3LPENR_SBSLPEN_Pos           (1U)
17049 #define RCC_APB3LPENR_SBSLPEN_Msk           (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos)    /*!< 0x00000001 */
17050 #define RCC_APB3LPENR_SBSLPEN               RCC_APB3LPENR_SBSLPEN_Msk
17051 #define RCC_APB3LPENR_SPI5LPEN_Pos          (5U)
17052 #define RCC_APB3LPENR_SPI5LPEN_Msk          (0x1UL << RCC_APB3LPENR_SPI5LPEN_Pos)   /*!< 0x00000010 */
17053 #define RCC_APB3LPENR_SPI5LPEN              RCC_APB3LPENR_SPI5LPEN_Msk
17054 #define RCC_APB3LPENR_LPUART1LPEN_Pos       (6U)
17055 #define RCC_APB3LPENR_LPUART1LPEN_Msk       (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */
17056 #define RCC_APB3LPENR_LPUART1LPEN           RCC_APB3LPENR_LPUART1LPEN_Msk
17057 #define RCC_APB3LPENR_I2C3LPEN_Pos          (7U)
17058 #define RCC_APB3LPENR_I2C3LPEN_Msk          (0x1UL << RCC_APB3LPENR_I2C3LPEN_Pos)   /*!< 0x00000080 */
17059 #define RCC_APB3LPENR_I2C3LPEN              RCC_APB3LPENR_I2C3LPEN_Msk
17060 #define RCC_APB3LPENR_I2C4LPEN_Pos          (8U)
17061 #define RCC_APB3LPENR_I2C4LPEN_Msk          (0x1UL << RCC_APB3LPENR_I2C4LPEN_Pos)   /*!< 0x00000100 */
17062 #define RCC_APB3LPENR_I2C4LPEN              RCC_APB3LPENR_I2C4LPEN_Msk
17063 #define RCC_APB3LPENR_LPTIM1LPEN_Pos        (11U)
17064 #define RCC_APB3LPENR_LPTIM1LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */
17065 #define RCC_APB3LPENR_LPTIM1LPEN            RCC_APB3LPENR_LPTIM1LPEN_Msk
17066 #define RCC_APB3LPENR_LPTIM3LPEN_Pos        (12U)
17067 #define RCC_APB3LPENR_LPTIM3LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM3LPEN_Pos) /*!< 0x00001000 */
17068 #define RCC_APB3LPENR_LPTIM3LPEN            RCC_APB3LPENR_LPTIM3LPEN_Msk
17069 #define RCC_APB3LPENR_LPTIM4LPEN_Pos        (13U)
17070 #define RCC_APB3LPENR_LPTIM4LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM4LPEN_Pos) /*!< 0x00002000 */
17071 #define RCC_APB3LPENR_LPTIM4LPEN            RCC_APB3LPENR_LPTIM4LPEN_Msk
17072 #define RCC_APB3LPENR_LPTIM5LPEN_Pos        (14U)
17073 #define RCC_APB3LPENR_LPTIM5LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM5LPEN_Pos) /*!< 0x00004000 */
17074 #define RCC_APB3LPENR_LPTIM5LPEN            RCC_APB3LPENR_LPTIM5LPEN_Msk
17075 #define RCC_APB3LPENR_LPTIM6LPEN_Pos        (15U)
17076 #define RCC_APB3LPENR_LPTIM6LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM6LPEN_Pos) /*!< 0x00008000 */
17077 #define RCC_APB3LPENR_LPTIM6LPEN            RCC_APB3LPENR_LPTIM6LPEN_Msk
17078 #define RCC_APB3LPENR_VREFLPEN_Pos          (20U)
17079 #define RCC_APB3LPENR_VREFLPEN_Msk          (0x1UL << RCC_APB3LPENR_VREFLPEN_Pos)   /*!< 0x00100000 */
17080 #define RCC_APB3LPENR_VREFLPEN              RCC_APB3LPENR_VREFLPEN_Msk
17081 #define RCC_APB3LPENR_RTCAPBLPEN_Pos        (21U)
17082 #define RCC_APB3LPENR_RTCAPBLPEN_Msk        (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */
17083 #define RCC_APB3LPENR_RTCAPBLPEN            RCC_APB3LPENR_RTCAPBLPEN_Msk
17084 
17085 /********************  Bit definition for RCC_CCIPR1 register  ******************/
17086 #define RCC_CCIPR1_USART1SEL_Pos            (0U)
17087 #define RCC_CCIPR1_USART1SEL_Msk            (0x7UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000007 */
17088 #define RCC_CCIPR1_USART1SEL                RCC_CCIPR1_USART1SEL_Msk
17089 #define RCC_CCIPR1_USART1SEL_0              (0x1UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000001 */
17090 #define RCC_CCIPR1_USART1SEL_1              (0x2UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000002 */
17091 #define RCC_CCIPR1_USART1SEL_2              (0x4UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000004 */
17092 
17093 #define RCC_CCIPR1_USART2SEL_Pos            (3U)
17094 #define RCC_CCIPR1_USART2SEL_Msk            (0x7UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000038 */
17095 #define RCC_CCIPR1_USART2SEL                RCC_CCIPR1_USART2SEL_Msk
17096 #define RCC_CCIPR1_USART2SEL_0              (0x1UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000008 */
17097 #define RCC_CCIPR1_USART2SEL_1              (0x2UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000010 */
17098 #define RCC_CCIPR1_USART2SEL_2              (0x4UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000020 */
17099 
17100 #define RCC_CCIPR1_USART3SEL_Pos            (6U)
17101 #define RCC_CCIPR1_USART3SEL_Msk            (0x7UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x000001C0 */
17102 #define RCC_CCIPR1_USART3SEL                RCC_CCIPR1_USART3SEL_Msk
17103 #define RCC_CCIPR1_USART3SEL_0              (0x1UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000040 */
17104 #define RCC_CCIPR1_USART3SEL_1              (0x2UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000080 */
17105 #define RCC_CCIPR1_USART3SEL_2              (0x4UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000100 */
17106 #define RCC_CCIPR1_UART4SEL_Pos             (9U)
17107 #define RCC_CCIPR1_UART4SEL_Msk             (0x7UL << RCC_CCIPR1_UART4SEL_Pos)      /*!< 0x00000E00 */
17108 #define RCC_CCIPR1_UART4SEL                 RCC_CCIPR1_UART4SEL_Msk
17109 #define RCC_CCIPR1_UART4SEL_0               (0x1UL << RCC_CCIPR1_UART4SEL_Pos)      /*!< 0x00000200 */
17110 #define RCC_CCIPR1_UART4SEL_1               (0x2UL << RCC_CCIPR1_UART4SEL_Pos)      /*!< 0x00000400 */
17111 #define RCC_CCIPR1_UART4SEL_2               (0x4UL << RCC_CCIPR1_UART4SEL_Pos)      /*!< 0x00000800 */
17112 
17113 #define RCC_CCIPR1_UART5SEL_Pos             (12U)
17114 #define RCC_CCIPR1_UART5SEL_Msk             (0x7UL << RCC_CCIPR1_UART5SEL_Pos)      /*!< 0x00007000 */
17115 #define RCC_CCIPR1_UART5SEL                 RCC_CCIPR1_UART5SEL_Msk
17116 #define RCC_CCIPR1_UART5SEL_0               (0x1UL << RCC_CCIPR1_UART5SEL_Pos)      /*!< 0x00001000 */
17117 #define RCC_CCIPR1_UART5SEL_1               (0x2UL << RCC_CCIPR1_UART5SEL_Pos)      /*!< 0x00002000 */
17118 #define RCC_CCIPR1_UART5SEL_2               (0x4UL << RCC_CCIPR1_UART5SEL_Pos)      /*!< 0x00004000 */
17119 
17120 #define RCC_CCIPR1_USART6SEL_Pos            (15U)
17121 #define RCC_CCIPR1_USART6SEL_Msk            (0x7UL << RCC_CCIPR1_USART6SEL_Pos)      /*!< 0x00038000 */
17122 #define RCC_CCIPR1_USART6SEL                RCC_CCIPR1_USART6SEL_Msk
17123 #define RCC_CCIPR1_USART6SEL_0              (0x1UL << RCC_CCIPR1_USART6SEL_Pos)      /*!< 0x00008000 */
17124 #define RCC_CCIPR1_USART6SEL_1              (0x2UL << RCC_CCIPR1_USART6SEL_Pos)      /*!< 0x00010000 */
17125 #define RCC_CCIPR1_USART6SEL_2              (0x4UL << RCC_CCIPR1_USART6SEL_Pos)      /*!< 0x00020000 */
17126 
17127 #define RCC_CCIPR1_UART7SEL_Pos             (18U)
17128 #define RCC_CCIPR1_UART7SEL_Msk             (0x7UL << RCC_CCIPR1_UART7SEL_Pos)      /*!< 0x001C0000 */
17129 #define RCC_CCIPR1_UART7SEL                 RCC_CCIPR1_UART7SEL_Msk
17130 #define RCC_CCIPR1_UART7SEL_0               (0x1UL << RCC_CCIPR1_UART7SEL_Pos)      /*!< 0x00040000 */
17131 #define RCC_CCIPR1_UART7SEL_1               (0x2UL << RCC_CCIPR1_UART7SEL_Pos)      /*!< 0x00080000 */
17132 #define RCC_CCIPR1_UART7SEL_2               (0x4UL << RCC_CCIPR1_UART7SEL_Pos)      /*!< 0x00100000 */
17133 
17134 #define RCC_CCIPR1_UART8SEL_Pos             (21U)
17135 #define RCC_CCIPR1_UART8SEL_Msk             (0x7UL << RCC_CCIPR1_UART8SEL_Pos)      /*!< 0x00E00000 */
17136 #define RCC_CCIPR1_UART8SEL                 RCC_CCIPR1_UART8SEL_Msk
17137 #define RCC_CCIPR1_UART8SEL_0               (0x1UL << RCC_CCIPR1_UART8SEL_Pos)      /*!< 0x00200000 */
17138 #define RCC_CCIPR1_UART8SEL_1               (0x2UL << RCC_CCIPR1_UART8SEL_Pos)      /*!< 0x00400000 */
17139 #define RCC_CCIPR1_UART8SEL_2               (0x4UL << RCC_CCIPR1_UART8SEL_Pos)      /*!< 0x00800000 */
17140 
17141 #define RCC_CCIPR1_UART9SEL_Pos             (24U)
17142 #define RCC_CCIPR1_UART9SEL_Msk             (0x7UL << RCC_CCIPR1_UART9SEL_Pos)      /*!< 0x07000000 */
17143 #define RCC_CCIPR1_UART9SEL                 RCC_CCIPR1_UART9SEL_Msk
17144 #define RCC_CCIPR1_UART9SEL_0               (0x1UL << RCC_CCIPR1_UART9SEL_Pos)      /*!< 0x01000000 */
17145 #define RCC_CCIPR1_UART9SEL_1               (0x2UL << RCC_CCIPR1_UART9SEL_Pos)      /*!< 0x02000000 */
17146 #define RCC_CCIPR1_UART9SEL_2               (0x4UL << RCC_CCIPR1_UART9SEL_Pos)      /*!< 0x04000000 */
17147 
17148 #define RCC_CCIPR1_USART10SEL_Pos           (27U)
17149 #define RCC_CCIPR1_USART10SEL_Msk           (0x7UL << RCC_CCIPR1_USART10SEL_Pos)    /*!< 0x38000000 */
17150 #define RCC_CCIPR1_USART10SEL               RCC_CCIPR1_USART10SEL_Msk
17151 #define RCC_CCIPR1_USART10SEL_0             (0x1UL << RCC_CCIPR1_USART10SEL_Pos)    /*!< 0x08000000 */
17152 #define RCC_CCIPR1_USART10SEL_1             (0x2UL << RCC_CCIPR1_USART10SEL_Pos)    /*!< 0x10000000 */
17153 #define RCC_CCIPR1_USART10SEL_2             (0x4UL << RCC_CCIPR1_USART10SEL_Pos)    /*!< 0x20000000 */
17154 
17155 #define RCC_CCIPR1_TIMICSEL_Pos             (31U)
17156 #define RCC_CCIPR1_TIMICSEL_Msk             (0x1UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x10000000 */
17157 #define RCC_CCIPR1_TIMICSEL                 RCC_CCIPR1_TIMICSEL_Msk
17158 
17159 /********************  Bit definition for RCC_CCIPR2 register  ******************/
17160 #define RCC_CCIPR2_USART11SEL_Pos           (0U)
17161 #define RCC_CCIPR2_USART11SEL_Msk           (0x7UL << RCC_CCIPR2_USART11SEL_Pos)    /*!< 0x00000007 */
17162 #define RCC_CCIPR2_USART11SEL               RCC_CCIPR2_USART11SEL_Msk
17163 #define RCC_CCIPR2_USART11SEL_0             (0x1UL << RCC_CCIPR2_USART11SEL_Pos)    /*!< 0x00000001 */
17164 #define RCC_CCIPR2_USART11SEL_1             (0x2UL << RCC_CCIPR2_USART11SEL_Pos)    /*!< 0x00000002 */
17165 #define RCC_CCIPR2_USART11SEL_2             (0x4UL << RCC_CCIPR2_USART11SEL_Pos)    /*!< 0x00000004 */
17166 
17167 #define RCC_CCIPR2_UART12SEL_Pos            (4U)
17168 #define RCC_CCIPR2_UART12SEL_Msk            (0x7UL << RCC_CCIPR2_UART12SEL_Pos)     /*!< 0x00000070 */
17169 #define RCC_CCIPR2_UART12SEL                RCC_CCIPR2_UART12SEL_Msk
17170 #define RCC_CCIPR2_UART12SEL_0              (0x1UL << RCC_CCIPR2_UART12SEL_Pos)     /*!< 0x00000010 */
17171 #define RCC_CCIPR2_UART12SEL_1              (0x2UL << RCC_CCIPR2_UART12SEL_Pos)     /*!< 0x00000020 */
17172 #define RCC_CCIPR2_UART12SEL_2              (0x4UL << RCC_CCIPR2_UART12SEL_Pos)     /*!< 0x00000040 */
17173 
17174 #define RCC_CCIPR2_LPTIM1SEL_Pos            (8U)
17175 #define RCC_CCIPR2_LPTIM1SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000700 */
17176 #define RCC_CCIPR2_LPTIM1SEL                RCC_CCIPR2_LPTIM1SEL_Msk
17177 #define RCC_CCIPR2_LPTIM1SEL_0              (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000100 */
17178 #define RCC_CCIPR2_LPTIM1SEL_1              (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000200 */
17179 #define RCC_CCIPR2_LPTIM1SEL_2              (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000400 */
17180 
17181 #define RCC_CCIPR2_LPTIM2SEL_Pos            (12U)
17182 #define RCC_CCIPR2_LPTIM2SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00007000 */
17183 #define RCC_CCIPR2_LPTIM2SEL                RCC_CCIPR2_LPTIM2SEL_Msk
17184 #define RCC_CCIPR2_LPTIM2SEL_0              (0x1UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00001000 */
17185 #define RCC_CCIPR2_LPTIM2SEL_1              (0x2UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00002000 */
17186 #define RCC_CCIPR2_LPTIM2SEL_2              (0x4UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00004000 */
17187 
17188 #define RCC_CCIPR2_LPTIM3SEL_Pos            (16U)
17189 #define RCC_CCIPR2_LPTIM3SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM3SEL_Pos)     /*!< 0x00070000 */
17190 #define RCC_CCIPR2_LPTIM3SEL                RCC_CCIPR2_LPTIM3SEL_Msk
17191 #define RCC_CCIPR2_LPTIM3SEL_0              (0x1UL << RCC_CCIPR2_LPTIM3SEL_Pos)     /*!< 0x00010000 */
17192 #define RCC_CCIPR2_LPTIM3SEL_1              (0x2UL << RCC_CCIPR2_LPTIM3SEL_Pos)     /*!< 0x00020000 */
17193 #define RCC_CCIPR2_LPTIM3SEL_2              (0x4UL << RCC_CCIPR2_LPTIM3SEL_Pos)     /*!< 0x00040000 */
17194 
17195 #define RCC_CCIPR2_LPTIM4SEL_Pos            (20U)
17196 #define RCC_CCIPR2_LPTIM4SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM4SEL_Pos)     /*!< 0x00700000 */
17197 #define RCC_CCIPR2_LPTIM4SEL                RCC_CCIPR2_LPTIM4SEL_Msk
17198 #define RCC_CCIPR2_LPTIM4SEL_0              (0x1UL << RCC_CCIPR2_LPTIM4SEL_Pos)     /*!< 0x00100000 */
17199 #define RCC_CCIPR2_LPTIM4SEL_1              (0x2UL << RCC_CCIPR2_LPTIM4SEL_Pos)     /*!< 0x00200000 */
17200 #define RCC_CCIPR2_LPTIM4SEL_2              (0x4UL << RCC_CCIPR2_LPTIM4SEL_Pos)     /*!< 0x00400000 */
17201 
17202 #define RCC_CCIPR2_LPTIM5SEL_Pos            (24U)
17203 #define RCC_CCIPR2_LPTIM5SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM5SEL_Pos)     /*!< 0x07000000 */
17204 #define RCC_CCIPR2_LPTIM5SEL                RCC_CCIPR2_LPTIM5SEL_Msk
17205 #define RCC_CCIPR2_LPTIM5SEL_0              (0x1UL << RCC_CCIPR2_LPTIM5SEL_Pos)     /*!< 0x01000000 */
17206 #define RCC_CCIPR2_LPTIM5SEL_1              (0x2UL << RCC_CCIPR2_LPTIM5SEL_Pos)     /*!< 0x02000000 */
17207 #define RCC_CCIPR2_LPTIM5SEL_2              (0x4UL << RCC_CCIPR2_LPTIM5SEL_Pos)     /*!< 0x04000000 */
17208 
17209 #define RCC_CCIPR2_LPTIM6SEL_Pos            (28U)
17210 #define RCC_CCIPR2_LPTIM6SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM6SEL_Pos)     /*!< 0x70000000 */
17211 #define RCC_CCIPR2_LPTIM6SEL                RCC_CCIPR2_LPTIM6SEL_Msk
17212 #define RCC_CCIPR2_LPTIM6SEL_0              (0x1UL << RCC_CCIPR2_LPTIM6SEL_Pos)     /*!< 0x10000000 */
17213 #define RCC_CCIPR2_LPTIM6SEL_1              (0x2UL << RCC_CCIPR2_LPTIM6SEL_Pos)     /*!< 0x20000000 */
17214 #define RCC_CCIPR2_LPTIM6SEL_2              (0x4UL << RCC_CCIPR2_LPTIM6SEL_Pos)     /*!< 0x40000000 */
17215 
17216 /********************  Bit definition for RCC_CCIPR3 register  ***************/
17217 #define RCC_CCIPR3_SPI1SEL_Pos              (0U)
17218 #define RCC_CCIPR3_SPI1SEL_Msk              (0x7UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000007 */
17219 #define RCC_CCIPR3_SPI1SEL                  RCC_CCIPR3_SPI1SEL_Msk
17220 #define RCC_CCIPR3_SPI1SEL_0                (0x1UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000001 */
17221 #define RCC_CCIPR3_SPI1SEL_1                (0x2UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000002 */
17222 #define RCC_CCIPR3_SPI1SEL_2                (0x4UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000004 */
17223 
17224 #define RCC_CCIPR3_SPI2SEL_Pos              (3U)
17225 #define RCC_CCIPR3_SPI2SEL_Msk              (0x7UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000038 */
17226 #define RCC_CCIPR3_SPI2SEL                  RCC_CCIPR3_SPI2SEL_Msk
17227 #define RCC_CCIPR3_SPI2SEL_0                (0x1UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000008 */
17228 #define RCC_CCIPR3_SPI2SEL_1                (0x2UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000010 */
17229 #define RCC_CCIPR3_SPI2SEL_2                (0x4UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000020 */
17230 
17231 #define RCC_CCIPR3_SPI3SEL_Pos              (6U)
17232 #define RCC_CCIPR3_SPI3SEL_Msk              (0x7UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x000001C0 */
17233 #define RCC_CCIPR3_SPI3SEL                  RCC_CCIPR3_SPI3SEL_Msk
17234 #define RCC_CCIPR3_SPI3SEL_0                (0x1UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000040 */
17235 #define RCC_CCIPR3_SPI3SEL_1                (0x2UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000080 */
17236 #define RCC_CCIPR3_SPI3SEL_2                (0x4UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000100 */
17237 
17238 #define RCC_CCIPR3_SPI4SEL_Pos              (9U)
17239 #define RCC_CCIPR3_SPI4SEL_Msk              (0x7UL << RCC_CCIPR3_SPI4SEL_Pos)       /*!< 0x00000E00 */
17240 #define RCC_CCIPR3_SPI4SEL                  RCC_CCIPR3_SPI4SEL_Msk
17241 #define RCC_CCIPR3_SPI4SEL_0                (0x1UL << RCC_CCIPR3_SPI4SEL_Pos)       /*!< 0x00000200 */
17242 #define RCC_CCIPR3_SPI4SEL_1                (0x2UL << RCC_CCIPR3_SPI4SEL_Pos)       /*!< 0x00000400 */
17243 #define RCC_CCIPR3_SPI4SEL_2                (0x4UL << RCC_CCIPR3_SPI4SEL_Pos)       /*!< 0x00000800 */
17244 
17245 #define RCC_CCIPR3_SPI5SEL_Pos              (12U)
17246 #define RCC_CCIPR3_SPI5SEL_Msk              (0x7UL << RCC_CCIPR3_SPI5SEL_Pos)       /*!< 0x00007000 */
17247 #define RCC_CCIPR3_SPI5SEL                  RCC_CCIPR3_SPI5SEL_Msk
17248 #define RCC_CCIPR3_SPI5SEL_0                (0x1UL << RCC_CCIPR3_SPI5SEL_Pos)       /*!< 0x00001000 */
17249 #define RCC_CCIPR3_SPI5SEL_1                (0x2UL << RCC_CCIPR3_SPI5SEL_Pos)       /*!< 0x00002000 */
17250 #define RCC_CCIPR3_SPI5SEL_2                (0x4UL << RCC_CCIPR3_SPI5SEL_Pos)       /*!< 0x00004000 */
17251 
17252 #define RCC_CCIPR3_SPI6SEL_Pos              (15U)
17253 #define RCC_CCIPR3_SPI6SEL_Msk              (0x7UL << RCC_CCIPR3_SPI6SEL_Pos)       /*!< 0x00038000 */
17254 #define RCC_CCIPR3_SPI6SEL                  RCC_CCIPR3_SPI6SEL_Msk
17255 #define RCC_CCIPR3_SPI6SEL_0                (0x1UL << RCC_CCIPR3_SPI6SEL_Pos)       /*!< 0x00008000 */
17256 #define RCC_CCIPR3_SPI6SEL_1                (0x2UL << RCC_CCIPR3_SPI6SEL_Pos)       /*!< 0x00010000 */
17257 #define RCC_CCIPR3_SPI6SEL_2                (0x4UL << RCC_CCIPR3_SPI6SEL_Pos)       /*!< 0x00020000 */
17258 
17259 #define RCC_CCIPR3_LPUART1SEL_Pos           (24U)
17260 #define RCC_CCIPR3_LPUART1SEL_Msk           (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x07000000 */
17261 #define RCC_CCIPR3_LPUART1SEL               RCC_CCIPR3_LPUART1SEL_Msk
17262 #define RCC_CCIPR3_LPUART1SEL_0             (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x01000000 */
17263 #define RCC_CCIPR3_LPUART1SEL_1             (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x02000000 */
17264 #define RCC_CCIPR3_LPUART1SEL_2             (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x04000000 */
17265 
17266 /********************  Bit definition for RCC_CCIPR4 register  ***************/
17267 
17268 #define RCC_CCIPR4_OCTOSPISEL_Pos           (0U)
17269 #define RCC_CCIPR4_OCTOSPISEL_Msk           (0x3UL << RCC_CCIPR4_OCTOSPISEL_Pos)    /*!< 0x00000003 */
17270 #define RCC_CCIPR4_OCTOSPISEL               RCC_CCIPR4_OCTOSPISEL_Msk
17271 #define RCC_CCIPR4_OCTOSPISEL_0             (0x1UL << RCC_CCIPR4_OCTOSPISEL_Pos)    /*!< 0x00000001 */
17272 #define RCC_CCIPR4_OCTOSPISEL_1             (0x2UL << RCC_CCIPR4_OCTOSPISEL_Pos)    /*!< 0x00000002 */
17273 
17274 #define RCC_CCIPR4_SYSTICKSEL_Pos           (2U)
17275 #define RCC_CCIPR4_SYSTICKSEL_Msk           (0x3UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x0000000C */
17276 #define RCC_CCIPR4_SYSTICKSEL               RCC_CCIPR4_SYSTICKSEL_Msk
17277 #define RCC_CCIPR4_SYSTICKSEL_0             (0x1UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000004 */
17278 #define RCC_CCIPR4_SYSTICKSEL_1             (0x2UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000008 */
17279 
17280 #define RCC_CCIPR4_USBSEL_Pos               (4U)
17281 #define RCC_CCIPR4_USBSEL_Msk               (0x3UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000030 */
17282 #define RCC_CCIPR4_USBSEL                   RCC_CCIPR4_USBSEL_Msk
17283 #define RCC_CCIPR4_USBSEL_0                 (0x1UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000010 */
17284 #define RCC_CCIPR4_USBSEL_1                 (0x2UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000020 */
17285 
17286 #define RCC_CCIPR4_SDMMC1SEL_Pos            (6U)
17287 #define RCC_CCIPR4_SDMMC1SEL_Msk            (0x1UL << RCC_CCIPR4_SDMMC1SEL_Pos)     /*!< 0x00000040 */
17288 #define RCC_CCIPR4_SDMMC1SEL                RCC_CCIPR4_SDMMC1SEL_Msk
17289 
17290 #define RCC_CCIPR4_SDMMC2SEL_Pos            (7U)
17291 #define RCC_CCIPR4_SDMMC2SEL_Msk            (0x1UL << RCC_CCIPR4_SDMMC2SEL_Pos)     /*!< 0x00000080 */
17292 #define RCC_CCIPR4_SDMMC2SEL                RCC_CCIPR4_SDMMC2SEL_Msk
17293 
17294 #define RCC_CCIPR4_I2C1SEL_Pos             (16U)
17295 #define RCC_CCIPR4_I2C1SEL_Msk             (0x3UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00030000 */
17296 #define RCC_CCIPR4_I2C1SEL                 RCC_CCIPR4_I2C1SEL_Msk
17297 #define RCC_CCIPR4_I2C1SEL_0               (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00010000 */
17298 #define RCC_CCIPR4_I2C1SEL_1               (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00020000 */
17299 
17300 #define RCC_CCIPR4_I2C2SEL_Pos             (18U)
17301 #define RCC_CCIPR4_I2C2SEL_Msk             (0x3UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x000C0000 */
17302 #define RCC_CCIPR4_I2C2SEL                 RCC_CCIPR4_I2C2SEL_Msk
17303 #define RCC_CCIPR4_I2C2SEL_0               (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00040000 */
17304 #define RCC_CCIPR4_I2C2SEL_1               (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00080000 */
17305 
17306 #define RCC_CCIPR4_I2C3SEL_Pos             (20U)
17307 #define RCC_CCIPR4_I2C3SEL_Msk             (0x3UL << RCC_CCIPR4_I2C3SEL_Pos)      /*!< 0x00300000 */
17308 #define RCC_CCIPR4_I2C3SEL                 RCC_CCIPR4_I2C3SEL_Msk
17309 #define RCC_CCIPR4_I2C3SEL_0               (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)      /*!< 0x00100000 */
17310 #define RCC_CCIPR4_I2C3SEL_1               (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)      /*!< 0x00200000 */
17311 
17312 #define RCC_CCIPR4_I2C4SEL_Pos             (22U)
17313 #define RCC_CCIPR4_I2C4SEL_Msk             (0x3UL << RCC_CCIPR4_I2C4SEL_Pos)      /*!< 0x00C00000 */
17314 #define RCC_CCIPR4_I2C4SEL                 RCC_CCIPR4_I2C4SEL_Msk
17315 #define RCC_CCIPR4_I2C4SEL_0               (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)      /*!< 0x00400000 */
17316 #define RCC_CCIPR4_I2C4SEL_1               (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)      /*!< 0x00800000 */
17317 
17318 #define RCC_CCIPR4_I3C1SEL_Pos             (24U)
17319 #define RCC_CCIPR4_I3C1SEL_Msk             (0x3UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x03000000 */
17320 #define RCC_CCIPR4_I3C1SEL                 RCC_CCIPR4_I3C1SEL_Msk
17321 #define RCC_CCIPR4_I3C1SEL_0               (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x01000000 */
17322 #define RCC_CCIPR4_I3C1SEL_1               (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x02000000 */
17323 
17324 /********************  Bit definition for RCC_CCIPR5 register  ***************/
17325 
17326 #define RCC_CCIPR5_ADCDACSEL_Pos           (0U)
17327 #define RCC_CCIPR5_ADCDACSEL_Msk           (0x7UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000007 */
17328 #define RCC_CCIPR5_ADCDACSEL               RCC_CCIPR5_ADCDACSEL_Msk
17329 #define RCC_CCIPR5_ADCDACSEL_0             (0x1UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000001 */
17330 #define RCC_CCIPR5_ADCDACSEL_1             (0x2UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000002 */
17331 #define RCC_CCIPR5_ADCDACSEL_2             (0x4UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000004 */
17332 
17333 #define RCC_CCIPR5_DACSEL_Pos              (3U)
17334 #define RCC_CCIPR5_DACSEL_Msk              (0x1UL << RCC_CCIPR5_DACSEL_Pos)       /*!< 0x00000008 */
17335 #define RCC_CCIPR5_DACSEL                  RCC_CCIPR5_DACSEL_Msk
17336 
17337 #define RCC_CCIPR5_RNGSEL_Pos              (4U)
17338 #define RCC_CCIPR5_RNGSEL_Msk              (0x3UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000030 */
17339 #define RCC_CCIPR5_RNGSEL                  RCC_CCIPR5_RNGSEL_Msk
17340 #define RCC_CCIPR5_RNGSEL_0                (0x1UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000010 */
17341 #define RCC_CCIPR5_RNGSEL_1                (0x2UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000020 */
17342 
17343 #define RCC_CCIPR5_CECSEL_Pos              (6U)
17344 #define RCC_CCIPR5_CECSEL_Msk              (0x3UL << RCC_CCIPR5_CECSEL_Pos)       /*!< 0x000000C0 */
17345 #define RCC_CCIPR5_CECSEL                  RCC_CCIPR5_CECSEL_Msk
17346 #define RCC_CCIPR5_CECSEL_0                (0x1UL << RCC_CCIPR5_CECSEL_Pos)       /*!< 0x00000040 */
17347 #define RCC_CCIPR5_CECSEL_1                (0x2UL << RCC_CCIPR5_CECSEL_Pos)       /*!< 0x00000080 */
17348 
17349 #define RCC_CCIPR5_FDCAN12SEL_Pos          (8U)
17350 #define RCC_CCIPR5_FDCAN12SEL_Msk          (0x3UL << RCC_CCIPR5_FDCAN12SEL_Pos)   /*!< 0x00000300 */
17351 #define RCC_CCIPR5_FDCAN12SEL              RCC_CCIPR5_FDCAN12SEL_Msk
17352 #define RCC_CCIPR5_FDCAN12SEL_0            (0x1UL << RCC_CCIPR5_FDCAN12SEL_Pos)   /*!< 0x00000100 */
17353 #define RCC_CCIPR5_FDCAN12SEL_1            (0x2UL << RCC_CCIPR5_FDCAN12SEL_Pos)   /*!< 0x00000200 */
17354 
17355 #define RCC_CCIPR5_SAI1SEL_Pos             (16U)
17356 #define RCC_CCIPR5_SAI1SEL_Msk             (0x7UL << RCC_CCIPR5_SAI1SEL_Pos)      /*!< 0x00070000 */
17357 #define RCC_CCIPR5_SAI1SEL                 RCC_CCIPR5_SAI1SEL_Msk
17358 #define RCC_CCIPR5_SAI1SEL_0               (0x1UL << RCC_CCIPR5_SAI1SEL_Pos)      /*!< 0x00010000 */
17359 #define RCC_CCIPR5_SAI1SEL_1               (0x2UL << RCC_CCIPR5_SAI1SEL_Pos)      /*!< 0x00020000 */
17360 #define RCC_CCIPR5_SAI1SEL_2               (0x4UL << RCC_CCIPR5_SAI1SEL_Pos)      /*!< 0x00040000 */
17361 
17362 #define RCC_CCIPR5_SAI2SEL_Pos             (19U)
17363 #define RCC_CCIPR5_SAI2SEL_Msk             (0x7UL << RCC_CCIPR5_SAI2SEL_Pos)      /*!< 0x00380000 */
17364 #define RCC_CCIPR5_SAI2SEL                 RCC_CCIPR5_SAI2SEL_Msk
17365 #define RCC_CCIPR5_SAI2SEL_0               (0x1UL << RCC_CCIPR5_SAI2SEL_Pos)      /*!< 0x00080000 */
17366 #define RCC_CCIPR5_SAI2SEL_1               (0x2UL << RCC_CCIPR5_SAI2SEL_Pos)      /*!< 0x00100000 */
17367 #define RCC_CCIPR5_SAI2SEL_2               (0x4UL << RCC_CCIPR5_SAI2SEL_Pos)      /*!< 0x00200000 */
17368 
17369 #define RCC_CCIPR5_CKERPSEL_Pos            (30U)
17370 #define RCC_CCIPR5_CKERPSEL_Msk            (0x3UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0xC0000000 */
17371 #define RCC_CCIPR5_CKERPSEL                RCC_CCIPR5_CKERPSEL_Msk
17372 #define RCC_CCIPR5_CKERPSEL_0              (0x1UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x40000000 */
17373 #define RCC_CCIPR5_CKERPSEL_1              (0x2UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x80000000 */
17374 
17375 /********************  Bit definition for RCC_BDCR register  ******************/
17376 #define RCC_BDCR_LSEON_Pos                  (0U)
17377 #define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
17378 #define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
17379 #define RCC_BDCR_LSERDY_Pos                 (1U)
17380 #define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
17381 #define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
17382 #define RCC_BDCR_LSEBYP_Pos                 (2U)
17383 #define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
17384 #define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
17385 #define RCC_BDCR_LSEDRV_Pos                 (3U)
17386 #define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
17387 #define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
17388 #define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
17389 #define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
17390 #define RCC_BDCR_LSECSSON_Pos               (5U)
17391 #define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
17392 #define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
17393 #define RCC_BDCR_LSECSSD_Pos                (6U)
17394 #define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
17395 #define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
17396 #define RCC_BDCR_LSEEXT_Pos                 (7U)
17397 #define RCC_BDCR_LSEEXT_Msk                 (0x1UL << RCC_BDCR_LSEEXT_Pos)          /*!< 0x00000080 */
17398 #define RCC_BDCR_LSEEXT                     RCC_BDCR_LSEEXT_Msk
17399 #define RCC_BDCR_RTCSEL_Pos                 (8U)
17400 #define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
17401 #define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
17402 #define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
17403 #define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
17404 #define RCC_BDCR_RTCEN_Pos                  (15U)
17405 #define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
17406 #define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
17407 #define RCC_BDCR_VSWRST_Pos                 (16U)
17408 #define RCC_BDCR_VSWRST_Msk                 (0x1UL << RCC_BDCR_VSWRST_Pos)          /*!< 0x00010000 */
17409 #define RCC_BDCR_VSWRST                     RCC_BDCR_VSWRST_Msk
17410 #define RCC_BDCR_LSCOEN_Pos                 (24U)
17411 #define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
17412 #define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
17413 #define RCC_BDCR_LSCOSEL_Pos                (25U)
17414 #define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
17415 #define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
17416 #define RCC_BDCR_LSION_Pos                  (26U)
17417 #define RCC_BDCR_LSION_Msk                  (0x1UL << RCC_BDCR_LSION_Pos)           /*!< 0x04000000 */
17418 #define RCC_BDCR_LSION                      RCC_BDCR_LSION_Msk
17419 #define RCC_BDCR_LSIRDY_Pos                 (27U)
17420 #define RCC_BDCR_LSIRDY_Msk                 (0x1UL << RCC_BDCR_LSIRDY_Pos)          /*!< 0x08000000 */
17421 #define RCC_BDCR_LSIRDY                     RCC_BDCR_LSIRDY_Msk
17422 
17423 /********************  Bit definition for RCC_RSR register  *******************/
17424 #define RCC_RSR_RMVF_Pos                    (23U)
17425 #define RCC_RSR_RMVF_Msk                    (0x1UL << RCC_RSR_RMVF_Pos)             /*!< 0x00800000 */
17426 #define RCC_RSR_RMVF                        RCC_RSR_RMVF_Msk
17427 #define RCC_RSR_PINRSTF_Pos                 (26U)
17428 #define RCC_RSR_PINRSTF_Msk                 (0x1UL << RCC_RSR_PINRSTF_Pos)          /*!< 0x04000000 */
17429 #define RCC_RSR_PINRSTF                     RCC_RSR_PINRSTF_Msk
17430 #define RCC_RSR_BORRSTF_Pos                 (27U)
17431 #define RCC_RSR_BORRSTF_Msk                 (0x1UL << RCC_RSR_BORRSTF_Pos)          /*!< 0x08000000 */
17432 #define RCC_RSR_BORRSTF                     RCC_RSR_BORRSTF_Msk
17433 #define RCC_RSR_SFTRSTF_Pos                 (28U)
17434 #define RCC_RSR_SFTRSTF_Msk                 (0x1UL << RCC_RSR_SFTRSTF_Pos)          /*!< 0x10000000 */
17435 #define RCC_RSR_SFTRSTF                     RCC_RSR_SFTRSTF_Msk
17436 #define RCC_RSR_IWDGRSTF_Pos                (29U)
17437 #define RCC_RSR_IWDGRSTF_Msk                (0x1UL << RCC_RSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
17438 #define RCC_RSR_IWDGRSTF                    RCC_RSR_IWDGRSTF_Msk
17439 #define RCC_RSR_WWDGRSTF_Pos                (30U)
17440 #define RCC_RSR_WWDGRSTF_Msk                (0x1UL << RCC_RSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
17441 #define RCC_RSR_WWDGRSTF                    RCC_RSR_WWDGRSTF_Msk
17442 #define RCC_RSR_LPWRRSTF_Pos                (31U)
17443 #define RCC_RSR_LPWRRSTF_Msk                (0x1UL << RCC_RSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
17444 #define RCC_RSR_LPWRRSTF                    RCC_RSR_LPWRRSTF_Msk
17445 
17446 /********************  Bit definition for RCC_SECCFGR register  **************/
17447 #define RCC_SECCFGR_HSISEC_Pos              (0U)
17448 #define RCC_SECCFGR_HSISEC_Msk              (0x1UL << RCC_SECCFGR_HSISEC_Pos)       /*!< 0x00000001 */
17449 #define RCC_SECCFGR_HSISEC                  RCC_SECCFGR_HSISEC_Msk
17450 #define RCC_SECCFGR_HSESEC_Pos              (1U)
17451 #define RCC_SECCFGR_HSESEC_Msk              (0x1UL << RCC_SECCFGR_HSESEC_Pos)       /*!< 0x00000002 */
17452 #define RCC_SECCFGR_HSESEC                  RCC_SECCFGR_HSESEC_Msk
17453 #define RCC_SECCFGR_CSISEC_Pos              (2U)
17454 #define RCC_SECCFGR_CSISEC_Msk              (0x1UL << RCC_SECCFGR_CSISEC_Pos)       /*!< 0x00000004 */
17455 #define RCC_SECCFGR_CSISEC                  RCC_SECCFGR_CSISEC_Msk
17456 #define RCC_SECCFGR_LSISEC_Pos              (3U)
17457 #define RCC_SECCFGR_LSISEC_Msk              (0x1UL << RCC_SECCFGR_LSISEC_Pos)       /*!< 0x00000008 */
17458 #define RCC_SECCFGR_LSISEC                  RCC_SECCFGR_LSISEC_Msk
17459 #define RCC_SECCFGR_LSESEC_Pos              (4U)
17460 #define RCC_SECCFGR_LSESEC_Msk              (0x1UL << RCC_SECCFGR_LSESEC_Pos)       /*!< 0x00000010 */
17461 #define RCC_SECCFGR_LSESEC                  RCC_SECCFGR_LSESEC_Msk
17462 #define RCC_SECCFGR_SYSCLKSEC_Pos           (5U)
17463 #define RCC_SECCFGR_SYSCLKSEC_Msk           (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos)    /*!< 0x00000020 */
17464 #define RCC_SECCFGR_SYSCLKSEC               RCC_SECCFGR_SYSCLKSEC_Msk
17465 #define RCC_SECCFGR_PRESCSEC_Pos            (6U)
17466 #define RCC_SECCFGR_PRESCSEC_Msk            (0x1UL << RCC_SECCFGR_PRESCSEC_Pos)     /*!< 0x00000040 */
17467 #define RCC_SECCFGR_PRESCSEC                RCC_SECCFGR_PRESCSEC_Msk
17468 #define RCC_SECCFGR_PLL1SEC_Pos             (7U)
17469 #define RCC_SECCFGR_PLL1SEC_Msk             (0x1UL << RCC_SECCFGR_PLL1SEC_Pos)      /*!< 0x00000080 */
17470 #define RCC_SECCFGR_PLL1SEC                 RCC_SECCFGR_PLL1SEC_Msk
17471 #define RCC_SECCFGR_PLL2SEC_Pos             (8U)
17472 #define RCC_SECCFGR_PLL2SEC_Msk             (0x1UL << RCC_SECCFGR_PLL2SEC_Pos)      /*!< 0x00000100 */
17473 #define RCC_SECCFGR_PLL2SEC                 RCC_SECCFGR_PLL2SEC_Msk
17474 #define RCC_SECCFGR_PLL3SEC_Pos             (9U)
17475 #define RCC_SECCFGR_PLL3SEC_Msk             (0x1UL << RCC_SECCFGR_PLL3SEC_Pos)      /*!< 0x00000200 */
17476 #define RCC_SECCFGR_PLL3SEC                 RCC_SECCFGR_PLL3SEC_Msk
17477 #define RCC_SECCFGR_HSI48SEC_Pos            (11U)
17478 #define RCC_SECCFGR_HSI48SEC_Msk            (0x1UL << RCC_SECCFGR_HSI48SEC_Pos)     /*!< 0x00000800 */
17479 #define RCC_SECCFGR_HSI48SEC                RCC_SECCFGR_HSI48SEC_Msk
17480 #define RCC_SECCFGR_RMVFSEC_Pos             (12U)
17481 #define RCC_SECCFGR_RMVFSEC_Msk             (0x1UL << RCC_SECCFGR_RMVFSEC_Pos)      /*!< 0x00001000 */
17482 #define RCC_SECCFGR_RMVFSEC                 RCC_SECCFGR_RMVFSEC_Msk
17483 #define RCC_SECCFGR_CKPERSELSEC_Pos         (13U)
17484 #define RCC_SECCFGR_CKPERSELSEC_Msk         (0x1UL << RCC_SECCFGR_CKPERSELSEC_Pos)  /*!< 0x00002000 */
17485 #define RCC_SECCFGR_CKPERSELSEC             RCC_SECCFGR_CKPERSELSEC_Msk
17486 
17487 /********************  Bit definition for RCC_PRIVCFGR register  **************/
17488 #define RCC_PRIVCFGR_SPRIV_Pos              (0U)
17489 #define RCC_PRIVCFGR_SPRIV_Msk              (0x1UL << RCC_PRIVCFGR_SPRIV_Pos)       /*!< 0x00000001 */
17490 #define RCC_PRIVCFGR_SPRIV                  RCC_PRIVCFGR_SPRIV_Msk
17491 #define RCC_PRIVCFGR_NSPRIV_Pos             (1U)
17492 #define RCC_PRIVCFGR_NSPRIV_Msk             (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos)      /*!< 0x00000002 */
17493 #define RCC_PRIVCFGR_NSPRIV                 RCC_PRIVCFGR_NSPRIV_Msk
17494 
17495 /******************************************************************************/
17496 /*                                                                            */
17497 /*                           Real-Time Clock (RTC)                            */
17498 /*                                                                            */
17499 /******************************************************************************/
17500 /********************  Bits definition for RTC_TR register  *******************/
17501 #define RTC_TR_SU_Pos                       (0U)
17502 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
17503 #define RTC_TR_SU                           RTC_TR_SU_Msk
17504 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
17505 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
17506 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
17507 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
17508 #define RTC_TR_ST_Pos                       (4U)
17509 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
17510 #define RTC_TR_ST                           RTC_TR_ST_Msk
17511 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
17512 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
17513 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
17514 #define RTC_TR_MNU_Pos                      (8U)
17515 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
17516 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
17517 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
17518 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
17519 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
17520 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
17521 #define RTC_TR_MNT_Pos                      (12U)
17522 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
17523 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
17524 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
17525 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
17526 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
17527 #define RTC_TR_HU_Pos                       (16U)
17528 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
17529 #define RTC_TR_HU                           RTC_TR_HU_Msk
17530 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
17531 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
17532 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
17533 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
17534 #define RTC_TR_HT_Pos                       (20U)
17535 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
17536 #define RTC_TR_HT                           RTC_TR_HT_Msk
17537 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
17538 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
17539 #define RTC_TR_PM_Pos                       (22U)
17540 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
17541 #define RTC_TR_PM                           RTC_TR_PM_Msk
17542 
17543 /********************  Bits definition for RTC_DR register  *******************/
17544 #define RTC_DR_DU_Pos                       (0U)
17545 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
17546 #define RTC_DR_DU                           RTC_DR_DU_Msk
17547 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
17548 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
17549 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
17550 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
17551 #define RTC_DR_DT_Pos                       (4U)
17552 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
17553 #define RTC_DR_DT                           RTC_DR_DT_Msk
17554 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
17555 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
17556 #define RTC_DR_MU_Pos                       (8U)
17557 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
17558 #define RTC_DR_MU                           RTC_DR_MU_Msk
17559 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
17560 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
17561 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
17562 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
17563 #define RTC_DR_MT_Pos                       (12U)
17564 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
17565 #define RTC_DR_MT                           RTC_DR_MT_Msk
17566 #define RTC_DR_WDU_Pos                      (13U)
17567 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
17568 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
17569 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
17570 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
17571 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
17572 #define RTC_DR_YU_Pos                       (16U)
17573 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
17574 #define RTC_DR_YU                           RTC_DR_YU_Msk
17575 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
17576 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
17577 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
17578 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
17579 #define RTC_DR_YT_Pos                       (20U)
17580 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
17581 #define RTC_DR_YT                           RTC_DR_YT_Msk
17582 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
17583 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
17584 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
17585 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
17586 
17587 /********************  Bits definition for RTC_SSR register  ******************/
17588 #define RTC_SSR_SS_Pos                      (0U)
17589 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
17590 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
17591 
17592 /********************  Bits definition for RTC_ICSR register  ******************/
17593 #define RTC_ICSR_ALRAWF_Pos                 (0U)
17594 #define RTC_ICSR_ALRAWF_Msk                 (0x1UL << RTC_ICSR_ALRAWF_Pos)          /*!< 0x00000001 */
17595 #define RTC_ICSR_ALRAWF                     RTC_ICSR_ALRAWF_Msk
17596 #define RTC_ICSR_ALRBWF_Pos                 (1U)
17597 #define RTC_ICSR_ALRBWF_Msk                 (0x1UL << RTC_ICSR_ALRBWF_Pos)          /*!< 0x00000002 */
17598 #define RTC_ICSR_ALRBWF                     RTC_ICSR_ALRBWF_Msk
17599 #define RTC_ICSR_WUTWF_Pos                  (2U)
17600 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
17601 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
17602 #define RTC_ICSR_SHPF_Pos                   (3U)
17603 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
17604 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
17605 #define RTC_ICSR_INITS_Pos                  (4U)
17606 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
17607 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
17608 #define RTC_ICSR_RSF_Pos                    (5U)
17609 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
17610 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
17611 #define RTC_ICSR_INITF_Pos                  (6U)
17612 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
17613 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
17614 #define RTC_ICSR_INIT_Pos                   (7U)
17615 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
17616 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
17617 #define RTC_ICSR_BIN_Pos                    (8U)
17618 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
17619 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
17620 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
17621 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
17622 #define RTC_ICSR_BCDU_Pos                   (10U)
17623 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
17624 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
17625 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
17626 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
17627 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
17628 #define RTC_ICSR_RECALPF_Pos                (16U)
17629 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
17630 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
17631 
17632 /********************  Bits definition for RTC_PRER register  *****************/
17633 #define RTC_PRER_PREDIV_S_Pos               (0U)
17634 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
17635 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
17636 #define RTC_PRER_PREDIV_A_Pos               (16U)
17637 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
17638 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
17639 
17640 /********************  Bits definition for RTC_WUTR register  *****************/
17641 #define RTC_WUTR_WUT_Pos                    (0U)
17642 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
17643 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
17644 #define RTC_WUTR_WUTOCLR_Pos                (16U)
17645 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
17646 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
17647 
17648 /********************  Bits definition for RTC_CR register  *******************/
17649 #define RTC_CR_WUCKSEL_Pos                  (0U)
17650 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
17651 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
17652 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
17653 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
17654 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
17655 #define RTC_CR_TSEDGE_Pos                   (3U)
17656 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
17657 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
17658 #define RTC_CR_REFCKON_Pos                  (4U)
17659 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
17660 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
17661 #define RTC_CR_BYPSHAD_Pos                  (5U)
17662 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
17663 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
17664 #define RTC_CR_FMT_Pos                      (6U)
17665 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
17666 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
17667 #define RTC_CR_SSRUIE_Pos                   (7U)
17668 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
17669 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
17670 #define RTC_CR_ALRAE_Pos                    (8U)
17671 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
17672 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
17673 #define RTC_CR_ALRBE_Pos                    (9U)
17674 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
17675 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
17676 #define RTC_CR_WUTE_Pos                     (10U)
17677 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
17678 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
17679 #define RTC_CR_TSE_Pos                      (11U)
17680 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
17681 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
17682 #define RTC_CR_ALRAIE_Pos                   (12U)
17683 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
17684 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
17685 #define RTC_CR_ALRBIE_Pos                   (13U)
17686 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
17687 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
17688 #define RTC_CR_WUTIE_Pos                    (14U)
17689 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
17690 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
17691 #define RTC_CR_TSIE_Pos                     (15U)
17692 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
17693 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
17694 #define RTC_CR_ADD1H_Pos                    (16U)
17695 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
17696 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
17697 #define RTC_CR_SUB1H_Pos                    (17U)
17698 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
17699 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
17700 #define RTC_CR_BKP_Pos                      (18U)
17701 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
17702 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
17703 #define RTC_CR_COSEL_Pos                    (19U)
17704 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
17705 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
17706 #define RTC_CR_POL_Pos                      (20U)
17707 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
17708 #define RTC_CR_POL                          RTC_CR_POL_Msk
17709 #define RTC_CR_OSEL_Pos                     (21U)
17710 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
17711 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
17712 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
17713 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
17714 #define RTC_CR_COE_Pos                      (23U)
17715 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
17716 #define RTC_CR_COE                          RTC_CR_COE_Msk
17717 #define RTC_CR_ITSE_Pos                     (24U)
17718 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
17719 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
17720 #define RTC_CR_TAMPTS_Pos                   (25U)
17721 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
17722 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
17723 #define RTC_CR_TAMPOE_Pos                   (26U)
17724 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
17725 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
17726 #define RTC_CR_ALRAFCLR_Pos                 (27U)
17727 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
17728 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
17729 #define RTC_CR_ALRBFCLR_Pos                 (28U)
17730 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
17731 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
17732 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
17733 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
17734 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
17735 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
17736 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
17737 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
17738 #define RTC_CR_OUT2EN_Pos                   (31U)
17739 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
17740 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
17741 
17742 /********************  Bits definition for RTC_PRIVCFGR register  *****************/
17743 #define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
17744 #define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
17745 #define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
17746 #define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
17747 #define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
17748 #define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
17749 #define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
17750 #define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
17751 #define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
17752 #define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
17753 #define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
17754 #define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
17755 #define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
17756 #define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
17757 #define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
17758 #define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
17759 #define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
17760 #define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
17761 #define RTC_PRIVCFGR_PRIV_Pos               (15U)
17762 #define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
17763 #define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
17764 
17765 /********************  Bits definition for RTC_SECCFGR register  ******************/
17766 #define RTC_SECCFGR_ALRASEC_Pos             (0U)
17767 #define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
17768 #define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
17769 #define RTC_SECCFGR_ALRBSEC_Pos             (1U)
17770 #define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
17771 #define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
17772 #define RTC_SECCFGR_WUTSEC_Pos              (2U)
17773 #define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
17774 #define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
17775 #define RTC_SECCFGR_TSSEC_Pos               (3U)
17776 #define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
17777 #define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
17778 #define RTC_SECCFGR_CALSEC_Pos              (13U)
17779 #define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
17780 #define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
17781 #define RTC_SECCFGR_INITSEC_Pos             (14U)
17782 #define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
17783 #define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
17784 #define RTC_SECCFGR_SEC_Pos                 (15U)
17785 #define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
17786 #define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
17787 
17788 /********************  Bits definition for RTC_WPR register  ******************/
17789 #define RTC_WPR_KEY_Pos                     (0U)
17790 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
17791 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
17792 
17793 /********************  Bits definition for RTC_CALR register  *****************/
17794 #define RTC_CALR_CALM_Pos                   (0U)
17795 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
17796 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
17797 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
17798 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
17799 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
17800 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
17801 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
17802 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
17803 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
17804 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
17805 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
17806 #define RTC_CALR_LPCAL_Pos                  (12U)
17807 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
17808 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
17809 #define RTC_CALR_CALW16_Pos                 (13U)
17810 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
17811 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
17812 #define RTC_CALR_CALW8_Pos                  (14U)
17813 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
17814 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
17815 #define RTC_CALR_CALP_Pos                   (15U)
17816 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
17817 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
17818 
17819 /********************  Bits definition for RTC_SHIFTR register  ***************/
17820 #define RTC_SHIFTR_SUBFS_Pos                (0U)
17821 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
17822 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
17823 #define RTC_SHIFTR_ADD1S_Pos                (31U)
17824 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
17825 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
17826 
17827 /********************  Bits definition for RTC_TSTR register  *****************/
17828 #define RTC_TSTR_SU_Pos                     (0U)
17829 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
17830 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
17831 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
17832 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
17833 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
17834 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
17835 #define RTC_TSTR_ST_Pos                     (4U)
17836 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
17837 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
17838 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
17839 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
17840 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
17841 #define RTC_TSTR_MNU_Pos                    (8U)
17842 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
17843 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
17844 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
17845 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
17846 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
17847 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
17848 #define RTC_TSTR_MNT_Pos                    (12U)
17849 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
17850 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
17851 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
17852 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
17853 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
17854 #define RTC_TSTR_HU_Pos                     (16U)
17855 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
17856 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
17857 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
17858 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
17859 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
17860 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
17861 #define RTC_TSTR_HT_Pos                     (20U)
17862 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
17863 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
17864 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
17865 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
17866 #define RTC_TSTR_PM_Pos                     (22U)
17867 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
17868 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
17869 
17870 /********************  Bits definition for RTC_TSDR register  *****************/
17871 #define RTC_TSDR_DU_Pos                     (0U)
17872 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
17873 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
17874 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
17875 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
17876 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
17877 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
17878 #define RTC_TSDR_DT_Pos                     (4U)
17879 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
17880 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
17881 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
17882 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
17883 #define RTC_TSDR_MU_Pos                     (8U)
17884 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
17885 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
17886 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
17887 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
17888 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
17889 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
17890 #define RTC_TSDR_MT_Pos                     (12U)
17891 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
17892 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
17893 #define RTC_TSDR_WDU_Pos                    (13U)
17894 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
17895 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
17896 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
17897 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
17898 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
17899 
17900 /********************  Bits definition for RTC_TSSSR register  ****************/
17901 #define RTC_TSSSR_SS_Pos                    (0U)
17902 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
17903 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
17904 
17905 /********************  Bits definition for RTC_ALRMAR register  ***************/
17906 #define RTC_ALRMAR_SU_Pos                   (0U)
17907 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
17908 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
17909 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
17910 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
17911 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
17912 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
17913 #define RTC_ALRMAR_ST_Pos                   (4U)
17914 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
17915 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
17916 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
17917 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
17918 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
17919 #define RTC_ALRMAR_MSK1_Pos                 (7U)
17920 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
17921 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
17922 #define RTC_ALRMAR_MNU_Pos                  (8U)
17923 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
17924 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
17925 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
17926 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
17927 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
17928 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
17929 #define RTC_ALRMAR_MNT_Pos                  (12U)
17930 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
17931 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
17932 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
17933 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
17934 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
17935 #define RTC_ALRMAR_MSK2_Pos                 (15U)
17936 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
17937 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
17938 #define RTC_ALRMAR_HU_Pos                   (16U)
17939 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
17940 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
17941 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
17942 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
17943 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
17944 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
17945 #define RTC_ALRMAR_HT_Pos                   (20U)
17946 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
17947 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
17948 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
17949 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
17950 #define RTC_ALRMAR_PM_Pos                   (22U)
17951 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
17952 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
17953 #define RTC_ALRMAR_MSK3_Pos                 (23U)
17954 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
17955 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
17956 #define RTC_ALRMAR_DU_Pos                   (24U)
17957 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
17958 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
17959 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
17960 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
17961 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
17962 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
17963 #define RTC_ALRMAR_DT_Pos                   (28U)
17964 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
17965 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
17966 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
17967 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
17968 #define RTC_ALRMAR_WDSEL_Pos                (30U)
17969 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
17970 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
17971 #define RTC_ALRMAR_MSK4_Pos                 (31U)
17972 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
17973 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
17974 
17975 /********************  Bits definition for RTC_ALRMASSR register  *************/
17976 #define RTC_ALRMASSR_SS_Pos                 (0U)
17977 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
17978 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
17979 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
17980 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
17981 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
17982 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
17983 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
17984 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
17985 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
17986 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
17987 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
17988 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
17989 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
17990 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
17991 
17992 /********************  Bits definition for RTC_ALRMBR register  ***************/
17993 #define RTC_ALRMBR_SU_Pos                   (0U)
17994 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
17995 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
17996 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
17997 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
17998 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
17999 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
18000 #define RTC_ALRMBR_ST_Pos                   (4U)
18001 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
18002 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
18003 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
18004 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
18005 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
18006 #define RTC_ALRMBR_MSK1_Pos                 (7U)
18007 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
18008 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
18009 #define RTC_ALRMBR_MNU_Pos                  (8U)
18010 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
18011 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
18012 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
18013 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
18014 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
18015 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
18016 #define RTC_ALRMBR_MNT_Pos                  (12U)
18017 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
18018 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
18019 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
18020 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
18021 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
18022 #define RTC_ALRMBR_MSK2_Pos                 (15U)
18023 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
18024 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
18025 #define RTC_ALRMBR_HU_Pos                   (16U)
18026 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
18027 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
18028 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
18029 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
18030 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
18031 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
18032 #define RTC_ALRMBR_HT_Pos                   (20U)
18033 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
18034 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
18035 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
18036 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
18037 #define RTC_ALRMBR_PM_Pos                   (22U)
18038 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
18039 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
18040 #define RTC_ALRMBR_MSK3_Pos                 (23U)
18041 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
18042 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
18043 #define RTC_ALRMBR_DU_Pos                   (24U)
18044 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
18045 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
18046 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
18047 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
18048 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
18049 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
18050 #define RTC_ALRMBR_DT_Pos                   (28U)
18051 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
18052 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
18053 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
18054 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
18055 #define RTC_ALRMBR_WDSEL_Pos                (30U)
18056 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
18057 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
18058 #define RTC_ALRMBR_MSK4_Pos                 (31U)
18059 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
18060 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
18061 
18062 /********************  Bits definition for RTC_ALRMBSSR register  *************/
18063 #define RTC_ALRMBSSR_SS_Pos                 (0U)
18064 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
18065 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
18066 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
18067 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
18068 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
18069 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
18070 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
18071 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
18072 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
18073 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
18074 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
18075 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
18076 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
18077 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
18078 
18079 /********************  Bits definition for RTC_SR register  *******************/
18080 #define RTC_SR_ALRAF_Pos                    (0U)
18081 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
18082 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
18083 #define RTC_SR_ALRBF_Pos                    (1U)
18084 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
18085 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
18086 #define RTC_SR_WUTF_Pos                     (2U)
18087 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
18088 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
18089 #define RTC_SR_TSF_Pos                      (3U)
18090 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
18091 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
18092 #define RTC_SR_TSOVF_Pos                    (4U)
18093 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
18094 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
18095 #define RTC_SR_ITSF_Pos                     (5U)
18096 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
18097 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
18098 #define RTC_SR_SSRUF_Pos                    (6U)
18099 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
18100 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
18101 
18102 /********************  Bits definition for RTC_MISR register  *****************/
18103 #define RTC_MISR_ALRAMF_Pos                 (0U)
18104 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
18105 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
18106 #define RTC_MISR_ALRBMF_Pos                 (1U)
18107 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
18108 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
18109 #define RTC_MISR_WUTMF_Pos                  (2U)
18110 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
18111 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
18112 #define RTC_MISR_TSMF_Pos                   (3U)
18113 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
18114 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
18115 #define RTC_MISR_TSOVMF_Pos                 (4U)
18116 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
18117 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
18118 #define RTC_MISR_ITSMF_Pos                  (5U)
18119 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
18120 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
18121 #define RTC_MISR_SSRUMF_Pos                 (6U)
18122 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
18123 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
18124 
18125 /********************  Bits definition for RTC_SMISR register  *****************/
18126 #define RTC_SMISR_ALRAMF_Pos                (0U)
18127 #define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
18128 #define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
18129 #define RTC_SMISR_ALRBMF_Pos                (1U)
18130 #define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
18131 #define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
18132 #define RTC_SMISR_WUTMF_Pos                 (2U)
18133 #define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
18134 #define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
18135 #define RTC_SMISR_TSMF_Pos                  (3U)
18136 #define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
18137 #define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
18138 #define RTC_SMISR_TSOVMF_Pos                (4U)
18139 #define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
18140 #define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
18141 #define RTC_SMISR_ITSMF_Pos                 (5U)
18142 #define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
18143 #define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
18144 #define RTC_SMISR_SSRUMF_Pos                (6U)
18145 #define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
18146 #define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
18147 
18148 /********************  Bits definition for RTC_SCR register  ******************/
18149 #define RTC_SCR_CALRAF_Pos                  (0U)
18150 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
18151 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
18152 #define RTC_SCR_CALRBF_Pos                  (1U)
18153 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
18154 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
18155 #define RTC_SCR_CWUTF_Pos                   (2U)
18156 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
18157 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
18158 #define RTC_SCR_CTSF_Pos                    (3U)
18159 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
18160 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
18161 #define RTC_SCR_CTSOVF_Pos                  (4U)
18162 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
18163 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
18164 #define RTC_SCR_CITSF_Pos                   (5U)
18165 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
18166 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
18167 #define RTC_SCR_CSSRUF_Pos                  (6U)
18168 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
18169 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
18170 
18171 /********************  Bits definition for RTC_OR register  ******************/
18172 #define RTC_OR_OUT2_RMP_Pos                 (0U)
18173 #define RTC_OR_OUT2_RMP_Msk                 (0x1UL << RTC_OR_OUT2_RMP_Pos)         /*!< 0x00000001 */
18174 #define RTC_OR_OUT2_RMP                     RTC_OR_OUT2_RMP_Msk
18175 
18176 /********************  Bits definition for RTC_ALRABINR register  ******************/
18177 #define RTC_ALRABINR_SS_Pos                 (0U)
18178 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
18179 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
18180 
18181 /********************  Bits definition for RTC_ALRBBINR register  ******************/
18182 #define RTC_ALRBBINR_SS_Pos                 (0U)
18183 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
18184 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
18185 
18186 /******************************************************************************/
18187 /*                                                                            */
18188 /*                     Tamper and backup register (TAMP)                      */
18189 /*                                                                            */
18190 /******************************************************************************/
18191 /********************  Bits definition for TAMP_CR1 register  *****************/
18192 #define TAMP_CR1_TAMP1E_Pos                 (0U)
18193 #define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
18194 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
18195 #define TAMP_CR1_TAMP2E_Pos                 (1U)
18196 #define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
18197 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
18198 #define TAMP_CR1_TAMP3E_Pos                 (2U)
18199 #define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
18200 #define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
18201 #define TAMP_CR1_TAMP4E_Pos                 (3U)
18202 #define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
18203 #define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
18204 #define TAMP_CR1_TAMP5E_Pos                 (4U)
18205 #define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
18206 #define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
18207 #define TAMP_CR1_TAMP6E_Pos                 (5U)
18208 #define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
18209 #define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
18210 #define TAMP_CR1_TAMP7E_Pos                 (6U)
18211 #define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
18212 #define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
18213 #define TAMP_CR1_TAMP8E_Pos                 (7U)
18214 #define TAMP_CR1_TAMP8E_Msk                 (0x1UL << TAMP_CR1_TAMP8E_Pos)          /*!< 0x00000080 */
18215 #define TAMP_CR1_TAMP8E                     TAMP_CR1_TAMP8E_Msk
18216 #define TAMP_CR1_ITAMP1E_Pos                (16U)
18217 #define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
18218 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
18219 #define TAMP_CR1_ITAMP2E_Pos                (17U)
18220 #define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
18221 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
18222 #define TAMP_CR1_ITAMP3E_Pos                (18U)
18223 #define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
18224 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
18225 #define TAMP_CR1_ITAMP4E_Pos                (19U)
18226 #define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
18227 #define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
18228 #define TAMP_CR1_ITAMP5E_Pos                (20U)
18229 #define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
18230 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
18231 #define TAMP_CR1_ITAMP6E_Pos                (21U)
18232 #define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
18233 #define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
18234 #define TAMP_CR1_ITAMP7E_Pos                (22U)
18235 #define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
18236 #define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
18237 #define TAMP_CR1_ITAMP8E_Pos                (23U)
18238 #define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
18239 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
18240 #define TAMP_CR1_ITAMP9E_Pos                (24U)
18241 #define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
18242 #define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
18243 #define TAMP_CR1_ITAMP11E_Pos               (26U)
18244 #define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
18245 #define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
18246 #define TAMP_CR1_ITAMP12E_Pos               (27U)
18247 #define TAMP_CR1_ITAMP12E_Msk               (0x1UL << TAMP_CR1_ITAMP12E_Pos)        /*!< 0x08000000 */
18248 #define TAMP_CR1_ITAMP12E                   TAMP_CR1_ITAMP12E_Msk
18249 #define TAMP_CR1_ITAMP13E_Pos               (28U)
18250 #define TAMP_CR1_ITAMP13E_Msk               (0x1UL << TAMP_CR1_ITAMP13E_Pos)        /*!< 0x10000000 */
18251 #define TAMP_CR1_ITAMP13E                   TAMP_CR1_ITAMP13E_Msk
18252 #define TAMP_CR1_ITAMP15E_Pos               (30U)
18253 #define TAMP_CR1_ITAMP15E_Msk               (0x1UL << TAMP_CR1_ITAMP15E_Pos)        /*!< 0x40000000 */
18254 #define TAMP_CR1_ITAMP15E                   TAMP_CR1_ITAMP15E_Msk
18255 
18256 /********************  Bits definition for TAMP_CR2 register  *****************/
18257 #define TAMP_CR2_TAMP1NOERASE_Pos           (0U)
18258 #define TAMP_CR2_TAMP1NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)    /*!< 0x00000001 */
18259 #define TAMP_CR2_TAMP1NOERASE               TAMP_CR2_TAMP1NOERASE_Msk
18260 #define TAMP_CR2_TAMP2NOERASE_Pos           (1U)
18261 #define TAMP_CR2_TAMP2NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)    /*!< 0x00000002 */
18262 #define TAMP_CR2_TAMP2NOERASE               TAMP_CR2_TAMP2NOERASE_Msk
18263 #define TAMP_CR2_TAMP3NOERASE_Pos           (2U)
18264 #define TAMP_CR2_TAMP3NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)    /*!< 0x00000004 */
18265 #define TAMP_CR2_TAMP3NOERASE               TAMP_CR2_TAMP3NOERASE_Msk
18266 #define TAMP_CR2_TAMP4NOERASE_Pos           (3U)
18267 #define TAMP_CR2_TAMP4NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos)    /*!< 0x00000008 */
18268 #define TAMP_CR2_TAMP4NOERASE               TAMP_CR2_TAMP4NOERASE_Msk
18269 #define TAMP_CR2_TAMP5NOERASE_Pos           (4U)
18270 #define TAMP_CR2_TAMP5NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos)    /*!< 0x00000010 */
18271 #define TAMP_CR2_TAMP5NOERASE               TAMP_CR2_TAMP5NOERASE_Msk
18272 #define TAMP_CR2_TAMP6NOERASE_Pos           (5U)
18273 #define TAMP_CR2_TAMP6NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos)    /*!< 0x00000020 */
18274 #define TAMP_CR2_TAMP6NOERASE               TAMP_CR2_TAMP6NOERASE_Msk
18275 #define TAMP_CR2_TAMP7NOERASE_Pos           (6U)
18276 #define TAMP_CR2_TAMP7NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos)    /*!< 0x00000040 */
18277 #define TAMP_CR2_TAMP7NOERASE               TAMP_CR2_TAMP7NOERASE_Msk
18278 #define TAMP_CR2_TAMP8NOERASE_Pos           (7U)
18279 #define TAMP_CR2_TAMP8NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos)    /*!< 0x00000080 */
18280 #define TAMP_CR2_TAMP8NOERASE               TAMP_CR2_TAMP8NOERASE_Msk
18281 #define TAMP_CR2_TAMP1MSK_Pos               (16U)
18282 #define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
18283 #define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
18284 #define TAMP_CR2_TAMP2MSK_Pos               (17U)
18285 #define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
18286 #define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
18287 #define TAMP_CR2_TAMP3MSK_Pos               (18U)
18288 #define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
18289 #define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
18290 #define TAMP_CR2_BKBLOCK_Pos                (22U)
18291 #define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
18292 #define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
18293 #define TAMP_CR2_BKERASE_Pos                (23U)
18294 #define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
18295 #define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
18296 #define TAMP_CR2_TAMP1TRG_Pos               (24U)
18297 #define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
18298 #define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
18299 #define TAMP_CR2_TAMP2TRG_Pos               (25U)
18300 #define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
18301 #define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
18302 #define TAMP_CR2_TAMP3TRG_Pos               (26U)
18303 #define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
18304 #define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
18305 #define TAMP_CR2_TAMP4TRG_Pos               (27U)
18306 #define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
18307 #define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
18308 #define TAMP_CR2_TAMP5TRG_Pos               (28U)
18309 #define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
18310 #define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
18311 #define TAMP_CR2_TAMP6TRG_Pos               (29U)
18312 #define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
18313 #define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
18314 #define TAMP_CR2_TAMP7TRG_Pos               (30U)
18315 #define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
18316 #define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
18317 #define TAMP_CR2_TAMP8TRG_Pos               (31U)
18318 #define TAMP_CR2_TAMP8TRG_Msk               (0x1UL << TAMP_CR2_TAMP8TRG_Pos)        /*!< 0x02000000 */
18319 #define TAMP_CR2_TAMP8TRG                   TAMP_CR2_TAMP8TRG_Msk
18320 
18321 /********************  Bits definition for TAMP_CR3 register  *****************/
18322 #define TAMP_CR3_ITAMP1NOER_Pos             (0U)
18323 #define TAMP_CR3_ITAMP1NOER_Msk             (0x1UL << TAMP_CR3_ITAMP1NOER_Pos)      /*!< 0x00000001 */
18324 #define TAMP_CR3_ITAMP1NOER                 TAMP_CR3_ITAMP1NOER_Msk
18325 #define TAMP_CR3_ITAMP2NOER_Pos             (1U)
18326 #define TAMP_CR3_ITAMP2NOER_Msk             (0x1UL << TAMP_CR3_ITAMP2NOER_Pos)      /*!< 0x00000002 */
18327 #define TAMP_CR3_ITAMP2NOER                 TAMP_CR3_ITAMP2NOER_Msk
18328 #define TAMP_CR3_ITAMP3NOER_Pos             (2U)
18329 #define TAMP_CR3_ITAMP3NOER_Msk             (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)      /*!< 0x00000004 */
18330 #define TAMP_CR3_ITAMP3NOER                 TAMP_CR3_ITAMP3NOER_Msk
18331 #define TAMP_CR3_ITAMP4NOER_Pos             (3U)
18332 #define TAMP_CR3_ITAMP4NOER_Msk             (0x1UL << TAMP_CR3_ITAMP4NOER_Pos)      /*!< 0x00000008 */
18333 #define TAMP_CR3_ITAMP4NOER                 TAMP_CR3_ITAMP4NOER_Msk
18334 #define TAMP_CR3_ITAMP5NOER_Pos             (4U)
18335 #define TAMP_CR3_ITAMP5NOER_Msk             (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)      /*!< 0x00000010 */
18336 #define TAMP_CR3_ITAMP5NOER                 TAMP_CR3_ITAMP5NOER_Msk
18337 #define TAMP_CR3_ITAMP6NOER_Pos             (5U)
18338 #define TAMP_CR3_ITAMP6NOER_Msk             (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)      /*!< 0x00000020 */
18339 #define TAMP_CR3_ITAMP6NOER                 TAMP_CR3_ITAMP6NOER_Msk
18340 #define TAMP_CR3_ITAMP7NOER_Pos             (6U)
18341 #define TAMP_CR3_ITAMP7NOER_Msk             (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)      /*!< 0x00000040 */
18342 #define TAMP_CR3_ITAMP7NOER                 TAMP_CR3_ITAMP7NOER_Msk
18343 #define TAMP_CR3_ITAMP8NOER_Pos             (7U)
18344 #define TAMP_CR3_ITAMP8NOER_Msk             (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)      /*!< 0x00000080 */
18345 #define TAMP_CR3_ITAMP8NOER                 TAMP_CR3_ITAMP8NOER_Msk
18346 #define TAMP_CR3_ITAMP9NOER_Pos             (8U)
18347 #define TAMP_CR3_ITAMP9NOER_Msk             (0x1UL << TAMP_CR3_ITAMP9NOER_Pos)      /*!< 0x00000100 */
18348 #define TAMP_CR3_ITAMP9NOER                 TAMP_CR3_ITAMP9NOER_Msk
18349 #define TAMP_CR3_ITAMP11NOER_Pos            (10U)
18350 #define TAMP_CR3_ITAMP11NOER_Msk            (0x1UL << TAMP_CR3_ITAMP11NOER_Pos)     /*!< 0x00000400 */
18351 #define TAMP_CR3_ITAMP11NOER                TAMP_CR3_ITAMP11NOER_Msk
18352 #define TAMP_CR3_ITAMP12NOER_Pos            (11U)
18353 #define TAMP_CR3_ITAMP12NOER_Msk            (0x1UL << TAMP_CR3_ITAMP12NOER_Pos)     /*!< 0x00000800 */
18354 #define TAMP_CR3_ITAMP12NOER                TAMP_CR3_ITAMP12NOER_Msk
18355 #define TAMP_CR3_ITAMP13NOER_Pos            (12U)
18356 #define TAMP_CR3_ITAMP13NOER_Msk            (0x1UL << TAMP_CR3_ITAMP13NOER_Pos)     /*!< 0x00001000 */
18357 #define TAMP_CR3_ITAMP13NOER                TAMP_CR3_ITAMP13NOER_Msk
18358 #define TAMP_CR3_ITAMP15NOER_Pos            (14U)
18359 #define TAMP_CR3_ITAMP15NOER_Msk            (0x1UL << TAMP_CR3_ITAMP15NOER_Pos)     /*!< 0x00004000 */
18360 #define TAMP_CR3_ITAMP15NOER                TAMP_CR3_ITAMP15NOER_Msk
18361 
18362 /********************  Bits definition for TAMP_FLTCR register  ***************/
18363 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
18364 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
18365 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
18366 #define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
18367 #define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
18368 #define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
18369 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
18370 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
18371 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
18372 #define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
18373 #define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
18374 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
18375 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
18376 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
18377 #define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
18378 #define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
18379 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
18380 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
18381 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
18382 
18383 /********************  Bits definition for TAMP_ATCR1 register  ***************/
18384 #define TAMP_ATCR1_TAMP1AM_Pos              (0U)
18385 #define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
18386 #define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
18387 #define TAMP_ATCR1_TAMP2AM_Pos              (1U)
18388 #define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
18389 #define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
18390 #define TAMP_ATCR1_TAMP3AM_Pos              (2U)
18391 #define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
18392 #define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
18393 #define TAMP_ATCR1_TAMP4AM_Pos              (3U)
18394 #define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
18395 #define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
18396 #define TAMP_ATCR1_TAMP5AM_Pos              (4U)
18397 #define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
18398 #define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
18399 #define TAMP_ATCR1_TAMP6AM_Pos              (5U)
18400 #define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
18401 #define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
18402 #define TAMP_ATCR1_TAMP7AM_Pos              (6U)
18403 #define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
18404 #define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
18405 #define TAMP_ATCR1_TAMP8AM_Pos              (7U)
18406 #define TAMP_ATCR1_TAMP8AM_Msk              (0x1UL << TAMP_ATCR1_TAMP8AM_Pos)       /*!< 0x00000080 */
18407 #define TAMP_ATCR1_TAMP8AM                  TAMP_ATCR1_TAMP8AM_Msk
18408 #define TAMP_ATCR1_ATOSEL1_Pos              (8U)
18409 #define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
18410 #define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
18411 #define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
18412 #define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
18413 #define TAMP_ATCR1_ATOSEL2_Pos              (10U)
18414 #define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
18415 #define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
18416 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
18417 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
18418 #define TAMP_ATCR1_ATOSEL3_Pos              (12U)
18419 #define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
18420 #define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
18421 #define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
18422 #define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
18423 #define TAMP_ATCR1_ATOSEL4_Pos              (14U)
18424 #define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
18425 #define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
18426 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
18427 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
18428 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
18429 #define TAMP_ATCR1_ATCKSEL_Msk              (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00070000 */
18430 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
18431 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
18432 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
18433 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
18434 #define TAMP_ATCR1_ATPER_Pos                (24U)
18435 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
18436 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
18437 #define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
18438 #define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
18439 #define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
18440 #define TAMP_ATCR1_ATOSHARE_Pos             (30U)
18441 #define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
18442 #define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
18443 #define TAMP_ATCR1_FLTEN_Pos                (31U)
18444 #define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
18445 #define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
18446 
18447 /********************  Bits definition for TAMP_ATSEEDR register  ******************/
18448 #define TAMP_ATSEEDR_SEED_Pos               (0U)
18449 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
18450 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
18451 
18452 /********************  Bits definition for TAMP_ATOR register  ******************/
18453 #define TAMP_ATOR_PRNG_Pos                  (0U)
18454 #define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)            /*!< 0x000000FF */
18455 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
18456 #define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
18457 #define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
18458 #define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
18459 #define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
18460 #define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
18461 #define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
18462 #define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
18463 #define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
18464 #define TAMP_ATOR_SEEDF_Pos                 (14U)
18465 #define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
18466 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
18467 #define TAMP_ATOR_INITS_Pos                 (15U)
18468 #define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
18469 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
18470 
18471 /********************  Bits definition for TAMP_ATCR2 register  ***************/
18472 #define TAMP_ATCR2_ATOSEL1_Pos              (8U)
18473 #define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
18474 #define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
18475 #define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
18476 #define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
18477 #define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
18478 #define TAMP_ATCR2_ATOSEL2_Pos              (11U)
18479 #define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
18480 #define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
18481 #define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
18482 #define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
18483 #define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
18484 #define TAMP_ATCR2_ATOSEL3_Pos              (14U)
18485 #define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
18486 #define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
18487 #define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
18488 #define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
18489 #define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
18490 #define TAMP_ATCR2_ATOSEL4_Pos              (17U)
18491 #define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
18492 #define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
18493 #define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
18494 #define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
18495 #define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
18496 #define TAMP_ATCR2_ATOSEL5_Pos              (20U)
18497 #define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
18498 #define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
18499 #define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
18500 #define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
18501 #define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
18502 #define TAMP_ATCR2_ATOSEL6_Pos              (23U)
18503 #define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
18504 #define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
18505 #define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
18506 #define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
18507 #define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
18508 #define TAMP_ATCR2_ATOSEL7_Pos              (26U)
18509 #define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
18510 #define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
18511 #define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
18512 #define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
18513 #define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
18514 #define TAMP_ATCR2_ATOSEL8_Pos              (29U)
18515 #define TAMP_ATCR2_ATOSEL8_Msk              (0x7UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0xE0000000 */
18516 #define TAMP_ATCR2_ATOSEL8                  TAMP_ATCR2_ATOSEL8_Msk
18517 #define TAMP_ATCR2_ATOSEL8_0                (0x1UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x20000000 */
18518 #define TAMP_ATCR2_ATOSEL8_1                (0x2UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x40000000 */
18519 #define TAMP_ATCR2_ATOSEL8_2                (0x4UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x80000000 */
18520 
18521 /********************  Bits definition for TAMP_SECCFGR register  *************/
18522 #define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
18523 #define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)     /*!< 0x000000FF */
18524 #define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
18525 #define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
18526 #define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
18527 #define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
18528 #define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
18529 #define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
18530 #define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
18531 #define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
18532 #define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
18533 #define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
18534 #define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)       /*!< 0x00008000 */
18535 #define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
18536 #define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
18537 #define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)      /*!< 0x00FF0000 */
18538 #define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
18539 #define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
18540 #define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
18541 #define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
18542 #define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
18543 #define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
18544 #define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
18545 #define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
18546 #define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
18547 #define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
18548 #define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
18549 #define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
18550 #define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
18551 #define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
18552 #define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
18553 
18554 /********************  Bits definition for TAMP_PRIVCFGR register  ************/
18555 #define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
18556 #define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)     /*!< 0x20000000 */
18557 #define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
18558 #define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
18559 #define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)    /*!< 0x20000000 */
18560 #define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
18561 #define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
18562 #define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)     /*!< 0x40000000 */
18563 #define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
18564 #define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
18565 #define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
18566 #define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
18567 
18568 /********************  Bits definition for TAMP_IER register  *****************/
18569 #define TAMP_IER_TAMP1IE_Pos                (0U)
18570 #define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
18571 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
18572 #define TAMP_IER_TAMP2IE_Pos                (1U)
18573 #define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
18574 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
18575 #define TAMP_IER_TAMP3IE_Pos                (2U)
18576 #define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
18577 #define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
18578 #define TAMP_IER_TAMP4IE_Pos                (3U)
18579 #define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
18580 #define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
18581 #define TAMP_IER_TAMP5IE_Pos                (4U)
18582 #define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
18583 #define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
18584 #define TAMP_IER_TAMP6IE_Pos                (5U)
18585 #define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
18586 #define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
18587 #define TAMP_IER_TAMP7IE_Pos                (6U)
18588 #define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
18589 #define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
18590 #define TAMP_IER_TAMP8IE_Pos                (7U)
18591 #define TAMP_IER_TAMP8IE_Msk                (0x1UL << TAMP_IER_TAMP8IE_Pos)         /*!< 0x00000080 */
18592 #define TAMP_IER_TAMP8IE                    TAMP_IER_TAMP8IE_Msk
18593 #define TAMP_IER_ITAMP1IE_Pos               (16U)
18594 #define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
18595 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
18596 #define TAMP_IER_ITAMP2IE_Pos               (17U)
18597 #define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
18598 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
18599 #define TAMP_IER_ITAMP3IE_Pos               (18U)
18600 #define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
18601 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
18602 #define TAMP_IER_ITAMP4IE_Pos               (19U)
18603 #define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
18604 #define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
18605 #define TAMP_IER_ITAMP5IE_Pos               (20U)
18606 #define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
18607 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
18608 #define TAMP_IER_ITAMP6IE_Pos               (21U)
18609 #define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
18610 #define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
18611 #define TAMP_IER_ITAMP7IE_Pos               (22U)
18612 #define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
18613 #define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
18614 #define TAMP_IER_ITAMP8IE_Pos               (23U)
18615 #define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
18616 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
18617 #define TAMP_IER_ITAMP9IE_Pos               (24U)
18618 #define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
18619 #define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
18620 #define TAMP_IER_ITAMP11IE_Pos              (26U)
18621 #define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
18622 #define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
18623 #define TAMP_IER_ITAMP12IE_Pos              (27U)
18624 #define TAMP_IER_ITAMP12IE_Msk              (0x1UL << TAMP_IER_ITAMP12IE_Pos)       /*!< 0x08000000 */
18625 #define TAMP_IER_ITAMP12IE                  TAMP_IER_ITAMP12IE_Msk
18626 #define TAMP_IER_ITAMP13IE_Pos              (28U)
18627 #define TAMP_IER_ITAMP13IE_Msk              (0x1UL << TAMP_IER_ITAMP13IE_Pos)       /*!< 0x10000000 */
18628 #define TAMP_IER_ITAMP13IE                  TAMP_IER_ITAMP13IE_Msk
18629 #define TAMP_IER_ITAMP15IE_Pos              (30U)
18630 #define TAMP_IER_ITAMP15IE_Msk              (0x1UL << TAMP_IER_ITAMP15IE_Pos)       /*!< 0x40000000 */
18631 #define TAMP_IER_ITAMP15IE                  TAMP_IER_ITAMP15IE_Msk
18632 
18633 /********************  Bits definition for TAMP_SR register  *****************/
18634 #define TAMP_SR_TAMP1F_Pos                  (0U)
18635 #define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
18636 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
18637 #define TAMP_SR_TAMP2F_Pos                  (1U)
18638 #define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
18639 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
18640 #define TAMP_SR_TAMP3F_Pos                  (2U)
18641 #define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
18642 #define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
18643 #define TAMP_SR_TAMP4F_Pos                  (3U)
18644 #define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
18645 #define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
18646 #define TAMP_SR_TAMP5F_Pos                  (4U)
18647 #define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
18648 #define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
18649 #define TAMP_SR_TAMP6F_Pos                  (5U)
18650 #define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
18651 #define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
18652 #define TAMP_SR_TAMP7F_Pos                  (6U)
18653 #define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
18654 #define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
18655 #define TAMP_SR_TAMP8F_Pos                  (7U)
18656 #define TAMP_SR_TAMP8F_Msk                  (0x1UL << TAMP_SR_TAMP8F_Pos)           /*!< 0x00000080 */
18657 #define TAMP_SR_TAMP8F                      TAMP_SR_TAMP8F_Msk
18658 #define TAMP_SR_ITAMP1F_Pos                 (16U)
18659 #define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
18660 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
18661 #define TAMP_SR_ITAMP2F_Pos                 (17U)
18662 #define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
18663 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
18664 #define TAMP_SR_ITAMP3F_Pos                 (18U)
18665 #define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
18666 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
18667 #define TAMP_SR_ITAMP4F_Pos                 (19U)
18668 #define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
18669 #define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
18670 #define TAMP_SR_ITAMP5F_Pos                 (20U)
18671 #define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
18672 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
18673 #define TAMP_SR_ITAMP6F_Pos                 (21U)
18674 #define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
18675 #define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
18676 #define TAMP_SR_ITAMP7F_Pos                 (22U)
18677 #define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
18678 #define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
18679 #define TAMP_SR_ITAMP8F_Pos                 (23U)
18680 #define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
18681 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
18682 #define TAMP_SR_ITAMP9F_Pos                 (24U)
18683 #define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
18684 #define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
18685 #define TAMP_SR_ITAMP11F_Pos                (26U)
18686 #define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
18687 #define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
18688 #define TAMP_SR_ITAMP12F_Pos                (27U)
18689 #define TAMP_SR_ITAMP12F_Msk                (0x1UL << TAMP_SR_ITAMP12F_Pos)         /*!< 0x08000000 */
18690 #define TAMP_SR_ITAMP12F                    TAMP_SR_ITAMP12F_Msk
18691 #define TAMP_SR_ITAMP13F_Pos                (28U)
18692 #define TAMP_SR_ITAMP13F_Msk                (0x1UL << TAMP_SR_ITAMP13F_Pos)         /*!< 0x10000000 */
18693 #define TAMP_SR_ITAMP13F                    TAMP_SR_ITAMP13F_Msk
18694 #define TAMP_SR_ITAMP15F_Pos                (30U)
18695 #define TAMP_SR_ITAMP15F_Msk                (0x1UL << TAMP_SR_ITAMP15F_Pos)         /*!< 0x40000000 */
18696 #define TAMP_SR_ITAMP15F                    TAMP_SR_ITAMP15F_Msk
18697 
18698 /********************  Bits definition for TAMP_MISR register  ****************/
18699 #define TAMP_MISR_TAMP1MF_Pos               (0U)
18700 #define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
18701 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
18702 #define TAMP_MISR_TAMP2MF_Pos               (1U)
18703 #define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
18704 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
18705 #define TAMP_MISR_TAMP3MF_Pos               (2U)
18706 #define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
18707 #define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
18708 #define TAMP_MISR_TAMP4MF_Pos               (3U)
18709 #define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
18710 #define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
18711 #define TAMP_MISR_TAMP5MF_Pos               (4U)
18712 #define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
18713 #define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
18714 #define TAMP_MISR_TAMP6MF_Pos               (5U)
18715 #define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
18716 #define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
18717 #define TAMP_MISR_TAMP7MF_Pos               (6U)
18718 #define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
18719 #define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
18720 #define TAMP_MISR_TAMP8MF_Pos               (7U)
18721 #define TAMP_MISR_TAMP8MF_Msk               (0x1UL << TAMP_MISR_TAMP8MF_Pos)        /*!< 0x00000080 */
18722 #define TAMP_MISR_TAMP8MF                   TAMP_MISR_TAMP8MF_Msk
18723 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
18724 #define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
18725 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
18726 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
18727 #define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
18728 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
18729 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
18730 #define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
18731 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
18732 #define TAMP_MISR_ITAMP4MF_Pos              (19U)
18733 #define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
18734 #define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
18735 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
18736 #define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
18737 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
18738 #define TAMP_MISR_ITAMP6MF_Pos              (21U)
18739 #define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
18740 #define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
18741 #define TAMP_MISR_ITAMP7MF_Pos              (22U)
18742 #define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
18743 #define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
18744 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
18745 #define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
18746 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
18747 #define TAMP_MISR_ITAMP9MF_Pos              (24U)
18748 #define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
18749 #define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
18750 #define TAMP_MISR_ITAMP11MF_Pos             (26U)
18751 #define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
18752 #define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
18753 #define TAMP_MISR_ITAMP12MF_Pos             (27U)
18754 #define TAMP_MISR_ITAMP12MF_Msk             (0x1UL << TAMP_MISR_ITAMP12MF_Pos)       /*!< 0x08000000 */
18755 #define TAMP_MISR_ITAMP12MF                 TAMP_MISR_ITAMP12MF_Msk
18756 #define TAMP_MISR_ITAMP13MF_Pos             (28U)
18757 #define TAMP_MISR_ITAMP13MF_Msk             (0x1UL << TAMP_MISR_ITAMP13MF_Pos)       /*!< 0x10000000 */
18758 #define TAMP_MISR_ITAMP13MF                 TAMP_MISR_ITAMP13MF_Msk
18759 #define TAMP_MISR_ITAMP15MF_Pos             (30U)
18760 #define TAMP_MISR_ITAMP15MF_Msk             (0x1UL << TAMP_MISR_ITAMP15MF_Pos)      /*!< 0x40000000 */
18761 #define TAMP_MISR_ITAMP15MF                 TAMP_MISR_ITAMP15MF_Msk
18762 
18763 /********************  Bits definition for TAMP_SMISR register  ************ *****/
18764 #define TAMP_SMISR_TAMP1MF_Pos              (0U)
18765 #define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
18766 #define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
18767 #define TAMP_SMISR_TAMP2MF_Pos              (1U)
18768 #define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
18769 #define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
18770 #define TAMP_SMISR_TAMP3MF_Pos              (2U)
18771 #define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
18772 #define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
18773 #define TAMP_SMISR_TAMP4MF_Pos              (3U)
18774 #define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
18775 #define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
18776 #define TAMP_SMISR_TAMP5MF_Pos              (4U)
18777 #define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
18778 #define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
18779 #define TAMP_SMISR_TAMP6MF_Pos              (5U)
18780 #define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
18781 #define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
18782 #define TAMP_SMISR_TAMP7MF_Pos              (6U)
18783 #define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
18784 #define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
18785 #define TAMP_SMISR_TAMP8MF_Pos              (7U)
18786 #define TAMP_SMISR_TAMP8MF_Msk              (0x1UL << TAMP_SMISR_TAMP8MF_Pos)       /*!< 0x00000080 */
18787 #define TAMP_SMISR_TAMP8MF                  TAMP_SMISR_TAMP8MF_Msk
18788 #define TAMP_SMISR_ITAMP1MF_Pos             (16U)
18789 #define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
18790 #define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
18791 #define TAMP_SMISR_ITAMP2MF_Pos             (17U)
18792 #define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
18793 #define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
18794 #define TAMP_SMISR_ITAMP3MF_Pos             (18U)
18795 #define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
18796 #define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
18797 #define TAMP_SMISR_ITAMP4MF_Pos             (19U)
18798 #define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
18799 #define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
18800 #define TAMP_SMISR_ITAMP5MF_Pos             (20U)
18801 #define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
18802 #define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
18803 #define TAMP_SMISR_ITAMP6MF_Pos             (21U)
18804 #define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
18805 #define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
18806 #define TAMP_SMISR_ITAMP7MF_Pos             (22U)
18807 #define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
18808 #define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
18809 #define TAMP_SMISR_ITAMP8MF_Pos             (23U)
18810 #define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
18811 #define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
18812 #define TAMP_SMISR_ITAMP9MF_Pos             (24U)
18813 #define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
18814 #define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
18815 #define TAMP_SMISR_ITAMP11MF_Pos            (26U)
18816 #define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
18817 #define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
18818 #define TAMP_SMISR_ITAMP12MF_Pos            (27U)
18819 #define TAMP_SMISR_ITAMP12MF_Msk            (0x1UL << TAMP_SMISR_ITAMP12MF_Pos)      /*!< 0x08000000 */
18820 #define TAMP_SMISR_ITAMP12MF                TAMP_SMISR_ITAMP12MF_Msk
18821 #define TAMP_SMISR_ITAMP13MF_Pos            (28U)
18822 #define TAMP_SMISR_ITAMP13MF_Msk            (0x1UL << TAMP_SMISR_ITAMP13MF_Pos)      /*!< 0x10000000 */
18823 #define TAMP_SMISR_ITAMP13MF                TAMP_SMISR_ITAMP13MF_Msk
18824 #define TAMP_SMISR_ITAMP15MF_Pos            (30U)
18825 #define TAMP_SMISR_ITAMP15MF_Msk            (0x1UL << TAMP_SMISR_ITAMP15MF_Pos)      /*!< 0x40000000 */
18826 #define TAMP_SMISR_ITAMP15MF                TAMP_SMISR_ITAMP15MF_Msk
18827 
18828 /********************  Bits definition for TAMP_SCR register  *****************/
18829 #define TAMP_SCR_CTAMP1F_Pos                (0U)
18830 #define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
18831 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
18832 #define TAMP_SCR_CTAMP2F_Pos                (1U)
18833 #define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
18834 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
18835 #define TAMP_SCR_CTAMP3F_Pos                (2U)
18836 #define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
18837 #define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
18838 #define TAMP_SCR_CTAMP4F_Pos                (3U)
18839 #define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
18840 #define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
18841 #define TAMP_SCR_CTAMP5F_Pos                (4U)
18842 #define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
18843 #define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
18844 #define TAMP_SCR_CTAMP6F_Pos                (5U)
18845 #define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
18846 #define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
18847 #define TAMP_SCR_CTAMP7F_Pos                (6U)
18848 #define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
18849 #define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
18850 #define TAMP_SCR_CTAMP8F_Pos                (7U)
18851 #define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
18852 #define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
18853 #define TAMP_SCR_CITAMP1F_Pos               (16U)
18854 #define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
18855 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
18856 #define TAMP_SCR_CITAMP2F_Pos               (17U)
18857 #define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
18858 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
18859 #define TAMP_SCR_CITAMP3F_Pos               (18U)
18860 #define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
18861 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
18862 #define TAMP_SCR_CITAMP4F_Pos               (19U)
18863 #define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
18864 #define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
18865 #define TAMP_SCR_CITAMP5F_Pos               (20U)
18866 #define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
18867 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
18868 #define TAMP_SCR_CITAMP6F_Pos               (21U)
18869 #define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
18870 #define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
18871 #define TAMP_SCR_CITAMP7F_Pos               (22U)
18872 #define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
18873 #define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
18874 #define TAMP_SCR_CITAMP8F_Pos               (23U)
18875 #define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
18876 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
18877 #define TAMP_SCR_CITAMP9F_Pos               (24U)
18878 #define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
18879 #define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
18880 #define TAMP_SCR_CITAMP11F_Pos              (26U)
18881 #define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
18882 #define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
18883 #define TAMP_SCR_CITAMP12F_Pos              (27U)
18884 #define TAMP_SCR_CITAMP12F_Msk              (0x1UL << TAMP_SCR_CITAMP12F_Pos)       /*!< 0x08000000 */
18885 #define TAMP_SCR_CITAMP12F                  TAMP_SCR_CITAMP12F_Msk
18886 #define TAMP_SCR_CITAMP13F_Pos              (28U)
18887 #define TAMP_SCR_CITAMP13F_Msk              (0x1UL << TAMP_SCR_CITAMP13F_Pos)       /*!< 0x10000000 */
18888 #define TAMP_SCR_CITAMP13F                  TAMP_SCR_CITAMP13F_Msk
18889 #define TAMP_SCR_CITAMP15F_Pos              (30U)
18890 #define TAMP_SCR_CITAMP15F_Msk              (0x1UL << TAMP_SCR_CITAMP15F_Pos)       /*!< 0x40000000 */
18891 #define TAMP_SCR_CITAMP15F                  TAMP_SCR_CITAMP15F_Msk
18892 /********************  Bits definition for TAMP_COUNT1R register  ***************/
18893 #define TAMP_COUNT1R_COUNT_Pos              (0U)
18894 #define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
18895 #define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
18896 
18897 /********************  Bits definition for TAMP_OR register  ***************/
18898 #define TAMP_OR_OUT3_RMP_Pos               (1U)
18899 #define TAMP_OR_OUT3_RMP_Msk               (0x2UL << TAMP_OR_OUT3_RMP_Pos)         /*!< 0x00000006 */
18900 #define TAMP_OR_OUT3_RMP                   TAMP_OR_OUT3_RMP_Msk
18901 #define TAMP_OR_OUT3_RMP_0                 (0x1UL << TAMP_OR_OUT3_RMP_Pos)         /*!< 0x00100000 */
18902 #define TAMP_OR_OUT3_RMP_1                 (0x2UL << TAMP_OR_OUT3_RMP_Pos)         /*!< 0x00200000 */
18903 #define TAMP_OR_OUT5_RMP_Pos               (3U)
18904 #define TAMP_OR_OUT5_RMP_Msk               (0x1UL << TAMP_OR_OUT5_RMP_Pos)         /*!< 0x00000001 */
18905 #define TAMP_OR_OUT5_RMP                   TAMP_OR_OUT5_RMP_Msk
18906 #define TAMP_OR_IN2_RMP_Pos                (8U)
18907 #define TAMP_OR_IN2_RMP_Msk                (0x1UL << TAMP_OR_IN2_RMP_Pos)          /*!< 0x00000001 */
18908 #define TAMP_OR_IN2_RMP                    TAMP_OR_IN2_RMP_Msk
18909 #define TAMP_OR_IN3_RMP_Pos                (9U)
18910 #define TAMP_OR_IN3_RMP_Msk                (0x1UL << TAMP_OR_IN3_RMP_Pos)          /*!< 0x00000001 */
18911 #define TAMP_OR_IN3_RMP                    TAMP_OR_IN3_RMP_Msk
18912 #define TAMP_OR_IN4_RMP_Pos                (10U)
18913 #define TAMP_OR_IN4_RMP_Msk                (0x1UL << TAMP_OR_IN4_RMP_Pos)          /*!< 0x00000001 */
18914 #define TAMP_OR_IN4_RMP                    TAMP_OR_IN4_RMP_Msk
18915 
18916 /********************  Bits definition for TAMP_ERCFG register  ***************/
18917 #define TAMP_ERCFGR_ERCFG0_Pos              (0U)
18918 #define TAMP_ERCFGR_ERCFG0_Msk              (0x1UL << TAMP_ERCFGR_ERCFG0_Pos)         /*!< 0x00000001 */
18919 #define TAMP_ERCFGR_ERCFG0                  TAMP_ERCFGR_ERCFG0_Msk
18920 
18921 /********************  Bits definition for TAMP_BKP0R register  ***************/
18922 #define TAMP_BKP0R_Pos                      (0U)
18923 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
18924 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
18925 
18926 /********************  Bits definition for TAMP_BKP1R register  ****************/
18927 #define TAMP_BKP1R_Pos                      (0U)
18928 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
18929 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
18930 
18931 /********************  Bits definition for TAMP_BKP2R register  ****************/
18932 #define TAMP_BKP2R_Pos                      (0U)
18933 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
18934 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
18935 
18936 /********************  Bits definition for TAMP_BKP3R register  ****************/
18937 #define TAMP_BKP3R_Pos                      (0U)
18938 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
18939 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
18940 
18941 /********************  Bits definition for TAMP_BKP4R register  ****************/
18942 #define TAMP_BKP4R_Pos                      (0U)
18943 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
18944 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
18945 
18946 /********************  Bits definition for TAMP_BKP5R register  ****************/
18947 #define TAMP_BKP5R_Pos                      (0U)
18948 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
18949 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
18950 
18951 /********************  Bits definition for TAMP_BKP6R register  ****************/
18952 #define TAMP_BKP6R_Pos                      (0U)
18953 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
18954 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
18955 
18956 /********************  Bits definition for TAMP_BKP7R register  ****************/
18957 #define TAMP_BKP7R_Pos                      (0U)
18958 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
18959 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
18960 
18961 /********************  Bits definition for TAMP_BKP8R register  ****************/
18962 #define TAMP_BKP8R_Pos                      (0U)
18963 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
18964 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
18965 
18966 /********************  Bits definition for TAMP_BKP9R register  ****************/
18967 #define TAMP_BKP9R_Pos                      (0U)
18968 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
18969 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
18970 
18971 /********************  Bits definition for TAMP_BKP10R register  ***************/
18972 #define TAMP_BKP10R_Pos                     (0U)
18973 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
18974 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
18975 
18976 /********************  Bits definition for TAMP_BKP11R register  ***************/
18977 #define TAMP_BKP11R_Pos                     (0U)
18978 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
18979 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
18980 
18981 /********************  Bits definition for TAMP_BKP12R register  ***************/
18982 #define TAMP_BKP12R_Pos                     (0U)
18983 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
18984 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
18985 
18986 /********************  Bits definition for TAMP_BKP13R register  ***************/
18987 #define TAMP_BKP13R_Pos                     (0U)
18988 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
18989 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
18990 
18991 /********************  Bits definition for TAMP_BKP14R register  ***************/
18992 #define TAMP_BKP14R_Pos                     (0U)
18993 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
18994 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
18995 
18996 /********************  Bits definition for TAMP_BKP15R register  ***************/
18997 #define TAMP_BKP15R_Pos                     (0U)
18998 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
18999 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
19000 
19001 /********************  Bits definition for TAMP_BKP16R register  ***************/
19002 #define TAMP_BKP16R_Pos                     (0U)
19003 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
19004 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
19005 
19006 /********************  Bits definition for TAMP_BKP17R register  ***************/
19007 #define TAMP_BKP17R_Pos                     (0U)
19008 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
19009 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
19010 
19011 /********************  Bits definition for TAMP_BKP18R register  ***************/
19012 #define TAMP_BKP18R_Pos                     (0U)
19013 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
19014 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
19015 
19016 /********************  Bits definition for TAMP_BKP19R register  ***************/
19017 #define TAMP_BKP19R_Pos                     (0U)
19018 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
19019 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
19020 
19021 /********************  Bits definition for TAMP_BKP20R register  ***************/
19022 #define TAMP_BKP20R_Pos                     (0U)
19023 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
19024 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
19025 
19026 /********************  Bits definition for TAMP_BKP21R register  ***************/
19027 #define TAMP_BKP21R_Pos                     (0U)
19028 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
19029 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
19030 
19031 /********************  Bits definition for TAMP_BKP22R register  ***************/
19032 #define TAMP_BKP22R_Pos                     (0U)
19033 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
19034 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
19035 
19036 /********************  Bits definition for TAMP_BKP23R register  ***************/
19037 #define TAMP_BKP23R_Pos                     (0U)
19038 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
19039 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
19040 
19041 /********************  Bits definition for TAMP_BKP24R register  ***************/
19042 #define TAMP_BKP24R_Pos                     (0U)
19043 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
19044 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
19045 
19046 /********************  Bits definition for TAMP_BKP25R register  ***************/
19047 #define TAMP_BKP25R_Pos                     (0U)
19048 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
19049 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
19050 
19051 /********************  Bits definition for TAMP_BKP26R register  ***************/
19052 #define TAMP_BKP26R_Pos                     (0U)
19053 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
19054 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
19055 
19056 /********************  Bits definition for TAMP_BKP27R register  ***************/
19057 #define TAMP_BKP27R_Pos                     (0U)
19058 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
19059 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
19060 
19061 /********************  Bits definition for TAMP_BKP28R register  ***************/
19062 #define TAMP_BKP28R_Pos                     (0U)
19063 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
19064 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
19065 
19066 /********************  Bits definition for TAMP_BKP29R register  ***************/
19067 #define TAMP_BKP29R_Pos                     (0U)
19068 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
19069 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
19070 
19071 /********************  Bits definition for TAMP_BKP30R register  ***************/
19072 #define TAMP_BKP30R_Pos                     (0U)
19073 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
19074 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
19075 
19076 /********************  Bits definition for TAMP_BKP31R register  ***************/
19077 #define TAMP_BKP31R_Pos                     (0U)
19078 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
19079 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
19080 
19081 /******************************************************************************/
19082 /*                                                                            */
19083 /*                          Serial Audio Interface                            */
19084 /*                                                                            */
19085 /******************************************************************************/
19086 /********************  Bit definition for SAI_GCR register  *******************/
19087 #define SAI_GCR_SYNCIN_Pos                  (0U)
19088 #define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
19089 #define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
19090 #define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
19091 #define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
19092 #define SAI_GCR_SYNCOUT_Pos                 (4U)
19093 #define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
19094 #define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
19095 #define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
19096 #define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
19097 
19098 /*******************  Bit definition for SAI_xCR1 register  *******************/
19099 #define SAI_xCR1_MODE_Pos                   (0U)
19100 #define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
19101 #define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
19102 #define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
19103 #define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
19104 #define SAI_xCR1_PRTCFG_Pos                 (2U)
19105 #define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
19106 #define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
19107 #define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
19108 #define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
19109 #define SAI_xCR1_DS_Pos                     (5U)
19110 #define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
19111 #define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
19112 #define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
19113 #define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
19114 #define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
19115 #define SAI_xCR1_LSBFIRST_Pos               (8U)
19116 #define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
19117 #define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
19118 #define SAI_xCR1_CKSTR_Pos                  (9U)
19119 #define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
19120 #define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
19121 #define SAI_xCR1_SYNCEN_Pos                 (10U)
19122 #define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
19123 #define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
19124 #define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
19125 #define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
19126 #define SAI_xCR1_MONO_Pos                   (12U)
19127 #define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
19128 #define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
19129 #define SAI_xCR1_OUTDRIV_Pos                (13U)
19130 #define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
19131 #define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
19132 #define SAI_xCR1_SAIEN_Pos                  (16U)
19133 #define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
19134 #define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
19135 #define SAI_xCR1_DMAEN_Pos                  (17U)
19136 #define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
19137 #define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
19138 #define SAI_xCR1_NODIV_Pos                  (19U)
19139 #define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
19140 #define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
19141 #define SAI_xCR1_MCKDIV_Pos                 (20U)
19142 #define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
19143 #define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
19144 #define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
19145 #define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
19146 #define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
19147 #define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
19148 #define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
19149 #define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
19150 #define SAI_xCR1_OSR_Pos                    (26U)
19151 #define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
19152 #define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
19153 #define SAI_xCR1_MCKEN_Pos                  (27U)
19154 #define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
19155 #define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
19156 
19157 /*******************  Bit definition for SAI_xCR2 register  *******************/
19158 #define SAI_xCR2_FTH_Pos                    (0U)
19159 #define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
19160 #define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
19161 #define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
19162 #define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
19163 #define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
19164 #define SAI_xCR2_FFLUSH_Pos                 (3U)
19165 #define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
19166 #define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
19167 #define SAI_xCR2_TRIS_Pos                   (4U)
19168 #define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
19169 #define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
19170 #define SAI_xCR2_MUTE_Pos                   (5U)
19171 #define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
19172 #define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
19173 #define SAI_xCR2_MUTEVAL_Pos                (6U)
19174 #define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
19175 #define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
19176 #define SAI_xCR2_MUTECNT_Pos                (7U)
19177 #define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
19178 #define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
19179 #define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
19180 #define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
19181 #define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
19182 #define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
19183 #define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
19184 #define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
19185 #define SAI_xCR2_CPL_Pos                    (13U)
19186 #define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
19187 #define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
19188 #define SAI_xCR2_COMP_Pos                   (14U)
19189 #define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
19190 #define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
19191 #define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
19192 #define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
19193 
19194 /******************  Bit definition for SAI_xFRCR register  *******************/
19195 #define SAI_xFRCR_FRL_Pos                   (0U)
19196 #define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
19197 #define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
19198 #define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
19199 #define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
19200 #define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
19201 #define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
19202 #define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
19203 #define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
19204 #define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
19205 #define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
19206 #define SAI_xFRCR_FSALL_Pos                 (8U)
19207 #define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
19208 #define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
19209 #define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
19210 #define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
19211 #define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
19212 #define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
19213 #define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
19214 #define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
19215 #define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
19216 #define SAI_xFRCR_FSDEF_Pos                 (16U)
19217 #define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
19218 #define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
19219 #define SAI_xFRCR_FSPOL_Pos                 (17U)
19220 #define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
19221 #define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
19222 #define SAI_xFRCR_FSOFF_Pos                 (18U)
19223 #define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
19224 #define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
19225 
19226 /******************  Bit definition for SAI_xSLOTR register  *******************/
19227 #define SAI_xSLOTR_FBOFF_Pos                (0U)
19228 #define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
19229 #define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
19230 #define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
19231 #define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
19232 #define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
19233 #define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
19234 #define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
19235 #define SAI_xSLOTR_SLOTSZ_Pos               (6U)
19236 #define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
19237 #define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
19238 #define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
19239 #define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
19240 #define SAI_xSLOTR_NBSLOT_Pos               (8U)
19241 #define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
19242 #define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
19243 #define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
19244 #define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
19245 #define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
19246 #define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
19247 #define SAI_xSLOTR_SLOTEN_Pos               (16U)
19248 #define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
19249 #define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
19250 
19251 /*******************  Bit definition for SAI_xIMR register  *******************/
19252 #define SAI_xIMR_OVRUDRIE_Pos               (0U)
19253 #define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
19254 #define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
19255 #define SAI_xIMR_MUTEDETIE_Pos              (1U)
19256 #define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
19257 #define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
19258 #define SAI_xIMR_WCKCFGIE_Pos               (2U)
19259 #define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
19260 #define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
19261 #define SAI_xIMR_FREQIE_Pos                 (3U)
19262 #define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
19263 #define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
19264 #define SAI_xIMR_CNRDYIE_Pos                (4U)
19265 #define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
19266 #define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
19267 #define SAI_xIMR_AFSDETIE_Pos               (5U)
19268 #define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
19269 #define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
19270 #define SAI_xIMR_LFSDETIE_Pos               (6U)
19271 #define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
19272 #define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
19273 
19274 /********************  Bit definition for SAI_xSR register  *******************/
19275 #define SAI_xSR_OVRUDR_Pos                  (0U)
19276 #define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
19277 #define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
19278 #define SAI_xSR_MUTEDET_Pos                 (1U)
19279 #define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
19280 #define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
19281 #define SAI_xSR_WCKCFG_Pos                  (2U)
19282 #define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
19283 #define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
19284 #define SAI_xSR_FREQ_Pos                    (3U)
19285 #define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
19286 #define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
19287 #define SAI_xSR_CNRDY_Pos                   (4U)
19288 #define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
19289 #define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
19290 #define SAI_xSR_AFSDET_Pos                  (5U)
19291 #define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
19292 #define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
19293 #define SAI_xSR_LFSDET_Pos                  (6U)
19294 #define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
19295 #define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
19296 #define SAI_xSR_FLVL_Pos                    (16U)
19297 #define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
19298 #define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
19299 #define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
19300 #define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
19301 #define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
19302 
19303 /******************  Bit definition for SAI_xCLRFR register  ******************/
19304 #define SAI_xCLRFR_COVRUDR_Pos              (0U)
19305 #define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
19306 #define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
19307 #define SAI_xCLRFR_CMUTEDET_Pos             (1U)
19308 #define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
19309 #define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
19310 #define SAI_xCLRFR_CWCKCFG_Pos              (2U)
19311 #define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
19312 #define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
19313 #define SAI_xCLRFR_CFREQ_Pos                (3U)
19314 #define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
19315 #define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
19316 #define SAI_xCLRFR_CCNRDY_Pos               (4U)
19317 #define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
19318 #define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
19319 #define SAI_xCLRFR_CAFSDET_Pos              (5U)
19320 #define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
19321 #define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
19322 #define SAI_xCLRFR_CLFSDET_Pos              (6U)
19323 #define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
19324 #define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
19325 
19326 /******************  Bit definition for SAI_xDR register  ******************/
19327 #define SAI_xDR_DATA_Pos                    (0U)
19328 #define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
19329 #define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
19330 
19331 /******************  Bit definition for SAI_PDMCR register  *******************/
19332 #define SAI_PDMCR_PDMEN_Pos                 (0U)
19333 #define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
19334 #define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
19335 #define SAI_PDMCR_MICNBR_Pos                (4U)
19336 #define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
19337 #define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
19338 #define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
19339 #define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
19340 #define SAI_PDMCR_CKEN1_Pos                 (8U)
19341 #define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
19342 #define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
19343 #define SAI_PDMCR_CKEN2_Pos                 (9U)
19344 #define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
19345 #define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
19346 #define SAI_PDMCR_CKEN3_Pos                 (10U)
19347 #define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
19348 #define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
19349 #define SAI_PDMCR_CKEN4_Pos                 (11U)
19350 #define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
19351 #define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
19352 
19353 /******************  Bit definition for SAI_PDMDLY register  ******************/
19354 #define SAI_PDMDLY_DLYM1L_Pos               (0U)
19355 #define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
19356 #define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
19357 #define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
19358 #define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
19359 #define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
19360 #define SAI_PDMDLY_DLYM1R_Pos               (4U)
19361 #define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
19362 #define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
19363 #define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
19364 #define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
19365 #define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
19366 #define SAI_PDMDLY_DLYM2L_Pos               (8U)
19367 #define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
19368 #define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
19369 #define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
19370 #define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
19371 #define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
19372 #define SAI_PDMDLY_DLYM2R_Pos               (12U)
19373 #define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
19374 #define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
19375 #define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
19376 #define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
19377 #define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
19378 #define SAI_PDMDLY_DLYM3L_Pos               (16U)
19379 #define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
19380 #define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
19381 #define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
19382 #define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
19383 #define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
19384 #define SAI_PDMDLY_DLYM3R_Pos               (20U)
19385 #define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
19386 #define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
19387 #define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
19388 #define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
19389 #define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
19390 #define SAI_PDMDLY_DLYM4L_Pos               (24U)
19391 #define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
19392 #define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
19393 #define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
19394 #define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
19395 #define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
19396 #define SAI_PDMDLY_DLYM4R_Pos               (28U)
19397 #define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
19398 #define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
19399 #define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
19400 #define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
19401 #define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
19402 
19403 /******************************************************************************/
19404 /*                                                                            */
19405 /*                                 SBS                                        */
19406 /*                                                                            */
19407 /******************************************************************************/
19408 /********************  Bit definition for SBS_HDPLCR register  *****************/
19409 #define SBS_HDPLCR_INCR_HDPL_Pos            (0U)
19410 #define SBS_HDPLCR_INCR_HDPL_Msk            (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos)     /*!< 0x000000FF */
19411 #define SBS_HDPLCR_INCR_HDPL                SBS_HDPLCR_INCR_HDPL_Msk                 /*!< Increment HDPL value. */
19412 
19413 /********************  Bit definition for SBS_HDPLSR register  *****************/
19414 #define SBS_HDPLSR_HDPL_Pos                 (0U)
19415 #define SBS_HDPLSR_HDPL_Msk                 (0xFFUL << SBS_HDPLSR_HDPL_Pos)          /*!< 0x000000FF */
19416 #define SBS_HDPLSR_HDPL                     SBS_HDPLSR_HDPL_Msk                      /*!< HDPL value. */
19417 
19418 /********************  Bit definition for SBS_NEXTHDPLCR register  *****************/
19419 #define SBS_NEXTHDPLCR_NEXTHDPL_Pos         (0U)
19420 #define SBS_NEXTHDPLCR_NEXTHDPL_Msk         (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos)   /*!< 0x00000003 */
19421 #define SBS_NEXTHDPLCR_NEXTHDPL             SBS_NEXTHDPLCR_NEXTHDPL_Msk              /*!< NEXTHDPL value. */
19422 #define SBS_NEXTHDPLCR_NEXTHDPL_0           (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos)   /*!< 0x00000001 */
19423 #define SBS_NEXTHDPLCR_NEXTHDPL_1           (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos)   /*!< 0x00000002 */
19424 
19425 /********************  Bit definition for SBS_DBGCR register  *****************/
19426 #define SBS_DBGCR_AP_UNLOCK_Pos           (0U)
19427 #define SBS_DBGCR_AP_UNLOCK_Msk           (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos)    /*!< 0x000000FF */
19428 #define SBS_DBGCR_AP_UNLOCK               SBS_DBGCR_AP_UNLOCK_Msk                /*!< Open the Access Port. */
19429 
19430 #define SBS_DBGCR_DBG_UNLOCK_Pos          (8U)
19431 #define SBS_DBGCR_DBG_UNLOCK_Msk          (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos)   /*!< 0x0000FF00 */
19432 #define SBS_DBGCR_DBG_UNLOCK              SBS_DBGCR_DBG_UNLOCK_Msk               /*!< Open the debug when DBG_AUTH_HDPL is reached. */
19433 
19434 #define SBS_DBGCR_DBG_AUTH_HDPL_Pos       (16U)
19435 #define SBS_DBGCR_DBG_AUTH_HDPL_Msk       (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */
19436 #define SBS_DBGCR_DBG_AUTH_HDPL           SBS_DBGCR_DBG_AUTH_HDPL_Msk             /*!< HDPL value when the debug should be effectively opened. */
19437 
19438 #define SBS_DBGCR_DBG_AUTH_SEC_Pos        (24U)
19439 #define SBS_DBGCR_DBG_AUTH_SEC_Msk        (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */
19440 #define SBS_DBGCR_DBG_AUTH_SEC            SBS_DBGCR_DBG_AUTH_SEC_Msk             /*!< Open the non-secured and secured debugs. */
19441 
19442 /********************  Bit definition for SBS_DBGLCKR register  *****************/
19443 #define SBS_DBGLOCKR_DBGCFG_LOCK_Pos      (0U)
19444 #define SBS_DBGLOCKR_DBGCFG_LOCK_Msk      (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */
19445 #define SBS_DBGLOCKR_DBGCFG_LOCK          SBS_DBGLOCKR_DBGCFG_LOCK_Msk             /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */
19446 
19447 /********************  Bit definition for SBS_RSSCMDR register  ***************/
19448 #define SBS_RSSCMDR_RSSCMD_Pos            (0U)
19449 #define SBS_RSSCMDR_RSSCMD_Msk            (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos)    /*!< 0x0000FFFF */
19450 #define SBS_RSSCMDR_RSSCMD                SBS_RSSCMDR_RSSCMD_Msk                 /*!< command to be executed by the RSS. */
19451 
19452 /********************  Bit definition for SBS_EPOCHSELCR register  ************/
19453 #define SBS_EPOCHSELCR_EPOCH_SEL_Pos      (0U)
19454 #define SBS_EPOCHSELCR_EPOCH_SEL_Msk      (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos)    /*!< 0x00000003 */
19455 #define SBS_EPOCHSELCR_EPOCH_SEL          SBS_EPOCHSELCR_EPOCH_SEL_Msk               /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys  */
19456 #define SBS_EPOCHSELCR_EPOCH_SEL_0        (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos)    /*!< 0x00000001 */
19457 #define SBS_EPOCHSELCR_EPOCH_SEL_1        (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos)    /*!< 0x00000002 */
19458 
19459 /******************  Bit definition for SBS_PMCR register  ****************/
19460 #define SBS_PMCR_BOOSTEN_Pos              (8U)
19461 #define SBS_PMCR_BOOSTEN_Msk              (0x1UL << SBS_PMCR_BOOSTEN_Pos)            /*!< 0x00000100 */
19462 #define SBS_PMCR_BOOSTEN                  SBS_PMCR_BOOSTEN_Msk                       /*!< I/O analog switch voltage booster enable */
19463 #define SBS_PMCR_BOOSTVDDSEL_Pos          (9U)
19464 #define SBS_PMCR_BOOSTVDDSEL_Msk          (0x1UL << SBS_PMCR_BOOSTVDDSEL_Pos)        /*!< 0x00000200 */
19465 #define SBS_PMCR_BOOSTVDDSEL              SBS_PMCR_BOOSTVDDSEL_Msk                   /*!< GPIO analog switch control voltage selection */
19466 #define SBS_PMCR_PB6_FMP_Pos              (16U)
19467 #define SBS_PMCR_PB6_FMP_Msk              (0x1UL << SBS_PMCR_PB6_FMP_Pos)            /*!< 0x00010000 */
19468 #define SBS_PMCR_PB6_FMP                  SBS_PMCR_PB6_FMP_Msk                       /*!< Fast-mode Plus command on PB(6) */
19469 #define SBS_PMCR_PB7_FMP_Pos              (17U)
19470 #define SBS_PMCR_PB7_FMP_Msk              (0x1UL << SBS_PMCR_PB7_FMP_Pos)            /*!< 0x00020000 */
19471 #define SBS_PMCR_PB7_FMP                  SBS_PMCR_PB7_FMP_Msk                       /*!< Fast-mode Plus command on PB(7) */
19472 #define SBS_PMCR_PB8_FMP_Pos              (18U)
19473 #define SBS_PMCR_PB8_FMP_Msk              (0x1UL << SBS_PMCR_PB8_FMP_Pos)            /*!< 0x00040000 */
19474 #define SBS_PMCR_PB8_FMP                  SBS_PMCR_PB8_FMP_Msk                       /*!< Fast-mode Plus command on PB(8) */
19475 #define SBS_PMCR_PB9_FMP_Pos              (19U)
19476 #define SBS_PMCR_PB9_FMP_Msk              (0x1UL << SBS_PMCR_PB9_FMP_Pos)            /*!< 0x00080000 */
19477 #define SBS_PMCR_PB9_FMP                  SBS_PMCR_PB9_FMP_Msk                       /*!< Fast-mode Plus command on PB(9) */
19478 #define SBS_PMCR_ETH_SEL_PHY_Pos          (21U)
19479 #define SBS_PMCR_ETH_SEL_PHY_Msk          (0x7UL << SBS_PMCR_ETH_SEL_PHY_Pos)        /*!< 0x00E00000 */
19480 #define SBS_PMCR_ETH_SEL_PHY              SBS_PMCR_ETH_SEL_PHY_Msk                   /*!< Ethernet PHY Interface Selection */
19481 #define SBS_PMCR_ETH_SEL_PHY_0            (0x1UL << SBS_PMCR_ETH_SEL_PHY_Pos)        /*!< 0x00200000 */
19482 #define SBS_PMCR_ETH_SEL_PHY_1            (0x2UL << SBS_PMCR_ETH_SEL_PHY_Pos)        /*!< 0x00400000 */
19483 #define SBS_PMCR_ETH_SEL_PHY_2            (0x4UL << SBS_PMCR_ETH_SEL_PHY_Pos)        /*!< 0x00800000 */
19484 
19485 /******************  Bit definition for SBS_FPUIMR register  ***************/
19486 #define SBS_FPUIMR_FPU_IE_Pos            (0U)
19487 #define SBS_FPUIMR_FPU_IE_Msk            (0x3FUL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x0000003F - */
19488 #define SBS_FPUIMR_FPU_IE                SBS_FPUIMR_FPU_IE_Msk                       /*!<  All FPU interrupts enable */
19489 #define SBS_FPUIMR_FPU_IE_0              (0x1UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000001 - Invalid operation Interrupt enable */
19490 #define SBS_FPUIMR_FPU_IE_1              (0x2UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000002 - Divide-by-zero Interrupt enable */
19491 #define SBS_FPUIMR_FPU_IE_2              (0x4UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000004 - Underflow Interrupt enable */
19492 #define SBS_FPUIMR_FPU_IE_3              (0x8UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000008 - Overflow Interrupt enable */
19493 #define SBS_FPUIMR_FPU_IE_4              (0x10UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000010 - Input denormal Interrupt enable */
19494 #define SBS_FPUIMR_FPU_IE_5              (0x20UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */
19495 
19496 /******************  Bit definition for SBS_MESR register  ****************/
19497 #define SBS_MESR_MCLR_Pos                (0U)
19498 #define SBS_MESR_MCLR_Msk                (0x1UL << SBS_MESR_MCLR_Pos)         /*!< 0x00000001 */
19499 #define SBS_MESR_MCLR                    SBS_MESR_MCLR_Msk                    /*!< Status of Erase after Reset */
19500 #define SBS_MESR_IPMEE_Pos               (16U)
19501 #define SBS_MESR_IPMEE_Msk               (0x1UL << SBS_MESR_IPMEE_Pos)        /*!< 0x00010000 */
19502 #define SBS_MESR_IPMEE                   SBS_MESR_IPMEE_Msk                   /*!< Status of End of Erase for ICache and PKA RAMs */
19503 
19504 /******************  Bit definition for SBS_CCCSR register  ****************/
19505 #define SBS_CCCSR_EN1_Pos                (0U)
19506 #define SBS_CCCSR_EN1_Msk                (0x1UL << SBS_CCCSR_EN1_Pos)         /*!< 0x00000001 */
19507 #define SBS_CCCSR_EN1                    SBS_CCCSR_EN1_Msk                    /*!< Enable compensation cell for VDD power rail */
19508 #define SBS_CCCSR_CS1_Pos                (1U)
19509 #define SBS_CCCSR_CS1_Msk                (0x1UL << SBS_CCCSR_CS1_Pos)         /*!< 0x00000002 */
19510 #define SBS_CCCSR_CS1                    SBS_CCCSR_CS1_Msk                    /*!< Code selection for VDD power rail */
19511 #define SBS_CCCSR_EN2_Pos                (2U)
19512 #define SBS_CCCSR_EN2_Msk                (0x1UL << SBS_CCCSR_EN2_Pos)         /*!< 0x00000004 */
19513 #define SBS_CCCSR_EN2                    SBS_CCCSR_EN2_Msk                    /*!< Enable compensation cell for VDDIO power rail */
19514 #define SBS_CCCSR_CS2_Pos                (3U)
19515 #define SBS_CCCSR_CS2_Msk                (0x1UL << SBS_CCCSR_CS2_Pos)         /*!< 0x00000008 */
19516 #define SBS_CCCSR_CS2                    SBS_CCCSR_CS2_Msk                    /*!< Code selection for VDDIO power rail */
19517 #define SBS_CCCSR_RDY1_Pos               (8U)
19518 #define SBS_CCCSR_RDY1_Msk               (0x1UL << SBS_CCCSR_RDY1_Pos)        /*!< 0x00000100 */
19519 #define SBS_CCCSR_RDY1                   SBS_CCCSR_RDY1_Msk                   /*!< VDD compensation cell ready flag */
19520 #define SBS_CCCSR_RDY2_Pos               (9U)
19521 #define SBS_CCCSR_RDY2_Msk               (0x1UL << SBS_CCCSR_RDY2_Pos)        /*!< 0x00000200 */
19522 #define SBS_CCCSR_RDY2                   SBS_CCCSR_RDY2_Msk                   /*!< VDDIO compensation cell ready flag */
19523 
19524 /******************  Bit definition for SBS_CCVALR register  ****************/
19525 #define SBS_CCVALR_ANSRC1_Pos            (0U)
19526 #define SBS_CCVALR_ANSRC1_Msk            (0xFUL << SBS_CCVALR_ANSRC1_Pos)     /*!< 0x0000000F */
19527 #define SBS_CCVALR_ANSRC1                SBS_CCVALR_ANSRC1_Msk                /*!< NMOS compensation value */
19528 #define SBS_CCVALR_APSRC1_Pos            (4U)
19529 #define SBS_CCVALR_APSRC1_Msk            (0xFUL << SBS_CCVALR_APSRC1_Pos)     /*!< 0x000000F0 */
19530 #define SBS_CCVALR_APSRC1                SBS_CCVALR_APSRC1_Msk                /*!< PMOS compensation value */
19531 #define SBS_CCVALR_ANSRC2_Pos            (8U)
19532 #define SBS_CCVALR_ANSRC2_Msk            (0xFUL << SBS_CCVALR_ANSRC2_Pos)     /*!< 0x00000F00 */
19533 #define SBS_CCVALR_ANSRC2                SBS_CCVALR_ANSRC2_Msk                /*!< NMOS compensation value */
19534 #define SBS_CCVALR_APSRC2_Pos            (12U)
19535 #define SBS_CCVALR_APSRC2_Msk            (0xFUL << SBS_CCVALR_APSRC2_Pos)     /*!< 0x0000F000 */
19536 #define SBS_CCVALR_APSRC2                SBS_CCVALR_APSRC2_Msk                /*!< PMOS compensation value */
19537 
19538 /******************  Bit definition for SBS_CCSWCR register  ****************/
19539 #define SBS_CCSWCR_SW_ANSRC1_Pos         (0U)
19540 #define SBS_CCSWCR_SW_ANSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos)  /*!< 0x0000000F */
19541 #define SBS_CCSWCR_SW_ANSRC1             SBS_CCSWCR_SW_ANSRC1_Msk             /*!< NMOS compensation code for VDD Power Rail */
19542 #define SBS_CCSWCR_SW_APSRC1_Pos         (4U)
19543 #define SBS_CCSWCR_SW_APSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos)  /*!< 0x000000F0 */
19544 #define SBS_CCSWCR_SW_APSRC1             SBS_CCSWCR_SW_APSRC1_Msk             /*!< PMOS compensation code for VDD Power Rail */
19545 #define SBS_CCSWCR_SW_ANSRC2_Pos         (8U)
19546 #define SBS_CCSWCR_SW_ANSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos)  /*!< 0x00000F00 */
19547 #define SBS_CCSWCR_SW_ANSRC2             SBS_CCSWCR_SW_ANSRC2_Msk             /*!< NMOS compensation code for VDDIO Power Rail */
19548 #define SBS_CCSWCR_SW_APSRC2_Pos         (12U)
19549 #define SBS_CCSWCR_SW_APSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos)  /*!< 0x0000F000 */
19550 #define SBS_CCSWCR_SW_APSRC2             SBS_CCSWCR_SW_APSRC2_Msk             /*!< PMOS compensation code for VDDIO Power Rail */
19551 
19552 /******************  Bit definition for SBS_CFGR2 register  ****************/
19553 #define SBS_CFGR2_CLL_Pos                (0U)
19554 #define SBS_CFGR2_CLL_Msk                (0x1UL << SBS_CFGR2_CLL_Pos)   /*!< 0x00000001 */
19555 #define SBS_CFGR2_CLL                    SBS_CFGR2_CLL_Msk              /*!< Core Lockup Lock */
19556 #define SBS_CFGR2_SEL_Pos                (1U)
19557 #define SBS_CFGR2_SEL_Msk                (0x1UL << SBS_CFGR2_SEL_Pos)   /*!< 0x00000002 */
19558 #define SBS_CFGR2_SEL                    SBS_CFGR2_SEL_Msk              /*!< SRAM ECC Lock */
19559 #define SBS_CFGR2_PVDL_Pos               (2U)
19560 #define SBS_CFGR2_PVDL_Msk               (0x1UL << SBS_CFGR2_PVDL_Pos)  /*!< 0x00000004 */
19561 #define SBS_CFGR2_PVDL                   SBS_CFGR2_PVDL_Msk             /*!<  PVD Lock */
19562 #define SBS_CFGR2_ECCL_Pos               (3U)
19563 #define SBS_CFGR2_ECCL_Msk               (0x1UL << SBS_CFGR2_ECCL_Pos)  /*!< 0x00000008 */
19564 #define SBS_CFGR2_ECCL                   SBS_CFGR2_ECCL_Msk             /*!< Flash ECC Lock*/
19565 
19566 /********************  Bit definition for SBS_SECCFGR register  ***************/
19567 #define SBS_SECCFGR_SBSSEC_Pos           (0U)
19568 #define SBS_SECCFGR_SBSSEC_Msk           (0x1UL << SBS_SECCFGR_SBSSEC_Pos)    /*!< 0x00000001 */
19569 #define SBS_SECCFGR_SBSSEC               SBS_SECCFGR_SBSSEC_Msk               /*!< SBS clock control security enable */
19570 #define SBS_SECCFGR_CLASSBSEC_Pos        (1U)
19571 #define SBS_SECCFGR_CLASSBSEC_Msk        (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */
19572 #define SBS_SECCFGR_CLASSBSEC            SBS_SECCFGR_CLASSBSEC_Msk            /*!< ClassB SBS security enable */
19573 #define SBS_SECCFGR_FPUSEC_Pos           (3U)
19574 #define SBS_SECCFGR_FPUSEC_Msk           (0x1UL << SBS_SECCFGR_FPUSEC_Pos)    /*!< 0x00000008 */
19575 #define SBS_SECCFGR_FPUSEC               SBS_SECCFGR_FPUSEC_Msk               /*!< FPU SBS security enable */
19576 #define SBS_SECCFGR_SDCE_SEC_EN_Pos      (31U)
19577 #define SBS_SECCFGR_SDCE_SEC_EN_Msk      (0x1UL << SBS_SECCFGR_SDCE_SEC_EN_Pos) /*!< 0x80000000 */
19578 #define SBS_SECCFGR_SDCE_SEC_EN          SBS_SECCFGR_SDCE_SEC_EN_Msk            /*!< SMPS SBS security enable */
19579 
19580 /******************  Bit definition for SBS_CNSLCKR register  **************/
19581 #define SBS_CNSLCKR_LOCKNSVTOR_Pos       (0U)
19582 #define SBS_CNSLCKR_LOCKNSVTOR_Msk       (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */
19583 #define SBS_CNSLCKR_LOCKNSVTOR           SBS_CNSLCKR_LOCKNSVTOR_Msk            /*!< Disable VTOR_NS register writes by SW or debug agent */
19584 #define SBS_CNSLCKR_LOCKNSMPU_Pos        (1U)
19585 #define SBS_CNSLCKR_LOCKNSMPU_Msk        (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos)  /*!< 0x00000002 */
19586 #define SBS_CNSLCKR_LOCKNSMPU            SBS_CNSLCKR_LOCKNSMPU_Msk             /*!< Disable Non-Secure MPU registers writes by SW or debug agent */
19587 
19588 /******************  Bit definition for SBS_CSLCKR register  ***************/
19589 #define SBS_CSLCKR_LOCKSVTAIRCR_Pos      (0U)
19590 #define SBS_CSLCKR_LOCKSVTAIRCR_Msk      (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */
19591 #define SBS_CSLCKR_LOCKSVTAIRCR          SBS_CSLCKR_LOCKSVTAIRCR_Msk          /*!< Disable changes to the secure vector table address, handling of system faults */
19592 #define SBS_CSLCKR_LOCKSMPU_Pos          (1U)
19593 #define SBS_CSLCKR_LOCKSMPU_Msk          (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos)   /*!< 0x00000002 */
19594 #define SBS_CSLCKR_LOCKSMPU              SBS_CSLCKR_LOCKSMPU_Msk              /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
19595 #define SBS_CSLCKR_LOCKSAU_Pos           (2U)
19596 #define SBS_CSLCKR_LOCKSAU_Msk           (0x1UL << SBS_CSLCKR_LOCKSAU_Pos)    /*!< 0x00000004 */
19597 #define SBS_CSLCKR_LOCKSAU               SBS_CSLCKR_LOCKSAU_Msk               /*!< Disable changes to SAU registers */
19598 
19599 /******************  Bit definition for SBS_ECCNMIR register  ***************/
19600 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos   (0U)
19601 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk   (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos)   /*!< 0x00000001 */
19602 #define SBS_ECCNMIR_ECCNMI_MASK_EN       SBS_ECCNMIR_ECCNMI_MASK_EN_Msk              /*!< Disable NMI in case of double ECC error in flash interface */
19603 
19604 /*****************************************************************************/
19605 /*                                                                           */
19606 /*                        Global TrustZone Control                           */
19607 /*                                                                           */
19608 /*****************************************************************************/
19609 /*******************  Bits definition for GTZC_TZSC_CR register  ******************/
19610 #define GTZC_TZSC_CR_LCK_Pos                (0U)
19611 #define GTZC_TZSC_CR_LCK_Msk                (0x01UL << GTZC_TZSC_CR_LCK_Pos)        /*!< 0x00000001 */
19612 
19613 /*******************  Bits definition for GTZC_TZSC_MPCWM_CFGR register  **********/
19614 #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos       (0U)
19615 #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos)
19616 #define GTZC_TZSC_MPCWM_CFGR_SREN           GTZC_TZSC_MPCWM_CFGR_SREN_Msk
19617 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos     (1U)
19618 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk     (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos)
19619 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK         GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
19620 #define GTZC_TZSC_MPCWM_CFGR_SEC_Pos        (8U)
19621 #define GTZC_TZSC_MPCWM_CFGR_SEC_Msk        (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos)
19622 #define GTZC_TZSC_MPCWM_CFGR_SEC            GTZC_TZSC_MPCWM_CFGR_SEC_Msk
19623 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos       (9U)
19624 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos)
19625 #define GTZC_TZSC_MPCWM_CFGR_PRIV           GTZC_TZSC_MPCWM_CFGR_PRIV_Msk
19626 
19627 /*******************  Bits definition for GTZC_TZSC_MPCWMR register  **************/
19628 #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos     (0U)
19629 #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk     (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos)
19630 #define GTZC_TZSC_MPCWMR_SUBZ_START         GTZC_TZSC_MPCWMR_SUBZ_START_Msk
19631 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos    (16U)
19632 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk    (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos)
19633 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH        GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
19634 
19635 /*******  Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers  *****/
19636 /*******  Bits definition for TZIC _IERx/_SRx/_IFCRx registers  ********/
19637 
19638 /***************  Bits definition for register x=1 (TZSC1) *************/
19639 #define GTZC_CFGR1_TIM2_Pos                 (0U)
19640 #define GTZC_CFGR1_TIM2_Msk                 (0x01UL << GTZC_CFGR1_TIM2_Pos)
19641 #define GTZC_CFGR1_TIM3_Pos                 (1U)
19642 #define GTZC_CFGR1_TIM3_Msk                 (0x01UL << GTZC_CFGR1_TIM3_Pos)
19643 #define GTZC_CFGR1_TIM4_Pos                 (2U)
19644 #define GTZC_CFGR1_TIM4_Msk                 (0x01UL << GTZC_CFGR1_TIM4_Pos)
19645 #define GTZC_CFGR1_TIM5_Pos                 (3U)
19646 #define GTZC_CFGR1_TIM5_Msk                 (0x01UL << GTZC_CFGR1_TIM5_Pos)
19647 #define GTZC_CFGR1_TIM6_Pos                 (4U)
19648 #define GTZC_CFGR1_TIM6_Msk                 (0x01UL << GTZC_CFGR1_TIM6_Pos)
19649 #define GTZC_CFGR1_TIM7_Pos                 (5U)
19650 #define GTZC_CFGR1_TIM7_Msk                 (0x01UL << GTZC_CFGR1_TIM7_Pos)
19651 #define GTZC_CFGR1_TIM12_Pos                (6U)
19652 #define GTZC_CFGR1_TIM12_Msk                (0x01UL << GTZC_CFGR1_TIM12_Pos)
19653 #define GTZC_CFGR1_TIM13_Pos                (7U)
19654 #define GTZC_CFGR1_TIM13_Msk                (0x01UL << GTZC_CFGR1_TIM13_Pos)
19655 #define GTZC_CFGR1_TIM14_Pos                (8U)
19656 #define GTZC_CFGR1_TIM14_Msk                (0x01UL << GTZC_CFGR1_TIM14_Pos)
19657 #define GTZC_CFGR1_WWDG_Pos                 (9U)
19658 #define GTZC_CFGR1_WWDG_Msk                 (0x01UL << GTZC_CFGR1_WWDG_Pos)
19659 #define GTZC_CFGR1_IWDG_Pos                 (10U)
19660 #define GTZC_CFGR1_IWDG_Msk                 (0x01UL << GTZC_CFGR1_IWDG_Pos)
19661 #define GTZC_CFGR1_SPI2_Pos                 (11U)
19662 #define GTZC_CFGR1_SPI2_Msk                 (0x01UL << GTZC_CFGR1_SPI2_Pos)
19663 #define GTZC_CFGR1_SPI3_Pos                 (12U)
19664 #define GTZC_CFGR1_SPI3_Msk                 (0x01UL << GTZC_CFGR1_SPI3_Pos)
19665 #define GTZC_CFGR1_USART2_Pos               (13U)
19666 #define GTZC_CFGR1_USART2_Msk               (0x01UL << GTZC_CFGR1_USART2_Pos)
19667 #define GTZC_CFGR1_USART3_Pos               (14U)
19668 #define GTZC_CFGR1_USART3_Msk               (0x01UL << GTZC_CFGR1_USART3_Pos)
19669 #define GTZC_CFGR1_UART4_Pos                (15U)
19670 #define GTZC_CFGR1_UART4_Msk                (0x01UL << GTZC_CFGR1_UART4_Pos)
19671 #define GTZC_CFGR1_UART5_Pos                (16U)
19672 #define GTZC_CFGR1_UART5_Msk                (0x01UL << GTZC_CFGR1_UART5_Pos)
19673 #define GTZC_CFGR1_I2C1_Pos                 (17U)
19674 #define GTZC_CFGR1_I2C1_Msk                 (0x01UL << GTZC_CFGR1_I2C1_Pos)
19675 #define GTZC_CFGR1_I2C2_Pos                 (18U)
19676 #define GTZC_CFGR1_I2C2_Msk                 (0x01UL << GTZC_CFGR1_I2C2_Pos)
19677 #define GTZC_CFGR1_I3C1_Pos                 (19U)
19678 #define GTZC_CFGR1_I3C1_Msk                 (0x01UL << GTZC_CFGR1_I3C1_Pos)
19679 #define GTZC_CFGR1_CRS_Pos                  (20U)
19680 #define GTZC_CFGR1_CRS_Msk                  (0x01UL << GTZC_CFGR1_CRS_Pos)
19681 #define GTZC_CFGR1_USART6_Pos               (21U)
19682 #define GTZC_CFGR1_USART6_Msk               (0x01UL << GTZC_CFGR1_USART6_Pos)
19683 #define GTZC_CFGR1_USART10_Pos              (22U)
19684 #define GTZC_CFGR1_USART10_Msk              (0x01UL << GTZC_CFGR1_USART10_Pos)
19685 #define GTZC_CFGR1_USART11_Pos              (23U)
19686 #define GTZC_CFGR1_USART11_Msk              (0x01UL << GTZC_CFGR1_USART11_Pos)
19687 #define GTZC_CFGR1_HDMICEC_Pos              (24U)
19688 #define GTZC_CFGR1_HDMICEC_Msk              (0x01UL << GTZC_CFGR1_HDMICEC_Pos)
19689 #define GTZC_CFGR1_DAC12_Pos                (25U)
19690 #define GTZC_CFGR1_DAC12_Msk                (0x01UL << GTZC_CFGR1_DAC12_Pos)
19691 #define GTZC_CFGR1_UART7_Pos                (26U)
19692 #define GTZC_CFGR1_UART7_Msk                (0x01UL << GTZC_CFGR1_UART7_Pos)
19693 #define GTZC_CFGR1_UART8_Pos                (27U)
19694 #define GTZC_CFGR1_UART8_Msk                (0x01UL << GTZC_CFGR1_UART8_Pos)
19695 #define GTZC_CFGR1_UART9_Pos                (28U)
19696 #define GTZC_CFGR1_UART9_Msk                (0x01UL << GTZC_CFGR1_UART9_Pos)
19697 #define GTZC_CFGR1_UART12_Pos               (29U)
19698 #define GTZC_CFGR1_UART12_Msk               (0x01UL << GTZC_CFGR1_UART12_Pos)
19699 #define GTZC_CFGR1_DTS_Pos                  (30U)
19700 #define GTZC_CFGR1_DTS_Msk                  (0x01UL << GTZC_CFGR1_DTS_Pos)
19701 #define GTZC_CFGR1_LPTIM2_Pos               (31U)
19702 #define GTZC_CFGR1_LPTIM2_Msk               (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
19703 
19704 
19705 /***************  Bits definition for register x=2 (TZSC1) *************/
19706 #define GTZC_CFGR2_FDCAN1_Pos               (0U)
19707 #define GTZC_CFGR2_FDCAN1_Msk               (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
19708 #define GTZC_CFGR2_FDCAN2_Pos               (1U)
19709 #define GTZC_CFGR2_FDCAN2_Msk               (0x01UL << GTZC_CFGR2_FDCAN2_Pos)
19710 #define GTZC_CFGR2_UCPD1_Pos                (2U)
19711 #define GTZC_CFGR2_UCPD1_Msk                (0x01UL << GTZC_CFGR2_UCPD1_Pos)
19712 #define GTZC_CFGR2_TIM1_Pos                 (8U)
19713 #define GTZC_CFGR2_TIM1_Msk                 (0x01UL << GTZC_CFGR2_TIM1_Pos)
19714 #define GTZC_CFGR2_SPI1_Pos                 (9U)
19715 #define GTZC_CFGR2_SPI1_Msk                 (0x01UL << GTZC_CFGR2_SPI1_Pos)
19716 #define GTZC_CFGR2_TIM8_Pos                 (10U)
19717 #define GTZC_CFGR2_TIM8_Msk                 (0x01UL << GTZC_CFGR2_TIM8_Pos)
19718 #define GTZC_CFGR2_USART1_Pos               (11U)
19719 #define GTZC_CFGR2_USART1_Msk               (0x01UL << GTZC_CFGR2_USART1_Pos)
19720 #define GTZC_CFGR2_TIM15_Pos                (12U)
19721 #define GTZC_CFGR2_TIM15_Msk                (0x01UL << GTZC_CFGR2_TIM15_Pos)
19722 #define GTZC_CFGR2_TIM16_Pos                (13U)
19723 #define GTZC_CFGR2_TIM16_Msk                (0x01UL << GTZC_CFGR2_TIM16_Pos)
19724 #define GTZC_CFGR2_TIM17_Pos                (14U)
19725 #define GTZC_CFGR2_TIM17_Msk                (0x01UL << GTZC_CFGR2_TIM17_Pos)
19726 #define GTZC_CFGR2_SPI4_Pos                 (15U)
19727 #define GTZC_CFGR2_SPI4_Msk                 (0x01UL << GTZC_CFGR2_SPI4_Pos)
19728 #define GTZC_CFGR2_SPI6_Pos                 (16U)
19729 #define GTZC_CFGR2_SPI6_Msk                 (0x01UL << GTZC_CFGR2_SPI6_Pos)
19730 #define GTZC_CFGR2_SAI1_Pos                 (17U)
19731 #define GTZC_CFGR2_SAI1_Msk                 (0x01UL << GTZC_CFGR2_SAI1_Pos)
19732 #define GTZC_CFGR2_SAI2_Pos                 (18U)
19733 #define GTZC_CFGR2_SAI2_Msk                 (0x01UL << GTZC_CFGR2_SAI2_Pos)
19734 #define GTZC_CFGR2_USB_Pos                  (19U)
19735 #define GTZC_CFGR2_USB_Msk                  (0x01UL << GTZC_CFGR2_USB_Pos)
19736 #define GTZC_CFGR2_SPI5_Pos                 (24U)
19737 #define GTZC_CFGR2_SPI5_Msk                 (0x01UL << GTZC_CFGR2_SPI5_Pos)
19738 #define GTZC_CFGR2_LPUART1_Pos              (25U)
19739 #define GTZC_CFGR2_LPUART1_Msk              (0x01UL << GTZC_CFGR2_LPUART1_Pos)
19740 #define GTZC_CFGR2_I2C3_Pos                 (26U)
19741 #define GTZC_CFGR2_I2C3_Msk                 (0x01UL << GTZC_CFGR2_I2C3_Pos)
19742 #define GTZC_CFGR2_I2C4_Pos                 (27U)
19743 #define GTZC_CFGR2_I2C4_Msk                 (0x01UL << GTZC_CFGR2_I2C4_Pos)
19744 #define GTZC_CFGR2_LPTIM1_Pos               (28U)
19745 #define GTZC_CFGR2_LPTIM1_Msk               (0x01UL << GTZC_CFGR2_LPTIM1_Pos)
19746 #define GTZC_CFGR2_LPTIM3_Pos               (29U)
19747 #define GTZC_CFGR2_LPTIM3_Msk               (0x01UL << GTZC_CFGR2_LPTIM3_Pos)
19748 #define GTZC_CFGR2_LPTIM4_Pos               (30U)
19749 #define GTZC_CFGR2_LPTIM4_Msk               (0x01UL << GTZC_CFGR2_LPTIM4_Pos)
19750 #define GTZC_CFGR2_LPTIM5_Pos               (31U)
19751 #define GTZC_CFGR2_LPTIM5_Msk               (0x01UL << GTZC_CFGR2_LPTIM5_Pos)
19752 
19753 /***************  Bits definition for register x=3 (TZSC1) *************/
19754 #define GTZC_CFGR3_LPTIM6_Pos               (0U)
19755 #define GTZC_CFGR3_LPTIM6_Msk               (0x01UL << GTZC_CFGR3_LPTIM6_Pos)
19756 #define GTZC_CFGR3_VREFBUF_Pos              (1U)
19757 #define GTZC_CFGR3_VREFBUF_Msk              (0x01UL << GTZC_CFGR3_VREFBUF_Pos)
19758 #define GTZC_CFGR3_CRC_Pos                  (8U)
19759 #define GTZC_CFGR3_CRC_Msk                  (0x01UL << GTZC_CFGR3_CRC_Pos)
19760 #define GTZC_CFGR3_CORDIC_Pos               (9U)
19761 #define GTZC_CFGR3_CORDIC_Msk               (0x01UL << GTZC_CFGR3_CORDIC_Pos)
19762 #define GTZC_CFGR3_FMAC_Pos                 (10U)
19763 #define GTZC_CFGR3_FMAC_Msk                 (0x01UL << GTZC_CFGR3_FMAC_Pos)
19764 #define GTZC_CFGR3_ETHERNET_Pos             (11U)
19765 #define GTZC_CFGR3_ETHERNET_Msk             (0x01UL << GTZC_CFGR3_ETHERNET_Pos)
19766 #define GTZC_CFGR3_ICACHE_REG_Pos           (12U)
19767 #define GTZC_CFGR3_ICACHE_REG_Msk           (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos)
19768 #define GTZC_CFGR3_DCACHE1_REG_Pos          (13U)
19769 #define GTZC_CFGR3_DCACHE1_REG_Msk          (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos)
19770 #define GTZC_CFGR3_ADC12_Pos                (14U)
19771 #define GTZC_CFGR3_ADC12_Msk                (0x01UL << GTZC_CFGR3_ADC12_Pos)
19772 #define GTZC_CFGR3_DCMI_PSSI_Pos            (15U)
19773 #define GTZC_CFGR3_DCMI_PSSI_Msk            (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos)
19774 #define GTZC_CFGR3_AES_Pos                  (16U)
19775 #define GTZC_CFGR3_AES_Msk                  (0x01UL << GTZC_CFGR3_AES_Pos)
19776 #define GTZC_CFGR3_HASH_Pos                 (17U)
19777 #define GTZC_CFGR3_HASH_Msk                 (0x01UL << GTZC_CFGR3_HASH_Pos)
19778 #define GTZC_CFGR3_RNG_Pos                  (18U)
19779 #define GTZC_CFGR3_RNG_Msk                  (0x01UL << GTZC_CFGR3_RNG_Pos)
19780 #define GTZC_CFGR3_SAES_Pos                 (19U)
19781 #define GTZC_CFGR3_SAES_Msk                 (0x01UL << GTZC_CFGR3_SAES_Pos)
19782 #define GTZC_CFGR3_PKA_Pos                  (20U)
19783 #define GTZC_CFGR3_PKA_Msk                  (0x01UL << GTZC_CFGR3_PKA_Pos)
19784 #define GTZC_CFGR3_SDMMC1_Pos               (21U)
19785 #define GTZC_CFGR3_SDMMC1_Msk               (0x01UL << GTZC_CFGR3_SDMMC1_Pos)
19786 #define GTZC_CFGR3_SDMMC2_Pos               (22U)
19787 #define GTZC_CFGR3_SDMMC2_Msk               (0x01UL << GTZC_CFGR3_SDMMC2_Pos)
19788 #define GTZC_CFGR3_FMC_REG_Pos              (23U)
19789 #define GTZC_CFGR3_FMC_REG_Msk              (0x01UL << GTZC_CFGR3_FMC_REG_Pos)
19790 #define GTZC_CFGR3_OCTOSPI1_Pos             (24U)
19791 #define GTZC_CFGR3_OCTOSPI1_Msk             (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos)
19792 #define GTZC_CFGR3_RAMCFG_Pos               (26U)
19793 #define GTZC_CFGR3_RAMCFG_Msk               (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
19794 
19795 /***************  Bits definition for register x=4 (TZSC1) *************/
19796 #define GTZC_CFGR4_GPDMA1_Pos               (0U)
19797 #define GTZC_CFGR4_GPDMA1_Msk               (0x01UL << GTZC_CFGR4_GPDMA1_Pos)
19798 #define GTZC_CFGR4_GPDMA2_Pos               (1U)
19799 #define GTZC_CFGR4_GPDMA2_Msk               (0x01UL << GTZC_CFGR4_GPDMA2_Pos)
19800 #define GTZC_CFGR4_FLASH_Pos                (2U)
19801 #define GTZC_CFGR4_FLASH_Msk                (0x01UL << GTZC_CFGR4_FLASH_Pos)
19802 #define GTZC_CFGR4_FLASH_REG_Pos            (3U)
19803 #define GTZC_CFGR4_FLASH_REG_Msk            (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
19804 #define GTZC_CFGR4_OTFDEC1_Pos              (4U)
19805 #define GTZC_CFGR4_OTFDEC1_Msk              (0x01UL << GTZC_CFGR4_OTFDEC1_Pos)
19806 #define GTZC_CFGR4_SBS_Pos                  (6U)
19807 #define GTZC_CFGR4_SBS_Msk                  (0x01UL << GTZC_CFGR4_SBS_Pos)
19808 #define GTZC_CFGR4_RTC_Pos                  (7U)
19809 #define GTZC_CFGR4_RTC_Msk                  (0x01UL << GTZC_CFGR4_RTC_Pos)
19810 #define GTZC_CFGR4_TAMP_Pos                 (8U)
19811 #define GTZC_CFGR4_TAMP_Msk                 (0x01UL << GTZC_CFGR4_TAMP_Pos)
19812 #define GTZC_CFGR4_PWR_Pos                  (9U)
19813 #define GTZC_CFGR4_PWR_Msk                  (0x01UL << GTZC_CFGR4_PWR_Pos)
19814 #define GTZC_CFGR4_RCC_Pos                  (10U)
19815 #define GTZC_CFGR4_RCC_Msk                  (0x01UL << GTZC_CFGR4_RCC_Pos)
19816 #define GTZC_CFGR4_EXTI_Pos                 (11U)
19817 #define GTZC_CFGR4_EXTI_Msk                 (0x01UL << GTZC_CFGR4_EXTI_Pos)
19818 #define GTZC_CFGR4_TZSC_Pos                 (16U)
19819 #define GTZC_CFGR4_TZSC_Msk                 (0x01UL << GTZC_CFGR4_TZSC_Pos)
19820 #define GTZC_CFGR4_TZIC_Pos                 (17U)
19821 #define GTZC_CFGR4_TZIC_Msk                 (0x01UL << GTZC_CFGR4_TZIC_Pos)
19822 #define GTZC_CFGR4_OCTOSPI1_MEM_Pos         (18U)
19823 #define GTZC_CFGR4_OCTOSPI1_MEM_Msk         (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos)
19824 #define GTZC_CFGR4_FMC_MEM_Pos              (19U)
19825 #define GTZC_CFGR4_FMC_MEM_Msk              (0x01UL << GTZC_CFGR4_FMC_MEM_Pos)
19826 #define GTZC_CFGR4_BKPSRAM_Pos              (20U)
19827 #define GTZC_CFGR4_BKPSRAM_Msk              (0x01UL << GTZC_CFGR4_BKPSRAM_Pos)
19828 #define GTZC_CFGR4_SRAM1_Pos                (24U)
19829 #define GTZC_CFGR4_SRAM1_Msk                (0x01UL << GTZC_CFGR4_SRAM1_Pos)
19830 #define GTZC_CFGR4_MPCBB1_REG_Pos           (25U)
19831 #define GTZC_CFGR4_MPCBB1_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
19832 #define GTZC_CFGR4_SRAM2_Pos                (26U)
19833 #define GTZC_CFGR4_SRAM2_Msk                (0x01UL << GTZC_CFGR4_SRAM2_Pos)
19834 #define GTZC_CFGR4_MPCBB2_REG_Pos           (27U)
19835 #define GTZC_CFGR4_MPCBB2_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos)
19836 #define GTZC_CFGR4_SRAM3_Pos                (28U)
19837 #define GTZC_CFGR4_SRAM3_Msk                (0x01UL << GTZC_CFGR4_SRAM3_Pos)
19838 #define GTZC_CFGR4_MPCBB3_REG_Pos           (29U)
19839 #define GTZC_CFGR4_MPCBB3_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos)
19840 
19841 /*******************  Bits definition for GTZC_TZSC1_SECCFGR1 register  ***************/
19842 #define GTZC_TZSC1_SECCFGR1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
19843 #define GTZC_TZSC1_SECCFGR1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
19844 #define GTZC_TZSC1_SECCFGR1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
19845 #define GTZC_TZSC1_SECCFGR1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
19846 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
19847 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
19848 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
19849 #define GTZC_TZSC1_SECCFGR1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
19850 #define GTZC_TZSC1_SECCFGR1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
19851 #define GTZC_TZSC1_SECCFGR1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
19852 #define GTZC_TZSC1_SECCFGR1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
19853 #define GTZC_TZSC1_SECCFGR1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
19854 #define GTZC_TZSC1_SECCFGR1_TIM12_Pos           GTZC_CFGR1_TIM12_Pos
19855 #define GTZC_TZSC1_SECCFGR1_TIM12_Msk           GTZC_CFGR1_TIM12_Msk
19856 #define GTZC_TZSC1_SECCFGR1_TIM13_Pos           GTZC_CFGR1_TIM13_Pos
19857 #define GTZC_TZSC1_SECCFGR1_TIM13_Msk           GTZC_CFGR1_TIM13_Msk
19858 #define GTZC_TZSC1_SECCFGR1_TIM14_Pos           GTZC_CFGR1_TIM14_Pos
19859 #define GTZC_TZSC1_SECCFGR1_TIM14_Msk           GTZC_CFGR1_TIM14_Msk
19860 #define GTZC_TZSC1_SECCFGR1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
19861 #define GTZC_TZSC1_SECCFGR1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
19862 #define GTZC_TZSC1_SECCFGR1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
19863 #define GTZC_TZSC1_SECCFGR1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
19864 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
19865 #define GTZC_TZSC1_SECCFGR1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
19866 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
19867 #define GTZC_TZSC1_SECCFGR1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
19868 #define GTZC_TZSC1_SECCFGR1_USART2_Pos          GTZC_CFGR1_USART2_Pos
19869 #define GTZC_TZSC1_SECCFGR1_USART2_Msk          GTZC_CFGR1_USART2_Msk
19870 #define GTZC_TZSC1_SECCFGR1_USART3_Pos          GTZC_CFGR1_USART3_Pos
19871 #define GTZC_TZSC1_SECCFGR1_USART3_Msk          GTZC_CFGR1_USART3_Msk
19872 #define GTZC_TZSC1_SECCFGR1_UART4_Pos           GTZC_CFGR1_UART4_Pos
19873 #define GTZC_TZSC1_SECCFGR1_UART4_Msk           GTZC_CFGR1_UART4_Msk
19874 #define GTZC_TZSC1_SECCFGR1_UART5_Pos           GTZC_CFGR1_UART5_Pos
19875 #define GTZC_TZSC1_SECCFGR1_UART5_Msk           GTZC_CFGR1_UART5_Msk
19876 #define GTZC_TZSC1_SECCFGR1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
19877 #define GTZC_TZSC1_SECCFGR1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
19878 #define GTZC_TZSC1_SECCFGR1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
19879 #define GTZC_TZSC1_SECCFGR1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
19880 #define GTZC_TZSC1_SECCFGR1_I3C1_Pos            GTZC_CFGR1_I3C1_Pos
19881 #define GTZC_TZSC1_SECCFGR1_I3C1_Msk            GTZC_CFGR1_I3C1_Msk
19882 #define GTZC_TZSC1_SECCFGR1_CRS_Pos             GTZC_CFGR1_CRS_Pos
19883 #define GTZC_TZSC1_SECCFGR1_CRS_Msk             GTZC_CFGR1_CRS_Msk
19884 #define GTZC_TZSC1_SECCFGR1_USART6_Pos          GTZC_CFGR1_USART6_Pos
19885 #define GTZC_TZSC1_SECCFGR1_USART6_Msk          GTZC_CFGR1_USART6_Msk
19886 #define GTZC_TZSC1_SECCFGR1_USART10_Pos         GTZC_CFGR1_USART10_Pos
19887 #define GTZC_TZSC1_SECCFGR1_USART10_Msk         GTZC_CFGR1_USART10_Msk
19888 #define GTZC_TZSC1_SECCFGR1_USART11_Pos         GTZC_CFGR1_USART11_Pos
19889 #define GTZC_TZSC1_SECCFGR1_USART11_Msk         GTZC_CFGR1_USART11_Msk
19890 #define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos         GTZC_CFGR1_HDMICEC_Pos
19891 #define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk         GTZC_CFGR1_HDMICEC_Msk
19892 #define GTZC_TZSC1_SECCFGR1_DAC12_Pos           GTZC_CFGR1_DAC12_Pos
19893 #define GTZC_TZSC1_SECCFGR1_DAC12_Msk           GTZC_CFGR1_DAC12_Msk
19894 #define GTZC_TZSC1_SECCFGR1_UART7_Pos           GTZC_CFGR1_UART7_Pos
19895 #define GTZC_TZSC1_SECCFGR1_UART7_Msk           GTZC_CFGR1_UART7_Msk
19896 #define GTZC_TZSC1_SECCFGR1_UART8_Pos           GTZC_CFGR1_UART8_Pos
19897 #define GTZC_TZSC1_SECCFGR1_UART8_Msk           GTZC_CFGR1_UART8_Msk
19898 #define GTZC_TZSC1_SECCFGR1_UART9_Pos           GTZC_CFGR1_UART9_Pos
19899 #define GTZC_TZSC1_SECCFGR1_UART9_Msk           GTZC_CFGR1_UART9_Msk
19900 #define GTZC_TZSC1_SECCFGR1_UART12_Pos          GTZC_CFGR1_UART12_Pos
19901 #define GTZC_TZSC1_SECCFGR1_UART12_Msk          GTZC_CFGR1_UART12_Msk
19902 #define GTZC_TZSC1_SECCFGR1_DTS_Pos             GTZC_CFGR1_DTS_Pos
19903 #define GTZC_TZSC1_SECCFGR1_DTS_Msk             GTZC_CFGR1_DTS_Msk
19904 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
19905 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
19906 
19907 
19908 /*******************  Bits definition for GTZC_TZSC_SECCFGR2 register  ***************/
19909 #define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos          GTZC_CFGR2_FDCAN1_Pos
19910 #define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk          GTZC_CFGR2_FDCAN1_Msk
19911 #define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos          GTZC_CFGR2_FDCAN2_Pos
19912 #define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk          GTZC_CFGR2_FDCAN2_Msk
19913 #define GTZC_TZSC1_SECCFGR2_UCPD_Pos            GTZC_CFGR2_UCPD_Pos
19914 #define GTZC_TZSC1_SECCFGR2_UCPD_Msk            GTZC_CFGR2_UCPD_Msk
19915 #define GTZC_TZSC1_SECCFGR2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
19916 #define GTZC_TZSC1_SECCFGR2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
19917 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
19918 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
19919 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
19920 #define GTZC_TZSC1_SECCFGR2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
19921 #define GTZC_TZSC1_SECCFGR2_USART1_Pos          GTZC_CFGR2_USART1_Pos
19922 #define GTZC_TZSC1_SECCFGR2_USART1_Msk          GTZC_CFGR2_USART1_Msk
19923 #define GTZC_TZSC1_SECCFGR2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
19924 #define GTZC_TZSC1_SECCFGR2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
19925 #define GTZC_TZSC1_SECCFGR2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
19926 #define GTZC_TZSC1_SECCFGR2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
19927 #define GTZC_TZSC1_SECCFGR2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
19928 #define GTZC_TZSC1_SECCFGR2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
19929 #define GTZC_TZSC1_SECCFGR2_SPI4_Pos            GTZC_CFGR2_SPI4_Pos
19930 #define GTZC_TZSC1_SECCFGR2_SPI4_Msk            GTZC_CFGR2_SPI4_Msk
19931 #define GTZC_TZSC1_SECCFGR2_SPI6_Pos            GTZC_CFGR2_SPI6_Pos
19932 #define GTZC_TZSC1_SECCFGR2_SPI6_Msk            GTZC_CFGR2_SPI6_Msk
19933 #define GTZC_TZSC1_SECCFGR2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
19934 #define GTZC_TZSC1_SECCFGR2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
19935 #define GTZC_TZSC1_SECCFGR2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
19936 #define GTZC_TZSC1_SECCFGR2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
19937 #define GTZC_TZSC1_SECCFGR2_USB_Pos             GTZC_CFGR2_USB_Pos
19938 #define GTZC_TZSC1_SECCFGR2_USB_Msk             GTZC_CFGR2_USB_Msk
19939 #define GTZC_TZSC1_SECCFGR2_SPI5_Pos            GTZC_CFGR2_SPI5_Pos
19940 #define GTZC_TZSC1_SECCFGR2_SPI5_Msk            GTZC_CFGR2_SPI5_Msk
19941 #define GTZC_TZSC1_SECCFGR2_LPUART1_Pos         GTZC_CFGR2_LPUART1_Pos
19942 #define GTZC_TZSC1_SECCFGR2_LPUART1_Msk         GTZC_CFGR2_LPUART1_Msk
19943 #define GTZC_TZSC1_SECCFGR2_I2C3_Pos            GTZC_CFGR2_I2C3_Pos
19944 #define GTZC_TZSC1_SECCFGR2_I2C3_Msk            GTZC_CFGR2_I2C3_Msk
19945 #define GTZC_TZSC1_SECCFGR2_I2C4_Pos            GTZC_CFGR2_I2C4_Pos
19946 #define GTZC_TZSC1_SECCFGR2_I2C4_Msk            GTZC_CFGR2_I2C4_Msk
19947 #define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos          GTZC_CFGR2_LPTIM1_Pos
19948 #define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk          GTZC_CFGR2_LPTIM1_Msk
19949 #define GTZC_TZSC1_SECCFGR2_LPTIM3_Pos          GTZC_CFGR2_LPTIM3_Pos
19950 #define GTZC_TZSC1_SECCFGR2_LPTIM3_Msk          GTZC_CFGR2_LPTIM3_Msk
19951 #define GTZC_TZSC1_SECCFGR2_LPTIM4_Pos          GTZC_CFGR2_LPTIM4_Pos
19952 #define GTZC_TZSC1_SECCFGR2_LPTIM4_Msk          GTZC_CFGR2_LPTIM4_Msk
19953 #define GTZC_TZSC1_SECCFGR2_LPTIM5_Pos          GTZC_CFGR2_LPTIM5_Pos
19954 #define GTZC_TZSC1_SECCFGR2_LPTIM5_Msk          GTZC_CFGR2_LPTIM5_Msk
19955 
19956 /*******************  Bits definition for GTZC_TZSC_SECCFGR3 register  ***************/
19957 #define GTZC_TZSC1_SECCFGR3_LPTIM6_Pos          GTZC_CFGR3_LPTIM6_Pos
19958 #define GTZC_TZSC1_SECCFGR3_LPTIM6_Msk          GTZC_CFGR3_LPTIM6_Msk
19959 #define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos         GTZC_CFGR3_VREFBUF_Pos
19960 #define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk         GTZC_CFGR3_VREFBUF_Msk
19961 #define GTZC_TZSC1_SECCFGR3_CRC_Pos             GTZC_CFGR3_CRC_Pos
19962 #define GTZC_TZSC1_SECCFGR3_CRC_Msk             GTZC_CFGR3_CRC_Msk
19963 #define GTZC_TZSC1_SECCFGR3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
19964 #define GTZC_TZSC1_SECCFGR3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
19965 #define GTZC_TZSC1_SECCFGR3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
19966 #define GTZC_TZSC1_SECCFGR3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
19967 #define GTZC_TZSC1_SECCFGR3_ETHERNET_Pos        GTZC_CFGR3_ETHERNET_Pos
19968 #define GTZC_TZSC1_SECCFGR3_ETHERNET_Msk        GTZC_CFGR3_ETHERNET_Msk
19969 #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
19970 #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
19971 #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
19972 #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
19973 #define GTZC_TZSC1_SECCFGR3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
19974 #define GTZC_TZSC1_SECCFGR3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
19975 #define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos       GTZC_CFGR3_DCMI_PSSI_Pos
19976 #define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk       GTZC_CFGR3_DCMI_PSSI_Msk
19977 #define GTZC_TZSC1_SECCFGR3_AES_Pos             GTZC_CFGR3_AES_Pos
19978 #define GTZC_TZSC1_SECCFGR3_AES_Msk             GTZC_CFGR3_AES_Msk
19979 #define GTZC_TZSC1_SECCFGR3_HASH_Pos            GTZC_CFGR3_HASH_Pos
19980 #define GTZC_TZSC1_SECCFGR3_HASH_Msk            GTZC_CFGR3_HASH_Msk
19981 #define GTZC_TZSC1_SECCFGR3_RNG_Pos             GTZC_CFGR3_RNG_Pos
19982 #define GTZC_TZSC1_SECCFGR3_RNG_Msk             GTZC_CFGR3_RNG_Msk
19983 #define GTZC_TZSC1_SECCFGR3_SAES_Pos            GTZC_CFGR3_SAES_Pos
19984 #define GTZC_TZSC1_SECCFGR3_SAES_Msk            GTZC_CFGR3_SAES_Msk
19985 #define GTZC_TZSC1_SECCFGR3_PKA_Pos             GTZC_CFGR3_PKA_Pos
19986 #define GTZC_TZSC1_SECCFGR3_PKA_Msk             GTZC_CFGR3_PKA_Msk
19987 #define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
19988 #define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
19989 #define GTZC_TZSC1_SECCFGR3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
19990 #define GTZC_TZSC1_SECCFGR3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
19991 #define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos         GTZC_CFGR3_FMC_REG_Pos
19992 #define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk         GTZC_CFGR3_FMC_REG_Msk
19993 #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos        GTZC_CFGR3_OCTOSPI1_Pos
19994 #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk        GTZC_CFGR3_OCTOSPI1_Msk
19995 #define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
19996 #define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
19997 
19998 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR1 register  ***************/
19999 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos           GTZC_CFGR1_TIM2_Pos
20000 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk           GTZC_CFGR1_TIM2_Msk
20001 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos           GTZC_CFGR1_TIM3_Pos
20002 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk           GTZC_CFGR1_TIM3_Msk
20003 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos           GTZC_CFGR1_TIM4_Pos
20004 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk           GTZC_CFGR1_TIM4_Msk
20005 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos           GTZC_CFGR1_TIM5_Pos
20006 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk           GTZC_CFGR1_TIM5_Msk
20007 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos           GTZC_CFGR1_TIM6_Pos
20008 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk           GTZC_CFGR1_TIM6_Msk
20009 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos           GTZC_CFGR1_TIM7_Pos
20010 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk           GTZC_CFGR1_TIM7_Msk
20011 #define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos          GTZC_CFGR1_TIM12_Pos
20012 #define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk          GTZC_CFGR1_TIM12_Msk
20013 #define GTZC_TZSC1_PRIVCFGR1_TIM13_Pos          GTZC_CFGR1_TIM13_Pos
20014 #define GTZC_TZSC1_PRIVCFGR1_TIM13_Msk          GTZC_CFGR1_TIM13_Msk
20015 #define GTZC_TZSC1_PRIVCFGR1_TIM14_Pos          GTZC_CFGR1_TIM14_Pos
20016 #define GTZC_TZSC1_PRIVCFGR1_TIM14_Msk          GTZC_CFGR1_TIM14_Msk
20017 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos           GTZC_CFGR1_WWDG_Pos
20018 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk           GTZC_CFGR1_WWDG_Msk
20019 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos           GTZC_CFGR1_IWDG_Pos
20020 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk           GTZC_CFGR1_IWDG_Msk
20021 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos           GTZC_CFGR1_SPI2_Pos
20022 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk           GTZC_CFGR1_SPI2_Msk
20023 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos           GTZC_CFGR1_SPI3_Pos
20024 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk           GTZC_CFGR1_SPI3_Msk
20025 #define GTZC_TZSC1_PRIVCFGR1_USART2_Pos         GTZC_CFGR1_USART2_Pos
20026 #define GTZC_TZSC1_PRIVCFGR1_USART2_Msk         GTZC_CFGR1_USART2_Msk
20027 #define GTZC_TZSC1_PRIVCFGR1_USART3_Pos         GTZC_CFGR1_USART3_Pos
20028 #define GTZC_TZSC1_PRIVCFGR1_USART3_Msk         GTZC_CFGR1_USART3_Msk
20029 #define GTZC_TZSC1_PRIVCFGR1_UART4_Pos          GTZC_CFGR1_UART4_Pos
20030 #define GTZC_TZSC1_PRIVCFGR1_UART4_Msk          GTZC_CFGR1_UART4_Msk
20031 #define GTZC_TZSC1_PRIVCFGR1_UART5_Pos          GTZC_CFGR1_UART5_Pos
20032 #define GTZC_TZSC1_PRIVCFGR1_UART5_Msk          GTZC_CFGR1_UART5_Msk
20033 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos           GTZC_CFGR1_I2C1_Pos
20034 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk           GTZC_CFGR1_I2C1_Msk
20035 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos           GTZC_CFGR1_I2C2_Pos
20036 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk           GTZC_CFGR1_I2C2_Msk
20037 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos           GTZC_CFGR1_I3C1_Pos
20038 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk           GTZC_CFGR1_I3C1_Msk
20039 #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos            GTZC_CFGR1_CRS_Pos
20040 #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk            GTZC_CFGR1_CRS_Msk
20041 #define GTZC_TZSC1_PRIVCFGR1_USART6_Pos         GTZC_CFGR1_USART6_Pos
20042 #define GTZC_TZSC1_PRIVCFGR1_USART6_Msk         GTZC_CFGR1_USART6_Msk
20043 #define GTZC_TZSC1_PRIVCFGR1_USART10_Pos        GTZC_CFGR1_USART10_Pos
20044 #define GTZC_TZSC1_PRIVCFGR1_USART10_Msk        GTZC_CFGR1_USART10_Msk
20045 #define GTZC_TZSC1_PRIVCFGR1_USART11_Pos        GTZC_CFGR1_USART11_Pos
20046 #define GTZC_TZSC1_PRIVCFGR1_USART11_Msk        GTZC_CFGR1_USART11_Msk
20047 #define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos        GTZC_CFGR1_HDMICEC_Pos
20048 #define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk        GTZC_CFGR1_HDMICEC_Msk
20049 #define GTZC_TZSC1_PRIVCFGR1_DAC12_Pos          GTZC_CFGR1_DAC12_Pos
20050 #define GTZC_TZSC1_PRIVCFGR1_DAC12_Msk          GTZC_CFGR1_DAC12_Msk
20051 #define GTZC_TZSC1_PRIVCFGR1_UART7_Pos          GTZC_CFGR1_UART7_Pos
20052 #define GTZC_TZSC1_PRIVCFGR1_UART7_Msk          GTZC_CFGR1_UART7_Msk
20053 #define GTZC_TZSC1_PRIVCFGR1_UART8_Pos          GTZC_CFGR1_UART8_Pos
20054 #define GTZC_TZSC1_PRIVCFGR1_UART8_Msk          GTZC_CFGR1_UART8_Msk
20055 #define GTZC_TZSC1_PRIVCFGR1_UART9_Pos          GTZC_CFGR1_UART9_Pos
20056 #define GTZC_TZSC1_PRIVCFGR1_UART9_Msk          GTZC_CFGR1_UART9_Msk
20057 #define GTZC_TZSC1_PRIVCFGR1_UART12_Pos         GTZC_CFGR1_UART12_Pos
20058 #define GTZC_TZSC1_PRIVCFGR1_UART12Msk          GTZC_CFGR1_UART12_Msk
20059 #define GTZC_TZSC1_PRIVCFGR1_DTS_Pos            GTZC_CFGR1_DTS_Pos
20060 #define GTZC_TZSC1_PRIVCFGR1_DTS_Msk            GTZC_CFGR1_DTS_Msk
20061 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos         GTZC_CFGR1_LPTIM2_Pos
20062 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk         GTZC_CFGR1_LPTIM2_Msk
20063 
20064 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR2 register  ***************/
20065 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos         GTZC_CFGR2_FDCAN1_Pos
20066 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk         GTZC_CFGR2_FDCAN1_Msk
20067 #define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos         GTZC_CFGR2_FDCAN2_Pos
20068 #define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk         GTZC_CFGR2_FDCAN2_Msk
20069 #define GTZC_TZSC1_PRIVCFGR2_UCPD_Pos           GTZC_CFGR2_UCPD_Pos
20070 #define GTZC_TZSC1_PRIVCFGR2_UCPD_Msk           GTZC_CFGR2_UCPD_Msk
20071 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos           GTZC_CFGR2_TIM1_Pos
20072 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk           GTZC_CFGR2_TIM1_Msk
20073 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos           GTZC_CFGR2_SPI1_Pos
20074 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk           GTZC_CFGR2_SPI1_Msk
20075 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos           GTZC_CFGR2_TIM8_Pos
20076 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk           GTZC_CFGR2_TIM8_Msk
20077 #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos         GTZC_CFGR2_USART1_Pos
20078 #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk         GTZC_CFGR2_USART1_Msk
20079 #define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos          GTZC_CFGR2_TIM15_Pos
20080 #define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk          GTZC_CFGR2_TIM15_Msk
20081 #define GTZC_TZSC1_PRIVCFGR2_TIM16_Pos          GTZC_CFGR2_TIM16_Pos
20082 #define GTZC_TZSC1_PRIVCFGR2_TIM16_Msk          GTZC_CFGR2_TIM16_Msk
20083 #define GTZC_TZSC1_PRIVCFGR2_TIM17_Pos          GTZC_CFGR2_TIM17_Pos
20084 #define GTZC_TZSC1_PRIVCFGR2_TIM17_Msk          GTZC_CFGR2_TIM17_Msk
20085 #define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos           GTZC_CFGR2_SPI4_Pos
20086 #define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk           GTZC_CFGR2_SPI4_Msk
20087 #define GTZC_TZSC1_PRIVCFGR2_SPI6_Pos           GTZC_CFGR2_SPI6_Pos
20088 #define GTZC_TZSC1_PRIVCFGR2_SPI6_Msk           GTZC_CFGR2_SPI6_Msk
20089 #define GTZC_TZSC1_PRIVCFGR2_SAI1_Pos           GTZC_CFGR2_SAI1_Pos
20090 #define GTZC_TZSC1_PRIVCFGR2_SAI1_Msk           GTZC_CFGR2_SAI1_Msk
20091 #define GTZC_TZSC1_PRIVCFGR2_SAI2_Pos           GTZC_CFGR2_SAI2_Pos
20092 #define GTZC_TZSC1_PRIVCFGR2_SAI2_Msk           GTZC_CFGR2_SAI2_Msk
20093 #define GTZC_TZSC1_PRIVCFGR2_USB_Pos            GTZC_CFGR2_USB_Pos
20094 #define GTZC_TZSC1_PRIVCFGR2_USB_Msk            GTZC_CFGR2_USB_Msk
20095 #define GTZC_TZSC1_PRIVCFGR2_SPI5_Pos           GTZC_CFGR2_SPI5_Pos
20096 #define GTZC_TZSC1_PRIVCFGR2_SPI5_Msk           GTZC_CFGR2_SPI5_Msk
20097 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos        GTZC_CFGR2_LPUART1_Pos
20098 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk        GTZC_CFGR2_LPUART1_Msk
20099 #define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos           GTZC_CFGR2_I2C3_Pos
20100 #define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk           GTZC_CFGR2_I2C3_Msk
20101 #define GTZC_TZSC1_PRIVCFGR2_I2C4_Pos           GTZC_CFGR2_I2C4_Pos
20102 #define GTZC_TZSC1_PRIVCFGR2_I2C4_Msk           GTZC_CFGR2_I2C4_Msk
20103 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos         GTZC_CFGR2_LPTIM1_Pos
20104 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk         GTZC_CFGR2_LPTIM1_Msk
20105 #define GTZC_TZSC1_PRIVCFGR2_LPTIM3_Pos         GTZC_CFGR2_LPTIM3_Pos
20106 #define GTZC_TZSC1_PRIVCFGR2_LPTIM3_Msk         GTZC_CFGR2_LPTIM3_Msk
20107 #define GTZC_TZSC1_PRIVCFGR2_LPTIM4_Pos         GTZC_CFGR2_LPTIM4_Pos
20108 #define GTZC_TZSC1_PRIVCFGR2_LPTIM4_Msk         GTZC_CFGR2_LPTIM4_Msk
20109 #define GTZC_TZSC1_PRIVCFGR2_LPTIM5_Pos         GTZC_CFGR2_LPTIM5_Pos
20110 #define GTZC_TZSC1_PRIVCFGR2_LPTIM5_Msk         GTZC_CFGR2_LPTIM5_Msk
20111 
20112 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR3 register  ***************/
20113 #define GTZC_TZSC1_PRIVCFGR3_LPTIM6_Pos         GTZC_CFGR3_LPTIM6_Pos
20114 #define GTZC_TZSC1_PRIVCFGR3_LPTIM6_Msk         GTZC_CFGR3_LPTIM6_Msk
20115 #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos        GTZC_CFGR3_VREFBUF_Pos
20116 #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk        GTZC_CFGR3_VREFBUF_Msk
20117 #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos            GTZC_CFGR3_CRC_Pos
20118 #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk            GTZC_CFGR3_CRC_Msk
20119 #define GTZC_TZSC1_PRIVCFGR3_CORDIC_Pos         GTZC_CFGR3_CORDIC_Pos
20120 #define GTZC_TZSC1_PRIVCFGR3_CORDIC_Msk         GTZC_CFGR3_CORDIC_Msk
20121 #define GTZC_TZSC1_PRIVCFGR3_FMAC_Pos           GTZC_CFGR3_FMAC_Pos
20122 #define GTZC_TZSC1_PRIVCFGR3_FMAC_Msk           GTZC_CFGR3_FMAC_Msk
20123 #define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Pos       GTZC_CFGR3_ETHERNET_Pos
20124 #define GTZC_TZSC1_PRIVCFGR3_ETHERNET_Msk       GTZC_CFGR3_ETHERNET_Msk
20125 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos     GTZC_CFGR3_ICACHE_REG_Pos
20126 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk     GTZC_CFGR3_ICACHE_REG_Msk
20127 #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos    GTZC_CFGR3_DCACHE1_REG_Pos
20128 #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk    GTZC_CFGR3_DCACHE1_REG_Msk
20129 #define GTZC_TZSC1_PRIVCFGR3_ADC12_Pos          GTZC_CFGR3_ADC12_Pos
20130 #define GTZC_TZSC1_PRIVCFGR3_ADC12_Msk          GTZC_CFGR3_ADC12_Msk
20131 #define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos      GTZC_CFGR3_DCMI_PSSI_Pos
20132 #define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk      GTZC_CFGR3_DCMI_PSSI_Msk
20133 #define GTZC_TZSC1_PRIVCFGR3_AES_Pos            GTZC_CFGR3_AES_Pos
20134 #define GTZC_TZSC1_PRIVCFGR3_AES_Msk            GTZC_CFGR3_AES_Msk
20135 #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos           GTZC_CFGR3_HASH_Pos
20136 #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk           GTZC_CFGR3_HASH_Msk
20137 #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos            GTZC_CFGR3_RNG_Pos
20138 #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk            GTZC_CFGR3_RNG_Msk
20139 #define GTZC_TZSC1_PRIVCFGR3_SAES_Pos           GTZC_CFGR3_SAES_Pos
20140 #define GTZC_TZSC1_PRIVCFGR3_SAES_Msk           GTZC_CFGR3_SAES_Msk
20141 #define GTZC_TZSC1_PRIVCFGR3_PKA_Pos            GTZC_CFGR3_PKA_Pos
20142 #define GTZC_TZSC1_PRIVCFGR3_PKA_Msk            GTZC_CFGR3_PKA_Msk
20143 #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos         GTZC_CFGR3_SDMMC1_Pos
20144 #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk         GTZC_CFGR3_SDMMC1_Msk
20145 #define GTZC_TZSC1_PRIVCFGR3_SDMMC2_Pos         GTZC_CFGR3_SDMMC2_Pos
20146 #define GTZC_TZSC1_PRIVCFGR3_SDMMC2_Msk         GTZC_CFGR3_SDMMC2_Msk
20147 #define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos        GTZC_CFGR3_FMC_REG_Pos
20148 #define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk        GTZC_CFGR3_FMC_REG_Msk
20149 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos       GTZC_CFGR3_OCTOSPI1_Pos
20150 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk       GTZC_CFGR3_OCTOSPI1_Msk
20151 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos         GTZC_CFGR3_RAMCFG_Pos
20152 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk         GTZC_CFGR3_RAMCFG_Msk
20153 
20154 /*******************  Bits definition for GTZC_TZIC_IER1 register  ***************/
20155 #define GTZC_TZIC1_IER1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
20156 #define GTZC_TZIC1_IER1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
20157 #define GTZC_TZIC1_IER1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
20158 #define GTZC_TZIC1_IER1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
20159 #define GTZC_TZIC1_IER1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
20160 #define GTZC_TZIC1_IER1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
20161 #define GTZC_TZIC1_IER1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
20162 #define GTZC_TZIC1_IER1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
20163 #define GTZC_TZIC1_IER1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
20164 #define GTZC_TZIC1_IER1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
20165 #define GTZC_TZIC1_IER1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
20166 #define GTZC_TZIC1_IER1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
20167 #define GTZC_TZIC1_IER1_TIM12_Pos           GTZC_CFGR1_TIM12_Pos
20168 #define GTZC_TZIC1_IER1_TIM12_Msk           GTZC_CFGR1_TIM12_Msk
20169 #define GTZC_TZIC1_IER1_TIM13_Pos           GTZC_CFGR1_TIM13_Pos
20170 #define GTZC_TZIC1_IER1_TIM13_Msk           GTZC_CFGR1_TIM13_Msk
20171 #define GTZC_TZIC1_IER1_TIM14_Pos           GTZC_CFGR1_TIM14_Pos
20172 #define GTZC_TZIC1_IER1_TIM14_Msk           GTZC_CFGR1_TIM14_Msk
20173 #define GTZC_TZIC1_IER1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
20174 #define GTZC_TZIC1_IER1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
20175 #define GTZC_TZIC1_IER1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
20176 #define GTZC_TZIC1_IER1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
20177 #define GTZC_TZIC1_IER1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
20178 #define GTZC_TZIC1_IER1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
20179 #define GTZC_TZIC1_IER1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
20180 #define GTZC_TZIC1_IER1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
20181 #define GTZC_TZIC1_IER1_USART2_Pos          GTZC_CFGR1_USART2_Pos
20182 #define GTZC_TZIC1_IER1_USART2_Msk          GTZC_CFGR1_USART2_Msk
20183 #define GTZC_TZIC1_IER1_USART3_Pos          GTZC_CFGR1_USART3_Pos
20184 #define GTZC_TZIC1_IER1_USART3_Msk          GTZC_CFGR1_USART3_Msk
20185 #define GTZC_TZIC1_IER1_UART4_Pos           GTZC_CFGR1_UART4_Pos
20186 #define GTZC_TZIC1_IER1_UART4_Msk           GTZC_CFGR1_UART4_Msk
20187 #define GTZC_TZIC1_IER1_UART5_Pos           GTZC_CFGR1_UART5_Pos
20188 #define GTZC_TZIC1_IER1_UART5_Msk           GTZC_CFGR1_UART5_Msk
20189 #define GTZC_TZIC1_IER1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
20190 #define GTZC_TZIC1_IER1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
20191 #define GTZC_TZIC1_IER1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
20192 #define GTZC_TZIC1_IER1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
20193 #define GTZC_TZIC1_IER1_I3C1_Pos            GTZC_CFGR1_I3C1_Pos
20194 #define GTZC_TZIC1_IER1_I3C1_Msk            GTZC_CFGR1_I3C1_Msk
20195 #define GTZC_TZIC1_IER1_CRS_Pos             GTZC_CFGR1_CRS_Pos
20196 #define GTZC_TZIC1_IER1_CRS_Msk             GTZC_CFGR1_CRS_Msk
20197 #define GTZC_TZIC1_IER1_USART6_Pos          GTZC_CFGR1_USART6_Pos
20198 #define GTZC_TZIC1_IER1_USART6_Msk          GTZC_CFGR1_USART6_Msk
20199 #define GTZC_TZIC1_IER1_USART10_Pos         GTZC_CFGR1_USART10_Pos
20200 #define GTZC_TZIC1_IER1_USART10_Msk         GTZC_CFGR1_USART10_Msk
20201 #define GTZC_TZIC1_IER1_USART11_Pos         GTZC_CFGR1_USART11_Pos
20202 #define GTZC_TZIC1_IER1_USART11_Msk         GTZC_CFGR1_USART11_Msk
20203 #define GTZC_TZIC1_IER1_HDMICEC_Pos         GTZC_CFGR1_HDMICEC_Pos
20204 #define GTZC_TZIC1_IER1_HDMICEC_Msk         GTZC_CFGR1_HDMICEC_Msk
20205 #define GTZC_TZIC1_IER1_DAC12_Pos           GTZC_CFGR1_DAC12_Pos
20206 #define GTZC_TZIC1_IER1_DAC12_Msk           GTZC_CFGR1_DAC12_Msk
20207 #define GTZC_TZIC1_IER1_UART7_Pos           GTZC_CFGR1_UART7_Pos
20208 #define GTZC_TZIC1_IER1_UART7_Msk           GTZC_CFGR1_UART7_Msk
20209 #define GTZC_TZIC1_IER1_UART8_Pos           GTZC_CFGR1_UART8_Pos
20210 #define GTZC_TZIC1_IER1_UART8_Msk           GTZC_CFGR1_UART8_Msk
20211 #define GTZC_TZIC1_IER1_UART9_Pos           GTZC_CFGR1_UART9_Pos
20212 #define GTZC_TZIC1_IER1_UART9_Msk           GTZC_CFGR1_UART9_Msk
20213 #define GTZC_TZIC1_IER1_UART12_Pos          GTZC_CFGR1_UART12_Pos
20214 #define GTZC_TZIC1_IER1_UART12_Msk          GTZC_CFGR1_UART12_Msk
20215 #define GTZC_TZIC1_IER1_DTS_Pos             GTZC_CFGR1_DTS_Pos
20216 #define GTZC_TZIC1_IER1_DTS_Msk             GTZC_CFGR1_DTS_Msk
20217 #define GTZC_TZIC1_IER1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
20218 #define GTZC_TZIC1_IER1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
20219 
20220 /*******************  Bits definition for GTZC_TZIC_IER2 register  ***************/
20221 #define GTZC_TZIC1_IER2_FDCAN1_Pos          GTZC_CFGR2_FDCAN1_Pos
20222 #define GTZC_TZIC1_IER2_FDCAN1_Msk          GTZC_CFGR2_FDCAN1_Msk
20223 #define GTZC_TZIC1_IER2_FDCAN2_Pos          GTZC_CFGR2_FDCAN2_Pos
20224 #define GTZC_TZIC1_IER2_FDCAN2_Msk          GTZC_CFGR2_FDCAN2_Msk
20225 #define GTZC_TZIC1_IER2_UCPD_Pos            GTZC_CFGR2_UCPD_Pos
20226 #define GTZC_TZIC1_IER2_UCPD_Msk            GTZC_CFGR2_UCPD_Msk
20227 #define GTZC_TZIC1_IER2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
20228 #define GTZC_TZIC1_IER2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
20229 #define GTZC_TZIC1_IER2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
20230 #define GTZC_TZIC1_IER2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
20231 #define GTZC_TZIC1_IER2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
20232 #define GTZC_TZIC1_IER2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
20233 #define GTZC_TZIC1_IER2_USART1_Pos          GTZC_CFGR2_USART1_Pos
20234 #define GTZC_TZIC1_IER2_USART1_Msk          GTZC_CFGR2_USART1_Msk
20235 #define GTZC_TZIC1_IER2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
20236 #define GTZC_TZIC1_IER2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
20237 #define GTZC_TZIC1_IER2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
20238 #define GTZC_TZIC1_IER2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
20239 #define GTZC_TZIC1_IER2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
20240 #define GTZC_TZIC1_IER2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
20241 #define GTZC_TZIC1_IER2_SPI4_Pos            GTZC_CFGR2_SPI4_Pos
20242 #define GTZC_TZIC1_IER2_SPI4_Msk            GTZC_CFGR2_SPI4_Msk
20243 #define GTZC_TZIC1_IER2_SPI6_Pos            GTZC_CFGR2_SPI6_Pos
20244 #define GTZC_TZIC1_IER2_SPI6_Msk            GTZC_CFGR2_SPI6_Msk
20245 #define GTZC_TZIC1_IER2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
20246 #define GTZC_TZIC1_IER2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
20247 #define GTZC_TZIC1_IER2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
20248 #define GTZC_TZIC1_IER2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
20249 #define GTZC_TZIC1_IER2_USB_Pos             GTZC_CFGR2_USB_Pos
20250 #define GTZC_TZIC1_IER2_USB_Msk             GTZC_CFGR2_USB_Msk
20251 #define GTZC_TZIC1_IER2_SPI5_Pos            GTZC_CFGR2_SPI5_Pos
20252 #define GTZC_TZIC1_IER2_SPI5_Msk            GTZC_CFGR2_SPI5_Msk
20253 #define GTZC_TZIC1_IER2_LPUART1_Pos         GTZC_CFGR2_LPUART1_Pos
20254 #define GTZC_TZIC1_IER2_LPUART1_Msk         GTZC_CFGR2_LPUART1_Msk
20255 #define GTZC_TZIC1_IER2_I2C3_Pos            GTZC_CFGR2_I2C3_Pos
20256 #define GTZC_TZIC1_IER2_I2C3_Msk            GTZC_CFGR2_I2C3_Msk
20257 #define GTZC_TZIC1_IER2_I2C4_Pos            GTZC_CFGR2_I2C4_Pos
20258 #define GTZC_TZIC1_IER2_I2C4_Msk            GTZC_CFGR2_I2C4_Msk
20259 #define GTZC_TZIC1_IER2_LPTIM1_Pos          GTZC_CFGR2_LPTIM1_Pos
20260 #define GTZC_TZIC1_IER2_LPTIM1_Msk          GTZC_CFGR2_LPTIM1_Msk
20261 #define GTZC_TZIC1_IER2_LPTIM3_Pos          GTZC_CFGR2_LPTIM3_Pos
20262 #define GTZC_TZIC1_IER2_LPTIM3_Msk          GTZC_CFGR2_LPTIM3_Msk
20263 #define GTZC_TZIC1_IER2_LPTIM4_Pos          GTZC_CFGR2_LPTIM4_Pos
20264 #define GTZC_TZIC1_IER2_LPTIM4_Msk          GTZC_CFGR2_LPTIM4_Msk
20265 #define GTZC_TZIC1_IER2_LPTIM5_Pos          GTZC_CFGR2_LPTIM5_Pos
20266 #define GTZC_TZIC1_IER2_LPTIM5_Msk          GTZC_CFGR2_LPTIM5_Msk
20267 
20268 
20269 /*******************  Bits definition for GTZC_TZIC_IER3 register  ***************/
20270 #define GTZC_TZIC1_IER3_LPTIM6_Pos          GTZC_CFGR3_LPTIM6_Pos
20271 #define GTZC_TZIC1_IER3_LPTIM6_Msk          GTZC_CFGR3_LPTIM6_Msk
20272 #define GTZC_TZIC1_IER3_VREFBUF_Pos         GTZC_CFGR3_VREFBUF_Pos
20273 #define GTZC_TZIC1_IER3_VREFBUF_Msk         GTZC_CFGR3_VREFBUF_Msk
20274 #define GTZC_TZIC1_IER3_CRC_Pos             GTZC_CFGR3_CRC_Pos
20275 #define GTZC_TZIC1_IER3_CRC_Msk             GTZC_CFGR3_CRC_Msk
20276 #define GTZC_TZIC1_IER3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
20277 #define GTZC_TZIC1_IER3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
20278 #define GTZC_TZIC1_IER3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
20279 #define GTZC_TZIC1_IER3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
20280 #define GTZC_TZIC1_IER3_ETHERNET_Pos        GTZC_CFGR3_ETHERNET_Pos
20281 #define GTZC_TZIC1_IER3_ETHERNET_Msk        GTZC_CFGR3_ETHERNET_Msk
20282 #define GTZC_TZIC1_IER3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
20283 #define GTZC_TZIC1_IER3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
20284 #define GTZC_TZIC1_IER3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
20285 #define GTZC_TZIC1_IER3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
20286 #define GTZC_TZIC1_IER3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
20287 #define GTZC_TZIC1_IER3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
20288 #define GTZC_TZIC1_IER3_DCMI_PSSI_Pos       GTZC_CFGR3_DCMI_PSSI_Pos
20289 #define GTZC_TZIC1_IER3_DCMI_PSSI_Msk       GTZC_CFGR3_DCMI_PSSI_Msk
20290 #define GTZC_TZIC1_IER3_AES_Pos             GTZC_CFGR3_AES_Pos
20291 #define GTZC_TZIC1_IER3_AES_Msk             GTZC_CFGR3_AES_Msk
20292 #define GTZC_TZIC1_IER3_HASH_Pos            GTZC_CFGR3_HASH_Pos
20293 #define GTZC_TZIC1_IER3_HASH_Msk            GTZC_CFGR3_HASH_Msk
20294 #define GTZC_TZIC1_IER3_RNG_Pos             GTZC_CFGR3_RNG_Pos
20295 #define GTZC_TZIC1_IER3_RNG_Msk             GTZC_CFGR3_RNG_Msk
20296 #define GTZC_TZIC1_IER3_SAES_Pos            GTZC_CFGR3_SAES_Pos
20297 #define GTZC_TZIC1_IER3_SAES_Msk            GTZC_CFGR3_SAES_Msk
20298 #define GTZC_TZIC1_IER3_PKA_Pos             GTZC_CFGR3_PKA_Pos
20299 #define GTZC_TZIC1_IER3_PKA_Msk             GTZC_CFGR3_PKA_Msk
20300 #define GTZC_TZIC1_IER3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
20301 #define GTZC_TZIC1_IER3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
20302 #define GTZC_TZIC1_IER3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
20303 #define GTZC_TZIC1_IER3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
20304 #define GTZC_TZIC1_IER3_FMC_REG_Pos         GTZC_CFGR3_FMC_REG_Pos
20305 #define GTZC_TZIC1_IER3_FMC_REG_Msk         GTZC_CFGR3_FMC_REG_Msk
20306 #define GTZC_TZIC1_IER3_OCTOSPI1_Pos        GTZC_CFGR3_OCTOSPI1_Pos
20307 #define GTZC_TZIC1_IER3_OCTOSPI1_Msk        GTZC_CFGR3_OCTOSPI1_Msk
20308 #define GTZC_TZIC1_IER3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
20309 #define GTZC_TZIC1_IER3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
20310 
20311 /*******************  Bits definition for GTZC_TZIC_IER4 register  ***************/
20312 #define GTZC_TZIC1_IER4_GPDMA1_Pos          GTZC_CFGR4_GPDMA1_Pos
20313 #define GTZC_TZIC1_IER4_GPDMA1_Msk          GTZC_CFGR4_GPDMA1_Msk
20314 #define GTZC_TZIC1_IER4_GPDMA2_Pos          GTZC_CFGR4_GPDMA2_Pos
20315 #define GTZC_TZIC1_IER4_GPDMA2_Msk          GTZC_CFGR4_GPDMA2_Msk
20316 #define GTZC_TZIC1_IER4_FLASH_Pos           GTZC_CFGR4_FLASH_Pos
20317 #define GTZC_TZIC1_IER4_FLASH_Msk           GTZC_CFGR4_FLASH_Msk
20318 #define GTZC_TZIC1_IER4_FLASH_REG_Pos       GTZC_CFGR4_FLASH_REG_Pos
20319 #define GTZC_TZIC1_IER4_FLASH_REG_Msk       GTZC_CFGR4_FLASH_REG_Msk
20320 #define GTZC_TZIC1_IER4_OTFDEC1_Pos         GTZC_CFGR4_OTFDEC1_Pos
20321 #define GTZC_TZIC1_IER4_OTFDEC1_Msk         GTZC_CFGR4_OTFDEC1_Msk
20322 #define GTZC_TZIC1_IER4_SBS_Pos             GTZC_CFGR4_SBS_Pos
20323 #define GTZC_TZIC1_IER4_SBS_Msk             GTZC_CFGR4_SBS_Msk
20324 #define GTZC_TZIC1_IER4_RTC_Pos             GTZC_CFGR4_RTC_Pos
20325 #define GTZC_TZIC1_IER4_RTC_Msk             GTZC_CFGR4_RTC_Msk
20326 #define GTZC_TZIC1_IER4_TAMP_Pos            GTZC_CFGR4_TAMP_Pos
20327 #define GTZC_TZIC1_IER4_TAMP_Msk            GTZC_CFGR4_TAMP_Msk
20328 #define GTZC_TZIC1_IER4_PWR_Pos             GTZC_CFGR4_PWR_Pos
20329 #define GTZC_TZIC1_IER4_PWR_Msk             GTZC_CFGR4_PWR_Msk
20330 #define GTZC_TZIC1_IER4_RCC_Pos             GTZC_CFGR4_RCC_Pos
20331 #define GTZC_TZIC1_IER4_RCC_Msk             GTZC_CFGR4_RCC_Msk
20332 #define GTZC_TZIC1_IER4_EXTI_Pos            GTZC_CFGR4_EXTI_Pos
20333 #define GTZC_TZIC1_IER4_EXTI_Msk            GTZC_CFGR4_EXTI_Msk
20334 #define GTZC_TZIC1_IER4_TZSC_Pos            GTZC_CFGR4_TZSC_Pos
20335 #define GTZC_TZIC1_IER4_TZSC_Msk            GTZC_CFGR4_TZSC_Msk
20336 #define GTZC_TZIC1_IER4_TZIC_Pos            GTZC_CFGR4_TZIC_Pos
20337 #define GTZC_TZIC1_IER4_TZIC_Msk            GTZC_CFGR4_TZIC_Msk
20338 #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos    GTZC_CFGR4_OCTOSPI1_MEM_Pos
20339 #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk    GTZC_CFGR4_OCTOSPI1_MEM_Msk
20340 #define GTZC_TZIC1_IER4_FMC_MEM_Pos         GTZC_CFGR4_FMC_MEM_Pos
20341 #define GTZC_TZIC1_IER4_FMC_MEM_Msk         GTZC_CFGR4_FMC_MEM_Msk
20342 #define GTZC_TZIC1_IER4_BKPSRAM_Pos         GTZC_CFGR4_BKPSRAM_Pos
20343 #define GTZC_TZIC1_IER4_BKPSRAM_Msk         GTZC_CFGR4_BKPSRAM_Msk
20344 #define GTZC_TZIC1_IER4_SRAM1_Pos           GTZC_CFGR4_SRAM1_Pos
20345 #define GTZC_TZIC1_IER4_SRAM1_Msk           GTZC_CFGR4_SRAM1_Msk
20346 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos      GTZC_CFGR4_MPCBB1_REG_Pos
20347 #define GTZC_TZIC1_IER4_MPCBB1_REG_Msk      GTZC_CFGR4_MPCBB1_REG_Msk
20348 #define GTZC_TZIC1_IER4_SRAM2_Pos           GTZC_CFGR4_SRAM2_Pos
20349 #define GTZC_TZIC1_IER4_SRAM2_Msk           GTZC_CFGR4_SRAM2_Msk
20350 #define GTZC_TZIC1_IER4_MPCBB2_REG_Pos      GTZC_CFGR4_MPCBB2_REG_Pos
20351 #define GTZC_TZIC1_IER4_MPCBB2_REG_Msk      GTZC_CFGR4_MPCBB2_REG_Msk
20352 #define GTZC_TZIC1_IER4_SRAM3_Pos           GTZC_CFGR4_SRAM3_Pos
20353 #define GTZC_TZIC1_IER4_SRAM3_Msk           GTZC_CFGR4_SRAM3_Msk
20354 #define GTZC_TZIC1_IER4_MPCBB3_REG_Pos      GTZC_CFGR4_MPCBB3_REG_Pos
20355 #define GTZC_TZIC1_IER4_MPCBB3_REG_Msk      GTZC_CFGR4_MPCBB3_REG_Msk
20356 
20357 /*******************  Bits definition for GTZC_TZIC_SR1 register  **************/
20358 #define GTZC_TZIC1_SR1_TIM2_Pos             GTZC_CFGR1_TIM2_Pos
20359 #define GTZC_TZIC1_SR1_TIM2_Msk             GTZC_CFGR1_TIM2_Msk
20360 #define GTZC_TZIC1_SR1_TIM3_Pos             GTZC_CFGR1_TIM3_Pos
20361 #define GTZC_TZIC1_SR1_TIM3_Msk             GTZC_CFGR1_TIM3_Msk
20362 #define GTZC_TZIC1_SR1_TIM4_Pos             GTZC_CFGR1_TIM4_Pos
20363 #define GTZC_TZIC1_SR1_TIM4_Msk             GTZC_CFGR1_TIM4_Msk
20364 #define GTZC_TZIC1_SR1_TIM5_Pos             GTZC_CFGR1_TIM5_Pos
20365 #define GTZC_TZIC1_SR1_TIM5_Msk             GTZC_CFGR1_TIM5_Msk
20366 #define GTZC_TZIC1_SR1_TIM6_Pos             GTZC_CFGR1_TIM6_Pos
20367 #define GTZC_TZIC1_SR1_TIM6_Msk             GTZC_CFGR1_TIM6_Msk
20368 #define GTZC_TZIC1_SR1_TIM7_Pos             GTZC_CFGR1_TIM7_Pos
20369 #define GTZC_TZIC1_SR1_TIM7_Msk             GTZC_CFGR1_TIM7_Msk
20370 #define GTZC_TZIC1_SR1_TIM12_Pos            GTZC_CFGR1_TIM12_Pos
20371 #define GTZC_TZIC1_SR1_TIM12_Msk            GTZC_CFGR1_TIM12_Msk
20372 #define GTZC_TZIC1_SR1_TIM13_Pos            GTZC_CFGR1_TIM13_Pos
20373 #define GTZC_TZIC1_SR1_TIM13_Msk            GTZC_CFGR1_TIM13_Msk
20374 #define GTZC_TZIC1_SR1_TIM14_Pos            GTZC_CFGR1_TIM14_Pos
20375 #define GTZC_TZIC1_SR1_TIM14_Msk            GTZC_CFGR1_TIM14_Msk
20376 #define GTZC_TZIC1_SR1_WWDG_Pos             GTZC_CFGR1_WWDG_Pos
20377 #define GTZC_TZIC1_SR1_WWDG_Msk             GTZC_CFGR1_WWDG_Msk
20378 #define GTZC_TZIC1_SR1_IWDG_Pos             GTZC_CFGR1_IWDG_Pos
20379 #define GTZC_TZIC1_SR1_IWDG_Msk             GTZC_CFGR1_IWDG_Msk
20380 #define GTZC_TZIC1_SR1_SPI2_Pos             GTZC_CFGR1_SPI2_Pos
20381 #define GTZC_TZIC1_SR1_SPI2_Msk             GTZC_CFGR1_SPI2_Msk
20382 #define GTZC_TZIC1_SR1_SPI3_Pos             GTZC_CFGR1_SPI3_Pos
20383 #define GTZC_TZIC1_SR1_SPI3_Msk             GTZC_CFGR1_SPI3_Msk
20384 #define GTZC_TZIC1_SR1_USART2_Pos           GTZC_CFGR1_USART2_Pos
20385 #define GTZC_TZIC1_SR1_USART2_Msk           GTZC_CFGR1_USART2_Msk
20386 #define GTZC_TZIC1_SR1_USART3_Pos           GTZC_CFGR1_USART3_Pos
20387 #define GTZC_TZIC1_SR1_USART3_Msk           GTZC_CFGR1_USART3_Msk
20388 #define GTZC_TZIC1_SR1_UART4_Pos            GTZC_CFGR1_UART4_Pos
20389 #define GTZC_TZIC1_SR1_UART4_Msk            GTZC_CFGR1_UART4_Msk
20390 #define GTZC_TZIC1_SR1_UART5_Pos            GTZC_CFGR1_UART5_Pos
20391 #define GTZC_TZIC1_SR1_UART5_Msk            GTZC_CFGR1_UART5_Msk
20392 #define GTZC_TZIC1_SR1_I2C1_Pos             GTZC_CFGR1_I2C1_Pos
20393 #define GTZC_TZIC1_SR1_I2C1_Msk             GTZC_CFGR1_I2C1_Msk
20394 #define GTZC_TZIC1_SR1_I2C2_Pos             GTZC_CFGR1_I2C2_Pos
20395 #define GTZC_TZIC1_SR1_I2C2_Msk             GTZC_CFGR1_I2C2_Msk
20396 #define GTZC_TZIC1_SR1_I3C1_Pos             GTZC_CFGR1_I3C1_Pos
20397 #define GTZC_TZIC1_SR1_I3C1_Msk             GTZC_CFGR1_I3C1_Msk
20398 #define GTZC_TZIC1_SR1_CRS_Pos              GTZC_CFGR1_CRS_Pos
20399 #define GTZC_TZIC1_SR1_CRS_Msk              GTZC_CFGR1_CRS_Msk
20400 #define GTZC_TZIC1_SR1_USART6_Pos           GTZC_CFGR1_USART6_Pos
20401 #define GTZC_TZIC1_SR1_USART6_Msk           GTZC_CFGR1_USART6_Msk
20402 #define GTZC_TZIC1_SR1_USART10_Pos          GTZC_CFGR1_USART10_Pos
20403 #define GTZC_TZIC1_SR1_USART10_Msk          GTZC_CFGR1_USART10_Msk
20404 #define GTZC_TZIC1_SR1_USART11_Pos          GTZC_CFGR1_USART11_Pos
20405 #define GTZC_TZIC1_SR1_USART11_Msk          GTZC_CFGR1_USART11_Msk
20406 #define GTZC_TZIC1_SR1_HDMICEC_Pos          GTZC_CFGR1_HDMICEC_Pos
20407 #define GTZC_TZIC1_SR1_HDMICEC_Msk          GTZC_CFGR1_HDMICEC_Msk
20408 #define GTZC_TZIC1_SR1_DAC12_Pos            GTZC_CFGR1_DAC12_Pos
20409 #define GTZC_TZIC1_SR1_DAC12_Msk            GTZC_CFGR1_DAC12_Msk
20410 #define GTZC_TZIC1_SR1_UART7_Pos            GTZC_CFGR1_UART7_Pos
20411 #define GTZC_TZIC1_SR1_UART7_Msk            GTZC_CFGR1_UART7_Msk
20412 #define GTZC_TZIC1_SR1_UART8_Pos            GTZC_CFGR1_UART8_Pos
20413 #define GTZC_TZIC1_SR1_UART8_Msk            GTZC_CFGR1_UART8_Msk
20414 #define GTZC_TZIC1_SR1_UART9_Pos            GTZC_CFGR1_UART9_Pos
20415 #define GTZC_TZIC1_SR1_UART9_Msk            GTZC_CFGR1_UART9_Msk
20416 #define GTZC_TZIC1_SR1_UART12_Pos           GTZC_CFGR1_UART12_Pos
20417 #define GTZC_TZIC1_SR1_UART12_Msk           GTZC_CFGR1_UART12_Msk
20418 #define GTZC_TZIC1_SR1_DTS_Pos              GTZC_CFGR1_DTS_Pos
20419 #define GTZC_TZIC1_SR1_DTS_Msk              GTZC_CFGR1_DTS_Msk
20420 #define GTZC_TZIC1_SR1_LPTIM2_Pos           GTZC_CFGR1_LPTIM2_Pos
20421 #define GTZC_TZIC1_SR1_LPTIM2_Msk           GTZC_CFGR1_LPTIM2_Msk
20422 
20423 /*******************  Bits definition for GTZC_TZIC_SR2 register  **************/
20424 #define GTZC_TZIC1_SR2_FDCAN1_Pos           GTZC_CFGR2_FDCAN1_Pos
20425 #define GTZC_TZIC1_SR2_FDCAN1_Msk           GTZC_CFGR2_FDCAN1_Msk
20426 #define GTZC_TZIC1_SR2_FDCAN2_Pos           GTZC_CFGR2_FDCAN2_Pos
20427 #define GTZC_TZIC1_SR2_FDCAN2_Msk           GTZC_CFGR2_FDCAN2_Msk
20428 #define GTZC_TZIC1_SR2_UCPD_Pos             GTZC_CFGR2_UCPD_Pos
20429 #define GTZC_TZIC1_SR2_UCPD_Msk             GTZC_CFGR2_UCPD_Msk
20430 #define GTZC_TZIC1_SR2_TIM1_Pos             GTZC_CFGR2_TIM1_Pos
20431 #define GTZC_TZIC1_SR2_TIM1_Msk             GTZC_CFGR2_TIM1_Msk
20432 #define GTZC_TZIC1_SR2_SPI1_Pos             GTZC_CFGR2_SPI1_Pos
20433 #define GTZC_TZIC1_SR2_SPI1_Msk             GTZC_CFGR2_SPI1_Msk
20434 #define GTZC_TZIC1_SR2_TIM8_Pos             GTZC_CFGR2_TIM8_Pos
20435 #define GTZC_TZIC1_SR2_TIM8_Msk             GTZC_CFGR2_TIM8_Msk
20436 #define GTZC_TZIC1_SR2_USART1_Pos           GTZC_CFGR2_USART1_Pos
20437 #define GTZC_TZIC1_SR2_USART1_Msk           GTZC_CFGR2_USART1_Msk
20438 #define GTZC_TZIC1_SR2_TIM15_Pos            GTZC_CFGR2_TIM15_Pos
20439 #define GTZC_TZIC1_SR2_TIM15_Msk            GTZC_CFGR2_TIM15_Msk
20440 #define GTZC_TZIC1_SR2_TIM16_Pos            GTZC_CFGR2_TIM16_Pos
20441 #define GTZC_TZIC1_SR2_TIM16_Msk            GTZC_CFGR2_TIM16_Msk
20442 #define GTZC_TZIC1_SR2_TIM17_Pos            GTZC_CFGR2_TIM17_Pos
20443 #define GTZC_TZIC1_SR2_TIM17_Msk            GTZC_CFGR2_TIM17_Msk
20444 #define GTZC_TZIC1_SR2_SPI4_Pos             GTZC_CFGR2_SPI4_Pos
20445 #define GTZC_TZIC1_SR2_SPI4_Msk             GTZC_CFGR2_SPI4_Msk
20446 #define GTZC_TZIC1_SR2_SPI6_Pos             GTZC_CFGR2_SPI6_Pos
20447 #define GTZC_TZIC1_SR2_SPI6_Msk             GTZC_CFGR2_SPI6_Msk
20448 #define GTZC_TZIC1_SR2_SAI1_Pos             GTZC_CFGR2_SAI1_Pos
20449 #define GTZC_TZIC1_SR2_SAI1_Msk             GTZC_CFGR2_SAI1_Msk
20450 #define GTZC_TZIC1_SR2_SAI2_Pos             GTZC_CFGR2_SAI2_Pos
20451 #define GTZC_TZIC1_SR2_SAI2_Msk             GTZC_CFGR2_SAI2_Msk
20452 #define GTZC_TZIC1_SR2_USB_Pos              GTZC_CFGR2_USB_Pos
20453 #define GTZC_TZIC1_SR2_USB_Msk              GTZC_CFGR2_USB_Msk
20454 #define GTZC_TZIC1_SR2_SPI5_Pos             GTZC_CFGR2_SPI5_Pos
20455 #define GTZC_TZIC1_SR2_SPI5_Msk             GTZC_CFGR2_SPI5_Msk
20456 #define GTZC_TZIC1_SR2_LPUART1_Pos          GTZC_CFGR2_LPUART1_Pos
20457 #define GTZC_TZIC1_SR2_LPUART1_Msk          GTZC_CFGR2_LPUART1_Msk
20458 #define GTZC_TZIC1_SR2_I2C3_Pos             GTZC_CFGR2_I2C3_Pos
20459 #define GTZC_TZIC1_SR2_I2C3_Msk             GTZC_CFGR2_I2C3_Msk
20460 #define GTZC_TZIC1_SR2_I2C4_Pos             GTZC_CFGR2_I2C4_Pos
20461 #define GTZC_TZIC1_SR2_I2C4_Msk             GTZC_CFGR2_I2C4_Msk
20462 #define GTZC_TZIC1_SR2_LPTIM1_Pos           GTZC_CFGR2_LPTIM1_Pos
20463 #define GTZC_TZIC1_SR2_LPTIM1_Msk           GTZC_CFGR2_LPTIM1_Msk
20464 #define GTZC_TZIC1_SR2_LPTIM3_Pos           GTZC_CFGR2_LPTIM3_Pos
20465 #define GTZC_TZIC1_SR2_LPTIM3_Msk           GTZC_CFGR2_LPTIM3_Msk
20466 #define GTZC_TZIC1_SR2_LPTIM4_Pos           GTZC_CFGR2_LPTIM4_Pos
20467 #define GTZC_TZIC1_SR2_LPTIM4_Msk           GTZC_CFGR2_LPTIM4_Msk
20468 #define GTZC_TZIC1_SR2_LPTIM5_Pos           GTZC_CFGR2_LPTIM5_Pos
20469 #define GTZC_TZIC1_SR2_LPTIM5_Msk           GTZC_CFGR2_LPTIM5_Msk
20470 
20471 /*******************  Bits definition for GTZC_TZIC_SR3 register  **************/
20472 #define GTZC_TZIC1_SR3_LPTIM6_Pos           GTZC_CFGR3_LPTIM6_Pos
20473 #define GTZC_TZIC1_SR3_LPTIM6_Msk           GTZC_CFGR3_LPTIM6_Msk
20474 #define GTZC_TZIC1_SR3_VREFBUF_Pos          GTZC_CFGR3_VREFBUF_Pos
20475 #define GTZC_TZIC1_SR3_VREFBUF_Msk          GTZC_CFGR3_VREFBUF_Msk
20476 #define GTZC_TZIC1_SR3_CRC_Pos              GTZC_CFGR3_CRC_Pos
20477 #define GTZC_TZIC1_SR3_CRC_Msk              GTZC_CFGR3_CRC_Msk
20478 #define GTZC_TZIC1_SR3_CORDIC_Pos           GTZC_CFGR3_CORDIC_Pos
20479 #define GTZC_TZIC1_SR3_CORDIC_Msk           GTZC_CFGR3_CORDIC_Msk
20480 #define GTZC_TZIC1_SR3_FMAC_Pos             GTZC_CFGR3_FMAC_Pos
20481 #define GTZC_TZIC1_SR3_FMAC_Msk             GTZC_CFGR3_FMAC_Msk
20482 #define GTZC_TZIC1_SR3_ETHERNET_Pos         GTZC_CFGR3_ETHERNET_Pos
20483 #define GTZC_TZIC1_SR3_ETHERNET_Msk         GTZC_CFGR3_ETHERNET_Msk
20484 #define GTZC_TZIC1_SR3_ICACHE_REG_Pos       GTZC_CFGR3_ICACHE_REG_Pos
20485 #define GTZC_TZIC1_SR3_ICACHE_REG_Msk       GTZC_CFGR3_ICACHE_REG_Msk
20486 #define GTZC_TZIC1_SR3_DCACHE1_REG_Pos      GTZC_CFGR3_DCACHE1_REG_Pos
20487 #define GTZC_TZIC1_SR3_DCACHE1_REG_Msk      GTZC_CFGR3_DCACHE1_REG_Msk
20488 #define GTZC_TZIC1_SR3_ADC12_Pos            GTZC_CFGR3_ADC12_Pos
20489 #define GTZC_TZIC1_SR3_ADC12_Msk            GTZC_CFGR3_ADC12_Msk
20490 #define GTZC_TZIC1_SR3_DCMI_PSSI_Pos        GTZC_CFGR3_DCMI_PSSI_Pos
20491 #define GTZC_TZIC1_SR3_DCMI_PSSI_Msk        GTZC_CFGR3_DCMI_PSSI_Msk
20492 #define GTZC_TZIC1_SR3_AES_Pos              GTZC_CFGR3_AES_Pos
20493 #define GTZC_TZIC1_SR3_AES_Msk              GTZC_CFGR3_AES_Msk
20494 #define GTZC_TZIC1_SR3_HASH_Pos             GTZC_CFGR3_HASH_Pos
20495 #define GTZC_TZIC1_SR3_HASH_Msk             GTZC_CFGR3_HASH_Msk
20496 #define GTZC_TZIC1_SR3_RNG_Pos              GTZC_CFGR3_RNG_Pos
20497 #define GTZC_TZIC1_SR3_RNG_Msk              GTZC_CFGR3_RNG_Msk
20498 #define GTZC_TZIC1_SR3_SAES_Pos             GTZC_CFGR3_SAES_Pos
20499 #define GTZC_TZIC1_SR3_SAES_Msk             GTZC_CFGR3_SAES_Msk
20500 #define GTZC_TZIC1_SR3_PKA_Pos              GTZC_CFGR3_PKA_Pos
20501 #define GTZC_TZIC1_SR3_PKA_Msk              GTZC_CFGR3_PKA_Msk
20502 #define GTZC_TZIC1_SR3_SDMMC1_Pos           GTZC_CFGR3_SDMMC1_Pos
20503 #define GTZC_TZIC1_SR3_SDMMC1_Msk           GTZC_CFGR3_SDMMC1_Msk
20504 #define GTZC_TZIC1_SR3_SDMMC2_Pos           GTZC_CFGR3_SDMMC2_Pos
20505 #define GTZC_TZIC1_SR3_SDMMC2_Msk           GTZC_CFGR3_SDMMC2_Msk
20506 #define GTZC_TZIC1_SR3_FMC_REG_Pos          GTZC_CFGR3_FMC_REG_Pos
20507 #define GTZC_TZIC1_SR3_FMC_REG_Msk          GTZC_CFGR3_FMC_REG_Msk
20508 #define GTZC_TZIC1_SR3_OCTOSPI1_Pos         GTZC_CFGR3_OCTOSPI1_Pos
20509 #define GTZC_TZIC1_SR3_OCTOSPI1_Msk         GTZC_CFGR3_OCTOSPI1_Msk
20510 #define GTZC_TZIC1_SR3_RAMCFG_Pos           GTZC_CFGR3_RAMCFG_Pos
20511 #define GTZC_TZIC1_SR3_RAMCFG_Msk           GTZC_CFGR3_RAMCFG_Msk
20512 
20513 /*******************  Bits definition for GTZC_TZIC_SR4 register  ***************/
20514 #define GTZC_TZIC1_SR4_GPDMA1_Pos           GTZC_CFGR4_GPDMA1_Pos
20515 #define GTZC_TZIC1_SR4_GPDMA1_Msk           GTZC_CFGR4_GPDMA1_Msk
20516 #define GTZC_TZIC1_SR4_GPDMA2_Pos           GTZC_CFGR4_GPDMA2_Pos
20517 #define GTZC_TZIC1_SR4_GPDMA2_Msk           GTZC_CFGR4_GPDMA2_Msk
20518 #define GTZC_TZIC1_SR4_FLASH_Pos            GTZC_CFGR4_FLASH_Pos
20519 #define GTZC_TZIC1_SR4_FLASH_Msk            GTZC_CFGR4_FLASH_Msk
20520 #define GTZC_TZIC1_SR4_FLASH_REG_Pos        GTZC_CFGR4_FLASH_REG_Pos
20521 #define GTZC_TZIC1_SR4_FLASH_REG_Msk        GTZC_CFGR4_FLASH_REG_Msk
20522 #define GTZC_TZIC1_SR4_OTFDEC1_Pos          GTZC_CFGR4_OTFDEC1_Pos
20523 #define GTZC_TZIC1_SR4_OTFDEC1_Msk          GTZC_CFGR4_OTFDEC1_Msk
20524 #define GTZC_TZIC1_SR4_SBS_Pos              GTZC_CFGR4_SBS_Pos
20525 #define GTZC_TZIC1_SR4_SBS_Msk              GTZC_CFGR4_SBS_Msk
20526 #define GTZC_TZIC1_SR4_RTC_Pos              GTZC_CFGR4_RTC_Pos
20527 #define GTZC_TZIC1_SR4_RTC_Msk              GTZC_CFGR4_RTC_Msk
20528 #define GTZC_TZIC1_SR4_TAMP_Pos             GTZC_CFGR4_TAMP_Pos
20529 #define GTZC_TZIC1_SR4_TAMP_Msk             GTZC_CFGR4_TAMP_Msk
20530 #define GTZC_TZIC1_SR4_PWR_Pos              GTZC_CFGR4_PWR_Pos
20531 #define GTZC_TZIC1_SR4_PWR_Msk              GTZC_CFGR4_PWR_Msk
20532 #define GTZC_TZIC1_SR4_RCC_Pos              GTZC_CFGR4_RCC_Pos
20533 #define GTZC_TZIC1_SR4_RCC_Msk              GTZC_CFGR4_RCC_Msk
20534 #define GTZC_TZIC1_SR4_EXTI_Pos             GTZC_CFGR4_EXTI_Pos
20535 #define GTZC_TZIC1_SR4_EXTI_Msk             GTZC_CFGR4_EXTI_Msk
20536 #define GTZC_TZIC1_SR4_TZSC_Pos             GTZC_CFGR4_TZSC_Pos
20537 #define GTZC_TZIC1_SR4_TZSC_Msk             GTZC_CFGR4_TZSC_Msk
20538 #define GTZC_TZIC1_SR4_TZIC_Pos             GTZC_CFGR4_TZIC_Pos
20539 #define GTZC_TZIC1_SR4_TZIC_Msk             GTZC_CFGR4_TZIC_Msk
20540 #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos     GTZC_CFGR4_OCTOSPI1_MEM_Pos
20541 #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk     GTZC_CFGR4_OCTOSPI1_MEM_Msk
20542 #define GTZC_TZIC1_SR4_FMC_MEM_Pos          GTZC_CFGR4_FMC_MEM_Pos
20543 #define GTZC_TZIC1_SR4_FMC_MEM_Msk          GTZC_CFGR4_FMC_MEM_Msk
20544 #define GTZC_TZIC1_SR4_BKPSRAM_Pos          GTZC_CFGR4_BKPSRAM_Pos
20545 #define GTZC_TZIC1_SR4_BKPSRAM_Msk          GTZC_CFGR4_BKPSRAM_Msk
20546 #define GTZC_TZIC1_SR4_SRAM1_Pos            GTZC_CFGR4_SRAM1_Pos
20547 #define GTZC_TZIC1_SR4_SRAM1_Msk            GTZC_CFGR4_SRAM1_Msk
20548 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos       GTZC_CFGR4_MPCBB1_REG_Pos
20549 #define GTZC_TZIC1_SR4_MPCBB1_REG_Msk       GTZC_CFGR4_MPCBB1_REG_Msk
20550 #define GTZC_TZIC1_SR4_SRAM2_Pos            GTZC_CFGR4_SRAM2_Pos
20551 #define GTZC_TZIC1_SR4_SRAM2_Msk            GTZC_CFGR4_SRAM2_Msk
20552 #define GTZC_TZIC1_SR4_MPCBB2_REG_Pos       GTZC_CFGR4_MPCBB2_REG_Pos
20553 #define GTZC_TZIC1_SR4_MPCBB2_REG_Msk       GTZC_CFGR4_MPCBB2_REG_Msk
20554 #define GTZC_TZIC1_SR4_SRAM3_Pos            GTZC_CFGR4_SRAM3_Pos
20555 #define GTZC_TZIC1_SR4_SRAM3_Msk            GTZC_CFGR4_SRAM3_Msk
20556 #define GTZC_TZIC1_SR4_MPCBB3_REG_Pos       GTZC_CFGR4_MPCBB3_REG_Pos
20557 #define GTZC_TZIC1_SR4_MPCBB3_REG_Msk       GTZC_CFGR4_MPCBB3_REG_Msk
20558 
20559 /******************  Bits definition for GTZC_TZIC_FCR1 register  ****************/
20560 #define GTZC_TZIC1_FCR1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
20561 #define GTZC_TZIC1_FCR1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
20562 #define GTZC_TZIC1_FCR1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
20563 #define GTZC_TZIC1_FCR1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
20564 #define GTZC_TZIC1_FCR1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
20565 #define GTZC_TZIC1_FCR1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
20566 #define GTZC_TZIC1_FCR1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
20567 #define GTZC_TZIC1_FCR1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
20568 #define GTZC_TZIC1_FCR1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
20569 #define GTZC_TZIC1_FCR1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
20570 #define GTZC_TZIC1_FCR1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
20571 #define GTZC_TZIC1_FCR1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
20572 #define GTZC_TZIC1_FCR1_TIM12_Pos           GTZC_CFGR1_TIM12_Pos
20573 #define GTZC_TZIC1_FCR1_TIM12_Msk           GTZC_CFGR1_TIM12_Msk
20574 #define GTZC_TZIC1_FCR1_TIM13_Pos           GTZC_CFGR1_TIM13_Pos
20575 #define GTZC_TZIC1_FCR1_TIM13_Msk           GTZC_CFGR1_TIM13_Msk
20576 #define GTZC_TZIC1_FCR1_TIM14_Pos           GTZC_CFGR1_TIM14_Pos
20577 #define GTZC_TZIC1_FCR1_TIM14_Msk           GTZC_CFGR1_TIM14_Msk
20578 #define GTZC_TZIC1_FCR1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
20579 #define GTZC_TZIC1_FCR1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
20580 #define GTZC_TZIC1_FCR1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
20581 #define GTZC_TZIC1_FCR1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
20582 #define GTZC_TZIC1_FCR1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
20583 #define GTZC_TZIC1_FCR1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
20584 #define GTZC_TZIC1_FCR1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
20585 #define GTZC_TZIC1_FCR1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
20586 #define GTZC_TZIC1_FCR1_USART2_Pos          GTZC_CFGR1_USART2_Pos
20587 #define GTZC_TZIC1_FCR1_USART2_Msk          GTZC_CFGR1_USART2_Msk
20588 #define GTZC_TZIC1_FCR1_USART3_Pos          GTZC_CFGR1_USART3_Pos
20589 #define GTZC_TZIC1_FCR1_USART3_Msk          GTZC_CFGR1_USART3_Msk
20590 #define GTZC_TZIC1_FCR1_UART4_Pos           GTZC_CFGR1_UART4_Pos
20591 #define GTZC_TZIC1_FCR1_UART4_Msk           GTZC_CFGR1_UART4_Msk
20592 #define GTZC_TZIC1_FCR1_UART5_Pos           GTZC_CFGR1_UART5_Pos
20593 #define GTZC_TZIC1_FCR1_UART5_Msk           GTZC_CFGR1_UART5_Msk
20594 #define GTZC_TZIC1_FCR1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
20595 #define GTZC_TZIC1_FCR1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
20596 #define GTZC_TZIC1_FCR1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
20597 #define GTZC_TZIC1_FCR1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
20598 #define GTZC_TZIC1_FCR1_I3C1_Pos            GTZC_CFGR1_I3C1_Pos
20599 #define GTZC_TZIC1_FCR1_I3C1_Msk            GTZC_CFGR1_I3C1_Msk
20600 #define GTZC_TZIC1_FCR1_CRS_Pos             GTZC_CFGR1_CRS_Pos
20601 #define GTZC_TZIC1_FCR1_CRS_Msk             GTZC_CFGR1_CRS_Msk
20602 #define GTZC_TZIC1_FCR1_USART6_Pos          GTZC_CFGR1_USART6_Pos
20603 #define GTZC_TZIC1_FCR1_USART6_Msk          GTZC_CFGR1_USART6_Msk
20604 #define GTZC_TZIC1_FCR1_USART10_Pos         GTZC_CFGR1_USART10_Pos
20605 #define GTZC_TZIC1_FCR1_USART10_Msk         GTZC_CFGR1_USART10_Msk
20606 #define GTZC_TZIC1_FCR1_USART11_Pos         GTZC_CFGR1_USART11_Pos
20607 #define GTZC_TZIC1_FCR1_USART11_Msk         GTZC_CFGR1_USART11_Msk
20608 #define GTZC_TZIC1_FCR1_HDMICEC_Pos         GTZC_CFGR1_HDMICEC_Pos
20609 #define GTZC_TZIC1_FCR1_HDMICEC_Msk         GTZC_CFGR1_HDMICEC_Msk
20610 #define GTZC_TZIC1_FCR1_DAC12_Pos           GTZC_CFGR1_DAC12_Pos
20611 #define GTZC_TZIC1_FCR1_DAC12_Msk           GTZC_CFGR1_DAC12_Msk
20612 #define GTZC_TZIC1_FCR1_UART7_Pos           GTZC_CFGR1_UART7_Pos
20613 #define GTZC_TZIC1_FCR1_UART7_Msk           GTZC_CFGR1_UART7_Msk
20614 #define GTZC_TZIC1_FCR1_UART8_Pos           GTZC_CFGR1_UART8_Pos
20615 #define GTZC_TZIC1_FCR1_UART8_Msk           GTZC_CFGR1_UART8_Msk
20616 #define GTZC_TZIC1_FCR1_UART9_Pos           GTZC_CFGR1_UART9_Pos
20617 #define GTZC_TZIC1_FCR1_UART9_Msk           GTZC_CFGR1_UART9_Msk
20618 #define GTZC_TZIC1_FCR1_UART12_Pos          GTZC_CFGR1_UART12_Pos
20619 #define GTZC_TZIC1_FCR1_UART12_Msk          GTZC_CFGR1_UART12_Msk
20620 #define GTZC_TZIC1_FCR1_DTS_Pos             GTZC_CFGR1_DTS_Pos
20621 #define GTZC_TZIC1_FCR1_DTS_Msk             GTZC_CFGR1_DTS_Msk
20622 #define GTZC_TZIC1_FCR1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
20623 #define GTZC_TZIC1_FCR1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
20624 
20625 /*******************  Bits definition for GTZC_TZIC_FCR2 register  **************/
20626 #define GTZC_TZIC1_FCR2_FDCAN1_Pos          GTZC_CFGR2_FDCAN1_Pos
20627 #define GTZC_TZIC1_FCR2_FDCAN1_Msk          GTZC_CFGR2_FDCAN1_Msk
20628 #define GTZC_TZIC1_FCR2_FDCAN2_Pos          GTZC_CFGR2_FDCAN2_Pos
20629 #define GTZC_TZIC1_FCR2_FDCAN2_Msk          GTZC_CFGR2_FDCAN2_Msk
20630 #define GTZC_TZIC1_FCR2_UCPD_Pos            GTZC_CFGR2_UCPD_Pos
20631 #define GTZC_TZIC1_FCR2_UCPD_Msk            GTZC_CFGR2_UCPD_Msk
20632 #define GTZC_TZIC1_FCR2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
20633 #define GTZC_TZIC1_FCR2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
20634 #define GTZC_TZIC1_FCR2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
20635 #define GTZC_TZIC1_FCR2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
20636 #define GTZC_TZIC1_FCR2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
20637 #define GTZC_TZIC1_FCR2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
20638 #define GTZC_TZIC1_FCR2_USART1_Pos          GTZC_CFGR2_USART1_Pos
20639 #define GTZC_TZIC1_FCR2_USART1_Msk          GTZC_CFGR2_USART1_Msk
20640 #define GTZC_TZIC1_FCR2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
20641 #define GTZC_TZIC1_FCR2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
20642 #define GTZC_TZIC1_FCR2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
20643 #define GTZC_TZIC1_FCR2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
20644 #define GTZC_TZIC1_FCR2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
20645 #define GTZC_TZIC1_FCR2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
20646 #define GTZC_TZIC1_FCR2_SPI4_Pos            GTZC_CFGR2_SPI4_Pos
20647 #define GTZC_TZIC1_FCR2_SPI4_Msk            GTZC_CFGR2_SPI4_Msk
20648 #define GTZC_TZIC1_FCR2_SPI6_Pos            GTZC_CFGR2_SPI6_Pos
20649 #define GTZC_TZIC1_FCR2_SPI6_Msk            GTZC_CFGR2_SPI6_Msk
20650 #define GTZC_TZIC1_FCR2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
20651 #define GTZC_TZIC1_FCR2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
20652 #define GTZC_TZIC1_FCR2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
20653 #define GTZC_TZIC1_FCR2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
20654 #define GTZC_TZIC1_FCR2_USB_Pos             GTZC_CFGR2_USB_Pos
20655 #define GTZC_TZIC1_FCR2_USB_Msk             GTZC_CFGR2_USB_Msk
20656 #define GTZC_TZIC1_FCR2_SPI5_Pos            GTZC_CFGR2_SPI5_Pos
20657 #define GTZC_TZIC1_FCR2_SPI5_Msk            GTZC_CFGR2_SPI5_Msk
20658 #define GTZC_TZIC1_FCR2_LPUART1_Pos         GTZC_CFGR2_LPUART1_Pos
20659 #define GTZC_TZIC1_FCR2_LPUART1_Msk         GTZC_CFGR2_LPUART1_Msk
20660 #define GTZC_TZIC1_FCR2_I2C3_Pos            GTZC_CFGR2_I2C3_Pos
20661 #define GTZC_TZIC1_FCR2_I2C3_Msk            GTZC_CFGR2_I2C3_Msk
20662 #define GTZC_TZIC1_FCR2_I2C4_Pos            GTZC_CFGR2_I2C4_Pos
20663 #define GTZC_TZIC1_FCR2_I2C4_Msk            GTZC_CFGR2_I2C4_Msk
20664 #define GTZC_TZIC1_FCR2_LPTIM1_Pos          GTZC_CFGR2_LPTIM1_Pos
20665 #define GTZC_TZIC1_FCR2_LPTIM1_Msk          GTZC_CFGR2_LPTIM1_Msk
20666 #define GTZC_TZIC1_FCR2_LPTIM3_Pos          GTZC_CFGR2_LPTIM3_Pos
20667 #define GTZC_TZIC1_FCR2_LPTIM3_Msk          GTZC_CFGR2_LPTIM3_Msk
20668 #define GTZC_TZIC1_FCR2_LPTIM4_Pos          GTZC_CFGR2_LPTIM4_Pos
20669 #define GTZC_TZIC1_FCR2_LPTIM4_Msk          GTZC_CFGR2_LPTIM4_Msk
20670 #define GTZC_TZIC1_FCR2_LPTIM5_Pos          GTZC_CFGR2_LPTIM5_Pos
20671 #define GTZC_TZIC1_FCR2_LPTIM5_Msk          GTZC_CFGR2_LPTIM5_Msk
20672 
20673 /******************  Bits definition for GTZC_TZIC_FCR3 register  ****************/
20674 #define GTZC_TZIC1_FCR3_LPTIM6_Pos          GTZC_CFGR3_LPTIM6_Pos
20675 #define GTZC_TZIC1_FCR3_LPTIM6_Msk          GTZC_CFGR3_LPTIM6_Msk
20676 #define GTZC_TZIC1_FCR3_VREFBUF_Pos         GTZC_CFGR3_VREFBUF_Pos
20677 #define GTZC_TZIC1_FCR3_VREFBUF_Msk         GTZC_CFGR3_VREFBUF_Msk
20678 #define GTZC_TZIC1_FCR3_CRC_Pos             GTZC_CFGR3_CRC_Pos
20679 #define GTZC_TZIC1_FCR3_CRC_Msk             GTZC_CFGR3_CRC_Msk
20680 #define GTZC_TZIC1_FCR3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
20681 #define GTZC_TZIC1_FCR3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
20682 #define GTZC_TZIC1_FCR3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
20683 #define GTZC_TZIC1_FCR3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
20684 #define GTZC_TZIC1_FCR3_ETHERNET_Pos        GTZC_CFGR3_ETHERNET_Pos
20685 #define GTZC_TZIC1_FCR3_ETHERNET_Msk        GTZC_CFGR3_ETHERNET_Msk
20686 #define GTZC_TZIC1_FCR3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
20687 #define GTZC_TZIC1_FCR3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
20688 #define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
20689 #define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
20690 #define GTZC_TZIC1_FCR3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
20691 #define GTZC_TZIC1_FCR3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
20692 #define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos       GTZC_CFGR3_DCMI_PSSI_Pos
20693 #define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk       GTZC_CFGR3_DCMI_PSSI_Msk
20694 #define GTZC_TZIC1_FCR3_AES_Pos             GTZC_CFGR3_AES_Pos
20695 #define GTZC_TZIC1_FCR3_AES_Msk             GTZC_CFGR3_AES_Msk
20696 #define GTZC_TZIC1_FCR3_HASH_Pos            GTZC_CFGR3_HASH_Pos
20697 #define GTZC_TZIC1_FCR3_HASH_Msk            GTZC_CFGR3_HASH_Msk
20698 #define GTZC_TZIC1_FCR3_RNG_Pos             GTZC_CFGR3_RNG_Pos
20699 #define GTZC_TZIC1_FCR3_RNG_Msk             GTZC_CFGR3_RNG_Msk
20700 #define GTZC_TZIC1_FCR3_SAES_Pos            GTZC_CFGR3_SAES_Pos
20701 #define GTZC_TZIC1_FCR3_SAES_Msk            GTZC_CFGR3_SAES_Msk
20702 #define GTZC_TZIC1_FCR3_PKA_Pos             GTZC_CFGR3_PKA_Pos
20703 #define GTZC_TZIC1_FCR3_PKA_Msk             GTZC_CFGR3_PKA_Msk
20704 #define GTZC_TZIC1_FCR3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
20705 #define GTZC_TZIC1_FCR3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
20706 #define GTZC_TZIC1_FCR3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
20707 #define GTZC_TZIC1_FCR3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
20708 #define GTZC_TZIC1_FCR3_FMC_REG_Pos         GTZC_CFGR3_FMC_REG_Pos
20709 #define GTZC_TZIC1_FCR3_FMC_REG_Msk         GTZC_CFGR3_FMC_REG_Msk
20710 #define GTZC_TZIC1_FCR3_OCTOSPI1_Pos        GTZC_CFGR3_OCTOSPI1_Pos
20711 #define GTZC_TZIC1_FCR3_OCTOSPI1_Msk        GTZC_CFGR3_OCTOSPI1_Msk
20712 #define GTZC_TZIC1_FCR3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
20713 #define GTZC_TZIC1_FCR3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
20714 
20715 /*******************  Bits definition for GTZC_TZIC_FCR4 register  ***************/
20716 #define GTZC_TZIC1_FCR4_GPDMA1_Pos          GTZC_CFGR4_GPDMA1_Pos
20717 #define GTZC_TZIC1_FCR4_GPDMA1_Msk          GTZC_CFGR4_GPDMA1_Msk
20718 #define GTZC_TZIC1_FCR4_GPDMA2_Pos          GTZC_CFGR4_GPDMA2_Pos
20719 #define GTZC_TZIC1_FCR4_GPDMA2_Msk          GTZC_CFGR4_GPDMA2_Msk
20720 #define GTZC_TZIC1_FCR4_FLASH_Pos           GTZC_CFGR4_FLASH_Pos
20721 #define GTZC_TZIC1_FCR4_FLASH_Msk           GTZC_CFGR4_FLASH_Msk
20722 #define GTZC_TZIC1_FCR4_FLASH_REG_Pos       GTZC_CFGR4_FLASH_REG_Pos
20723 #define GTZC_TZIC1_FCR4_FLASH_REG_Msk       GTZC_CFGR4_FLASH_REG_Msk
20724 #define GTZC_TZIC1_FCR4_OTFDEC1_Pos         GTZC_CFGR4_OTFDEC1_Pos
20725 #define GTZC_TZIC1_FCR4_OTFDEC1_Msk         GTZC_CFGR4_OTFDEC1_Msk
20726 #define GTZC_TZIC1_FCR4_SBS_Pos             GTZC_CFGR4_SBS_Pos
20727 #define GTZC_TZIC1_FCR4_SBS_Msk             GTZC_CFGR4_SBS_Msk
20728 #define GTZC_TZIC1_FCR4_RTC_Pos             GTZC_CFGR4_RTC_Pos
20729 #define GTZC_TZIC1_FCR4_RTC_Msk             GTZC_CFGR4_RTC_Msk
20730 #define GTZC_TZIC1_FCR4_TAMP_Pos            GTZC_CFGR4_TAMP_Pos
20731 #define GTZC_TZIC1_FCR4_TAMP_Msk            GTZC_CFGR4_TAMP_Msk
20732 #define GTZC_TZIC1_FCR4_PWR_Pos             GTZC_CFGR4_PWR_Pos
20733 #define GTZC_TZIC1_FCR4_PWR_Msk             GTZC_CFGR4_PWR_Msk
20734 #define GTZC_TZIC1_FCR4_RCC_Pos             GTZC_CFGR4_RCC_Pos
20735 #define GTZC_TZIC1_FCR4_RCC_Msk             GTZC_CFGR4_RCC_Msk
20736 #define GTZC_TZIC1_FCR4_EXTI_Pos            GTZC_CFGR4_EXTI_Pos
20737 #define GTZC_TZIC1_FCR4_EXTI_Msk            GTZC_CFGR4_EXTI_Msk
20738 #define GTZC_TZIC1_FCR4_TZSC_Pos            GTZC_CFGR4_TZSC_Pos
20739 #define GTZC_TZIC1_FCR4_TZSC_Msk            GTZC_CFGR4_TZSC_Msk
20740 #define GTZC_TZIC1_FCR4_TZIC_Pos            GTZC_CFGR4_TZIC_Pos
20741 #define GTZC_TZIC1_FCR4_TZIC_Msk            GTZC_CFGR4_TZIC_Msk
20742 #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos    GTZC_CFGR4_OCTOSPI1_MEM_Pos
20743 #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk    GTZC_CFGR4_OCTOSPI1_MEM_Msk
20744 #define GTZC_TZIC1_FCR4_FMC_MEM_Pos         GTZC_CFGR4_FMC_MEM_Pos
20745 #define GTZC_TZIC1_FCR4_FMC_MEM_Msk         GTZC_CFGR4_FMC_MEM_Msk
20746 #define GTZC_TZIC1_FCR4_BKPSRAM_Pos         GTZC_CFGR4_BKPSRAM_Pos
20747 #define GTZC_TZIC1_FCR4_BKPSRAM_Msk         GTZC_CFGR4_BKPSRAM_Msk
20748 #define GTZC_TZIC1_FCR4_SRAM1_Pos           GTZC_CFGR4_SRAM1_Pos
20749 #define GTZC_TZIC1_FCR4_SRAM1_Msk           GTZC_CFGR4_SRAM1_Msk
20750 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos      GTZC_CFGR4_MPCBB1_REG_Pos
20751 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk      GTZC_CFGR4_MPCBB1_REG_Msk
20752 #define GTZC_TZIC1_FCR4_SRAM2_Pos           GTZC_CFGR4_SRAM2_Pos
20753 #define GTZC_TZIC1_FCR4_SRAM2_Msk           GTZC_CFGR4_SRAM2_Msk
20754 #define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos      GTZC_CFGR4_MPCBB2_REG_Pos
20755 #define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk      GTZC_CFGR4_MPCBB2_REG_Msk
20756 #define GTZC_TZIC1_FCR4_SRAM3_Pos           GTZC_CFGR4_SRAM3_Pos
20757 #define GTZC_TZIC1_FCR4_SRAM3_Msk           GTZC_CFGR4_SRAM3_Msk
20758 #define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos      GTZC_CFGR4_MPCBB3_REG_Pos
20759 #define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk      GTZC_CFGR4_MPCBB3_REG_Msk
20760 
20761 /*******************  Bits definition for GTZC_MPCBB_CR register  *****************/
20762 #define GTZC_MPCBB_CR_GLOCK_Pos             (0U)
20763 #define GTZC_MPCBB_CR_GLOCK_Msk             (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos)       /*!< 0x00000001 */
20764 #define GTZC_MPCBB_CR_INVSECSTATE_Pos       (30U)
20765 #define GTZC_MPCBB_CR_INVSECSTATE_Msk       (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */
20766 #define GTZC_MPCBB_CR_SRWILADIS_Pos         (31U)
20767 #define GTZC_MPCBB_CR_SRWILADIS_Msk         (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos)   /*!< 0x80000000 */
20768 
20769 /*******************  Bits definition for GTZC_MPCBB_CFGLOCKR1 register  ************/
20770 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos      (0U)
20771 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */
20772 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos      (1U)
20773 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */
20774 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos      (2U)
20775 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */
20776 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos      (3U)
20777 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */
20778 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos      (4U)
20779 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */
20780 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos      (5U)
20781 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */
20782 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos      (6U)
20783 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */
20784 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos      (7U)
20785 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */
20786 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos      (8U)
20787 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */
20788 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos      (9U)
20789 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */
20790 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos     (10U)
20791 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */
20792 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos     (11U)
20793 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */
20794 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos     (12U)
20795 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */
20796 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos     (13U)
20797 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */
20798 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos     (14U)
20799 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */
20800 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos     (15U)
20801 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */
20802 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos     (16U)
20803 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */
20804 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos     (17U)
20805 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */
20806 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos     (18U)
20807 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */
20808 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos     (19U)
20809 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */
20810 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos     (20U)
20811 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */
20812 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos     (21U)
20813 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */
20814 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos     (22U)
20815 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */
20816 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos     (23U)
20817 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */
20818 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos     (24U)
20819 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */
20820 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos     (25U)
20821 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */
20822 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos     (26U)
20823 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */
20824 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos     (27U)
20825 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */
20826 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos     (28U)
20827 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */
20828 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos     (29U)
20829 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */
20830 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos     (30U)
20831 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */
20832 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos     (31U)
20833 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */
20834 
20835 
20836 /******************************************************************************/
20837 /*                                                                            */
20838 /*                                    UCPD                                    */
20839 /*                                                                            */
20840 /******************************************************************************/
20841 /********************  Bits definition for UCPD_CFG1 register  *******************/
20842 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
20843 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x0000003F */
20844 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk                /*!< Number of cycles (minus 1) for a half bit clock */
20845 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000001 */
20846 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000002 */
20847 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000004 */
20848 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000008 */
20849 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000010 */
20850 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000020 */
20851 #define UCPD_CFG1_IFRGAP_Pos                (6U)
20852 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x000007C0 */
20853 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                    /*!< Clock divider value to generates Interframe gap */
20854 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000040 */
20855 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000080 */
20856 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000100 */
20857 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000200 */
20858 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000400 */
20859 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
20860 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x0000F800 */
20861 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk                  /*!< Number of cycles (minus 1) of the half bit clock */
20862 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00000800 */
20863 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00001000 */
20864 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00002000 */
20865 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00004000 */
20866 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00008000 */
20867 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
20868 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x000E0000 */
20869 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk               /*!< Prescaler for UCPDCLK */
20870 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00020000 */
20871 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00040000 */
20872 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00080000 */
20873 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
20874 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x1FF00000 */
20875 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk                /*!< Receiver ordered set detection enable */
20876 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00100000 */
20877 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00200000 */
20878 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00400000 */
20879 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00800000 */
20880 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x01000000 */
20881 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x02000000 */
20882 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x04000000 */
20883 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x08000000 */
20884 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x10000000 */
20885 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
20886 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)        /*!< 0x20000000 */
20887 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                   /*!< DMA transmission requests enable   */
20888 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
20889 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)        /*!< 0x40000000 */
20890 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                   /*!< DMA reception requests enable   */
20891 #define UCPD_CFG1_UCPDEN_Pos                (31U)
20892 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)         /*!< 0x80000000 */
20893 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                    /*!< USB Power Delivery Block Enable */
20894 
20895 /********************  Bits definition for UCPD_CFG2 register  *******************/
20896 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
20897 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)      /*!< 0x00000001 */
20898 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk                 /*!< Enables an Rx pre-filter for the BMC decoder */
20899 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
20900 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)      /*!< 0x00000002 */
20901 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk                 /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
20902 #define UCPD_CFG2_FORCECLK_Pos              (2U)
20903 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)       /*!< 0x00000004 */
20904 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk                  /*!< Controls forcing of the clock request UCPDCLK_REQ */
20905 #define UCPD_CFG2_WUPEN_Pos                 (3U)
20906 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)          /*!< 0x00000008 */
20907 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                     /*!< Wakeup from STOP enable */
20908 #define UCPD_CFG2_RXAFILTEN_Pos             (8U)
20909 #define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)      /*!< 0x00000100 */
20910 #define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk                 /*!< Rx analog filter enable */
20911 
20912 /********************  Bits definition for UCPD_CFG3 register  *******************/
20913 #define UCPD_CFG3_TRIM1_NG_CCRPD_Pos        (0U)
20914 #define UCPD_CFG3_TRIM1_NG_CCRPD_Msk        (0xFUL << UCPD_CFG3_TRIM1_NG_CCRPD_Pos) /*!< 0x0000000F */
20915 #define UCPD_CFG3_TRIM1_NG_CCRPD            UCPD_CFG3_TRIM1_NG_CCRPD_Msk            /*!< SW trim value for RPDEFAULT resistors (CC1) */
20916 #define UCPD_CFG3_TRIM1_NG_CC1A5_Pos        (4U)
20917 #define UCPD_CFG3_TRIM1_NG_CC1A5_Msk        (0x1FUL << UCPD_CFG3_TRIM1_NG_CC1A5_Pos) /*!< 0x000001F0 */
20918 #define UCPD_CFG3_TRIM1_NG_CC1A5            UCPD_CFG3_TRIM1_NG_CC1A5_Msk            /*!< SW trim value for RP1A5 resistors (CC1) */
20919 #define UCPD_CFG3_TRIM1_NG_CC3A0_Pos        (9U)
20920 #define UCPD_CFG3_TRIM1_NG_CC3A0_Msk        (0xFUL << UCPD_CFG3_TRIM1_NG_CC3A0_Pos) /*!< 0x00001E00 */
20921 #define UCPD_CFG3_TRIM1_NG_CC3A0            UCPD_CFG3_TRIM1_NG_CC3A0_Msk            /*!< SW trim value for RP3A0 resistors (CC1) */
20922 #define UCPD_CFG3_TRIM2_NG_CCRPD_Pos        (16U)
20923 #define UCPD_CFG3_TRIM2_NG_CCRPD_Msk        (0xFUL << UCPD_CFG3_TRIM2_NG_CCRPD_Pos) /*!< 0x000F0000 */
20924 #define UCPD_CFG3_TRIM2_NG_CCRPD            UCPD_CFG3_TRIM2_NG_CCRPD_Msk            /*!< SW trim value for RPDEFAULT resistors (CC1) */
20925 #define UCPD_CFG3_TRIM2_NG_CC1A5_Pos        (20U)
20926 #define UCPD_CFG3_TRIM2_NG_CC1A5_Msk        (0x1FUL << UCPD_CFG3_TRIM2_NG_CC1A5_Pos) /*!< 0x01F00000 */
20927 #define UCPD_CFG3_TRIM2_NG_CC1A5            UCPD_CFG3_TRIM2_NG_CC1A5_Msk            /*!< SW trim value for RP1A5 resistors (CC1) */
20928 #define UCPD_CFG3_TRIM2_NG_CC3A0_Pos        (25U)
20929 #define UCPD_CFG3_TRIM2_NG_CC3A0_Msk        (0xFUL << UCPD_CFG3_TRIM2_NG_CC3A0_Pos) /*!< 0x1E000000 */
20930 #define UCPD_CFG3_TRIM2_NG_CC3A0            UCPD_CFG3_TRIM2_NG_CC3A0_Msk            /*!< SW trim value for RP3A0 resistors (CC1) */
20931 
20932 /********************  Bits definition for UCPD_CR register  ********************/
20933 #define UCPD_CR_TXMODE_Pos                  (0U)
20934 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000003 */
20935 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                      /*!< Type of Tx packet  */
20936 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000001 */
20937 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000002 */
20938 #define UCPD_CR_TXSEND_Pos                  (2U)
20939 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)           /*!< 0x00000004 */
20940 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                      /*!< Type of Tx packet  */
20941 #define UCPD_CR_TXHRST_Pos                  (3U)
20942 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)           /*!< 0x00000008 */
20943 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                      /*!< Command to send a Tx Hard Reset  */
20944 #define UCPD_CR_RXMODE_Pos                  (4U)
20945 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)           /*!< 0x00000010 */
20946 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                      /*!< Receiver mode  */
20947 #define UCPD_CR_PHYRXEN_Pos                 (5U)
20948 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)          /*!< 0x00000020 */
20949 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                     /*!< Controls enable of USB Power Delivery receiver  */
20950 #define UCPD_CR_PHYCCSEL_Pos                (6U)
20951 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)         /*!< 0x00000040 */
20952 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                    /*!<  */
20953 #define UCPD_CR_ANASUBMODE_Pos              (7U)
20954 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000180 */
20955 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk                  /*!< Analog PHY sub-mode   */
20956 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000080 */
20957 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000100 */
20958 #define UCPD_CR_ANAMODE_Pos                 (9U)
20959 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)          /*!< 0x00000200 */
20960 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                     /*!< Analog PHY working mode   */
20961 #define UCPD_CR_CCENABLE_Pos                (10U)
20962 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000C00 */
20963 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                    /*!<  */
20964 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000400 */
20965 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000800 */
20966 #define UCPD_CR_USEEXTPHY_Pos               (12U)
20967 #define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)        /*!< 0x00001000 */
20968 #define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                   /*!< Controls enable of USB Power Delivery transmitter */
20969 #define UCPD_CR_CC2VCONNEN_Pos              (13U)
20970 #define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)       /*!< 0x00002000 */
20971 #define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk                  /*!< VCONN enable for CC2 */
20972 #define UCPD_CR_CC1VCONNEN_Pos              (14U)
20973 #define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)       /*!< 0x00004000 */
20974 #define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk                  /*!< VCONN enable for CC1 */
20975 #define UCPD_CR_DBATEN_Pos                  (15U)
20976 #define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)           /*!< 0x00008000 */
20977 #define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                      /*!< Enable dead battery behavior (Active High) */
20978 #define UCPD_CR_FRSRXEN_Pos                 (16U)
20979 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)          /*!< 0x00010000 */
20980 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                     /*!< Enable FRS request detection function */
20981 #define UCPD_CR_FRSTX_Pos                   (17U)
20982 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)            /*!< 0x00020000 */
20983 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                       /*!< Signal Fast Role Swap request */
20984 #define UCPD_CR_RDCH_Pos                    (18U)
20985 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)             /*!< 0x00040000 */
20986 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                        /*!<  */
20987 #define UCPD_CR_RPUSBABSENT_Pos             (19U)
20988 #define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)      /*!< 0x00080000 */
20989 #define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk                 /*!<  */
20990 #define UCPD_CR_CC1TCDIS_Pos                (20U)
20991 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)         /*!< 0x00100000 */
20992 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                    /*!< The bit allows the Type-C detector for CC0 to be disabled. */
20993 #define UCPD_CR_CC2TCDIS_Pos                (21U)
20994 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)         /*!< 0x00200000 */
20995 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                    /*!< The bit allows the Type-C detector for CC2 to be disabled. */
20996 
20997 /********************  Bits definition for UCPD_IMR register  *******************/
20998 #define UCPD_IMR_TXISIE_Pos                 (0U)
20999 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)          /*!< 0x00000001 */
21000 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                     /*!< Enable TXIS interrupt  */
21001 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
21002 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)     /*!< 0x00000002 */
21003 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk                /*!< Enable TXMSGDISC interrupt  */
21004 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
21005 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)     /*!< 0x00000004 */
21006 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk                /*!< Enable TXMSGSENT interrupt  */
21007 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
21008 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)      /*!< 0x00000008 */
21009 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk                 /*!< Enable TXMSGABT interrupt  */
21010 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
21011 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)      /*!< 0x00000010 */
21012 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk                 /*!< Enable HRSTDISC interrupt  */
21013 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
21014 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)      /*!< 0x00000020 */
21015 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk                 /*!< Enable HRSTSENT interrupt  */
21016 #define UCPD_IMR_TXUNDIE_Pos                (6U)
21017 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)         /*!< 0x00000040 */
21018 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                    /*!< Enable TXUND interrupt  */
21019 #define UCPD_IMR_RXNEIE_Pos                 (8U)
21020 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)          /*!< 0x00000100 */
21021 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                     /*!< Enable RXNE interrupt  */
21022 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
21023 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)      /*!< 0x00000200 */
21024 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk                 /*!< Enable RXORDDET interrupt  */
21025 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
21026 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)     /*!< 0x00000400 */
21027 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk                /*!< Enable RXHRSTDET interrupt  */
21028 #define UCPD_IMR_RXOVRIE_Pos                (11U)
21029 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)         /*!< 0x00000800 */
21030 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                    /*!< Enable RXOVR interrupt  */
21031 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
21032 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)      /*!< 0x00001000 */
21033 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk                 /*!< Enable RXMSGEND interrupt  */
21034 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
21035 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)     /*!< 0x00004000 */
21036 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk                /*!< Enable TYPECEVT1IE interrupt  */
21037 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
21038 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)     /*!< 0x00008000 */
21039 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk                /*!< Enable TYPECEVT2IE interrupt  */
21040 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
21041 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)        /*!< 0x00100000 */
21042 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                   /*!< Fast Role Swap interrupt  */
21043 
21044 /********************  Bits definition for UCPD_SR register  ********************/
21045 #define UCPD_SR_TXIS_Pos                    (0U)
21046 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)             /*!< 0x00000001 */
21047 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                        /*!< Transmit interrupt status  */
21048 #define UCPD_SR_TXMSGDISC_Pos               (1U)
21049 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)        /*!< 0x00000002 */
21050 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                   /*!< Transmit message discarded interrupt  */
21051 #define UCPD_SR_TXMSGSENT_Pos               (2U)
21052 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)        /*!< 0x00000004 */
21053 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                   /*!< Transmit message sent interrupt  */
21054 #define UCPD_SR_TXMSGABT_Pos                (3U)
21055 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)         /*!< 0x00000008 */
21056 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                    /*!< Transmit message abort interrupt  */
21057 #define UCPD_SR_HRSTDISC_Pos                (4U)
21058 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)         /*!< 0x00000010 */
21059 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                    /*!< HRST discarded interrupt  */
21060 #define UCPD_SR_HRSTSENT_Pos                (5U)
21061 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)         /*!< 0x00000020 */
21062 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                    /*!< HRST sent interrupt  */
21063 #define UCPD_SR_TXUND_Pos                   (6U)
21064 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)            /*!< 0x00000040 */
21065 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                       /*!< Tx data underrun condition interrupt  */
21066 #define UCPD_SR_RXNE_Pos                    (8U)
21067 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)             /*!< 0x00000100 */
21068 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                        /*!< Receive data register not empty interrupt  */
21069 #define UCPD_SR_RXORDDET_Pos                (9U)
21070 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)         /*!< 0x00000200 */
21071 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                    /*!< Rx ordered set (4 K-codes) detected interrupt  */
21072 #define UCPD_SR_RXHRSTDET_Pos               (10U)
21073 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)        /*!< 0x00000400 */
21074 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                   /*!< Rx Hard Reset detect interrupt  */
21075 #define UCPD_SR_RXOVR_Pos                   (11U)
21076 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)            /*!< 0x00000800 */
21077 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                       /*!< Rx data overflow interrupt  */
21078 #define UCPD_SR_RXMSGEND_Pos                (12U)
21079 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)         /*!< 0x00001000 */
21080 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                    /*!< Rx message received  */
21081 #define UCPD_SR_RXERR_Pos                   (13U)
21082 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)            /*!< 0x00002000 */
21083 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                       /*!< RX Error */
21084 #define UCPD_SR_TYPECEVT1_Pos               (14U)
21085 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)        /*!< 0x00004000 */
21086 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                   /*!< Type C voltage level event on CC1  */
21087 #define UCPD_SR_TYPECEVT2_Pos               (15U)
21088 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)        /*!< 0x00008000 */
21089 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                   /*!< Type C voltage level event on CC2  */
21090 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
21091 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */
21092 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk            /*!< Status of DC level on CC1 pin  */
21093 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */
21094 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */
21095 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
21096 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */
21097 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk            /*!<Status of DC level on CC2 pin  */
21098 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00040000 */
21099 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00080000 */
21100 #define UCPD_SR_FRSEVT_Pos                  (20U)
21101 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)           /*!< 0x00100000 */
21102 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                      /*!< Fast Role Swap detection event  */
21103 
21104 /********************  Bits definition for UCPD_ICR register  *******************/
21105 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
21106 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)     /*!< 0x00000002 */
21107 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk                /*!< Tx message discarded flag (TXMSGDISC) clear  */
21108 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
21109 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)     /*!< 0x00000004 */
21110 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk                /*!< Tx message sent flag (TXMSGSENT) clear  */
21111 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
21112 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)      /*!< 0x00000008 */
21113 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk                 /*!< Tx message abort flag (TXMSGABT) clear  */
21114 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
21115 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)      /*!< 0x00000010 */
21116 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk                 /*!< Hard reset discarded flag (HRSTDISC) clear  */
21117 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
21118 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)      /*!< 0x00000020 */
21119 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk                 /*!< Hard reset sent flag (HRSTSENT) clear  */
21120 #define UCPD_ICR_TXUNDCF_Pos                (6U)
21121 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)         /*!< 0x00000040 */
21122 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                    /*!< Tx underflow flag (TXUND) clear  */
21123 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
21124 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)      /*!< 0x00000200 */
21125 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk                 /*!< Rx ordered set detect flag (RXORDDET) clear  */
21126 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
21127 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)     /*!< 0x00000400 */
21128 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk                /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
21129 #define UCPD_ICR_RXOVRCF_Pos                (11U)
21130 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)         /*!< 0x00000800 */
21131 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                    /*!< Rx overflow flag (RXOVR) clear  */
21132 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
21133 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)      /*!< 0x00001000 */
21134 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk                 /*!< Rx message received flag (RXMSGEND) clear  */
21135 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
21136 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)     /*!< 0x00004000 */
21137 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk                /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
21138 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
21139 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)     /*!< 0x00008000 */
21140 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk                /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
21141 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
21142 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)        /*!< 0x00100000 */
21143 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                   /*!< Fast Role Swap event flag clear  */
21144 
21145 /********************  Bits definition for UCPD_TXORDSET register  **************/
21146 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
21147 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos) /*!< 0x000FFFFF */
21148 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk             /*!< Tx Ordered Set */
21149 
21150 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
21151 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
21152 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)  /*!< 0x000003FF */
21153 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk               /*!< Tx payload size in bytes  */
21154 
21155 /********************  Bits definition for UCPD_TXDR register  *******************/
21156 #define UCPD_TXDR_TXDATA_Pos                (0U)
21157 #define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)        /*!< 0x000000FF */
21158 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                    /*!< Tx Data Register */
21159 
21160 /********************  Bits definition for UCPD_RXORDSET register  **************/
21161 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
21162 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000007 */
21163 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk             /*!< Rx Ordered Set Code detected  */
21164 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000001 */
21165 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000002 */
21166 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000004 */
21167 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
21168 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos) /*!< 0x00000008 */
21169 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk            /*!< Rx Ordered Set Debug indication */
21170 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
21171 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos) /*!< 0x00000070 */
21172 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk        /*!< Rx Ordered Set corrupted K-Codes (Debug) */
21173 
21174 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
21175 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
21176 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)  /*!< 0x000003FF */
21177 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk               /*!< Rx payload size in bytes  */
21178 
21179 /********************  Bits definition for UCPD_RXDR register  *******************/
21180 #define UCPD_RXDR_RXDATA_Pos                (0U)
21181 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)        /*!< 0x000000FF */
21182 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                    /*!< 8-bit receive data  */
21183 
21184 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
21185 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
21186 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos) /*!< 0x000FFFFF */
21187 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk             /*!< RX Ordered Set Extension Register 1 */
21188 
21189 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
21190 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
21191 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos) /*!< 0x000FFFFF */
21192 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk             /*!< RX Ordered Set Extension Register 1 */
21193 
21194 /********************  Bits definition for UCPD_IPVER register  **************/
21195 #define UCPD_IPVER_Pos                      (0U)
21196 #define UCPD_IPVER_Msk                      (0xFFFFFFFFUL << UCPD_IPVER_Pos)        /*!< 0xFFFFFFFF */
21197 #define UCPD_IPVER                          UCPD_IPVER_Msk                          /*!< IP version  */
21198 
21199 /********************  Bits definition for UCPD_IPID register  **************/
21200 #define UCPD_IPID_Pos                       (0U)
21201 #define UCPD_IPID_Msk                       (0xFFFFFFFFUL << UCPD_IPID_Pos)         /*!< 0xFFFFFFFF */
21202 #define UCPD_IPID                           UCPD_IPID_Msk                           /*!< IP ID register  */
21203 
21204 /********************  Bits definition for UCPD_MID register  **************/
21205 #define UCPD_MID_Pos                        (0U)
21206 #define UCPD_MID_Msk                        (0xFFFFFFFFUL << UCPD_MID_Pos)          /*!< 0xFFFFFFFF */
21207 #define UCPD_MID                            UCPD_MID_Msk                            /*!< IP Magic ID register  */
21208 
21209 
21210 /******************************************************************************/
21211 /*                                                                            */
21212 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
21213 /*                                                                            */
21214 /******************************************************************************/
21215 /******************  Bit definition for USART_CR1 register  *******************/
21216 #define USART_CR1_UE_Pos                    (0U)
21217 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
21218 #define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
21219 #define USART_CR1_UESM_Pos                  (1U)
21220 #define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
21221 #define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
21222 #define USART_CR1_RE_Pos                    (2U)
21223 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
21224 #define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
21225 #define USART_CR1_TE_Pos                    (3U)
21226 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
21227 #define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
21228 #define USART_CR1_IDLEIE_Pos                (4U)
21229 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
21230 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
21231 #define USART_CR1_RXNEIE_Pos                (5U)
21232 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
21233 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
21234 #define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
21235 #define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
21236 #define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
21237 #define USART_CR1_TCIE_Pos                  (6U)
21238 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
21239 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
21240 #define USART_CR1_TXEIE_Pos                 (7U)
21241 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
21242 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
21243 #define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
21244 #define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
21245 #define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
21246 #define USART_CR1_PEIE_Pos                  (8U)
21247 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
21248 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
21249 #define USART_CR1_PS_Pos                    (9U)
21250 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
21251 #define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
21252 #define USART_CR1_PCE_Pos                   (10U)
21253 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
21254 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
21255 #define USART_CR1_WAKE_Pos                  (11U)
21256 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
21257 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
21258 #define USART_CR1_M_Pos                     (12U)
21259 #define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
21260 #define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
21261 #define USART_CR1_M0_Pos                    (12U)
21262 #define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
21263 #define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
21264 #define USART_CR1_MME_Pos                   (13U)
21265 #define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
21266 #define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
21267 #define USART_CR1_CMIE_Pos                  (14U)
21268 #define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
21269 #define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
21270 #define USART_CR1_OVER8_Pos                 (15U)
21271 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
21272 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
21273 #define USART_CR1_DEDT_Pos                  (16U)
21274 #define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
21275 #define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
21276 #define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
21277 #define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
21278 #define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
21279 #define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
21280 #define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
21281 #define USART_CR1_DEAT_Pos                  (21U)
21282 #define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
21283 #define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
21284 #define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
21285 #define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
21286 #define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
21287 #define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
21288 #define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
21289 #define USART_CR1_RTOIE_Pos                 (26U)
21290 #define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
21291 #define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out interrupt enable */
21292 #define USART_CR1_EOBIE_Pos                 (27U)
21293 #define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
21294 #define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block interrupt enable */
21295 #define USART_CR1_M1_Pos                    (28U)
21296 #define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
21297 #define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
21298 #define USART_CR1_FIFOEN_Pos                (29U)
21299 #define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
21300 #define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
21301 #define USART_CR1_TXFEIE_Pos                (30U)
21302 #define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
21303 #define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TXFIFO empty interrupt enable */
21304 #define USART_CR1_RXFFIE_Pos                (31U)
21305 #define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
21306 #define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RXFIFO Full interrupt enable */
21307 
21308 /******************  Bit definition for USART_CR2 register  *******************/
21309 #define USART_CR2_SLVEN_Pos                 (0U)
21310 #define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
21311 #define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
21312 #define USART_CR2_DIS_NSS_Pos               (3U)
21313 #define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
21314 #define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
21315 #define USART_CR2_ADDM7_Pos                 (4U)
21316 #define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
21317 #define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
21318 #define USART_CR2_LBDL_Pos                  (5U)
21319 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
21320 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
21321 #define USART_CR2_LBDIE_Pos                 (6U)
21322 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
21323 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
21324 #define USART_CR2_LBCL_Pos                  (8U)
21325 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
21326 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
21327 #define USART_CR2_CPHA_Pos                  (9U)
21328 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
21329 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
21330 #define USART_CR2_CPOL_Pos                  (10U)
21331 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
21332 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
21333 #define USART_CR2_CLKEN_Pos                 (11U)
21334 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
21335 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
21336 #define USART_CR2_STOP_Pos                  (12U)
21337 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
21338 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
21339 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
21340 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
21341 #define USART_CR2_LINEN_Pos                 (14U)
21342 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
21343 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
21344 #define USART_CR2_SWAP_Pos                  (15U)
21345 #define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
21346 #define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
21347 #define USART_CR2_RXINV_Pos                 (16U)
21348 #define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
21349 #define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
21350 #define USART_CR2_TXINV_Pos                 (17U)
21351 #define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
21352 #define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
21353 #define USART_CR2_DATAINV_Pos               (18U)
21354 #define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
21355 #define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
21356 #define USART_CR2_MSBFIRST_Pos              (19U)
21357 #define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
21358 #define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
21359 #define USART_CR2_ABREN_Pos                 (20U)
21360 #define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
21361 #define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
21362 #define USART_CR2_ABRMODE_Pos               (21U)
21363 #define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
21364 #define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
21365 #define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
21366 #define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
21367 #define USART_CR2_RTOEN_Pos                 (23U)
21368 #define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
21369 #define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
21370 #define USART_CR2_ADD_Pos                   (24U)
21371 #define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
21372 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
21373 
21374 /******************  Bit definition for USART_CR3 register  *******************/
21375 #define USART_CR3_EIE_Pos                   (0U)
21376 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
21377 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
21378 #define USART_CR3_IREN_Pos                  (1U)
21379 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
21380 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
21381 #define USART_CR3_IRLP_Pos                  (2U)
21382 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
21383 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
21384 #define USART_CR3_HDSEL_Pos                 (3U)
21385 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
21386 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
21387 #define USART_CR3_NACK_Pos                  (4U)
21388 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
21389 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
21390 #define USART_CR3_SCEN_Pos                  (5U)
21391 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
21392 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
21393 #define USART_CR3_DMAR_Pos                  (6U)
21394 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
21395 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
21396 #define USART_CR3_DMAT_Pos                  (7U)
21397 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
21398 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
21399 #define USART_CR3_RTSE_Pos                  (8U)
21400 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
21401 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
21402 #define USART_CR3_CTSE_Pos                  (9U)
21403 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
21404 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
21405 #define USART_CR3_CTSIE_Pos                 (10U)
21406 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
21407 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
21408 #define USART_CR3_ONEBIT_Pos                (11U)
21409 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
21410 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
21411 #define USART_CR3_OVRDIS_Pos                (12U)
21412 #define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
21413 #define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
21414 #define USART_CR3_DDRE_Pos                  (13U)
21415 #define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
21416 #define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
21417 #define USART_CR3_DEM_Pos                   (14U)
21418 #define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
21419 #define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
21420 #define USART_CR3_DEP_Pos                   (15U)
21421 #define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
21422 #define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
21423 #define USART_CR3_SCARCNT_Pos               (17U)
21424 #define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
21425 #define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
21426 #define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
21427 #define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
21428 #define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
21429 #define USART_CR3_WUS_Pos                   (20U)
21430 #define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
21431 #define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
21432 #define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
21433 #define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
21434 #define USART_CR3_WUFIE_Pos                 (22U)
21435 #define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
21436 #define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
21437 #define USART_CR3_TXFTIE_Pos                (23U)
21438 #define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
21439 #define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TXFIFO threshold interrupt enable */
21440 #define USART_CR3_TCBGTIE_Pos               (24U)
21441 #define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
21442 #define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
21443 #define USART_CR3_RXFTCFG_Pos               (25U)
21444 #define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
21445 #define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RXFIFO FIFO threshold configuration */
21446 #define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
21447 #define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
21448 #define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
21449 #define USART_CR3_RXFTIE_Pos                (28U)
21450 #define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
21451 #define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RXFIFO threshold interrupt enable */
21452 #define USART_CR3_TXFTCFG_Pos               (29U)
21453 #define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
21454 #define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TXFIFO threshold configuration */
21455 #define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
21456 #define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
21457 #define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
21458 
21459 /******************  Bit definition for USART_BRR register  *******************/
21460 #define USART_BRR_LPUART_Pos                (0U)
21461 #define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
21462 #define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
21463 #define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
21464 
21465 /******************  Bit definition for USART_GTPR register  ******************/
21466 #define USART_GTPR_PSC_Pos                  (0U)
21467 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
21468 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
21469 #define USART_GTPR_GT_Pos                   (8U)
21470 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
21471 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
21472 
21473 /*******************  Bit definition for USART_RTOR register  *****************/
21474 #define USART_RTOR_RTO_Pos                  (0U)
21475 #define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
21476 #define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
21477 #define USART_RTOR_BLEN_Pos                 (24U)
21478 #define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
21479 #define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
21480 
21481 /*******************  Bit definition for USART_RQR register  ******************/
21482 #define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
21483 #define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
21484 #define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
21485 #define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
21486 #define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */
21487 
21488 /*******************  Bit definition for USART_ISR register  ******************/
21489 #define USART_ISR_PE_Pos                    (0U)
21490 #define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
21491 #define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
21492 #define USART_ISR_FE_Pos                    (1U)
21493 #define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
21494 #define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
21495 #define USART_ISR_NE_Pos                    (2U)
21496 #define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
21497 #define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise detected Flag */
21498 #define USART_ISR_ORE_Pos                   (3U)
21499 #define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
21500 #define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
21501 #define USART_ISR_IDLE_Pos                  (4U)
21502 #define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
21503 #define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
21504 #define USART_ISR_RXNE_Pos                  (5U)
21505 #define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
21506 #define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
21507 #define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
21508 #define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
21509 #define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
21510 #define USART_ISR_TC_Pos                    (6U)
21511 #define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
21512 #define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
21513 #define USART_ISR_TXE_Pos                   (7U)
21514 #define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
21515 #define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
21516 #define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
21517 #define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
21518 #define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
21519 #define USART_ISR_LBDF_Pos                  (8U)
21520 #define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
21521 #define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
21522 #define USART_ISR_CTSIF_Pos                 (9U)
21523 #define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
21524 #define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt flag */
21525 #define USART_ISR_CTS_Pos                   (10U)
21526 #define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
21527 #define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS flag */
21528 #define USART_ISR_RTOF_Pos                  (11U)
21529 #define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
21530 #define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
21531 #define USART_ISR_EOBF_Pos                  (12U)
21532 #define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
21533 #define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
21534 #define USART_ISR_UDR_Pos                   (13U)
21535 #define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
21536 #define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI slave underrun error flag */
21537 #define USART_ISR_ABRE_Pos                  (14U)
21538 #define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
21539 #define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
21540 #define USART_ISR_ABRF_Pos                  (15U)
21541 #define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
21542 #define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
21543 #define USART_ISR_BUSY_Pos                  (16U)
21544 #define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
21545 #define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
21546 #define USART_ISR_CMF_Pos                   (17U)
21547 #define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
21548 #define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
21549 #define USART_ISR_SBKF_Pos                  (18U)
21550 #define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
21551 #define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
21552 #define USART_ISR_RWU_Pos                   (19U)
21553 #define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
21554 #define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
21555 #define USART_ISR_WUF_Pos                   (20U)
21556 #define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
21557 #define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
21558 #define USART_ISR_TEACK_Pos                 (21U)
21559 #define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
21560 #define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
21561 #define USART_ISR_REACK_Pos                 (22U)
21562 #define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
21563 #define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
21564 #define USART_ISR_TXFE_Pos                  (23U)
21565 #define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
21566 #define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TXFIFO Empty */
21567 #define USART_ISR_RXFF_Pos                  (24U)
21568 #define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
21569 #define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RXFIFO Full */
21570 #define USART_ISR_TCBGT_Pos                 (25U)
21571 #define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
21572 #define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
21573 #define USART_ISR_RXFT_Pos                  (26U)
21574 #define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
21575 #define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RXFIFO threshold flag */
21576 #define USART_ISR_TXFT_Pos                  (27U)
21577 #define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
21578 #define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TXFIFO threshold flag */
21579 
21580 /*******************  Bit definition for USART_ICR register  ******************/
21581 #define USART_ICR_PECF_Pos                  (0U)
21582 #define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
21583 #define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
21584 #define USART_ICR_FECF_Pos                  (1U)
21585 #define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
21586 #define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
21587 #define USART_ICR_NECF_Pos                  (2U)
21588 #define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
21589 #define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise detected Clear Flag */
21590 #define USART_ICR_ORECF_Pos                 (3U)
21591 #define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
21592 #define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
21593 #define USART_ICR_IDLECF_Pos                (4U)
21594 #define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
21595 #define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
21596 #define USART_ICR_TXFECF_Pos                (5U)
21597 #define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
21598 #define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TXFIFO empty Clear flag */
21599 #define USART_ICR_TCCF_Pos                  (6U)
21600 #define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
21601 #define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
21602 #define USART_ICR_TCBGTCF_Pos               (7U)
21603 #define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
21604 #define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
21605 #define USART_ICR_LBDCF_Pos                 (8U)
21606 #define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
21607 #define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
21608 #define USART_ICR_CTSCF_Pos                 (9U)
21609 #define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
21610 #define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
21611 #define USART_ICR_RTOCF_Pos                 (11U)
21612 #define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
21613 #define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
21614 #define USART_ICR_EOBCF_Pos                 (12U)
21615 #define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
21616 #define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
21617 #define USART_ICR_UDRCF_Pos                 (13U)
21618 #define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
21619 #define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
21620 #define USART_ICR_CMCF_Pos                  (17U)
21621 #define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
21622 #define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
21623 #define USART_ICR_WUCF_Pos                  (20U)
21624 #define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
21625 #define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
21626 
21627 /*******************  Bit definition for USART_RDR register  ******************/
21628 #define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
21629 
21630 /*******************  Bit definition for USART_TDR register  ******************/
21631 #define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
21632 
21633 /*******************  Bit definition for USART_PRESC register  ****************/
21634 #define USART_PRESC_PRESCALER_Pos           (0U)
21635 #define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
21636 #define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
21637 #define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
21638 #define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
21639 #define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
21640 #define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
21641 
21642 /*******************  Bit definition for USART_HWCFGR2 register  **************/
21643 #define USART_HWCFGR2_CFG1_Pos              (0U)
21644 #define USART_HWCFGR2_CFG1_Msk              (0xFUL << USART_HWCFGR2_CFG1_Pos)       /*!< 0x0000000F */
21645 #define USART_HWCFGR2_CFG1                  USART_HWCFGR2_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
21646 #define USART_HWCFGR2_CFG2_Pos              (4U)
21647 #define USART_HWCFGR2_CFG2_Msk              (0xFUL << USART_HWCFGR2_CFG2_Pos)       /*!< 0x000000F0 */
21648 #define USART_HWCFGR2_CFG2                  USART_HWCFGR2_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
21649 
21650 /*******************  Bit definition for USART_HWCFGR1 register  **************/
21651 #define USART_HWCFGR1_CFG1_Pos              (0U)
21652 #define USART_HWCFGR1_CFG1_Msk              (0xFUL << USART_HWCFGR1_CFG1_Pos)       /*!< 0x0000000F */
21653 #define USART_HWCFGR1_CFG1                  USART_HWCFGR1_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
21654 #define USART_HWCFGR1_CFG2_Pos              (4U)
21655 #define USART_HWCFGR1_CFG2_Msk              (0xFUL << USART_HWCFGR1_CFG2_Pos)       /*!< 0x000000F0 */
21656 #define USART_HWCFGR1_CFG2                  USART_HWCFGR1_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
21657 #define USART_HWCFGR1_CFG3_Pos              (8U)
21658 #define USART_HWCFGR1_CFG3_Msk              (0xFUL << USART_HWCFGR1_CFG3_Pos)       /*!< 0x00000F00 */
21659 #define USART_HWCFGR1_CFG3                  USART_HWCFGR1_CFG3_Msk                  /*!< CFG3[11:8] bits (USART hardware configuration 3) */
21660 #define USART_HWCFGR1_CFG4_Pos              (12U)
21661 #define USART_HWCFGR1_CFG4_Msk              (0xFUL << USART_HWCFGR1_CFG4_Pos)       /*!< 0x0000F000 */
21662 #define USART_HWCFGR1_CFG4                  USART_HWCFGR1_CFG4_Msk                  /*!< CFG4[15:12] bits (USART hardware configuration 4) */
21663 #define USART_HWCFGR1_CFG5_Pos              (16U)
21664 #define USART_HWCFGR1_CFG5_Msk              (0xFUL << USART_HWCFGR1_CFG5_Pos)       /*!< 0x000F0000 */
21665 #define USART_HWCFGR1_CFG5                  USART_HWCFGR1_CFG5_Msk                  /*!< CFG5[19:16] bits (USART hardware configuration 5) */
21666 #define USART_HWCFGR1_CFG6_Pos              (20U)
21667 #define USART_HWCFGR1_CFG6_Msk              (0xFUL << USART_HWCFGR1_CFG6_Pos)       /*!< 0x00F00000 */
21668 #define USART_HWCFGR1_CFG6                  USART_HWCFGR1_CFG6_Msk                  /*!< CFG6[23:20] bits (USART hardware configuration 6) */
21669 #define USART_HWCFGR1_CFG7_Pos              (24U)
21670 #define USART_HWCFGR1_CFG7_Msk              (0xFUL << USART_HWCFGR1_CFG7_Pos)       /*!< 0x0F000000 */
21671 #define USART_HWCFGR1_CFG7                  USART_HWCFGR1_CFG7_Msk                  /*!< CFG7[27:24] bits (USART hardware configuration 7) */
21672 #define USART_HWCFGR1_CFG8_Pos              (28U)
21673 #define USART_HWCFGR1_CFG8_Msk              (0xFUL << USART_HWCFGR1_CFG8_Pos)       /*!< 0xF0000000 */
21674 #define USART_HWCFGR1_CFG8                  USART_HWCFGR1_CFG8_Msk                  /*!< CFG8[31:28] bits (USART hardware configuration 8) */
21675 
21676 /*******************  Bit definition for USART_VERR register  *****************/
21677 #define USART_VERR_MINREV_Pos               (0U)
21678 #define USART_VERR_MINREV_Msk               (0xFUL << USART_VERR_MINREV_Pos)        /*!< 0x0000000F */
21679 #define USART_VERR_MINREV                   USART_VERR_MINREV_Msk                   /*!< MAJREV[3:0] bits (Minor revision) */
21680 #define USART_VERR_MAJREV_Pos               (4U)
21681 #define USART_VERR_MAJREV_Msk               (0xFUL << USART_VERR_MAJREV_Pos)        /*!< 0x000000F0 */
21682 #define USART_VERR_MAJREV                   USART_VERR_MAJREV_Msk                   /*!< MINREV[3:0] bits (Major revision) */
21683 
21684 /*******************  Bit definition for USART_IPIDR register  ****************/
21685 #define USART_IPIDR_ID_Pos                  (0U)
21686 #define USART_IPIDR_ID_Msk                  (0xFFFFFFFFUL << USART_IPIDR_ID_Pos)    /*!< 0xFFFFFFFF */
21687 #define USART_IPIDR_ID                      USART_IPIDR_ID_Msk                      /*!< ID[31:0] bits (Peripheral identifier) */
21688 
21689 /*******************  Bit definition for USART_SIDR register  ****************/
21690 #define USART_SIDR_ID_Pos                   (0U)
21691 #define USART_SIDR_ID_Msk                   (0xFFFFFFFFUL << USART_SIDR_ID_Pos)     /*!< 0xFFFFFFFF */
21692 #define USART_SIDR_ID                       USART_SIDR_ID_Msk                       /*!< SID[31:0] bits (Size identification) */
21693 
21694 
21695 /******************************************************************************/
21696 /*                                                                            */
21697 /*                      Inter-integrated Circuit Interface (I2C)              */
21698 /*                                                                            */
21699 /******************************************************************************/
21700 /*******************  Bit definition for I2C_CR1 register  *******************/
21701 #define I2C_CR1_PE_Pos                      (0U)
21702 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
21703 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
21704 #define I2C_CR1_TXIE_Pos                    (1U)
21705 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
21706 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
21707 #define I2C_CR1_RXIE_Pos                    (2U)
21708 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
21709 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
21710 #define I2C_CR1_ADDRIE_Pos                  (3U)
21711 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
21712 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
21713 #define I2C_CR1_NACKIE_Pos                  (4U)
21714 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
21715 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
21716 #define I2C_CR1_STOPIE_Pos                  (5U)
21717 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
21718 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
21719 #define I2C_CR1_TCIE_Pos                    (6U)
21720 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
21721 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
21722 #define I2C_CR1_ERRIE_Pos                   (7U)
21723 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
21724 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
21725 #define I2C_CR1_DNF_Pos                     (8U)
21726 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
21727 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
21728 #define I2C_CR1_ANFOFF_Pos                  (12U)
21729 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
21730 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
21731 #define I2C_CR1_SWRST_Pos                   (13U)
21732 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
21733 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
21734 #define I2C_CR1_TXDMAEN_Pos                 (14U)
21735 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
21736 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
21737 #define I2C_CR1_RXDMAEN_Pos                 (15U)
21738 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
21739 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
21740 #define I2C_CR1_SBC_Pos                     (16U)
21741 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
21742 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
21743 #define I2C_CR1_NOSTRETCH_Pos               (17U)
21744 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
21745 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
21746 #define I2C_CR1_WUPEN_Pos                   (18U)
21747 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
21748 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
21749 #define I2C_CR1_GCEN_Pos                    (19U)
21750 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
21751 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
21752 #define I2C_CR1_SMBHEN_Pos                  (20U)
21753 #define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
21754 #define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
21755 #define I2C_CR1_SMBDEN_Pos                  (21U)
21756 #define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
21757 #define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
21758 #define I2C_CR1_ALERTEN_Pos                 (22U)
21759 #define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
21760 #define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
21761 #define I2C_CR1_PECEN_Pos                   (23U)
21762 #define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
21763 #define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
21764 #define I2C_CR1_FMP_Pos                     (24U)
21765 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
21766 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
21767 #define I2C_CR1_ADDRACLR_Pos                (30U)
21768 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
21769 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
21770 #define I2C_CR1_STOPFACLR_Pos               (31U)
21771 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
21772 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
21773 
21774 /******************  Bit definition for I2C_CR2 register  ********************/
21775 #define I2C_CR2_SADD_Pos                    (0U)
21776 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
21777 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
21778 #define I2C_CR2_RD_WRN_Pos                  (10U)
21779 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
21780 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
21781 #define I2C_CR2_ADD10_Pos                   (11U)
21782 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
21783 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
21784 #define I2C_CR2_HEAD10R_Pos                 (12U)
21785 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
21786 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
21787 #define I2C_CR2_START_Pos                   (13U)
21788 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
21789 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
21790 #define I2C_CR2_STOP_Pos                    (14U)
21791 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
21792 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
21793 #define I2C_CR2_NACK_Pos                    (15U)
21794 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
21795 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
21796 #define I2C_CR2_NBYTES_Pos                  (16U)
21797 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
21798 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
21799 #define I2C_CR2_RELOAD_Pos                  (24U)
21800 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
21801 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
21802 #define I2C_CR2_AUTOEND_Pos                 (25U)
21803 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
21804 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
21805 #define I2C_CR2_PECBYTE_Pos                 (26U)
21806 #define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
21807 #define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
21808 
21809 /*******************  Bit definition for I2C_OAR1 register  ******************/
21810 #define I2C_OAR1_OA1_Pos                    (0U)
21811 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
21812 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
21813 #define I2C_OAR1_OA1MODE_Pos                (10U)
21814 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
21815 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
21816 #define I2C_OAR1_OA1EN_Pos                  (15U)
21817 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
21818 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
21819 
21820 /*******************  Bit definition for I2C_OAR2 register  ******************/
21821 #define I2C_OAR2_OA2_Pos                    (1U)
21822 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
21823 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
21824 #define I2C_OAR2_OA2MSK_Pos                 (8U)
21825 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
21826 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
21827 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
21828 #define I2C_OAR2_OA2MASK01_Pos              (8U)
21829 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
21830 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
21831 #define I2C_OAR2_OA2MASK02_Pos              (9U)
21832 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
21833 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
21834 #define I2C_OAR2_OA2MASK03_Pos              (8U)
21835 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
21836 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
21837 #define I2C_OAR2_OA2MASK04_Pos              (10U)
21838 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
21839 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
21840 #define I2C_OAR2_OA2MASK05_Pos              (8U)
21841 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
21842 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
21843 #define I2C_OAR2_OA2MASK06_Pos              (9U)
21844 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
21845 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
21846 #define I2C_OAR2_OA2MASK07_Pos              (8U)
21847 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
21848 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
21849 #define I2C_OAR2_OA2EN_Pos                  (15U)
21850 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
21851 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
21852 
21853 /*******************  Bit definition for I2C_TIMINGR register *******************/
21854 #define I2C_TIMINGR_SCLL_Pos                (0U)
21855 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
21856 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
21857 #define I2C_TIMINGR_SCLH_Pos                (8U)
21858 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
21859 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
21860 #define I2C_TIMINGR_SDADEL_Pos              (16U)
21861 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
21862 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
21863 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
21864 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
21865 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
21866 #define I2C_TIMINGR_PRESC_Pos               (28U)
21867 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
21868 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
21869 
21870 /******************* Bit definition for I2C_TIMEOUTR register *******************/
21871 #define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
21872 #define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
21873 #define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
21874 #define I2C_TIMEOUTR_TIDLE_Pos              (12U)
21875 #define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
21876 #define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
21877 #define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
21878 #define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
21879 #define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
21880 #define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
21881 #define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
21882 #define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
21883 #define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
21884 #define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
21885 #define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
21886 
21887 /******************  Bit definition for I2C_ISR register  *********************/
21888 #define I2C_ISR_TXE_Pos                     (0U)
21889 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
21890 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
21891 #define I2C_ISR_TXIS_Pos                    (1U)
21892 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
21893 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
21894 #define I2C_ISR_RXNE_Pos                    (2U)
21895 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
21896 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
21897 #define I2C_ISR_ADDR_Pos                    (3U)
21898 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
21899 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
21900 #define I2C_ISR_NACKF_Pos                   (4U)
21901 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
21902 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
21903 #define I2C_ISR_STOPF_Pos                   (5U)
21904 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
21905 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
21906 #define I2C_ISR_TC_Pos                      (6U)
21907 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
21908 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
21909 #define I2C_ISR_TCR_Pos                     (7U)
21910 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
21911 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
21912 #define I2C_ISR_BERR_Pos                    (8U)
21913 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
21914 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
21915 #define I2C_ISR_ARLO_Pos                    (9U)
21916 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
21917 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
21918 #define I2C_ISR_OVR_Pos                     (10U)
21919 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
21920 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
21921 #define I2C_ISR_PECERR_Pos                  (11U)
21922 #define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
21923 #define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
21924 #define I2C_ISR_TIMEOUT_Pos                 (12U)
21925 #define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
21926 #define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
21927 #define I2C_ISR_ALERT_Pos                   (13U)
21928 #define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
21929 #define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
21930 #define I2C_ISR_BUSY_Pos                    (15U)
21931 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
21932 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
21933 #define I2C_ISR_DIR_Pos                     (16U)
21934 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
21935 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
21936 #define I2C_ISR_ADDCODE_Pos                 (17U)
21937 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
21938 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
21939 
21940 /******************  Bit definition for I2C_ICR register  *********************/
21941 #define I2C_ICR_ADDRCF_Pos                  (3U)
21942 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
21943 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
21944 #define I2C_ICR_NACKCF_Pos                  (4U)
21945 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
21946 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
21947 #define I2C_ICR_STOPCF_Pos                  (5U)
21948 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
21949 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
21950 #define I2C_ICR_BERRCF_Pos                  (8U)
21951 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
21952 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
21953 #define I2C_ICR_ARLOCF_Pos                  (9U)
21954 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
21955 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
21956 #define I2C_ICR_OVRCF_Pos                   (10U)
21957 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
21958 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
21959 #define I2C_ICR_PECCF_Pos                   (11U)
21960 #define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
21961 #define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
21962 #define I2C_ICR_TIMOUTCF_Pos                (12U)
21963 #define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
21964 #define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
21965 #define I2C_ICR_ALERTCF_Pos                 (13U)
21966 #define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
21967 #define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
21968 
21969 /******************  Bit definition for I2C_PECR register  *********************/
21970 #define I2C_PECR_PEC_Pos                    (0U)
21971 #define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
21972 #define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
21973 
21974 /******************  Bit definition for I2C_RXDR register  *********************/
21975 #define I2C_RXDR_RXDATA_Pos                 (0U)
21976 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
21977 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
21978 
21979 /******************  Bit definition for I2C_TXDR register  *********************/
21980 #define I2C_TXDR_TXDATA_Pos                 (0U)
21981 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
21982 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
21983 
21984 
21985 /******************************************************************************/
21986 /*                                                                            */
21987 /*             Improved Inter-integrated Circuit Interface (I3C)              */
21988 /*                                                                            */
21989 /******************************************************************************/
21990 /*******************  Bit definition for I3C_CR register  *********************/
21991 #define I3C_CR_DCNT_Pos                     (0U)
21992 #define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
21993 #define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
21994 #define I3C_CR_RNW_Pos                      (16U)
21995 #define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
21996 #define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
21997 #define I3C_CR_CCC_Pos                      (16U)
21998 #define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
21999 #define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
22000 #define I3C_CR_ADD_Pos                      (17U)
22001 #define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
22002 #define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
22003 #define I3C_CR_MTYPE_Pos                    (27U)
22004 #define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
22005 #define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
22006 #define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
22007 #define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
22008 #define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
22009 #define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
22010 #define I3C_CR_MEND_Pos                     (31U)
22011 #define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
22012 #define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
22013 
22014 /*******************  Bit definition for I3C_CFGR register  *******************/
22015 #define I3C_CFGR_EN_Pos                     (0U)
22016 #define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
22017 #define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
22018 #define I3C_CFGR_CRINIT_Pos                 (1U)
22019 #define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
22020 #define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
22021 #define I3C_CFGR_NOARBH_Pos                 (2U)
22022 #define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
22023 #define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
22024 #define I3C_CFGR_RSTPTRN_Pos                (3U)
22025 #define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
22026 #define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
22027 #define I3C_CFGR_EXITPTRN_Pos               (4U)
22028 #define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
22029 #define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
22030 #define I3C_CFGR_HKSDAEN_Pos                (5U)
22031 #define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
22032 #define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
22033 #define I3C_CFGR_HJACK_Pos                  (7U)
22034 #define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
22035 #define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
22036 #define I3C_CFGR_RXDMAEN_Pos                (8U)
22037 #define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
22038 #define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
22039 #define I3C_CFGR_RXFLUSH_Pos                (9U)
22040 #define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
22041 #define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
22042 #define I3C_CFGR_RXTHRES_Pos                (10U)
22043 #define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
22044 #define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
22045 #define I3C_CFGR_TXDMAEN_Pos                (12U)
22046 #define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
22047 #define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
22048 #define I3C_CFGR_TXFLUSH_Pos                (13U)
22049 #define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
22050 #define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
22051 #define I3C_CFGR_TXTHRES_Pos                (14U)
22052 #define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
22053 #define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
22054 #define I3C_CFGR_SDMAEN_Pos                 (16U)
22055 #define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
22056 #define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
22057 #define I3C_CFGR_SFLUSH_Pos                 (17U)
22058 #define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
22059 #define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
22060 #define I3C_CFGR_SMODE_Pos                  (18U)
22061 #define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
22062 #define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
22063 #define I3C_CFGR_TMODE_Pos                  (19U)
22064 #define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
22065 #define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
22066 #define I3C_CFGR_CDMAEN_Pos                 (20U)
22067 #define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
22068 #define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
22069 #define I3C_CFGR_CFLUSH_Pos                 (21U)
22070 #define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
22071 #define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
22072 #define I3C_CFGR_TSFSET_Pos                 (30U)
22073 #define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
22074 #define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
22075 
22076 /*******************  Bit definition for I3C_RDR register  ********************/
22077 #define I3C_RDR_RDB0_Pos                    (0U)
22078 #define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
22079 #define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
22080 
22081 /******************  Bit definition for I3C_RDWR register  ********************/
22082 #define I3C_RDWR_RDBx_Pos                   (0U)
22083 #define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
22084 #define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
22085 #define I3C_RDWR_RDB0_Pos                   (0U)
22086 #define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
22087 #define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
22088 #define I3C_RDWR_RDB1_Pos                   (8U)
22089 #define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
22090 #define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
22091 #define I3C_RDWR_RDB2_Pos                   (16U)
22092 #define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
22093 #define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
22094 #define I3C_RDWR_RDB3_Pos                   (24U)
22095 #define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
22096 #define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
22097 
22098 /*******************  Bit definition for I3C_TDR register  ********************/
22099 #define I3C_TDR_TDB0_Pos                    (0U)
22100 #define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
22101 #define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
22102 
22103 /******************  Bit definition for I3C_TDWR register  ********************/
22104 #define I3C_TDWR_TDBx_Pos                   (0U)
22105 #define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
22106 #define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
22107 #define I3C_TDWR_TDB0_Pos                   (0U)
22108 #define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
22109 #define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
22110 #define I3C_TDWR_TDB1_Pos                   (8U)
22111 #define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
22112 #define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
22113 #define I3C_TDWR_TDB2_Pos                   (16U)
22114 #define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
22115 #define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
22116 #define I3C_TDWR_TDB3_Pos                   (24U)
22117 #define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
22118 #define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
22119 
22120 /*******************  Bit definition for I3C_IBIDR register  ******************/
22121 #define I3C_IBIDR_IBIDBx_Pos                (0U)
22122 #define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
22123 #define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
22124 #define I3C_IBIDR_IBIDB0_Pos                (0U)
22125 #define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
22126 #define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
22127 #define I3C_IBIDR_IBIDB1_Pos                (8U)
22128 #define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
22129 #define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
22130 #define I3C_IBIDR_IBIDB2_Pos                (16U)
22131 #define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
22132 #define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
22133 #define I3C_IBIDR_IBIDB3_Pos                (24U)
22134 #define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
22135 #define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
22136 
22137 /******************  Bit definition for I3C_TGTTDR register  ******************/
22138 #define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
22139 #define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
22140 #define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
22141 #define I3C_TGTTDR_PRELOAD_Pos              (16U)
22142 #define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
22143 #define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
22144 
22145 /*******************  Bit definition for I3C_SR register  *********************/
22146 #define I3C_SR_XDCNT_Pos                    (0U)
22147 #define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
22148 #define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
22149 #define I3C_SR_ABT_Pos                      (17U)
22150 #define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
22151 #define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
22152 #define I3C_SR_DIR_Pos                      (18U)
22153 #define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
22154 #define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
22155 #define I3C_SR_MID_Pos                      (24U)
22156 #define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
22157 #define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
22158 
22159 /*******************  Bit definition for I3C_SER register  ********************/
22160 #define I3C_SER_CODERR_Pos                  (0U)
22161 #define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
22162 #define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
22163 #define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
22164 #define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
22165 #define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
22166 #define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
22167 #define I3C_SER_PERR_Pos                    (4U)
22168 #define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
22169 #define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
22170 #define I3C_SER_STALL_Pos                   (5U)
22171 #define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
22172 #define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
22173 #define I3C_SER_DOVR_Pos                    (6U)
22174 #define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
22175 #define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
22176 #define I3C_SER_COVR_Pos                    (7U)
22177 #define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
22178 #define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
22179 #define I3C_SER_ANACK_Pos                   (8U)
22180 #define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
22181 #define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
22182 #define I3C_SER_DNACK_Pos                   (9U)
22183 #define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
22184 #define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
22185 #define I3C_SER_DERR_Pos                    (10U)
22186 #define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
22187 #define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
22188 
22189 /*******************  Bit definition for I3C_RMR register  ********************/
22190 #define I3C_RMR_IBIRDCNT_Pos                (0U)
22191 #define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
22192 #define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
22193 #define I3C_RMR_RCODE_Pos                   (8U)
22194 #define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
22195 #define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
22196 #define I3C_RMR_RADD_Pos                    (17U)
22197 #define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
22198 #define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
22199 
22200 /*******************  Bit definition for I3C_EVR register  ********************/
22201 #define I3C_EVR_CFEF_Pos                    (0U)
22202 #define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
22203 #define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
22204 #define I3C_EVR_TXFEF_Pos                   (1U)
22205 #define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
22206 #define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
22207 #define I3C_EVR_CFNFF_Pos                   (2U)
22208 #define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
22209 #define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
22210 #define I3C_EVR_SFNEF_Pos                   (3U)
22211 #define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
22212 #define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
22213 #define I3C_EVR_TXFNFF_Pos                  (4U)
22214 #define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
22215 #define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
22216 #define I3C_EVR_RXFNEF_Pos                  (5U)
22217 #define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
22218 #define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
22219 #define I3C_EVR_TXLASTF_Pos                 (6U)
22220 #define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
22221 #define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
22222 #define I3C_EVR_RXLASTF_Pos                 (7U)
22223 #define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
22224 #define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
22225 #define I3C_EVR_FCF_Pos                     (9U)
22226 #define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
22227 #define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
22228 #define I3C_EVR_RXTGTENDF_Pos               (10U)
22229 #define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
22230 #define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
22231 #define I3C_EVR_ERRF_Pos                    (11U)
22232 #define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
22233 #define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
22234 #define I3C_EVR_IBIF_Pos                    (15U)
22235 #define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
22236 #define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
22237 #define I3C_EVR_IBIENDF_Pos                 (16U)
22238 #define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
22239 #define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
22240 #define I3C_EVR_CRF_Pos                     (17U)
22241 #define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
22242 #define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
22243 #define I3C_EVR_CRUPDF_Pos                  (18U)
22244 #define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
22245 #define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
22246 #define I3C_EVR_HJF_Pos                     (19U)
22247 #define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
22248 #define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
22249 #define I3C_EVR_WKPF_Pos                    (21U)
22250 #define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
22251 #define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
22252 #define I3C_EVR_GETF_Pos                    (22U)
22253 #define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
22254 #define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
22255 #define I3C_EVR_STAF_Pos                    (23U)
22256 #define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
22257 #define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
22258 #define I3C_EVR_DAUPDF_Pos                  (24U)
22259 #define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
22260 #define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
22261 #define I3C_EVR_MWLUPDF_Pos                 (25U)
22262 #define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
22263 #define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
22264 #define I3C_EVR_MRLUPDF_Pos                 (26U)
22265 #define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
22266 #define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
22267 #define I3C_EVR_RSTF_Pos                    (27U)
22268 #define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
22269 #define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
22270 #define I3C_EVR_ASUPDF_Pos                  (28U)
22271 #define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
22272 #define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
22273 #define I3C_EVR_INTUPDF_Pos                 (29U)
22274 #define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
22275 #define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
22276 #define I3C_EVR_DEFF_Pos                    (30U)
22277 #define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
22278 #define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
22279 #define I3C_EVR_GRPF_Pos                    (31U)
22280 #define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
22281 #define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
22282 
22283 /*******************  Bit definition for I3C_IER register  ********************/
22284 #define I3C_IER_CFNFIE_Pos                  (2U)
22285 #define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
22286 #define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
22287 #define I3C_IER_SFNEIE_Pos                  (3U)
22288 #define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
22289 #define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
22290 #define I3C_IER_TXFNFIE_Pos                 (4U)
22291 #define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
22292 #define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
22293 #define I3C_IER_RXFNEIE_Pos                 (5U)
22294 #define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
22295 #define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
22296 #define I3C_IER_FCIE_Pos                    (9U)
22297 #define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
22298 #define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
22299 #define I3C_IER_RXTGTENDIE_Pos              (10U)
22300 #define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
22301 #define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
22302 #define I3C_IER_ERRIE_Pos                   (11U)
22303 #define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
22304 #define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
22305 #define I3C_IER_IBIIE_Pos                   (15U)
22306 #define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
22307 #define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
22308 #define I3C_IER_IBIENDIE_Pos                (16U)
22309 #define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
22310 #define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
22311 #define I3C_IER_CRIE_Pos                    (17U)
22312 #define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
22313 #define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
22314 #define I3C_IER_CRUPDIE_Pos                 (18U)
22315 #define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
22316 #define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
22317 #define I3C_IER_HJIE_Pos                    (19U)
22318 #define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
22319 #define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
22320 #define I3C_IER_WKPIE_Pos                   (21U)
22321 #define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
22322 #define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
22323 #define I3C_IER_GETIE_Pos                   (22U)
22324 #define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
22325 #define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
22326 #define I3C_IER_STAIE_Pos                   (23U)
22327 #define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
22328 #define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
22329 #define I3C_IER_DAUPDIE_Pos                 (24U)
22330 #define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
22331 #define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
22332 #define I3C_IER_MWLUPDIE_Pos                (25U)
22333 #define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
22334 #define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
22335 #define I3C_IER_MRLUPDIE_Pos                (26U)
22336 #define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
22337 #define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
22338 #define I3C_IER_RSTIE_Pos                   (27U)
22339 #define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
22340 #define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
22341 #define I3C_IER_ASUPDIE_Pos                 (28U)
22342 #define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
22343 #define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
22344 #define I3C_IER_INTUPDIE_Pos                (29U)
22345 #define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
22346 #define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
22347 #define I3C_IER_DEFIE_Pos                   (30U)
22348 #define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
22349 #define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
22350 #define I3C_IER_GRPIE_Pos                   (31U)
22351 #define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
22352 #define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
22353 
22354 /*******************  Bit definition for I3C_CEVR register  *******************/
22355 #define I3C_CEVR_CFCF_Pos                   (9U)
22356 #define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
22357 #define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
22358 #define I3C_CEVR_CRXTGTENDF_Pos             (10U)
22359 #define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
22360 #define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
22361 #define I3C_CEVR_CERRF_Pos                  (11U)
22362 #define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
22363 #define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
22364 #define I3C_CEVR_CIBIF_Pos                  (15U)
22365 #define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
22366 #define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
22367 #define I3C_CEVR_CIBIENDF_Pos               (16U)
22368 #define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
22369 #define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
22370 #define I3C_CEVR_CCRF_Pos                   (17U)
22371 #define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
22372 #define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
22373 #define I3C_CEVR_CCRUPDF_Pos                (18U)
22374 #define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
22375 #define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
22376 #define I3C_CEVR_CHJF_Pos                   (19U)
22377 #define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
22378 #define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
22379 #define I3C_CEVR_CWKPF_Pos                  (21U)
22380 #define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
22381 #define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
22382 #define I3C_CEVR_CGETF_Pos                  (22U)
22383 #define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
22384 #define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
22385 #define I3C_CEVR_CSTAF_Pos                  (23U)
22386 #define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
22387 #define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
22388 #define I3C_CEVR_CDAUPDF_Pos                (24U)
22389 #define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
22390 #define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
22391 #define I3C_CEVR_CMWLUPDF_Pos               (25U)
22392 #define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
22393 #define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
22394 #define I3C_CEVR_CMRLUPDF_Pos               (26U)
22395 #define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
22396 #define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
22397 #define I3C_CEVR_CRSTF_Pos                  (27U)
22398 #define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
22399 #define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
22400 #define I3C_CEVR_CASUPDF_Pos                (28U)
22401 #define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
22402 #define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
22403 #define I3C_CEVR_CINTUPDF_Pos               (29U)
22404 #define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
22405 #define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
22406 #define I3C_CEVR_CDEFF_Pos                  (30U)
22407 #define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
22408 #define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
22409 #define I3C_CEVR_CGRPF_Pos                  (31U)
22410 #define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
22411 #define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
22412 
22413 /******************  Bit definition for I3C_DEVR0 register  *******************/
22414 #define I3C_DEVR0_DAVAL_Pos                 (0U)
22415 #define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
22416 #define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
22417 #define I3C_DEVR0_DA_Pos                    (1U)
22418 #define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
22419 #define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
22420 #define I3C_DEVR0_IBIEN_Pos                 (16U)
22421 #define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
22422 #define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
22423 #define I3C_DEVR0_CREN_Pos                  (17U)
22424 #define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
22425 #define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
22426 #define I3C_DEVR0_HJEN_Pos                  (19U)
22427 #define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
22428 #define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
22429 #define I3C_DEVR0_AS_Pos                    (20U)
22430 #define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
22431 #define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
22432 #define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
22433 #define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
22434 #define I3C_DEVR0_RSTACT_Pos                (22U)
22435 #define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
22436 #define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
22437 #define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
22438 #define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
22439 #define I3C_DEVR0_RSTVAL_Pos                (24U)
22440 #define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
22441 #define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
22442 
22443 /******************  Bit definition for I3C_DEVRX register  *******************/
22444 #define I3C_DEVRX_DA_Pos                    (1U)
22445 #define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
22446 #define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
22447 #define I3C_DEVRX_IBIACK_Pos                (16U)
22448 #define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
22449 #define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
22450 #define I3C_DEVRX_CRACK_Pos                 (17U)
22451 #define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
22452 #define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
22453 #define I3C_DEVRX_IBIDEN_Pos                (18U)
22454 #define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
22455 #define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
22456 #define I3C_DEVRX_SUSP_Pos                  (19U)
22457 #define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
22458 #define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
22459 #define I3C_DEVRX_DIS_Pos                   (31U)
22460 #define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
22461 #define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
22462 
22463 /******************  Bit definition for I3C_MAXRLR register  ******************/
22464 #define I3C_MAXRLR_MRL_Pos                  (0U)
22465 #define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
22466 #define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
22467 #define I3C_MAXRLR_IBIP_Pos                 (16U)
22468 #define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
22469 #define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
22470 #define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
22471 #define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
22472 #define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
22473 
22474 /******************  Bit definition for I3C_MAXWLR register  ******************/
22475 #define I3C_MAXWLR_MWL_Pos                  (0U)
22476 #define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
22477 #define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
22478 
22479 /****************  Bit definition for I3C_TIMINGR0 register  ******************/
22480 #define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
22481 #define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
22482 #define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
22483 #define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
22484 #define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
22485 #define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
22486 #define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
22487 #define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
22488 #define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
22489 #define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
22490 #define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
22491 #define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
22492 
22493 /****************  Bit definition for I3C_TIMINGR1 register  ******************/
22494 #define I3C_TIMINGR1_AVAL_Pos               (0U)
22495 #define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
22496 #define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
22497 #define I3C_TIMINGR1_ASNCR_Pos              (8U)
22498 #define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
22499 #define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
22500 #define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
22501 #define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
22502 #define I3C_TIMINGR1_FREE_Pos               (16U)
22503 #define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
22504 #define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
22505 #define I3C_TIMINGR1_SDA_HD_Pos             (28U)
22506 #define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
22507 #define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
22508 
22509 /****************  Bit definition for I3C_TIMINGR2 register  ******************/
22510 #define I3C_TIMINGR2_STALLT_Pos             (0U)
22511 #define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x00000001 */
22512 #define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
22513 #define I3C_TIMINGR2_STALLD_Pos             (1U)
22514 #define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x00000002 */
22515 #define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
22516 #define I3C_TIMINGR2_STALLC_Pos             (2U)
22517 #define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x00000004 */
22518 #define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
22519 #define I3C_TIMINGR2_STALLA_Pos             (3U)
22520 #define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x00000008 */
22521 #define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
22522 #define I3C_TIMINGR2_STALL_Pos              (8U)
22523 #define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x0000FF00 */
22524 #define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
22525 
22526 /*******************  Bit definition for I3C_BCR register  ********************/
22527 #define I3C_BCR_BCR_Pos                     (0U)
22528 #define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
22529 #define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
22530 #define I3C_BCR_BCR0_Pos                    (0U)
22531 #define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
22532 #define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
22533 #define I3C_BCR_BCR1_Pos                    (1U)
22534 #define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
22535 #define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
22536 #define I3C_BCR_BCR2_Pos                    (2U)
22537 #define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
22538 #define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
22539 #define I3C_BCR_BCR6_Pos                    (6U)
22540 #define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
22541 #define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
22542 
22543 /*******************  Bit definition for I3C_DCR register  ********************/
22544 #define I3C_DCR_DCR_Pos                     (0U)
22545 #define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x000000FF */
22546 #define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
22547 
22548 /*****************  Bit definition for I3C_GETCAPR register  ******************/
22549 #define I3C_GETCAPR_CAPPEND_Pos             (14U)
22550 #define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
22551 #define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
22552 
22553 /*****************  Bit definition for I3C_CRCAPR register  *******************/
22554 #define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
22555 #define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
22556 #define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
22557 #define I3C_CRCAPR_CAPGRP_Pos               (9U)
22558 #define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
22559 #define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
22560 
22561 /****************  Bit definition for I3C_GETMXDSR register  ******************/
22562 #define I3C_GETMXDSR_HOFFAS_Pos             (0U)
22563 #define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
22564 #define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
22565 #define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
22566 #define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
22567 #define I3C_GETMXDSR_FMT_Pos                (8U)
22568 #define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
22569 #define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
22570 #define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
22571 #define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
22572 #define I3C_GETMXDSR_RDTURN_Pos             (16U)
22573 #define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
22574 #define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
22575 #define I3C_GETMXDSR_TSCO_Pos               (24U)
22576 #define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
22577 #define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
22578 
22579 /******************  Bit definition for I3C_EPIDR register  *******************/
22580 #define I3C_EPIDR_MIPIID_Pos                (12U)
22581 #define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
22582 #define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
22583 #define I3C_EPIDR_IDTSEL_Pos                (16U)
22584 #define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
22585 #define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
22586 #define I3C_EPIDR_MIPIMID_Pos               (17U)
22587 #define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
22588 #define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
22589 
22590 /******************************************************************************/
22591 /*                                                                            */
22592 /*                           Independent WATCHDOG                             */
22593 /*                                                                            */
22594 /******************************************************************************/
22595 /*******************  Bit definition for IWDG_KR register  ********************/
22596 #define IWDG_KR_KEY_Pos                     (0U)
22597 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
22598 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */
22599 
22600 /*******************  Bit definition for IWDG_PR register  ********************/
22601 #define IWDG_PR_PR_Pos                      (0U)
22602 #define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
22603 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
22604 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
22605 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
22606 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
22607 #define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */
22608 
22609 /*******************  Bit definition for IWDG_RLR register  *******************/
22610 #define IWDG_RLR_RL_Pos                     (0U)
22611 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
22612 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */
22613 
22614 /*******************  Bit definition for IWDG_SR register  ********************/
22615 #define IWDG_SR_PVU_Pos                     (0U)
22616 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
22617 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
22618 #define IWDG_SR_RVU_Pos                     (1U)
22619 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
22620 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
22621 #define IWDG_SR_WVU_Pos                     (2U)
22622 #define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
22623 #define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
22624 #define IWDG_SR_EWU_Pos                     (3U)
22625 #define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
22626 #define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
22627 #define IWDG_SR_ONF_Pos                     (8U)
22628 #define IWDG_SR_ONF_Msk                     (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x00000100 */
22629 #define IWDG_SR_ONF                         IWDG_SR_ONF_Msk                         /*!< Watchdog Enable status bit */
22630 #define IWDG_SR_EWIF_Pos                    (14U)
22631 #define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
22632 #define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */
22633 
22634 /******************  Bit definition for IWDG_WINR register  *******************/
22635 #define IWDG_WINR_WIN_Pos                   (0U)
22636 #define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
22637 #define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */
22638 
22639 /******************  Bit definition for IWDG_EWCR register  *******************/
22640 #define IWDG_EWCR_EWIT_Pos                  (0U)
22641 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
22642 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
22643 #define IWDG_EWCR_EWIC_Pos                  (14U)
22644 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00000FFF */
22645 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
22646 #define IWDG_EWCR_EWIE_Pos                  (15U)
22647 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
22648 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
22649 
22650 
22651 /******************************************************************************/
22652 /*                                                                            */
22653 /*                   Serial Peripheral Interface (SPI/I2S)                    */
22654 /*                                                                            */
22655 /******************************************************************************/
22656 /*******************  Bit definition for SPI_CR1 register  ********************/
22657 #define SPI_CR1_SPE_Pos                     (0U)
22658 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
22659 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
22660 #define SPI_CR1_MASRX_Pos                   (8U)
22661 #define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
22662 #define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
22663 #define SPI_CR1_CSTART_Pos                  (9U)
22664 #define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
22665 #define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
22666 #define SPI_CR1_CSUSP_Pos                   (10U)
22667 #define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
22668 #define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
22669 #define SPI_CR1_HDDIR_Pos                   (11U)
22670 #define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
22671 #define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
22672 #define SPI_CR1_SSI_Pos                     (12U)
22673 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
22674 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
22675 #define SPI_CR1_CRC33_17_Pos                (13U)
22676 #define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
22677 #define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
22678 #define SPI_CR1_RCRCINI_Pos                 (14U)
22679 #define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
22680 #define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
22681 #define SPI_CR1_TCRCINI_Pos                 (15U)
22682 #define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
22683 #define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
22684 #define SPI_CR1_IOLOCK_Pos                  (16U)
22685 #define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
22686 #define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
22687 
22688 /*******************  Bit definition for SPI_CR2 register  ********************/
22689 #define SPI_CR2_TSIZE_Pos                   (0U)
22690 #define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
22691 #define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
22692 
22693 /*******************  Bit definition for SPI_CFG1 register  ********************/
22694 #define SPI_CFG1_DSIZE_Pos                  (0U)
22695 #define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
22696 #define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
22697 #define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
22698 #define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
22699 #define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
22700 #define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
22701 #define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
22702 #define SPI_CFG1_FTHLV_Pos                  (5U)
22703 #define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
22704 #define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
22705 #define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
22706 #define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
22707 #define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
22708 #define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
22709 #define SPI_CFG1_UDRCFG_Pos                 (9U)
22710 #define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
22711 #define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
22712 #define SPI_CFG1_RXDMAEN_Pos                (14U)
22713 #define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
22714 #define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
22715 #define SPI_CFG1_TXDMAEN_Pos                (15U)
22716 #define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
22717 #define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
22718 #define SPI_CFG1_CRCSIZE_Pos                (16U)
22719 #define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
22720 #define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
22721 #define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
22722 #define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
22723 #define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
22724 #define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
22725 #define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
22726 #define SPI_CFG1_CRCEN_Pos                  (22U)
22727 #define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
22728 #define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
22729 #define SPI_CFG1_MBR_Pos                    (28U)
22730 #define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
22731 #define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
22732 #define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
22733 #define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
22734 #define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
22735 #define SPI_CFG1_BPASS_Pos                  (31U)
22736 #define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
22737 #define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
22738 
22739 /*******************  Bit definition for SPI_CFG2 register  ********************/
22740 #define SPI_CFG2_MSSI_Pos                   (0U)
22741 #define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
22742 #define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
22743 #define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
22744 #define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
22745 #define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
22746 #define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
22747 #define SPI_CFG2_MIDI_Pos                   (4U)
22748 #define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
22749 #define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
22750 #define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
22751 #define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
22752 #define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
22753 #define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
22754 #define SPI_CFG2_RDIOM_Pos                  (13U)
22755 #define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
22756 #define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
22757 #define SPI_CFG2_RDIOP_Pos                  (14U)
22758 #define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
22759 #define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
22760 #define SPI_CFG2_IOSWP_Pos                  (15U)
22761 #define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
22762 #define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
22763 #define SPI_CFG2_COMM_Pos                   (17U)
22764 #define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
22765 #define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
22766 #define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
22767 #define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
22768 #define SPI_CFG2_SP_Pos                     (19U)
22769 #define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
22770 #define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
22771 #define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
22772 #define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
22773 #define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
22774 #define SPI_CFG2_MASTER_Pos                 (22U)
22775 #define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
22776 #define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
22777 #define SPI_CFG2_LSBFRST_Pos                (23U)
22778 #define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
22779 #define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
22780 #define SPI_CFG2_CPHA_Pos                   (24U)
22781 #define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
22782 #define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
22783 #define SPI_CFG2_CPOL_Pos                   (25U)
22784 #define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
22785 #define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
22786 #define SPI_CFG2_SSM_Pos                    (26U)
22787 #define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
22788 #define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
22789 #define SPI_CFG2_SSIOP_Pos                  (28U)
22790 #define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
22791 #define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
22792 #define SPI_CFG2_SSOE_Pos                   (29U)
22793 #define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
22794 #define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
22795 #define SPI_CFG2_SSOM_Pos                   (30U)
22796 #define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
22797 #define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
22798 #define SPI_CFG2_AFCNTR_Pos                 (31U)
22799 #define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
22800 #define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
22801 
22802 /*******************  Bit definition for SPI_IER register  ********************/
22803 #define SPI_IER_RXPIE_Pos                   (0U)
22804 #define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
22805 #define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
22806 #define SPI_IER_TXPIE_Pos                   (1U)
22807 #define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
22808 #define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
22809 #define SPI_IER_DXPIE_Pos                   (2U)
22810 #define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
22811 #define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
22812 #define SPI_IER_EOTIE_Pos                   (3U)
22813 #define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
22814 #define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
22815 #define SPI_IER_TXTFIE_Pos                  (4U)
22816 #define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
22817 #define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
22818 #define SPI_IER_UDRIE_Pos                   (5U)
22819 #define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
22820 #define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
22821 #define SPI_IER_OVRIE_Pos                   (6U)
22822 #define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
22823 #define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
22824 #define SPI_IER_CRCEIE_Pos                  (7U)
22825 #define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
22826 #define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
22827 #define SPI_IER_TIFREIE_Pos                 (8U)
22828 #define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
22829 #define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
22830 #define SPI_IER_MODFIE_Pos                  (9U)
22831 #define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
22832 #define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
22833 
22834 /*******************  Bit definition for SPI_SR register  ********************/
22835 #define SPI_SR_RXP_Pos                      (0U)
22836 #define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
22837 #define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
22838 #define SPI_SR_TXP_Pos                      (1U)
22839 #define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
22840 #define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
22841 #define SPI_SR_DXP_Pos                      (2U)
22842 #define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
22843 #define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
22844 #define SPI_SR_EOT_Pos                      (3U)
22845 #define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
22846 #define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
22847 #define SPI_SR_TXTF_Pos                     (4U)
22848 #define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
22849 #define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
22850 #define SPI_SR_UDR_Pos                      (5U)
22851 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
22852 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
22853 #define SPI_SR_OVR_Pos                      (6U)
22854 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
22855 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
22856 #define SPI_SR_CRCE_Pos                     (7U)
22857 #define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
22858 #define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
22859 #define SPI_SR_TIFRE_Pos                    (8U)
22860 #define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
22861 #define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
22862 #define SPI_SR_MODF_Pos                     (9U)
22863 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
22864 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
22865 #define SPI_SR_SUSP_Pos                     (11U)
22866 #define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
22867 #define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
22868 #define SPI_SR_TXC_Pos                      (12U)
22869 #define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
22870 #define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
22871 #define SPI_SR_RXPLVL_Pos                   (13U)
22872 #define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
22873 #define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
22874 #define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
22875 #define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
22876 #define SPI_SR_RXWNE_Pos                    (15U)
22877 #define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
22878 #define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
22879 #define SPI_SR_CTSIZE_Pos                   (16U)
22880 #define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
22881 #define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
22882 
22883 /*******************  Bit definition for SPI_IFCR register  ********************/
22884 #define SPI_IFCR_EOTC_Pos                   (3U)
22885 #define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
22886 #define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
22887 #define SPI_IFCR_TXTFC_Pos                  (4U)
22888 #define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
22889 #define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
22890 #define SPI_IFCR_UDRC_Pos                   (5U)
22891 #define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
22892 #define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
22893 #define SPI_IFCR_OVRC_Pos                   (6U)
22894 #define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
22895 #define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
22896 #define SPI_IFCR_CRCEC_Pos                  (7U)
22897 #define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
22898 #define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
22899 #define SPI_IFCR_TIFREC_Pos                 (8U)
22900 #define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
22901 #define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
22902 #define SPI_IFCR_MODFC_Pos                  (9U)
22903 #define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
22904 #define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
22905 #define SPI_IFCR_SUSPC_Pos                  (11U)
22906 #define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
22907 #define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
22908 
22909 /*******************  Bit definition for SPI_TXDR register  ********************/
22910 #define SPI_TXDR_TXDR_Pos                   (0U)
22911 #define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
22912 #define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /*!<Transmit Data Register */
22913 
22914 /*******************  Bit definition for SPI_RXDR register  ********************/
22915 #define SPI_RXDR_RXDR_Pos                   (0U)
22916 #define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
22917 #define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /*!<Receive Data Register */
22918 
22919 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
22920 #define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
22921 #define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
22922 #define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                   /*!<CRC Polynomial register */
22923 
22924 /*******************  Bit definition for SPI_TXCRC register  ********************/
22925 #define SPI_TXCRC_TXCRC_Pos                 (0U)
22926 #define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
22927 #define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /*!<CRCRegister for transmitter */
22928 
22929 /*******************  Bit definition for SPI_RXCRC register  ********************/
22930 #define SPI_RXCRC_RXCRC_Pos                 (0U)
22931 #define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
22932 #define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /*!<CRCRegister for receiver */
22933 
22934 /*******************  Bit definition for SPI_UDRDR register  ********************/
22935 #define SPI_UDRDR_UDRDR_Pos                 (0U)
22936 #define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
22937 #define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /*!<Data at slave underrun condition */
22938 
22939 /******************  Bit definition for SPI_I2SCFGR register  *****************/
22940 #define SPI_I2SCFGR_I2SMOD_Pos      (0U)
22941 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
22942 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
22943 #define SPI_I2SCFGR_I2SCFG_Pos      (1U)
22944 #define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
22945 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
22946 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
22947 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
22948 #define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
22949 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
22950 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
22951 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
22952 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
22953 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
22954 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
22955 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
22956 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
22957 #define SPI_I2SCFGR_DATLEN_Pos      (8U)
22958 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
22959 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
22960 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
22961 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
22962 #define SPI_I2SCFGR_CHLEN_Pos       (10U)
22963 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
22964 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
22965 #define SPI_I2SCFGR_CKPOL_Pos       (11U)
22966 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
22967 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
22968 #define SPI_I2SCFGR_FIXCH_Pos       (12U)
22969 #define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
22970 #define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
22971 #define SPI_I2SCFGR_WSINV_Pos       (13U)
22972 #define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
22973 #define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
22974 #define SPI_I2SCFGR_DATFMT_Pos      (14U)
22975 #define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
22976 #define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
22977 #define SPI_I2SCFGR_I2SDIV_Pos      (16U)
22978 #define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
22979 #define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
22980 #define SPI_I2SCFGR_ODD_Pos         (24U)
22981 #define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
22982 #define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
22983 #define SPI_I2SCFGR_MCKOE_Pos       (25U)
22984 #define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
22985 #define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
22986 
22987 /******************************************************************************/
22988 /*                                                                            */
22989 /*                                 VREFBUF                                    */
22990 /*                                                                            */
22991 /******************************************************************************/
22992 /*******************  Bit definition for VREFBUF_CSR register  ****************/
22993 #define VREFBUF_CSR_ENVR_Pos    (0U)
22994 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
22995 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
22996 #define VREFBUF_CSR_HIZ_Pos     (1U)
22997 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
22998 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
22999 #define VREFBUF_CSR_VRR_Pos     (3U)
23000 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
23001 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
23002 #define VREFBUF_CSR_VRS_Pos     (4U)
23003 #define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
23004 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
23005 #define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
23006 #define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
23007 #define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
23008 
23009 /*******************  Bit definition for VREFBUF_CCR register  ******************/
23010 #define VREFBUF_CCR_TRIM_Pos                (0U)
23011 #define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
23012 #define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
23013 
23014 
23015 /******************************************************************************/
23016 /*                                                                            */
23017 /*                            Window WATCHDOG                                 */
23018 /*                                                                            */
23019 /******************************************************************************/
23020 /*******************  Bit definition for WWDG_CR register  ********************/
23021 #define WWDG_CR_T_Pos                       (0U)
23022 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
23023 #define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
23024 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
23025 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
23026 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
23027 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
23028 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
23029 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
23030 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
23031 #define WWDG_CR_WDGA_Pos                    (7U)
23032 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
23033 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
23034 
23035 /*******************  Bit definition for WWDG_CFR register  *******************/
23036 #define WWDG_CFR_W_Pos                      (0U)
23037 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
23038 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
23039 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
23040 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
23041 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
23042 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
23043 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
23044 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
23045 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
23046 #define WWDG_CFR_EWI_Pos                    (9U)
23047 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
23048 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
23049 #define WWDG_CFR_WDGTB_Pos                  (11U)
23050 #define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
23051 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
23052 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
23053 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
23054 #define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
23055 
23056 /*******************  Bit definition for WWDG_SR register  ********************/
23057 #define WWDG_SR_EWIF_Pos                    (0U)
23058 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
23059 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
23060 
23061 
23062 /******************************************************************************/
23063 /*                                                                            */
23064 /*                         USB Dual Role Device FS Endpoint registers         */
23065 /*                                                                            */
23066 /******************************************************************************/
23067 
23068 /******************  Bits definition for USB_DRD_CNTR register  *******************/
23069 #define USB_CNTR_HOST_Pos               (31U)
23070 #define USB_CNTR_HOST_Msk               (0x1UL << USB_CNTR_HOST_Pos)    /*!< 0x80000000 */
23071 #define USB_CNTR_HOST                   USB_CNTR_HOST_Msk               /*!< Host Mode  */
23072 #define USB_CNTR_THR512M_Pos            (16U)
23073 #define USB_CNTR_THR512M_Msk            (0x1UL << USB_CNTR_THR512M_Pos)  /*!< 0x00010000 */
23074 #define USB_CNTR_THR512M                USB_CNTR_THR512M_Msk             /*!< 512byte Threshold interrupt mask */
23075 #define USB_CNTR_CTRM_Pos               (15U)
23076 #define USB_CNTR_CTRM_Msk               (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
23077 #define USB_CNTR_CTRM                   USB_CNTR_CTRM_Msk               /*!< Correct Transfer Mask */
23078 #define USB_CNTR_PMAOVRM_Pos            (14U)
23079 #define USB_CNTR_PMAOVRM_Msk            (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
23080 #define USB_CNTR_PMAOVRM                USB_CNTR_PMAOVRM_Msk            /*!< DMA OVeR/underrun Mask */
23081 #define USB_CNTR_ERRM_Pos               (13U)
23082 #define USB_CNTR_ERRM_Msk               (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
23083 #define USB_CNTR_ERRM                   USB_CNTR_ERRM_Msk               /*!< ERRor Mask */
23084 #define USB_CNTR_WKUPM_Pos              (12U)
23085 #define USB_CNTR_WKUPM_Msk              (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
23086 #define USB_CNTR_WKUPM                  USB_CNTR_WKUPM_Msk              /*!< WaKe UP Mask */
23087 #define USB_CNTR_SUSPM_Pos              (11U)
23088 #define USB_CNTR_SUSPM_Msk              (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
23089 #define USB_CNTR_SUSPM                  USB_CNTR_SUSPM_Msk              /*!< SUSPend Mask */
23090 #define USB_CNTR_RESETM_Pos             (10U)
23091 #define USB_CNTR_RESETM_Msk             (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
23092 #define USB_CNTR_RESETM                 USB_CNTR_RESETM_Msk             /*!< RESET Mask */
23093 #define USB_CNTR_DCON                   USB_CNTR_RESETM_Msk             /*!< Disconnection Connection Mask */
23094 #define USB_CNTR_SOFM_Pos               (9U)
23095 #define USB_CNTR_SOFM_Msk               (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
23096 #define USB_CNTR_SOFM                   USB_CNTR_SOFM_Msk               /*!< Start Of Frame Mask */
23097 #define USB_CNTR_ESOFM_Pos              (8U)
23098 #define USB_CNTR_ESOFM_Msk              (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
23099 #define USB_CNTR_ESOFM                  USB_CNTR_ESOFM_Msk              /*!< Expected Start Of Frame Mask */
23100 #define USB_CNTR_L1REQM_Pos             (7U)
23101 #define USB_CNTR_L1REQM_Msk             (0x1UL << USB_CNTR_L1REQM_Pos)  /*!< 0x00000080 */
23102 #define USB_CNTR_L1REQM                 USB_CNTR_L1REQM_Msk             /*!< LPM L1 state request interrupt Mask */
23103 #define USB_CNTR_L1XACT_Pos             (6U)
23104 #define USB_CNTR_L1XACT_Msk             (0x1UL << USB_CNTR_L1XACT_Pos)  /*!< 0x00000040 */
23105 #define USB_CNTR_L1XACT                 USB_CNTR_L1XACT_Msk             /*!< Host LPM L1 transaction request Mask */
23106 #define USB_CNTR_L1RES_Pos              (5U)
23107 #define USB_CNTR_L1RES_Msk              (0x1UL << USB_CNTR_L1RES_Pos)   /*!< 0x00000020 */
23108 #define USB_CNTR_L1RES                  USB_CNTR_L1RES_Msk              /*!< LPM L1 Resume request/ Remote Wakeup Mask */
23109 #define USB_CNTR_L2RES_Pos              (4U)
23110 #define USB_CNTR_L2RES_Msk              (0x1UL << USB_CNTR_L2RES_Pos)   /*!< 0x00000010 */
23111 #define USB_CNTR_L2RES                  USB_CNTR_L2RES_Msk              /*!< L2 Remote Wakeup / Resume driver Mask */
23112 #define USB_CNTR_SUSPEN_Pos             (3U)
23113 #define USB_CNTR_SUSPEN_Msk             (0x1UL << USB_CNTR_SUSPEN_Pos)  /*!< 0x00000008 */
23114 #define USB_CNTR_SUSPEN                 USB_CNTR_SUSPEN_Msk             /*!< Suspend state enable Mask */
23115 #define USB_CNTR_SUSPRDY_Pos            (2U)
23116 #define USB_CNTR_SUSPRDY_Msk            (0x1UL << USB_CNTR_SUSPRDY_Pos) /*!< 0x00000004 */
23117 #define USB_CNTR_SUSPRDY                USB_CNTR_SUSPRDY_Msk            /*!< Suspend state effective Mask */
23118 #define USB_CNTR_PDWN_Pos               (1U)
23119 #define USB_CNTR_PDWN_Msk               (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
23120 #define USB_CNTR_PDWN                   USB_CNTR_PDWN_Msk               /*!< Power DoWN Mask */
23121 #define USB_CNTR_USBRST_Pos             (0U)
23122 #define USB_CNTR_USBRST_Msk             (0x1UL << USB_CNTR_USBRST_Pos)  /*!< 0x00000001 */
23123 #define USB_CNTR_USBRST                 USB_CNTR_USBRST_Msk             /*!< USB Reset Mask */
23124 
23125 /******************  Bits definition for USB_DRD_ISTR register  *******************/
23126 #define USB_ISTR_IDN_Pos                (0U)
23127 #define USB_ISTR_IDN_Msk                (0xFUL << USB_ISTR_IDN_Pos)     /*!< 0x0000000F */
23128 #define USB_ISTR_IDN                    USB_ISTR_IDN_Msk                /*!< EndPoint IDentifier (read-only bit) Mask */
23129 #define USB_ISTR_DIR_Pos                (4U)
23130 #define USB_ISTR_DIR_Msk                (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
23131 #define USB_ISTR_DIR                    USB_ISTR_DIR_Msk                /*!< DIRection of transaction (read-only bit) Mask */
23132 #define USB_ISTR_L1REQ_Pos              (7U)
23133 #define USB_ISTR_L1REQ_Msk              (0x1UL << USB_ISTR_L1REQ_Pos)   /*!< 0x00000080 */
23134 #define USB_ISTR_L1REQ                  USB_ISTR_L1REQ_Msk              /*!< LPM L1 state request Mask */
23135 #define USB_ISTR_ESOF_Pos               (8U)
23136 #define USB_ISTR_ESOF_Msk               (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
23137 #define USB_ISTR_ESOF                   USB_ISTR_ESOF_Msk               /*!< Expected Start Of Frame (clear-only bit) Mask */
23138 #define USB_ISTR_SOF_Pos                (9U)
23139 #define USB_ISTR_SOF_Msk                (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
23140 #define USB_ISTR_SOF                    USB_ISTR_SOF_Msk                /*!< Start Of Frame (clear-only bit) Mask */
23141 #define USB_ISTR_RESET_Pos              (10U)
23142 #define USB_ISTR_RESET_Msk              (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
23143 #define USB_ISTR_RESET                  USB_ISTR_RESET_Msk              /*!< RESET Mask */
23144 #define USB_ISTR_DCON_Pos               (10U)
23145 #define USB_ISTR_DCON_Msk               (0x1UL << USB_ISTR_DCON_Pos)    /*!< 0x00000400 */
23146 #define USB_ISTR_DCON                   USB_ISTR_DCON_Msk               /*!< HOST MODE-Device Connection or disconnection Mask */
23147 #define USB_ISTR_SUSP_Pos               (11U)
23148 #define USB_ISTR_SUSP_Msk               (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
23149 #define USB_ISTR_SUSP                   USB_ISTR_SUSP_Msk               /*!< SUSPend (clear-only bit) Mask */
23150 #define USB_ISTR_WKUP_Pos               (12U)
23151 #define USB_ISTR_WKUP_Msk               (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
23152 #define USB_ISTR_WKUP                   USB_ISTR_WKUP_Msk               /*!< WaKe UP (clear-only bit) Mask */
23153 #define USB_ISTR_ERR_Pos                (13U)
23154 #define USB_ISTR_ERR_Msk                (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
23155 #define USB_ISTR_ERR                    USB_ISTR_ERR_Msk                /*!< ERRor (clear-only bit) Mask */
23156 #define USB_ISTR_PMAOVR_Pos             (14U)
23157 #define USB_ISTR_PMAOVR_Msk             (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
23158 #define USB_ISTR_PMAOVR                 USB_ISTR_PMAOVR_Msk             /*!< PMA OVeR/underrun (clear-only bit) Mask */
23159 #define USB_ISTR_CTR_Pos                (15U)
23160 #define USB_ISTR_CTR_Msk                (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
23161 #define USB_ISTR_CTR                    USB_ISTR_CTR_Msk                /*!< Correct TRansfer (clear-only bit) Mask */
23162 #define USB_ISTR_THR512_Pos             (16U)
23163 #define USB_ISTR_THR512_Msk             (0x1UL << USB_ISTR_THR512_Pos)  /*!< 0x00010000 */
23164 #define USB_ISTR_THR512                 USB_ISTR_THR512_Msk             /*!< 512byte threshold interrupt (used with isochrnous single buffer ) */
23165 #define USB_ISTR_DCON_STAT_Pos          (29U)
23166 #define USB_ISTR_DCON_STAT_Msk          (0x1UL << USB_ISTR_DCON_STAT_Pos)/*!< 0x20000000 */
23167 #define USB_ISTR_DCON_STAT              USB_ISTR_DCON_STAT_Msk           /*!< Device Connection status (connected/Disconnected) don't cause an interrupt */
23168 #define USB_ISTR_LS_DCONN_Pos           (30U)
23169 #define USB_ISTR_LS_DCONN_Msk           (0x1UL << USB_ISTR_LS_DCONN_Pos)/*!< 0x40000000 */
23170 #define USB_ISTR_LS_DCONN               USB_ISTR_LS_DCONN_Msk           /*!< LS_DCONN Mask */
23171 
23172 /******************  Bits definition for USB_DRD_FNR register  ********************/
23173 #define USB_FNR_FN_Pos                  (0U)
23174 #define USB_FNR_FN_Msk                  (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
23175 #define USB_FNR_FN                      USB_FNR_FN_Msk                  /*!< Frame Number Mask */
23176 #define USB_FNR_LSOF_Pos                (11U)
23177 #define USB_FNR_LSOF_Msk                (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
23178 #define USB_FNR_LSOF                    USB_FNR_LSOF_Msk                /*!< Lost SOF  Mask */
23179 #define USB_FNR_LCK_Pos                 (13U)
23180 #define USB_FNR_LCK_Msk                 (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
23181 #define USB_FNR_LCK                     USB_FNR_LCK_Msk                 /*!< LoCKed Mask */
23182 #define USB_FNR_RXDM_Pos                (14U)
23183 #define USB_FNR_RXDM_Msk                (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
23184 #define USB_FNR_RXDM                    USB_FNR_RXDM_Msk                /*!< status of D- data line Mask */
23185 #define USB_FNR_RXDP_Pos                (15U)
23186 #define USB_FNR_RXDP_Msk                (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
23187 #define USB_FNR_RXDP                    USB_FNR_RXDP_Msk                /*!< status of D+ data line Mask */
23188 
23189 /******************  Bits definition for USB_DRD_DADDR register    ****************/
23190 #define USB_DADDR_ADD_Pos               (0U)
23191 #define USB_DADDR_ADD_Msk               (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
23192 #define USB_DADDR_ADD                   USB_DADDR_ADD_Msk               /*!<  ADD[6:0] bits (Device Address)Mask */
23193 #define USB_DADDR_ADD0_Pos              (0U)
23194 #define USB_DADDR_ADD0_Msk              (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
23195 #define USB_DADDR_ADD0                  USB_DADDR_ADD0_Msk              /*!< Bit 0 Mask */
23196 #define USB_DADDR_ADD1_Pos              (1U)
23197 #define USB_DADDR_ADD1_Msk              (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
23198 #define USB_DADDR_ADD1                  USB_DADDR_ADD1_Msk              /*!< Bit 1 Mask */
23199 #define USB_DADDR_ADD2_Pos              (2U)
23200 #define USB_DADDR_ADD2_Msk              (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
23201 #define USB_DADDR_ADD2                  USB_DADDR_ADD2_Msk              /*!< Bit 2 Mask */
23202 #define USB_DADDR_ADD3_Pos              (3U)
23203 #define USB_DADDR_ADD3_Msk              (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
23204 #define USB_DADDR_ADD3                  USB_DADDR_ADD3_Msk              /*!< Bit 3 Mask */
23205 #define USB_DADDR_ADD4_Pos              (4U)
23206 #define USB_DADDR_ADD4_Msk              (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
23207 #define USB_DADDR_ADD4                  USB_DADDR_ADD4_Msk              /*!< Bit 4 Mask */
23208 #define USB_DADDR_ADD5_Pos              (5U)
23209 #define USB_DADDR_ADD5_Msk              (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
23210 #define USB_DADDR_ADD5                  USB_DADDR_ADD5_Msk              /*!< Bit 5 Mask */
23211 #define USB_DADDR_ADD6_Pos              (6U)
23212 #define USB_DADDR_ADD6_Msk              (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
23213 #define USB_DADDR_ADD6                  USB_DADDR_ADD6_Msk              /*!< Bit 6 Mask */
23214 #define USB_DADDR_EF_Pos                (7U)
23215 #define USB_DADDR_EF_Msk                (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
23216 #define USB_DADDR_EF                    USB_DADDR_EF_Msk                /*!< Enable Function Mask */
23217 
23218 /******************  Bit definition for USB_DRD_BTABLE register  ******************/
23219 #define USB_BTABLE_BTABLE_Pos          (3U)
23220 #define USB_BTABLE_BTABLE_Msk          (0xFFF8UL << USB_BTABLE_BTABLE_Pos)/*!< 0x00000000 */
23221 #define USB_BTABLE_BTABLE              USB_BTABLE_BTABLE_Msk              /*!< Buffer Table Mask */
23222 
23223 /*******************  Bit definition for LPMCSR register  *********************/
23224 #define USB_LPMCSR_LMPEN_Pos           (0U)
23225 #define USB_LPMCSR_LMPEN_Msk           (0x1UL << USB_LPMCSR_LMPEN_Pos)  /*!< 0x00000001 */
23226 #define USB_LPMCSR_LMPEN               USB_LPMCSR_LMPEN_Msk             /*!< LPM support enable Mask */
23227 #define USB_LPMCSR_LPMACK_Pos          (1U)
23228 #define USB_LPMCSR_LPMACK_Msk          (0x1UL << USB_LPMCSR_LPMACK_Pos) /*!< 0x00000002 */
23229 #define USB_LPMCSR_LPMACK              USB_LPMCSR_LPMACK_Msk            /*!< LPM Token acknowledge enable Mask */
23230 #define USB_LPMCSR_REMWAKE_Pos         (3U)
23231 #define USB_LPMCSR_REMWAKE_Msk         (0x1UL << USB_LPMCSR_REMWAKE_Pos)/*!< 0x00000008 */
23232 #define USB_LPMCSR_REMWAKE             USB_LPMCSR_REMWAKE_Msk           /*!< bRemoteWake value received with last ACKed LPM Token Mask */
23233 #define USB_LPMCSR_BESL_Pos            (4U)
23234 #define USB_LPMCSR_BESL_Msk            (0xFUL << USB_LPMCSR_BESL_Pos)   /*!< 0x000000F0 */
23235 #define USB_LPMCSR_BESL                USB_LPMCSR_BESL_Msk              /*!< BESL value received with last ACKed LPM Token Mask */
23236 
23237 /******************  Bits definition for USB_DRD_BCDR register  *******************/
23238 #define USB_BCDR_BCDEN_Pos             (0U)
23239 #define USB_BCDR_BCDEN_Msk             (0x1UL << USB_BCDR_BCDEN_Pos)    /*!< 0x00000001 */
23240 #define USB_BCDR_BCDEN                 USB_BCDR_BCDEN_Msk               /*!< Battery charging detector (BCD) enable Mask */
23241 #define USB_BCDR_DCDEN_Pos             (1U)
23242 #define USB_BCDR_DCDEN_Msk             (0x1UL << USB_BCDR_DCDEN_Pos)    /*!< 0x00000002 */
23243 #define USB_BCDR_DCDEN                 USB_BCDR_DCDEN_Msk               /*!< Data contact detection (DCD) mode enable Mask */
23244 #define USB_BCDR_PDEN_Pos              (2U)
23245 #define USB_BCDR_PDEN_Msk              (0x1UL << USB_BCDR_PDEN_Pos)     /*!< 0x00000004 */
23246 #define USB_BCDR_PDEN                  USB_BCDR_PDEN_Msk                /*!< Primary detection (PD) mode enable Mask */
23247 #define USB_BCDR_SDEN_Pos              (3U)
23248 #define USB_BCDR_SDEN_Msk              (0x1UL << USB_BCDR_SDEN_Pos)     /*!< 0x00000008 */
23249 #define USB_BCDR_SDEN                  USB_BCDR_SDEN_Msk                /*!< Secondary detection (SD) mode enable Mask */
23250 #define USB_BCDR_DCDET_Pos             (4U)
23251 #define USB_BCDR_DCDET_Msk             (0x1UL << USB_BCDR_DCDET_Pos)    /*!< 0x00000010 */
23252 #define USB_BCDR_DCDET                 USB_BCDR_DCDET_Msk               /*!< Data contact detection (DCD) status Mask */
23253 #define USB_BCDR_PDET_Pos              (5U)
23254 #define USB_BCDR_PDET_Msk              (0x1UL << USB_BCDR_PDET_Pos)     /*!< 0x00000020 */
23255 #define USB_BCDR_PDET                  USB_BCDR_PDET_Msk                /*!< Primary detection (PD) status Mask */
23256 #define USB_BCDR_SDET_Pos              (6U)
23257 #define USB_BCDR_SDET_Msk              (0x1UL << USB_BCDR_SDET_Pos)     /*!< 0x00000040 */
23258 #define USB_BCDR_SDET                  USB_BCDR_SDET_Msk                /*!< Secondary detection (SD) status Mask */
23259 #define USB_BCDR_PS2DET_Pos            (7U)
23260 #define USB_BCDR_PS2DET_Msk            (0x1UL << USB_BCDR_PS2DET_Pos)   /*!< 0x00000080 */
23261 #define USB_BCDR_PS2DET                USB_BCDR_PS2DET_Msk              /*!< PS2 port or proprietary charger detected Mask */
23262 #define USB_BCDR_DPPU_Pos              (15U)
23263 #define USB_BCDR_DPPU_Msk              (0x1UL << USB_BCDR_DPPU_Pos)     /*!< 0x00008000 */
23264 #define USB_BCDR_DPPU                  USB_BCDR_DPPU_Msk                /*!< DP Pull-up Enable Mask */
23265 #define USB_BCDR_DPPD_Pos              (15U)
23266 #define USB_BCDR_DPPD_Msk              (0x1UL << USB_BCDR_DPPD_Pos)     /*!< 0x00008000 */
23267 #define USB_BCDR_DPPD                  USB_BCDR_DPPD_Msk                /*!< DP Pull-Down Enable Mask */
23268 
23269 /******************  Bits definition for USB_DRD_CHEP register  *******************/
23270 #define USB_CHEP_ERRRX_Pos             (26U)
23271 #define USB_CHEP_ERRRX_Msk             (0x01UL << USB_CHEP_ERRRX_Pos)   /*!< 0x04000000 */
23272 #define USB_CHEP_ERRRX                 USB_CHEP_ERRRX_Msk               /*!< Receive error */
23273 #define USB_EP_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< EP Receive error */
23274 #define USB_CH_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< CH Receive error */
23275 #define USB_CHEP_ERRTX_Pos             (25U)
23276 #define USB_CHEP_ERRTX_Msk             (0x01UL << USB_CHEP_ERRTX_Pos)   /*!< 0x02000000 */
23277 #define USB_CHEP_ERRTX                 USB_CHEP_ERRTX_Msk               /*!< Transmit error */
23278 #define USB_EP_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< EP Transmit error */
23279 #define USB_CH_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< CH Transmit error */
23280 #define USB_CHEP_LSEP_Pos              (24U)
23281 #define USB_CHEP_LSEP_Msk              (0x01UL << USB_CHEP_LSEP_Pos)    /*!< 0x01000000 */
23282 #define USB_CHEP_LSEP                  USB_CHEP_LSEP_Msk                /*!< Low Speed Endpoint (host with Hub Only) */
23283 #define USB_CHEP_NAK_Pos               (23U)
23284 #define USB_CHEP_NAK_Msk               (0x01UL << USB_CHEP_NAK_Pos)     /*!< 0x00800000 */
23285 #define USB_CHEP_NAK                   USB_CHEP_NAK_Msk                 /*!< Previous NAK detected */
23286 #define USB_CHEP_DEVADDR_Pos           (16U)
23287 #define USB_CHEP_DEVADDR_Msk           (0x7FU << USB_CHEP_DEVADDR_Pos)  /*!< 0x7F000000 */
23288 #define USB_CHEP_DEVADDR               USB_CHEP_DEVADDR_Msk             /* Target Endpoint address*/
23289 #define USB_CHEP_VTRX_Pos              (15U)
23290 #define USB_CHEP_VTRX_Msk              (0x1UL << USB_CHEP_VTRX_Pos)     /*!< 0x00008000 */
23291 #define USB_CHEP_VTRX                  USB_CHEP_VTRX_Msk                /*!< USB valid transaction received Mask */
23292 #define USB_EP_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB Endpoint valid transaction received Mask */
23293 #define USB_CH_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB valid Channel transaction received Mask */
23294 #define USB_CHEP_DTOG_RX_Pos           (14U)
23295 #define USB_CHEP_DTOG_RX_Msk           (0x1UL << USB_CHEP_DTOG_RX_Pos)  /*!< 0x00004000 */
23296 #define USB_CHEP_DTOG_RX               USB_CHEP_DTOG_RX_Msk             /*!< Data Toggle, for reception transfers Mask */
23297 #define USB_EP_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< EP Data Toggle, for reception transfers Mask */
23298 #define USB_CH_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< CH Data Toggle, for reception transfers Mask */
23299 #define USB_CHEP_RX_STRX_Pos           (12U)
23300 #define USB_CHEP_RX_STRX_Msk           (0x3UL << USB_CHEP_RX_STRX_Pos)  /*!< 0x00003000 */
23301 #define USB_CHEP_RX_STRX               USB_CHEP_RX_STRX_Msk             /*!< Status bits, for reception transfers Mask */
23302 #define USB_EP_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for EP reception transfers Mask */
23303 #define USB_CH_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for CH reception transfers Mask */
23304 #define USB_CHEP_SETUP_Pos             (11U)
23305 #define USB_CHEP_SETUP_Msk             (0x1UL << USB_CHEP_SETUP_Pos)    /*!< 0x00000800 */
23306 #define USB_CHEP_SETUP                 USB_CHEP_SETUP_Msk               /*!< Setup transaction completed Mask */
23307 #define USB_EP_SETUP                   USB_CHEP_SETUP_Msk               /*!< EP Setup transaction completed Mask */
23308 #define USB_CH_SETUP                   USB_CHEP_SETUP_Msk               /*!< CH Setup transaction completed Mask */
23309 #define USB_CHEP_UTYPE_Pos             (9U)
23310 #define USB_CHEP_UTYPE_Msk             (0x3UL << USB_CHEP_UTYPE_Pos)    /*!< 0x00000600 */
23311 #define USB_CHEP_UTYPE                 USB_CHEP_UTYPE_Msk               /*!< USB type of transaction Mask */
23312 #define USB_EP_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of EP transaction Mask */
23313 #define USB_CH_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of CH transaction Mask */
23314 #define USB_CHEP_KIND_Pos              (8U)
23315 #define USB_CHEP_KIND_Msk              (0x1UL << USB_CHEP_KIND_Pos)     /*!< 0x00000100 */
23316 #define USB_CHEP_KIND                  USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
23317 #define USB_EP_KIND                    USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
23318 #define USB_CH_KIND                    USB_CHEP_KIND_Msk                /*!< Channel KIND Mask */
23319 #define USB_CHEP_VTTX_Pos              (7U)
23320 #define USB_CHEP_VTTX_Msk              (0x1UL << USB_CHEP_VTTX_Pos)     /*!< 0x00000080 */
23321 #define USB_CHEP_VTTX                  USB_CHEP_VTTX_Msk                /*!< Valid USB transaction transmitted Mask */
23322 #define USB_EP_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB Endpoint valid transaction transmitted Mask */
23323 #define USB_CH_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB valid Channel transaction transmitted Mask */
23324 #define USB_CHEP_DTOG_TX_Pos           (6U)
23325 #define USB_CHEP_DTOG_TX_Msk           (0x1UL << USB_CHEP_DTOG_TX_Pos)  /*!< 0x00000040 */
23326 #define USB_CHEP_DTOG_TX               USB_CHEP_DTOG_TX_Msk             /*!< Data Toggle, for transmission transfers Mask */
23327 #define USB_EP_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< EP Data Toggle, for transmission transfers Mask */
23328 #define USB_CH_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< CH Data Toggle, for transmission transfers Mask */
23329 #define USB_CHEP_TX_STTX_Pos           (4U)
23330 #define USB_CHEP_TX_STTX_Msk           (0x3UL << USB_CHEP_TX_STTX_Pos)  /*!< 0x00000030 */
23331 #define USB_CHEP_TX_STTX               USB_CHEP_TX_STTX_Msk             /*!< Status bits, for transmission transfers Mask */
23332 #define USB_EP_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for EP transmission transfers Mask */
23333 #define USB_CH_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for CH transmission transfers Mask */
23334 #define USB_CHEP_ADDR_Pos              (0U)
23335 #define USB_CHEP_ADDR_Msk              (0xFUL << USB_CHEP_ADDR_Pos)     /*!< 0x0000000F */
23336 #define USB_CHEP_ADDR                  USB_CHEP_ADDR_Msk                /*!< Endpoint address Mask */
23337 
23338 
23339 /* EndPoint Register MASK (no toggle fields) */
23340 #define USB_CHEP_REG_MASK                          (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
23341                                                     USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
23342                                                     USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR | \
23343                                                     USB_CHEP_NAK) /* 0x07FF8F8F */
23344 
23345 #define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
23346 #define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
23347 
23348 #define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
23349 #define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
23350 #define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
23351 #define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
23352 
23353 /*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
23354 #define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
23355 #define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
23356 #define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
23357 #define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
23358 #define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */
23359 
23360 #define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
23361 #define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
23362 
23363 #define USB_EP_KIND_MASK                           ((~USB_EP_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
23364 #define USB_CH_KIND_MASK                           ((~USB_CH_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
23365 
23366 /*!< STAT_TX[1:0] STATus for TX transfer */
23367 #define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
23368 #define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
23369 #define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
23370 #define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */
23371 
23372 #define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
23373 #define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
23374 #define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
23375 #define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */
23376 
23377 #define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
23378 #define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
23379 
23380 #define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
23381 #define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
23382 
23383 /*!< STAT_RX[1:0] STATus for RX transfer */
23384 #define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
23385 #define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
23386 #define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
23387 #define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */
23388 
23389 #define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
23390 #define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
23391 
23392 
23393 
23394 #define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
23395 #define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
23396 #define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
23397 #define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */
23398 
23399 #define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
23400 #define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
23401 
23402 /*! <used For Double Buffer Enable Disable */
23403 #define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)
23404 
23405 /*Buffer Descriptor Mask*/
23406 #define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
23407 #define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
23408 #define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)
23409 #define USB_PMA_RXBD_COUNTMSK                      (0x03FFFFFFUL)
23410 
23411 
23412 /******************************************************************************/
23413 /*                                                                            */
23414 /*                       Public Key Accelerator (PKA)                         */
23415 /*                                                                            */
23416 /******************************************************************************/
23417 
23418 /*******************  Bit definition for PKA_CR register  *********************/
23419 #define PKA_CR_EN_Pos                       (0U)
23420 #define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
23421 #define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
23422 #define PKA_CR_START_Pos                    (1U)
23423 #define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
23424 #define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
23425 #define PKA_CR_MODE_Pos                     (8U)
23426 #define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
23427 #define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
23428 #define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
23429 #define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
23430 #define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
23431 #define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
23432 #define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
23433 #define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
23434 #define PKA_CR_PROCENDIE_Pos                (17U)
23435 #define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
23436 #define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
23437 #define PKA_CR_RAMERRIE_Pos                 (19U)
23438 #define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
23439 #define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
23440 #define PKA_CR_ADDRERRIE_Pos                (20U)
23441 #define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
23442 #define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
23443 #define PKA_CR_OPERRIE_Pos                  (21U)
23444 #define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
23445 #define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
23446 
23447 /*******************  Bit definition for PKA_SR register  *********************/
23448 #define PKA_SR_INITOK_Pos                   (0U)
23449 #define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
23450 #define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
23451 #define PKA_SR_BUSY_Pos                     (16U)
23452 #define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
23453 #define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
23454 #define PKA_SR_PROCENDF_Pos                 (17U)
23455 #define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
23456 #define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
23457 #define PKA_SR_RAMERRF_Pos                  (19U)
23458 #define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
23459 #define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
23460 #define PKA_SR_ADDRERRF_Pos                 (20U)
23461 #define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
23462 #define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
23463 #define PKA_SR_OPERRF_Pos                   (21U)
23464 #define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
23465 #define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
23466 
23467 /*******************  Bit definition for PKA_CLRFR register  ******************/
23468 #define PKA_CLRFR_PROCENDFC_Pos             (17U)
23469 #define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
23470 #define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
23471 #define PKA_CLRFR_RAMERRFC_Pos              (19U)
23472 #define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
23473 #define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
23474 #define PKA_CLRFR_ADDRERRFC_Pos             (20U)
23475 #define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
23476 #define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
23477 #define PKA_CLRFR_OPERRFC_Pos               (21U)
23478 #define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
23479 #define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
23480 
23481 /*******************  Bits definition for PKA RAM  *************************/
23482 #define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
23483 
23484 /* Compute Montgomery parameter input data */
23485 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
23486 #define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
23487 
23488 /* Compute Montgomery parameter output data */
23489 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
23490 
23491 /* Compute modular exponentiation input data */
23492 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
23493 #define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23494 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
23495 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
23496 #define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
23497 #define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
23498 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
23499 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
23500 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
23501 #define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
23502 
23503 /* Compute modular exponentiation output data */
23504 #define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
23505 #define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
23506 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
23507 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
23508 
23509 /* Compute ECC scalar multiplication input data */
23510 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
23511 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
23512 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
23513 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
23514 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
23515 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
23516 #define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
23517 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
23518 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
23519 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
23520 
23521 /* Compute ECC scalar multiplication output data */
23522 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
23523 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
23524 #define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
23525 
23526 /* Point check input data */
23527 #define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
23528 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
23529 #define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
23530 #define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
23531 #define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
23532 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
23533 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
23534 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
23535 
23536 /* Point check output data */
23537 #define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
23538 
23539 /* ECDSA signature input data */
23540 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
23541 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
23542 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
23543 #define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
23544 #define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
23545 #define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
23546 #define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
23547 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
23548 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
23549 #define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
23550 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
23551 #define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
23552 
23553 /* ECDSA signature output data */
23554 #define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
23555 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
23556 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
23557 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
23558 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
23559 
23560 
23561 /* ECDSA verification input data */
23562 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
23563 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
23564 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
23565 #define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
23566 #define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
23567 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
23568 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
23569 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
23570 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
23571 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
23572 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
23573 #define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
23574 #define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
23575 
23576 /* ECDSA verification output data */
23577 #define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23578 
23579 /* RSA CRT exponentiation input data */
23580 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
23581 #define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
23582 #define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
23583 #define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
23584 #define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
23585 #define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
23586 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
23587 
23588 /* RSA CRT exponentiation output data */
23589 #define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23590 
23591 /* Modular reduction input data */
23592 #define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
23593 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
23594 #define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
23595 #define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
23596 
23597 /* Modular reduction output data */
23598 #define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23599 
23600 /* Arithmetic addition input data */
23601 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23602 #define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23603 #define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23604 
23605 /* Arithmetic addition output data */
23606 #define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23607 
23608 /* Arithmetic subtraction input data */
23609 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23610 #define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23611 #define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23612 
23613 /* Arithmetic subtraction output data */
23614 #define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23615 
23616 /* Arithmetic multiplication input data */
23617 #define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23618 #define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23619 #define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23620 
23621 /* Arithmetic multiplication output data */
23622 #define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23623 
23624 /* Comparison input data */
23625 #define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23626 #define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23627 #define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23628 
23629 /* Comparison output data */
23630 #define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23631 
23632 /* Modular addition input data */
23633 #define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23634 #define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23635 #define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23636 #define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
23637 
23638 /* Modular addition output data */
23639 #define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23640 
23641 /* Modular inversion input data */
23642 #define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23643 #define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23644 #define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
23645 
23646 /* Modular inversion output data */
23647 #define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23648 
23649 /* Modular subtraction input data */
23650 #define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23651 #define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23652 #define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23653 #define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
23654 
23655 /* Modular subtraction output data */
23656 #define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23657 
23658 /* Montgomery multiplication input data */
23659 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23660 #define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23661 #define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23662 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
23663 
23664 /* Montgomery multiplication output data */
23665 #define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
23666 
23667 /* Generic Arithmetic input data */
23668 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
23669 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
23670 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
23671 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
23672 
23673 /* Generic Arithmetic output data */
23674 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
23675 
23676 /* Compute ECC complete addition input data */
23677 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
23678 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
23679 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
23680 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
23681 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
23682 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
23683 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
23684 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
23685 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
23686 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
23687 
23688 /* Compute ECC complete addition output data */
23689 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
23690 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
23691 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
23692 
23693 /* Compute ECC double base ladder input data */
23694 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
23695 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
23696 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
23697 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
23698 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
23699 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
23700 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
23701 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
23702 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
23703 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
23704 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
23705 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
23706 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
23707 
23708 /* Compute ECC double base ladder output data */
23709 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
23710 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
23711 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
23712 
23713 /* Compute ECC projective to affine conversion input data */
23714 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
23715 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
23716 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
23717 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
23718 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
23719 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
23720 
23721 /* Compute ECC projective to affine conversion output data */
23722 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
23723 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
23724 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
23725 
23726 
23727 /** @addtogroup STM32H5xx_Peripheral_Exported_macros
23728   * @{
23729   */
23730 
23731 /******************************* ADC Instances ********************************/
23732 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) ||                   \
23733                                         ((INSTANCE) == ADC1_S)||                    \
23734                                         ((INSTANCE) == ADC2_NS)||                   \
23735                                         ((INSTANCE) == ADC2_S))
23736 
23737 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
23738                                                      ((INSTANCE) == ADC1_S))
23739 
23740 
23741 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) ||         \
23742                                           ((INSTANCE) == ADC12_COMMON_S))
23743 /******************************* AES Instances ********************************/
23744 #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S))
23745 
23746 /******************************* PKA Instances ********************************/
23747 #define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
23748 
23749 
23750 /******************************* CORDIC Instances *****************************/
23751 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
23752 
23753 /******************************* CRC Instances ********************************/
23754 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S))
23755 
23756 /******************************* DAC Instances ********************************/
23757 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S))
23758 
23759 /******************************* DCACHE Instances *****************************/
23760 #define IS_DCACHE_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S))
23761 
23762 /******************************* DELAYBLOCK Instances *******************************/
23763 #define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1_NS)   || \
23764                                          ((INSTANCE) == DLYB_SDMMC2_NS)   || \
23765                                          ((INSTANCE) == DLYB_SDMMC1_S)    || \
23766                                          ((INSTANCE) == DLYB_SDMMC2_S)    || \
23767                                          ((INSTANCE) == DLYB_OCTOSPI1_NS) || \
23768                                          ((INSTANCE) == DLYB_OCTOSPI1_S ))
23769 /******************************** DMA Instances *******************************/
23770 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || ((INSTANCE) == GPDMA1_Channel0_S)  || \
23771                                        ((INSTANCE) == GPDMA1_Channel1_NS)  || ((INSTANCE) == GPDMA1_Channel1_S)  || \
23772                                        ((INSTANCE) == GPDMA1_Channel2_NS)  || ((INSTANCE) == GPDMA1_Channel2_S)  || \
23773                                        ((INSTANCE) == GPDMA1_Channel3_NS)  || ((INSTANCE) == GPDMA1_Channel3_S)  || \
23774                                        ((INSTANCE) == GPDMA1_Channel4_NS)  || ((INSTANCE) == GPDMA1_Channel4_S)  || \
23775                                        ((INSTANCE) == GPDMA1_Channel5_NS)  || ((INSTANCE) == GPDMA1_Channel5_S)  || \
23776                                        ((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
23777                                        ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
23778                                        ((INSTANCE) == GPDMA2_Channel0_NS)  || ((INSTANCE) == GPDMA2_Channel0_S)  || \
23779                                        ((INSTANCE) == GPDMA2_Channel1_NS)  || ((INSTANCE) == GPDMA2_Channel1_S)  || \
23780                                        ((INSTANCE) == GPDMA2_Channel2_NS)  || ((INSTANCE) == GPDMA2_Channel2_S)  || \
23781                                        ((INSTANCE) == GPDMA2_Channel3_NS)  || ((INSTANCE) == GPDMA2_Channel3_S)  || \
23782                                        ((INSTANCE) == GPDMA2_Channel4_NS)  || ((INSTANCE) == GPDMA2_Channel4_S)  || \
23783                                        ((INSTANCE) == GPDMA2_Channel5_NS)  || ((INSTANCE) == GPDMA2_Channel5_S)  || \
23784                                        ((INSTANCE) == GPDMA2_Channel6_NS)  || ((INSTANCE) == GPDMA2_Channel6_S)  || \
23785                                        ((INSTANCE) == GPDMA2_Channel7_NS)  || ((INSTANCE) == GPDMA2_Channel7_S))
23786 
23787 #define IS_GPDMA_INSTANCE(INSTANCE)   IS_DMA_ALL_INSTANCE(INSTANCE)
23788 
23789 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
23790                                                  ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
23791                                                  ((INSTANCE) == GPDMA2_Channel6_NS)  || ((INSTANCE) == GPDMA2_Channel6_S)  || \
23792                                                  ((INSTANCE) == GPDMA2_Channel7_NS)  || ((INSTANCE) == GPDMA2_Channel7_S))
23793 
23794 /****************************** OTFDEC Instances ********************************/
23795 #define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S))
23796 
23797 /****************************** RAMCFG Instances ********************************/
23798 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS)  || ((INSTANCE) == RAMCFG_SRAM1_S)  || \
23799                                           ((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S)  || \
23800                                           ((INSTANCE) == RAMCFG_SRAM3_NS)  || ((INSTANCE) == RAMCFG_SRAM3_S)  || \
23801                                           ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
23802 
23803 /***************************** RAMCFG ECC Instances *****************************/
23804 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S)  || \
23805                                           ((INSTANCE) == RAMCFG_SRAM3_NS)  || ((INSTANCE) == RAMCFG_SRAM3_S)  || \
23806                                           ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
23807 
23808 /************************ RAMCFG Write Protection Instances *********************/
23809 #define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S))
23810 
23811 
23812 /******************************** FMAC Instances ******************************/
23813 #define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S))
23814 
23815 /******************************* GPIO Instances *******************************/
23816 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \
23817                                         ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \
23818                                         ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \
23819                                         ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \
23820                                         ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \
23821                                         ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \
23822                                         ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \
23823                                         ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \
23824                                         ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S))
23825 
23826 /******************************* DCMI Instances *******************************/
23827 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S))
23828 
23829 /******************************* PSSI Instances *******************************/
23830 #define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S))
23831 
23832 /******************************* DTS Instances *******************************/
23833 #define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S))
23834 
23835 /******************************* GPIO AF Instances ****************************/
23836 /* On H5, all GPIO Bank support AF */
23837 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
23838 
23839 /**************************** GPIO Lock Instances *****************************/
23840 /* On H5, all GPIO Bank support the Lock mechanism */
23841 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
23842 
23843 /******************************** I2C Instances *******************************/
23844 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
23845                                        ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
23846                                        ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
23847                                        ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
23848 
23849 /****************** I2C Instances : wakeup capability from stop modes *********/
23850 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
23851 
23852 /******************************** I3C Instances *******************************/
23853 #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S))
23854 
23855 /******************************* OSPI Instances *******************************/
23856 #define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S))
23857 
23858 /******************************* RNG Instances ********************************/
23859 #define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S))
23860 
23861 /****************************** RTC Instances *********************************/
23862 #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S))
23863 
23864 /******************************** SAI Instances *******************************/
23865 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \
23866                                        ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \
23867                                        ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \
23868                                        ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S))
23869 
23870 /****************************** SDMMC Instances *******************************/
23871 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \
23872                                          ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S))
23873 
23874 /****************************** FDCAN Instances *******************************/
23875 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \
23876                                          ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S))
23877 
23878 /****************************** SMBUS Instances *******************************/
23879 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
23880                                          ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
23881                                          ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
23882                                          ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S))
23883 
23884 /******************************** SPI Instances *******************************/
23885 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
23886                                        ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
23887                                        ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \
23888                                        ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \
23889                                        ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \
23890                                        ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S))
23891 
23892 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \
23893                                            ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \
23894                                            ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S))
23895 
23896 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
23897                                         ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
23898                                         ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
23899 
23900 /****************** LPTIM Instances : All supported instances *****************/
23901 #define IS_LPTIM_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
23902                                       ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
23903                                       ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
23904                                       ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\
23905                                       ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\
23906                                       ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S))
23907 
23908 /****************** LPTIM Instances : DMA supported instances *****************/
23909 #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
23910                                          ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
23911                                          ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
23912                                          ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\
23913                                          ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S))
23914 
23915 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
23916 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS)  || ((INSTANCE) == LPTIM1_S) ||\
23917                                          ((INSTANCE) == LPTIM2_NS)  || ((INSTANCE) == LPTIM2_S) ||\
23918                                          ((INSTANCE) == LPTIM3_NS)  || ((INSTANCE) == LPTIM3_S) ||\
23919                                          ((INSTANCE) == LPTIM4_NS)  || ((INSTANCE) == LPTIM4_S) ||\
23920                                          ((INSTANCE) == LPTIM5_NS)  || ((INSTANCE) == LPTIM5_S) ||\
23921                                          ((INSTANCE) == LPTIM6_NS)  || ((INSTANCE) == LPTIM6_S))
23922 
23923 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
23924 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
23925                                          ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
23926                                          ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
23927                                          ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\
23928                                          ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S))
23929 
23930 /****************** LPTIM Instances : supporting encoder interface **************/
23931 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
23932                                                        ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
23933                                                        ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
23934                                                        ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\
23935                                                        ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S))
23936 
23937 /****************** LPTIM Instances : supporting Input Capture **************/
23938 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
23939                                                    ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
23940                                                    ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
23941                                                    ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\
23942                                                    ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S))
23943 
23944 /****************** TIM Instances : All supported instances *******************/
23945 #define IS_TIM_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23946                                     ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
23947                                     ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
23948                                     ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
23949                                     ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
23950                                     ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
23951                                     ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
23952                                     ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
23953                                     ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
23954                                     ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
23955                                     ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
23956                                     ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
23957                                     ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
23958                                     ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
23959 
23960 /****************** TIM Instances : supporting 32 bits counter ****************/
23961 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
23962                                                ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S))
23963 
23964 /****************** TIM Instances : supporting the break function *************/
23965 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23966                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
23967                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
23968                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
23969                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
23970 
23971 /************** TIM Instances : supporting Break source selection *************/
23972 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23973                                                ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
23974                                                ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
23975                                                ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
23976                                                ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
23977 
23978 /****************** TIM Instances : supporting 2 break inputs *****************/
23979 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23980                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
23981 
23982 /************* TIM Instances : at least 1 capture/compare channel *************/
23983 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23984                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
23985                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
23986                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
23987                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
23988                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
23989                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
23990                                          ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
23991                                          ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
23992                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
23993                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
23994                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
23995 
23996 /************ TIM Instances : at least 2 capture/compare channels *************/
23997 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
23998                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
23999                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24000                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24001                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24002                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24003                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24004                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24005 
24006 /************ TIM Instances : at least 3 capture/compare channels *************/
24007 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24008                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24009                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24010                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24011                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24012                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24013 
24014 /************ TIM Instances : at least 4 capture/compare channels *************/
24015 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24016                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24017                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24018                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24019                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24020                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24021 
24022 /****************** TIM Instances : at least 5 capture/compare channels *******/
24023 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24024                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24025 
24026 /****************** TIM Instances : at least 6 capture/compare channels *******/
24027 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24028                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24029 
24030 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
24031 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24032                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24033                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24034                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24035                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24036                                             ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
24037                                             ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
24038                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24039                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24040                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24041                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24042 
24043 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
24044 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24045                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24046                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24047                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24048                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24049                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24050                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24051                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24052                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24053 
24054 /******************** TIM Instances : DMA burst feature ***********************/
24055 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24056                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24057                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24058                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24059                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24060                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24061                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24062                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24063                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24064 
24065 /******************* TIM Instances : output(s) available **********************/
24066 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
24067     (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
24068      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24069       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24070       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24071       ((CHANNEL) == TIM_CHANNEL_4) ||          \
24072       ((CHANNEL) == TIM_CHANNEL_5) ||          \
24073       ((CHANNEL) == TIM_CHANNEL_6)))           \
24074      ||                                        \
24075      ((((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S))  && \
24076      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24077       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24078       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24079       ((CHANNEL) == TIM_CHANNEL_4)))           \
24080      ||                                        \
24081      ((((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))  && \
24082      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24083       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24084       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24085       ((CHANNEL) == TIM_CHANNEL_4)))           \
24086      ||                                        \
24087      ((((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))  && \
24088      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24089       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24090       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24091       ((CHANNEL) == TIM_CHANNEL_4)))           \
24092      ||                                        \
24093      ((((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S))  && \
24094      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24095       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24096       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24097       ((CHANNEL) == TIM_CHANNEL_4)))           \
24098      ||                                        \
24099      ((((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))  && \
24100      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24101       ((CHANNEL) == TIM_CHANNEL_2) ||          \
24102       ((CHANNEL) == TIM_CHANNEL_3) ||          \
24103       ((CHANNEL) == TIM_CHANNEL_4) ||          \
24104       ((CHANNEL) == TIM_CHANNEL_5) ||          \
24105       ((CHANNEL) == TIM_CHANNEL_6)))           \
24106      ||                                        \
24107      ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \
24108      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24109       ((CHANNEL) == TIM_CHANNEL_2)))           \
24110      ||                                        \
24111      ((((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)) && \
24112      (((CHANNEL) == TIM_CHANNEL_1)))           \
24113      ||                                        \
24114      ((((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)) && \
24115      (((CHANNEL) == TIM_CHANNEL_1)))           \
24116      ||                                        \
24117      ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
24118      (((CHANNEL) == TIM_CHANNEL_1) ||          \
24119       ((CHANNEL) == TIM_CHANNEL_2)))           \
24120      ||                                        \
24121      ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
24122      (((CHANNEL) == TIM_CHANNEL_1)))           \
24123      ||                                        \
24124      ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
24125      (((CHANNEL) == TIM_CHANNEL_1))))
24126 
24127 /****************** TIM Instances : supporting complementary output(s) ********/
24128 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
24129     (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
24130      (((CHANNEL) == TIM_CHANNEL_1) ||           \
24131       ((CHANNEL) == TIM_CHANNEL_2) ||           \
24132       ((CHANNEL) == TIM_CHANNEL_3) ||           \
24133       ((CHANNEL) == TIM_CHANNEL_4)))            \
24134     ||                                          \
24135     ((((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))  && \
24136      (((CHANNEL) == TIM_CHANNEL_1) ||           \
24137       ((CHANNEL) == TIM_CHANNEL_2) ||           \
24138       ((CHANNEL) == TIM_CHANNEL_3) ||           \
24139       ((CHANNEL) == TIM_CHANNEL_4)))            \
24140     ||                                          \
24141     ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
24142      ((CHANNEL) == TIM_CHANNEL_1))              \
24143     ||                                          \
24144     ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
24145      ((CHANNEL) == TIM_CHANNEL_1))              \
24146     ||                                          \
24147     ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
24148      ((CHANNEL) == TIM_CHANNEL_1)))
24149 
24150 /****************** TIM Instances : supporting clock division *****************/
24151 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24152                                                     ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24153                                                     ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24154                                                     ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24155                                                     ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24156                                                     ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24157                                                     ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24158                                                     ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
24159                                                     ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
24160                                                     ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24161                                                     ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24162                                                     ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24163 
24164 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
24165 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24166                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24167                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24168                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24169                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24170                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24171 
24172 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
24173 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24174                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24175                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24176                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24177                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24178                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24179 
24180 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
24181 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24182                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24183                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24184                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24185                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24186                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24187                                                         ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24188                                                         ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
24189                                                         ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
24190                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24191 
24192 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
24193 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24194                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24195                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24196                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24197                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24198                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24199                                                         ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24200                                                         ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
24201                                                         ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
24202                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24203 
24204 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
24205 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24206                                                      ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24207 
24208 /****************** TIM Instances : supporting commutation event generation ***/
24209 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24210                                                      ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24211                                                      ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24212                                                      ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24213                                                      ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24214 
24215 /****************** TIM Instances : supporting counting mode selection ********/
24216 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24217                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24218                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24219                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24220                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24221                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24222 
24223 /****************** TIM Instances : supporting encoder interface **************/
24224 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24225                                                       ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24226                                                       ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24227                                                       ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24228                                                       ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24229                                                       ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24230 
24231 /****************** TIM Instances : supporting Hall sensor interface **********/
24232 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || ((INSTANCE) == TIM1_S)  || \
24233                                                          ((INSTANCE) == TIM2_NS)   || ((INSTANCE) == TIM2_S)  || \
24234                                                          ((INSTANCE) == TIM3_NS)   || ((INSTANCE) == TIM3_S)  || \
24235                                                          ((INSTANCE) == TIM4_NS)   || ((INSTANCE) == TIM4_S)  || \
24236                                                          ((INSTANCE) == TIM5_NS)   || ((INSTANCE) == TIM5_S)  || \
24237                                                          ((INSTANCE) == TIM8_NS)   || ((INSTANCE) == TIM8_S))
24238 
24239 /**************** TIM Instances : external trigger input available ************/
24240 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24241                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24242                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24243                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24244                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24245                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24246 
24247 /************* TIM Instances : supporting ETR source selection ***************/
24248 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24249                                              ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24250                                              ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24251                                              ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24252                                              ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24253                                              ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24254 
24255 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
24256 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24257                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24258                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24259                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24260                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24261                                             ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
24262                                             ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
24263                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24264                                             ((INSTANCE) == TIM12_NS)  || ((INSTANCE) == TIM12_S)  || \
24265                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24266 
24267 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
24268 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24269                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24270                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24271                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24272                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24273                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24274                                             ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24275                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24276 
24277 /****************** TIM Instances : supporting OCxREF clear *******************/
24278 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24279                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24280                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24281                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24282                                                        ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24283                                                        ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24284                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24285                                                        ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24286                                                        ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24287 
24288 /****************** TIM Instances : remapping capability **********************/
24289 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24290                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24291                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24292                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24293                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24294                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24295 
24296 /****************** TIM Instances : supporting repetition counter *************/
24297 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24298                                                        ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24299                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
24300                                                        ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
24301                                                        ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24302 
24303 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
24304 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
24305                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24306 
24307 /******************* TIM Instances : Timer input XOR function *****************/
24308 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
24309                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
24310                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
24311                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
24312                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
24313                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
24314                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
24315 
24316 /******************* TIM Instances : Timer input selection ********************/
24317 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
24318                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
24319                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) || \
24320                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) || \
24321                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S) || \
24322                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S) || \
24323                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
24324                                          ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
24325                                          ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
24326                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
24327                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
24328                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
24329 
24330 /****************** TIM Instances : Advanced timer instances *******************/
24331 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
24332                                                   ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
24333 
24334 /****************** TIM Instances : supporting synchronization ****************/
24335 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || ((__INSTANCE__) == TIM1_S) || \
24336                                                 ((__INSTANCE__) == TIM2_NS)  || ((__INSTANCE__) == TIM2_S) || \
24337                                                 ((__INSTANCE__) == TIM3_NS)  || ((__INSTANCE__) == TIM3_S) || \
24338                                                 ((__INSTANCE__) == TIM4_NS)  || ((__INSTANCE__) == TIM4_S) || \
24339                                                 ((__INSTANCE__) == TIM5_NS)  || ((__INSTANCE__) == TIM5_S) || \
24340                                                 ((__INSTANCE__) == TIM6_NS)  || ((__INSTANCE__) == TIM6_S) || \
24341                                                 ((__INSTANCE__) == TIM7_NS)  || ((__INSTANCE__) == TIM7_S) || \
24342                                                 ((__INSTANCE__) == TIM8_NS)  || ((__INSTANCE__) == TIM8_S) || \
24343                                                 ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \
24344                                                 ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S))
24345 
24346 /******************** USART Instances : Synchronous mode **********************/
24347 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24348                                      ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24349                                      ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24350                                      ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24351                                      ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24352                                      ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S))
24353 
24354 /******************** UART Instances : Asynchronous mode **********************/
24355 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24356                                     ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24357                                     ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24358                                     ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24359                                     ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24360                                     ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24361                                     ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24362                                     ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24363                                     ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24364                                     ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24365                                     ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24366                                     ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S))
24367 
24368 /*********************** UART Instances : FIFO mode ***************************/
24369 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24370                                          ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24371                                          ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24372                                          ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24373                                          ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24374                                          ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24375                                          ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24376                                          ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24377                                          ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24378                                          ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24379                                          ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24380                                          ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S)  || \
24381                                          ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24382 
24383 /*********************** UART Instances : SPI Slave mode **********************/
24384 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)   || \
24385                                               ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)   || \
24386                                               ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)   || \
24387                                               ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)   || \
24388                                               ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S)  || \
24389                                               ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S))
24390 
24391 /******************************** I2S Instances *******************************/
24392 #define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
24393                                          ((INSTANCE) == SPI2) || \
24394                                          ((INSTANCE) == SPI3))
24395 
24396 /****************** UART Instances : Auto Baud Rate detection ****************/
24397 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24398                                                             ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24399                                                             ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24400                                                             ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24401                                                             ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24402                                                             ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24403                                                             ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24404                                                             ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24405                                                             ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24406                                                             ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24407                                                             ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24408                                                             ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S))
24409 
24410 /****************** UART Instances : Driver Enable *****************/
24411 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24412                                                       ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24413                                                       ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24414                                                       ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24415                                                       ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24416                                                       ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24417                                                       ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24418                                                       ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24419                                                       ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24420                                                       ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24421                                                       ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24422                                                       ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S)  || \
24423                                                       ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24424 
24425 /******************** UART Instances : Half-Duplex mode **********************/
24426 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24427                                                  ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24428                                                  ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24429                                                  ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24430                                                  ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24431                                                  ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24432                                                  ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24433                                                  ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24434                                                  ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24435                                                  ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24436                                                  ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24437                                                  ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S)  || \
24438                                                  ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24439 
24440 /****************** UART Instances : Hardware Flow control ********************/
24441 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24442                                            ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24443                                            ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24444                                            ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24445                                            ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24446                                            ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24447                                            ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24448                                            ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24449                                            ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24450                                            ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24451                                            ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24452                                            ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S)  || \
24453                                            ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24454 
24455 /******************** UART Instances : LIN mode **********************/
24456 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24457                                           ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24458                                           ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24459                                           ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24460                                           ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24461                                           ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24462                                           ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24463                                           ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24464                                           ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24465                                           ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24466                                           ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24467                                           ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S))
24468 
24469 /******************** UART Instances : Wake-up from Stop mode **********************/
24470 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24471                                                       ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24472                                                       ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24473                                                       ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24474                                                       ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24475                                                       ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24476                                                       ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24477                                                       ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24478                                                       ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24479                                                       ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24480                                                       ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24481                                                       ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S)  || \
24482                                                       ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24483 
24484 /*********************** UART Instances : IRDA mode ***************************/
24485 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24486                                     ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24487                                     ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24488                                     ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)   || \
24489                                     ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)   || \
24490                                     ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24491                                     ((INSTANCE) == UART7_NS)   || ((INSTANCE) == UART7_S)   || \
24492                                     ((INSTANCE) == UART8_NS)   || ((INSTANCE) == UART8_S)   || \
24493                                     ((INSTANCE) == UART9_NS)   || ((INSTANCE) == UART9_S)   || \
24494                                     ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24495                                     ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \
24496                                     ((INSTANCE) == UART12_NS)  || ((INSTANCE) == UART12_S))
24497 
24498 /********************* USART Instances : Smard card mode ***********************/
24499 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S)  || \
24500                                          ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S)  || \
24501                                          ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S)  || \
24502                                          ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S)  || \
24503                                          ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \
24504                                          ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S))
24505 
24506 /******************** LPUART Instance *****************************************/
24507 #define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
24508 
24509 /******************** CEC Instance *****************************************/
24510 #define IS_CEC_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S))
24511 
24512 /****************************** IWDG Instances ********************************/
24513 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S))
24514 
24515 /****************************** WWDG Instances ********************************/
24516 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S))
24517 
24518 /****************************** UCPD Instances ********************************/
24519 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S))
24520 
24521 /******************************* USB DRD FS HCD Instances *************************/
24522 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
24523 
24524 /******************************* USB DRD FS PCD Instances *************************/
24525 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
24526 
24527 
24528 /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
24529 
24530 /** @} */ /* End of group STM32H573xx */
24531 
24532 /** @} */ /* End of group ST */
24533 
24534 #ifdef __cplusplus
24535 }
24536 #endif
24537 
24538 #endif  /* STM32H573xx_H */
24539