1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32MP1xx_HAL_RCC_H 21 #define __STM32MP1xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL12_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 56 This parameter must be a number between 1 and 64 */ 57 58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock 59 This parameter must be a number between: 60 Integer mode: 25 and 100 for PLL1600 (PLL1 and PLL2), 25 and 200 for PLL800 61 Fractional mode: 4 and 512 (PLL1600 and PLL800) */ 62 63 uint32_t PLLP; /*!< PLLP: Division factor ck_pll1_p 64 This parameter must be a number between 1 and 128 */ 65 66 uint32_t PLLQ; /*!< PLLQ: Division factor ck_pll1_q 67 This parameter must be a number between 1 and 128 */ 68 69 uint32_t PLLR; /*!< PLLR: Division for ck_pll1_r 70 This parameter must be a number between 1 and 128 */ 71 72 uint32_t PLLRGE; /*!< PLLRGE: PLL input frequency range for PLL3 and PLL4 73 This parameter must be a value of @ref RCC_PLL3_IF_Range and RCC_PLL4_IF_Range */ 74 75 uint32_t PLLFRACV; /*!< PLLFRACV: Fractional Part Of The Multiplication Factor for PLL1 VCO 76 It should be a value between 0 and 8191 ((2^13)-1) */ 77 78 uint32_t PLLMODE; /*!< PLLMODE: PLL mode used 79 This parameter must be a value of @ref RCC_PLL_Mode */ 80 81 uint32_t MOD_PER; /*!< MOD_PER: Modulation Period Adjustment 82 This parameter must have a value contained on @ref RCC_MOD_PER */ 83 84 uint32_t RPDFN_DIS; /*!< RPDFN_DIS: Dithering RPDF noise control 85 This parameter must be a value of @ref RCC_RPDFN_DIS*/ 86 87 uint32_t TPDFN_DIS; /*!< TPDFN_DIS: Dithering TPDF noise control 88 This parameter must be a value of @ref RCC_TPDFN_DIS*/ 89 90 uint32_t SSCG_MODE; /*!< SSCG_MODE: Spread spectrum clock generator mode 91 This parameter must be a value of @ref RCC_SSCG_MODE*/ 92 93 uint32_t INC_STEP; /*!< INC_STEP: Modulation Depth Adjustment 94 This parameter must have a value contained on @ref RCC_INC_STEP */ 95 96 } RCC_PLLInitTypeDef; 97 98 99 100 101 typedef struct 102 { 103 uint32_t PLL1_P_Frequency; 104 uint32_t PLL1_Q_Frequency; 105 uint32_t PLL1_R_Frequency; 106 } PLL1_ClocksTypeDef; 107 108 /** 109 * @brief RCC PLL2 Clocks structure definition => [FCH] used in UART set_config use case 110 */ 111 typedef struct 112 { 113 uint32_t PLL2_P_Frequency; 114 uint32_t PLL2_Q_Frequency; 115 uint32_t PLL2_R_Frequency; 116 } PLL2_ClocksTypeDef; 117 118 /** 119 * @brief RCC PLL3 Clocks structure definition => [FCH] used in UART set_config use case 120 */ 121 typedef struct 122 { 123 uint32_t PLL3_P_Frequency; 124 uint32_t PLL3_Q_Frequency; 125 uint32_t PLL3_R_Frequency; 126 } PLL3_ClocksTypeDef; 127 128 129 typedef struct 130 { 131 uint32_t PLL4_P_Frequency; 132 uint32_t PLL4_Q_Frequency; 133 uint32_t PLL4_R_Frequency; 134 } PLL4_ClocksTypeDef; 135 136 /** 137 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 138 */ 139 typedef struct 140 { 141 142 uint32_t OscillatorType; /*!< The oscillators to be configured. 143 This parameter can be a value of @ref RCC_Oscillator_Type */ 144 145 uint32_t HSEState; /*!< The new state of the HSE. 146 This parameter can be a value of @ref RCC_HSE_Config */ 147 148 uint32_t LSEState; /*!< The new state of the LSE. 149 This parameter can be a value of @ref RCC_LSE_Config */ 150 151 uint32_t HSIState; /*!< The new state of the HSI. 152 This parameter can be a value of @ref RCC_HSI_Config */ 153 154 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 155 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 156 157 uint32_t HSIDivValue; /*!< The HSI Division value. 158 This parameter must be a value of @ref RCC_HSI_Clock_Prescaler */ 159 160 uint32_t LSIState; /*!< The new state of the LSI. 161 This parameter can be a value of @ref RCC_LSI_Config */ 162 163 uint32_t CSIState; /*!< The new state of the CSI. 164 This parameter can be a value of @ref RCC_CSI_Config */ 165 166 uint32_t CSICalibrationValue; /*!< The calibration trimming value. 167 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 168 169 RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ 170 171 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ 172 173 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ 174 175 RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters */ 176 177 } RCC_OscInitTypeDef; 178 179 /** 180 * @brief MPU configuration structure definition. 181 */ 182 typedef struct 183 { 184 uint32_t MPU_Clock; 185 uint32_t MPU_Div; 186 } RCC_MPUInitTypeDef; 187 188 /** 189 * @brief AXI configuration structure definition. 190 */ 191 typedef struct 192 { 193 uint32_t AXI_Clock; 194 uint32_t AXI_Div; 195 } RCC_AXISSInitTypeDef; 196 197 198 /** 199 * @brief MCU configuration structure definition. 200 */ 201 typedef struct 202 { 203 uint32_t MCU_Clock; 204 uint32_t MCU_Div; 205 } RCC_MCUInitTypeDef; 206 207 /** 208 * @brief RCC MPU, MCU, AXI, AHB and APB busses clock configuration structure definition. 209 */ 210 typedef struct 211 { 212 uint32_t ClockType; /*!< The clock to be configured. 213 This parameter can be a value of @ref RCC_System_Clock_Type */ 214 215 RCC_MPUInitTypeDef MPUInit; 216 RCC_AXISSInitTypeDef AXISSInit; 217 RCC_MCUInitTypeDef MCUInit; 218 uint32_t APB4_Div; 219 uint32_t APB5_Div; 220 uint32_t APB1_Div; 221 uint32_t APB2_Div; 222 uint32_t APB3_Div; 223 } RCC_ClkInitTypeDef; 224 225 /** 226 * @} 227 */ 228 229 /* Exported constants --------------------------------------------------------*/ 230 231 /** @defgroup RCC_Exported_Constants RCC Exported Constants 232 * @{ 233 */ 234 #define DBP_TIMEOUT_VALUE ((uint32_t)100) 235 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) 236 237 /** @defgroup RCC_Oscillator_Type RCC_Oscillator_Type 238 * @{ 239 */ 240 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) 241 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) 242 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) 243 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) 244 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) 245 #define RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010) 246 247 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 248 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 249 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 250 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ 251 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 252 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 253 /** 254 * @} 255 */ 256 257 /** @defgroup RCC_System_Clock_Type RCC_System_Clock_Type 258 * @{ 259 */ 260 #define RCC_CLOCKTYPE_NONE ((uint32_t)0x00000000) 261 #define RCC_CLOCKTYPE_MPU ((uint32_t)0x00000001) 262 #define RCC_CLOCKTYPE_ACLK ((uint32_t)0x00000002) 263 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000004) 264 #define RCC_CLOCKTYPE_PCLK4 ((uint32_t)0x00000008) 265 #define RCC_CLOCKTYPE_PCLK5 ((uint32_t)0x00000010) 266 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000020) 267 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000040) 268 #define RCC_CLOCKTYPE_PCLK3 ((uint32_t)0x00000080) 269 270 271 272 #define IS_RCC_CLOCKTYPETYPE(CLOCK) (((CLOCK) == RCC_CLOCKTYPE_NONE) || \ 273 (((CLOCK) & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU) || \ 274 (((CLOCK) & RCC_CLOCKTYPE_ACLK)== RCC_CLOCKTYPE_ACLK) || \ 275 (((CLOCK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 276 (((CLOCK) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) || \ 277 (((CLOCK) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) || \ 278 (((CLOCK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 279 (((CLOCK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) || \ 280 (((CLOCK) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)) 281 /** 282 * @} 283 */ 284 285 /** @defgroup RCC_HSE_Config RCC_HSE_Config 286 * @{ 287 */ 288 #define RCC_HSE_OFF ((uint32_t)0x00000000) 289 #define RCC_HSE_ON RCC_OCENSETR_HSEON 290 #define RCC_HSE_BYPASS (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON) 291 #define RCC_HSE_BYPASS_DIG (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON | RCC_OCENSETR_DIGBYP) 292 293 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 294 ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIG)) 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCC_LSE_Config RCC_LSE_Config 300 * @{ 301 */ 302 #define RCC_LSE_OFF ((uint32_t)0x00000000) 303 #define RCC_LSE_ON RCC_BDCR_LSEON 304 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) 305 #define RCC_LSE_BYPASS_DIG (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON | RCC_BDCR_DIGBYP) 306 307 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 308 ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIG)) 309 /** 310 * @} 311 */ 312 313 /** @defgroup RCC_HSI_Config RCC_HSI_Config 314 * @{ 315 */ 316 #define RCC_HSI_OFF ((uint32_t)0x00000000) 317 #define RCC_HSI_ON RCC_OCENSETR_HSION 318 319 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCC_HSI_Clock_Prescaler RCC_HSI_Clock_Prescaler 325 * @{ 326 */ 327 #define RCC_HSI_DIV1 0U /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/ 328 #define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_0 /* Division by 2, ck_hsi(_ker) = 32 MHz*/ 329 #define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_1 /* Division by 4, ck_hsi(_ker) = 16 MHz*/ 330 #define RCC_HSI_DIV8 (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1) /* Division by 8, ck_hsi(_ker) = 8 MHz*/ 331 332 #define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \ 333 ((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) ) 334 /** 335 * @} 336 */ 337 338 339 /** @defgroup RCC_LSI_Config RCC_LSI_Config 340 * @{ 341 */ 342 #define RCC_LSI_OFF ((uint32_t)0x00000000) 343 #define RCC_LSI_ON RCC_RDLSICR_LSION 344 345 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 346 /** 347 * @} 348 */ 349 350 /** @defgroup RCC_CSI_Config RCC_CSI_Config 351 * @{ 352 */ 353 #define RCC_CSI_OFF ((uint32_t)0x00000000) 354 #define RCC_CSI_ON RCC_OCENSETR_CSION 355 356 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) 357 /** 358 * @} 359 */ 360 361 362 /** @defgroup RCC_MCO_Index RCC_MCO_Index 363 * @{ 364 */ 365 #define RCC_MCO1 ((uint32_t)0x00000000) 366 #define RCC_MCO2 ((uint32_t)0x00000001) 367 368 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 369 /** 370 * @} 371 */ 372 373 /** @defgroup RCC_MCO1_Clock_Source RCC_MCO1_Clock_Source 374 * @{ 375 */ 376 #define RCC_MCO1SOURCE_HSI 0U 377 #define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_0 378 #define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_1 379 #define RCC_MCO1SOURCE_LSI (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1) 380 #define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_2 381 382 383 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 384 ((SOURCE) == RCC_MCO1SOURCE_CSI) || ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 385 ((SOURCE) == RCC_MCO1SOURCE_LSE) ) 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_MCO2_Clock_Source RCC_MCO2_Clock_Source 391 * @{ 392 */ 393 #define RCC_MCO2SOURCE_MPU 0U 394 #define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_0 395 #define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_1 396 #define RCC_MCO2SOURCE_PLL4 (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0) 397 #define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_2 398 #define RCC_MCO2SOURCE_HSI (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0) 399 400 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_MPU) || ((SOURCE) == RCC_MCO2SOURCE_AXI) || \ 401 ((SOURCE) == RCC_MCO2SOURCE_MCU) || ((SOURCE) == RCC_MCO2SOURCE_PLL4) || \ 402 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_HSI)) 403 /** 404 * @} 405 */ 406 407 /** @defgroup RCC_MCOx_Clock_Prescaler RCC_MCOx_Clock_Prescaler 408 * @{ 409 * @note: MCO1 division factors are used for MCODIV values as they are the same for MCO2 410 */ 411 #define RCC_MCODIV_1 0U 412 #define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_0 413 #define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_1 414 #define RCC_MCODIV_4 (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) 415 #define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_2 416 #define RCC_MCODIV_6 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) 417 #define RCC_MCODIV_7 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) 418 #define RCC_MCODIV_8 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) 419 #define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_3 420 #define RCC_MCODIV_10 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0) 421 #define RCC_MCODIV_11 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1) 422 #define RCC_MCODIV_12 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) 423 #define RCC_MCODIV_13 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2) 424 #define RCC_MCODIV_14 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) 425 #define RCC_MCODIV_15 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) 426 #define RCC_MCODIV_16 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) 427 428 429 430 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 431 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 432 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 433 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 434 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 435 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 436 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 437 ((DIV) == RCC_MCODIV_15) || ((DIV) == RCC_MCODIV_16) ) 438 /** 439 * @} 440 */ 441 442 443 /** @defgroup RCC_MPU_Clock_Source RCC_MPU_Clock_Source 444 * @{ 445 */ 446 #define RCC_MPUSOURCE_HSI 0U 447 #define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_0 448 #define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_1 449 #define RCC_MPUSOURCE_MPUDIV (RCC_MPCKSELR_MPUSRC_0 | RCC_MPCKSELR_MPUSRC_1) 450 451 #define IS_RCC_MPUSOURCE(SOURCE) (((SOURCE) == RCC_MPUSOURCE_HSI) || \ 452 ((SOURCE) == RCC_MPUSOURCE_HSE) || \ 453 ((SOURCE) == RCC_MPUSOURCE_PLL1) || \ 454 ((SOURCE) == RCC_MPUSOURCE_MPUDIV)) 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_AXISS_Clock_Source RCC_AXISS_Clock_Source 460 * @{ 461 */ 462 #define RCC_AXISSOURCE_HSI 0U 463 #define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_0 464 #define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_1 465 #define RCC_AXISSOURCE_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) 466 467 #define IS_RCC_AXISSOURCE(SOURCE) (((SOURCE) == RCC_AXISSOURCE_HSI) || \ 468 ((SOURCE) == RCC_AXISSOURCE_HSE) || \ 469 ((SOURCE) == RCC_AXISSOURCE_PLL2) || \ 470 ((SOURCE) == RCC_AXISSOURCE_OFF)) 471 /** 472 * @} 473 */ 474 475 /** @defgroup RCC_MCU_Clock_Source RCC_MCU_Clock_Source 476 * @{ 477 */ 478 #define RCC_MCUSSOURCE_HSI 0U 479 #define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_0 480 #define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_1 481 #define RCC_MCUSSOURCE_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) 482 483 #define IS_RCC_MCUSSOURCE(SOURCE) (((SOURCE) == RCC_MCUSSOURCE_HSI) || \ 484 ((SOURCE) == RCC_MCUSSOURCE_HSE) || \ 485 ((SOURCE) == RCC_MCUSSOURCE_CSI) || \ 486 ((SOURCE) == RCC_MCUSSOURCE_PLL3)) 487 /** 488 * @} 489 */ 490 491 492 /** @defgroup RCC_RTC_Division_Factor RCC_RTC_Division_Factor 493 * @{ 494 */ 495 #define RCC_RTCDIV(x) (uint32_t)(x - 1U) 496 497 #define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 498 /** 499 * @} 500 */ 501 502 /** @defgroup RCC_MPU_Clock_Divider RCC_MPU_Clock_Divider 503 * @{ 504 */ 505 #define RCC_MPU_DIV_OFF 0U 506 #define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_0 507 #define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_1 508 #define RCC_MPU_DIV8 (RCC_MPCKDIVR_MPUDIV_1 | RCC_MPCKDIVR_MPUDIV_0) 509 #define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_2 510 511 #define IS_RCC_MPUDIV(DIVIDER) ( ((DIVIDER) == RCC_MPU_DIV2) || \ 512 ((DIVIDER) == RCC_MPU_DIV4) || \ 513 ((DIVIDER) == RCC_MPU_DIV8) || \ 514 ((DIVIDER) == RCC_MPU_DIV16)) 515 /** 516 * @} 517 */ 518 519 /** @defgroup RCC_AXI_Clock_Divider RCC_AXI_Clock_Divider 520 * @{ 521 */ 522 #define RCC_AXI_DIV1 0U 523 #define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_0 524 #define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_1 525 #define RCC_AXI_DIV4 (RCC_AXIDIVR_AXIDIV_0 | RCC_AXIDIVR_AXIDIV_1) 526 527 #define IS_RCC_AXIDIV(DIVIDER) (((DIVIDER) == RCC_AXI_DIV1) || \ 528 ((DIVIDER) == RCC_AXI_DIV2) || \ 529 ((DIVIDER) == RCC_AXI_DIV3) || \ 530 ((DIVIDER) == RCC_AXI_DIV4)) 531 /** 532 * @} 533 */ 534 535 /** @defgroup RCC_APB4_Clock_Divider RCC_APB4_Clock_Divider 536 * @{ 537 */ 538 #define RCC_APB4_DIV1 0U 539 #define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_0 540 #define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_1 541 #define RCC_APB4_DIV8 (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0) 542 #define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_2 543 544 #define IS_RCC_APB4DIV(DIVIDER) (((DIVIDER) == RCC_APB4_DIV1) || \ 545 ((DIVIDER) == RCC_APB4_DIV2) || \ 546 ((DIVIDER) == RCC_APB4_DIV4) || \ 547 ((DIVIDER) == RCC_APB4_DIV8) || \ 548 ((DIVIDER) == RCC_APB4_DIV16)) 549 /** 550 * @} 551 */ 552 553 /** @defgroup RCC_APB5_Clock_Divider RCC_APB5_Clock_Divider 554 * @{ 555 */ 556 #define RCC_APB5_DIV1 0U 557 #define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_0 558 #define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_1 559 #define RCC_APB5_DIV8 (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0) 560 #define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_2 561 562 #define IS_RCC_APB5DIV(DIVIDER) (((DIVIDER) == RCC_APB5_DIV1) || \ 563 ((DIVIDER) == RCC_APB5_DIV2) || \ 564 ((DIVIDER) == RCC_APB5_DIV4) || \ 565 ((DIVIDER) == RCC_APB5_DIV8) || \ 566 ((DIVIDER) == RCC_APB5_DIV16)) 567 /** 568 * @} 569 */ 570 571 /** @defgroup RCC_MCU_Clock_Divider RCC_MCU_Clock_Divider 572 * @{ 573 */ 574 #define RCC_MCU_DIV1 0U 575 #define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_0 576 #define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_1 577 #define RCC_MCU_DIV8 (RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) 578 #define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_2 579 #define RCC_MCU_DIV32 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_0) 580 #define RCC_MCU_DIV64 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1) 581 #define RCC_MCU_DIV128 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) 582 #define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_3 583 #define RCC_MCU_DIV512 (RCC_MCUDIVR_MCUDIV_3 | RCC_MCUDIVR_MCUDIV_0) 584 585 #define IS_RCC_MCUDIV(DIVIDER) (((DIVIDER) == RCC_MCU_DIV1) || \ 586 ((DIVIDER) == RCC_MCU_DIV2) || \ 587 ((DIVIDER) == RCC_MCU_DIV4) || \ 588 ((DIVIDER) == RCC_MCU_DIV8) || \ 589 ((DIVIDER) == RCC_MCU_DIV16) || \ 590 ((DIVIDER) == RCC_MCU_DIV32) || \ 591 ((DIVIDER) == RCC_MCU_DIV64) || \ 592 ((DIVIDER) == RCC_MCU_DIV128) || \ 593 ((DIVIDER) == RCC_MCU_DIV256) || \ 594 ((DIVIDER) == RCC_MCU_DIV512)) 595 /** 596 * @} 597 */ 598 599 /** @defgroup RCC_APB1_Clock_Divider RCC_APB1_Clock_Divider 600 * @{ 601 */ 602 #define RCC_APB1_DIV1 0U 603 #define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_0 604 #define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_1 605 #define RCC_APB1_DIV8 (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0) 606 #define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_2 607 608 #define IS_RCC_APB1DIV(DIVIDER) (((DIVIDER) == RCC_APB1_DIV1) || \ 609 ((DIVIDER) == RCC_APB1_DIV2) || \ 610 ((DIVIDER) == RCC_APB1_DIV4) || \ 611 ((DIVIDER) == RCC_APB1_DIV8) || \ 612 ((DIVIDER) == RCC_APB1_DIV16)) 613 /** 614 * @} 615 */ 616 617 /** @defgroup RCC_APB2_Clock_Divider RCC_APB2_Clock_Divider 618 * @{ 619 */ 620 #define RCC_APB2_DIV1 0U 621 #define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_0 622 #define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_1 623 #define RCC_APB2_DIV8 (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0) 624 #define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_2 625 626 #define IS_RCC_APB2DIV(DIVIDER) (((DIVIDER) == RCC_APB2_DIV1) || \ 627 ((DIVIDER) == RCC_APB2_DIV2) || \ 628 ((DIVIDER) == RCC_APB2_DIV4) || \ 629 ((DIVIDER) == RCC_APB2_DIV8) || \ 630 ((DIVIDER) == RCC_APB2_DIV16)) 631 /** 632 * @} 633 */ 634 635 /** @defgroup RCC_APB3_Clock_Divider RCC_APB3_Clock_Divider 636 * @{ 637 */ 638 #define RCC_APB3_DIV1 0U 639 #define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_0 640 #define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_1 641 #define RCC_APB3_DIV8 (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0) 642 #define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_2 643 644 #define IS_RCC_APB3DIV(DIVIDER) (((DIVIDER) == RCC_APB3_DIV1) || \ 645 ((DIVIDER) == RCC_APB3_DIV2) || \ 646 ((DIVIDER) == RCC_APB3_DIV4) || \ 647 ((DIVIDER) == RCC_APB3_DIV8) || \ 648 ((DIVIDER) == RCC_APB3_DIV16)) 649 /** 650 * @} 651 */ 652 653 /** @defgroup RCC_PLL_Config RCC_PLL_Config 654 * @{ 655 */ 656 #define RCC_PLL_NONE ((uint32_t)0x00000000) 657 #define RCC_PLL_OFF ((uint32_t)0x00000001) 658 #define RCC_PLL_ON ((uint32_t)0x00000002) 659 660 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 661 ((PLL) == RCC_PLL_ON)) 662 /** 663 * @} 664 */ 665 666 /** @defgroup RCC_PLL_Mode RCC_PLL_Mode 667 * @{ 668 */ 669 #define RCC_PLL_INTEGER ((uint32_t)0x00000000) 670 #define RCC_PLL_FRACTIONAL ((uint32_t)0x00000001) 671 #define RCC_PLL_SPREAD_SPECTRUM ((uint32_t)0x00000002) 672 673 #define IS_RCC_PLLMODE(MODE) (((MODE) == RCC_PLL_FRACTIONAL) || \ 674 ((MODE) == RCC_PLL_INTEGER) || \ 675 ((MODE) == RCC_PLL_SPREAD_SPECTRUM)) 676 /** 677 * @} 678 */ 679 680 681 /** @defgroup RCC_SSCG_MODE RCC_SSCG_MODE 682 * @{ 683 */ 684 #define RCC_SSCG_CENTER_SPREAD ((uint32_t)0x00000000) 685 #define RCC_SSCG_DOWN_SPREAD ((uint32_t)RCC_PLL1CSGR_SSCG_MODE) 686 687 #define IS_RCC_SSCG_MODE(MODE) (((MODE) == RCC_SSCG_CENTER_SPREAD) || \ 688 ((MODE) == RCC_SSCG_DOWN_SPREAD)) 689 /** 690 * @} 691 */ 692 693 /** @defgroup RCC_MOD_PER RCC_MOD_PER 694 * @{ 695 */ 696 #define RCC_MOD_PER_MIN ((uint32_t)0x00000001) 697 #define RCC_MOD_PER_MAX ((uint32_t)RCC_PLL1CSGR_MOD_PER) /* 8191 */ 698 699 #define IS_RCC_MOD_PER(ADJ) ((RCC_MOD_PER_MIN <= (ADJ)) && \ 700 ((ADJ) <= RCC_MOD_PER_MAX)) 701 /** 702 * @} 703 */ 704 705 /** @defgroup RCC_INC_STEP RCC_INC_STEP 706 * @{ 707 */ 708 #define RCC_INC_STEP_MIN ((uint32_t)0x00000001) 709 #define RCC_INC_STEP_MAX ((uint32_t)0x7FFF) /* 32767 */ 710 711 #define IS_RCC_INC_STEP(ADJ) ((RCC_INC_STEP_MIN <= (ADJ)) && \ 712 ((ADJ) <= RCC_INC_STEP_MAX)) 713 /** 714 * @} 715 */ 716 717 /** @defgroup RCC_RPDFN_DIS RCC_RPDFN_DIS 718 * @{ 719 */ 720 #define RCC_RPDFN_DIS_ENABLED ((uint32_t)0x00000000) 721 #define RCC_RPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_RPDFN_DIS) 722 723 #define IS_RCC_RPDFN_DIS(STATE) (((STATE) == RCC_RPDFN_DIS_DISABLED) || \ 724 ((STATE) == RCC_RPDFN_DIS_ENABLED)) 725 /** 726 * @} 727 */ 728 729 730 /** @defgroup RCC_TPDFN_DIS RCC_TPDFN_DIS 731 * @{ 732 */ 733 #define RCC_TPDFN_DIS_ENABLED ((uint32_t)0x00000000) 734 #define RCC_TPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_TPDFN_DIS) 735 736 #define IS_RCC_TPDFN_DIS(STATE) (((STATE) == RCC_TPDFN_DIS_DISABLED) || \ 737 ((STATE) == RCC_TPDFN_DIS_ENABLED)) 738 /** 739 * @} 740 */ 741 742 743 /** @defgroup RCC_PLL12_Clock_Source RCC_PLL12_Clock_Source 744 * @{ 745 */ 746 #define RCC_PLL12SOURCE_HSI 0U 747 #define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_0 748 #define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_1 749 750 #define IS_RCC_PLL12SOURCE(SOURCE) (((SOURCE) == RCC_PLL12SOURCE_HSI) || \ 751 ((SOURCE) == RCC_PLL12SOURCE_HSE) || \ 752 ((SOURCE) == RCC_PLL12SOURCE_OFF)) 753 /** 754 * @} 755 */ 756 757 758 /** @defgroup RCC_PLL3_Clock_Source RCC_PLL3_Clock_Source 759 * @{ 760 */ 761 #define RCC_PLL3SOURCE_HSI 0U 762 #define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_0 763 #define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_1 764 #define RCC_PLL3SOURCE_OFF (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0) 765 766 767 #define IS_RCC_PLL3SOURCE(SOURCE) (((SOURCE) == RCC_PLL3SOURCE_HSI) || \ 768 ((SOURCE) == RCC_PLL3SOURCE_HSE) || \ 769 ((SOURCE) == RCC_PLL3SOURCE_CSI) || \ 770 ((SOURCE) == RCC_PLL3SOURCE_OFF)) 771 772 /** 773 * @} 774 */ 775 776 777 /** @defgroup RCC_PLL4_Clock_Source RCC_PLL4_Clock_Source 778 * @{ 779 */ 780 #define RCC_PLL4SOURCE_HSI 0U 781 #define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_0 782 #define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_1 783 #define RCC_PLL4SOURCE_I2S_CKIN (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0) 784 785 786 #define IS_RCC_PLL4SOURCE(SOURCE) (((SOURCE) == RCC_PLL4SOURCE_HSI) || \ 787 ((SOURCE) == RCC_PLL4SOURCE_HSE) || \ 788 ((SOURCE) == RCC_PLL4SOURCE_CSI) || \ 789 ((SOURCE) == RCC_PLL4SOURCE_I2S_CKIN)) 790 /** 791 * @} 792 */ 793 794 /** @defgroup RCC_PLL1_MUL_DIV_Factors RCC_PLL1_MUL_DIV_Factors 795 * @{ 796 */ 797 #define IS_RCC_PLLM1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 798 /* @note DIVN limits are different depending if using integer or fractional mode */ 799 #define IS_RCC_PLLN1_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) 800 #define IS_RCC_PLLN1_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 801 #define IS_RCC_PLLP1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 802 #define IS_RCC_PLLQ1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 803 #define IS_RCC_PLLR1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 804 /** 805 * @} 806 */ 807 808 /** @defgroup RCC_PLL2_MUL_DIV_Factors RCC_PLL2_MUL_DIV_Factors 809 * @{ 810 */ 811 #define IS_RCC_PLLM2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 812 /* @note DIVN limits are different depending if using integer or fractional mode */ 813 #define IS_RCC_PLLN2_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) 814 #define IS_RCC_PLLN2_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 815 #define IS_RCC_PLLP2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 816 #define IS_RCC_PLLQ2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 817 #define IS_RCC_PLLR2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 818 /** 819 * @} 820 */ 821 822 /** @defgroup RCC_PLL3_MUL_DIV_Factors RCC_PLL3_MUL_DIV_Factors 823 * @{ 824 */ 825 #define IS_RCC_PLLM3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 826 /* @note DIVN limits are different depending if using integer or fractional mode */ 827 #define IS_RCC_PLLN3_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200)) 828 #define IS_RCC_PLLN3_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 829 #define IS_RCC_PLLP3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 830 #define IS_RCC_PLLQ3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 831 #define IS_RCC_PLLR3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 832 /** 833 * @} 834 */ 835 836 /** @defgroup RCC_PLL4_MUL_DIV_Factors RCC_PLL4_MUL_DIV_Factors 837 * @{ 838 */ 839 #define IS_RCC_PLLM4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 840 /* @note DIVN limits are different depending if using integer or fractional mode */ 841 #define IS_RCC_PLLN4_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200)) 842 #define IS_RCC_PLLN4_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 843 #define IS_RCC_PLLP4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 844 #define IS_RCC_PLLQ4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 845 #define IS_RCC_PLLR4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 846 /** 847 * @} 848 */ 849 850 /** @defgroup RCC_PLL1_Clock_Output RCC_PLL1_Clock_Output 851 * @{ 852 */ 853 #define RCC_PLL1_DIVP RCC_PLL1CR_DIVPEN 854 #define RCC_PLL1_DIVQ RCC_PLL1CR_DIVQEN 855 #define RCC_PLL1_DIVR RCC_PLL1CR_DIVREN 856 857 #define IS_RCC_PLL1CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 858 ((VALUE) == RCC_PLL1_DIVQ) || \ 859 ((VALUE) == RCC_PLL1_DIVR)) 860 /** 861 * @} 862 */ 863 864 865 /** @defgroup RCC_PLL2_Clock_Output RCC_PLL2_Clock_Output 866 * @{ 867 */ 868 #define RCC_PLL2_DIVP RCC_PLL2CR_DIVPEN 869 #define RCC_PLL2_DIVQ RCC_PLL2CR_DIVQEN 870 #define RCC_PLL2_DIVR RCC_PLL2CR_DIVREN 871 872 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2CR_DIVPEN) || \ 873 ((VALUE) == RCC_PLL2CR_DIVQEN) || \ 874 ((VALUE) == RCC_PLL2CR_DIVREN)) 875 /** 876 * @} 877 */ 878 879 /** @defgroup RCC_PLL3_Clock_Output RCC_PLL3_Clock_Output 880 * @{ 881 */ 882 883 #define RCC_PLL3_DIVP RCC_PLL3CR_DIVPEN 884 #define RCC_PLL3_DIVQ RCC_PLL3CR_DIVQEN 885 #define RCC_PLL3_DIVR RCC_PLL3CR_DIVREN 886 887 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 888 ((VALUE) == RCC_PLL3_DIVQ) || \ 889 ((VALUE) == RCC_PLL3_DIVR)) 890 /** 891 * @} 892 */ 893 894 /** @defgroup RCC_PLL4_Clock_Output RCC_PLL4_Clock_Output 895 * @{ 896 */ 897 #define RCC_PLL4_DIVP RCC_PLL4CR_DIVPEN 898 #define RCC_PLL4_DIVQ RCC_PLL4CR_DIVQEN 899 #define RCC_PLL4_DIVR RCC_PLL4CR_DIVREN 900 901 #define IS_RCC_PLL4CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL4_DIVP) || \ 902 ((VALUE) == RCC_PLL4_DIVQ) || \ 903 ((VALUE) == RCC_PLL4_DIVR)) 904 905 906 /** 907 * @} 908 */ 909 910 /** @defgroup RCC_PLL3_IF_Range RCC_PLL3_IF_Range 911 * @{ 912 */ 913 #define RCC_PLL3IFRANGE_0 0U 914 #define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_0 915 /** 916 * @} 917 */ 918 919 /** @defgroup RCC_PLL4_IF_Range RCC_PLL4_IF_Range 920 * @{ 921 */ 922 #define RCC_PLL4IFRANGE_0 0U 923 #define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_0 924 /** 925 * @} 926 */ 927 928 929 /** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source 930 * @{ 931 */ 932 #define RCC_RTCCLKSOURCE_OFF 0U /* No clock (default after backup domain reset)*/ 933 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_0 934 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_1 935 #define RCC_RTCCLKSOURCE_HSE_DIV (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0) /* HSE clock divided by RTCDIV value is used as RTC clock*/ 936 937 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_OFF) || ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ 938 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV)) 939 /** 940 * @} 941 */ 942 943 /** @defgroup RCC_Flag RCC_Flag 944 * @{ 945 */ 946 /* Flags in the OCRDYR register */ 947 #define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY ) 948 #define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY ) 949 #define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY ) 950 #define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY ) 951 #define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY ) 952 #define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST ) 953 954 /* Flags in the MPCKSELR register */ 955 #define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MPUSRCRDY ) 956 957 /* Flags in the ASSCKSELR register */ 958 #define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_AXISSRCRDY ) 959 960 /* Flags in the MSSCKSELR register */ 961 #define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_MCUSSRCRDY ) 962 963 /* Flags in the RCK12SELR register */ 964 #define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_PLL12SRCRDY ) 965 966 /* Flags in the RCK3SELR */ 967 #define RCC_FLAG_PLL3SRCRDY ( (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY) == RCC_RCK3SELR_PLL3SRCRDY ) 968 969 /* Flags in the RCK4SELR register */ 970 #define RCC_FLAG_PLL4SRCRDY ( (RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRCRDY) == RCC_RCK4SELR_PLL4SRCRDY ) 971 972 /* Flags in the TIMG1PRER register */ 973 #define RCC_FLAG_TIMG1PRERDY ( (RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRERDY) == RCC_TIMG1PRER_TIMG1PRERDY ) 974 975 /* Flags in the TIMG2PRER register */ 976 #define RCC_FLAG_TIMG2PRERDY ( (RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRERDY) == RCC_TIMG2PRER_TIMG2PRERDY ) 977 978 /* Flags in the MPCKDIVR register */ 979 #define RCC_FLAG_MPUDIVRDY ( (RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIVRDY) == RCC_MPCKDIVR_MPUDIVRDY ) 980 981 /* Flags in the AXIDIVR register */ 982 #define RCC_FLAG_AXIDIVRDY ( (RCC->AXIDIVR & RCC_AXIDIVR_AXIDIVRDY) == RCC_AXIDIVR_AXIDIVRDY ) 983 984 /* Flags in the APB4DIVR register */ 985 #define RCC_FLAG_APB4DIVRDY ( (RCC->APB4DIVR & RCC_APB4DIVR_APB4DIVRDY) == RCC_APB4DIVR_APB4DIVRDY ) 986 987 /* Flags in the APB5DIVR register */ 988 #define RCC_FLAG_APB5DIVRDY ( (RCC->APB5DIVR & RCC_APB5DIVR_APB5DIVRDY) == RCC_APB5DIVR_APB5DIVRDY ) 989 990 /* Flags in the MCUDIVR register */ 991 #define RCC_FLAG_MCUDIVRDY ( (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY) == RCC_MCUDIVR_MCUDIVRDY ) 992 993 /* Flags in the APB1DIVR register */ 994 #define RCC_FLAG_APB1DIVRDY ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY) == RCC_APB1DIVR_APB1DIVRDY ) 995 996 /* Flags in the APB2DIVR register */ 997 #define RCC_FLAG_APB2DIVRDY ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY) == RCC_APB2DIVR_APB2DIVRDY ) 998 999 /* Flags in the APB3DIVR register */ 1000 #define RCC_FLAG_APB3DIVRDY ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY) == RCC_APB3DIVR_APB3DIVRDY ) 1001 1002 /* Flags in the PLL1CR register */ 1003 #define RCC_FLAG_PLL1RDY ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) == RCC_PLL1CR_PLL1RDY ) 1004 1005 /* Flags in the PLL2CR register */ 1006 #define RCC_FLAG_PLL2RDY ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) == RCC_PLL2CR_PLL2RDY ) 1007 1008 /* Flags in the PLL3CR register */ 1009 #define RCC_FLAG_PLL3RDY ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) == RCC_PLL3CR_PLL3RDY ) 1010 1011 /* Flags in the PLL4CR register */ 1012 #define RCC_FLAG_PLL4RDY ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) == RCC_PLL4CR_PLL4RDY ) 1013 1014 /* Flags in the DDRCKSELR register */ 1015 #define RCC_FLAG_DDRPHYCSRCRDY ((RCC->DDRCKSELR & RCC_DDRCKSELR_DDRPHYCSRCRDY) == RCC_DDRCKSELR_DDRPHYCSRCRDY ) 1016 1017 /* Flags in the BDCR register */ 1018 #define RCC_FLAG_LSERDY ((RCC->BDCR & RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY ) 1019 1020 /* Flags in the RDLSICR register */ 1021 #define RCC_FLAG_LSIRDY ((RCC->RDLSICR & RCC_RDLSICR_LSIRDY) == RCC_RDLSICR_LSIRDY ) 1022 1023 #if defined(CORE_CA7) 1024 /* Flags in the RCC_MP_RSTSCLRR */ 1025 #define RCC_MASK_ALL_RESET_FLAGS (0x00001BDFU) 1026 #define RCC_FLAG_PORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PORRSTF) == RCC_MP_RSTSCLRR_PORRSTF) 1027 #define RCC_FLAG_BORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_BORRSTF) == RCC_MP_RSTSCLRR_BORRSTF) 1028 #define RCC_FLAG_PADRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PADRSTF) == RCC_MP_RSTSCLRR_PADRSTF) 1029 #define RCC_FLAG_HCSSRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_HCSSRSTF) == RCC_MP_RSTSCLRR_HCSSRSTF) 1030 #define RCC_FLAG_VCORERST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_VCORERSTF) == RCC_MP_RSTSCLRR_VCORERSTF) 1031 #define RCC_FLAG_MPSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPSYSRSTF) == RCC_MP_RSTSCLRR_MPSYSRSTF) 1032 #define RCC_FLAG_MCSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MCSYSRSTF) == RCC_MP_RSTSCLRR_MCSYSRSTF) 1033 #define RCC_FLAG_IWDG1RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG1RSTF) == RCC_MP_RSTSCLRR_IWDG1RSTF) 1034 #define RCC_FLAG_IWDG2RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG2RSTF) == RCC_MP_RSTSCLRR_IWDG2RSTF) 1035 #define RCC_FLAG_STDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_STDBYRSTF) == RCC_MP_RSTSCLRR_STDBYRSTF) 1036 #define RCC_FLAG_CSTDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_CSTDBYRSTF) == RCC_MP_RSTSCLRR_CSTDBYRSTF) 1037 #define RCC_FLAG_MPUP0RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP0RSTF) == RCC_MP_RSTSCLRR_MPUP0RSTF) 1038 #define RCC_FLAG_MPUP1RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP1RSTF) == RCC_MP_RSTSCLRR_MPUP1RSTF) 1039 #elif defined(CORE_CM4) 1040 /* Flags in the RCC_MC_RSTSCLRR */ 1041 #define RCC_MASK_ALL_RESET_FLAGS (0x000007FFU) 1042 #define RCC_FLAG_PORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PORRSTF) == RCC_MC_RSTSCLRR_PORRSTF) 1043 #define RCC_FLAG_BORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_BORRSTF) == RCC_MC_RSTSCLRR_BORRSTF) 1044 #define RCC_FLAG_PADRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PADRSTF) == RCC_MC_RSTSCLRR_PADRSTF) 1045 #define RCC_FLAG_HCSSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_HCSSRSTF) == RCC_MC_RSTSCLRR_HCSSRSTF) 1046 #define RCC_FLAG_VCORERST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_VCORERSTF) == RCC_MC_RSTSCLRR_VCORERSTF) 1047 #define RCC_FLAG_MCURST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCURSTF) == RCC_MC_RSTSCLRR_MCURSTF) 1048 #define RCC_FLAG_MPSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MPSYSRSTF) == RCC_MC_RSTSCLRR_MPSYSRSTF) 1049 #define RCC_FLAG_MCSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCSYSRSTF) == RCC_MC_RSTSCLRR_MCSYSRSTF) 1050 #define RCC_FLAG_IWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG1RSTF) == RCC_MC_RSTSCLRR_IWDG1RSTF) 1051 #define RCC_FLAG_IWDG2RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG2RSTF) == RCC_MC_RSTSCLRR_IWDG2RSTF) 1052 #define RCC_FLAG_WWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_WWDG1RSTF) == RCC_MC_RSTSCLRR_WWDG1RSTF) 1053 #endif 1054 1055 /** @brief Clear all the reset flags 1056 * @note Writing a '1' clears the corresponding bit to '0' 1057 */ 1058 #if defined(CORE_CA7) 1059 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MP_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS) 1060 #elif defined(CORE_CM4) 1061 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MC_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS) 1062 #endif /* CORE_CA7 */ 1063 1064 #if defined(CORE_CA7) 1065 /** @brief Check RCC flag is set or not. 1066 * @param __FLAG__: specifies the flag to check. 1067 * This parameter can be one of the following values: 1068 * @arg RCC_FLAG_PORRST 1069 * @arg RCC_FLAG_BORRST 1070 * @arg RCC_FLAG_PADRST 1071 * @arg RCC_FLAG_HCSSRST 1072 * @arg RCC_FLAG_VCORERST 1073 * @arg RCC_FLAG_MPSYSRSTF 1074 * @arg RCC_FLAG_MCSYSRSTF 1075 * @arg RCC_FLAG_IWDG1RST 1076 * @arg RCC_FLAG_IWDG2RST 1077 * @arg RCC_FLAG_STDBYRSTF 1078 * @arg RCC_FLAG_CSTDBYRSTF 1079 * @arg RCC_FLAG_MPUP0RSTF 1080 * @arg RCC_FLAG_MPUP1RSTF 1081 * @retval The state of __FLAG__ (TRUE or FALSE). 1082 */ 1083 #elif defined(CORE_CM4) 1084 /** @brief Check RCC flag is set or not. 1085 * @param __FLAG__: specifies the flag to check. 1086 * This parameter can be one of the following values: 1087 * @arg RCC_FLAG_PORRST 1088 * @arg RCC_FLAG_BORRST 1089 * @arg RCC_FLAG_PADRST 1090 * @arg RCC_FLAG_HCSSRST 1091 * @arg RCC_FLAG_VCORERST 1092 * @arg RCC_FLAG_MCURST 1093 * @arg RCC_FLAG_MPSYSRST 1094 * @arg RCC_FLAG_MCSYSRST 1095 * @arg RCC_FLAG_IWDG1RST 1096 * @arg RCC_FLAG_IWDG2RST 1097 * @arg RCC_FLAG_WWDG1RST 1098 * @retval The state of __FLAG__ (TRUE or FALSE). 1099 */ 1100 #endif /* CORE_CA7 */ 1101 #define __HAL_RCC_GET_FLAG(__FLAG__) ((uint32_t)(__FLAG__ ? 1:0 )) 1102 /** 1103 * @} 1104 */ 1105 1106 /** @defgroup RCC_Calibration RCC_Calibration limits 1107 * @{ 1108 */ 1109 /** RCC_Calibration limits*/ 1110 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 1111 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 1112 /** 1113 * @} 1114 */ 1115 1116 /** @defgroup RCC_LSEDrive_Config RCC_LSEDrive_Config 1117 * @{ 1118 */ 1119 #define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ 1120 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 1121 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 1122 #define RCC_LSEDRIVE_HIGH (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0) /*!< LSE high drive capability */ 1123 1124 #define IS_RCC_LSEDRIVE(VALUE) (((VALUE) == RCC_LSEDRIVE_LOW) || ((VALUE) == RCC_LSEDRIVE_MEDIUMLOW) || \ 1125 ((VALUE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((VALUE) == RCC_LSEDRIVE_HIGH)) 1126 /** 1127 * @} 1128 */ 1129 1130 1131 /** @defgroup RCC_Interrupt RCC_Interrupt 1132 * @{ 1133 */ 1134 #ifdef CORE_CM4 1135 #define RCC_IT_LSIRDY RCC_MC_CIFR_LSIRDYF 1136 #define RCC_IT_LSERDY RCC_MC_CIFR_LSERDYF 1137 #define RCC_IT_HSIRDY RCC_MC_CIFR_HSIRDYF 1138 #define RCC_IT_HSERDY RCC_MC_CIFR_HSERDYF 1139 #define RCC_IT_CSIRDY RCC_MC_CIFR_CSIRDYF 1140 #define RCC_IT_PLLRDY RCC_MC_CIFR_PLL1DYF 1141 #define RCC_IT_PLL2RDY RCC_MC_CIFR_PLL2DYF 1142 #define RCC_IT_PLL3RDY RCC_MC_CIFR_PLL3DYF 1143 #define RCC_IT_PLL4RDY RCC_MC_CIFR_PLL4DYF 1144 #define RCC_IT_LSECSS RCC_MC_CIFR_LSECSSF 1145 #define RCC_IT_WKUP RCC_MC_CIFR_WKUPF 1146 #endif /* CORE_CM4*/ 1147 1148 #ifdef CORE_CA7 1149 #define RCC_IT_LSIRDY RCC_MP_CIFR_LSIRDYF 1150 #define RCC_IT_LSERDY RCC_MP_CIFR_LSERDYF 1151 #define RCC_IT_HSIRDY RCC_MP_CIFR_HSIRDYF 1152 #define RCC_IT_HSERDY RCC_MP_CIFR_HSERDYF 1153 #define RCC_IT_CSIRDY RCC_MP_CIFR_CSIRDYF 1154 #define RCC_IT_PLLRDY RCC_MP_CIFR_PLL1DYF 1155 #define RCC_IT_PLL2RDY RCC_MP_CIFR_PLL2DYF 1156 #define RCC_IT_PLL3RDY RCC_MP_CIFR_PLL3DYF 1157 #define RCC_IT_PLL4RDY RCC_MP_CIFR_PLL4DYF 1158 #define RCC_IT_LSECSS RCC_MP_CIFR_LSECSSF 1159 #define RCC_IT_WKUP RCC_MP_CIFR_WKUPF 1160 #endif /* CORE_CA7 */ 1161 1162 #define RCC_IT_ALL (RCC_IT_LSIRDY | RCC_IT_LSERDY | RCC_IT_HSIRDY | \ 1163 RCC_IT_HSERDY | RCC_IT_CSIRDY | RCC_IT_PLLRDY | \ 1164 RCC_IT_PLL2RDY | RCC_IT_PLL3RDY | RCC_IT_PLL4RDY | \ 1165 RCC_IT_LSECSS | RCC_IT_WKUP) 1166 1167 #define IS_RCC_IT(VALUE) (((VALUE) == RCC_IT_LSIRDY) || ((VALUE) == RCC_IT_LSERDY) || \ 1168 ((VALUE) == RCC_IT_HSIRDY) || ((VALUE) == RCC_IT_HSERDY) || \ 1169 ((VALUE) == RCC_IT_CSIRDY) || ((VALUE) == RCC_IT_PLLRDY) || \ 1170 ((VALUE) == RCC_IT_PLL2RDY) || ((VALUE) == RCC_IT_PLL3RDY) || \ 1171 ((VALUE) == RCC_IT_PLL4RDY) || ((VALUE) == RCC_IT_LSECSS) || \ 1172 ((VALUE) == RCC_IT_WKUP)) 1173 1174 /** 1175 * @} 1176 */ 1177 1178 /** 1179 * @} 1180 */ 1181 1182 /* Exported macros -----------------------------------------------------------*/ 1183 1184 /** @defgroup RCC_Exported_Macros RCC_Exported_Macros 1185 * @{ 1186 */ 1187 /** @brief Force or release the APB1 peripheral reset */ 1188 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTSETR = 0xADEFDBFFU) 1189 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM2RST) 1190 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM3RST) 1191 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM4RST) 1192 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM5RST) 1193 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM6RST) 1194 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM7RST) 1195 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM12RST) 1196 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM13RST) 1197 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM14RST) 1198 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_LPTIM1RST) 1199 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI2RST) 1200 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI3RST) 1201 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART2RST) 1202 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART3RST) 1203 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART4RST) 1204 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART5RST) 1205 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART7RST) 1206 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART8RST) 1207 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C1RST) 1208 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C2RST) 1209 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C3RST) 1210 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C5RST) 1211 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPDIFRST) 1212 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_CECRST) 1213 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_DAC12RST) 1214 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_MDIOSRST) 1215 1216 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTCLRR = 0xADEFDBFFU) 1217 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM2RST) 1218 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM3RST) 1219 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM4RST) 1220 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM5RST) 1221 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM6RST) 1222 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM7RST) 1223 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM12RST) 1224 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM13RST) 1225 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM14RST) 1226 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_LPTIM1RST) 1227 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI2RST) 1228 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI3RST) 1229 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART2RST) 1230 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART3RST) 1231 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART4RST) 1232 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART5RST) 1233 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART7RST) 1234 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART8RST) 1235 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C1RST) 1236 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C2RST) 1237 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C3RST) 1238 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C5RST) 1239 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPDIFRST) 1240 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_CECRST) 1241 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_DAC12RST) 1242 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_MDIOSRST) 1243 1244 /** @brief Force or release the APB2 peripheral reset. */ 1245 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTSETR = 0x117271FU) 1246 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM1RST) 1247 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM8RST) 1248 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM15RST) 1249 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM16RST) 1250 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM17RST) 1251 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI1RST) 1252 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI4RST) 1253 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI5RST) 1254 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_USART6RST) 1255 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI1RST) 1256 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI2RST) 1257 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI3RST) 1258 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_DFSDMRST) 1259 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_FDCANRST) 1260 1261 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTCLRR = 0x117271FU) 1262 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM1RST) 1263 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM8RST) 1264 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM15RST) 1265 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM16RST) 1266 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM17RST) 1267 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI1RST) 1268 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI4RST) 1269 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI5RST) 1270 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_USART6RST) 1271 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI1RST) 1272 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI2RST) 1273 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI3RST) 1274 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_DFSDMRST) 1275 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_FDCANRST) 1276 1277 /** @brief Force or release the APB3 peripheral reset. */ 1278 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTSETR = 0x0003290FU) 1279 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM2RST) 1280 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM3RST) 1281 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM4RST) 1282 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM5RST) 1283 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SAI4RST) 1284 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST) 1285 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST) 1286 #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_DTSRST) 1287 1288 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU) 1289 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST) 1290 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM3RST) 1291 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM4RST) 1292 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM5RST) 1293 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SAI4RST) 1294 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST) 1295 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST) 1296 #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_DTSRST) 1297 1298 /** @brief Force or release the AHB2 peripheral reset. */ 1299 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U) 1300 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA1RST) 1301 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA2RST) 1302 #define __HAL_RCC_DMAMUX_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMAMUXRST) 1303 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_ADC12RST) 1304 #define __HAL_RCC_USBO_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_USBORST) 1305 #define __HAL_RCC_SDMMC3_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_SDMMC3RST) 1306 1307 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTCLRR = 0x00010127U) 1308 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA1RST) 1309 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA2RST) 1310 #define __HAL_RCC_DMAMUX_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMAMUXRST) 1311 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_ADC12RST) 1312 #define __HAL_RCC_USBO_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_USBORST) 1313 #define __HAL_RCC_SDMMC3_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_SDMMC3RST) 1314 1315 /** @brief Force or release the AHB3 peripheral reset. */ 1316 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_DCMIRST) 1317 #if defined(CRYP2) 1318 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018F1U) 1319 #define __HAL_RCC_CRYP2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRYP2RST) 1320 #else 1321 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018E1U) 1322 #endif /* CRYP2 */ 1323 #define __HAL_RCC_HASH2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HASH2RST) 1324 #define __HAL_RCC_RNG2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_RNG2RST) 1325 #define __HAL_RCC_CRC2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRC2RST) 1326 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HSEMRST) 1327 #define __HAL_RCC_IPCC_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_IPCCRST) 1328 1329 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_DCMIRST) 1330 #if defined(CRYP2) 1331 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018F1U) 1332 #define __HAL_RCC_CRYP2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRYP2RST) 1333 #else 1334 #define __HAL_RCC_AHB3_REALEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018E1U) 1335 #endif /* CRYP2 */ 1336 #define __HAL_RCC_HASH2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HASH2RST) 1337 #define __HAL_RCC_RNG2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_RNG2RST) 1338 #define __HAL_RCC_CRC2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRC2RST) 1339 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HSEMRST) 1340 #define __HAL_RCC_IPCC_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_IPCCRST) 1341 1342 /** @brief Force or release the AHB4 peripheral reset. */ 1343 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTSETR = 0x000007FFU) 1344 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOARST) 1345 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOBRST) 1346 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOCRST) 1347 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIODRST) 1348 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOERST) 1349 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOFRST) 1350 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOGRST) 1351 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOHRST) 1352 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOIRST) 1353 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOJRST) 1354 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOKRST) 1355 1356 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTCLRR = 0x000007FFU) 1357 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOARST) 1358 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOBRST) 1359 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOCRST) 1360 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIODRST) 1361 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOERST) 1362 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOFRST) 1363 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOGRST) 1364 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOHRST) 1365 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOIRST) 1366 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOJRST) 1367 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOKRST) 1368 1369 /** @brief Force or release the APB4 peripheral reset. */ 1370 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTSETR = 0x00010111U) 1371 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_LTDCRST) 1372 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DSIRST) 1373 #define __HAL_RCC_DDRPERFM_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DDRPERFMRST) 1374 #define __HAL_RCC_USBPHY_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_USBPHYRST) 1375 1376 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTCLRR = 0x00010111U) 1377 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_LTDCRST) 1378 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DSIRST) 1379 #define __HAL_RCC_DDRPERFM_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DDRPERFMRST) 1380 #define __HAL_RCC_USBPHY_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_USBPHYRST) 1381 1382 /** @brief Force or release the APB5 peripheral reset. */ 1383 /** @note Note that when the secure mode is enabled, only secure accesses can 1384 * reset the peripherals connected to APB5. 1385 */ 1386 #define __HAL_RCC_APB5_FORCE_RESET() (RCC->APB5RSTSETR = 0x0010001DU) 1387 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_SPI6RST) 1388 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C4RST) 1389 #define __HAL_RCC_I2C6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C6RST) 1390 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_USART1RST) 1391 #define __HAL_RCC_STGEN_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_STGENRST) 1392 1393 #define __HAL_RCC_APB5_RELEASE_RESET() (RCC->APB5RSTCLRR = 0x0010001DU) 1394 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_SPI6RST) 1395 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C4RST) 1396 #define __HAL_RCC_I2C6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C6RST) 1397 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_USART1RST) 1398 #define __HAL_RCC_STGEN_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_STGENRST) 1399 1400 /** @brief Force or release the AHB5 peripheral reset. */ 1401 #define __HAL_RCC_GPIOZ_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_GPIOZRST) 1402 #if defined(CRYP1) 1403 #define __HAL_RCC_CRYP1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_CRYP1RST) 1404 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010071U) 1405 #else 1406 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010061U) 1407 #endif /* CRYP1 */ 1408 #define __HAL_RCC_HASH1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_HASH1RST) 1409 #define __HAL_RCC_RNG1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_RNG1RST) 1410 #define __HAL_RCC_AXIMC_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_AXIMCRST) 1411 1412 #define __HAL_RCC_GPIOZ_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_GPIOZRST) 1413 #if defined(CRYP1) 1414 #define __HAL_RCC_CRYP1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_CRYP1RST) 1415 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010071U) 1416 #else 1417 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010061U) 1418 #endif /* CRYP1 */ 1419 #define __HAL_RCC_HASH1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_HASH1RST) 1420 #define __HAL_RCC_RNG1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_RNG1RST) 1421 #define __HAL_RCC_AXIMC_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_AXIMCRST) 1422 1423 /** @brief Force or release the AHB6 peripheral reset. */ 1424 #define __HAL_RCC_AHB6_FORCE_RESET() (RCC->AHB6RSTSETR = 0x01135420U) 1425 #define __HAL_RCC_GPU_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_GPURST) 1426 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_ETHMACRST) 1427 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_FMCRST) 1428 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_QSPIRST) 1429 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC1RST) 1430 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC2RST) 1431 #define __HAL_RCC_CRC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_CRC1RST) 1432 #define __HAL_RCC_USBH_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_USBHRST) 1433 1434 /** @note __HAL_RCC_GPU_RELEASE_RESET does not exist as GPU reset process may 1435 * take several clock cycles, for that purpose, the application can 1436 * read-back the reset bit RCC_AHB6RSTSETR_GPURST in order to check if 1437 * the reset process is on-going or completed after setting 1438 * RCC_AHB6RSTSETR_GPURST 1439 */ 1440 #define __HAL_RCC_AHB6_RELEASE_RESET() (RCC->AHB6RSTCLRR = 0x01135400U) 1441 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_ETHMACRST) 1442 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_FMCRST) 1443 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_QSPIRST) 1444 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC1RST) 1445 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC2RST) 1446 #define __HAL_RCC_CRC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_CRC1RST) 1447 #define __HAL_RCC_USBH_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_USBHRST) 1448 1449 /** @brief Force or release the TZAHB6 peripheral reset. */ 1450 #define __HAL_RCC_TZAHB6_FORCE_RESET() (RCC->TZAHB6RSTSETR = 0x00000001U) 1451 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->TZAHB6RSTSETR = RCC_TZAHB6RSTSETR_MDMARST) 1452 1453 #define __HAL_RCC_TZAHB6_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = 0x00000001U) 1454 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = RCC_TZAHB6RSTCLRR_MDMARST) 1455 1456 #ifdef CORE_CA7 1457 /** @brief Enable or disable the APB1 peripheral clock. 1458 * @note After reset, the peripheral clock (used for registers read/write access) 1459 * is disabled and the application software has to enable this clock before 1460 * using it. It shall be used to allocate a peripheral to the MPU. 1461 */ 1462 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM2EN) 1463 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM3EN) 1464 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM4EN) 1465 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM5EN) 1466 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM6EN) 1467 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM7EN) 1468 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM12EN) 1469 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM13EN) 1470 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM14EN) 1471 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_LPTIM1EN) 1472 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI2EN) 1473 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI3EN) 1474 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART2EN) 1475 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART3EN) 1476 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART4EN) 1477 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART5EN) 1478 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART7EN) 1479 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART8EN) 1480 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C1EN) 1481 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C2EN) 1482 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C3EN) 1483 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C5EN) 1484 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPDIFEN) 1485 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_CECEN) 1486 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_DAC12EN) 1487 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_MDIOSEN) 1488 1489 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM2EN) 1490 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM3EN) 1491 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM4EN) 1492 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM5EN) 1493 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM6EN) 1494 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM7EN) 1495 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM12EN) 1496 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM13EN) 1497 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM14EN) 1498 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_LPTIM1EN) 1499 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI2EN) 1500 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI3EN) 1501 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART2EN) 1502 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART3EN) 1503 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN) 1504 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN) 1505 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART5EN) 1506 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART7EN) 1507 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART8EN) 1508 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C1EN) 1509 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C2EN) 1510 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C3EN) 1511 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C5EN) 1512 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPDIFEN) 1513 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_CECEN) 1514 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_DAC12EN) 1515 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_MDIOSEN) 1516 1517 /** @brief Enable or disable the APB2 peripheral clock. 1518 * @note After reset, the peripheral clock (used for registers read/write access) 1519 * is disabled and the application software has to enable this clock before 1520 * using it. It shall be used to allocate a peripheral to the MPU. 1521 */ 1522 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM1EN) 1523 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM8EN) 1524 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM15EN) 1525 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM16EN) 1526 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM17EN) 1527 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI1EN) 1528 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI4EN) 1529 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI5EN) 1530 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_USART6EN) 1531 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI1EN) 1532 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI2EN) 1533 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI3EN) 1534 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_DFSDMEN) 1535 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_ADFSDMEN) 1536 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_FDCANEN) 1537 1538 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM1EN) 1539 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM8EN) 1540 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM15EN) 1541 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM16EN) 1542 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM17EN) 1543 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI1EN) 1544 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI4EN) 1545 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI5EN) 1546 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_USART6EN) 1547 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI1EN) 1548 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI2EN) 1549 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI3EN) 1550 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_DFSDMEN) 1551 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_ADFSDMEN) 1552 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_FDCANEN) 1553 1554 /** @brief Enable or disable the APB3 peripheral clock. 1555 * @note After reset, the peripheral clock (used for registers read/write access) 1556 * is disabled and the application software has to enable this clock before 1557 * using it. It shall be used to allocate a peripheral to the MPU. 1558 */ 1559 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM2EN) 1560 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM3EN) 1561 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM4EN) 1562 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM5EN) 1563 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SAI4EN) 1564 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SYSCFGEN) 1565 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_VREFEN) 1566 #define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_DTSEN) 1567 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_HDPEN) 1568 1569 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM2EN) 1570 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM3EN) 1571 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM4EN) 1572 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM5EN) 1573 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SAI4EN) 1574 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SYSCFGEN) 1575 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_VREFEN) 1576 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_DTSEN) 1577 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_HDPEN) 1578 1579 /** @brief Enable or disable the APB4 peripheral clock. 1580 * @note After reset, the peripheral clock (used for registers read/write access) 1581 * is disabled and the application software has to enable this clock before 1582 * using it. It shall be used to allocate a peripheral to the MPU. 1583 */ 1584 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_LTDCEN) 1585 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DSIEN) 1586 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DDRPERFMEN) 1587 #define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN) 1588 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_USBPHYEN) 1589 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_STGENROEN) 1590 1591 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_LTDCEN) 1592 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DSIEN) 1593 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DDRPERFMEN) 1594 #define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN) 1595 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_USBPHYEN) 1596 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_STGENROEN) 1597 1598 /** @brief Enable or disable the APB5 peripheral clock. 1599 * @note After reset, the peripheral clock (used for registers read/write access) 1600 * is disabled and the application software has to enable this clock before 1601 * using it. It shall be used to allocate a peripheral to the MPU. 1602 */ 1603 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_SPI6EN) 1604 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C4EN) 1605 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C6EN) 1606 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_USART1EN) 1607 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_RTCAPBEN) 1608 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC1EN) 1609 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC2EN) 1610 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZPCEN) 1611 #define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN) 1612 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_BSECEN) 1613 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_STGENEN) 1614 1615 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_SPI6EN) 1616 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C4EN) 1617 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C6EN) 1618 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_USART1EN) 1619 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_RTCAPBEN) 1620 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC1EN) 1621 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC2EN) 1622 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZPCEN) 1623 #define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN) 1624 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_BSECEN) 1625 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_STGENEN) 1626 1627 /** @brief Enable or disable the AHB5 peripheral clock. 1628 * @note After reset, the peripheral clock (used for registers read/write access) 1629 * is disabled and the application software has to enable this clock before 1630 * using it. It shall be used to allocate a peripheral to the MPU. 1631 */ 1632 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_GPIOZEN) 1633 #if defined(CRYP1) 1634 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_CRYP1EN) 1635 #endif 1636 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_HASH1EN) 1637 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_RNG1EN) 1638 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_BKPSRAMEN) 1639 1640 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN) 1641 #if defined(CRYP1) 1642 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN) 1643 #endif 1644 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN) 1645 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN) 1646 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN) 1647 1648 /** @brief Enable or disable the AHB6 peripheral clock. 1649 * @note After reset, the peripheral clock (used for registers read/write access) 1650 * is disabled and the application software has to enable this clock before 1651 * using it. It shall be used to allocate a peripheral to the MPU. 1652 */ 1653 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_MDMAEN) 1654 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_GPUEN) 1655 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHCKEN) 1656 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHTXEN) 1657 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHRXEN) 1658 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHMACEN) 1659 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_FMCEN) 1660 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_QSPIEN) 1661 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC1EN) 1662 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC2EN) 1663 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_CRC1EN) 1664 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_USBHEN) 1665 1666 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_MDMAEN) 1667 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_GPUEN) 1668 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHCKEN) 1669 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHTXEN) 1670 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHRXEN) 1671 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHMACEN) 1672 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_FMCEN) 1673 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_QSPIEN) 1674 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC1EN) 1675 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC2EN) 1676 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_CRC1EN) 1677 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_USBHEN) 1678 1679 /** @brief Enable or disable the AHB2 peripheral clock. 1680 * @note After reset, the peripheral clock (used for registers read/write access) 1681 * is disabled and the application software has to enable this clock before 1682 * using it. It shall be used to allocate a peripheral to the MPU. 1683 */ 1684 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA1EN) 1685 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA2EN) 1686 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMAMUXEN) 1687 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_ADC12EN) 1688 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_USBOEN) 1689 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_SDMMC3EN) 1690 1691 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA1EN) 1692 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA2EN) 1693 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMAMUXEN) 1694 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_ADC12EN) 1695 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_USBOEN) 1696 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_SDMMC3EN) 1697 1698 /** @brief Enable or disable the AHB3 peripheral clock. 1699 * @note After reset, the peripheral clock (used for registers read/write access) 1700 * is disabled and the application software has to enable this clock before 1701 * using it. It shall be used to allocate a peripheral to the MPU. 1702 */ 1703 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_DCMIEN) 1704 #if defined(CRYP2) 1705 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRYP2EN) 1706 #endif 1707 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HASH2EN) 1708 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_RNG2EN) 1709 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRC2EN) 1710 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HSEMEN) 1711 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_IPCCEN) 1712 1713 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_DCMIEN) 1714 #if defined(CRYP2) 1715 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRYP2EN) 1716 #endif 1717 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HASH2EN) 1718 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_RNG2EN) 1719 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRC2EN) 1720 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HSEMEN) 1721 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_IPCCEN) 1722 1723 /** @brief Enable or disable the AHB4 peripheral clock. 1724 * @note After reset, the peripheral clock (used for registers read/write access) 1725 * is disabled and the application software has to enable this clock before 1726 * using it. It shall be used to allocate a peripheral to the MPU. 1727 */ 1728 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOAEN) 1729 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOBEN) 1730 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOCEN) 1731 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIODEN) 1732 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOEEN) 1733 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOFEN) 1734 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOGEN) 1735 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOHEN) 1736 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOIEN) 1737 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOJEN) 1738 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOKEN) 1739 1740 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOAEN) 1741 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOBEN) 1742 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOCEN) 1743 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIODEN) 1744 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOEEN) 1745 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOFEN) 1746 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOGEN) 1747 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOHEN) 1748 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOIEN) 1749 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOJEN) 1750 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOKEN) 1751 1752 1753 /** @brief Enable or disable the MLAHB peripheral clock. 1754 * @note After reset, the peripheral clock (used for registers read/write access) 1755 * is disabled and the application software has to enable this clock before 1756 * using it. It shall be used to allocate a peripheral to the MPU. 1757 */ 1758 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MP_MLAHBENSETR_RETRAMEN) 1759 1760 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MP_MLAHBENCLRR_RETRAMEN) 1761 1762 /** @brief MCU reset 1763 * @note It generates a reset of the MCU core 1764 * MCURST bit is set by software, cleared by hardware when the reset 1765 * command is executed. 1766 */ 1767 #define __HAL_RCC_MCU_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MCURST) 1768 1769 /** @brief System reset 1770 * @note It generates a system reset 1771 * MPSYSRST bit is set by software, cleared by hardware. 1772 */ 1773 #define __HAL_RCC_SYS_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MPSYSRST) 1774 1775 1776 1777 1778 /** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode. 1779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1780 * power consumption. 1781 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1782 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1783 */ 1784 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM2LPEN) 1785 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM3LPEN) 1786 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM4LPEN) 1787 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM5LPEN) 1788 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM6LPEN) 1789 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM7LPEN) 1790 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM12LPEN) 1791 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM13LPEN) 1792 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM14LPEN) 1793 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_LPTIM1LPEN) 1794 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI2LPEN) 1795 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI3LPEN) 1796 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART2LPEN) 1797 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART3LPEN) 1798 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART4LPEN) 1799 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART5LPEN) 1800 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART7LPEN) 1801 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART8LPEN) 1802 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C1LPEN) 1803 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C2LPEN) 1804 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C3LPEN) 1805 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C5LPEN) 1806 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPDIFLPEN) 1807 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_CECLPEN) 1808 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_DAC12LPEN) 1809 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_MDIOSLPEN) 1810 1811 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM2LPEN) 1812 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM3LPEN) 1813 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM4LPEN) 1814 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM5LPEN) 1815 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM6LPEN) 1816 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM7LPEN) 1817 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM12LPEN) 1818 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM13LPEN) 1819 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM14LPEN) 1820 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_LPTIM1LPEN) 1821 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI2LPEN) 1822 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI3LPEN) 1823 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART2LPEN) 1824 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART3LPEN) 1825 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART4LPEN) 1826 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART5LPEN) 1827 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART7LPEN) 1828 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART8LPEN) 1829 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C1LPEN) 1830 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C2LPEN) 1831 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C3LPEN) 1832 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C5LPEN) 1833 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPDIFLPEN) 1834 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_CECLPEN) 1835 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_DAC12LPEN) 1836 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_MDIOSLPEN) 1837 1838 1839 /** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode. 1840 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1841 * power consumption. 1842 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1843 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1844 */ 1845 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM1LPEN) 1846 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM8LPEN) 1847 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM15LPEN) 1848 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM16LPEN) 1849 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM17LPEN) 1850 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI1LPEN) 1851 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI4LPEN) 1852 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI5LPEN) 1853 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_USART6LPEN) 1854 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI1LPEN) 1855 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI2LPEN) 1856 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI3LPEN) 1857 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_DFSDMLPEN) 1858 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_ADFSDMLPEN) 1859 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_FDCANLPEN) 1860 1861 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM1LPEN) 1862 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM8LPEN) 1863 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM15LPEN) 1864 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM16LPEN) 1865 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM17LPEN) 1866 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI1LPEN) 1867 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI4LPEN) 1868 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI5LPEN) 1869 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_USART6LPEN) 1870 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI1LPEN) 1871 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI2LPEN) 1872 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI3LPEN) 1873 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_DFSDMLPEN) 1874 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_ADFSDMLPEN) 1875 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_FDCANLPEN) 1876 1877 1878 /** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode. 1879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1880 * power consumption. 1881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1882 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1883 */ 1884 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM2LPEN) 1885 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM3LPEN) 1886 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM4LPEN) 1887 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM5LPEN) 1888 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SAI4LPEN) 1889 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SYSCFGLPEN) 1890 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_VREFLPEN) 1891 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_DTSLPEN) 1892 1893 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM2LPEN) 1894 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM3LPEN) 1895 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM4LPEN) 1896 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM5LPEN) 1897 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SAI4LPEN) 1898 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SYSCFGLPEN) 1899 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_VREFLPEN) 1900 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_DTSLPEN) 1901 1902 /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. 1903 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1904 * power consumption. 1905 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1906 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1907 */ 1908 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_LTDCLPEN) 1909 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DSILPEN) 1910 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DDRPERFMLPEN) 1911 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2APBLPEN) 1912 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_USBPHYLPEN) 1913 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROLPEN) 1914 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROSTPEN) 1915 1916 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_LTDCLPEN) 1917 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DSILPEN) 1918 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DDRPERFMLPEN) 1919 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2APBLPEN) 1920 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_USBPHYLPEN) 1921 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROLPEN) 1922 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROSTPEN) 1923 1924 /** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode. 1925 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1926 * power consumption. 1927 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1928 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1929 */ 1930 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_SPI6LPEN) 1931 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C4LPEN) 1932 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C6LPEN) 1933 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_USART1LPEN) 1934 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_RTCAPBLPEN) 1935 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC1LPEN) 1936 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC2LPEN) 1937 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZPCLPEN) 1938 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_BSECLPEN) 1939 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_STGENLPEN) 1940 1941 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_SPI6LPEN) 1942 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C4LPEN) 1943 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C6LPEN) 1944 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_USART1LPEN) 1945 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_RTCAPBLPEN) 1946 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC1LPEN) 1947 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC2LPEN) 1948 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZPCLPEN) 1949 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_BSECLPEN) 1950 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_STGENLPEN) 1951 1952 1953 /** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode. 1954 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1955 * power consumption. 1956 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1957 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1958 */ 1959 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_GPIOZLPEN) 1960 #if defined(CRYP1) 1961 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_CRYP1LPEN) 1962 #endif 1963 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_HASH1LPEN) 1964 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_RNG1LPEN) 1965 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_BKPSRAMLPEN) 1966 1967 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_GPIOZLPEN) 1968 #if defined(CRYP1) 1969 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_CRYP1LPEN) 1970 #endif 1971 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_HASH1LPEN) 1972 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_RNG1LPEN) 1973 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN) 1974 1975 1976 /** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode. 1977 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1978 * power consumption. 1979 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1980 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1981 */ 1982 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_MDMALPEN) 1983 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_GPULPEN) 1984 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHCKLPEN) 1985 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHTXLPEN) 1986 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHRXLPEN) 1987 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHMACLPEN) 1988 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_FMCLPEN) 1989 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_QSPILPEN) 1990 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC1LPEN) 1991 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC2LPEN) 1992 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_CRC1LPEN) 1993 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_USBHLPEN) 1994 1995 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_MDMALPEN) 1996 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_GPULPEN) 1997 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHCKLPEN) 1998 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHTXLPEN) 1999 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHRXLPEN) 2000 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHMACLPEN) 2001 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_FMCLPEN) 2002 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_QSPILPEN) 2003 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC1LPEN) 2004 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC2LPEN) 2005 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_CRC1LPEN) 2006 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_USBHLPEN) 2007 2008 2009 /** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode. 2010 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2011 * power consumption. 2012 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2013 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2014 */ 2015 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA1LPEN) 2016 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA2LPEN) 2017 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMAMUXLPEN) 2018 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_ADC12LPEN) 2019 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_USBOLPEN) 2020 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_SDMMC3LPEN) 2021 2022 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA1LPEN) 2023 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA2LPEN) 2024 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMAMUXLPEN) 2025 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_ADC12LPEN) 2026 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_USBOLPEN) 2027 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_SDMMC3LPEN) 2028 2029 /** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode. 2030 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2031 * power consumption. 2032 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2033 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2034 */ 2035 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_DCMILPEN) 2036 #if defined(CRYP2) 2037 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRYP2LPEN) 2038 #endif 2039 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HASH2LPEN) 2040 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_RNG2LPEN) 2041 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRC2LPEN) 2042 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HSEMLPEN) 2043 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_IPCCLPEN) 2044 2045 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_DCMILPEN) 2046 #if defined(CRYP2) 2047 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRYP2LPEN) 2048 #endif 2049 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HASH2LPEN) 2050 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_RNG2LPEN) 2051 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRC2LPEN) 2052 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HSEMLPEN) 2053 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_IPCCLPEN) 2054 2055 2056 /** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode. 2057 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2058 * power consumption. 2059 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2060 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2061 */ 2062 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOALPEN) 2063 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOBLPEN) 2064 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOCLPEN) 2065 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIODLPEN) 2066 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOELPEN) 2067 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOFLPEN) 2068 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOGLPEN) 2069 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOHLPEN) 2070 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOILPEN) 2071 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOJLPEN) 2072 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOKLPEN) 2073 2074 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOALPEN) 2075 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOBLPEN) 2076 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOCLPEN) 2077 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIODLPEN) 2078 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOELPEN) 2079 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOFLPEN) 2080 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOGLPEN) 2081 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOHLPEN) 2082 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOILPEN) 2083 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOJLPEN) 2084 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOKLPEN) 2085 2086 /** @brief Enable or disable the AXI peripheral clock during CSLEEP mode. 2087 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2088 * power consumption. 2089 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2090 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2091 */ 2092 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MP_AXIMLPENSETR_SYSRAMLPEN) 2093 2094 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MP_AXIMLPENCLRR_SYSRAMLPEN) 2095 2096 2097 /** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode. 2098 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2099 * power consumption. 2100 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2101 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2102 */ 2103 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MP_MLAHBLPENSETR_RETRAMLPEN) 2104 2105 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MP_MLAHBLPENCLRR_RETRAMLPEN) 2106 2107 2108 2109 2110 2111 #else /* CORE_CA7 */ 2112 2113 2114 2115 2116 /** @brief Enable or disable the APB1 peripheral clock. 2117 * @note After reset, the peripheral clock (used for registers read/write access) 2118 * is disabled and the application software has to enable this clock before 2119 * using it. It shall be used to allocate a peripheral to the MCU. 2120 */ 2121 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN) 2122 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN) 2123 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN) 2124 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN) 2125 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN) 2126 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN) 2127 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN) 2128 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN) 2129 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN) 2130 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN) 2131 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN) 2132 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN) 2133 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN) 2134 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN) 2135 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN) 2136 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN) 2137 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN) 2138 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN) 2139 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN) 2140 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN) 2141 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN) 2142 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN) 2143 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN) 2144 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN) 2145 #define __HAL_RCC_WWDG1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_WWDG1EN) 2146 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN) 2147 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN) 2148 2149 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN) 2150 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN) 2151 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN) 2152 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN) 2153 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN) 2154 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN) 2155 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN) 2156 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN) 2157 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN) 2158 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN) 2159 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN) 2160 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN) 2161 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN) 2162 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN) 2163 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) 2164 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN) 2165 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN) 2166 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN) 2167 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN) 2168 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN) 2169 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN) 2170 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN) 2171 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN) 2172 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN) 2173 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_WWDG1EN) 2174 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN) 2175 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN) 2176 2177 /** @brief Enable or disable the APB2 peripheral clock. 2178 * @note After reset, the peripheral clock (used for registers read/write access) 2179 * is disabled and the application software has to enable this clock before 2180 * using it. It shall be used to allocate a peripheral to the MCU. 2181 */ 2182 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN) 2183 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN) 2184 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN) 2185 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN) 2186 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN) 2187 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN) 2188 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN) 2189 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN) 2190 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN) 2191 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN) 2192 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN) 2193 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN) 2194 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN) 2195 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN) 2196 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN) 2197 2198 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN) 2199 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN) 2200 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN) 2201 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN) 2202 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN) 2203 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN) 2204 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN) 2205 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN) 2206 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN) 2207 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN) 2208 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN) 2209 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN) 2210 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN) 2211 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN) 2212 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN) 2213 2214 /** @brief Enable or disable the APB3 peripheral clock. 2215 * @note After reset, the peripheral clock (used for registers read/write access) 2216 * is disabled and the application software has to enable this clock before 2217 * using it. It shall be used to allocate a peripheral to the MCU. 2218 */ 2219 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN) 2220 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN) 2221 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN) 2222 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN) 2223 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN) 2224 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN) 2225 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN) 2226 #define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN) 2227 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN) 2228 2229 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN) 2230 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN) 2231 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN) 2232 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN) 2233 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN) 2234 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN) 2235 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN) 2236 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN) 2237 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN) 2238 2239 /** @brief Enable or disable the APB4 peripheral clock. 2240 * @note After reset, the peripheral clock (used for registers read/write access) 2241 * is disabled and the application software has to enable this clock before 2242 * using it. It shall be used to allocate a peripheral to the MCU. 2243 */ 2244 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN) 2245 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN) 2246 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN) 2247 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN) 2248 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN) 2249 2250 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN) 2251 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN) 2252 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN) 2253 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN) 2254 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN) 2255 2256 /** @brief Enable or disable the APB5 peripheral clock. 2257 * @note After reset, the peripheral clock (used for registers read/write access) 2258 * is disabled and the application software has to enable this clock before 2259 * using it. It shall be used to allocate a peripheral to the MCU. 2260 */ 2261 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN) 2262 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN) 2263 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN) 2264 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN) 2265 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN) 2266 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN) 2267 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN) 2268 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN) 2269 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN) 2270 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN) 2271 2272 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN) 2273 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN) 2274 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN) 2275 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN) 2276 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN) 2277 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN) 2278 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN) 2279 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN) 2280 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN) 2281 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN) 2282 2283 /** @brief Enable or disable the AHB5 peripheral clock. 2284 * @note After reset, the peripheral clock (used for registers read/write access) 2285 * is disabled and the application software has to enable this clock before 2286 * using it. It shall be used to allocate a peripheral to the MCU. 2287 */ 2288 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN) 2289 #if defined(CRYP1) 2290 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN) 2291 #endif 2292 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN) 2293 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN) 2294 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN) 2295 2296 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN) 2297 #if defined(CRYP1) 2298 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN) 2299 #endif 2300 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN) 2301 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN) 2302 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN) 2303 2304 /** @brief Enable or disable the AHB6 peripheral clock. 2305 * @note After reset, the peripheral clock (used for registers read/write access) 2306 * is disabled and the application software has to enable this clock before 2307 * using it. It shall be used to allocate a peripheral to the MCU. 2308 */ 2309 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN) 2310 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN) 2311 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN) 2312 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN) 2313 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN) 2314 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN) 2315 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN) 2316 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN) 2317 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN) 2318 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN) 2319 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN) 2320 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN) 2321 2322 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN) 2323 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN) 2324 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN) 2325 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN) 2326 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN) 2327 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN) 2328 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN) 2329 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN) 2330 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN) 2331 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN) 2332 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN) 2333 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN) 2334 2335 /** @brief Enable or disable the AHB2 peripheral clock. 2336 * @note After reset, the peripheral clock (used for registers read/write access) 2337 * is disabled and the application software has to enable this clock before 2338 * using it. It shall be used to allocate a peripheral to the MCU. 2339 */ 2340 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN) 2341 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN) 2342 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN) 2343 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN) 2344 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN) 2345 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN) 2346 2347 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN) 2348 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN) 2349 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN) 2350 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN) 2351 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN) 2352 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN) 2353 2354 /** @brief Enable or disable the AHB3 peripheral clock. 2355 * @note After reset, the peripheral clock (used for registers read/write access) 2356 * is disabled and the application software has to enable this clock before 2357 * using it. It shall be used to allocate a peripheral to the MCU. 2358 */ 2359 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN) 2360 #if defined(CRYP2) 2361 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN) 2362 #endif 2363 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN) 2364 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN) 2365 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN) 2366 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN) 2367 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN) 2368 2369 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN) 2370 #if defined(CRYP2) 2371 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN) 2372 #endif 2373 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN) 2374 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN) 2375 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN) 2376 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN) 2377 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN) 2378 2379 /** @brief Enable or disable the AHB4 peripheral clock. 2380 * @note After reset, the peripheral clock (used for registers read/write access) 2381 * is disabled and the application software has to enable this clock before 2382 * using it. It shall be used to allocate a peripheral to the MCU. 2383 */ 2384 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN) 2385 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN) 2386 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN) 2387 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN) 2388 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN) 2389 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN) 2390 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN) 2391 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN) 2392 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN) 2393 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN) 2394 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN) 2395 2396 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN) 2397 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN) 2398 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN) 2399 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN) 2400 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN) 2401 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN) 2402 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN) 2403 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN) 2404 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN) 2405 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN) 2406 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN) 2407 2408 /** @brief Enable or disable the AXI peripheral clock. 2409 * @note After reset, the peripheral clock (used for registers read/write access) 2410 * is disabled and the application software has to enable this clock before 2411 * using it. It shall be used to allocate a peripheral to the MCU. 2412 */ 2413 #define __HAL_RCC_SYSRAM_CLK_ENABLE() (RCC->MC_AXIMENSETR = RCC_MC_AXIMENSETR_SYSRAMEN) 2414 2415 #define __HAL_RCC_SYSRAM_CLK_DISABLE() (RCC->MC_AXIMENCLRR = RCC_MC_AXIMENCLRR_SYSRAMEN) 2416 2417 /** @brief Enable or disable the MLAHB peripheral clock. 2418 * @note After reset, the peripheral clock (used for registers read/write access) 2419 * is disabled and the application software has to enable this clock before 2420 * using it. It shall be used to allocate a peripheral to the MCU. 2421 */ 2422 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MC_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN) 2423 2424 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MC_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN) 2425 2426 2427 2428 2429 2430 2431 2432 /** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode. 2433 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2434 * power consumption. 2435 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2436 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2437 */ 2438 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN) 2439 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN) 2440 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN) 2441 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN) 2442 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN) 2443 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN) 2444 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN) 2445 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN) 2446 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN) 2447 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN) 2448 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN) 2449 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN) 2450 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN) 2451 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN) 2452 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN) 2453 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN) 2454 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN) 2455 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN) 2456 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN) 2457 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN) 2458 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN) 2459 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN) 2460 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN) 2461 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN) 2462 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_WWDG1LPEN) 2463 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN) 2464 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN) 2465 2466 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN) 2467 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN) 2468 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN) 2469 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN) 2470 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN) 2471 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN) 2472 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN) 2473 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN) 2474 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN) 2475 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN) 2476 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN) 2477 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN) 2478 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN) 2479 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN) 2480 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN) 2481 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN) 2482 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN) 2483 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN) 2484 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN) 2485 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN) 2486 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN) 2487 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN) 2488 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN) 2489 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN) 2490 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_WWDG1LPEN) 2491 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN) 2492 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN) 2493 2494 2495 /** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode. 2496 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2497 * power consumption. 2498 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2499 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2500 */ 2501 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN) 2502 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN) 2503 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN) 2504 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN) 2505 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN) 2506 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN) 2507 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN) 2508 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN) 2509 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN) 2510 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN) 2511 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN) 2512 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN) 2513 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN) 2514 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN) 2515 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN) 2516 2517 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN) 2518 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN) 2519 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN) 2520 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN) 2521 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN) 2522 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN) 2523 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN) 2524 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN) 2525 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN) 2526 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN) 2527 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN) 2528 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN) 2529 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN) 2530 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN) 2531 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN) 2532 2533 2534 /** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode. 2535 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2536 * power consumption. 2537 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2538 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2539 */ 2540 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN) 2541 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN) 2542 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN) 2543 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN) 2544 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN) 2545 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN) 2546 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN) 2547 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN) 2548 2549 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN) 2550 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN) 2551 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN) 2552 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN) 2553 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN) 2554 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN) 2555 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN) 2556 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN) 2557 2558 /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. 2559 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2560 * power consumption. 2561 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2562 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2563 */ 2564 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN) 2565 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN) 2566 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN) 2567 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN) 2568 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN) 2569 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN) 2570 2571 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN) 2572 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN) 2573 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN) 2574 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN) 2575 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN) 2576 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN) 2577 2578 /** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode. 2579 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2580 * power consumption. 2581 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2582 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2583 */ 2584 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN) 2585 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN) 2586 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN) 2587 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN) 2588 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN) 2589 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN) 2590 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN) 2591 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN) 2592 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN) 2593 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN) 2594 2595 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN) 2596 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN) 2597 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN) 2598 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN) 2599 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN) 2600 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN) 2601 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN) 2602 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN) 2603 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN) 2604 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN) 2605 2606 2607 /** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode. 2608 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2609 * power consumption. 2610 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2611 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2612 */ 2613 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN) 2614 #if defined(CRYP1) 2615 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN) 2616 #endif 2617 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN) 2618 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN) 2619 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN) 2620 2621 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN) 2622 #if defined(CRYP1) 2623 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN) 2624 #endif 2625 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN) 2626 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN) 2627 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN) 2628 2629 2630 /** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode. 2631 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2632 * power consumption. 2633 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2634 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2635 */ 2636 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN) 2637 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN) 2638 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN) 2639 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN) 2640 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN) 2641 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN) 2642 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN) 2643 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN) 2644 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN) 2645 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN) 2646 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN) 2647 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN) 2648 2649 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN) 2650 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN) 2651 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN) 2652 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN) 2653 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN) 2654 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN) 2655 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN) 2656 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN) 2657 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN) 2658 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN) 2659 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN) 2660 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN) 2661 2662 2663 /** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode. 2664 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2665 * power consumption. 2666 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2667 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2668 */ 2669 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN) 2670 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN) 2671 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN) 2672 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN) 2673 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN) 2674 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN) 2675 2676 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN) 2677 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN) 2678 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN) 2679 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN) 2680 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN) 2681 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN) 2682 2683 /** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode. 2684 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2685 * power consumption. 2686 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2687 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2688 */ 2689 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN) 2690 #if defined(CRYP2) 2691 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN) 2692 #endif 2693 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN) 2694 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN) 2695 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN) 2696 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN) 2697 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN) 2698 2699 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN) 2700 #if defined(CRYP2) 2701 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN) 2702 #endif 2703 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN) 2704 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN) 2705 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN) 2706 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN) 2707 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN) 2708 2709 2710 /** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode. 2711 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2712 * power consumption. 2713 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2714 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2715 */ 2716 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN) 2717 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN) 2718 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN) 2719 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN) 2720 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN) 2721 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN) 2722 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN) 2723 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN) 2724 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN) 2725 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN) 2726 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN) 2727 2728 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN) 2729 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN) 2730 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN) 2731 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN) 2732 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN) 2733 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN) 2734 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN) 2735 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN) 2736 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN) 2737 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN) 2738 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN) 2739 2740 /** @brief Enable or disable the AXI peripheral clock during CSLEEP mode. 2741 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2742 * power consumption. 2743 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2744 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2745 */ 2746 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN) 2747 2748 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN) 2749 2750 2751 /** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode. 2752 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2753 * power consumption. 2754 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2755 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2756 */ 2757 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN) 2758 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM1LPEN) 2759 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM2LPEN) 2760 #define __HAL_RCC_SRAM34_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM34LPEN) 2761 2762 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN) 2763 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM1LPEN) 2764 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM2LPEN) 2765 #define __HAL_RCC_SRAM34_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM3LPEN) 2766 2767 /** @brief Enable or disable the AHB6 peripheral clock during (C)STOP mode. 2768 * @note Peripheral clock gating in (C)STOP mode can be used to further reduce 2769 * power consumption. 2770 * @note It is possible to control the gating of clocks coming from PADs ETH_RX_CLK and ETH_TX_CLK 2771 * in CSTOP and STOP modes via the ETHSTPEN bit 2772 */ 2773 #define __HAL_RCC_ETH1CK_CLK_STOP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHSTPEN) 2774 2775 #define __HAL_RCC_ETH1CK_CLK_STOP_DISABLE() (RCC->MC_AHB6LPENSETR) = (RCC_MC_AHB6LPENCLRR_ETHSTPEN) 2776 2777 #endif /* !CORE_CA7 */ 2778 2779 /** @brief Macro to test if HSE oscillator is used somewhere in the core system 2780 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2781 * up to user code 2782 */ 2783 #define IS_HSE_IN_USE() \ 2784 (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \ 2785 ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY)) || \ 2786 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \ 2787 \ 2788 ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSE) && \ 2789 ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \ 2790 \ 2791 ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2792 \ 2793 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0) 2794 2795 /** @brief Macro to test if HSI oscillator is used somewhere in the core system 2796 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2797 * up to user code 2798 */ 2799 #define IS_HSI_IN_USE() \ 2800 (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \ 2801 ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) ) || \ 2802 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) ) || \ 2803 \ 2804 ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSI) && \ 2805 ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \ 2806 \ 2807 ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2808 \ 2809 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0) 2810 2811 2812 /** @brief Macro to test if CSI oscillator is used somewhere in the core system 2813 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2814 * up to user code 2815 */ 2816 #define IS_CSI_IN_USE() \ 2817 (( ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2818 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \ 2819 \ 2820 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY)))? 1 : 0) 2821 2822 /** @brief Macros to test if PLLx are used on the Core and buses clock generation system (MPU, MCU or AXIS blocks) 2823 * @note HAL driver does not ensure these clocks are used by peripherals, it's up to user code */ 2824 #define __IS_PLL1_IN_USE() \ 2825 ( ( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_PLL1) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) || \ 2826 ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_MPUDIV) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) ) ? 1:0) 2827 2828 #define __IS_PLL2_IN_USE() \ 2829 ( ( (__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_PLL2) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) )? 1:0) 2830 2831 #define __IS_PLL3_IN_USE() \ 2832 ( ( (__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_PLL3) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) )? 1:0) 2833 2834 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 2835 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2836 * It is used (enabled by hardware) as system clock source after startup 2837 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2838 * of the HSE used directly or indirectly as system clock (if the Clock 2839 * Security System CSS is enabled). 2840 * @note HSI can not be stopped if it is used as system clock source. In this case, 2841 * you have to select another source of the system clock then stop the HSI. 2842 * @note After enabling the HSI, the application software should wait on HSIRDY 2843 * flag to be set indicating that HSI clock is stable and can be used as 2844 * system clock source. 2845 * This parameter can be: ENABLE or DISABLE. 2846 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2847 * clock cycles. 2848 */ 2849 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION) 2850 #define __HAL_RCC_HSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSION) 2851 2852 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2853 * @note The calibration is used to compensate for the variations in voltage 2854 * and temperature that influence the frequency of the internal HSI RC. 2855 * @param __HSICalibrationValue__: specifies the calibration trimming value 2856 * HSITRIM. HSITRIM represents a signed value. HSITRIM field is added 2857 * to the engineering Option Bytes loaded during reset phase 2858 * (bsec_hsi_cal[11:0]) in order to form the calibration trimming value. 2859 * HSICAL[11:0] = bsec_hsi_cal[11:0] + HSITRIM[6:0] 2860 * This parameter must be a number between 0 and 0x7F: 2861 * 0x40: bsec_hsi_cal[11:0] - 64 2862 * 0x41: bsec_hsi_cal[11:0] - 63 2863 * ... 2864 * 0x0: bsec_hsi_cal[11:0] (default after reset) 2865 * ... 2866 * 0x3E: bsec_hsi_cal[11:0] + 62 2867 * 0x3F: bsec_hsi_cal[11:0] + 63 2868 */ 2869 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 2870 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, \ 2871 (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos) 2872 2873 2874 /** 2875 * @brief Macro to configure HSI clock divider 2876 * @note Set and reset by software to control the HSI clock division factor. 2877 * @note It is not allowed to change HSIDIV, if the HSI is currently used as 2878 * reference clock for a PLL. 2879 * @note If TZEN = 1, this parameter can only be modified in secure mode. 2880 * @note Write access to this register is not allowed during the clock restore sequence 2881 * @note The application can check if the new division factor is taken into 2882 * account by reading back the HSIDIVRDY flag 2883 * 2884 * @param __RCC_HSIDIV__: specifies the HSI division factor 2885 * This parameter can be one of the following values: 2886 * @arg RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset) 2887 * @arg RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz 2888 * @arg RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz 2889 * @arg RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz 2890 */ 2891 #define __HAL_RCC_HSI_DIV(__RCC_HSIDIV__) \ 2892 do{ MODIFY_REG( RCC->HSICFGR, RCC_HSICFGR_HSIDIV , (__RCC_HSIDIV__) );\ 2893 } while(0) 2894 2895 /** @brief Macro to get the HSI clock division factor. 2896 * @retval The HSI clock division factor. The returned value can be one 2897 * of the following: 2898 * - RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset) 2899 * - RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz 2900 * - RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz 2901 * - RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz 2902 */ 2903 #define __HAL_RCC_GET_HSI_DIV() ((uint32_t)(RCC->HSICFGR & RCC_HSICFGR_HSIDIV )) 2904 2905 2906 /** 2907 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2908 * in STOP mode to be quickly available as kernel clock. 2909 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2910 * speed because of the HSI startup time. 2911 * @note The enable of this function has not effect on the HSION bit. 2912 * This parameter can be: ENABLE or DISABLE. 2913 * @retval None 2914 */ 2915 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSIKERON) 2916 #define __HAL_RCC_HSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON) 2917 2918 2919 /** 2920 * @brief Macros to enable or disable the Internal oscillator (CSI). 2921 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 2922 * It is used (enabled by hardware) as system clock source after 2923 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2924 * of failure of the HSE used directly or indirectly as system clock 2925 * (if the Clock Security System CSS is enabled). 2926 * @note CSI can not be stopped if it is used as system clock source. 2927 * In this case, you have to select another source of the system 2928 * clock then stop the CSI. 2929 * @note After enabling the CSI, the application software should wait on 2930 * CSIRDY flag to be set indicating that CSI clock is stable and can 2931 * be used as system clock source. 2932 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 2933 * clock cycles. 2934 */ 2935 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSION) 2936 #define __HAL_RCC_CSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENSETR_CSION) 2937 2938 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 2939 * @note The calibration is used to compensate for the variations in voltage 2940 * and temperature that influence the frequency of the internal CSI RC. 2941 * Please refer to the datasheet of the product for for more details on how to 2942 * calibrate the CSI. 2943 * @param __CSICalibrationValue__: specifies the calibration trimming value. 2944 * This parameter must be a number between 0 and 0x1F. 2945 */ 2946 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 2947 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, \ 2948 (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos) 2949 2950 /** 2951 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (CSI) 2952 * in STOP mode to be quickly available as kernel clock. 2953 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 2954 * speed because of the CSI startup time. 2955 * @note The enable of this function has not effect on the CSION bit. 2956 * This parameter can be: ENABLE or DISABLE. 2957 * @retval None 2958 */ 2959 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSIKERON) 2960 #define __HAL_RCC_CSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSIKERON) 2961 2962 2963 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2964 * @note After enabling the LSI, the application software should wait on 2965 * LSIRDY flag to be set indicating that LSI clock is stable and can 2966 * be used to clock the IWDG and/or the RTC. 2967 * @note LSI can not be disabled if the IWDG is running. 2968 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2969 * clock cycles. 2970 */ 2971 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION) 2972 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION) 2973 2974 2975 2976 2977 /** @brief Macro to configure the Minimum Reset Duration 2978 * @note Set and reset by software. They define the minimum guaranteed 2979 * duration of the NRST low pulse. The LSI oscillator is automatically 2980 * enabled when needed by the RPCTL. 2981 * @note 00000: NRST low pulse duration is guaranteed by the pulse stretcher 2982 * of the PAD. The RPCTL is bypassed (default after reset) 2983 * 00010: The guaranteed NRST low pulse duration is about 2 ms (2 x 32 ck_lsi cycles), 2984 * ... 2985 * 11111: The guaranteed NRST low pulse duration is about 31 ms (31 x 32 ck_lsi cycles). 2986 */ 2987 #define __HAL_RCC_MRD_CONFIG(__DURATION__) \ 2988 do { MODIFY_REG(RCC->RDLSICR, RCC_RDLSICR_MRD, \ 2989 (uint32_t)(__DURATION__) << RCC_RDLSICR_MRD_Pos) \ 2990 HAL_Delay(1); \ 2991 } while(0) 2992 2993 2994 2995 /** 2996 * @brief Macro (depricated) to configure the External High Speed oscillator (HSE). 2997 * @note Macro name is kept to mantain compatibility and it is mapped on 2998 * HAL_RCC_HSEConfig function which replaces macro and should be used 2999 * instead. 3000 * @note HSE state can not be changed if it is used directly or through the 3001 * PLL as system clock. In this case, you have to select another source 3002 * of the system clock then change the HSE state (ex. disable it). 3003 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 3004 * @note This function reset the CSSON bit, so if the clock security system(CSS) 3005 * was previously enabled you have to enable it again after calling this 3006 * function. 3007 * @param __STATE__: specifies the new state of the HSE. 3008 * This parameter can be one of the following values: 3009 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator 3010 * @arg RCC_HSE_ON: turn ON the HSE oscillator using an external 3011 * crystal/ceramic resonator 3012 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock 3013 * using a low-swing analog signal provided to OSC_IN 3014 * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external 3015 * clock using a full-swing digital signal provided to OSC_IN 3016 */ 3017 #define __HAL_RCC_HSE_CONFIG(__STATE__) HAL_RCC_HSEConfig(__STATE__) 3018 3019 3020 /** 3021 * @brief Macros to enable or disable the force of the External High Speed oscillator (HSE) 3022 * in STOP mode to be quickly available as kernel clock. 3023 * @note Keeping the HSE ON in STOP mode allows to avoid slowing down the communication 3024 * speed because of the HSE startup time. 3025 * @note The enable of this function has not effect on the HSION bit. 3026 * This parameter can be: ENABLE or DISABLE. 3027 * @retval None 3028 */ 3029 #define __HAL_RCC_HSESTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEKERON) 3030 #define __HAL_RCC_HSESTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEKERON) 3031 3032 3033 /** 3034 * @brief Macro (depricated) to configure the External Low Speed oscillator (LSE). 3035 * @note Macro name is kept to mantain compatibility and it is mapped on 3036 * HAL_RCC_LSEConfig function which replaces macro and should be used 3037 * instead. 3038 * @note As the LSE is in the Backup domain and write access is denied to 3039 * this domain after reset, you have to enable write access using 3040 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3041 * (to be done once after reset). 3042 * @param __STATE__: specifies the new state of the LSE. 3043 * This parameter can be a value of @ref RCC_LSE_Config 3044 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator 3045 * @arg RCC_LSE_ON: turn ON the LSE oscillator using an external 3046 * crystal/ceramic resonator 3047 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock 3048 * using a low-swing analog signal provided to OSC32_IN 3049 * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external clock using 3050 * a full-swing digital signal provided to OSC32_IN 3051 */ 3052 #define __HAL_RCC_LSE_CONFIG(__STATE__) HAL_RCC_LSEConfig(__STATE__) 3053 3054 3055 /** 3056 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. 3057 * @note As the LSE is in the Backup domain and write access is denied to 3058 * this domain after reset, you have to enable write access using 3059 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3060 * (to be done once after reset). 3061 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 3062 * This parameter can be one of the following values: 3063 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset) 3064 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 3065 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 3066 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 3067 * @retval None 3068 */ 3069 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3070 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3071 3072 3073 /** @brief Macro to get the LSE driving capability. 3074 * @retval The LSE Driving capability . The returned value can be one 3075 * of the following: 3076 * - RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset) 3077 * - RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 3078 * - RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 3079 * - RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 3080 */ 3081 #define __HAL_RCC_GET_LSEDRIVE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV))) 3082 3083 /** @brief Macros to enable or disable the the RTC clock. 3084 * @note These macros must be used only after the RTC clock source was selected. 3085 */ 3086 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN) 3087 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN) 3088 3089 /** @brief Macros to configure the RTC clock (RTCCLK). 3090 * @note As the RTC clock configuration bits are in the Backup domain and write 3091 * access is protected to this domain after reset, you have to enable write 3092 * access using the Power Backup Access macro ( DBP bit in the PWR control 3093 * register 1 PWR_CR1 has to be set to 1) before to configure 3094 * the RTC clock source (to be done once after reset). 3095 * @note Once the RTC clock is configured it can't be changed unless the 3096 * Backup domain is reset using __HAL_RCC_BACKUPRESET_RELEASE() macro, or by 3097 * a Power On Reset (POR). 3098 * @param __RTCCLKSource__: specifies the RTC clock source. 3099 * This parameter can be one of the following values: 3100 * @arg RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset) 3101 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 3102 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 3103 * @arg RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock 3104 * 3105 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3106 * work in STOP and STANDBY modes, and can be used as wakeup source. 3107 * However, when the HSE clock is used as RTC clock source, the RTC 3108 * cannot be used in STOP and STANDBY modes. 3109 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3110 * RTC clock source). 3111 */ 3112 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ 3113 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSRC, (__RTCCLKSource__)) 3114 3115 3116 /** @brief Macro to get the clock source used as RTC clock. 3117 * @retval The clock source used as RTC clock. The returned value can be one 3118 * of the following: 3119 * - RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset) 3120 * - RCC_RTCCLKSOURCE_LSE: LSE used as RTC clock. 3121 * - RCC_RTCCLKSOURCE_LSI: LSI used as RTC clock. 3122 * - RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock 3123 */ 3124 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSRC))) 3125 3126 3127 /** @brief Macros to force or release the Backup domain reset. 3128 * @note This function resets the RTC peripheral (including the backup registers) 3129 * 3130 * @note The BKPSRAM and RETRAM are not affected 3131 */ 3132 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3133 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3134 3135 3136 /** @brief Macros to enable or disable the PLL1. 3137 * @note After enabling the main PLL, the application software should wait on 3138 * PLLRDY flag to be set indicating that PLL clock is stable and can 3139 * be used as system clock source. 3140 * @note The PLL1 can not be disabled if it is used as MPU clock source 3141 * @note The PLL1 is disabled by hardware when entering STOP and STANDBY modes. 3142 */ 3143 3144 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON ) 3145 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON) 3146 3147 /** 3148 * @brief Enables or disables each clock output 3149 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3150 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3151 * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputed 3152 * This parameter can be one of the following values: 3153 * @arg RCC_PLL1_DIVP 3154 * @arg RCC_PLL1_DIVQ 3155 * @arg RCC_PLL1_DIVR 3156 * @retval None 3157 */ 3158 3159 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLL1CR, (__RCC_PLL1ClockOut__)) 3160 3161 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLL1CR, (__RCC_PLL1ClockOut__)) 3162 3163 3164 /** 3165 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 3166 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL1 3167 * @retval None 3168 */ 3169 3170 #define __HAL_RCC_PLL1FRACV_ENABLE() SET_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) 3171 3172 #define __HAL_RCC_PLL1FRACV_DISABLE() CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) 3173 3174 3175 3176 /** 3177 * @brief Macro to configure PLL1 and PLL2 clock source 3178 * @note This function must be used only when the PLLs are disabled. 3179 * 3180 * @param __RCC_PLL12SOURCE__: specifies the PLL1 and PLL2 entry clock source. 3181 * This parameter can be one of the following values: 3182 * @arg RCC_PLL12SOURCE_HSI: HSI oscillator clock selected as PLL1 and PLL2 clock entry 3183 * @arg RCC_PLL12SOURCE_HSE: HSE oscillator clock selected as PLL1 and PLL2 clock entry 3184 * @arg RCC_PLL12SOURCE_OFF: No clock send to DIVMx divider and PLLs 3185 * @note This clock source (__RCC_PLL12Source__) is common for the PLL1 and PLL2 . 3186 * @retval None 3187 */ 3188 #define __HAL_RCC_PLL12_SOURCE(__RCC_PLL12SOURCE__ ) \ 3189 do{ MODIFY_REG( RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC, (__RCC_PLL12SOURCE__)); \ 3190 } while(0) 3191 3192 /** @brief Macro to get the clock source used as PLL1 and PLL2 clocks. 3193 * @retval The clock source used as PLL1 and PLL1 clocks. The returned value can be one 3194 * of the following: 3195 * - RCC_PLL12SOURCE_HSI: HSI used as PLL12 clock. 3196 * - RCC_PLL12SOURCE_HSE: HSE used as PLL12 clock. 3197 * - RCC_PLL12SOURCE_OFF: PLL1 and PLL2 clock is gated. 3198 */ 3199 #define __HAL_RCC_GET_PLL12_SOURCE() ((uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC)) 3200 3201 /** 3202 * @brief Macro to configure PLL1 multiplication and division factors. 3203 * @note This function must be used only when the PLL1 is disabled. 3204 * 3205 * @param __PLLM1__: specifies the division factor for PLL VCO input clock 3206 * This parameter must be a number between 1 and 64 3207 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3208 * frequency ranges from 8 to 16 MHz 3209 * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock 3210 * This parameter must be a number between 25 and 100 3211 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3212 * output frequency is between 800 to 1600 MHz 3213 * @param __PLLP1__: specifies the division factor for the PLL1 P output 3214 * This parameter must be a number in the range 1 to 128 3215 * @param __PLLQ1__: specifies the division factor for for the PLL1 Q output 3216 * This parameter must be in the range 1 to 128 3217 * @param __PLLR1__: specifies the division factor for for the PLL1 R output 3218 * This parameter must be in the range 1 to 128 3219 * @retval None 3220 */ 3221 #define __HAL_RCC_PLL1_CONFIG(__PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ 3222 do{ MODIFY_REG( RCC->PLL1CFGR1, (RCC_PLL1CFGR1_DIVN | RCC_PLL1CFGR1_DIVM1) , \ 3223 ( ((__PLLN1__) - 1U) | ( ((__PLLM1__) - 1U) << 16U) ) ); \ 3224 MODIFY_REG( RCC->PLL1CFGR2, (RCC_PLL1CFGR2_DIVP | RCC_PLL1CFGR2_DIVQ | RCC_PLL1CFGR2_DIVR), \ 3225 ( ((__PLLP1__) - 1U) | ( ((__PLLQ1__) - 1U) <<8U ) | ( ((__PLLR1__) - 1U) <<16U) )); \ 3226 } while(0) 3227 3228 3229 3230 /** 3231 * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor 3232 * 3233 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 3234 * 3235 * @param __RCC_PLL1FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL1 VCO 3236 * It should be a value between 0 and 8191 ((2^13)-1) 3237 * @note Warning: the software has to set correctly these bits to insure that the VCO 3238 * output frequency is between its valid frequency range, which is: 800 to 1600 MHz 3239 * @retval None 3240 */ 3241 #define __HAL_RCC_PLL1FRACV_CONFIG(__RCC_PLL1FRACV__) \ 3242 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV,\ 3243 (uint32_t)(__RCC_PLL1FRACV__) << RCC_PLL1FRACR_FRACV_Pos) 3244 3245 3246 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL1 3247 */ 3248 #define __HAL_RCC_PLL1_SSMODE_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL) 3249 3250 #define __HAL_RCC_PLL1_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL) 3251 3252 3253 /** @brief Macro to config the PLL1 Clock Spreading Generator 3254 * @param __RCC_PLL1_MOD_PER__: Modulation Period Adjustment for PLL1 3255 * This parameter must have a value between 1 and 8191 3256 * 3257 * @param __RCC_PLL1_TPDFN_DIS__: Dithering TPDF noise control 3258 * This parameter can be one of the following values: 3259 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3260 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3261 3262 * @param __RCC_PLL1_RPDFN_DIS__: Dithering TPDF noise control 3263 * This parameter can be one of the following values: 3264 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3265 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3266 * 3267 * 3268 * @param __RCC_PLL1_SSCG_MODE__: Spread spectrum clock generator mode 3269 * This parameter can be one of the following values: 3270 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3271 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3272 * 3273 * @param __RCC_PLL1_INC_STEP__: Modulation Depth Adjustment for PLL1 3274 * This parameter must have a value between 1 and 32767 3275 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3276 * @retval None 3277 */ 3278 #define __HAL_RCC_PLL1CSGCONFIG(__RCC_PLL1_MOD_PER__, __RCC_PLL1_TPDFN_DIS__, __RCC_PLL1_RPDFN_DIS__, \ 3279 __RCC_PLL1_SSCG_MODE__, __RCC_PLL1_INC_STEP__ ) \ 3280 do{ MODIFY_REG( RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | RCC_PLL1CSGR_RPDFN_DIS | \ 3281 RCC_PLL1CSGR_SSCG_MODE | RCC_PLL1CSGR_INC_STEP) , \ 3282 ((__RCC_PLL1_MOD_PER__) | (__RCC_PLL1_TPDFN_DIS__) | (__RCC_PLL1_RPDFN_DIS__) | \ 3283 (__RCC_PLL1_SSCG_MODE__) | ((__RCC_PLL1_INC_STEP__) << RCC_PLL1CSGR_INC_STEP_Pos)) ) ; \ 3284 } while(0) 3285 3286 3287 3288 /** @brief Macros to enable or disable the PLL2. 3289 * @note After enabling the main PLL, the application software should wait on 3290 * PLLRDY flag to be set indicating that PLL clock is stable and can 3291 * be used as system clock source. 3292 * @note The PLL2 can not be disabled if it is used as MPU clock source 3293 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 3294 */ 3295 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON ) 3296 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON) 3297 3298 /** 3299 * @brief Enables or disables each clock output 3300 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL 3301 * @param __RCC_PLL2ClockOut__: specifies the PLL clock to be outputed 3302 * This parameter can be one of the following values: 3303 * @arg RCC_PLL2_DIVP 3304 * @arg RCC_PLL2_DIVQ 3305 * @arg RCC_PLL2_DIVR 3306 * @retval None 3307 */ 3308 3309 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLL2CR, (__RCC_PLL2ClockOut__)) 3310 3311 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLL2CR, (__RCC_PLL2ClockOut__)) 3312 3313 /** 3314 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 3315 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL2 3316 * @retval None 3317 */ 3318 3319 #define __HAL_RCC_PLL2FRACV_ENABLE() SET_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE) 3320 3321 #define __HAL_RCC_PLL2FRACV_DISABLE() CLEAR_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE) 3322 3323 /** 3324 * @brief Macro to configure PLL2 multiplication and division factors. 3325 * @note This function must be used only when the PLL2 is disabled. 3326 * 3327 * @param __PLLM2__: specifies the division factor for PLL VCO input clock 3328 * This parameter must be a number between 1 and 64 3329 * @note You have to set the PLLM2 parameter correctly to ensure that the VCO input 3330 * frequency ranges from 8 to 16 MHz 3331 * @param __PLLN2__: specifies the multiplication factor for PLL VCO output clock 3332 * This parameter must be a number between 25 and 100 3333 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3334 * output frequency is between 800 to 1600 MHz 3335 * @param __PLLP2__: specifies the division factor for the PLL2 P output 3336 * This parameter must be a number in the range 1 to 128 3337 * @param __PLLQ2__: specifies the division factor for for the PLL2 Q output 3338 * This parameter must be in the range 1 to 128 3339 * @param __PLLR2__: specifies the division factor for for the PLL2 R output 3340 * This parameter must be in the range 1 to 128 3341 * @retval None 3342 */ 3343 #define __HAL_RCC_PLL2_CONFIG(__PLLM2__, __PLLN2__, __PLLP2__, __PLLQ2__,__PLLR2__ ) \ 3344 do{ MODIFY_REG( RCC->PLL2CFGR1, (RCC_PLL2CFGR1_DIVN | RCC_PLL2CFGR1_DIVM2) , \ 3345 ( ((__PLLN2__) - 1U) | ( ((__PLLM2__) - 1U) << 16U) ) ); \ 3346 MODIFY_REG( RCC->PLL2CFGR2, (RCC_PLL2CFGR2_DIVP | RCC_PLL2CFGR2_DIVQ | RCC_PLL2CFGR2_DIVR), \ 3347 ( ((__PLLP2__) - 1U) | ( ((__PLLQ2__) - 1U) <<8U ) | ( ((__PLLR2__) - 1U) <<16U) )); \ 3348 } while(0) 3349 3350 /** 3351 * @brief Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor 3352 * 3353 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 3354 * 3355 * @param __RCC_PLL2FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL2 VCO 3356 * It should be a value between 0 and 8191 ((2^13)-1) 3357 * @note Warning: the software has to set correctly these bits to insure that the VCO 3358 * output frequency is between its valid frequency range, which is: 800 to 1600 MHz 3359 * @retval None 3360 */ 3361 #define __HAL_RCC_PLL2FRACV_CONFIG(__RCC_PLL2FRACV__) \ 3362 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV, \ 3363 (uint32_t)(__RCC_PLL2FRACV__) << RCC_PLL2FRACR_FRACV_Pos) 3364 3365 3366 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL2 3367 */ 3368 #define __HAL_RCC_PLL2_SSMODE_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL) 3369 3370 #define __HAL_RCC_PLL2_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL) 3371 3372 3373 /** @brief Macro to config the PLL2 Clock Spreading Generator 3374 * @param __RCC_PLL2_MOD_PER__: Modulation Period Adjustment for PLL2 3375 * This parameter must have a value between 1 and 8191 3376 * 3377 * @param __RCC_PLL2_TPDFN_DIS__: Dithering TPDF noise control 3378 * This parameter can be one of the following values: 3379 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3380 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3381 3382 * @param __RCC_PLL2_RPDFN_DIS__: Dithering TPDF noise control 3383 * This parameter can be one of the following values: 3384 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3385 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3386 * 3387 * 3388 * @param __RCC_PLL2_SSCG_MODE__: Spread spectrum clock generator mode 3389 * This parameter can be one of the following values: 3390 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3391 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3392 * 3393 * @param __RCC_PLL2_INC_STEP__: Modulation Depth Adjustment for PLL2 3394 * This parameter must have a value between 1 and 32767 3395 * 3396 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3397 * @retval None 3398 */ 3399 #define __HAL_RCC_PLL2CSGCONFIG(__RCC_PLL2_MOD_PER__, __RCC_PLL2_TPDFN_DIS__, __RCC_PLL2_RPDFN_DIS__, \ 3400 __RCC_PLL2_SSCG_MODE__, __RCC_PLL2_INC_STEP__ ) \ 3401 do{ MODIFY_REG( RCC->PLL2CSGR, (RCC_PLL2CSGR_MOD_PER | RCC_PLL2CSGR_TPDFN_DIS | RCC_PLL2CSGR_RPDFN_DIS | \ 3402 RCC_PLL2CSGR_SSCG_MODE | RCC_PLL2CSGR_INC_STEP) , \ 3403 ((__RCC_PLL2_MOD_PER__) | (__RCC_PLL2_TPDFN_DIS__) | (__RCC_PLL2_RPDFN_DIS__) | \ 3404 (__RCC_PLL2_SSCG_MODE__) | ((__RCC_PLL2_INC_STEP__) << RCC_PLL2CSGR_INC_STEP_Pos)) ) ; \ 3405 } while(0) 3406 3407 /** @brief Macros to enable or disable the PLL3. 3408 * @note After enabling the main PLL, the application software should wait on 3409 * PLLRDY flag to be set indicating that PLL clock is stable and can 3410 * be used as system clock source. 3411 * @note The PLL3 can not be disabled if it is used as MPU clock source 3412 * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. 3413 */ 3414 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON ) 3415 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON) 3416 3417 /** 3418 * @brief Enables or disables each clock output 3419 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3420 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3421 * @param __RCC_PLL3ClockOut__: specifies the PLL clock to be outputed 3422 * This parameter can be one of the following values: 3423 * @arg RCC_PLL3_DIVP 3424 * @arg RCC_PLL3_DIVQ 3425 * @arg RCC_PLL3_DIVR 3426 * @retval None 3427 */ 3428 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLL3CR, (__RCC_PLL3ClockOut__)) 3429 3430 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLL3CR, (__RCC_PLL3ClockOut__)) 3431 3432 3433 /** 3434 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 3435 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL3 3436 * @retval None 3437 */ 3438 3439 #define __HAL_RCC_PLL3FRACV_ENABLE() SET_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE) 3440 3441 #define __HAL_RCC_PLL3FRACV_DISABLE() CLEAR_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE) 3442 3443 3444 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL3 3445 */ 3446 #define __HAL_RCC_PLL3_SSMODE_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL) 3447 3448 #define __HAL_RCC_PLL3_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL) 3449 3450 3451 /** @brief Macro to config the PLL3 Clock Spreading Generator 3452 * @param __RCC_PLL3_MOD_PER__: Modulation Period Adjustment for PLL3 3453 * This parameter must have a value between 1 and 8191 3454 * 3455 * @param __RCC_PLL3_TPDFN_DIS__: Dithering TPDF noise control 3456 * This parameter can be one of the following values: 3457 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3458 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3459 3460 * @param __RCC_PLL3_RPDFN_DIS__: Dithering TPDF noise control 3461 * This parameter can be one of the following values: 3462 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3463 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3464 * 3465 * 3466 * @param __RCC_PLL3_SSCG_MODE__: Spread spectrum clock generator mode 3467 * This parameter can be one of the following values: 3468 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3469 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3470 * 3471 * @param __RCC_PLL3_INC_STEP__: Modulation Depth Adjustment for PLL3 3472 * This parameter must have a value between 1 and 32767 3473 * 3474 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3475 * @retval None 3476 */ 3477 #define __HAL_RCC_PLL3CSGCONFIG(__RCC_PLL3_MOD_PER__, __RCC_PLL3_TPDFN_DIS__, __RCC_PLL3_RPDFN_DIS__, \ 3478 __RCC_PLL3_SSCG_MODE__, __RCC_PLL3_INC_STEP__ ) \ 3479 do{ MODIFY_REG( RCC->PLL3CSGR, (RCC_PLL3CSGR_MOD_PER | RCC_PLL3CSGR_TPDFN_DIS | RCC_PLL3CSGR_RPDFN_DIS | \ 3480 RCC_PLL3CSGR_SSCG_MODE | RCC_PLL3CSGR_INC_STEP) , \ 3481 ((__RCC_PLL3_MOD_PER__) | (__RCC_PLL3_TPDFN_DIS__) | (__RCC_PLL3_RPDFN_DIS__) | \ 3482 (__RCC_PLL3_SSCG_MODE__) | ((__RCC_PLL3_INC_STEP__) << RCC_PLL3CSGR_INC_STEP_Pos)) ) ; \ 3483 } while(0) 3484 3485 3486 /** 3487 * @brief Macro to configure PLL3 clock source 3488 * @note This function must be used only when the PLL is disabled. 3489 * 3490 * @param __RCC_PLL3SOURCE__: specifies the PLL3 entry clock source. 3491 * This parameter can be one of the following values: 3492 * @arg RCC_PLL3SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 3493 * @arg RCC_PLL3SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 3494 * @arg RCC_PLL3SOURCE_CSI: HSE oscillator clock selected as PLL3 clock entry 3495 * @arg RCC_PLL3SOURCE_OFF: No clock send to DIVMx divider and PLL 3496 * @retval None 3497 */ 3498 #define __HAL_RCC_PLL3_SOURCE(__RCC_PLL3SOURCE__ ) \ 3499 do{ MODIFY_REG( RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC, (__RCC_PLL3SOURCE__)); \ 3500 } while(0) 3501 3502 /** @brief Macro to get the clock source used as PLL3 clock. 3503 * @retval The clock source used as PLL3 clock. The returned value can be one 3504 * of the following: 3505 * - RCC_PLL3SOURCE_HSI: HSI used as PLL3 clock. 3506 * - RCC_PLL3SOURCE_HSE: HSE used as PLL3 clock. 3507 * - RCC_PLL3SOURCE_CSI: CSI used as PLL3 clock. 3508 * - RCC_PLL3SOURCE_OFF: PLL3 clock is gated. 3509 */ 3510 #define __HAL_RCC_GET_PLL3_SOURCE() ((uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC)) 3511 3512 /** 3513 * @brief Macro to configure PLL3 multiplication and division factors. 3514 * @note This function must be used only when the PLL3 is disabled. 3515 * 3516 * @param __PLLM3__: specifies the division factor for PLL VCO input clock 3517 * This parameter must be a number between 1 and 64 3518 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3519 * frequency ranges from 4 to 16 MHz 3520 * @param __PLLN3__: specifies the multiplication factor for PLL VCO output clock 3521 * This parameter must be a number between 25 and 200 3522 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3523 * output frequency is between 400 to 800 MHz 3524 * @param __PLLP3__: specifies the division factor for the PLL3 P output 3525 * This parameter must be a number in the range 1 to 128 3526 * @param __PLLQ3__: specifies the division factor for for the PLL3 Q output 3527 * This parameter must be in the range 1 to 128 3528 * @param __PLLR3__: specifies the division factor for for the PLL3 R output 3529 * This parameter must be in the range 1 to 128 3530 * @retval None 3531 */ 3532 #define __HAL_RCC_PLL3_CONFIG(__PLLM3__, __PLLN3__, __PLLP3__, __PLLQ3__,__PLLR3__ ) \ 3533 do{ MODIFY_REG( RCC->PLL3CFGR1, (RCC_PLL3CFGR1_DIVN | RCC_PLL3CFGR1_DIVM3) , \ 3534 ( ((__PLLN3__) - 1U) | ( ((__PLLM3__) - 1U) << 16U) ) ); \ 3535 MODIFY_REG( RCC->PLL3CFGR2, (RCC_PLL3CFGR2_DIVP | RCC_PLL3CFGR2_DIVQ | RCC_PLL3CFGR2_DIVR), \ 3536 ( ((__PLLP3__) - 1U) | ( ((__PLLQ3__) - 1U) <<8U ) | ( ((__PLLR3__) - 1U) <<16U) )); \ 3537 } while(0) 3538 3539 /** 3540 * @brief Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor 3541 * 3542 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 3543 * 3544 * @param __RCC_PLL3FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL3 VCO 3545 * It should be a value between 0 and 8191 ((2^13)-1) 3546 * @note Warning: the software has to set correctly these bits to insure that the VCO 3547 * output frequency is between its valid frequency range, which is: 400 to 800 MHz 3548 * @retval None 3549 */ 3550 #define __HAL_RCC_PLL3FRACV_CONFIG(__RCC_PLL3FRACV__) \ 3551 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV, \ 3552 (uint32_t)(__RCC_PLL3FRACV__) << RCC_PLL3FRACR_FRACV_Pos) 3553 3554 3555 /** @brief Macro to select the PLL3 input frequency range. 3556 * @param __RCC_PLL3IFRange__: specifies the PLL3 input frequency range 3557 * This parameter can be one of the following values: 3558 * @arg RCC_PLL3IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset) 3559 * @arg RCC_PLL3IFRANGE_1: Range frequency is between 8 and 16 MHz 3560 * @retval None 3561 */ 3562 #define __HAL_RCC_PLL3_IFRANGE(__RCC_PLL3IFRange__) \ 3563 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE, (__RCC_PLL3IFRange__)) 3564 3565 3566 /** @brief Macros to enable or disable the PLL4. 3567 * @note After enabling the main PLL, the application software should wait on 3568 * PLLRDY flag to be set indicating that PLL clock is stable and can 3569 * be used as system clock source. 3570 * @note The PLL4 can not be disabled if it is used as MPU clock source 3571 * @note The PLL4 is disabled by hardware when entering STOP and STANDBY modes. 3572 */ 3573 #define __HAL_RCC_PLL4_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON ) 3574 #define __HAL_RCC_PLL4_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON) 3575 3576 /** 3577 * @brief Enables or disables each clock output 3578 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3579 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3580 * @param __RCC_PLL4ClockOut__: specifies the PLL clock to be outputed 3581 * This parameter can be one of the following values: 3582 * @arg RCC_PLL4_DIVP 3583 * @arg RCC_PLL4_DIVQ 3584 * @arg RCC_PLL4_DIVR 3585 * @retval None 3586 */ 3587 #define __HAL_RCC_PLL4CLKOUT_ENABLE(__RCC_PLL4ClockOut__) SET_BIT(RCC->PLL4CR, (__RCC_PLL4ClockOut__)) 3588 3589 #define __HAL_RCC_PLL4CLKOUT_DISABLE(__RCC_PLL4ClockOut__) CLEAR_BIT(RCC->PLL4CR, (__RCC_PLL4ClockOut__)) 3590 3591 3592 /** 3593 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL4 VCO 3594 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL4 3595 * @retval None 3596 */ 3597 3598 #define __HAL_RCC_PLL4FRACV_ENABLE() SET_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE) 3599 3600 #define __HAL_RCC_PLL4FRACV_DISABLE() CLEAR_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE) 3601 3602 3603 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL4 3604 */ 3605 #define __HAL_RCC_PLL4_SSMODE_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL) 3606 3607 #define __HAL_RCC_PLL4_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL) 3608 3609 3610 /** @brief Macro to config the PLL4 Clock Spreading Generator 3611 * @param __RCC_PLL4_MOD_PER__: Modulation Period Adjustment for PLL4 3612 * This parameter must have a value between 1 and 8191 3613 * 3614 * @param __RCC_PLL4_TPDFN_DIS__: Dithering TPDF noise control 3615 * This parameter can be one of the following values: 3616 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3617 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3618 3619 * @param __RCC_PLL4_RPDFN_DIS__: Dithering TPDF noise control 3620 * This parameter can be one of the following values: 3621 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3622 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3623 * 3624 * 3625 * @param __RCC_PLL4_SSCG_MODE__: Spread spectrum clock generator mode 3626 * This parameter can be one of the following values: 3627 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3628 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3629 * 3630 * @param __RCC_PLL4_INC_STEP__: Modulation Depth Adjustment for PLL4 3631 * This parameter must have a value between 1 and 32767 3632 * 3633 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3634 * @retval None 3635 */ 3636 #define __HAL_RCC_PLL4CSGCONFIG(__RCC_PLL4_MOD_PER__, __RCC_PLL4_TPDFN_DIS__, __RCC_PLL4_RPDFN_DIS__, \ 3637 __RCC_PLL4_SSCG_MODE__, __RCC_PLL4_INC_STEP__ ) \ 3638 do{ MODIFY_REG( RCC->PLL4CSGR, (RCC_PLL4CSGR_MOD_PER | RCC_PLL4CSGR_TPDFN_DIS | RCC_PLL4CSGR_RPDFN_DIS | \ 3639 RCC_PLL4CSGR_SSCG_MODE | RCC_PLL4CSGR_INC_STEP) , \ 3640 ((__RCC_PLL4_MOD_PER__) | (__RCC_PLL4_TPDFN_DIS__) | (__RCC_PLL4_RPDFN_DIS__) | \ 3641 (__RCC_PLL4_SSCG_MODE__) | ((__RCC_PLL4_INC_STEP__) << RCC_PLL4CSGR_INC_STEP_Pos)) ) ; \ 3642 } while(0) 3643 3644 3645 /** 3646 * @brief Macro to configure PLL4 clock source 3647 * @note This function must be used only when the PLL is disabled. 3648 * 3649 * @param __RCC_PLL4SOURCE__: specifies the PLL4 entry clock source. 3650 * This parameter can be one of the following values: 3651 * @arg RCC_PLL4SOURCE_HSI: HSI oscillator clock selected as PLL4 clock entry 3652 * @arg RCC_PLL4SOURCE_HSE: HSE oscillator clock selected as PLL4 clock entry 3653 * @arg RCC_PLL4SOURCE_CSI: HSE oscillator clock selected as PLL4 clock entry 3654 * @arg RCC_PLL4SOURCE_I2S_CKIN: Signal I2S_CKIN used as reference clock 3655 * @retval None 3656 */ 3657 #define __HAL_RCC_PLL4_SOURCE(__RCC_PLL4SOURCE__ ) \ 3658 do{ MODIFY_REG( RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC, (__RCC_PLL4SOURCE__)); \ 3659 } while(0) 3660 3661 /** @brief Macro to get the clock source used as PLL4 clock. 3662 * @retval The clock source used as PLL4 clock. The returned value can be one 3663 * of the following: 3664 * - RCC_PLL4SOURCE_HSI: HSI used as PLL4 clock. 3665 * - RCC_PLL4SOURCE_HSE: HSE used as PLL4 clock. 3666 * - RCC_PLL4SOURCE_CSI: CSI used as PLL4 clock. 3667 * - RCC_PLL4SOURCE_I2S_CKIN: I2S_CKIN used as PLL4 clock. 3668 */ 3669 #define __HAL_RCC_GET_PLL4_SOURCE() ((uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC)) 3670 3671 3672 /** 3673 * @brief Macro to configure PLL4 multiplication and division factors. 3674 * @note This function must be used only when the PLL4 is disabled. 3675 * 3676 * @param __PLLM4__: specifies the division factor for PLL VCO input clock 3677 * This parameter must be a number between 1 and 64 3678 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3679 * frequency ranges from 4 to 16 MHz 3680 * @param __PLLN4__: specifies the multiplication factor for PLL VCO output clock 3681 * This parameter must be a number between 25 and 200 3682 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3683 * output frequency is between 400 to 800 MHz 3684 * @param __PLLP4__: specifies the division factor for the PLL4 P output 3685 * This parameter must be a number in the range 1 to 128 3686 * @param __PLLQ4__: specifies the division factor for for the PLL4 Q output 3687 * This parameter must be in the range 1 to 128 3688 * @param __PLLR4__: specifies the division factor for for the PLL4 R output 3689 * This parameter must be in the range 1 to 128 3690 * @retval None 3691 */ 3692 #define __HAL_RCC_PLL4_CONFIG(__PLLM4__, __PLLN4__, __PLLP4__, __PLLQ4__,__PLLR4__ ) \ 3693 do{ MODIFY_REG( RCC->PLL4CFGR1, (RCC_PLL4CFGR1_DIVN | RCC_PLL4CFGR1_DIVM4) , \ 3694 ( ((__PLLN4__) - 1U) | ( ((__PLLM4__) - 1U) << 16U) ) ); \ 3695 MODIFY_REG( RCC->PLL4CFGR2, (RCC_PLL4CFGR2_DIVP | RCC_PLL4CFGR2_DIVQ | RCC_PLL4CFGR2_DIVR), \ 3696 ( ((__PLLP4__) - 1U) | ( ((__PLLQ4__) - 1U) <<8U ) | ( ((__PLLR4__) - 1U) <<16U) )); \ 3697 } while(0) 3698 3699 3700 /** 3701 * @brief Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor 3702 * 3703 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL4 VCO 3704 * 3705 * @param __RCC_PLL4FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL4 VCO 3706 * It should be a value between 0 and 8191 ((2^13)-1) 3707 * @note Warning: the software has to set correctly these bits to insure that the VCO 3708 * output frequency is between its valid frequency range, which is: 400 to 800 MHz 3709 * @retval None 3710 */ 3711 #define __HAL_RCC_PLL4FRACV_CONFIG(__RCC_PLL4FRACV__) \ 3712 MODIFY_REG(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV, \ 3713 (uint32_t)(__RCC_PLL4FRACV__) << RCC_PLL4FRACR_FRACV_Pos) 3714 3715 3716 /** @brief Macro to select the PLL4 input frequency range. 3717 * @param __RCC_PLL4IFRange__: specifies the PLL4 input frequency range 3718 * This parameter can be one of the following values: 3719 * @arg RCC_PLL4IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset) 3720 * @arg RCC_PLL4IFRANGE_1: Range frequency is between 8 and 16 MHz 3721 * @retval None 3722 */ 3723 #define __HAL_RCC_PLL4_IFRANGE(__RCC_PLL4IFRange__) \ 3724 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, (__RCC_PLL4IFRange__)) 3725 3726 3727 /** @brief Macros to enable or disable the MCO1 output. 3728 * 3729 */ 3730 #define __HAL_RCC_MCO1_ENABLE() SET_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON) 3731 #define __HAL_RCC_MCO1_DISABLE() CLEAR_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON) 3732 3733 /** 3734 * @brief Macro to configure MCO1 prescaler 3735 * @note Set and cleared by software to configure the prescaler of the MCO1. 3736 * @note Modification of this prescaler may generate glitches on MCO1. 3737 * @note It is highly recommended to change this prescaler only after reset, 3738 * before enabling the external oscillators and the PLLs. 3739 * 3740 * @param __RCC_MCO1SOURCE__: specifies the MCO1 entry clock source. 3741 * This parameter can be one of the following values: 3742 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 clock entry (default after reset) 3743 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 clock entry 3744 * @arg RCC_MCO1SOURCE_CSI: CSI clock selected as MCO1 clock entry 3745 * @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO1 clock entry 3746 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 clock entry 3747 * 3748 * @param __RCC_MCO1PRESCALER__: specifies the MCO1 prescaler value. 3749 * This parameter can be one of the following values: 3750 * @arg RCC_MCODIV_1: bypass (default after reset) 3751 * @arg RCC_MCODIV_2: division by 2 3752 * @arg RCC_MCODIV_3: division by 3 3753 * @arg RCC_MCODIV_4: division by 4 3754 * @arg RCC_MCODIV_5: division by 5 3755 * @arg RCC_MCODIV_6: division by 6 3756 * @arg RCC_MCODIV_7: division by 7 3757 * @arg RCC_MCODIV_8: division by 8 3758 * @arg RCC_MCODIV_9: division by 9 3759 * @arg RCC_MCODIV_10: division by 10 3760 * @arg RCC_MCODIV_11: division by 11 3761 * @arg RCC_MCODIV_12: division by 12 3762 * @arg RCC_MCODIV_13: division by 13 3763 * @arg RCC_MCODIV_14: division by 14 3764 * @arg RCC_MCODIV_15: division by 15 3765 * @arg RCC_MCODIV_16: division by 16 3766 * @retval None 3767 */ 3768 #define __HAL_RCC_MCO1_CONFIGURE(__RCC_MCO1SOURCE__ , __RCC_MCO1PRESCALER__ ) \ 3769 do{ MODIFY_REG( RCC->MCO1CFGR, (RCC_MCO1CFGR_MCO1SEL | RCC_MCO1CFGR_MCO1DIV) , \ 3770 ((__RCC_MCO1SOURCE__) | (__RCC_MCO1PRESCALER__)) );\ 3771 } while(0) 3772 3773 3774 /** @brief Macro to get the clock source used as MCO1 clock. 3775 * @retval The clock source used as MCO1 clock. The returned value can be one 3776 * of the following: 3777 * - RCC_MCO1SOURCE_HSI: HSI used as MCO1 clock (default after reset). 3778 * - RCC_MCO1SOURCE_HSE: HSE used as MCO1 clock. 3779 * - RCC_MCO1SOURCE_CSI: CSI used as MCO1 clock. 3780 * - RCC_MCO1SOURCE_LSI: LSI used as MCO1 clock. 3781 * - RCC_MCO1SOURCE_LSE: LSE used as MCO1 clock. 3782 */ 3783 #define __HAL_RCC_GET_MCO1_SOURCE() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1SEL)) 3784 3785 /** @brief Macro to get the MCO1 prescaler value 3786 * @retval The MCO1 prescaler value. The returned value can be one 3787 * of the following: 3788 * - RCC_MCODIV_1: bypass (default after reset) 3789 * - RCC_MCODIV_2: division by 2 3790 * - RCC_MCODIV_3: division by 3 3791 * - RCC_MCODIV_4: division by 4 3792 * - RCC_MCODIV_5: division by 5 3793 * - RCC_MCODIV_6: division by 6 3794 * - RCC_MCODIV_7: division by 7 3795 * - RCC_MCODIV_8: division by 8 3796 * - RCC_MCODIV_9: division by 9 3797 * - RCC_MCODIV_10: division by 10 3798 * - RCC_MCODIV_11: division by 11 3799 * - RCC_MCODIV_12: division by 12 3800 * - RCC_MCODIV_13: division by 13 3801 * - RCC_MCODIV_14: division by 14 3802 * - RCC_MCODIV_15: division by 15 3803 * - RCC_MCODIV_16: division by 16 3804 */ 3805 #define __HAL_RCC_GET_MCO1_DIV() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1DIV)) 3806 3807 3808 /** @brief Macros to enable or disable the MCO2 output. 3809 * 3810 */ 3811 #define __HAL_RCC_MCO2_ENABLE() SET_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON) 3812 #define __HAL_RCC_MCO2_DISABLE() CLEAR_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON) 3813 3814 /** 3815 * @brief Macro to configure MCO2 prescaler 3816 * @note Set and cleared by software to configure the prescaler of the MCO2. 3817 * @note Modification of this prescaler may generate glitches on MCO2. 3818 * @note It is highly recommended to change this prescaler only after reset, 3819 * before enabling the external oscillators and the PLLs. 3820 * 3821 * @param __RCC_MCO2SOURCE__: specifies the MCO2 entry clock source. 3822 * This parameter can be one of the following values: 3823 * @arg RCC_MCO2SOURCE_MPU: MPU clock selected as MCO2 clock entry (default after reset) 3824 * @arg RCC_MCO2SOURCE_AXI: AXI clock selected as MCO2 clock entry 3825 * @arg RCC_MCO2SOURCE_MCU: MCU clock selected as MCO2 clock entry 3826 * @arg RCC_MCO2SOURCE_PLL4: PLL4 clock selected as MCO2 clock entry 3827 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 clock entry 3828 * @arg RCC_MCO2SOURCE_HSI: HSI clock selected as MCO2 clock entry 3829 * 3830 * @param __RCC_MCO2PRESCALER__: specifies the MCO2 prescaler value. 3831 * This parameter can be one of the following values: 3832 * @arg RCC_MCODIV_1: bypass (default after reset) 3833 * @arg RCC_MCODIV_2: division by 2 3834 * @arg RCC_MCODIV_3: division by 3 3835 * @arg RCC_MCODIV_4: division by 4 3836 * @arg RCC_MCODIV_5: division by 5 3837 * @arg RCC_MCODIV_6: division by 6 3838 * @arg RCC_MCODIV_7: division by 7 3839 * @arg RCC_MCODIV_8: division by 8 3840 * @arg RCC_MCODIV_9: division by 9 3841 * @arg RCC_MCODIV_10: division by 10 3842 * @arg RCC_MCODIV_11: division by 11 3843 * @arg RCC_MCODIV_12: division by 12 3844 * @arg RCC_MCODIV_13: division by 13 3845 * @arg RCC_MCODIV_14: division by 14 3846 * @arg RCC_MCODIV_15: division by 15 3847 * @arg RCC_MCODIV_16: division by 16 3848 * @retval None 3849 */ 3850 #define __HAL_RCC_MCO2_CONFIGURE(__RCC_MCO2SOURCE__ , __RCC_MCO2PRESCALER__ ) \ 3851 do{ MODIFY_REG( RCC->MCO2CFGR, (RCC_MCO2CFGR_MCO2SEL | RCC_MCO2CFGR_MCO2DIV) , \ 3852 ((__RCC_MCO2SOURCE__) | (__RCC_MCO2PRESCALER__)));\ 3853 } while(0) 3854 3855 3856 /** @brief Macro to get the clock source used as MCO2 clock. 3857 * @retval The clock source used as MCO2 clock. The returned value can be one 3858 * of the following: 3859 * - RCC_MCO2SOURCE_MPU: MPU used as MCO2 clock (default after reset). 3860 * - RCC_MCO2SOURCE_AXI: AXI used as MCO2 clock. 3861 * - RCC_MCO2SOURCE_MCU: MCU used as MCO2 clock. 3862 * - RCC_MCO2SOURCE_PLL4: PLL4 used as MCO2 clock. 3863 * - RCC_MCO2SOURCE_HSE: HSE used as MCO2 clock. 3864 * - RCC_MCO2SOURCE_HSI: HSI used as MCO2 clock. 3865 */ 3866 #define __HAL_RCC_GET_MCO2_SOURCE() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2SEL)) 3867 3868 /** @brief Macro to get the MCO2 prescaler value 3869 * @retval The MCO2 prescaler value. The returned value can be one 3870 * of the following: 3871 * - RCC_MCODIV_1: bypass (default after reset) 3872 * - RCC_MCODIV_2: division by 2 3873 * - RCC_MCODIV_3: division by 3 3874 * - RCC_MCODIV_4: division by 4 3875 * - RCC_MCODIV_5: division by 5 3876 * - RCC_MCODIV_6: division by 6 3877 * - RCC_MCODIV_7: division by 7 3878 * - RCC_MCODIV_8: division by 8 3879 * - RCC_MCODIV_9: division by 9 3880 * - RCC_MCODIV_10: division by 10 3881 * - RCC_MCODIV_11: division by 11 3882 * - RCC_MCODIV_12: division by 12 3883 * - RCC_MCODIV_13: division by 13 3884 * - RCC_MCODIV_14: division by 14 3885 * - RCC_MCODIV_15: division by 15 3886 * - RCC_MCODIV_16: division by 16 3887 */ 3888 #define __HAL_RCC_GET_MCO2_DIV() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2DIV)) 3889 3890 3891 /** 3892 * @brief Macro to configure MPU sub-system clock source 3893 * @note Set and reset by software to select the MPU sub-system clock source (ck_mpuss) 3894 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3895 * @note Write access is not allowed during the clock restore sequence 3896 * 3897 * @param __RCC_MPUSOURCE__: specifies the MPU entry clock source. 3898 * This parameter can be one of the following values: 3899 * @arg RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset). 3900 * @arg RCC_MPUSOURCE_HSE: HSE used as MPU clock. 3901 * @arg RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock. 3902 * @arg RCC_MPUSOURCE_MPUDIV: MPUDIV used as MPU clock. 3903 */ 3904 #define __HAL_RCC_MPU_SOURCE(__RCC_MPUSOURCE__) \ 3905 do{ MODIFY_REG( RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC , (__RCC_MPUSOURCE__));\ 3906 } while(0) 3907 3908 /** @brief Macro to get the clock source used as MPU clock. 3909 * @retval The clock source used as MPU clock. The returned value can be one 3910 * of the following: 3911 * - RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset). 3912 * - RCC_MPUSOURCE_HSE: HSE used as MPU clock. 3913 * - RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock. 3914 * - RCC_MPUSOURCE_MPUDIV: MPU used as MPU clock. 3915 */ 3916 #define __HAL_RCC_GET_MPU_SOURCE() ((uint32_t)(RCC->MPCKSELR & RCC_MPCKSELR_MPUSRC)) 3917 3918 3919 /** 3920 * @brief Macro to configure AXISS clock source 3921 * @note Set and reset by software to select the AXI sub-system clock source (ck_axiss) 3922 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3923 * @note Write access is not allowed during the clock restore sequence 3924 * 3925 * @param __RCC_AXISSOURCE__: specifies the AXISS entry clock source. 3926 * This parameter can be one of the following values: 3927 * @arg RCC_AXISSOURCE_HSI: HSI used as AXISS clock (default after reset). 3928 * @arg RCC_AXISSOURCE_HSE: HSE used as AXISS clock. 3929 * @arg RCC_AXISSOURCE_PLL2: PLL2 used as AXISS clock. 3930 * @arg RCC_AXISSOURCE_OFF: AXISS clock is gated. 3931 */ 3932 #define __HAL_RCC_AXISS_SOURCE(__RCC_AXISSOURCE__) \ 3933 do{ MODIFY_REG( RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC , (__RCC_AXISSOURCE__));\ 3934 } while(0) 3935 3936 /** @brief Macro to get the clock source used as AXIS clock. 3937 * @retval The clock source used as AXIS clock. The returned value can be one 3938 * of the following: 3939 * - RCC_AXISSOURCE_HSI: HSI used as AXIS clock (default after reset). 3940 * - RCC_AXISSOURCE_HSE: HSE used as AXIS clock. 3941 * - RCC_AXISSOURCE_PLL2: PLL2 used as AXIS clock. 3942 * - RCC_AXISSOURCE_OFF: AXIS clock is gated. 3943 */ 3944 #define __HAL_RCC_GET_AXIS_SOURCE() ((uint32_t)(RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRC)) 3945 3946 3947 /** 3948 * @brief Macro to configure MCU sub-system clock source 3949 * @note Set and reset by software to select the mcu sub-system clock source (ck_mcuss) 3950 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3951 * @note Write access is not allowed during the clock restore sequence 3952 * 3953 * @param __RCC_MCUSSOURCE__: specifies the MCU entry clock source. 3954 * This parameter can be one of the following values: 3955 * @arg RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset). 3956 * @arg RCC_MCUSSOURCE_HSE: HSE used as MCU clock. 3957 * @arg RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock. 3958 */ 3959 #define __HAL_RCC_MCU_SOURCE(__RCC_MCUSSOURCE__) \ 3960 do{ MODIFY_REG( RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC , (__RCC_MCUSSOURCE__));\ 3961 } while(0) 3962 3963 /** @brief Macro to get the clock source used as MCU clock. 3964 * @retval The clock source used as MCU clock. The returned value can be one 3965 * of the following: 3966 * - RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset). 3967 * - RCC_MCUSSOURCE_HSE: HSE used as MCU clock. 3968 * - RCC_MCUSSOURCE_CSI: CSI used as MCU clock. 3969 * - RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock. 3970 */ 3971 #define __HAL_RCC_GET_MCU_SOURCE() ((uint32_t)(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)) 3972 3973 3974 3975 /** 3976 * @brief Macro to set the HSE division factor for RTC clock 3977 * @note Set and cleared by software to divide the HSE to generate a clock for RTC. 3978 * @note If TZEN = 1, this parameter can only be modified in secure mode 3979 * @note Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is lower than 4 MHz. 3980 * @note These bits must be configured if needed before selecting the RTC clock source 3981 * 3982 * @param __HSEDIV__: Specifies the HSE division factor for RTC clock 3983 * This parameter must be a number between 1 and 64. Eg.: 3984 * 1: HSE (default after reset) 3985 * 2: HSE/2 3986 * 64: HSE/64 3987 * @retval None 3988 */ 3989 #define __HAL_RCC_RTC_HSEDIV(__HSEDIV__) \ 3990 do{ MODIFY_REG( RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV , ((__HSEDIV__) -1U )); \ 3991 } while(0) 3992 3993 /** @brief Macro to get the HSE division factor for RTC clock. 3994 * @retval The HSE division factor for RTC clock. The returned value can be a number between 1 and 64 Eg.: 3995 * 1: HSE (default after reset) 3996 * 2: HSE/2 3997 * 64: HSE/64 3998 */ 3999 #define __HAL_RCC_GET_RTC_HSEDIV() ((uint32_t)((RCC->RTCDIVR & RCC_RTCDIVR_RTCDIV) + 1U )) 4000 4001 /** 4002 * @brief Macro to configure MPU Core clock divider 4003 * @note Set and reset by software to control the MPU clock division factor. 4004 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4005 * @note It is possible to change this division ratio on-the-fly. It impacts only the frequency of MPU clock. 4006 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mpuss cycles after MPUDIV update. 4007 * @note The application can check if the new division factor is taken into account by reading back the MPUDIVRDY flag 4008 * 4009 * @param __RCC_MPUDIV__: specifies the MPU division factor 4010 * This parameter can be one of the following values: 4011 * @arg RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset) 4012 * @arg RCC_MPU_DIV2: ck_mpuss divided by 2 4013 * @arg RCC_MPU_DIV4: ck_mpuss divided by 4 4014 * @arg RCC_MPU_DIV8: ck_mpuss divided by 8 4015 * @arg RCC_MPU_DIV16: ck_mpuss divided by 16 4016 * 4017 * @note Warning: Do not set RCC_MPU_DIV_OFF if the MPUSRC = RCC_MPUSOURCE_MPUDIV, 4018 * otherwise the processor will no longer be clocked 4019 */ 4020 #define __HAL_RCC_MPU_DIV(__RCC_MPUDIV__) \ 4021 do{ MODIFY_REG( RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV , (__RCC_MPUDIV__));\ 4022 } while(0) 4023 4024 /** @brief Macro to get the MPU clock division factor. 4025 * @retval The MPU clock division factor. The returned value can be one 4026 * of the following: 4027 * - RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset) 4028 * - RCC_MPU_DIV2: ck_mpuss divided by 2 4029 * - RCC_MPU_DIV4: ck_mpuss divided by 4 4030 * - RCC_MPU_DIV8: ck_mpuss divided by 8 4031 * - RCC_MPU_DIV16: ck_mpuss divided by 16 4032 */ 4033 #define __HAL_RCC_GET_MPU_DIV() ((uint32_t)(RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIV )) 4034 4035 4036 /** 4037 * @brief Macro to configure AXI Core clock divider 4038 * @note Set and reset by software to control the AXI, AHB5 and AHB6 clock division factor. 4039 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4040 * @note It is possible to change this division ratio on-the-fly. It impacts the frequency 4041 * of AXI, APB4, APB5 AHB5 and AHB6 clocks. 4042 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_axiss cycles after AXIDIV update. 4043 * @note The application can check if the new division factor is taken into account by reading back the AXIDIVRDY flag 4044 * 4045 * @param __RCC_AXIDIV__: specifies the AXI division factor 4046 * This parameter can be one of the following values: 4047 * @arg RCC_AXI_DIV1: ck_axiss not divided (default after reset) 4048 * @arg RCC_AXI_DIV2: ck_axiss divided by 2 4049 * @arg RCC_AXI_DIV3: ck_axiss divided by 3 4050 * @arg RCC_AXI_DIV4: ck_axiss divided by 4 4051 */ 4052 #define __HAL_RCC_AXI_DIV(__RCC_AXIDIV__) \ 4053 do{ MODIFY_REG( RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV , (__RCC_AXIDIV__));\ 4054 } while(0) 4055 4056 /** @brief Macro to get the AXI, AHB5 and AHB6 clock division factor. 4057 * @retval The AXI clock division factor. The returned value can be one 4058 * of the following: 4059 * - RCC_AXI_DIV1: ck_axiss not divided (default after reset) 4060 * - RCC_AXI_DIV2: ck_axiss divided by 2 4061 * - RCC_AXI_DIV3: ck_axiss divided by 3 4062 * - RCC_AXI_DIV4: ck_axiss divided by 4 4063 */ 4064 #define __HAL_RCC_GET_AXI_DIV() ((uint32_t)(RCC->AXIDIVR & RCC_AXIDIVR_AXIDIV )) 4065 4066 4067 /** 4068 * @brief Macro to configure APB4 clock divider 4069 * @note Set and reset by software to control the APB4 clock division factor. 4070 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4071 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB4 clock. 4072 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB4DIV update. 4073 * @note The application can check if the new division factor is taken into account by reading back the APB4DIVRDY flag 4074 * 4075 * @param __RCC_APB4DIV__: specifies the APB4 division factor 4076 * This parameter can be one of the following values: 4077 * @arg RCC_APB4_DIV1: ck_aclk not divided (default after reset) 4078 * @arg RCC_APB4_DIV2: ck_aclk divided by 2 4079 * @arg RCC_APB4_DIV4: ck_aclk divided by 4 4080 * @arg RCC_APB4_DIV8: ck_aclk divided by 8 4081 * @arg RCC_APB4_DIV16: ck_aclk divided by 16 4082 */ 4083 #define __HAL_RCC_APB4_DIV(__RCC_APB4DIV__) \ 4084 do{ MODIFY_REG( RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV , (__RCC_APB4DIV__));\ 4085 } while(0) 4086 4087 /** @brief Macro to get the APB4 clock division factor. 4088 * @retval The APB4 clock division factor. The returned value can be one 4089 * of the following: 4090 * - RCC_APB4_DIV1: ck_aclk not divided (default after reset) 4091 * - RCC_APB4_DIV2: ck_aclk divided by 2 4092 * - RCC_APB4_DIV4: ck_aclk divided by 4 4093 * - RCC_APB4_DIV8: ck_aclk divided by 8 4094 * - RCC_APB4_DIV16: ck_aclk divided by 16 4095 */ 4096 #define __HAL_RCC_GET_APB4_DIV() ((uint32_t)(RCC->APB4DIVR & RCC_APB4DIVR_APB4DIV )) 4097 4098 4099 /** 4100 * @brief Macro to configure APB5 clock divider 4101 * @note Set and reset by software to control the APB5 clock division factor. 4102 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4103 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB5 clock. 4104 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB5DIV update. 4105 * @note The application can check if the new division factor is taken into account by reading back the APB5DIVRDY flag 4106 * 4107 * @param __RCC_APB5DIV__: specifies the APB5 division factor 4108 * This parameter can be one of the following values: 4109 * @arg RCC_APB5_DIV1: ck_aclk not divided (default after reset) 4110 * @arg RCC_APB5_DIV2: ck_aclk divided by 2 4111 * @arg RCC_APB5_DIV4: ck_aclk divided by 4 4112 * @arg RCC_APB5_DIV8: ck_aclk divided by 8 4113 * @arg RCC_APB5_DIV16: ck_aclk divided by 16 4114 */ 4115 #define __HAL_RCC_APB5_DIV(__RCC_APB5DIV__) \ 4116 do{ MODIFY_REG( RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV , (__RCC_APB5DIV__));\ 4117 } while(0) 4118 4119 /** @brief Macro to get the APB5 clock division factor. 4120 * @retval The APB5 clock division factor. The returned value can be one 4121 * of the following: 4122 * - RCC_APB5_DIV1: ck_aclk not divided (default after reset) 4123 * - RCC_APB5_DIV2: ck_aclk divided by 2 4124 * - RCC_APB5_DIV4: ck_aclk divided by 4 4125 * - RCC_APB5_DIV8: ck_aclk divided by 8 4126 * - RCC_APB5_DIV16: ck_aclk divided by 16 4127 */ 4128 #define __HAL_RCC_GET_APB5_DIV() ((uint32_t)(RCC->APB5DIVR & RCC_APB5DIVR_APB5DIV )) 4129 4130 4131 /** 4132 * @brief Macro to configure MCU clock divider 4133 * @note Set and reset by software to control the MCU clock division factor. 4134 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4135 * @note Changing this division ratio has an impact on the frequency of MCU clock, and all bus matrix clocks. 4136 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mcuss cycles after MCUDIV update. 4137 * @note The application can check if the new division factor is taken into account by reading back the MCUDIVRDY flag 4138 * 4139 * @param __RCC_MCUDIV__: specifies the MCU division factor 4140 * This parameter can be one of the following values: 4141 * @arg RCC_MCU_DIV1: ck_mcuss not divided (default after reset) 4142 * @arg RCC_MCU_DIV2: ck_mcuss divided by 2 4143 * @arg RCC_MCU_DIV4: ck_mcuss divided by 4 4144 * @arg RCC_MCU_DIV8: ck_mcuss divided by 8 4145 * @arg RCC_MCU_DIV16: ck_mcuss divided by 16 4146 * @arg RCC_MCU_DIV32: ck_mcuss divided by 32 4147 * @arg RCC_MCU_DIV64: ck_mcuss divided by 64 4148 * @arg RCC_MCU_DIV128: ck_mcuss divided by 128 4149 * @arg RCC_MCU_DIV256: ck_mcuss divided by 256 4150 * @arg RCC_MCU_DIV512: ck_mcuss divided by 512 4151 */ 4152 #define __HAL_RCC_MCU_DIV(__RCC_MCUDIV__) \ 4153 do{ MODIFY_REG( RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV , (__RCC_MCUDIV__));\ 4154 } while(0) 4155 4156 /** @brief Macro to get the MCU clock division factor. 4157 * @retval The MCU clock division factor. The returned value can be one 4158 * of the following: 4159 * - RCC_MCU_DIV1: ck_mcuss not divided (default after reset) 4160 * - RCC_MCU_DIV2: ck_mcuss divided by 2 4161 * - RCC_MCU_DIV4: ck_mcuss divided by 4 4162 * - RCC_MCU_DIV8: ck_mcuss divided by 8 4163 * - RCC_MCU_DIV16: ck_mcuss divided by 16 4164 * - RCC_MCU_DIV32: ck_mcuss divided by 32 4165 * - RCC_MCU_DIV64: ck_mcuss divided by 64 4166 * - RCC_MCU_DIV128: ck_mcuss divided by 128 4167 * - RCC_MCU_DIV256: ck_mcuss divided by 256 4168 * - RCC_MCU_DIV512: ck_mcuss divided by 512 4169 */ 4170 #define __HAL_RCC_GET_MCU_DIV() ((uint32_t)(RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV )) 4171 4172 /** 4173 * @brief Macro to configure APB1 clock divider 4174 * @note Set and reset by software to control the APB1 clock division factor. 4175 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB1 clock. 4176 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB1DIV update. 4177 * @note The application can check if the new division factor is taken into account by reading back the APB1DIVRDY flag 4178 * 4179 * @param __RCC_APB1DIV__: specifies the APB1 division factor 4180 * This parameter can be one of the following values: 4181 * @arg RCC_APB1_DIV1: ck_hclk not divided (default after reset) 4182 * @arg RCC_APB1_DIV2: ck_hclk divided by 2 4183 * @arg RCC_APB1_DIV4: ck_hclk divided by 4 4184 * @arg RCC_APB1_DIV8: ck_hclk divided by 8 4185 * @arg RCC_APB1_DIV16: ck_hclk divided by 16 4186 */ 4187 #define __HAL_RCC_APB1_DIV(__RCC_APB1DIV__) \ 4188 do{ MODIFY_REG( RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV , (__RCC_APB1DIV__));\ 4189 } while(0) 4190 4191 /** @brief Macro to get the APB1 clock division factor. 4192 * @retval The APB1 clock division factor. The returned value can be one 4193 * of the following: 4194 * - RCC_APB1_DIV1: ck_hclk not divided (default after reset) 4195 * - RCC_APB1_DIV2: ck_hclk divided by 2 4196 * - RCC_APB1_DIV4: ck_hclk divided by 4 4197 * - RCC_APB1_DIV8: ck_hclk divided by 8 4198 * - RCC_APB1_DIV16: ck_hclk divided by 16 4199 */ 4200 #define __HAL_RCC_GET_APB1_DIV() ((uint32_t)(RCC->APB1DIVR & RCC_APB1DIVR_APB1DIV )) 4201 4202 4203 /** 4204 * @brief Macro to configure APB2 clock divider 4205 * @note Set and reset by software to control the APB2 clock division factor. 4206 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB2 clock. 4207 4208 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB2DIV update. 4209 * @note The application can check if the new division factor is taken into account by reading back the APB2DIVRDY flag 4210 * 4211 * @param __RCC_APB2DIV__: specifies the APB2 division factor 4212 * This parameter can be one of the following values: 4213 * @arg RCC_APB2_DIV1: ck_hclk not divided (default after reset) 4214 * @arg RCC_APB2_DIV2: ck_hclk divided by 2 4215 * @arg RCC_APB2_DIV4: ck_hclk divided by 4 4216 * @arg RCC_APB2_DIV8: ck_hclk divided by 8 4217 * @arg RCC_APB2_DIV16: ck_hclk divided by 16 4218 */ 4219 #define __HAL_RCC_APB2_DIV(__RCC_APB2DIV__) \ 4220 do{ MODIFY_REG( RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV , (__RCC_APB2DIV__));\ 4221 } while(0) 4222 4223 /** @brief Macro to get the APB2 clock division factor. 4224 * @retval The APB2 clock division factor. The returned value can be one 4225 * of the following: 4226 * - RCC_APB2_DIV1: ck_hclk not divided (default after reset) 4227 * - RCC_APB2_DIV2: ck_hclk divided by 2 4228 * - RCC_APB2_DIV4: ck_hclk divided by 4 4229 * - RCC_APB2_DIV8: ck_hclk divided by 8 4230 * - RCC_APB2_DIV16: ck_hclk divided by 16 4231 */ 4232 #define __HAL_RCC_GET_APB2_DIV() ((uint32_t)(RCC->APB2DIVR & RCC_APB2DIVR_APB2DIV )) 4233 4234 4235 /** 4236 * @brief Macro to configure APB3 clock divider 4237 * @note Set and reset by software to control the APB3 clock division factor. 4238 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB3 clock. 4239 4240 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB3DIV update. 4241 * @note The application can check if the new division factor is taken into account by reading back the APB3DIVRDY flag 4242 * 4243 * @param __RCC_APB3DIV__: specifies the APB3 division factor 4244 * This parameter can be one of the following values: 4245 * @arg RCC_APB3_DIV1: ck_hclk not divided (default after reset) 4246 * @arg RCC_APB3_DIV2: ck_hclk divided by 2 4247 * @arg RCC_APB3_DIV4: ck_hclk divided by 4 4248 * @arg RCC_APB3_DIV8: ck_hclk divided by 8 4249 * @arg RCC_APB3_DIV16: ck_hclk divided by 16 4250 */ 4251 #define __HAL_RCC_APB3_DIV(__RCC_APB3DIV__) \ 4252 do{ MODIFY_REG( RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV , (__RCC_APB3DIV__));\ 4253 } while(0) 4254 4255 /** @brief Macro to get the APB3 clock division factor. 4256 * @retval The APB3 clock division factor. The returned value can be one 4257 * of the following: 4258 * - RCC_APB3_DIV1: ck_hclk not divided (default after reset) 4259 * - RCC_APB3_DIV2: ck_hclk divided by 2 4260 * - RCC_APB3_DIV4: ck_hclk divided by 4 4261 * - RCC_APB3_DIV8: ck_hclk divided by 8 4262 * - RCC_APB3_DIV16: ck_hclk divided by 16 4263 */ 4264 #define __HAL_RCC_GET_APB3_DIV() ((uint32_t)(RCC->APB3DIVR & RCC_APB3DIVR_APB3DIV )) 4265 4266 4267 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR bits to enable 4268 * the selected interrupts). 4269 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4270 * This parameter can be any combination of the following values: 4271 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4272 * @arg RCC_IT_LSERDY: LSE ready interrupt 4273 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4274 * @arg RCC_IT_HSERDY: HSE ready interrupt 4275 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4276 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4277 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4278 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4279 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4280 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4281 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4282 * @arg RCC_IT_ALL: All RCC interrupts 4283 */ 4284 #ifdef CORE_CM4 4285 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MC_CIER, (__INTERRUPT__)) 4286 #endif /* CORE_CM4 */ 4287 #ifdef CORE_CA7 4288 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MP_CIER, (__INTERRUPT__)) 4289 #endif /* CORE_CA7 */ 4290 4291 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 4292 * the selected interrupts). 4293 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4294 * This parameter can be any combination of the following values: 4295 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4296 * @arg RCC_IT_LSERDY: LSE ready interrupt 4297 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4298 * @arg RCC_IT_HSERDY: HSE ready interrupt 4299 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4300 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4301 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4302 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4303 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4304 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4305 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4306 * @arg RCC_IT_ALL: All RCC interrupts 4307 */ 4308 #ifdef CORE_CM4 4309 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MC_CIER, (__INTERRUPT__)) 4310 #endif /* CORE_CM4 */ 4311 #ifdef CORE_CA7 4312 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MP_CIER, (__INTERRUPT__)) 4313 #endif /* CORE_CA7 */ 4314 4315 4316 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 4317 * bits to clear the selected interrupt pending bits. 4318 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4319 * This parameter can be any combination of the following values: 4320 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4321 * @arg RCC_IT_LSERDY: LSE ready interrupt 4322 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4323 * @arg RCC_IT_HSERDY: HSE ready interrupt 4324 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4325 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4326 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4327 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4328 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4329 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4330 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4331 * @arg RCC_IT_ALL: All RCC interrupts 4332 */ 4333 #ifdef CORE_CM4 4334 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MC_CIFR = (__INTERRUPT__)) 4335 #endif /* CORE_CM4 */ 4336 #ifdef CORE_CA7 4337 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MP_CIFR = (__INTERRUPT__)) 4338 #endif /* CORE_CA7 */ 4339 4340 /** @brief Check the RCC's interrupt has occurred or not. 4341 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4342 * This parameter can be one of the following values: 4343 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4344 * @arg RCC_IT_LSERDY: LSE ready interrupt 4345 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4346 * @arg RCC_IT_HSERDY: HSE ready interrupt 4347 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4348 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4349 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4350 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4351 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4352 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4353 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4354 * @arg RCC_IT_ALL: All RCC interrupts 4355 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4356 */ 4357 #ifdef CORE_CM4 4358 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MC_CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4359 #endif /* CORE_CM4 */ 4360 #ifdef CORE_CA7 4361 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MP_CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4362 #endif /* CORE_CA7 */ 4363 /** 4364 * @} 4365 */ 4366 /* Include RCC HAL Extension module */ 4367 #include "stm32mp1xx_hal_rcc_ex.h" 4368 4369 /* Exported functions --------------------------------------------------------*/ 4370 /** @addtogroup RCC_Exported_Functions RCC Exported Functions 4371 * @{ 4372 */ 4373 4374 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 4375 * @{ 4376 */ 4377 /* Initialization and de-initialization functions ******************************/ 4378 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4379 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4380 HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State); 4381 HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State); 4382 4383 HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1); 4384 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct); 4385 HAL_StatusTypeDef HAL_RCC_LSEDriveConfig(uint32_t LseDriveValue); 4386 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4387 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4388 4389 void HAL_RCC_WAKEUP_IRQHandler(void); 4390 void HAL_RCC_WAKEUP_Callback(void); 4391 void HAL_RCC_IRQHandler(void); 4392 void HAL_RCC_Callback(uint32_t Flags); 4393 void HAL_RCC_EnableHSECSS(void); 4394 4395 4396 /** 4397 * @} 4398 */ 4399 4400 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions 4401 * @{ 4402 */ 4403 /* Peripheral Control functions ************************************************/ 4404 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4405 /* Get frequency functions *****************************************************/ 4406 void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); 4407 void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); 4408 void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); 4409 void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks); 4410 4411 uint32_t HAL_RCC_GetMPUSSFreq(void); 4412 uint32_t HAL_RCC_GetAXISSFreq(void); 4413 uint32_t HAL_RCC_GetMCUSSFreq(void); 4414 uint32_t HAL_RCC_GetACLKFreq(void); 4415 uint32_t HAL_RCC_GetHCLK1Freq(void); 4416 uint32_t HAL_RCC_GetHCLK2Freq(void); 4417 uint32_t HAL_RCC_GetHCLK3Freq(void); 4418 uint32_t HAL_RCC_GetHCLK4Freq(void); 4419 uint32_t HAL_RCC_GetHCLK5Freq(void); 4420 uint32_t HAL_RCC_GetHCLK6Freq(void); 4421 uint32_t HAL_RCC_GetMCUFreq(void); 4422 uint32_t HAL_RCC_GetFCLKFreq(void); 4423 uint32_t HAL_RCC_GetMLHCLKFreq(void); 4424 uint32_t HAL_RCC_GetPCLK1Freq(void); 4425 uint32_t HAL_RCC_GetPCLK2Freq(void); 4426 uint32_t HAL_RCC_GetPCLK3Freq(void); 4427 uint32_t HAL_RCC_GetPCLK4Freq(void); 4428 uint32_t HAL_RCC_GetPCLK5Freq(void); 4429 4430 uint32_t HAL_RCC_GetSystemCoreClockFreq(void); 4431 4432 uint32_t RCC_GetCKPERFreq(void); 4433 /** 4434 * @} 4435 */ 4436 4437 /** 4438 * @} 4439 */ 4440 4441 /* Private types -------------------------------------------------------------*/ 4442 /* Private variables ---------------------------------------------------------*/ 4443 /* Private constants ---------------------------------------------------------*/ 4444 /** @defgroup RCC_Private_Constants RCC Private Constants 4445 * @{ 4446 */ 4447 4448 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 4449 #define HSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4450 #define CSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4451 #define LSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4452 #define PLL_TIMEOUT_VALUE (100U) /* 100 ms */ 4453 #define CLOCKSWITCH_TIMEOUT_VALUE (1000U) /* 1 s */ 4454 4455 /** 4456 * @} 4457 */ 4458 4459 /* Private macros ------------------------------------------------------------*/ 4460 /** @addtogroup RCC_Private_Macros RCC Private Macros 4461 * @{ 4462 */ 4463 4464 /** 4465 * @} 4466 */ 4467 4468 4469 /** 4470 * @} 4471 */ 4472 4473 /** 4474 * @} 4475 */ 4476 #ifdef __cplusplus 4477 } 4478 #endif 4479 4480 #endif /* __STM32MP1xx_HAL_RCC_H */ 4481
