1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32U5xx_HAL_RCC_EX_H 22 #define STM32U5xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PLL2 Clock structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. 50 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 51 52 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 53 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 54 55 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 56 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 57 58 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 59 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 60 61 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 62 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 63 64 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 66 odd division factors are not allowed */ 67 68 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 69 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 70 71 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 72 PLL2 VCO It should be a value between 0 and 8191 */ 73 74 uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. 75 This parameter must be a value of @ref RCC_PLL2_Clock_Output */ 76 } RCC_PLL2InitTypeDef; 77 78 79 /** 80 * @brief PLL3 Clock structure definition 81 */ 82 typedef struct 83 { 84 uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. 85 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 86 87 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 88 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 89 90 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 91 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 92 93 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 94 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 95 96 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 97 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 98 99 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 100 This parameter must be a number between Min_Data = 1 and Max_Data = 128 101 odd division factors are not allowed */ 102 103 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 104 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 105 106 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 107 PLL3 VCO It should be a value between 0 and 8191 */ 108 109 uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. 110 This parameter must be a value of @ref RCC_PLL3_Clock_Output */ 111 } RCC_PLL3InitTypeDef; 112 113 /** 114 * @brief RCC PLL1 Clocks structure definition 115 */ 116 typedef struct 117 { 118 uint32_t PLL1_P_Frequency; 119 uint32_t PLL1_Q_Frequency; 120 uint32_t PLL1_R_Frequency; 121 } PLL1_ClocksTypeDef; 122 123 /** 124 * @brief RCC PLL2 Clocks structure definition 125 */ 126 typedef struct 127 { 128 uint32_t PLL2_P_Frequency; 129 uint32_t PLL2_Q_Frequency; 130 uint32_t PLL2_R_Frequency; 131 } PLL2_ClocksTypeDef; 132 133 /** 134 * @brief RCC PLL3 Clocks structure definition 135 */ 136 typedef struct 137 { 138 uint32_t PLL3_P_Frequency; 139 uint32_t PLL3_Q_Frequency; 140 uint32_t PLL3_R_Frequency; 141 } PLL3_ClocksTypeDef; 142 143 144 /** 145 * @brief RCC extended clocks structure definition 146 */ 147 typedef struct 148 { 149 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 150 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 151 152 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 153 This parameter will be used only when PLL2 is selected as kernel clock Source 154 for some peripherals */ 155 156 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 157 This parameter will be used only when PLL2 is selected as kernel clock Source 158 for some peripherals */ 159 160 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 161 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 162 163 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 164 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 165 166 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 167 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 168 169 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 170 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 171 172 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 173 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 174 175 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 176 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 177 178 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 179 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 180 181 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 182 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 183 184 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 185 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 186 187 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 188 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 189 190 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 191 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 192 193 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 194 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 195 196 uint32_t Lptim34ClockSelection; /*!< Specifies LPTIM3 and LPTIM4 clock source. 197 This parameter can be a value of @ref RCCEx_LPTIM34_Clock_Source */ 198 199 uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 kernel clock source. 200 This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ 201 202 uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 kernel clock source. 203 This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ 204 205 uint32_t Adf1ClockSelection; /*!< Specifies Adf1 kernel clock source. 206 This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ 207 208 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 209 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 210 211 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 212 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 213 214 uint32_t RngClockSelection; /*!< Specifies RNG clock source 215 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 216 217 uint32_t SaesClockSelection; /*!< Specifies SAES clock source 218 This parameter can be a value of @ref RCCEx_SAES_Clock_Source */ 219 220 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB, RNG and SDMMC1 221 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 222 223 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC1/2 clock source. 224 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 225 226 uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC4 and DAC interface clock source. 227 This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ 228 229 uint32_t Dac1ClockSelection; /*!< Specifies DAC1 interface clock source. 230 This parameter can be a value of @ref RCCEx_DAC1_Clock_Source */ 231 232 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 233 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 234 235 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 236 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 237 238 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source 239 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 240 241 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source 242 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 243 244 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 245 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 246 } RCC_PeriphCLKInitTypeDef; 247 248 #if defined(CRS) 249 250 /** 251 * @brief RCC_CRS Init structure definition 252 */ 253 typedef struct 254 { 255 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 256 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 257 258 uint32_t Source; /*!< Specifies the SYNC signal source. 259 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 260 261 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 262 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 263 264 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 265 event. It can be calculated in using macro 266 __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 267 This parameter must be a number between 0 and 0xFFFF or a value of 268 @ref RCCEx_CRS_ReloadValueDefault .*/ 269 270 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 271 This parameter must be a number between 0 and 0xFF or a value of 272 @ref RCCEx_CRS_ErrorLimitDefault */ 273 274 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 275 This parameter must be a number between 0 and 0x3F or a value of 276 @ref RCCEx_CRS_HSI48CalibrationDefault */ 277 278 } RCC_CRSInitTypeDef; 279 280 /** 281 * @brief RCC_CRS Synchronization structure definition 282 */ 283 typedef struct 284 { 285 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 286 This parameter must be a number between 0 and 0xFFFF */ 287 288 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 289 This parameter must be a number between 0 and 0x3F */ 290 291 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 292 value latched in the time of the last SYNC event. 293 This parameter must be a number between 0 and 0xFFFF */ 294 295 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 296 frequency error counter latched in the time of the last SYNC event. 297 It shows whether the actual frequency is below or above the target. 298 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 299 300 } RCC_CRSSynchroInfoTypeDef; 301 302 #endif /* CRS */ 303 /** 304 * @} 305 */ 306 307 308 /* Exported constants --------------------------------------------------------*/ 309 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 310 * @{ 311 */ 312 313 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 314 * @{ 315 */ 316 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 317 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup RCCEx_MSI_Pll_Mode_Selection MSI Pll Mode Selection 323 * @{ 324 */ 325 #define RCC_MSIKPLL_MODE_SEL 0x00000000U /*!< PLL mode applied to MSIK (MSI kernel) clock output */ 326 #define RCC_MSISPLL_MODE_SEL RCC_CR_MSIPLLSEL /*!< PLL mode applied to MSIS (MSI system) clock output */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 332 * @{ 333 */ 334 #define RCC_PERIPHCLK_USART1 0x00000001U 335 #define RCC_PERIPHCLK_USART2 0x00000002U 336 #define RCC_PERIPHCLK_USART3 0x00000004U 337 #define RCC_PERIPHCLK_UART4 0x00000008U 338 #define RCC_PERIPHCLK_UART5 0x00000010U 339 #define RCC_PERIPHCLK_LPUART1 0x00000020U 340 #define RCC_PERIPHCLK_I2C1 0x00000040U 341 #define RCC_PERIPHCLK_I2C2 0x00000080U 342 #define RCC_PERIPHCLK_I2C3 0x00000100U 343 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 344 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 345 #define RCC_PERIPHCLK_LPTIM34 0x00000800U 346 #define RCC_PERIPHCLK_SAES 0x00001000U 347 #define RCC_PERIPHCLK_SAI1 0x00002000U 348 #define RCC_PERIPHCLK_SAI2 0x00004000U 349 #define RCC_PERIPHCLK_ADCDAC 0x00008000U 350 #define RCC_PERIPHCLK_MDF1 0x00010000U 351 #define RCC_PERIPHCLK_ADF1 0x00020000U 352 #define RCC_PERIPHCLK_RTC 0x00040000U 353 #define RCC_PERIPHCLK_RNG 0x00080000U 354 #define RCC_PERIPHCLK_CLK48 0x00100000U 355 #define RCC_PERIPHCLK_SDMMC 0x00200000U 356 #define RCC_PERIPHCLK_I2C4 0x00400000U 357 #define RCC_PERIPHCLK_SPI1 0x00800000U 358 #define RCC_PERIPHCLK_SPI2 0x01000000U 359 #define RCC_PERIPHCLK_SPI3 0x02000000U 360 #define RCC_PERIPHCLK_OSPI 0x04000000U 361 #define RCC_PERIPHCLK_FDCAN1 0x08000000U 362 #define RCC_PERIPHCLK_DAC1 0x10000000U 363 364 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ 365 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ 366 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 367 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ 368 RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 369 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ 370 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_CLK48 | \ 371 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ 372 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ 373 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) 374 /** 375 * @} 376 */ 377 378 379 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 380 * @{ 381 */ 382 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN 383 #define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN 384 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN 385 /** 386 * @} 387 */ 388 389 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 390 * @{ 391 */ 392 #define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN 393 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN 394 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN 395 /** 396 * @} 397 */ 398 399 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 400 * @{ 401 */ 402 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 403 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 404 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 405 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 406 /** 407 * @} 408 */ 409 410 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 411 * @{ 412 */ 413 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 414 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 415 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 416 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 422 * @{ 423 */ 424 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 425 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 426 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 427 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 433 * @{ 434 */ 435 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 436 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 437 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 438 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 444 * @{ 445 */ 446 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 447 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 448 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 449 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) 450 /** 451 * @} 452 */ 453 454 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 455 * @{ 456 */ 457 #define RCC_LPUART1CLKSOURCE_PCLK3 0x00000000U 458 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 459 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 460 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 461 #define RCC_LPUART1CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 462 /** 463 * @} 464 */ 465 466 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 467 * @{ 468 */ 469 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 470 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 471 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 472 #define RCC_I2C1CLKSOURCE_MSIK (RCC_CCIPR1_I2C1SEL_1 | RCC_CCIPR1_I2C1SEL_0) 473 /** 474 * @} 475 */ 476 477 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 478 * @{ 479 */ 480 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 481 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 482 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 483 #define RCC_I2C2CLKSOURCE_MSIK (RCC_CCIPR1_I2C2SEL_1 | RCC_CCIPR1_I2C2SEL_0) 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 489 * @{ 490 */ 491 #define RCC_I2C3CLKSOURCE_PCLK3 0x00000000U 492 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 493 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 494 #define RCC_I2C3CLKSOURCE_MSIK (RCC_CCIPR3_I2C3SEL_0 | RCC_CCIPR3_I2C3SEL_1) 495 /** 496 * @} 497 */ 498 499 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 500 * @{ 501 */ 502 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 503 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR1_I2C4SEL_0 504 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR1_I2C4SEL_1 505 #define RCC_I2C4CLKSOURCE_MSIK (RCC_CCIPR1_I2C4SEL_1 | RCC_CCIPR1_I2C4SEL_0) 506 /** 507 * @} 508 */ 509 510 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 511 * @{ 512 */ 513 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 514 #define RCC_RNGCLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 515 #define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 516 /** 517 * @} 518 */ 519 520 /** @defgroup RCCEx_SAES_Clock_Source RCCEx SAES Clock Source 521 * @{ 522 */ 523 #define RCC_SAESCLKSOURCE_SHSI 0x00000000U 524 #define RCC_SAESCLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 530 * @{ 531 */ 532 #define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U 533 #define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 534 #define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 535 #define RCC_SPI1CLKSOURCE_MSIK (RCC_CCIPR1_SPI1SEL_0 | RCC_CCIPR1_SPI1SEL_1) 536 /** 537 * @} 538 */ 539 540 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 541 * @{ 542 */ 543 #define RCC_SPI2CLKSOURCE_PCLK1 0x00000000U 544 #define RCC_SPI2CLKSOURCE_SYSCLK RCC_CCIPR1_SPI2SEL_0 545 #define RCC_SPI2CLKSOURCE_HSI RCC_CCIPR1_SPI2SEL_1 546 #define RCC_SPI2CLKSOURCE_MSIK (RCC_CCIPR1_SPI2SEL_0 | RCC_CCIPR1_SPI2SEL_1) 547 /** 548 * @} 549 */ 550 551 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 552 * @{ 553 */ 554 #define RCC_SPI3CLKSOURCE_PCLK3 0x00000000U 555 #define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 556 #define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 557 #define RCC_SPI3CLKSOURCE_MSIK (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) 558 /** 559 * @} 560 */ 561 562 /** @defgroup RCCEx_LPTIM34_Clock_Source LPTIM34 Clock Source 563 * @{ 564 */ 565 #define RCC_LPTIM34CLKSOURCE_MSIK 0x00000000U 566 #define RCC_LPTIM34CLKSOURCE_LSI RCC_CCIPR3_LPTIM34SEL_0 567 #define RCC_LPTIM34CLKSOURCE_HSI RCC_CCIPR3_LPTIM34SEL_1 568 #define RCC_LPTIM34CLKSOURCE_LSE (RCC_CCIPR3_LPTIM34SEL_0 | RCC_CCIPR3_LPTIM34SEL_1) 569 /** 570 * @} 571 */ 572 573 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 574 * @{ 575 */ 576 #define RCC_LPTIM1CLKSOURCE_MSIK 0x00000000U 577 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 578 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 579 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL 580 /** 581 * @} 582 */ 583 584 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 585 * @{ 586 */ 587 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 588 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 589 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 590 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL 591 /** 592 * @} 593 */ 594 595 /** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Kernel Clock Source 596 * @{ 597 */ 598 #define RCC_FDCAN1CLKSOURCE_HSE 0x00000000U 599 #define RCC_FDCAN1CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 600 #define RCC_FDCAN1CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 601 /** 602 * @} 603 */ 604 605 /** @defgroup RCCEx_CLK48_Clock_Source CLK48 Clock Source 606 * @{ 607 */ 608 #define RCC_CLK48CLKSOURCE_HSI48 0x00000000U 609 #define RCC_CLK48CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0 610 #define RCC_CLK48CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1 611 #define RCC_CLK48CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCCEx_ADCDAC_Clock_Source ADC1 Clock Source 617 * @{ 618 */ 619 #define RCC_ADCDACCLKSOURCE_HCLK 0x00000000U 620 #define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 621 #define RCC_ADCDACCLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 622 #define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_1) 623 #define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 624 #define RCC_ADCDACCLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_2) 625 /** 626 * @} 627 */ 628 629 /** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source 630 * @{ 631 */ 632 #define RCC_MDF1CLKSOURCE_HCLK 0x00000000U 633 #define RCC_MDF1CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 634 #define RCC_MDF1CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 635 #define RCC_MDF1CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_0 | RCC_CCIPR2_MDF1SEL_1) 636 #define RCC_MDF1CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 637 /** 638 * @} 639 */ 640 641 /** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source 642 * @{ 643 */ 644 #define RCC_ADF1CLKSOURCE_HCLK 0x00000000U 645 #define RCC_ADF1CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 646 #define RCC_ADF1CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 647 #define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_0 | RCC_CCIPR3_ADF1SEL_1) 648 #define RCC_ADF1CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 649 /** 650 * @} 651 */ 652 653 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 654 * @{ 655 */ 656 #define RCC_SAI1CLKSOURCE_PLL2 0x00000000U 657 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CCIPR2_SAI1SEL_0 658 #define RCC_SAI1CLKSOURCE_PLL1 RCC_CCIPR2_SAI1SEL_1 659 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 660 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 661 /** 662 * @} 663 */ 664 665 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 666 * @{ 667 */ 668 #define RCC_SAI2CLKSOURCE_PLL2 0x00000000U 669 #define RCC_SAI2CLKSOURCE_PLL3 RCC_CCIPR2_SAI2SEL_0 670 #define RCC_SAI2CLKSOURCE_PLL1 RCC_CCIPR2_SAI2SEL_1 671 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 672 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 673 /** 674 * @} 675 */ 676 677 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1/2 Clock Source 678 * @{ 679 */ 680 #define RCC_SDMMCCLKSOURCE_CLK48 0x00000000U 681 #define RCC_SDMMCCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL 682 /** 683 * @} 684 */ 685 686 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 687 * @{ 688 */ 689 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 690 #define RCC_OSPICLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 691 #define RCC_OSPICLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 692 #define RCC_OSPICLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) 693 /** 694 * @} 695 */ 696 697 /** @defgroup RCCEx_DAC1_Clock_Source DAC1 Clock Source 698 * @{ 699 */ 700 #define RCC_DAC1CLKSOURCE_LSE 0x00000000U 701 #define RCC_DAC1CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL 702 /** 703 * @} 704 */ 705 706 /** @defgroup RCC_Timicsel_items RCC timicsel items 707 * @brief RCC Timicsel items to configure timicsel 708 * @{ 709 */ 710 #define RCC_TIMIC_HSI_256 RCC_CCIPR1_TIMICSEL_2 /*!<HSI/256 selected for Timer16/17 and LPTimer2 */ 711 #define RCC_TIMIC_MSI_1024 RCC_CCIPR1_TIMICSEL_2 /*!<MSIS/1024 selected for Timer16/17 and LPTimer2*/ 712 #define RCC_TIMIC_MSI_4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!<MSIS/4 selected for Timer16/17 and LPTimer2*/ 713 #define RCC_TIMIC_MSIK_4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!<MSIK/1024 selected for Timer16/17 and LPTimer2*/ 714 #define RCC_TIMIC_MSIK_1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | RCC_CCIPR1_TIMICSEL_0) /*!<MSIK/4 selected for Timer16/17 and LPTimer2*/ 715 /** 716 * @} 717 */ 718 #if defined(CRS) 719 720 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 721 * @{ 722 */ 723 #define RCC_CRS_NONE 0x00000000U 724 #define RCC_CRS_TIMEOUT 0x00000001U 725 #define RCC_CRS_SYNCOK 0x00000002U 726 #define RCC_CRS_SYNCWARN 0x00000004U 727 #define RCC_CRS_SYNCERR 0x00000008U 728 #define RCC_CRS_SYNCMISS 0x00000010U 729 #define RCC_CRS_TRIMOVF 0x00000020U 730 /** 731 * @} 732 */ 733 734 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 735 * @{ 736 */ 737 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 738 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 739 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 740 /** 741 * @} 742 */ 743 744 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 745 * @{ 746 */ 747 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 748 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 749 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 750 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 751 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 752 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 753 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 754 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 760 * @{ 761 */ 762 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 763 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 769 * @{ 770 */ 771 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 772 to a target frequency of 48 MHz and a synchronization 773 signal frequency of 1 kHz (SOF signal from USB). */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 779 * @{ 780 */ 781 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 787 * @{ 788 */ 789 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to 790 the middle of the trimming interval. 791 The trimming step is around 67 kHz between two 792 consecutive TRIM steps. A higher TRIM value 793 corresponds to a higher output frequency */ 794 /** 795 * @} 796 */ 797 798 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 799 * @{ 800 */ 801 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 802 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 803 /** 804 * @} 805 */ 806 807 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 808 * @{ 809 */ 810 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 811 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 812 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 813 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 814 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 815 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 816 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 817 /** 818 * @} 819 */ 820 821 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 822 * @{ 823 */ 824 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 825 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 826 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 827 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 828 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 829 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 830 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 831 /** 832 * @} 833 */ 834 /** 835 * @} 836 */ 837 #endif /* CRS */ 838 839 /* Exported macros -----------------------------------------------------------*/ 840 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 841 * @{ 842 */ 843 844 /** @brief Macro to adjust the MSI oscillator calibration value. 845 * @note The calibration is used to compensate for the variations in voltage 846 * and temperature that influence the frequency of the internal MSI RC. 847 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value 848 * This parameter must be a number between 0 and 0x1F. 849 * @param __MSIRANGE__ : specifies the MSI Range value 850 * This parameter can be one of the following values: 851 * @arg RCC_MSIRANGE_0 852 * @arg RCC_MSIRANGE_1 853 * @arg RCC_MSIRANGE_2 854 * @arg RCC_MSIRANGE_3 855 * @arg RCC_MSIRANGE_4 856 * @arg RCC_MSIRANGE_5 857 * @arg RCC_MSIRANGE_6 858 * @arg RCC_MSIRANGE_7 859 * @arg RCC_MSIRANGE_8 860 * @arg RCC_MSIRANGE_9 861 * @arg RCC_MSIRANGE_10 862 * @arg RCC_MSIRANGE_11 863 * @arg RCC_MSIRANGE_12 864 * @arg RCC_MSIRANGE_13 865 * @arg RCC_MSIRANGE_14 866 * @arg RCC_MSIRANGE_15 867 * @retval None 868 */ 869 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__ , __MSIRANGE__) \ 870 do \ 871 { \ 872 if(__MSIRANGE__ >= RCC_MSIRANGE_12) \ 873 {\ 874 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 875 RCC_ICSCR2_MSITRIM3_Pos));\ 876 }\ 877 else if(__MSIRANGE__ >= RCC_MSIRANGE_8)\ 878 {\ 879 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 880 RCC_ICSCR2_MSITRIM2_Pos));\ 881 }\ 882 else if(__MSIRANGE__ >= RCC_MSIRANGE_4)\ 883 {\ 884 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 885 RCC_ICSCR2_MSITRIM1_Pos));\ 886 } \ 887 else /* if(__MSIRANGE__ >= RCC_MSIRANGE_0) */\ 888 { \ 889 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 890 RCC_ICSCR2_MSITRIM0_Pos));\ 891 } \ 892 } while(0) 893 894 /** @brief Macro to configure timer input capture clock source. 895 * @param __TIMICSOURCE__ : specifies the TIMIC clock source 896 * This parameter can be one or a combination of the following values: 897 * @arg RCC_TIMIC_HSI_256: HSI/256 selected for Timer16/17 and LPTimer2 898 * @arg RCC_TIMIC_MSI_1024: MSIS/1024 selected for Timer16/17 and LPTimer2 899 * @arg RCC_TIMIC_MSI_4: MSIS/4 selected for Timer16/17 and LPTimer2 900 * @arg RCC_TIMIC_MSIK_1024: MSIK/1024 selected for Timer16/17 and LPTimer2 901 * @arg RCC_TIMIC_MSIK_4 : MSIK/4 selected for Timer16/17 and LPTimer2 902 * @note combination to be avoid : 903 * RCC_TIMIC_MSI_1024 and RCC_TIMIC_MSIK_1024 904 * RCC_TIMIC_MSI_4 and RCC_TIMIC_MSIK_4 905 * @retval None 906 */ 907 #define __HAL_RCC_TIMIC_CLK_CONFIG(__TIMICSOURCE__) \ 908 do \ 909 { \ 910 /*Disable All TIMIC SOURCE*/ \ 911 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \ 912 /*Select TIMIC clock SOURCE*/ \ 913 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\ 914 } while(0) 915 916 /** @brief Macro to disable timer input capture clock source. 917 * @retval None 918 */ 919 #define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)) 920 921 /** @brief Macros to enable or disable the PLL2. 922 * @note After enabling PLL2, the application software should wait on 923 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 924 * be used as kernel clock source. 925 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 926 * @retval None 927 */ 928 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 929 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 930 931 /** @brief Macro to configure the PLL2 clock source. 932 * @note This function must be used only when all PLL2 is disabled. 933 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 934 * This parameter can be one of the following values: 935 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL2 clock entry 936 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry 937 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry 938 */ 939 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC,\ 940 (__PLL2SOURCE__)) 941 942 /** @brief Macro to get the oscillator used as PLL2 clock source. 943 * @retval The oscillator used as PLL2 clock source. The returned value can be one 944 * of the following: 945 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 946 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 947 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 948 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 949 */ 950 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) 951 952 /** @brief Macro to configures the PLL2 source, multiplication and division factors. 953 * @note This function must be used only when PLL2 is disabled. 954 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 955 * This parameter can be one of the following values: 956 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL2 clock entry 957 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL2 clock entry 958 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL2 clock entry 959 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL2 clock entry 960 * @param __PLL2M__ specifies the division factor of PLL2 input clock. 961 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 962 * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock 963 * This parameter must be a number between 4 and 512. 964 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 965 * output frequency is between 64 and 344 MHz. 966 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 967 * @param __PLL2P__: specifies the division factor for peripheral kernel clocks 968 * This parameter must be a number between 1 and 128 969 * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks 970 * This parameter must be a number between 1 and 128 971 * @param __PLL2R__: specifies the division factor for peripheral kernel clocks 972 * This parameter must be a number between 1 and 128 973 * @retval None 974 */ 975 #define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ 976 do \ 977 { \ 978 MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CFGR_PLL2SRC_Pos) |\ 979 (((__PLL2M__) - 1U) << RCC_PLL2CFGR_PLL2M_Pos));\ 980 MODIFY_REG(RCC->PLL2DIVR ,(RCC_PLL2DIVR_PLL2N|RCC_PLL2DIVR_PLL2P|RCC_PLL2DIVR_PLL2Q|\ 981 RCC_PLL2DIVR_PLL2R), ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | ((((__PLL2P__) -1U)<< \ 982 RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) |\ 983 ((((__PLL2Q__) -1U) << RCC_PLL2DIVR_PLL2Q_Pos)& \ 984 RCC_PLL2DIVR_PLL2Q) | ((((__PLL2R__)- 1U) << \ 985 RCC_PLL2DIVR_PLL2R_Pos) & \ 986 RCC_PLL2DIVR_PLL2R))); \ 987 } while(0) 988 989 /** 990 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 991 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2, 992 * This is mainly used to save Power. 993 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock outputted. 994 * This parameter can be one or a combination of the following values: 995 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve 996 * high-quality audio performance on SAI interface. 997 * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), 998 * the random number generator (<=48 MHz). 999 * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. 1000 * @retval None 1001 */ 1002 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1003 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1004 1005 /** 1006 * @brief Macro to get the PLL2 clock output enable status. 1007 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be outputted. 1008 * This parameter can be one of the following values: 1009 * This parameter can be one or a combination of the following values: 1010 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve 1011 * high-quality audio performance on SAI interface. 1012 * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), 1013 * the random number generator (<=48 MHz). 1014 * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. 1015 * @retval SET / RESET 1016 */ 1017 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1018 1019 /** 1020 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1021 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 1022 * @retval None 1023 */ 1024 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1025 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1026 1027 /** 1028 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1029 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1030 * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1031 * It should be a value between 0 and 8191 1032 * @note Warning: the software has to set correctly these bits to insure that the VCO 1033 * output frequency is between its valid frequency range, which is: 1034 * 192 to 836 MHz if PLL2VCOSEL = 0 1035 * 150 to 420 MHz if PLL2VCOSEL = 1 1036 * @retval None 1037 */ 1038 #define __HAL_RCC_PLL2FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN,\ 1039 (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) 1040 1041 /** @brief Macro to select the PLL2 reference frequency range. 1042 * @param __PLL2VCIRange__: specifies the PLL2 input frequency range 1043 * This parameter can be one of the following values: 1044 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 1045 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 1046 * @retval None 1047 */ 1048 #define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ 1049 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) 1050 1051 /** @brief Macros to enable or disable the main PLL3. 1052 * @note After enabling PLL3, the application software should wait on 1053 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1054 * be used as kernel clock source. 1055 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1056 */ 1057 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1058 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1059 1060 /** @brief Macro to configure the PLL3 clock source. 1061 * @note This function must be used only when all PLL3 is disabled. 1062 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1063 * This parameter can be one of the following values: 1064 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL3 clock entry 1065 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 1066 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 1067 * 1068 */ 1069 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ 1070 (__PLL3SOURCE__)) 1071 1072 /** @brief Macro to get the oscillator used as PLL3 clock source. 1073 * @retval The oscillator used as PLL3 clock source. The returned value can be one 1074 * of the following: 1075 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 1076 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 1077 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 1078 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 1079 */ 1080 #define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) 1081 1082 /** @brief Macro to configures the PLL3 source, multiplication and division factors. 1083 * @note This function must be used only when PLL3 is disabled. 1084 * 1085 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1086 * This parameter can be one of the following values: 1087 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL3 clock entry 1088 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL3 clock entry 1089 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL3 clock entry 1090 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL3 clock entry 1091 * @param __PLL3M__ specifies the division factor of PLL3 input clock. 1092 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 1093 * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock 1094 * This parameter must be a number between 4 and 512. 1095 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1096 * output frequency is between 64 and 344 MHz. 1097 * PLL3 clock frequency = f(PLL3) multiplied by PLL3N 1098 * @param __PLL3P__: specifies the division factor for peripheral kernel clocks 1099 * This parameter must be a number between 1 and 128 1100 * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks 1101 * This parameter must be a number between 1 and 128 1102 * @param __PLL3R__: specifies the division factor for peripheral kernel clocks 1103 * This parameter must be a number between 1 and 128 1104 * @retval None 1105 */ 1106 #define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ 1107 do\ 1108 {\ 1109 MODIFY_REG(RCC->PLL3CFGR,(RCC_PLL3CFGR_PLL3SRC|RCC_PLL3CFGR_PLL3M), ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos)|\ 1110 (((__PLL3M__) - 1U) << RCC_PLL3CFGR_PLL3M_Pos));\ 1111 MODIFY_REG(RCC->PLL3DIVR ,(RCC_PLL3DIVR_PLL3N|RCC_PLL3DIVR_PLL3P|RCC_PLL3DIVR_PLL3Q|RCC_PLL3DIVR_PLL3R),\ 1112 ((((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | ((((__PLL3P__) -1U) << RCC_PLL3DIVR_PLL3P_Pos) &\ 1113 RCC_PLL3DIVR_PLL3P) | ((((__PLL3Q__) -1U) << \ 1114 RCC_PLL3DIVR_PLL3Q_Pos) & \ 1115 RCC_PLL3DIVR_PLL3Q) | \ 1116 ((((__PLL3R__)- 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ 1117 } while(0) 1118 1119 /** 1120 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1121 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1122 * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1123 * It should be a value between 0 and 8191 1124 * @note Warning: the software has to set correctly these bits to insure that the VCO 1125 * output frequency is between its valid frequency range, which is: 1126 * 192 to 836 MHz if PLL3VCOSEL = 0 1127 * 150 to 420 MHz if PLL3VCOSEL = 1 1128 * @retval None 1129 */ 1130 #define __HAL_RCC_PLL3FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ 1131 (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) 1132 1133 /** @brief Macro to select the PLL3 reference frequency range. 1134 * @param __PLL3VCIRange__: specifies the PLL1 input frequency range 1135 * This parameter can be one of the following values: 1136 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 1137 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 1138 * @retval None 1139 */ 1140 #define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ 1141 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) 1142 1143 /** 1144 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1145 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 1146 * @retval None 1147 */ 1148 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1149 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1150 1151 /** 1152 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1153 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, 1154 * This is mainly used to save Power. 1155 * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted 1156 * This parameter can be one of the following values: 1157 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1158 * high-quality audio performance on SAI interface. 1159 * @retval None 1160 */ 1161 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1162 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1163 1164 /** 1165 * @brief Macro to get clock output enable status (PLL3_SAI2). 1166 * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be outputted. 1167 * This parameter can be one of the following values: 1168 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1169 * high-quality audio performance on SAI interface. 1170 * @retval SET / RESET 1171 */ 1172 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1173 1174 /** @brief Macro to configure the ADC1, ADC4 and DAC interface clock. 1175 * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. 1176 * This parameter can be one of the following values: 1177 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC4 and DAC clock 1178 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC4 and DAC clock 1179 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC4 and DAC clock 1180 * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC4 and DAC clock 1181 * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC4 and DAC clock 1182 * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC4 and DAC clock 1183 * @retval None 1184 */ 1185 #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ 1186 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) 1187 1188 /** @brief Macro to get the ADCDAC clock source. 1189 * @retval The clock source can be one of the following values: 1190 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC4 and DAC clock 1191 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC4 and DAC clock 1192 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC4 and DAC clock 1193 * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC4 and DAC clock 1194 * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC4 and DAC clock 1195 * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC4 and DAC clock 1196 */ 1197 #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) 1198 1199 /** @brief Macro to configure the CLK48 source (CLK48CLK). 1200 * @param __CLK48_SOURCE__: specifies the CLK48 clock source. 1201 * This parameter can be one of the following values: 1202 * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 selected as CLK48 source 1203 * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 selected as CLK48 source 1204 * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 selected as CLK48 source 1205 * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source 1206 */ 1207 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ 1208 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__CLK48_SOURCE__)) 1209 1210 /** @brief macro to get the CLK48 source. 1211 * @retval The clock source can be one of the following values: 1212 * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 used as CLK48 source 1213 * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 used as CLK48 source 1214 * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source 1215 * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source 1216 */ 1217 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) 1218 1219 /** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). 1220 * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. 1221 * This parameter can be one of the following values: 1222 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock 1223 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock 1224 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock 1225 * @retval None 1226 */ 1227 #define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ 1228 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) 1229 1230 /** @brief Macro to get the FDCAN1 clock source. 1231 * @retval The clock source can be one of the following values: 1232 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock 1233 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock 1234 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock 1235 */ 1236 #define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) 1237 1238 /** @brief Macro to configure the LPTIM34 clock (LPTIM34CLK). 1239 * @param __LPTIM34_CLKSOURCE__ specifies the LPTIM34 clock source. 1240 * This parameter can be one of the following values: 1241 * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock 1242 * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock 1243 * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock 1244 * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock 1245 * @retval None 1246 */ 1247 #define __HAL_RCC_LPTIM34_CONFIG(__LPTIM34_CLKSOURCE__) \ 1248 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL, (uint32_t)(__LPTIM34_CLKSOURCE__)) 1249 1250 /** @brief Macro to get the LPTIM34 clock source. 1251 * @retval The clock source can be one of the following values: 1252 * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock 1253 * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock 1254 * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock 1255 * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock 1256 */ 1257 #define __HAL_RCC_GET_LPTIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL))) 1258 1259 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1260 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1261 * This parameter can be one of the following values: 1262 * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock 1263 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1264 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1265 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1266 * @retval None 1267 */ 1268 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1269 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1270 1271 /** @brief Macro to get the LPTIM1 clock source. 1272 * @retval The clock source can be one of the following values: 1273 * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock 1274 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1275 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1276 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1277 */ 1278 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL))) 1279 1280 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1281 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1282 * This parameter can be one of the following values: 1283 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1284 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1285 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1286 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1287 * @retval None 1288 */ 1289 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1290 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1291 1292 /** @brief Macro to get the LPTIM2 clock source. 1293 * @retval The clock source can be one of the following values: 1294 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1295 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1296 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1297 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1298 */ 1299 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) 1300 1301 /** @brief macro to configure the SPI1 clock source. 1302 * @retval The clock source can be one of the following values: 1303 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock 1304 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock 1305 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock 1306 * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock selected as SPI1 clock 1307 */ 1308 1309 #define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ 1310 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) 1311 1312 /** @brief macro to get the SPI1 clock source. 1313 * @retval The clock source can be one of the following values: 1314 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock 1315 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock 1316 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock 1317 * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock used as SPI1 clock 1318 */ 1319 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL))) 1320 1321 /** @brief macro to configure the SPI2 clock source. 1322 * @retval The clock source can be one of the following values: 1323 * @arg RCC_SPI2CLKSOURCE_PCLK3 : PCLK3 selected as SPI2 clock 1324 * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock 1325 * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock 1326 * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock selected as SPI2 clock 1327 */ 1328 1329 #define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ 1330 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) 1331 1332 /** @brief macro to get the SPI2 clock source. 1333 * @retval The clock source can be one of the following values: 1334 * @arg RCC_SPI2CLKSOURCE_PCLK1 : PCLK1 Clock used as SPI2 clock 1335 * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock 1336 * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock 1337 * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock used as SPI2 clock 1338 */ 1339 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL))) 1340 1341 /** @brief macro to configure the SPI3 clock source. 1342 * @retval The clock source can be one of the following values: 1343 * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 selected as SPI3 clock 1344 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock 1345 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock 1346 * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock selected as SPI3 clock 1347 */ 1348 #define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ 1349 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) 1350 1351 /** @brief macro to get the SPI3 clock source. 1352 * @retval The clock source can be one of the following values: 1353 * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 used as SPI3 clock 1354 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI3 clock 1355 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock used as SPI3 clock 1356 * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock used as SPI3 clock 1357 */ 1358 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) 1359 1360 1361 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1362 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1363 * This parameter can be one of the following values: 1364 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1365 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1366 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1367 * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock 1368 * @retval None 1369 */ 1370 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1371 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1372 1373 /** @brief Macro to get the I2C1 clock source. 1374 * @retval The clock source can be one of the following values: 1375 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1376 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1377 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1378 * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock 1379 */ 1380 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) 1381 1382 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1383 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1384 * This parameter can be one of the following values: 1385 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1386 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1387 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1388 * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock 1389 * @retval None 1390 */ 1391 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1392 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 1393 1394 /** @brief Macro to get the I2C2 clock source. 1395 * @retval The clock source can be one of the following values: 1396 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1397 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1398 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1399 * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock 1400 */ 1401 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) 1402 1403 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1404 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1405 * This parameter can be one of the following values: 1406 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 selected as I2C3 clock 1407 * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI selected as I2C3 clock 1408 * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK selected as I2C3 clock 1409 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock selected as I2C3 clock 1410 * @retval None 1411 */ 1412 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1413 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1414 1415 /** @brief Macro to get the I2C3 clock source. 1416 * @retval The clock source can be one of the following values: 1417 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 used as I2C3 clock 1418 * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI used as I2C3 clock 1419 * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK used as I2C3 clock 1420 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock used as I2C3 clock 1421 */ 1422 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL))) 1423 1424 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1425 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1426 * This parameter can be one of the following values: 1427 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1428 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1429 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1430 * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock 1431 * @retval None 1432 */ 1433 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1434 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 1435 1436 /** @brief Macro to get the I2C4 clock source. 1437 * @retval The clock source can be one of the following values: 1438 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1439 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1440 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1441 * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock 1442 */ 1443 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) 1444 1445 /** @brief Macro to configure the USART1 clock (USART1CLK). 1446 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1447 * This parameter can be one of the following values: 1448 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 1449 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1450 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1451 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1452 * @retval None 1453 */ 1454 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1455 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1456 1457 /** @brief Macro to get the USART1 clock source. 1458 * @retval The clock source can be one of the following values: 1459 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 1460 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1461 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1462 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1463 */ 1464 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 1465 1466 /** @brief Macro to configure the USART2 clock (USART2CLK). 1467 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1468 * This parameter can be one of the following values: 1469 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1470 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1471 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1472 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1473 * @retval None 1474 */ 1475 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1476 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1477 1478 /** @brief Macro to get the USART2 clock source. 1479 * @retval The clock source can be one of the following values: 1480 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1481 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1482 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1483 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1484 */ 1485 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 1486 1487 /** @brief Macro to configure the USART3 clock (USART3CLK). 1488 * 1489 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1490 * This parameter can be one of the following values: 1491 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1492 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1493 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1494 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1495 * @retval None 1496 */ 1497 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1498 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 1499 1500 /** @brief Macro to get the USART3 clock source. 1501 * @retval The clock source can be one of the following values: 1502 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1503 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1504 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1505 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1506 */ 1507 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 1508 1509 /** @brief Macro to configure the UART4 clock (UART4CLK). 1510 * 1511 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1512 * This parameter can be one of the following values: 1513 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1514 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1515 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1516 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1517 * @retval None 1518 */ 1519 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1520 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 1521 1522 /** @brief Macro to get the UART4 clock source. 1523 * @retval The clock source can be one of the following values: 1524 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1525 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1526 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1527 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1528 */ 1529 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 1530 1531 /** @brief Macro to configure the UART5 clock (UART5CLK). 1532 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1533 * This parameter can be one of the following values: 1534 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1535 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1536 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1537 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1538 * @retval None 1539 */ 1540 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1541 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 1542 1543 /** @brief Macro to get the UART5 clock source. 1544 * @retval The clock source can be one of the following values: 1545 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1546 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1547 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1548 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1549 */ 1550 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 1551 1552 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1553 * 1554 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1555 * This parameter can be one of the following values: 1556 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 1557 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1558 * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock 1559 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1560 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1561 * @retval None 1562 */ 1563 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1564 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1565 1566 /** @brief Macro to get the LPUART1 clock source. 1567 * @retval The clock source can be one of the following values: 1568 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 1569 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1570 * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock 1571 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1572 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1573 */ 1574 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) 1575 1576 1577 /** @brief Macro to configure the OctoSPI clock. 1578 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 1579 * This parameter can be one of the following values: 1580 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1581 * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock 1582 * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock 1583 * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock 1584 * @retval None 1585 */ 1586 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 1587 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 1588 1589 /** @brief Macro to get the OctoSPI clock source. 1590 * @retval The clock source can be one of the following values: 1591 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1592 * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock 1593 * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock 1594 * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock 1595 */ 1596 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) 1597 1598 /** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). 1599 * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. 1600 * This parameter can be one of the following values: 1601 * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock 1602 * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock 1603 */ 1604 #define __HAL_RCC_SDMMC_CONFIG(__SDMMC_CLKSOURCE__) \ 1605 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, (uint32_t)(__SDMMC_CLKSOURCE__)) 1606 1607 /** @brief macro to get the SDMMC1/2 clock source. 1608 * @retval The clock source can be one of the following values: 1609 * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock 1610 * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock 1611 */ 1612 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))) 1613 1614 /** @brief macro to configure the RNG clock (RNGCLK). 1615 * @param __RNG_CLKSource__: specifies the RNG clock source. 1616 * This parameter can be one of the following values: 1617 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 1618 * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock 1619 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 1620 */ 1621 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSource__) \ 1622 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (uint32_t)(__RNG_CLKSource__)) 1623 1624 /** @brief macro to get the RNG clock source. 1625 * @retval The clock source can be one of the following values: 1626 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 1627 * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock 1628 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 1629 */ 1630 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL))) 1631 1632 /** @brief macro to configure the SAES clock (SAESCLK). 1633 * @param __SAES_CLKSource__: specifies the SAES clock source. 1634 * This parameter can be one of the following values: 1635 * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock 1636 * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock 1637 */ 1638 #define __HAL_RCC_SAES_CONFIG(__SAES_CLKSource__) \ 1639 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, (uint32_t)(__SAES_CLKSource__)) 1640 1641 /** @brief macro to get the SAES clock source. 1642 * @retval The clock source can be one of the following values: 1643 * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock 1644 * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock 1645 */ 1646 #define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL))) 1647 1648 /** 1649 * @brief Macro to configure the SAI1 clock source. 1650 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 1651 * from the PLL2, system PLL or external clock (through a dedicated pin). 1652 * This parameter can be one of the following values: 1653 * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) 1654 * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) 1655 * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL1 "P" clock (PLL1CLK) 1656 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1657 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1658 * 1659 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLL3. 1660 * @retval None 1661 */ 1662 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 1663 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 1664 1665 /** @brief Macro to get the SAI1 clock source. 1666 * @retval The clock source can be one of the following values: 1667 * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) 1668 * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) 1669 * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL "P" clock (PLL1CLK) 1670 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1671 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1672 * @note Despite returned values RCC_SAI1CLKSOURCE_PLL2 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 1673 * clock source when PLLs are disabled for devices without PLL3. 1674 */ 1675 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) 1676 1677 /** 1678 * @brief Macro to configure the SAI2 clock source. 1679 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 1680 * from the PLL3, system PLL or external clock (through a dedicated pin). 1681 * This parameter can be one of the following values: 1682 * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) 1683 * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) 1684 * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) 1685 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1686 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1687 * @retval None 1688 */ 1689 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1690 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 1691 1692 /** @brief Macro to get the SAI2 clock source. 1693 * @retval The clock source can be one of the following values: 1694 * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) 1695 * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) 1696 * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) 1697 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1698 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1699 */ 1700 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) 1701 1702 /** @brief Macro to configure the MDF1 clock. 1703 * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. 1704 * This parameter can be one of the following values: 1705 * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock 1706 * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 P Clock selected as MDF1 clock 1707 * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Q Clock selected as MDF1 clock 1708 * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as MDF1 clock 1709 * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock selected as MDF1 clock 1710 * @retval None 1711 */ 1712 #define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ 1713 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, (uint32_t)(__MDF1_CLKSOURCE__)) 1714 1715 /** @brief Macro to get the MDF1 clock source. 1716 * @retval The clock source can be one of the following values: 1717 * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock used as MDF1 clock 1718 * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 Clock used as MDF1 clock 1719 * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Clock used as MDF1 clock 1720 * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as MDF1 clock 1721 * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock used as MDF1 clock 1722 */ 1723 #define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL))) 1724 1725 /** @brief Macro to configure the ADF1 clock. 1726 * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. 1727 * This parameter can be one of the following values: 1728 * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 1729 * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock selected as ADF1 clock 1730 * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock selected as ADF1 clock 1731 * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as ADF1 clock 1732 * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock selected as ADF1 clock 1733 * @retval None 1734 */ 1735 #define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ 1736 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) 1737 1738 /** @brief Macro to get the ADF1 clock source. 1739 * @retval The clock source can be one of the following values: 1740 * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock used as ADF1 clock 1741 * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock used as ADF1 clock 1742 * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock used as ADF1 clock 1743 * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as ADF1 clock 1744 * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock used as ADF1 clock 1745 */ 1746 #define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL))) 1747 1748 /** @brief Macro to configure the DAC1 interface clock. 1749 * @param __DAC1_CLKSOURCE__ specifies the DAC1 digital interface clock source. 1750 * This parameter can be one of the following values: 1751 * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock 1752 * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock 1753 * @retval None 1754 */ 1755 #define __HAL_RCC_DAC1_CONFIG(__DAC1_CLKSOURCE__) \ 1756 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, (uint32_t)(__DAC1_CLKSOURCE__)) 1757 1758 /** @brief Macro to get the DAC1 clock source. 1759 * @retval The clock source can be one of the following values: 1760 * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock 1761 * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock 1762 */ 1763 #define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) 1764 1765 #if defined(CRS) 1766 1767 /** 1768 * @brief Enable the specified CRS interrupts. 1769 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1770 * This parameter can be any combination of the following values: 1771 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1772 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1773 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1774 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1775 * @retval None 1776 */ 1777 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1778 1779 /** 1780 * @brief Disable the specified CRS interrupts. 1781 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1782 * This parameter can be any combination of the following values: 1783 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1784 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1785 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1786 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1787 * @retval None 1788 */ 1789 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1790 1791 /** @brief Check whether the CRS interrupt has occurred or not. 1792 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1793 * This parameter can be one of the following values: 1794 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1795 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1796 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1797 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1798 * @retval The new state of __INTERRUPT__ (SET or RESET). 1799 */ 1800 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 1801 1802 /** @brief Clear the CRS interrupt pending bits 1803 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1804 * This parameter can be any combination of the following values: 1805 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1806 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1807 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1808 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1809 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1810 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1811 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1812 */ 1813 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 1814 1815 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1816 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1817 { \ 1818 WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\ 1819 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1820 } \ 1821 else \ 1822 { \ 1823 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1824 } \ 1825 } while(0) 1826 1827 /** 1828 * @brief Check whether the specified CRS flag is set or not. 1829 * @param __FLAG__ specifies the flag to check. 1830 * This parameter can be one of the following values: 1831 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1832 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1833 * @arg @ref RCC_CRS_FLAG_ERR Error 1834 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1835 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1836 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1837 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1838 * @retval The new state of _FLAG_ (TRUE or FALSE). 1839 */ 1840 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1841 1842 /** 1843 * @brief Clear the CRS specified FLAG. 1844 * @param __FLAG__ specifies the flag to clear. 1845 * This parameter can be one of the following values: 1846 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1847 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1848 * @arg @ref RCC_CRS_FLAG_ERR Error 1849 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1850 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1851 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1852 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1853 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently 1854 * RCC_CRS_FLAG_ERR 1855 * @retval None 1856 */ 1857 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | \ 1858 RCC_CRS_FLAG_SYNCMISS)) 1859 1860 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1861 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1862 { \ 1863 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 1864 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1865 } \ 1866 else \ 1867 { \ 1868 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1869 } \ 1870 } while(0) 1871 1872 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1873 * @{ 1874 */ 1875 /** 1876 * @brief Enable the oscillator clock for frequency error counter. 1877 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1878 * @retval None 1879 */ 1880 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1881 1882 /** 1883 * @brief Disable the oscillator clock for frequency error counter. 1884 * @retval None 1885 */ 1886 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1887 1888 /** 1889 * @brief Enable the automatic hardware adjustment of TRIM bits. 1890 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1891 * @retval None 1892 */ 1893 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1894 1895 /** 1896 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1897 * @retval None 1898 */ 1899 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1900 1901 /** 1902 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1903 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1904 * of the synchronization source after prescaling. It is then decreased by one in order to 1905 * reach the expected synchronization on the zero value. The formula is the following: 1906 * RELOAD = (fTARGET / fSYNC) -1 1907 * @param __FTARGET__ Target frequency (value in Hz) 1908 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1909 * @retval None 1910 */ 1911 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1912 1913 1914 /** 1915 * @} 1916 */ 1917 1918 #endif /* CRS */ 1919 1920 /** 1921 * @} 1922 */ 1923 1924 /* Exported functions --------------------------------------------------------*/ 1925 /** @addtogroup RCCEx_Exported_Functions 1926 * @{ 1927 */ 1928 1929 /** @addtogroup RCCEx_Exported_Functions_Group1 1930 * @{ 1931 */ 1932 1933 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 1934 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 1935 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1936 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); 1937 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); 1938 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); 1939 /** 1940 * @} 1941 */ 1942 1943 /** @addtogroup RCCEx_Exported_Functions_Group2 1944 * @{ 1945 */ 1946 1947 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); 1948 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 1949 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init); 1950 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); 1951 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); 1952 HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); 1953 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection); 1954 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1955 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 1956 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 1957 void HAL_RCCEx_EnableLSECSS(void); 1958 void HAL_RCCEx_DisableLSECSS(void); 1959 void HAL_RCCEx_LSECSS_IRQHandler(void); 1960 void HAL_RCCEx_LSECSS_Callback(void); 1961 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1962 void HAL_RCCEx_DisableLSCO(void); 1963 void HAL_RCCEx_EnableMSIPLLMode(void); 1964 void HAL_RCCEx_DisableMSIPLLMode(void); 1965 1966 /** 1967 * @} 1968 */ 1969 1970 #if defined(CRS) 1971 1972 /** @addtogroup RCCEx_Exported_Functions_Group3 1973 * @{ 1974 */ 1975 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit); 1976 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1977 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1978 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1979 void HAL_RCCEx_CRS_IRQHandler(void); 1980 void HAL_RCCEx_CRS_SyncOkCallback(void); 1981 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1982 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1983 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1984 /** 1985 * @} 1986 */ 1987 1988 #endif /* CRS */ 1989 1990 /** 1991 * @} 1992 */ 1993 1994 /** 1995 * @} 1996 */ 1997 1998 /** 1999 * @} 2000 */ 2001 2002 #ifdef __cplusplus 2003 } 2004 #endif 2005 2006 #endif /* STM32U5xx_HAL_RCC_EX_H */ 2007
