1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 * 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7RSxx_HAL_RCC_EX_H 22 #define STM32H7RSxx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7rsxx_hal_def.h" 30 31 /** @addtogroup STM32H7RSxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL1 Clocks structure definition 46 */ 47 48 /** 49 * @brief RCC extended clocks structure definition 50 */ 51 typedef struct 52 { 53 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 54 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 55 56 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 57 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 58 59 uint32_t Xspi1ClockSelection; /*!< Specifies XSPI1 clock source 60 This parameter can be a value of @ref RCCEx_XSPI1_Clock_Source */ 61 62 uint32_t Xspi2ClockSelection; /*!< Specifies XSPI2 clock source 63 This parameter can be a value of @ref RCCEx_XSPI2_Clock_Source */ 64 65 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 66 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 67 68 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 69 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 70 71 uint32_t Adf1ClockSelection; /*!< Specifies ADF1 Clock clock source 72 This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ 73 74 uint32_t CecClockSelection; /*!< Specifies CEC clock source 75 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 76 77 uint32_t Eth1RefClockSelection; /*!< Specifies ETH1 REF clock source 78 This parameter can be a value of @ref RCCEx_ETH1REF_Clock_Source */ 79 80 uint32_t Eth1PhyClockSelection; /*!< Specifies ETH1 PHY clock source 81 This parameter can be a value of @ref RCCEx_ETH1PHY_Clock_Source */ 82 83 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source 84 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 85 86 uint32_t I2c1_I3c1ClockSelection; /*!< Specifies I2C1/I3C1 clock source 87 This parameter can be a value of @ref RCCEx_I2C1_I3C1_Clock_Source */ 88 89 uint32_t I2c23ClockSelection; /*!< Specifies I2C2/I2C3 clock source 90 This parameter can be a value of @ref RCCEx_I2C23_Clock_Source */ 91 92 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 93 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 94 95 uint32_t Lptim23ClockSelection; /*!< Specifies LPTIM2/LPTIM3 clock source 96 This parameter can be a value of @ref RCCEx_LPTIM23_Clock_Source */ 97 98 uint32_t Lptim45ClockSelection; /*!< Specifies LPTIM4/LPTIM5 clock source 99 This parameter can be a value of @ref RCCEx_LPTIM45_Clock_Source */ 100 101 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 102 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 103 104 uint32_t LtdcClockSelection; /*!< Specifies LPUART1 clock source 105 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 106 107 uint32_t PssiClockSelection; /*!< Specifies PSSI clock source 108 This parameter can be a value of @ref RCCEx_PSSI_Clock_Source */ 109 110 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 111 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 112 113 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source 114 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 115 116 uint32_t Sdmmc12ClockSelection; /*!< Specifies SDMMC clock source 117 This parameter can be a value of @ref RCCEx_SDMMC12_Clock_Source */ 118 119 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 120 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 121 122 uint32_t Spi23ClockSelection; /*!< Specifies SPI2/SPI3 clock source 123 This parameter can be a value of @ref RCCEx_SPI23_Clock_Source */ 124 125 uint32_t Spi45ClockSelection; /*!< Specifies SPI4/SPI5 clock source 126 This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ 127 128 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 129 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 130 131 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 132 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 133 134 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source 135 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 136 137 uint32_t Usart234578ClockSelection; /*!< Specifies USART2/USART3/UART4/UART5/UART7/UART8 clock source 138 This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ 139 140 uint32_t UsbPhycClockSelection; /*!< Specifies USB PHYC clock source 141 This parameter can be a value of @ref RCCEx_USB_PHYC_Clock_Source */ 142 143 uint32_t UsbOtgFsClockSelection; /*!< Specifies USB OTG FS clock source 144 This parameter can be a value of @ref RCCEx_USB_OTGFS_Clock_Source */ 145 146 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source 147 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 148 149 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 150 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 151 } RCC_PeriphCLKInitTypeDef; 152 153 /** 154 * @brief RCC_CRS Init structure definition 155 */ 156 typedef struct 157 { 158 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 159 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 160 161 uint32_t Source; /*!< Specifies the SYNC signal source. 162 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 163 164 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 165 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 166 167 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 168 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 169 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 170 171 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 172 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 173 174 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 175 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 176 177 } RCC_CRSInitTypeDef; 178 179 /** 180 * @brief RCC_CRS Synchronization structure definition 181 */ 182 typedef struct 183 { 184 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 185 This parameter must be a number between 0 and 0xFFFF */ 186 187 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 188 This parameter must be a number between 0 and 0x3F */ 189 190 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 191 value latched in the time of the last SYNC event. 192 This parameter must be a number between 0 and 0xFFFF */ 193 194 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 195 frequency error counter latched in the time of the last SYNC event. 196 It shows whether the actual frequency is below or above the target. 197 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 198 199 } RCC_CRSSynchroInfoTypeDef; 200 201 /** 202 * @} 203 */ 204 205 206 /* Exported constants --------------------------------------------------------*/ 207 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 208 * @{ 209 */ 210 211 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 212 * @{ 213 */ 214 #define RCC_PERIPHCLK_FMC (0x00000001U) 215 #define RCC_PERIPHCLK_XSPI1 (0x00000002U) 216 #define RCC_PERIPHCLK_XSPI2 (0x00000004U) 217 #define RCC_PERIPHCLK_CKPER (0x00000008U) 218 #define RCC_PERIPHCLK_ADC (0x00000010U) 219 #define RCC_PERIPHCLK_ADF1 (0x00000020U) 220 #define RCC_PERIPHCLK_CEC (0x00000040U) 221 #define RCC_PERIPHCLK_ETH1REF (0x00000080U) 222 #define RCC_PERIPHCLK_ETH1PHY (0x00000100U) 223 #define RCC_PERIPHCLK_FDCAN (0x00000200U) 224 #define RCC_PERIPHCLK_I2C23 (0x00000400U) 225 #define RCC_PERIPHCLK_I2C1_I3C1 (0x00000800U) 226 #define RCC_PERIPHCLK_LPTIM1 (0x00001000U) 227 #define RCC_PERIPHCLK_LPTIM23 (0x00002000U) 228 #define RCC_PERIPHCLK_LPTIM45 (0x00004000U) 229 #define RCC_PERIPHCLK_LPUART1 (0x00008000U) 230 #define RCC_PERIPHCLK_LTDC (0x00010000U) 231 #define RCC_PERIPHCLK_PSSI (0x00020000U) 232 #define RCC_PERIPHCLK_RTC (0x00040000U) 233 #define RCC_PERIPHCLK_SAI1 (0x00080000U) 234 #define RCC_PERIPHCLK_SAI2 (0x00100000U) 235 #define RCC_PERIPHCLK_SDMMC12 (0x00200000U) 236 #define RCC_PERIPHCLK_SPDIFRX (0x00400000U) 237 #define RCC_PERIPHCLK_SPI1 (0x00800000U) 238 #define RCC_PERIPHCLK_SPI23 (0x01000000U) 239 #define RCC_PERIPHCLK_SPI45 (0x02000000U) 240 #define RCC_PERIPHCLK_SPI6 (0x04000000U) 241 #define RCC_PERIPHCLK_TIM (0x08000000U) 242 #define RCC_PERIPHCLK_USART1 (0x10000000U) 243 #define RCC_PERIPHCLK_USART234578 (0x20000000U) 244 #define RCC_PERIPHCLK_USBPHYC (0x40000000U) 245 #define RCC_PERIPHCLK_USBOTGFS (0x80000000U) 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source 251 * @{ 252 */ 253 #define RCC_FMCCLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ 254 #define RCC_FMCCLKSOURCE_PLL1Q RCC_CCIPR1_FMCSEL_0 /*!< PLL 'Q' output selection */ 255 #define RCC_FMCCLKSOURCE_PLL2R RCC_CCIPR1_FMCSEL_1 /*!< PLL2 'R' output selection */ 256 #define RCC_FMCCLKSOURCE_HSI RCC_CCIPR1_FMCSEL /*!< HSI selection */ 257 #define RCC_FMCCLKSOURCE_HCLK_DIV4 (RCC_CKPROTR_FMCSWP_2 | RCC_CKPROTR_FMCSWP_0) /*!< HCLK/4 selection (recovery position) */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup RCCEx_XSPI1_Clock_Source XSPI1 Clock Source 263 * @{ 264 */ 265 #define RCC_XSPI1CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ 266 #define RCC_XSPI1CLKSOURCE_PLL2S RCC_CCIPR1_XSPI1SEL_0 /*!< PLL2 'S' output selection */ 267 #define RCC_XSPI1CLKSOURCE_PLL2T RCC_CCIPR1_XSPI1SEL_1 /*!< PLL2 'T' output selection */ 268 #define RCC_XSPI1CLKSOURCE_HCLK_DIV4 RCC_CKPROTR_XSPI1SWP_2 /*!< HCLK/4 selection (recovery position) */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup RCCEx_XSPI2_Clock_Source XSPI2 Clock Source 274 * @{ 275 */ 276 #define RCC_XSPI2CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ 277 #define RCC_XSPI2CLKSOURCE_PLL2S RCC_CCIPR1_XSPI2SEL_0 /*!< PLL2 'S' output selection */ 278 #define RCC_XSPI2CLKSOURCE_PLL2T RCC_CCIPR1_XSPI2SEL_1 /*!< PLL2 'T' output selection */ 279 #define RCC_XSPI2CLKSOURCE_HCLK_DIV4 RCC_CKPROTR_XSPI2SWP_2 /*!< HCLK/4 selection (recovery position) */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup RCCEx_CLKP_Clock_Source CLKP Clock Source 285 * @{ 286 */ 287 #define RCC_CLKPSOURCE_HSI 0U /*!< HSI selection (default) */ 288 #define RCC_CLKPSOURCE_CSI RCC_CCIPR1_CKPERSEL_0 /*!< CSI selection */ 289 #define RCC_CLKPSOURCE_HSE RCC_CCIPR1_CKPERSEL_1 /*!< HSE selection */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 295 * @{ 296 */ 297 #define RCC_ADCCLKSOURCE_PLL2P 0U /*!< PLL2 'P' output selection (default) */ 298 #define RCC_ADCCLKSOURCE_PLL3R RCC_CCIPR1_ADCSEL_0 /*!< PLL3 'R' output selection */ 299 #define RCC_ADCCLKSOURCE_CLKP RCC_CCIPR1_ADCSEL_1 /*!< Clock peripheral output selection */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source 305 * @{ 306 */ 307 #define RCC_ADF1CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ 308 #define RCC_ADF1CLKSOURCE_PLL2P RCC_CCIPR1_ADF1SEL_0 /*!< PLL2 'P' output selection */ 309 #define RCC_ADF1CLKSOURCE_PLL3P RCC_CCIPR1_ADF1SEL_1 /*!< PLL3 'P' output selection */ 310 #define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0) /*!< External I2S_PIN selection */ 311 #define RCC_ADF1CLKSOURCE_CSI RCC_CCIPR1_ADF1SEL_2 /*!< CSI selection */ 312 #define RCC_ADF1CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0) /*!< HSI selection */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 318 * @{ 319 */ 320 #define RCC_CECCLKSOURCE_LSE 0U /*!< LSE selection (default) */ 321 #define RCC_CECCLKSOURCE_LSI RCC_CCIPR2_CECSEL_0 /*!< LSI selection */ 322 #define RCC_CECCLKSOURCE_CSI RCC_CCIPR2_CECSEL_1 /*!< CSI divided by 122 selection */ 323 /** 324 * @} 325 */ 326 327 /** @defgroup RCCEx_ETH1REF_Clock_Source ETH1 REF Clock Source 328 * @{ 329 */ 330 #define RCC_ETH1REFCLKSOURCE_PHY 0U /*!< ETH PHY selection (default) */ 331 #define RCC_ETH1REFCLKSOURCE_HSE RCC_CCIPR1_ETH1REFCKSEL_0 /*!< HSE selection */ 332 #define RCC_ETH1REFCLKSOURCE_ETH RCC_CCIPR1_ETH1REFCKSEL_1 /*!< ETH Feedback output selection */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup RCCEx_ETH1PHY_Clock_Source ETH1 PHY Clock Source 338 * @{ 339 */ 340 #define RCC_ETH1PHYCLKSOURCE_HSE 0U /*!< HSE selection (default) */ 341 #define RCC_ETH1PHYCLKSOURCE_PLL3S RCC_CCIPR1_ETH1PHYCKSEL /*!< PLL3 'S' output selection */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 347 * @{ 348 */ 349 #define RCC_FDCANCLKSOURCE_HSE 0U /*!< HSE selection (default) */ 350 #define RCC_FDCANCLKSOURCE_PLL1Q RCC_CCIPR2_FDCANSEL_0 /*!< PLL1 'Q' output selection */ 351 #define RCC_FDCANCLKSOURCE_PLL2P RCC_CCIPR2_FDCANSEL_1 /*!< PLL2 'P' output selection */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCCEx_I2C23_Clock_Source I2C2/I2C3 Clock Source 357 * @{ 358 */ 359 #define RCC_I2C23CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ 360 #define RCC_I2C23CLKSOURCE_PLL3R RCC_CCIPR2_I2C23SEL_0 /*!< PLL3 'R' output selection */ 361 #define RCC_I2C23CLKSOURCE_HSI RCC_CCIPR2_I2C23SEL_1 /*!< HSI selection */ 362 #define RCC_I2C23CLKSOURCE_CSI (RCC_CCIPR2_I2C23SEL_1 | RCC_CCIPR2_I2C23SEL_0) /*!< CSI selection */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup RCCEx_I2C1_I3C1_Clock_Source I2C1/I3C1Clock Source 368 * @{ 369 */ 370 #define RCC_I2C1_I3C1CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ 371 #define RCC_I2C1_I3C1CLKSOURCE_PLL3R RCC_CCIPR2_I2C1_I3C1SEL_0 /*!< PLL3 'R' output selection */ 372 #define RCC_I2C1_I3C1CLKSOURCE_HSI RCC_CCIPR2_I2C1_I3C1SEL_1 /*!< HSI selection */ 373 #define RCC_I2C1_I3C1CLKSOURCE_CSI (RCC_CCIPR2_I2C1_I3C1SEL_1 | RCC_CCIPR2_I2C1_I3C1SEL_0) /*!< CSI selection */ 374 /** 375 * @} 376 */ 377 378 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 379 * @{ 380 */ 381 #define RCC_LPTIM1CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ 382 #define RCC_LPTIM1CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM1SEL_0 /*!< PLL2 'P' output selection */ 383 #define RCC_LPTIM1CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM1SEL_1 /*!< PLL3 'R' output selection */ 384 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR2_LPTIM1SEL_1 | RCC_CCIPR2_LPTIM1SEL_0) /*!< LSE selection */ 385 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL_2 /*!< LSI selection */ 386 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM1SEL_2 | RCC_CCIPR2_LPTIM1SEL_0) /*!< Clock peripheral output selection */ 387 /** 388 * @} 389 */ 390 391 /** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM2/LPTIM3 Clock Source 392 * @{ 393 */ 394 #define RCC_LPTIM23CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ 395 #define RCC_LPTIM23CLKSOURCE_PLL2P RCC_CCIPR4_LPTIM23SEL_0 /*!< PLL2 'P' output selection */ 396 #define RCC_LPTIM23CLKSOURCE_PLL3R RCC_CCIPR4_LPTIM23SEL_1 /*!< PLL3 'R' output selection */ 397 #define RCC_LPTIM23CLKSOURCE_LSE (RCC_CCIPR4_LPTIM23SEL_1 | RCC_CCIPR4_LPTIM23SEL_0) /*!< LSE selection */ 398 #define RCC_LPTIM23CLKSOURCE_LSI RCC_CCIPR4_LPTIM23SEL_2 /*!< LSI selection */ 399 #define RCC_LPTIM23CLKSOURCE_CLKP (RCC_CCIPR4_LPTIM23SEL_2 | RCC_CCIPR4_LPTIM23SEL_0) /*!< Clock peripheral output selection */ 400 /** 401 * @} 402 */ 403 404 /** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM4/LPTIM5 Clock Source 405 * @{ 406 */ 407 #define RCC_LPTIM45CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ 408 #define RCC_LPTIM45CLKSOURCE_PLL2P RCC_CCIPR4_LPTIM45SEL_0 /*!< PLL2 'P' output selection */ 409 #define RCC_LPTIM45CLKSOURCE_PLL3R RCC_CCIPR4_LPTIM45SEL_1 /*!< PLL3 'R' output selection */ 410 #define RCC_LPTIM45CLKSOURCE_LSE (RCC_CCIPR4_LPTIM45SEL_1 | RCC_CCIPR4_LPTIM45SEL_0) /*!< LSE selection */ 411 #define RCC_LPTIM45CLKSOURCE_LSI RCC_CCIPR4_LPTIM45SEL_2 /*!< LSI selection */ 412 #define RCC_LPTIM45CLKSOURCE_CLKP (RCC_CCIPR4_LPTIM45SEL_2 | RCC_CCIPR4_LPTIM45SEL_0) /*!< Clock peripheral output selection */ 413 /** 414 * @} 415 */ 416 417 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 418 * @{ 419 */ 420 #define RCC_LPUART1CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ 421 #define RCC_LPUART1CLKSOURCE_PLL2Q RCC_CCIPR4_LPUART1SEL_0 /*!< PLL2 'Q' output selection */ 422 #define RCC_LPUART1CLKSOURCE_PLL3Q RCC_CCIPR4_LPUART1SEL_1 /*!< PLL2 'Q' output selection */ 423 #define RCC_LPUART1CLKSOURCE_HSI (RCC_CCIPR4_LPUART1SEL_1 | RCC_CCIPR4_LPUART1SEL_0) /*!< HSI selection */ 424 #define RCC_LPUART1CLKSOURCE_CSI RCC_CCIPR4_LPUART1SEL_2 /*!< CSI selection */ 425 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR4_LPUART1SEL_2 | RCC_CCIPR4_LPUART1SEL_0) /*!< LSE selection */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 431 * @{ 432 */ 433 #define RCC_LTDCCLKSOURCE_PLL3R 0U /*!< PLL3 'R' output selection (unique) */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup RCCEx_PSSI_Clock_Source PSSI Clock Source 439 * @{ 440 */ 441 #define RCC_PSSICLKSOURCE_PLL3R 0U /*!< PLL3 'R' output selection (default) */ 442 #define RCC_PSSICLKSOURCE_CLKP RCC_CCIPR1_PSSISEL /*!< Clock peripheral output selection */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 448 * @{ 449 */ 450 #define RCC_SAI1CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ 451 #define RCC_SAI1CLKSOURCE_PLL2P RCC_CCIPR3_SAI1SEL_0 /*!< PLL2 'P' output selection */ 452 #define RCC_SAI1CLKSOURCE_PLL3P RCC_CCIPR3_SAI1SEL_1 /*!< PLL3 'P' output selection */ 453 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR3_SAI1SEL_1 | RCC_CCIPR3_SAI1SEL_0) /*!< I2S_PIN selection */ 454 #define RCC_SAI1CLKSOURCE_CLKP RCC_CCIPR3_SAI1SEL_2 /*!< Clock peripheral output selection */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 460 * @{ 461 */ 462 #define RCC_SAI2CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ 463 #define RCC_SAI2CLKSOURCE_PLL2P RCC_CCIPR3_SAI2SEL_0 /*!< PLL2 'P' output selection */ 464 #define RCC_SAI2CLKSOURCE_PLL3P RCC_CCIPR3_SAI2SEL_1 /*!< PLL3 'P' output selection */ 465 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR3_SAI2SEL_1 | RCC_CCIPR3_SAI2SEL_0) /*!< I2S_PIN selection */ 466 #define RCC_SAI2CLKSOURCE_CLKP RCC_CCIPR3_SAI2SEL_2 /*!< Clock peripheral output selection */ 467 #define RCC_SAI2CLKSOURCE_SPDIF (RCC_CCIPR3_SAI2SEL_2 | RCC_CCIPR3_SAI2SEL_0) /*!< SPDIF output selection */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC Clock Source 473 * @{ 474 */ 475 #define RCC_SDMMC12CLKSOURCE_PLL2S 0U /*!< PLL2 'S' output selection (default) */ 476 #define RCC_SDMMC12CLKSOURCE_PLL2T RCC_CCIPR1_SDMMC12SEL /*!< PLL2 'T' output selection */ 477 /** 478 * @} 479 */ 480 481 /** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source 482 * @{ 483 */ 484 #define RCC_SPDIFRXCLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ 485 #define RCC_SPDIFRXCLKSOURCE_PLL2R RCC_CCIPR2_SPDIFRXSEL_0 /*!< PLL2 'R' output selection */ 486 #define RCC_SPDIFRXCLKSOURCE_PLL3R RCC_CCIPR2_SPDIFRXSEL_1 /*!< PLL3 'R' output selection */ 487 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CCIPR2_SPDIFRXSEL /*!< HSI selection */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 493 * @{ 494 */ 495 #define RCC_SPI1CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ 496 #define RCC_SPI1CLKSOURCE_PLL2P RCC_CCIPR3_SPI1SEL_0 /*!< PLL2 'P' output selection */ 497 #define RCC_SPI1CLKSOURCE_PLL3P RCC_CCIPR3_SPI1SEL_1 /*!< PLL3 'P' output selection */ 498 #define RCC_SPI1CLKSOURCE_PIN (RCC_CCIPR3_SPI1SEL_1 | RCC_CCIPR3_SPI1SEL_0) /*!< I2S_PIN selection */ 499 #define RCC_SPI1CLKSOURCE_CLKP RCC_CCIPR3_SPI1SEL_2 /*!< Clock peripheral output selection */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup RCCEx_SPI23_Clock_Source SPI2/SPI3 Clock Source 505 * @{ 506 */ 507 #define RCC_SPI23CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ 508 #define RCC_SPI23CLKSOURCE_PLL2P RCC_CCIPR2_SPI23SEL_0 /*!< PLL2 'P' output selection */ 509 #define RCC_SPI23CLKSOURCE_PLL3P RCC_CCIPR2_SPI23SEL_1 /*!< PLL3 'P' output selection */ 510 #define RCC_SPI23CLKSOURCE_PIN (RCC_CCIPR2_SPI23SEL_1 | RCC_CCIPR2_SPI23SEL_0) /*!< I2S_PIN selection */ 511 #define RCC_SPI23CLKSOURCE_CLKP RCC_CCIPR2_SPI23SEL_2 /*!< Clock peripheral output selection */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/SPI5 Clock Source 517 * @{ 518 */ 519 #define RCC_SPI45CLKSOURCE_PCLK2 0U /*!< PCLK2 selection (default) */ 520 #define RCC_SPI45CLKSOURCE_PLL2Q RCC_CCIPR3_SPI45SEL_0 /*!< PLL2 'Q' output selection */ 521 #define RCC_SPI45CLKSOURCE_PLL3Q RCC_CCIPR3_SPI45SEL_1 /*!< PLL3 'Q' output selection */ 522 #define RCC_SPI45CLKSOURCE_HSI (RCC_CCIPR3_SPI45SEL_1 | RCC_CCIPR3_SPI45SEL_0) /*!< HSI selection */ 523 #define RCC_SPI45CLKSOURCE_CSI RCC_CCIPR3_SPI45SEL_2 /*!< CSI selection */ 524 #define RCC_SPI45CLKSOURCE_HSE (RCC_CCIPR3_SPI45SEL_2 | RCC_CCIPR3_SPI45SEL_0) /*!< HSE selection */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 530 * @{ 531 */ 532 #define RCC_SPI6CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ 533 #define RCC_SPI6CLKSOURCE_PLL2Q RCC_CCIPR4_SPI6SEL_0 /*!< PLL2 'Q' output selection */ 534 #define RCC_SPI6CLKSOURCE_PLL3Q RCC_CCIPR4_SPI6SEL_1 /*!< PLL3 'Q' output selection */ 535 #define RCC_SPI6CLKSOURCE_HSI (RCC_CCIPR4_SPI6SEL_1 | RCC_CCIPR4_SPI6SEL_0) /*!< HSI selection */ 536 #define RCC_SPI6CLKSOURCE_CSI RCC_CCIPR4_SPI6SEL_2 /*!< CSI selection */ 537 #define RCC_SPI6CLKSOURCE_HSE (RCC_CCIPR4_SPI6SEL_2 | RCC_CCIPR4_SPI6SEL_0) /*!< HSE selection */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup RCCEx_TIM_Prescaler_Selection TIM Prescaler Selection 543 * @{ 544 */ 545 #define RCC_TIMPRES_DISABLE 0U /*!< Timers clocks prescaler not set (default) */ 546 #define RCC_TIMPRES_ENABLE RCC_CFGR_TIMPRE /*!< Timers clocks prescaler set */ 547 548 /** 549 * @} 550 */ 551 552 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 553 * @{ 554 */ 555 #define RCC_USART1CLKSOURCE_PCLK2 0U /*!< PCLK2 selection (default) */ 556 #define RCC_USART1CLKSOURCE_PLL2Q RCC_CCIPR3_USART1SEL_0 /*!< PLL2 'Q' output selection */ 557 #define RCC_USART1CLKSOURCE_PLL3Q RCC_CCIPR3_USART1SEL_1 /*!< PLL2 'Q' output selection */ 558 #define RCC_USART1CLKSOURCE_HSI (RCC_CCIPR3_USART1SEL_1 | RCC_CCIPR3_USART1SEL_0) /*!< HSI selection */ 559 #define RCC_USART1CLKSOURCE_CSI RCC_CCIPR3_USART1SEL_2 /*!< CSI selection */ 560 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR3_USART1SEL_2 | RCC_CCIPR3_USART1SEL_0) /*!< LSE selection */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup RCCEx_USART234578_Clock_Source USART2/USART3/UART4/UART5/UART7/UART8 Clock Source 566 * @{ 567 */ 568 #define RCC_USART234578CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ 569 #define RCC_USART234578CLKSOURCE_PLL2Q RCC_CCIPR2_UART234578SEL_0 /*!< PLL2 'Q' output selection */ 570 #define RCC_USART234578CLKSOURCE_PLL3Q RCC_CCIPR2_UART234578SEL_1 /*!< PLL3 'Q' output selection */ 571 #define RCC_USART234578CLKSOURCE_HSI (RCC_CCIPR2_UART234578SEL_1 | RCC_CCIPR2_UART234578SEL_0) /*!< HSI selection */ 572 #define RCC_USART234578CLKSOURCE_CSI RCC_CCIPR2_UART234578SEL_2 /*!< CSI selection */ 573 #define RCC_USART234578CLKSOURCE_LSE (RCC_CCIPR2_UART234578SEL_2 | RCC_CCIPR2_UART234578SEL_0) /*!< LSE selection */ 574 /** 575 * @} 576 */ 577 578 /** @defgroup RCCEx_USB_PHYC_Clock_Source USB PHYC Clock Source 579 * @{ 580 */ 581 #define RCC_USBPHYCCLKSOURCE_HSE 0U /*!< HSE selection (default) */ 582 #define RCC_USBPHYCCLKSOURCE_HSE_DIV2 RCC_CCIPR1_USBPHYCSEL_0 /*!< HSE div 2 selection */ 583 #define RCC_USBPHYCCLKSOURCE_PLL3Q RCC_CCIPR1_USBPHYCSEL_1 /*!< PLL3 'Q' output selection */ 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_USB_OTGFS_Clock_Source USB OTG FS Clock Source 589 * @{ 590 */ 591 #define RCC_USBOTGFSCLKSOURCE_HSI48 0U /*!< HSI48 selection (default) */ 592 #define RCC_USBOTGFSCLKSOURCE_PLL3Q RCC_CCIPR1_OTGFSSEL_0 /*!< PLL3 'Q' output selection */ 593 #define RCC_USBOTGFSCLKSOURCE_HSE RCC_CCIPR1_OTGFSSEL_1 /*!< HSE selection */ 594 #define RCC_USBOTGFSCLKSOURCE_CLK48 RCC_CCIPR1_OTGFSSEL /*!< USBPHYC CLK48 output selection */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup RCCEx_Clock_Protection Clock Protection 600 * @{ 601 */ 602 #define RCC_CLOCKPROTECT_XSPI RCC_CKPROTR_XSPICKP /*!< XSPIs clock protection */ 603 #define RCC_CLOCKPROTECT_FMC RCC_CKPROTR_FMCCKP /*!< FMC clock protection */ 604 /** 605 * @} 606 */ 607 608 609 /** @defgroup RCCEx_EXTI_LINE_LSECSS LSE CSS external interrupt line 610 * @{ 611 */ 612 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup RCCEx_CRS_Status CRS Status 618 * @{ 619 */ 620 #define RCC_CRS_NONE 0x00000000U 621 #define RCC_CRS_TIMEOUT 0x00000001U 622 #define RCC_CRS_SYNCOK 0x00000002U 623 #define RCC_CRS_SYNCWARN 0x00000004U 624 #define RCC_CRS_SYNCERR 0x00000008U 625 #define RCC_CRS_SYNCMISS 0x00000010U 626 #define RCC_CRS_TRIMOVF 0x00000020U 627 /** 628 * @} 629 */ 630 631 /** @defgroup RCCEx_CRS_SynchroSource CRS SynchroSource 632 * @{ 633 */ 634 #define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ 635 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 636 #define RCC_CRS_SYNC_SOURCE_USB_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB OTG FS SOF (default) */ 637 #define RCC_CRS_SYNC_SOURCE_USB_OTG_HS (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB OTG HS SOF */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup RCCEx_CRS_SynchroDivider CRS SynchroDivider 643 * @{ 644 */ 645 #define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ 646 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 647 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 648 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 649 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 650 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 651 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 652 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup RCCEx_CRS_SynchroPolarity CRS SynchroPolarity 658 * @{ 659 */ 660 #define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ 661 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 662 /** 663 * @} 664 */ 665 666 /** @defgroup RCCEx_CRS_ReloadValueDefault CRS ReloadValueDefault 667 * @{ 668 */ 669 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 670 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 671 /** 672 * @} 673 */ 674 675 /** @defgroup RCCEx_CRS_ErrorLimitDefault CRS ErrorLimitDefault 676 * @{ 677 */ 678 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault CRS HSI48CalibrationDefault 684 * @{ 685 */ 686 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 687 The trimming step is specified in the product datasheet. A higher TRIM value corresponds 688 to a higher output frequency */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup RCCEx_CRS_FreqErrorDirection CRS FreqErrorDirection 694 * @{ 695 */ 696 #define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ 697 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup RCCEx_CRS_Interrupt_Sources CRS Interrupt Sources 703 * @{ 704 */ 705 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 706 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 707 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 708 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 709 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 710 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 711 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 712 713 /** 714 * @} 715 */ 716 717 /** @defgroup RCCEx_CRS_Flags CRS Flags 718 * @{ 719 */ 720 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 721 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 722 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 723 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 724 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 725 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 726 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 727 728 /** 729 * @} 730 */ 731 732 /** 733 * @} 734 */ 735 736 /* Exported macro ------------------------------------------------------------*/ 737 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 738 * @{ 739 */ 740 741 /** @brief Macro to configure the ADC clock 742 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 743 * This parameter can be one of the following values: 744 * @arg RCC_ADCCLKSOURCE_PLL2P PLL2_P Clock selected as ADC clock 745 * @arg RCC_ADCCLKSOURCE_PLL3R PLL3_R Clock selected as ADC clock 746 * @arg RCC_ADCCLKSOURCE_CLKP CLKP Clock selected as ADC clock 747 */ 748 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 749 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 750 751 /** @brief Macro to get the ADC clock source. 752 * @retval The clock source can be one of the following values: 753 * @arg RCC_ADCCLKSOURCE_PLL2P PLL2_P Clock selected as ADC clock 754 * @arg RCC_ADCCLKSOURCE_PLL3R PLL3_R Clock selected as ADC clock 755 * @arg RCC_ADCCLKSOURCE_CLKP CLKP Clock selected as ADC clock 756 */ 757 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL))) 758 759 /** @brief Macro to configure the ADF1 clock 760 * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. 761 * This parameter can be one of the following values: 762 * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 763 * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2_P Clock selected as ADF1 clock 764 * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3_P Clock selected as ADF1 clock 765 * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock 766 * @arg RCC_ADF1CLKSOURCE_CSI CSI selected as ADF1 clock 767 * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock 768 */ 769 #define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ 770 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) 771 772 /** @brief Macro to get the ADF1 clock source. 773 * @retval The clock source can be one of the following values: 774 * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 775 * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2_P Clock selected as ADF1 clock 776 * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3_P Clock selected as ADF1 clock 777 * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock 778 * @arg RCC_ADF1CLKSOURCE_CSI CSI selected as ADF1 clock 779 * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock 780 */ 781 #define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL))) 782 783 /** @brief Macro to configure the HDMI-CEC clock source. 784 * @param __CEC_CLKSOURCE__ specifies the CEC clock source. 785 * This parameter can be one of the following values: 786 * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 787 * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock 788 * @arg RCC_CECCLKSOURCE_CSI CSI divided by 122 selected as CEC clock 789 */ 790 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ 791 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) 792 793 /** @brief Macro to get the HDMI-CEC clock source. 794 * @retval The clock source can be one of the following values: 795 * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 796 * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock 797 * @arg RCC_CECCLKSOURCE_CSI CSI divided by 122 selected as CEC clock 798 */ 799 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_CECSEL))) 800 801 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 802 * @param __CLKP_CLKSOURCE__ specifies Oscillator clock for peripheral 803 * This parameter can be one of the following values: 804 * @arg RCC_CLKPSOURCE_HSI HSI selected as peripheral clock (default) 805 * @arg RCC_CLKPSOURCE_CSI CSI selected as peripheral clock 806 * @arg RCC_CLKPSOURCE_HSE HSE selected as peripheral clock 807 */ 808 #define __HAL_RCC_CLKP_CONFIG(__CLKP_CLKSOURCE__) \ 809 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL, (uint32_t)(__CLKP_CLKSOURCE__)) 810 811 /** @brief Macro to get the Oscillator clock for peripheral source. 812 * @retval The clock source can be one of the following values: 813 * @arg RCC_CLKPSOURCE_HSI HSI selected as peripheral clock (default) 814 * @arg RCC_CLKPSOURCE_CSI CSI selected as peripheral clock 815 * @arg RCC_CLKPSOURCE_HSE HSE selected as peripheral clock 816 */ 817 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL))) 818 819 /** @brief Macro to configure the ETH1 REF clock source. 820 * @param __ETH1REF_CLKSOURCE__ specifies clock source for ETH1 REF 821 * This parameter can be one of the following values: 822 * @arg RCC_ETH1REFCLKSOURCE_PHY ETH PHY selected as ETH1 REF clock (default) 823 * @arg RCC_ETH1REFCLKSOURCE_HSE HSE selected as ETH1 clock 824 * @arg RCC_ETH1REFCLKSOURCE_ETH ETH feedback selected as ETH1 REF clock 825 */ 826 #define __HAL_RCC_ETH1REF_CONFIG(__ETH1REF_CLKSOURCE__) \ 827 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL, (uint32_t)(__ETH1REF_CLKSOURCE__)) 828 829 /** @brief Macro to get the ETH1 REF clock source. 830 * @retval The clock source can be one of the following values: 831 * @arg RCC_ETH1REFCLKSOURCE_PHY ETH PHY selected as ETH1 clock (default) 832 * @arg RCC_ETH1REFCLKSOURCE_HSE HSE selected as ETH1 clock 833 * @arg RCC_ETH1REFCLKSOURCE_ETH ETH feedback selected as ETH1 clock 834 */ 835 #define __HAL_RCC_GET_ETH1REF_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL))) 836 837 /** @brief Macro to configure the ETH1 PHY clock source. 838 * @param __ETH1PHY_CLKSOURCE__ specifies clock source for ETH PHY 839 * This parameter can be one of the following values: 840 * @arg RCC_ETH1PHYCLKSOURCE_HSE HSE selected as ETH PHY clock (default) 841 * @arg RCC_ETH1PHYCLKSOURCE_PLL3S PLL3_S selected as ETH PHY clock 842 */ 843 #define __HAL_RCC_ETH1PHY_CONFIG(__ETH1PHY_CLKSOURCE__) \ 844 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL, (uint32_t)(__ETH1PHY_CLKSOURCE__)) 845 846 /** @brief Macro to get the ETH1 PHY clock source. 847 * @retval The clock source can be one of the following values: 848 * @arg RCC_ETH1PHYCLKSOURCE_HSE HSE selected as ETH PHY clock (default) 849 * @arg RCC_ETH1PHYCLKSOURCE_PLL3S PLL3_S selected as ETH PHY clock 850 */ 851 #define __HAL_RCC_GET_ETH1PHY_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL))) 852 853 /** @brief Macro to configure the FDCAN kernel clock source. 854 * @param __FDCAN_CLKSOURCE__ specifies clock source for FDCAN kernel 855 * This parameter can be one of the following values: 856 * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock (default) 857 * @arg RCC_FDCANCLKSOURCE_PLL1Q PLL1_Q selected as FDCAN kernel clock 858 * @arg RCC_FDCANCLKSOURCE_PLL2P PLL2_P selected as FDCAN kernel clock 859 */ 860 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 861 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 862 863 /** @brief Macro to get the FDCAN kernel clock source. 864 * @retval The clock source can be one of the following values: 865 * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock (default) 866 * @arg RCC_FDCANCLKSOURCE_PLL1Q PLL1_Q selected as FDCAN kernel clock 867 * @arg RCC_FDCANCLKSOURCE_PLL2P PLL2_P selected as FDCAN kernel clock 868 */ 869 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL))) 870 871 /** @brief Macro to configure the FMC clock source. 872 * 873 * @param __FMC_CLKSOURCE__ specifies the FMC clock source. 874 * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock 875 * @arg RCC_FMCCLKSOURCE_PLL1Q PLL1_Q Clock selected as FMC clock 876 * @arg RCC_FMCCLKSOURCE_PLL2R PLL2_R Clock selected as FMC clock 877 * @arg RCC_FMCCLKSOURCE_HSI HSI selected as FMC clock 878 */ 879 #define __HAL_RCC_FMC_CONFIG(__FMC_CLKSOURCE__) \ 880 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FMCSEL, (uint32_t)(__FMC_CLKSOURCE__)) 881 882 /** @brief Macro to get the FMC clock source. 883 * @retval The clock source can be one of the following values: 884 * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock 885 * @arg RCC_FMCCLKSOURCE_PLL1Q PLL1_Q Clock selected as FMC clock 886 * @arg RCC_FMCCLKSOURCE_PLL2R PLL2_R Clock selected as FMC clock 887 * @arg RCC_FMCCLKSOURCE_HSI HSI selected as FMC clock 888 * @arg RCC_FMCCLKSOURCE_HCLK_DIV4 Recovery Clock selected as FMC clock 889 */ 890 #define __HAL_RCC_GET_FMC_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP) == RCC_FMCCLKSOURCE_HCLK_DIV4) ? \ 891 RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL)))) 892 893 /** @brief Macro to configure the I2C1/I3C1 clock source. 894 * @param __I2C1_I3C1_CLKSOURCE__ specifies the I2C1/I3C1clock source. 895 * This parameter can be one of the following values: 896 * @arg RCC_I2C1_I3C1CLKSOURCE_PCLK1 APB1 selected as I2C1/I3C1clock 897 * @arg RCC_I2C1_I3C1CLKSOURCE_PLL3R PLL3_R selected as I2C1/I3C1clock 898 * @arg RCC_I2C1_I3C1CLKSOURCE_HSI HSI selected as I2C1/I3C1clock 899 * @arg RCC_I2C1_I3C1CLKSOURCE_CSI CSI selected as I2C1/I3C1clock 900 */ 901 #define __HAL_RCC_I2C1_I3C1_CONFIG(__I2C1_I3C1_CLKSOURCE__) \ 902 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, (uint32_t)(__I2C1_I3C1_CLKSOURCE__)) 903 904 /** @brief Macro to get the I2C1/I3C1clock source. 905 * @retval The clock source can be one of the following values: 906 * @arg RCC_I2C1_I3C1CLKSOURCE_PCLK1 APB1 selected as I2C1/I3C1clock 907 * @arg RCC_I2C1_I3C1CLKSOURCE_PLL3R PLL3_R selected as I2C1/I3C1clock 908 * @arg RCC_I2C1_I3C1CLKSOURCE_HSI HSI selected as I2C1/I3C1clock 909 * @arg RCC_I2C1_I3C1CLKSOURCE_CSI CSI selected as I2C1/I3C1clock 910 */ 911 #define __HAL_RCC_GET_I2C1_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL))) 912 913 /** @brief Macro to configure the I2C2/I2C3 clock source. 914 * @param __I2C23_CLKSOURCE__ specifies the I2C2/I2C3 clock source. 915 * This parameter can be one of the following values: 916 * @arg RCC_I2C23CLKSOURCE_PCLK1 APB1 selected as I2C2/I2C3 clock 917 * @arg RCC_I2C23CLKSOURCE_PLL3R PLL3_R selected as I2C2/I2C3 clock 918 * @arg RCC_I2C23CLKSOURCE_HSI HSI selected as I2C2/I2C3 clock 919 * @arg RCC_I2C23CLKSOURCE_CSI CSI selected as I2C2/I2C3 clock 920 */ 921 #define __HAL_RCC_I2C23_CONFIG(__I2C23_CLKSOURCE__) \ 922 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C23SEL, (uint32_t)(__I2C23_CLKSOURCE__)) 923 924 /** @brief Macro to get the I2C2/I2C3 clock source. 925 * @retval The clock source can be one of the following values: 926 * @arg RCC_I2C23CLKSOURCE_PCLK1 APB1 selected as I2C2/I2C3 clock 927 * @arg RCC_I2C23CLKSOURCE_PLL3R PLL3_R selected as I2C2/I2C3 clock 928 * @arg RCC_I2C23CLKSOURCE_HSI HSI selected as I2C2/I2C3 clock 929 * @arg RCC_I2C23CLKSOURCE_CSI CSI selected as I2C2/I2C3 clock 930 */ 931 #define __HAL_RCC_GET_I2C23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C23SEL))) 932 933 /** @brief Macro to configure the I3C1 clock source. 934 * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. 935 * This parameter can be one of the following values: 936 * @arg RCC_I3C1CLKSOURCE_PCLK1 APB1 selected as I3C1 clock 937 * @arg RCC_I3C1CLKSOURCE_PLL3R PLL3_R selected as I3C1 clock 938 * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 939 * @arg RCC_I3C1CLKSOURCE_CSI CSI selected as I3C1 clock 940 */ 941 #define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ 942 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) 943 944 /** @brief Macro to get the I3C1 clock source. 945 * @retval The clock source can be one of the following values: 946 * @arg RCC_I3C1CLKSOURCE_PCLK1 APB1 selected as I3C1 clock 947 * @arg RCC_I3C1CLKSOURCE_PLL3R PLL3_R selected as I3C1 clock 948 * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 949 * @arg RCC_I3C1CLKSOURCE_CSI CSI selected as I3C1 clock 950 */ 951 #define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL))) 952 953 /** @brief Macro to configure the LPTIM1 clock source. 954 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 955 * This parameter can be one of the following values: 956 * @arg RCC_LPTIM1CLKSOURCE_PCLK1 APB1 clock selected as LPTIM1 clock 957 * @arg RCC_LPTIM1CLKSOURCE_PLL2P PLL2_P selected as LPTIM1 clock 958 * @arg RCC_LPTIM1CLKSOURCE_PLL3R PLL3_R selected as LPTIM1 clock 959 * @arg RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 960 * @arg RCC_LPTIM1CLKSOURCE_LSI LSI Clock selected as LPTIM1 clock 961 * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 962 */ 963 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 964 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 965 966 /** @brief Macro to get the LPTIM1 clock source. 967 * @retval The clock source can be one of the following values: 968 * @arg RCC_LPTIM1CLKSOURCE_PCLK1 APB1 clock selected as LPTIM1 clock 969 * @arg RCC_LPTIM1CLKSOURCE_PLL2P PLL2_P selected as LPTIM1 clock 970 * @arg RCC_LPTIM1CLKSOURCE_PLL3R PLL3_R selected as LPTIM1 clock 971 * @arg RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 972 * @arg RCC_LPTIM1CLKSOURCE_LSI LSI Clock selected as LPTIM1 clock 973 * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 974 */ 975 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) 976 977 /** @brief Macro to configure the LPTIM2/LPTIM3 clock source. 978 * @param __LPTIM23_CLKSOURCE__ specifies the LPTIM2/LPTIM3 clock source. 979 * This parameter can be one of the following values: 980 * @arg RCC_LPTIM23CLKSOURCE_PCLK4 APB4 clock selected as LPTIM2/LPTIM3 clock 981 * @arg RCC_LPTIM23CLKSOURCE_PLL2P PLL2_P selected as LPTIM2/LPTIM3 clock 982 * @arg RCC_LPTIM23CLKSOURCE_PLL3R PLL3_R selected as LPTIM2/LPTIM3 clock 983 * @arg RCC_LPTIM23CLKSOURCE_LSE LSE selected as LPTIM2/LPTIM3 clock 984 * @arg RCC_LPTIM23CLKSOURCE_LSI LSI Clock selected as LPTIM2/LPTIM3 clock 985 * @arg RCC_LPTIM23CLKSOURCE_CLKP CLKP selected as LPTIM2/LPTIM3 clock 986 */ 987 #define __HAL_RCC_LPTIM23_CONFIG(__LPTIM23_CLKSOURCE__) \ 988 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPTIM23SEL, (uint32_t)(__LPTIM23_CLKSOURCE__)) 989 990 /** @brief Macro to get the LPTIM2/LPTIM3 clock source. 991 * @retval The clock source can be one of the following values: 992 * @arg RCC_LPTIM23CLKSOURCE_PCLK4 APB4 clock selected as LPTIM2/LPTIM3 clock 993 * @arg RCC_LPTIM23CLKSOURCE_PLL2P PLL2_P selected as LPTIM2/LPTIM3 clock 994 * @arg RCC_LPTIM23CLKSOURCE_PLL3R PLL3_R selected as LPTIM2/LPTIM3 clock 995 * @arg RCC_LPTIM23CLKSOURCE_LSE LSE selected as LPTIM2/LPTIM3 clock 996 * @arg RCC_LPTIM23CLKSOURCE_LSI LSI Clock selected as LPTIM2/LPTIM3 clock 997 * @arg RCC_LPTIM23CLKSOURCE_CLKP CLKP selected as LPTIM2/LPTIM3 clock 998 */ 999 #define __HAL_RCC_GET_LPTIM23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPTIM23SEL))) 1000 1001 /** @brief Macro to configure the LPTIM4/LPTIM5 clock source. 1002 * @param __LPTIM45_CLKSOURCE__ specifies the LPTIM4/LPTIM5 clock source. 1003 * This parameter can be one of the following values: 1004 * @arg RCC_LPTIM45CLKSOURCE_PCLK4 APB4 clock selected as LPTIM4/LPTIM5 clock 1005 * @arg RCC_LPTIM45CLKSOURCE_PLL2P PLL2_P selected as LPTIM4/LPTIM5 clock 1006 * @arg RCC_LPTIM45CLKSOURCE_PLL3R PLL3_R selected as LPTIM4/LPTIM5 clock 1007 * @arg RCC_LPTIM45CLKSOURCE_LSE LSE selected as LPTIM4/LPTIM5 clock 1008 * @arg RCC_LPTIM45CLKSOURCE_LSI LSI Clock selected as LPTIM4/LPTIM5 clock 1009 * @arg RCC_LPTIM45CLKSOURCE_CLKP CLKP selected as LPTIM4/LPTIM5 clock 1010 */ 1011 #define __HAL_RCC_LPTIM45_CONFIG(__LPTIM45_CLKSOURCE__) \ 1012 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPTIM45SEL, (uint32_t)(__LPTIM45_CLKSOURCE__)) 1013 1014 /** @brief Macro to get the LPTIM4/LPTIM5 clock source. 1015 * @retval The clock source can be one of the following values: 1016 * @arg RCC_LPTIM45CLKSOURCE_PCLK4 APB4 clock selected as LPTIM4/LPTIM5 clock 1017 * @arg RCC_LPTIM45CLKSOURCE_PLL2P PLL2_P selected as LPTIM4/LPTIM5 clock 1018 * @arg RCC_LPTIM45CLKSOURCE_PLL3R PLL3_R selected as LPTIM4/LPTIM5 clock 1019 * @arg RCC_LPTIM45CLKSOURCE_LSE LSE selected as LPTIM4/LPTIM5 clock 1020 * @arg RCC_LPTIM45CLKSOURCE_LSI LSI Clock selected as LPTIM4/LPTIM5 clock 1021 * @arg RCC_LPTIM45CLKSOURCE_CLKP CLKP selected as LPTIM4/LPTIM5 clock 1022 */ 1023 #define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPTIM45SEL))) 1024 1025 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1026 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1027 * This parameter can be one of the following values: 1028 * @arg RCC_LPUART1CLKSOURCE_PCLK4 APB4 Clock selected as LPUART1 clock 1029 * @arg RCC_LPUART1CLKSOURCE_PLL2Q PLL2_Q Clock selected as LPUART1 clock 1030 * @arg RCC_LPUART1CLKSOURCE_PLL3Q PLL3_Q Clock selected as LPUART1 clock 1031 * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1032 * @arg RCC_LPUART1CLKSOURCE_CSI CSI Clock selected as LPUART1 clock 1033 * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1034 */ 1035 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1036 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1037 1038 /** @brief Macro to get the LPUART1 clock source. 1039 * @retval The clock source can be one of the following values: 1040 * @arg RCC_LPUART1CLKSOURCE_PCLK4 APB4 Clock selected as LPUART1 clock 1041 * @arg RCC_LPUART1CLKSOURCE_PLL2Q PLL2_Q Clock selected as LPUART1 clock 1042 * @arg RCC_LPUART1CLKSOURCE_PLL3Q PLL3_Q Clock selected as LPUART1 clock 1043 * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1044 * @arg RCC_LPUART1CLKSOURCE_CSI CSI Clock selected as LPUART1 clock 1045 * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1046 */ 1047 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL))) 1048 1049 /** @brief Macro to get the LTDC clock source. 1050 * @retval The clock source is internally connected to: 1051 * @arg RCC_LTDCCLKSOURCE_PLL3R PLL3_R Clock selected as LTDC clock 1052 */ 1053 #define __HAL_RCC_GET_LTDC_SOURCE() RCC_LTDCCLKSOURCE_PLL3R 1054 1055 /** @brief Macro to configure the XSPI1 clock source. 1056 * 1057 * @param __XSPI1_CLKSOURCE__ specifies the XSPI1 clock source. 1058 * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK Clock selected as XSPI1 clock 1059 * @arg RCC_XSPI1CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI1 clock 1060 * @arg RCC_XSPI1CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI1 clock 1061 */ 1062 #define __HAL_RCC_XSPI1_CONFIG(__XSPI1_CLKSOURCE__) \ 1063 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL, (uint32_t)(__XSPI1_CLKSOURCE__)) 1064 1065 /** @brief Macro to get the XSPI1 clock source. 1066 * @retval The clock source can be one of the following values: 1067 * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK Clock selected as XSPI1 clock 1068 * @arg RCC_XSPI1CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI1 clock 1069 * @arg RCC_XSPI1CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI1 clock 1070 * @arg RCC_XSPI1CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI1 clock 1071 */ 1072 #define __HAL_RCC_GET_XSPI1_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP) == RCC_XSPI1CLKSOURCE_HCLK_DIV4) ? \ 1073 RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL)))) 1074 1075 /** @brief Macro to configure the XSPI2 clock source. 1076 * 1077 * @param __XSPI2_CLKSOURCE__ specifies the XSPI2 clock source. 1078 * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK Clock selected as XSPI2 clock 1079 * @arg RCC_XSPI2CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI2 clock 1080 * @arg RCC_XSPI2CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI2 clock 1081 */ 1082 #define __HAL_RCC_XSPI2_CONFIG(__XSPI2_CLKSOURCE__) \ 1083 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL, (uint32_t)(__XSPI2_CLKSOURCE__)) 1084 1085 /** @brief Macro to get the XSPI2 clock source. 1086 * @retval The clock source can be one of the following values: 1087 * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK Clock selected as XSPI2 clock 1088 * @arg RCC_XSPI2CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI2 clock 1089 * @arg RCC_XSPI2CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI2 clock 1090 * @arg RCC_XSPI2CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI2 clock 1091 */ 1092 #define __HAL_RCC_GET_XSPI2_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP) == RCC_XSPI2CLKSOURCE_HCLK_DIV4) ? \ 1093 RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL)))) 1094 1095 /** 1096 * @brief Macro to configure the PSSI clock source. 1097 * @param __PSSI_CLKSOURCE__ defines the PSSI clock source. 1098 * This parameter can be one of the following values: 1099 * @arg RCC_PSSICLKSOURCE_PLL3R PLL3_R selected as PSSI clock 1100 * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock selected as PSSI clock 1101 * @retval None 1102 */ 1103 #define __HAL_RCC_PSSI_CONFIG(__PSSI_CLKSOURCE__) \ 1104 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_PSSISEL, (__PSSI_CLKSOURCE__)) 1105 1106 /** @brief Macro to get the PSSI clock source. 1107 * @retval The clock source can be one of the following values: 1108 * @arg RCC_PSSICLKSOURCE_PLL3R PLL3_R selected as PSSI clock 1109 * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock selected as PSSI clock 1110 */ 1111 #define __HAL_RCC_GET_PSSI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_PSSISEL))) 1112 1113 /** 1114 * @brief Macro to configure the SAI1 clock source. 1115 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. 1116 * This parameter can be one of the following values: 1117 * @arg RCC_SAI1CLKSOURCE_PLL1Q PLL1_Q selected as SAI1 clock 1118 * @arg RCC_SAI1CLKSOURCE_PLL2P PLL2_P selected as SAI1 clock 1119 * @arg RCC_SAI1CLKSOURCE_PLL3P PLL3_P selected as SAI1 clock 1120 * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock 1121 * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock selected as SAI1 clock 1122 * @retval None 1123 */ 1124 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \ 1125 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SAI1SEL, (__SAI1_CLKSOURCE__)) 1126 1127 /** @brief Macro to get the SAI1 clock source. 1128 * @retval The clock source can be one of the following values: 1129 * @arg RCC_SAI1CLKSOURCE_PLL1Q PLL1_Q selected as SAI1 clock 1130 * @arg RCC_SAI1CLKSOURCE_PLL2P PLL2_P selected as SAI1 clock 1131 * @arg RCC_SAI1CLKSOURCE_PLL3P PLL3_P selected as SAI1 clock 1132 * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock 1133 * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock selected as SAI1 clock 1134 */ 1135 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SAI1SEL))) 1136 1137 /** 1138 * @brief Macro to configure the SAI2 clock source. 1139 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. 1140 * This parameter can be one of the following values: 1141 * @arg RCC_SAI2CLKSOURCE_PLL1Q PLL1_Q selected as SAI2 clock 1142 * @arg RCC_SAI2CLKSOURCE_PLL2P PLL2_P selected as SAI2 clock 1143 * @arg RCC_SAI2CLKSOURCE_PLL3P PLL3_P selected as SAI2 clock 1144 * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock 1145 * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock selected as SAI2 clock 1146 * @arg RCC_SAI2CLKSOURCE_SPDIF SPDIF output clock selected as SAI2 clock 1147 * @retval None 1148 */ 1149 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) \ 1150 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SAI2SEL, (__SAI2_CLKSOURCE__)) 1151 1152 /** @brief Macro to get the SAI2 clock source. 1153 * @retval The clock source can be one of the following values: 1154 * @arg RCC_SAI2CLKSOURCE_PLL1Q PLL1_Q selected as SAI2 clock 1155 * @arg RCC_SAI2CLKSOURCE_PLL2P PLL2_P selected as SAI2 clock 1156 * @arg RCC_SAI2CLKSOURCE_PLL3P PLL3_P selected as SAI2 clock 1157 * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock 1158 * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock selected as SAI2 clock 1159 * @arg RCC_SAI2CLKSOURCE_SPDIF SPDIF output clock selected as SAI2 clock 1160 */ 1161 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SAI2SEL))) 1162 1163 1164 /** @brief Macro to configure the SDMMC kernel clock source. 1165 * @param __SDMMC12_CLKSOURCE__ specifies clock source for SDMMC 1166 * This parameter can be one of the following values: 1167 * @arg RCC_SDMMC12CLKSOURCE_PLL2S PLL2_S selected as SDMMC kernel clock 1168 * @arg RCC_SDMMC12CLKSOURCE_PLL2T PLL2_R selected as SDMMC kernel clock 1169 */ 1170 #define __HAL_RCC_SDMMC12_CONFIG(__SDMMC12_CLKSOURCE__) \ 1171 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL, (uint32_t)(__SDMMC12_CLKSOURCE__)) 1172 1173 /** @brief Macro to get the SDMMC kernel clock source. 1174 * @retval The clock source can be one of the following values: 1175 * @arg RCC_SDMMC12CLKSOURCE_PLL2S PLL2_S selected as SDMMC12 kernel clock 1176 * @arg RCC_SDMMC12CLKSOURCE_PLL2T PLL2_R selected as SDMMC12 kernel clock 1177 */ 1178 #define __HAL_RCC_GET_SDMMC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL))) 1179 1180 /** 1181 * @brief Macro to Configure the SPDIFRX clock source. 1182 * @param __SPDIFRX_CLKSOURCE__ defines the SPDIFRX clock source. 1183 * This parameter can be one of the following values: 1184 * @arg RCC_SPDIFRXCLKSOURCE_PLL1Q PLL1_Q selected as SPDIFRX clock 1185 * @arg RCC_SPDIFRXCLKSOURCE_PLL2R PLL2_R selected as SPDIFRX clock 1186 * @arg RCC_SPDIFRXCLKSOURCE_PLL3R PLL3_R selected as SPDIFRX clock 1187 * @arg RCC_SPDIFRXCLKSOURCE_HSI HSI selected as SPDIFRX clock 1188 * @retval None 1189 */ 1190 #define __HAL_RCC_SPDIFRX_CONFIG(__SPDIFRX_CLKSOURCE__ ) \ 1191 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL, (__SPDIFRX_CLKSOURCE__)) 1192 1193 /** 1194 * @brief Macro to get the SPDIFRX clock source. 1195 * @retval The clock source can be one of the following values: 1196 * @arg RCC_SPDIFRXCLKSOURCE_PLL1Q PLL1_Q selected as SPDIFRX clock 1197 * @arg RCC_SPDIFRXCLKSOURCE_PLL2R PLL2_R selected as SPDIFRX clock 1198 * @arg RCC_SPDIFRXCLKSOURCE_PLL3R PLL3_R selected as SPDIFRX clock 1199 * @arg RCC_SPDIFRXCLKSOURCE_HSI HSI selected as SPDIFRX clock 1200 * @retval None 1201 */ 1202 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL))) 1203 1204 /** 1205 * @brief Macro to configure the SPI1 clock source. 1206 * @param __SPI1_CLKSOURCE__ defines the SPI1 clock source. 1207 * This parameter can be one of the following values: 1208 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1_Q selected as SPI1 clock 1209 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2_P selected as SPI1 clock 1210 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3_P selected as SPI1 clock 1211 * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock 1212 * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock selected as SPI1 clock 1213 * @retval None 1214 */ 1215 #define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__ ) \ 1216 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (__SPI1_CLKSOURCE__)) 1217 1218 /** @brief Macro to get the SPI1 clock source. 1219 * @retval The clock source can be one of the following values: 1220 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1_Q selected as SPI1 clock 1221 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2_P selected as SPI1 clock 1222 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3_P selected as SPI1 clock 1223 * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock 1224 * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock selected as SPI1 clock 1225 */ 1226 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) 1227 1228 /** 1229 * @brief Macro to configure the SPI2/SPI3 clock source. 1230 * @param __SPI23_CLKSOURCE__ defines the SPI2/SPI3 clock source. 1231 * This parameter can be one of the following values: 1232 * @arg RCC_SPI23CLKSOURCE_PLL1Q PLL1_Q selected as SPI2/SPI3 clock 1233 * @arg RCC_SPI23CLKSOURCE_PLL2P PLL2_P selected as SPI2/SPI3 clock 1234 * @arg RCC_SPI23CLKSOURCE_PLL3P PLL3_P selected as SPI2/SPI3 clock 1235 * @arg RCC_SPI23CLKSOURCE_PIN External I2S_CKIN selected as SPI2/SPI3 clock 1236 * @arg RCC_SPI23CLKSOURCE_CLKP Peripheral clock selected as SPI2/SPI3 clock 1237 * @retval None 1238 */ 1239 #define __HAL_RCC_SPI23_CONFIG(__SPI23_CLKSOURCE__ ) \ 1240 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPI23SEL, (__SPI23_CLKSOURCE__)) 1241 1242 /** @brief Macro to get the SPI2/SPI3 clock source. 1243 * @retval The clock source can be one of the following values: 1244 * @arg RCC_SPI23CLKSOURCE_PLL1Q PLL1_Q selected as SPI2/SPI3 clock 1245 * @arg RCC_SPI23CLKSOURCE_PLL2P PLL2_P selected as SPI2/SPI3 clock 1246 * @arg RCC_SPI23CLKSOURCE_PLL3P PLL3_P selected as SPI2/SPI3 clock 1247 * @arg RCC_SPI23CLKSOURCE_PIN External I2S_CKIN selected as SPI2/SPI3 clock 1248 * @arg RCC_SPI23CLKSOURCE_CLKP Peripheral clock selected as SPI2/SPI3 clock 1249 */ 1250 #define __HAL_RCC_GET_SPI23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPI23SEL))) 1251 1252 /** 1253 * @brief Macro to configure the SPI4/SPI5 clock source. 1254 * @param __SPI45_CLKSOURCE__ defines the SPI4/SPI5 clock source. 1255 * This parameter can be one of the following values: 1256 * @arg RCC_SPI45CLKSOURCE_PCLK2 APB2 Clock selected as SPI4/SPI5 clock 1257 * @arg RCC_SPI45CLKSOURCE_PLL2Q PLL2_Q selected as SPI4/SPI5 clock 1258 * @arg RCC_SPI45CLKSOURCE_PLL3Q PLL3_Q selected as SPI4/SPI5 clock 1259 * @arg RCC_SPI45CLKSOURCE_HSI HSI selected as SPI4/SPI5 clock 1260 * @arg RCC_SPI45CLKSOURCE_CSI CSI selected as SPI4/SPI5 clock 1261 * @arg RCC_SPI45CLKSOURCE_HSE HSE selected as SPI4/SPI5 clock 1262 * @retval None 1263 */ 1264 #define __HAL_RCC_SPI45_CONFIG(__SPI45_CLKSOURCE__ ) \ 1265 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI45SEL, (__SPI45_CLKSOURCE__)) 1266 1267 /** @brief Macro to get the SPI4/SPI5 clock source. 1268 * @retval The clock source can be one of the following values: 1269 * @arg RCC_SPI45CLKSOURCE_PCLK2 APB2 Clock selected as SPI4/SPI5 clock 1270 * @arg RCC_SPI45CLKSOURCE_PLL2Q PLL2_Q selected as SPI4/SPI5 clock 1271 * @arg RCC_SPI45CLKSOURCE_PLL3Q PLL3_Q selected as SPI4/SPI5 clock 1272 * @arg RCC_SPI45CLKSOURCE_HSI HSI selected as SPI4/SPI5 clock 1273 * @arg RCC_SPI45CLKSOURCE_CSI CSI selected as SPI4/SPI5 clock 1274 * @arg RCC_SPI45CLKSOURCE_HSE HSE selected as SPI4/SPI5 clock 1275 */ 1276 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI45SEL))) 1277 1278 /** 1279 * @brief Macro to configure the SPI6 clock source. 1280 * @param __SPI6_CLKSOURCE__ defines the SPI6 clock source. 1281 * This parameter can be one of the following values: 1282 * @arg RCC_SPI6CLKSOURCE_PCLK4 APB4 Clock selected as SPI6 clock 1283 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2_Q selected as SPI6 clock 1284 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3_Q selected as SPI6 clock 1285 * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock 1286 * @arg RCC_SPI6CLKSOURCE_CSI CSI selected as SPI6 clock 1287 * @arg RCC_SPI6CLKSOURCE_HSE HSE selected as SPI6 clock 1288 * @retval None 1289 */ 1290 #define __HAL_RCC_SPI6_CONFIG(__SPI6_CLKSOURCE__ ) \ 1291 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SPI6SEL, (__SPI6_CLKSOURCE__)) 1292 1293 /** @brief Macro to get the SPI6 clock source. 1294 * @retval The clock source can be one of the following values: 1295 * @arg RCC_SPI6CLKSOURCE_PCLK4 APB4 Clock selected as SPI6 clock 1296 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2_Q selected as SPI6 clock 1297 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3_Q selected as SPI6 clock 1298 * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock 1299 * @arg RCC_SPI6CLKSOURCE_CSI CSI selected as SPI6 clock 1300 * @arg RCC_SPI6CLKSOURCE_HSE HSE selected as SPI6 clock 1301 */ 1302 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SPI6SEL))) 1303 1304 /** @brief Macro to configure the USART1 clock source. 1305 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1306 * This parameter can be one of the following values: 1307 * @arg RCC_USART1CLKSOURCE_PCLK2 APB2 Clock selected as USART1 clock 1308 * @arg RCC_USART1CLKSOURCE_PLL2Q PLL2_Q selected as USART1 clock 1309 * @arg RCC_USART1CLKSOURCE_PLL3Q PLL3_Q selected as USART1 clock 1310 * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1311 * @arg RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 1312 * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1313 */ 1314 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1315 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1316 1317 /** @brief Macro to get the USART1/6/9* /10* clock source. 1318 * @retval The clock source can be one of the following values: 1319 * @arg RCC_USART1CLKSOURCE_PCLK2 APB2 Clock selected as USART1 clock 1320 * @arg RCC_USART1CLKSOURCE_PLL2Q PLL2_Q selected as USART1 clock 1321 * @arg RCC_USART1CLKSOURCE_PLL3Q PLL3_Q selected as USART1 clock 1322 * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1323 * @arg RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 1324 * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1325 */ 1326 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_USART1SEL))) 1327 1328 /** @brief Macro to configure the USART2/USART3/UART4/UART5/UART7/UART8 clock source. 1329 * @param __USART234578_CLKSOURCE__ specifies the USART2/UART3/UART4/UART5/UART7/UART8 clock source. 1330 * This parameter can be one of the following values: 1331 * @arg RCC_USART234578CLKSOURCE_PCLK1 APB1 Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1332 * @arg RCC_USART234578CLKSOURCE_PLL2Q PLL2_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1333 * @arg RCC_USART234578CLKSOURCE_PLL3Q PLL3_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1334 * @arg RCC_USART234578CLKSOURCE_HSI HSI selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1335 * @arg RCC_USART234578CLKSOURCE_CSI CSI Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1336 * @arg RCC_USART234578CLKSOURCE_LSE LSE selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1337 */ 1338 #define __HAL_RCC_USART234578_CONFIG(__USART234578_CLKSOURCE__) \ 1339 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART234578SEL, (uint32_t)(__USART234578_CLKSOURCE__)) 1340 1341 /** @brief Macro to get the USART2/USART3/UART4/UART5/UART7/UART8 clock source. 1342 * @retval The clock source can be one of the following values: 1343 * @arg RCC_USART234578CLKSOURCE_PCLK1 APB1 Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1344 * @arg RCC_USART234578CLKSOURCE_PLL2Q PLL2_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1345 * @arg RCC_USART234578CLKSOURCE_PLL3Q PLL3_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1346 * @arg RCC_USART234578CLKSOURCE_HSI HSI selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1347 * @arg RCC_USART234578CLKSOURCE_CSI CSI Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1348 * @arg RCC_USART234578CLKSOURCE_LSE LSE selected as USART2/USART3/UART4/UART5/UART7/UART8 clock 1349 */ 1350 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART234578SEL))) 1351 1352 /** @brief Macro to configure the Timers clocks prescalers 1353 * @param __PRESC__ specifies the Timers clocks prescalers selection 1354 * This parameter can be one of the following values: 1355 * @arg RCC_TIMPRES_DISABLE 1356 * The timers kernel clock is equal to: 1357 * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 1358 * - 2*PCLKx_freq, otherwise (default after reset) 1359 * @arg RCC_TIMPRES_ENABLE 1360 * The timers kernel clock is equal to: 1361 * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 1362 * - 2*PCLKx_freq, if PCLKx = RCC_APBx_DIV2 1363 * - 4*PCLKx_freq, otherwise 1364 */ 1365 #define __HAL_RCC_TIMCLKPRESCALER_CONFIG(__PRESC__) \ 1366 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, (uint32_t)(__PRESC__)) 1367 1368 /** @brief Macro to get the Timers clocks prescalers 1369 * @retval The parameter can be one of the following values: 1370 * @arg RCC_TIMPRES_DISABLE 1371 * The timers kernel clock is equal to: 1372 * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 1373 * - 2*PCLKx_freq, otherwise (default after reset) 1374 * @arg RCC_TIMPRES_ENABLE 1375 * The timers kernel clock is equal to: 1376 * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 1377 * - 2*PCLKx_freq, if PCLKx = RCC_APBx_DIV2 1378 * - 4*PCLKx_freq, otherwise 1379 */ 1380 #define __HAL_RCC_GET_TIMCLKPRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE))) 1381 1382 /** @brief Macro to configure the USBPHYC clock. 1383 * @param __USBPHYC_CLKSOURCE__ specifies the USBPHYC clock source. 1384 * This parameter can be one of the following values: 1385 * @arg RCC_USBPHYCCLKSOURCE_HSE HSE selected as USBPHYC clock 1386 * @arg RCC_USBPHYCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHYC clock 1387 * @arg RCC_USBPHYCCLKSOURCE_PLL3Q PLL3_Q Clock selected as USBPHYC clock 1388 */ 1389 #define __HAL_RCC_USBPHYC_CONFIG(__USBPHYC_CLKSOURCE__) \ 1390 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL, (uint32_t)(__USBPHYC_CLKSOURCE__)) 1391 1392 /** @brief Macro to get the USBPHYC clock source. 1393 * @retval The clock source can be one of the following values: 1394 * @arg RCC_USBPHYCCLKSOURCE_HSE HSE selected as USBPHYC clock 1395 * @arg RCC_USBPHYCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHYC clock 1396 * @arg RCC_USBPHYCCLKSOURCE_PLL3Q PLL3_Q Clock selected as USBPHYC clock 1397 */ 1398 #define __HAL_RCC_GET_USBPHYC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL))) 1399 1400 /** @brief Macro to configure the USB OTGFS clock. 1401 * @param __USBOTGFS_CLKSOURCE__ specifies the USB OTGFS clock source. 1402 * This parameter can be one of the following values: 1403 * @arg RCC_USBOTGFSCLKSOURCE_HSI48 HSI48 selected as USB OTGFS clock 1404 * @arg RCC_USBOTGFSCLKSOURCE_PLL3Q PLL3_Q Clock selected as USB OTGFS clock 1405 * @arg RCC_USBOTGFSCLKSOURCE_HSE HSI48 selected as USB OTGFS clock 1406 * @arg RCC_USBOTGFSCLKSOURCE_CLK48 USBPHYC CLK48 output selected as USB OTGFS clock 1407 */ 1408 #define __HAL_RCC_USBOTGFS_CONFIG(__USBOTGFS_CLKSOURCE__) \ 1409 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL, (uint32_t)(__USBOTGFS_CLKSOURCE__)) 1410 1411 /** @brief Macro to get the USB OTGFS clock source. 1412 * @retval The clock source can be one of the following values: 1413 * @arg RCC_USBOTGFSCLKSOURCE_HSI48 HSI48 selected as USB OTGFS clock 1414 * @arg RCC_USBOTGFSCLKSOURCE_PLL3Q PLL3_Q Clock selected as USB OTGFS clock 1415 * @arg RCC_USBOTGFSCLKSOURCE_HSE HSI48 selected as USB OTGFS clock 1416 * @arg RCC_USBOTGFSCLKSOURCE_CLK48 USBPHYC CLK48 output selected as USB OTGFS clock 1417 */ 1418 #define __HAL_RCC_GET_USBOTGFS_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL))) 1419 1420 /** 1421 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 1422 * @retval None 1423 */ 1424 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1425 1426 /** 1427 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 1428 * @retval None 1429 */ 1430 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1431 1432 /** 1433 * @brief Enable the RCC LSE CSS Event Line. 1434 * @retval None. 1435 */ 1436 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1437 1438 /** 1439 * @brief Disable the RCC LSE CSS Event Line. 1440 * @retval None. 1441 */ 1442 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1443 1444 /** 1445 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1446 * @retval None. 1447 */ 1448 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1449 1450 /** 1451 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1452 * @retval None. 1453 */ 1454 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1455 1456 /** 1457 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1458 * @retval None. 1459 */ 1460 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1461 1462 /** 1463 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1464 * @retval None. 1465 */ 1466 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1467 1468 /** 1469 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1470 * @retval None. 1471 */ 1472 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1473 do { \ 1474 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1475 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1476 } while(0) 1477 1478 /** 1479 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1480 * @retval None. 1481 */ 1482 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1483 do { \ 1484 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1485 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1486 } while(0) 1487 1488 /** 1489 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1490 * @retval EXTI RCC LSE CSS Line Status. 1491 */ 1492 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 1493 1494 /** 1495 * @brief Clear the RCC LSE CSS EXTI flag. 1496 * @retval None. 1497 */ 1498 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 1499 1500 /** 1501 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1502 * @retval None. 1503 */ 1504 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 1505 1506 /** 1507 * @brief Enable the specified CRS interrupts. 1508 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1509 * This parameter can be any combination of the following values: 1510 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1511 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1512 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1513 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1514 * @retval None 1515 */ 1516 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1517 1518 /** 1519 * @brief Disable the specified CRS interrupts. 1520 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1521 * This parameter can be any combination of the following values: 1522 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1523 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1524 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1525 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1526 * @retval None 1527 */ 1528 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1529 1530 /** @brief Check whether the CRS interrupt has occurred or not. 1531 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1532 * This parameter can be one of the following values: 1533 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1534 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1535 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1536 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1537 * @retval The new state of __INTERRUPT__ (SET or RESET). 1538 */ 1539 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 1540 1541 /** @brief Clear the CRS interrupt pending bits 1542 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1543 * This parameter can be any combination of the following values: 1544 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1545 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1546 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1547 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1548 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1549 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1550 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1551 */ 1552 /* CRS IT Error Mask */ 1553 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ 1554 RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 1555 1556 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1557 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1558 { \ 1559 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1560 } \ 1561 else \ 1562 { \ 1563 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1564 } \ 1565 } while(0) 1566 1567 /** 1568 * @brief Check whether the specified CRS flag is set or not. 1569 * @param __FLAG__ specifies the flag to check. 1570 * This parameter can be one of the following values: 1571 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1572 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1573 * @arg @ref RCC_CRS_FLAG_ERR Error 1574 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1575 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1576 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1577 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1578 * @retval The new state of _FLAG_ (TRUE or FALSE). 1579 */ 1580 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1581 1582 /** 1583 * @brief Clear the CRS specified FLAG. 1584 * @param __FLAG__ specifies the flag to clear. 1585 * This parameter can be one of the following values: 1586 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1587 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1588 * @arg @ref RCC_CRS_FLAG_ERR Error 1589 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1590 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1591 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1592 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1593 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1594 * @retval None 1595 */ 1596 1597 /* CRS Flag Error Mask */ 1598 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ 1599 RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 1600 1601 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1602 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1603 { \ 1604 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1605 } \ 1606 else \ 1607 { \ 1608 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1609 } \ 1610 } while(0) 1611 1612 /** @defgroup RCCEx_CRS_Extended_Features CRS Extended Features 1613 * @{ 1614 */ 1615 /** 1616 * @brief Enable the oscillator clock for frequency error counter. 1617 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1618 * @retval None 1619 */ 1620 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1621 1622 /** 1623 * @brief Disable the oscillator clock for frequency error counter. 1624 * @retval None 1625 */ 1626 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1627 1628 /** 1629 * @brief Enable the automatic hardware adjustment of TRIM bits. 1630 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1631 * @retval None 1632 */ 1633 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1634 1635 /** 1636 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1637 * @retval None 1638 */ 1639 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1640 1641 /** 1642 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1643 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1644 * of the synchronization source after pre-scaling. It is then decreased by one in order to 1645 * reach the expected synchronization on the zero value. The formula is the following: 1646 * RELOAD = (fTARGET / fSYNC) -1 1647 * @param __FTARGET__ Target frequency (value in Hz) 1648 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1649 * @retval None 1650 */ 1651 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1652 1653 /** 1654 * @} 1655 */ 1656 1657 /** 1658 * @} 1659 */ 1660 1661 /* Exported functions --------------------------------------------------------*/ 1662 /** @addtogroup RCCEx_Exported_Functions 1663 * @{ 1664 */ 1665 /** @addtogroup RCCEx_Exported_Functions_Group1 1666 * @{ 1667 */ 1668 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1669 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1670 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1671 void HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk); 1672 void HAL_RCCEx_DisableClockProtection(uint32_t ProtectClk); 1673 /** 1674 * @} 1675 */ 1676 1677 /** @addtogroup RCCEx_Exported_Functions_Group2 1678 * @{ 1679 */ 1680 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1681 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 1682 void HAL_RCCEx_EnableLSECSS(void); 1683 void HAL_RCCEx_DisableLSECSS(void); 1684 void HAL_RCCEx_EnableLSECSS_IT(void); 1685 void HAL_RCCEx_LSECSS_IRQHandler(void); 1686 void HAL_RCCEx_LSECSS_Callback(void); 1687 /** 1688 * @} 1689 */ 1690 1691 /** @addtogroup RCCEx_Exported_Functions_Group3 1692 * @{ 1693 */ 1694 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); 1695 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1696 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1697 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1698 void HAL_RCCEx_CRS_IRQHandler(void); 1699 void HAL_RCCEx_CRS_SyncOkCallback(void); 1700 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1701 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1702 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1703 /** 1704 * @} 1705 */ 1706 1707 /** 1708 * @} 1709 */ 1710 1711 /* Private macros ------------------------------------------------------------*/ 1712 /** @addtogroup RCCEx_Private_Macros 1713 * @{ 1714 */ 1715 1716 /** @defgroup RCCEx_IS_RCC_Definitions Private macros to check input parameters 1717 * @{ 1718 */ 1719 1720 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1721 ((((__SELECTION__) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ 1722 (((__SELECTION__) & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) || \ 1723 (((__SELECTION__) & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) || \ 1724 (((__SELECTION__) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ 1725 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1726 (((__SELECTION__) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) || \ 1727 (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 1728 (((__SELECTION__) & RCC_PERIPHCLK_ETH1REF) == RCC_PERIPHCLK_ETH1REF) || \ 1729 (((__SELECTION__) & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) || \ 1730 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1731 (((__SELECTION__) & RCC_PERIPHCLK_I2C1_I3C1) == RCC_PERIPHCLK_I2C1_I3C1) || \ 1732 (((__SELECTION__) & RCC_PERIPHCLK_I2C23) == RCC_PERIPHCLK_I2C23) || \ 1733 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1734 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) || \ 1735 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) || \ 1736 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1737 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 1738 (((__SELECTION__) & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) || \ 1739 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1740 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1741 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 1742 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) || \ 1743 (((__SELECTION__) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 1744 (((__SELECTION__) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ 1745 (((__SELECTION__) & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) || \ 1746 (((__SELECTION__) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) || \ 1747 (((__SELECTION__) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ 1748 (((__SELECTION__) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 1749 (((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1750 (((__SELECTION__) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) || \ 1751 (((__SELECTION__) & RCC_PERIPHCLK_USBPHYC) == RCC_PERIPHCLK_USBPHYC) || \ 1752 (((__SELECTION__) & RCC_PERIPHCLK_USBOTGFS) == RCC_PERIPHCLK_USBOTGFS)) 1753 1754 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 1755 (((__SOURCE__) == RCC_ADCCLKSOURCE_PLL2P) || \ 1756 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL3R) || \ 1757 ((__SOURCE__) == RCC_ADCCLKSOURCE_CLKP)) 1758 1759 #define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ 1760 (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ 1761 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL2P) || \ 1762 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3P) || \ 1763 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ 1764 ((__SOURCE__) == RCC_ADF1CLKSOURCE_CSI) || \ 1765 ((__SOURCE__) == RCC_ADF1CLKSOURCE_HSI)) 1766 1767 #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ 1768 (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ 1769 ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ 1770 ((__SOURCE__) == RCC_CECCLKSOURCE_CSI)) 1771 1772 #define IS_RCC_CKPERCLKSOURCE(__SOURCE__) \ 1773 (((__SOURCE__) == RCC_CLKPSOURCE_HSI) || \ 1774 ((__SOURCE__) == RCC_CLKPSOURCE_CSI) || \ 1775 ((__SOURCE__) == RCC_CLKPSOURCE_HSE)) 1776 1777 #define IS_RCC_ETH1REFCLKSOURCE(__SOURCE__) \ 1778 (((__SOURCE__) == RCC_ETH1REFCLKSOURCE_PHY) || \ 1779 ((__SOURCE__) == RCC_ETH1REFCLKSOURCE_HSE) || \ 1780 ((__SOURCE__) == RCC_ETH1REFCLKSOURCE_ETH)) 1781 1782 #define IS_RCC_ETH1PHYCLKSOURCE(__SOURCE__) \ 1783 (((__SOURCE__) == RCC_ETH1PHYCLKSOURCE_HSE) || \ 1784 ((__SOURCE__) == RCC_ETH1PHYCLKSOURCE_PLL3S)) 1785 1786 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 1787 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 1788 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL1Q) || \ 1789 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2P)) 1790 1791 #define IS_RCC_FMCCLKSOURCE(__SOURCE__) \ 1792 (((__SOURCE__) == RCC_FMCCLKSOURCE_HCLK) || \ 1793 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL1Q) || \ 1794 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2R) || \ 1795 ((__SOURCE__) == RCC_FMCCLKSOURCE_HSI)) 1796 1797 #define IS_RCC_I2C1_I3C1CLKSOURCE(__SOURCE__) \ 1798 (((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_PCLK1) || \ 1799 ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_PLL3R) || \ 1800 ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_HSI) || \ 1801 ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_CSI)) 1802 1803 #define IS_RCC_I2C23CLKSOURCE(__SOURCE__) \ 1804 (((__SOURCE__) == RCC_I2C23CLKSOURCE_PCLK1) || \ 1805 ((__SOURCE__) == RCC_I2C23CLKSOURCE_PLL3R) || \ 1806 ((__SOURCE__) == RCC_I2C23CLKSOURCE_HSI) || \ 1807 ((__SOURCE__) == RCC_I2C23CLKSOURCE_CSI)) 1808 1809 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 1810 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 1811 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ 1812 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI) || \ 1813 ((__SOURCE__) == RCC_I3C1CLKSOURCE_CSI)) 1814 1815 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1816 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 1817 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 1818 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ 1819 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 1820 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1821 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 1822 1823 #define IS_RCC_LPTIM23CLKSOURCE(__SOURCE__) \ 1824 (((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PCLK4) || \ 1825 ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PLL2P) || \ 1826 ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PLL3R) || \ 1827 ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_LSE) || \ 1828 ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_LSI) || \ 1829 ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_CLKP)) 1830 1831 #define IS_RCC_LPTIM45CLKSOURCE(__SOURCE__) \ 1832 (((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PCLK4) || \ 1833 ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PLL2P) || \ 1834 ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PLL3R) || \ 1835 ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_LSE) || \ 1836 ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_LSI) || \ 1837 ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_CLKP)) 1838 1839 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1840 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK4) || \ 1841 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 1842 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ 1843 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 1844 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI) || \ 1845 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)) 1846 1847 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 1848 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3R) 1849 1850 #define IS_RCC_XSPI1CLKSOURCE(__SOURCE__) \ 1851 (((__SOURCE__) == RCC_XSPI1CLKSOURCE_HCLK) || \ 1852 ((__SOURCE__) == RCC_XSPI1CLKSOURCE_PLL2S) || \ 1853 ((__SOURCE__) == RCC_XSPI1CLKSOURCE_PLL2T)) 1854 1855 #define IS_RCC_XSPI2CLKSOURCE(__SOURCE__) \ 1856 (((__SOURCE__) == RCC_XSPI2CLKSOURCE_HCLK) || \ 1857 ((__SOURCE__) == RCC_XSPI2CLKSOURCE_PLL2S) || \ 1858 ((__SOURCE__) == RCC_XSPI2CLKSOURCE_PLL2T)) 1859 1860 #define IS_RCC_PSSICLKSOURCE(__SOURCE__) \ 1861 (((__SOURCE__) == RCC_PSSICLKSOURCE_PLL3R) || \ 1862 ((__SOURCE__) == RCC_PSSICLKSOURCE_CLKP)) 1863 1864 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 1865 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q) || \ 1866 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P) || \ 1867 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P) || \ 1868 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 1869 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 1870 1871 #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ 1872 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q) || \ 1873 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P) || \ 1874 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P) || \ 1875 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 1876 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 1877 ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIF)) 1878 1879 #define IS_RCC_SDMMC12CLKSOURCE(__SOURCE__) \ 1880 (((__SOURCE__) == RCC_SDMMC12CLKSOURCE_PLL2S) || \ 1881 ((__SOURCE__) == RCC_SDMMC12CLKSOURCE_PLL2T)) 1882 1883 #define IS_RCC_SPDIFRXCLKSOURCE(__SOURCE__) \ 1884 (((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL1Q) || \ 1885 ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL2R) || \ 1886 ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL3R) || \ 1887 ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_HSI)) 1888 1889 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 1890 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 1891 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 1892 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ 1893 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 1894 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 1895 1896 #define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \ 1897 (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL1Q) || \ 1898 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL2P) || \ 1899 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3P) || \ 1900 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PIN) || \ 1901 ((__SOURCE__) == RCC_SPI23CLKSOURCE_CLKP)) 1902 1903 #define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \ 1904 (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \ 1905 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2Q) || \ 1906 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3Q) || \ 1907 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 1908 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 1909 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 1910 1911 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 1912 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK4) || \ 1913 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ 1914 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ 1915 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 1916 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 1917 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 1918 1919 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1920 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1921 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 1922 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ 1923 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 1924 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 1925 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 1926 1927 #define IS_RCC_USART234578CLKSOURCE(__SOURCE__) \ 1928 (((__SOURCE__) == RCC_USART234578CLKSOURCE_PCLK1) || \ 1929 ((__SOURCE__) == RCC_USART234578CLKSOURCE_PLL2Q) || \ 1930 ((__SOURCE__) == RCC_USART234578CLKSOURCE_PLL3Q) || \ 1931 ((__SOURCE__) == RCC_USART234578CLKSOURCE_HSI) || \ 1932 ((__SOURCE__) == RCC_USART234578CLKSOURCE_LSE) || \ 1933 ((__SOURCE__) == RCC_USART234578CLKSOURCE_CSI)) 1934 1935 #define IS_RCC_USBPHYCCLKSOURCE(__SOURCE__) \ 1936 (((__SOURCE__) == RCC_USBPHYCCLKSOURCE_HSE) || \ 1937 ((__SOURCE__) == RCC_USBPHYCCLKSOURCE_HSE_DIV2) || \ 1938 ((__SOURCE__) == RCC_USBPHYCCLKSOURCE_PLL3Q)) 1939 1940 #define IS_RCC_USBOTGFSCLKSOURCE(__SOURCE__) \ 1941 (((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_HSI48) || \ 1942 ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_PLL3Q) || \ 1943 ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_HSE) || \ 1944 ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_CLK48)) 1945 1946 #define IS_RCC_TIMCLKPRESCALER(__VALUE__) \ 1947 (((__VALUE__) == RCC_TIMPRES_DISABLE) || \ 1948 ((__VALUE__) == RCC_TIMPRES_ENABLE)) 1949 1950 #define IS_RCC_CLOCKPROTECTION(__CLOCK__) \ 1951 ((((__CLOCK__) & RCC_CLOCKPROTECT_FMC) == RCC_CLOCKPROTECT_FMC) || \ 1952 (((__CLOCK__) & RCC_CLOCKPROTECT_XSPI) == RCC_CLOCKPROTECT_XSPI) || \ 1953 (((__CLOCK__) & ~(RCC_CLOCKPROTECT_FMC | RCC_CLOCKPROTECT_XSPI)) == 0U)) 1954 1955 1956 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1957 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB_OTG_FS) || \ 1958 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB_OTG_HS) || \ 1959 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO)) 1960 1961 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1962 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1963 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1964 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1965 1966 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1967 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1968 1969 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) ((__VALUE__) <= CRS_CFGR_RELOAD) 1970 1971 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) ((__VALUE__) <= (CRS_CFGR_FELIM >> CRS_CFGR_FELIM_Pos)) 1972 1973 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) ((__VALUE__) <= (CRS_CR_TRIM >> CRS_CR_TRIM_Pos)) 1974 1975 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1976 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1977 /** 1978 * @} 1979 */ 1980 1981 /** 1982 * @} 1983 */ 1984 1985 /** 1986 * @} 1987 */ 1988 1989 /** 1990 * @} 1991 */ 1992 #ifdef __cplusplus 1993 } 1994 #endif 1995 1996 #endif /* STM32H7RSxx_HAL_RCC_EX_H */ 1997
