1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G4xx_HAL_RCC_EX_H 20 #define STM32G4xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g4xx_hal_def.h" 28 29 /** @addtogroup STM32G4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC extended clocks structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 49 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 50 51 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 52 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 53 54 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 55 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 56 #if defined(USART3) 57 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 58 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 59 #endif /* UART3 */ 60 61 #if defined(UART4) 62 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 63 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 64 #endif /* UART4 */ 65 66 #if defined(UART5) 67 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 68 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 69 70 #endif /* UART5 */ 71 72 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 73 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 74 75 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 76 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 77 78 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 79 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 80 81 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 82 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 83 84 #if defined(I2C4) 85 86 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 87 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 88 #endif /* I2C4 */ 89 90 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 91 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 92 93 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 94 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 95 96 uint32_t I2sClockSelection; /*!< Specifies I2S clock source. 97 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 98 #if defined(FDCAN1) 99 100 uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. 101 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 102 #endif /* FDCAN1 */ 103 #if defined(USB) 104 105 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). 106 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 107 #endif /* USB */ 108 109 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). 110 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 111 112 uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. 113 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 114 115 #if defined(ADC345_COMMON) 116 uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. 117 This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ 118 #endif /* ADC345_COMMON */ 119 120 #if defined(QUADSPI) 121 uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. 122 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 123 #endif 124 125 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 126 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 127 }RCC_PeriphCLKInitTypeDef; 128 129 /** 130 * @brief RCC_CRS Init structure definition 131 */ 132 typedef struct 133 { 134 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 135 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 136 137 uint32_t Source; /*!< Specifies the SYNC signal source. 138 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 139 140 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 141 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 142 143 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 144 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 145 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 146 147 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 148 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 149 150 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 151 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 152 153 }RCC_CRSInitTypeDef; 154 155 /** 156 * @brief RCC_CRS Synchronization structure definition 157 */ 158 typedef struct 159 { 160 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 161 This parameter must be a number between 0 and 0xFFFF */ 162 163 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 164 This parameter must be a number between 0 and 0x7F */ 165 166 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 167 value latched in the time of the last SYNC event. 168 This parameter must be a number between 0 and 0xFFFF */ 169 170 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 171 frequency error counter latched in the time of the last SYNC event. 172 It shows whether the actual frequency is below or above the target. 173 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 174 175 }RCC_CRSSynchroInfoTypeDef; 176 177 /** 178 * @} 179 */ 180 181 /* Exported constants --------------------------------------------------------*/ 182 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 183 * @{ 184 */ 185 186 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 187 * @{ 188 */ 189 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 190 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 191 /** 192 * @} 193 */ 194 195 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 196 * @{ 197 */ 198 #define RCC_PERIPHCLK_USART1 0x00000001U 199 #define RCC_PERIPHCLK_USART2 0x00000002U 200 #define RCC_PERIPHCLK_USART3 0x00000004U 201 #if defined(UART4) 202 #define RCC_PERIPHCLK_UART4 0x00000008U 203 #endif /* UART4 */ 204 #if defined(UART5) 205 #define RCC_PERIPHCLK_UART5 0x00000010U 206 #endif /* UART5 */ 207 #define RCC_PERIPHCLK_LPUART1 0x00000020U 208 #define RCC_PERIPHCLK_I2C1 0x00000040U 209 #define RCC_PERIPHCLK_I2C2 0x00000080U 210 #define RCC_PERIPHCLK_I2C3 0x00000100U 211 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 212 #define RCC_PERIPHCLK_SAI1 0x00000400U 213 #define RCC_PERIPHCLK_I2S 0x00000800U 214 #if defined(FDCAN1) 215 #define RCC_PERIPHCLK_FDCAN 0x00001000U 216 #endif /* FDCAN1 */ 217 #define RCC_PERIPHCLK_USB 0x00002000U 218 #define RCC_PERIPHCLK_RNG 0x00004000U 219 #define RCC_PERIPHCLK_ADC12 0x00008000U 220 #if defined(ADC345_COMMON) 221 #define RCC_PERIPHCLK_ADC345 0x00010000U 222 #endif /* ADC345_COMMON */ 223 #if defined(I2C4) 224 #define RCC_PERIPHCLK_I2C4 0x00020000U 225 #endif /* I2C4 */ 226 #if defined(QUADSPI) 227 #define RCC_PERIPHCLK_QSPI 0x00040000U 228 #endif /* QUADSPI */ 229 #define RCC_PERIPHCLK_RTC 0x00080000U 230 /** 231 * @} 232 */ 233 234 235 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 236 * @{ 237 */ 238 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 239 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 240 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 241 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 242 /** 243 * @} 244 */ 245 246 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 247 * @{ 248 */ 249 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 250 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 251 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 252 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 253 /** 254 * @} 255 */ 256 257 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 258 * @{ 259 */ 260 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 261 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 262 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 263 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 264 /** 265 * @} 266 */ 267 268 #if defined(UART4) 269 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 270 * @{ 271 */ 272 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 273 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 274 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 275 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 276 /** 277 * @} 278 */ 279 #endif /* UART4 */ 280 281 #if defined(UART5) 282 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 283 * @{ 284 */ 285 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 286 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 287 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 288 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 289 /** 290 * @} 291 */ 292 #endif /* UART5 */ 293 294 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 295 * @{ 296 */ 297 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 298 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 299 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 300 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 301 /** 302 * @} 303 */ 304 305 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 306 * @{ 307 */ 308 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 309 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 310 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 311 /** 312 * @} 313 */ 314 315 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 316 * @{ 317 */ 318 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 319 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 320 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 321 /** 322 * @} 323 */ 324 325 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 326 * @{ 327 */ 328 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 329 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 330 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 336 * @{ 337 */ 338 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 339 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 340 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 341 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 347 * @{ 348 */ 349 #define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U 350 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 351 #define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 352 #define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) 353 /** 354 * @} 355 */ 356 357 #if defined(SPI_I2S_SUPPORT) 358 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 359 * @{ 360 */ 361 #define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U 362 #define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 363 #define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 364 #define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) 365 /** 366 * @} 367 */ 368 #endif /* SPI_I2S_SUPPORT */ 369 370 #if defined(FDCAN1) 371 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source 372 * @{ 373 */ 374 #define RCC_FDCANCLKSOURCE_HSE 0x00000000U 375 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 376 #define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 377 /** 378 * @} 379 */ 380 #endif /* FDCAN1 */ 381 382 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 383 * @{ 384 */ 385 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 386 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 387 /** 388 * @} 389 */ 390 391 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 392 * @{ 393 */ 394 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 395 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 396 /** 397 * @} 398 */ 399 400 /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source 401 * @{ 402 */ 403 #define RCC_ADC12CLKSOURCE_NONE 0x00000000U 404 #define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 405 #define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 406 /** 407 * @} 408 */ 409 410 #if defined(ADC345_COMMON) 411 /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source 412 * @{ 413 */ 414 #define RCC_ADC345CLKSOURCE_NONE 0x00000000U 415 #define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 416 #define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 417 /** 418 * @} 419 */ 420 #endif /* ADC345_COMMON */ 421 422 #if defined(I2C4) 423 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 424 * @{ 425 */ 426 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 427 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 428 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 429 /** 430 * @} 431 */ 432 #endif /* I2C4 */ 433 434 #if defined(QUADSPI) 435 /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source 436 * @{ 437 */ 438 #define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U 439 #define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 440 #define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 441 /** 442 * @} 443 */ 444 #endif /* QUADSPI */ 445 446 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 447 * @{ 448 */ 449 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 455 * @{ 456 */ 457 #define RCC_CRS_NONE 0x00000000U 458 #define RCC_CRS_TIMEOUT 0x00000001U 459 #define RCC_CRS_SYNCOK 0x00000002U 460 #define RCC_CRS_SYNCWARN 0x00000004U 461 #define RCC_CRS_SYNCERR 0x00000008U 462 #define RCC_CRS_SYNCMISS 0x00000010U 463 #define RCC_CRS_TRIMOVF 0x00000020U 464 /** 465 * @} 466 */ 467 468 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 469 * @{ 470 */ 471 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 472 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 473 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 474 /** 475 * @} 476 */ 477 478 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 479 * @{ 480 */ 481 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 482 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 483 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 484 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 485 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 486 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 487 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 488 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 494 * @{ 495 */ 496 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 497 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 498 /** 499 * @} 500 */ 501 502 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 503 * @{ 504 */ 505 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 506 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 507 /** 508 * @} 509 */ 510 511 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 512 * @{ 513 */ 514 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 520 * @{ 521 */ 522 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 523 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 524 corresponds to a higher output frequency */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 530 * @{ 531 */ 532 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 533 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 539 * @{ 540 */ 541 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 542 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 543 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 544 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 545 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 546 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 547 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 548 549 /** 550 * @} 551 */ 552 553 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 554 * @{ 555 */ 556 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 557 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 558 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 559 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 560 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 561 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 562 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 563 564 /** 565 * @} 566 */ 567 568 /** 569 * @} 570 */ 571 572 /* Exported macros -----------------------------------------------------------*/ 573 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 574 * @{ 575 */ 576 577 /** @brief Macro to configure the USART1 clock (USART1CLK). 578 * 579 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 580 * This parameter can be one of the following values: 581 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 582 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 583 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 584 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 585 * @retval None 586 */ 587 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 588 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 589 590 /** @brief Macro to get the USART1 clock source. 591 * @retval The clock source can be one of the following values: 592 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 593 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 594 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 595 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 596 */ 597 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 598 599 /** @brief Macro to configure the USART2 clock (USART2CLK). 600 * 601 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 602 * This parameter can be one of the following values: 603 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 604 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 605 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 606 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 607 * @retval None 608 */ 609 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 610 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 611 612 /** @brief Macro to get the USART2 clock source. 613 * @retval The clock source can be one of the following values: 614 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 615 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 616 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 617 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 618 */ 619 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 620 621 /** @brief Macro to configure the USART3 clock (USART3CLK). 622 * 623 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 624 * This parameter can be one of the following values: 625 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 626 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 627 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 628 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 629 * @retval None 630 */ 631 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 632 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 633 634 /** @brief Macro to get the USART3 clock source. 635 * @retval The clock source can be one of the following values: 636 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 637 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 638 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 639 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 640 */ 641 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 642 643 #if defined(UART4) 644 /** @brief Macro to configure the UART4 clock (UART4CLK). 645 * 646 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 647 * This parameter can be one of the following values: 648 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 649 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 650 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 651 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 652 * @retval None 653 */ 654 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 655 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 656 657 /** @brief Macro to get the UART4 clock source. 658 * @retval The clock source can be one of the following values: 659 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 660 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 661 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 662 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 663 */ 664 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 665 #endif /* UART4 */ 666 667 #if defined(UART5) 668 669 /** @brief Macro to configure the UART5 clock (UART5CLK). 670 * 671 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 672 * This parameter can be one of the following values: 673 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 674 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 675 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 676 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 677 * @retval None 678 */ 679 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 680 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 681 682 /** @brief Macro to get the UART5 clock source. 683 * @retval The clock source can be one of the following values: 684 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 685 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 686 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 687 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 688 */ 689 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 690 691 #endif /* UART5 */ 692 693 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 694 * 695 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 696 * This parameter can be one of the following values: 697 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 698 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 699 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 700 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 701 * @retval None 702 */ 703 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 704 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 705 706 /** @brief Macro to get the LPUART1 clock source. 707 * @retval The clock source can be one of the following values: 708 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 709 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 710 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 711 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 712 */ 713 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 714 715 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 716 * 717 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 718 * This parameter can be one of the following values: 719 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 720 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 721 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 722 * @retval None 723 */ 724 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 725 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 726 727 /** @brief Macro to get the I2C1 clock source. 728 * @retval The clock source can be one of the following values: 729 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 730 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 731 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 732 */ 733 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 734 735 736 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 737 * 738 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 739 * This parameter can be one of the following values: 740 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 741 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 742 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 743 * @retval None 744 */ 745 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 746 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 747 748 /** @brief Macro to get the I2C2 clock source. 749 * @retval The clock source can be one of the following values: 750 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 751 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 752 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 753 */ 754 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 755 756 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 757 * 758 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 759 * This parameter can be one of the following values: 760 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 761 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 762 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 763 * @retval None 764 */ 765 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 766 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 767 768 /** @brief Macro to get the I2C3 clock source. 769 * @retval The clock source can be one of the following values: 770 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 771 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 772 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 773 */ 774 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 775 776 #if defined(I2C4) 777 778 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 779 * 780 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 781 * This parameter can be one of the following values: 782 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 783 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 784 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 785 * @retval None 786 */ 787 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 788 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 789 790 /** @brief Macro to get the I2C4 clock source. 791 * @retval The clock source can be one of the following values: 792 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 793 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 794 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 795 */ 796 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 797 798 #endif /* I2C4 */ 799 800 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 801 * 802 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 803 * This parameter can be one of the following values: 804 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 805 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 806 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 807 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 808 * @retval None 809 */ 810 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 811 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 812 813 /** @brief Macro to get the LPTIM1 clock source. 814 * @retval The clock source can be one of the following values: 815 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 816 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 817 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 818 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 819 */ 820 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 821 822 /** 823 * @brief Macro to configure the SAI1 clock source. 824 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 825 * from the HSI, system PLL, System Clock or external clock. 826 * This parameter can be one of the following values: 827 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 828 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 829 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 830 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 831 * 832 * @retval None 833 */ 834 835 #if defined(SAI1) 836 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 837 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 838 839 /** @brief Macro to get the SAI1 clock source. 840 * @retval The clock source can be one of the following values: 841 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 842 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 843 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 844 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 845 * 846 */ 847 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 848 #endif /* SAI1 */ 849 850 #if defined(SPI_I2S_SUPPORT) 851 /** 852 * @brief Macro to configure the I2S clock source. 853 * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived 854 * from the HSI, system PLL, System Clock or external clock. 855 * This parameter can be one of the following values: 856 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 857 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 858 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 859 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 860 * 861 * @retval None 862 */ 863 #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ 864 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) 865 866 /** @brief Macro to get the I2S clock source. 867 * @retval The clock source can be one of the following values: 868 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 869 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 870 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 871 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 872 * 873 */ 874 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) 875 #endif /* SPI_I2S_SUPPORT */ 876 877 #if defined(FDCAN1) 878 /** 879 * @brief Macro to configure the FDCAN clock source. 880 * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived 881 * from the HSE, system PLL or PCLK1. 882 * This parameter can be one of the following values: 883 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 884 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 885 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 886 * 887 * @retval None 888 */ 889 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ 890 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 891 892 /** @brief Macro to get the FDCAN clock source. 893 * @retval The clock source can be one of the following values: 894 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 895 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 896 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 897 * 898 */ 899 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) 900 #endif /* FDCAN1 */ 901 902 /** @brief Macro to configure the RNG clock. 903 * 904 * @note USB and RNG peripherals share the same 48MHz clock source. 905 * 906 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 907 * This parameter can be one of the following values: 908 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 909 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 910 * @retval None 911 */ 912 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 913 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 914 915 /** @brief Macro to get the RNG clock. 916 * @retval The clock source can be one of the following values: 917 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 918 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock 919 */ 920 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 921 922 #if defined(USB) 923 924 /** @brief Macro to configure the USB clock (USBCLK). 925 * 926 * @note USB, RNG peripherals share the same 48MHz clock source. 927 * 928 * @param __USB_CLKSOURCE__ specifies the USB clock source. 929 * This parameter can be one of the following values: 930 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 931 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 932 * @retval None 933 */ 934 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 935 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 936 937 /** @brief Macro to get the USB clock source. 938 * @retval The clock source can be one of the following values: 939 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 940 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 941 */ 942 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 943 944 #endif /* USB */ 945 946 /** @brief Macro to configure the ADC12 interface clock. 947 * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. 948 * This parameter can be one of the following values: 949 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 950 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 951 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 952 * @retval None 953 */ 954 #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ 955 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) 956 957 /** @brief Macro to get the ADC12 clock source. 958 * @retval The clock source can be one of the following values: 959 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 960 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 961 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 962 */ 963 #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) 964 965 #if defined(ADC345_COMMON) 966 /** @brief Macro to configure the ADC345 interface clock. 967 * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. 968 * This parameter can be one of the following values: 969 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 970 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 971 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 972 * @retval None 973 */ 974 #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ 975 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) 976 977 /** @brief Macro to get the ADC345 clock source. 978 * @retval The clock source can be one of the following values: 979 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 980 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 981 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 982 */ 983 #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) 984 #endif /* ADC345_COMMON */ 985 986 #if defined(QUADSPI) 987 988 /** @brief Macro to configure the QuadSPI clock. 989 * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. 990 * This parameter can be one of the following values: 991 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 992 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 993 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 994 * @retval None 995 */ 996 #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ 997 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) 998 999 /** @brief Macro to get the QuadSPI clock source. 1000 * @retval The clock source can be one of the following values: 1001 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 1002 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 1003 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 1004 */ 1005 #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) 1006 1007 #endif /* QUADSPI */ 1008 1009 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1010 * @brief macros to manage the specified RCC Flags and interrupts. 1011 * @{ 1012 */ 1013 1014 /** 1015 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 1016 * @retval None 1017 */ 1018 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1019 1020 /** 1021 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 1022 * @retval None 1023 */ 1024 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1025 1026 /** 1027 * @brief Enable the RCC LSE CSS Event Line. 1028 * @retval None. 1029 */ 1030 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1031 1032 /** 1033 * @brief Disable the RCC LSE CSS Event Line. 1034 * @retval None. 1035 */ 1036 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1037 1038 1039 /** 1040 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1041 * @retval None. 1042 */ 1043 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1044 1045 1046 /** 1047 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1048 * @retval None. 1049 */ 1050 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1051 1052 1053 /** 1054 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1055 * @retval None. 1056 */ 1057 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1058 1059 /** 1060 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1061 * @retval None. 1062 */ 1063 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1064 1065 /** 1066 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1067 * @retval None. 1068 */ 1069 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1070 do { \ 1071 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1072 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1073 } while(0) 1074 1075 /** 1076 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1077 * @retval None. 1078 */ 1079 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1080 do { \ 1081 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1082 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1083 } while(0) 1084 1085 /** 1086 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1087 * @retval EXTI RCC LSE CSS Line Status. 1088 */ 1089 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 1090 1091 /** 1092 * @brief Clear the RCC LSE CSS EXTI flag. 1093 * @retval None. 1094 */ 1095 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 1096 1097 /** 1098 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1099 * @retval None. 1100 */ 1101 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 1102 1103 1104 /** 1105 * @brief Enable the specified CRS interrupts. 1106 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1107 * This parameter can be any combination of the following values: 1108 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1109 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1110 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1111 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1112 * @retval None 1113 */ 1114 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1115 1116 /** 1117 * @brief Disable the specified CRS interrupts. 1118 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1119 * This parameter can be any combination of the following values: 1120 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1121 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1122 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1123 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1124 * @retval None 1125 */ 1126 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1127 1128 /** @brief Check whether the CRS interrupt has occurred or not. 1129 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1130 * This parameter can be one of the following values: 1131 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1132 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1133 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1134 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1135 * @retval The new state of __INTERRUPT__ (SET or RESET). 1136 */ 1137 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 1138 1139 /** @brief Clear the CRS interrupt pending bits 1140 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1141 * This parameter can be any combination of the following values: 1142 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1143 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1144 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1145 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1146 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1147 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1148 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1149 */ 1150 /* CRS IT Error Mask */ 1151 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 1152 1153 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1154 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1155 { \ 1156 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1157 } \ 1158 else \ 1159 { \ 1160 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1161 } \ 1162 } while(0) 1163 1164 /** 1165 * @brief Check whether the specified CRS flag is set or not. 1166 * @param __FLAG__ specifies the flag to check. 1167 * This parameter can be one of the following values: 1168 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1169 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1170 * @arg @ref RCC_CRS_FLAG_ERR Error 1171 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1172 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1173 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1174 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1175 * @retval The new state of _FLAG_ (TRUE or FALSE). 1176 */ 1177 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1178 1179 /** 1180 * @brief Clear the CRS specified FLAG. 1181 * @param __FLAG__ specifies the flag to clear. 1182 * This parameter can be one of the following values: 1183 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1184 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1185 * @arg @ref RCC_CRS_FLAG_ERR Error 1186 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1187 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1188 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1189 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1190 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1191 * @retval None 1192 */ 1193 1194 /* CRS Flag Error Mask */ 1195 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 1196 1197 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1198 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1199 { \ 1200 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1201 } \ 1202 else \ 1203 { \ 1204 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1205 } \ 1206 } while(0) 1207 1208 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1214 * @{ 1215 */ 1216 /** 1217 * @brief Enable the oscillator clock for frequency error counter. 1218 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1219 * @retval None 1220 */ 1221 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1222 1223 /** 1224 * @brief Disable the oscillator clock for frequency error counter. 1225 * @retval None 1226 */ 1227 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1228 1229 /** 1230 * @brief Enable the automatic hardware adjustment of TRIM bits. 1231 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1232 * @retval None 1233 */ 1234 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1235 1236 /** 1237 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1238 * @retval None 1239 */ 1240 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1241 1242 /** 1243 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1244 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1245 * of the synchronization source after prescaling. It is then decreased by one in order to 1246 * reach the expected synchronization on the zero value. The formula is the following: 1247 * RELOAD = (fTARGET / fSYNC) -1 1248 * @param __FTARGET__ Target frequency (value in Hz) 1249 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1250 * @retval None 1251 */ 1252 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1253 1254 /** 1255 * @} 1256 */ 1257 1258 /** 1259 * @} 1260 */ 1261 1262 /* Exported functions --------------------------------------------------------*/ 1263 /** @addtogroup RCCEx_Exported_Functions 1264 * @{ 1265 */ 1266 1267 /** @addtogroup RCCEx_Exported_Functions_Group1 1268 * @{ 1269 */ 1270 1271 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1272 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1273 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1274 1275 /** 1276 * @} 1277 */ 1278 1279 /** @addtogroup RCCEx_Exported_Functions_Group2 1280 * @{ 1281 */ 1282 1283 void HAL_RCCEx_EnableLSECSS(void); 1284 void HAL_RCCEx_DisableLSECSS(void); 1285 void HAL_RCCEx_EnableLSECSS_IT(void); 1286 void HAL_RCCEx_LSECSS_IRQHandler(void); 1287 void HAL_RCCEx_LSECSS_Callback(void); 1288 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1289 void HAL_RCCEx_DisableLSCO(void); 1290 1291 /** 1292 * @} 1293 */ 1294 1295 /** @addtogroup RCCEx_Exported_Functions_Group3 1296 * @{ 1297 */ 1298 1299 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1300 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1301 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1302 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1303 void HAL_RCCEx_CRS_IRQHandler(void); 1304 void HAL_RCCEx_CRS_SyncOkCallback(void); 1305 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1306 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1307 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1308 1309 /** 1310 * @} 1311 */ 1312 1313 /** 1314 * @} 1315 */ 1316 1317 /* Private macros ------------------------------------------------------------*/ 1318 /** @addtogroup RCCEx_Private_Macros 1319 * @{ 1320 */ 1321 1322 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1323 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1324 1325 #if defined(STM32G474xx) || defined(STM32G484xx) 1326 1327 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1328 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1329 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1330 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1331 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1332 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1333 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1334 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1335 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1336 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1337 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1338 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1339 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1340 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1341 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1342 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1343 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1344 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1345 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1346 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1347 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1348 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 1349 1350 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1351 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1352 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1353 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1354 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1355 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1356 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1357 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1358 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1359 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1360 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1361 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1362 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1363 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1364 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1365 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1366 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1367 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1368 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1369 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1370 #elif defined(STM32G473xx) || defined(STM32G483xx) 1371 1372 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1373 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1374 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1375 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1376 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1377 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1378 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1379 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1380 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1381 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1382 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1383 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1384 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1385 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1386 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1387 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1388 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1389 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1390 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1391 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1392 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1393 1394 #elif defined(STM32G471xx) 1395 1396 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1397 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1398 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1399 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1400 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1401 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1402 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1403 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1404 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1405 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1406 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1407 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1408 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1409 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1410 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1411 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1412 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1413 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1414 1415 #elif defined(STM32G431xx) || defined(STM32G441xx) 1416 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1417 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1418 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1419 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1420 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1421 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1422 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1423 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1424 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1425 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1426 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1427 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1428 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1429 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1430 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1431 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1432 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1433 1434 #elif defined(STM32G411xB) || defined(STM32G411xC) 1435 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1436 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1437 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1438 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1439 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1440 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1441 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1442 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1443 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1444 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1445 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1446 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1447 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1448 #elif defined(STM32G414xx) 1449 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1450 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1451 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1452 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1453 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1454 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1455 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1456 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1457 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1458 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1459 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1460 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1461 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1462 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1463 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1464 #elif defined(STM32GBK1CB) 1465 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1466 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1467 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1468 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1469 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1470 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1471 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1472 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1473 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1474 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1475 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1476 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1477 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1478 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1479 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1480 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1481 1482 #endif /* STM32G474xx || STM32G484xx */ 1483 1484 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1485 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1486 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1487 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1488 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1489 1490 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1491 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1492 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1493 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1494 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1495 1496 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1497 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1498 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1499 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1500 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1501 1502 #if defined(UART4) 1503 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 1504 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 1505 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 1506 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 1507 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 1508 #endif /* UART4 */ 1509 1510 #if defined(UART5) 1511 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 1512 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 1513 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 1514 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 1515 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 1516 1517 #endif /* UART5 */ 1518 1519 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1520 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 1521 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 1522 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 1523 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 1524 1525 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 1526 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 1527 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 1528 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 1529 1530 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 1531 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 1532 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 1533 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 1534 1535 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 1536 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 1537 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 1538 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 1539 1540 #if defined(I2C4) 1541 1542 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 1543 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 1544 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 1545 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 1546 1547 #endif /* I2C4 */ 1548 1549 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1550 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 1551 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1552 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 1553 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 1554 1555 #if defined(SAI1) 1556 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 1557 (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ 1558 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 1559 ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ 1560 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 1561 #endif /* SAI1 */ 1562 1563 #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ 1564 (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ 1565 ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ 1566 ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ 1567 ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) 1568 1569 #if defined(FDCAN1) 1570 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 1571 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 1572 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 1573 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) 1574 1575 #endif /* FDCAN1 */ 1576 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1577 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 1578 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) 1579 1580 #if defined(USB) 1581 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1582 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 1583 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 1584 1585 #endif /* USB */ 1586 1587 #define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ 1588 (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ 1589 ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ 1590 ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) 1591 1592 #if defined(ADC345_COMMON) 1593 #define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ 1594 (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ 1595 ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ 1596 ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) 1597 #endif /* ADC345_COMMON */ 1598 1599 #if defined(QUADSPI) 1600 1601 #define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ 1602 (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ 1603 ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ 1604 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) 1605 1606 #endif /* QUADSPI */ 1607 1608 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 1609 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1610 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 1611 1612 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1613 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1614 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1615 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1616 1617 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1618 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1619 1620 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 1621 1622 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 1623 1624 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 1625 1626 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1627 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1628 1629 /** 1630 * @} 1631 */ 1632 1633 /** 1634 * @} 1635 */ 1636 1637 /** 1638 * @} 1639 */ 1640 1641 #ifdef __cplusplus 1642 } 1643 #endif 1644 1645 #endif /* STM32G4xx_HAL_RCC_EX_H */ 1646 1647
