1 /* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_ 8 #define SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_ 9 10 #include <soc_nrf_common.h> 11 12 #if defined(CONFIG_SOC_NRF54H20_CPUAPP) 13 #define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM1_Pos 14 #define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM2_Pos 15 #define RAMBLOCK_POWER_ID 0 16 #define RAMBLOCK_CONTROL_OFF 0 17 #define RAMBLOCK_RET_MASK (MEMCONF_POWER_RET_MEM0_Msk) 18 #define RAMBLOCK_RET_BIT_ICACHE MEMCONF_POWER_RET_MEM1_Pos 19 #define RAMBLOCK_RET_BIT_DCACHE MEMCONF_POWER_RET_MEM2_Pos 20 #elif defined(CONFIG_SOC_NRF54H20_CPURAD) 21 #define RAMBLOCK_CONTROL_BIT_ICACHE MEMCONF_POWER_CONTROL_MEM6_Pos 22 #define RAMBLOCK_CONTROL_BIT_DCACHE MEMCONF_POWER_CONTROL_MEM7_Pos 23 #define RAMBLOCK_POWER_ID 0 24 #define RAMBLOCK_CONTROL_OFF 0 25 #define RAMBLOCK_RET_MASK \ 26 (MEMCONF_POWER_RET_MEM0_Msk | MEMCONF_POWER_RET_MEM1_Msk | MEMCONF_POWER_RET_MEM2_Msk | \ 27 MEMCONF_POWER_RET_MEM3_Msk | MEMCONF_POWER_RET_MEM4_Msk | MEMCONF_POWER_RET_MEM5_Msk | \ 28 MEMCONF_POWER_RET_MEM8_Msk) 29 #define RAMBLOCK_RET2_MASK \ 30 (MEMCONF_POWER_RET2_MEM0_Msk | MEMCONF_POWER_RET2_MEM1_Msk | MEMCONF_POWER_RET2_MEM2_Msk | \ 31 MEMCONF_POWER_RET2_MEM3_Msk | MEMCONF_POWER_RET2_MEM4_Msk | MEMCONF_POWER_RET2_MEM5_Msk | \ 32 MEMCONF_POWER_RET2_MEM8_Msk) 33 #define RAMBLOCK_RET_BIT_ICACHE MEMCONF_POWER_RET_MEM6_Pos 34 #define RAMBLOCK_RET_BIT_DCACHE MEMCONF_POWER_RET_MEM7_Pos 35 #define RAMBLOCK_RET2_BIT_ICACHE MEMCONF_POWER_RET2_MEM6_Pos 36 #define RAMBLOCK_RET2_BIT_DCACHE MEMCONF_POWER_RET2_MEM7_Pos 37 #endif 38 39 #endif /* SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_ */ 40
