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Searched defs:RAM2_CTL0 (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h72 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ member
Dcyip_cpuss_v2.h90 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h100 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1122 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ member