1 /***************************************************************************//** 2 * @file 3 * @brief This file contains the type definitions for EFR32xG2x chip-specific 4 * aspects of RAIL. 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #ifdef SLI_LIBRARY_BUILD 33 34 // This file should not be included when doing SLI_LIBRARY_BUILDs 35 36 #else//!SLI_LIBRARY_BUILD 37 38 #ifndef __RAIL_CHIP_SPECIFIC_H_ 39 #if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS) 40 #warning rail_chip_specific.h should only be included by rail_types.h 41 #include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h 42 #else // __RAIL_TYPES_H__ 43 /// Include guard 44 #define __RAIL_CHIP_SPECIFIC_H_ 45 #include "sl_status.h" 46 #include "rail_features.h" 47 #ifdef RAIL_INTERNAL_BUILD 48 #include "rail_chip_specific_internal.h" 49 #endif 50 51 #ifdef __cplusplus 52 extern "C" { 53 #endif 54 55 /****************************************************************************** 56 * General Structures 57 *****************************************************************************/ 58 /** 59 * @addtogroup General_EFR32XG2X EFR32xG2x 60 * @ingroup General 61 * @{ 62 * @brief Types specific to the EFR32xG2x for general configuration. 63 */ 64 65 #ifndef DOXYGEN_SHOULD_SKIP_THIS 66 67 /** 68 * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES 69 * @brief The EFR32xG21 series size needed for 70 * \ref RAIL_StateBufferEntry_t::bufferBytes. 71 */ 72 #define RAIL_EFR32XG21_STATE_BUFFER_BYTES 592 73 74 /** 75 * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES 76 * @brief The EFR32xG22 series size needed for 77 * \ref RAIL_StateBufferEntry_t::bufferBytes. 78 */ 79 #define RAIL_EFR32XG22_STATE_BUFFER_BYTES 608 80 81 /** 82 * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES 83 * @brief The EFR32xG23 series size needed for 84 * \ref RAIL_StateBufferEntry_t::bufferBytes. 85 */ 86 #define RAIL_EFR32XG23_STATE_BUFFER_BYTES 616 87 88 /** 89 * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES 90 * @brief The EFR32xG24 series size needed for 91 * \ref RAIL_StateBufferEntry_t::bufferBytes. 92 */ 93 #define RAIL_EFR32XG24_STATE_BUFFER_BYTES 632 94 95 /** 96 * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES 97 * @brief The EFR32xG25 series size needed for 98 * \ref RAIL_StateBufferEntry_t::bufferBytes. 99 */ 100 #define RAIL_EFR32XG25_STATE_BUFFER_BYTES 624 101 102 /** 103 * @def RAIL_EFR32XG26_STATE_BUFFER_BYTES 104 * @brief The EFR32xG26 series size needed for 105 * \ref RAIL_StateBufferEntry_t::bufferBytes. 106 */ 107 #define RAIL_EFR32XG26_STATE_BUFFER_BYTES 632 108 109 /** 110 * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES 111 * @brief The EFR32xG27 series size needed for 112 * \ref RAIL_StateBufferEntry_t::bufferBytes. 113 */ 114 #define RAIL_EFR32XG27_STATE_BUFFER_BYTES 608 115 116 /** 117 * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES 118 * @brief The EFR32xG28 series size needed for 119 * \ref RAIL_StateBufferEntry_t::bufferBytes. 120 */ 121 #define RAIL_EFR32XG28_STATE_BUFFER_BYTES 624 122 123 /** 124 * @def RAIL_EFR32XG29_STATE_BUFFER_BYTES 125 * @brief The EFR32XG29 series size needed for 126 * \ref RAIL_StateBufferEntry_t::bufferBytes. 127 */ 128 #define RAIL_EFR32XG29_STATE_BUFFER_BYTES 608 129 130 #ifndef RAIL_STATE_BUFFER_BYTES 131 /** 132 * @def RAIL_STATE_BUFFER_BYTES 133 * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes 134 * on this platform for this radio. This compile-time size may be slightly 135 * larger than what \ref RAIL_GetStateBufferSize() determines at run-time. 136 */ 137 #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) 138 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES 139 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) 140 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES 141 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) 142 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES 143 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) 144 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES 145 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) 146 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES 147 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) 148 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG26_STATE_BUFFER_BYTES 149 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) 150 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES 151 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) 152 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES 153 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) 154 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG29_STATE_BUFFER_BYTES 155 #else 156 #define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen 157 #error "Unsupported platform!" 158 #endif 159 #endif //#ifndef RAIL_STATE_BUFFER_BYTES 160 161 #endif//DOXYGEN_SHOULD_SKIP_THIS 162 163 #ifndef DOXYGEN_SHOULD_SKIP_THIS 164 165 /** 166 * @def RAIL_SEQ_IMAGE_1 167 * @brief A macro for the first sequencer image. 168 */ 169 #define RAIL_SEQ_IMAGE_1 1 170 171 /** 172 * @def RAIL_SEQ_IMAGE_2 173 * @brief A macro for the second sequencer image. 174 */ 175 #define RAIL_SEQ_IMAGE_2 2 176 177 #ifndef RAIL_INTERNAL_BUILD 178 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) 179 /** 180 * @def RAIL_SEQ_IMAGE_PA_10_DBM 181 * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs 182 * with a 10 dBm PA. 183 */ 184 #define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1 185 186 /** 187 * @def RAIL_SEQ_IMAGE_PA_20_DBM 188 * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs 189 * with a 20 dBm PA. 190 */ 191 #define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2 192 193 /** 194 * @def RAIL_SEQ_IMAGE_COUNT 195 * @brief A macro for the total number of sequencer images supported on the 196 * platform. 197 */ 198 #define RAIL_SEQ_IMAGE_COUNT 2 199 200 #else //((_SILICON_LABS_32B_SERIES_2_CONFIG != 4) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 6)) 201 202 /** 203 * @def RAIL_SEQ_IMAGE_DEFAULT 204 * @brief A chip-specific macro for the default sequencer image on platforms 205 * that support only one sequencer image. 206 */ 207 #define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1 208 209 /** 210 * @def RAIL_SEQ_IMAGE_COUNT 211 * @brief A macro for the total number of sequencer images supported on the 212 * platform. 213 */ 214 #define RAIL_SEQ_IMAGE_COUNT 1 215 #endif //((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) 216 #endif //RAIL_INTERNAL_BUILD 217 218 /** 219 * @struct RAIL_RffpllConfig_t 220 * @brief Stores information relevant to the Radio-Friendly Frequency 221 * Phase-Locked Loop (RFFPLL) for the PHY configuration currently loaded in 222 * memory. 223 */ 224 typedef struct { 225 /** Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values. */ 226 uint32_t dividers; 227 /** Radio clock frequency in Hz. */ 228 uint32_t radioFreqHz; 229 /** System clock frequency in Hz. */ 230 uint32_t sysclkFreqHz; 231 } RAIL_RffpllConfig_t; 232 233 /** 234 * @def RAIL_RFFPLL_DIVIDERX_MASK 235 * @brief Bit mask for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. 236 */ 237 #define RAIL_RFFPLL_DIVIDERX_MASK 0x000000FFUL 238 239 /** 240 * @def RAIL_RFFPLL_DIVIDERX_SHIFT 241 * @brief Shift value for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. 242 */ 243 #define RAIL_RFFPLL_DIVIDERX_SHIFT 0 244 245 /** 246 * @def RAIL_RFFPLL_DIVIDERY_MASK 247 * @brief Bit mask for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. 248 */ 249 #define RAIL_RFFPLL_DIVIDERY_MASK 0x0000FF00UL 250 251 /** 252 * @def RAIL_RFFPLL_DIVIDERY_SHIFT 253 * @brief Shift value for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. 254 */ 255 #define RAIL_RFFPLL_DIVIDERY_SHIFT 8 256 257 /** 258 * @def RAIL_RFFPLL_DIVIDERN_MASK 259 * @brief Bit mask for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. 260 */ 261 #define RAIL_RFFPLL_DIVIDERN_MASK 0x00FF0000UL 262 263 /** 264 * @def RAIL_RFFPLL_DIVIDERN_SHIFT 265 * @brief Shift value for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. 266 */ 267 #define RAIL_RFFPLL_DIVIDERN_SHIFT 16 268 269 /** 270 * @typedef RAIL_TimerTick_t 271 * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. 272 * A tick is roughly 0.5 microseconds but it wraps somewhat before 273 * 0xFFFFFFFF giving a time range of about 17 minutes. 274 * 275 * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between 276 * two \ref RAIL_TimerTick_t values to microseconds. 277 */ 278 typedef uint32_t RAIL_TimerTick_t; 279 280 /** 281 * @def RAIL_GetTimerTick(timerTickType) 282 * @brief The RAIL hardware timer ticks value. 283 * 284 * @note timerTickType is added for compatibility reasons and is ignored here; 285 * this gets the equivalent of \ref RAIL_TIMER_TICK_DEFAULT. 286 */ 287 #define RAIL_GetTimerTick(timerTickType) (*RAIL_TimerTick) 288 289 /** 290 * A global pointer to the memory address of the 32-bit 291 * \ref RAIL_TimerTick_t internal RAIL hardware timer that drives 292 * the RAIL timebase. 293 * Equivalent to \ref RAIL_TimerTick_t for its granularity and range. 294 */ 295 extern const volatile uint32_t *RAIL_TimerTick; 296 297 /** 298 * A global pointer to the memory address of the internal RAIL hardware timer 299 * that captures the latest RX packet reception time. 300 * See \ref RAIL_TimerTick_t for its granularity and range. 301 * 302 * @note This would not include the RX chain delay, so may not exactly 303 * correspond to the \ref RAIL_Time_t packet timestamp available within 304 * \ref RAIL_RxPacketDetails_t::timeReceived which reflects the actual 305 * on-air time that the packet finished. 306 */ 307 extern const volatile uint32_t *RAIL_RxPacketTimestamp; 308 309 /** 310 * Get elapsed time, in microseconds, between two \ref RAIL_TimerTick_t ticks. 311 * 312 * @param[in] startTick Tick recorded at the start of the operation. 313 * @param[in] endTick Tick recorded at the end of the operation. 314 * @return The elapsed time, in microseconds, between two timer ticks. 315 */ 316 RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, 317 RAIL_TimerTick_t endTick); 318 319 /** 320 * Get \ref RAIL_TimerTick_t tick corresponding to a \ref RAIL_Time_t time. 321 * 322 * @param[in] microseconds Time in microseconds. 323 * @return The \ref RAIL_TimerTick_t tick corresponding to the 324 * \ref RAIL_Time_t time. 325 */ 326 RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); 327 328 #endif//DOXYGEN_SHOULD_SKIP_THIS 329 330 /** @} */ // end of group General_EFR32XG2X 331 332 /****************************************************************************** 333 * Multiprotocol 334 *****************************************************************************/ 335 /** 336 * @addtogroup Multiprotocol_EFR32XG2X EFR32xG2x 337 * @ingroup Multiprotocol 338 * @{ 339 * @brief EFR32xG2x-specific multiprotocol support defines. 340 */ 341 342 /** 343 * @def TRANSITION_TIME_US 344 * @brief Time it takes to take care of protocol switching. 345 */ 346 #if _SILICON_LABS_32B_SERIES_2_CONFIG > 1 347 // XG22 + devices 348 #define TRANSITION_TIME_US 510 349 #else 350 // XG21 351 #define TRANSITION_TIME_US 500 352 #endif 353 354 /** @} */ // end of group Multiprotocol_EFR32XG2X 355 356 /****************************************************************************** 357 * Calibration 358 *****************************************************************************/ 359 /** 360 * @addtogroup Calibration_EFR32XG2X EFR32xG2x 361 * @ingroup Calibration 362 * @{ 363 * @brief EFR32xG2x-specific Calibrations. 364 */ 365 366 /** 367 * @def RAIL_RF_PATHS_2P4GIG 368 * @brief Indicates the number of 2.4 GHz RF Paths suppported. 369 */ 370 #ifndef RAIL_RF_PATHS_2P4GIG 371 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) 372 #define RAIL_RF_PATHS_2P4GIG 2 373 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ 374 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ 375 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \ 376 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) 377 #define RAIL_RF_PATHS_2P4GIG 1 378 #else 379 #define RAIL_RF_PATHS_2P4GIG 0 380 #endif 381 #endif//RAIL_RF_PATHS_2P4GHZ 382 383 /** 384 * @def RAIL_RF_PATHS_SUBGIG 385 * @brief Indicates the number of Sub-GHz RF Paths supported. 386 */ 387 #ifndef RAIL_RF_PATHS_SUBGHZ 388 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 389 #define RAIL_RF_PATHS_SUBGIG 2 390 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 391 #define RAIL_RF_PATHS_SUBGIG 2 392 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 393 #define RAIL_RF_PATHS_SUBGIG 1 394 #else 395 #define RAIL_RF_PATHS_SUBGIG 0 396 #endif 397 #endif//RAIL_RF_PATHS_SUBGHZ 398 399 /** 400 * @def RAIL_RF_PATHS 401 * @brief Indicates the number of RF Paths supported. 402 */ 403 #define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG) 404 405 #if (RAIL_RF_PATHS > RAIL_MAX_RF_PATHS) 406 #error "Update rail_types.h RAIL_MAX_RF_PATHS" 407 #endif 408 409 /** 410 * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 411 * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths 412 * Needed for backwards compatibility. 413 */ 414 #if RAIL_RF_PATHS > 1 415 #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1 416 #else 417 #ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen 418 #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 419 #endif //DOXYGEN_SHOULD_SKIP_THIS 420 #endif //RAIL_RF_PATHS 421 422 /** 423 * @struct RAIL_ChannelConfigEntryAttr 424 * @brief A channel configuration entry attribute structure. Items listed 425 * are designed to be altered and updated during run-time. 426 */ 427 struct RAIL_ChannelConfigEntryAttr { 428 /** IR calibration attributes specific to each channel configuration entry. */ 429 #if RAIL_SUPPORTS_OFDM_PA 430 RAIL_IrCalValues_t calValues; 431 #else//!RAIL_SUPPORTS_OFDM_PA 432 RAIL_RxIrCalValues_t calValues; 433 #endif//RAIL_SUPPORTS_OFDM_PA 434 }; 435 436 /** @} */ // end of group Calibration_EFR32XG2X 437 438 /****************************************************************************** 439 * Transmit 440 *****************************************************************************/ 441 /** 442 * @addtogroup PA_EFR32XG2X EFR32xG2x 443 * @ingroup PA 444 * @{ 445 * @brief Types specific to the EFR32xG2x for dealing with the on-chip PAs. 446 */ 447 448 #ifndef RAIL_TX_POWER_LEVEL_2P4_HP_MAX 449 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 450 /** 451 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 452 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 453 */ 454 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) 455 /** 456 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 457 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 458 */ 459 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) 460 /** 461 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 462 * RAIL_TX_POWER_MODE_2P4GIG_MP mode. 463 */ 464 #define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (90U) 465 /** 466 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 467 * RAIL_TX_POWER_MODE_2P4GIG_MP mode. 468 */ 469 #define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (1U) 470 /** 471 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 472 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 473 */ 474 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (64U) 475 /** 476 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 477 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 478 */ 479 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) 480 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) 481 /** 482 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 483 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 484 * EFR32xG24: capable of 20dBm max output power has max powerlevel:180 485 * EFR32xG24: capable of 10dBm max output power has max powerlevel:90 486 * EFR32xG26: capable of 20dBm max output power has max powerlevel:180 487 * EFR32xG26: capable of 10dBm max output power has max powerlevel:90 488 */ 489 #if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ 490 && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) 491 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) 492 #else 493 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (90U) 494 #endif 495 /** 496 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 497 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 498 */ 499 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) 500 /** 501 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 502 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 503 */ 504 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) 505 /** 506 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 507 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 508 */ 509 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) 510 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ 511 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ 512 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) 513 /** 514 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 515 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 516 */ 517 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (127U) 518 /** 519 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 520 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 521 */ 522 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) 523 /** 524 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 525 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 526 */ 527 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) 528 /** 529 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 530 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 531 */ 532 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) 533 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 534 /** 535 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 536 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 537 */ 538 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) 539 /** 540 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 541 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 542 */ 543 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) 544 #else //EFR32xG23 545 /** 546 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 547 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 548 */ 549 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) 550 /** 551 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 552 * RAIL_TX_POWER_MODE_2P4GIG_HP mode. 553 */ 554 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) 555 /** 556 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 557 * RAIL_TX_POWER_MODE_2P4GIG_MP mode. 558 */ 559 #define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) 560 /** 561 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 562 * RAIL_TX_POWER_MODE_2P4GIG_MP mode. 563 */ 564 #define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) 565 /** 566 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 567 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 568 */ 569 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) 570 /** 571 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 572 * RAIL_TX_POWER_MODE_2P4GIG_LP mode. 573 */ 574 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) 575 /** 576 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 577 * RAIL_TX_POWER_MODE_2P4GIG_LLP mode. 578 */ 579 #define RAIL_TX_POWER_LEVEL_2P4_LLP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) 580 /** 581 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 582 * RAIL_TX_POWER_MODE_2P4GIG_LLP mode. 583 */ 584 #define RAIL_TX_POWER_LEVEL_2P4_LLP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) 585 #endif //_SILICON_LABS_32B_SERIES_2_CONFIG 586 #endif //RAIL_TX_POWER_LEVEL_2P4_HP_MAX 587 588 #if RAIL_SUPPORTS_SUBGHZ_BAND 589 /** 590 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when using 591 * a Sub-GHz PA mode. 592 */ 593 #ifndef RAIL_SUBGIG_MAX 594 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8 595 #define RAIL_SUBGIG_MAX 240U 596 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 597 #define RAIL_SUBGIG_MAX 79U 598 #else 599 #define RAIL_SUBGIG_MAX 0U 600 #endif 601 #endif//RAIL_SUBGIG_MAX 602 603 /** 604 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when using 605 * a Sub-GHz PA mode. 606 */ 607 #define RAIL_SUBGIG_MIN 1U 608 609 /** 610 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 611 * RAIL_TX_POWER_MODE_SUBGIG_HP mode. 612 */ 613 #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX) 614 615 /** 616 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 617 * RAIL_TX_POWER_MODE_SUBGIG_HP mode. 618 */ 619 #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN) 620 621 /** 622 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 623 * RAIL_TX_POWER_MODE_SUBGIG_MP mode. 624 */ 625 #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX) 626 627 /** 628 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 629 * RAIL_TX_POWER_MODE_SUBGIG_MP mode. 630 */ 631 #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN) 632 633 /** 634 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 635 * RAIL_TX_POWER_MODE_SUBGIG_LP mode. 636 */ 637 #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX) 638 639 /** 640 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 641 * RAIL_TX_POWER_MODE_SUBGIG_LP mode. 642 */ 643 #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN) 644 645 /** 646 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 647 * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. 648 */ 649 #define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX) 650 651 /** 652 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 653 * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. 654 */ 655 #define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (RAIL_SUBGIG_MIN) 656 #endif //RAIL_SUPPORTS_SUBGHZ_BAND 657 658 #if RAIL_SUPPORTS_OFDM_PA 659 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 5 660 #define RAIL_OFDM_PA_MAX 204U 661 #define RAIL_OFDM_PA_MULT 5U 662 #define RAIL_OFDM_PA_MIN 0U 663 #endif 664 665 /** 666 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 667 * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode. 668 */ 669 #define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX) 670 671 /** 672 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref 673 * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode. 674 */ 675 #define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN) 676 #endif //RAIL_SUPPORTS_OFDM_PA 677 678 /** Backwards compatability define */ 679 #define RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX 680 /** Backwards compatability define */ 681 #define RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN 682 /** Backwards compatability define */ 683 #define RAIL_TX_POWER_LEVEL_MP_MAX RAIL_TX_POWER_LEVEL_2P4_MP_MAX 684 /** Backwards compatability define */ 685 #define RAIL_TX_POWER_LEVEL_MP_MIN RAIL_TX_POWER_LEVEL_2P4_MP_MIN 686 /** Backwards compatability define */ 687 #define RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX 688 /** Backwards compatability define */ 689 #define RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN 690 /** Backwards compatability define */ 691 #define RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX 692 /** Backwards compatability define */ 693 #define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN 694 695 /** 696 * The number of PA's on this chip (including Virtual PAs). 697 */ 698 #ifndef RAIL_NUM_PA 699 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ 700 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ 701 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ 702 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ 703 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) 704 #define RAIL_NUM_PA (2U) 705 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) 706 #define RAIL_NUM_PA (4U) 707 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) 708 #define RAIL_NUM_PA (5U) 709 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) 710 #define RAIL_NUM_PA (4U) 711 #else 712 #define RAIL_NUM_PA (3U) 713 #endif 714 #endif //#ifndef RAIL_NUM_PA 715 716 #ifndef DOXYGEN_SHOULD_SKIP_THIS 717 // Self-referencing defines minimize compiler complaints when using RAIL_ENUM 718 // Only those supported per-platform are defined, for use with #ifdef in 719 // apps or librail code. 720 #if RAIL_SUPPORTS_2P4GHZ_BAND 721 #define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP) 722 #define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP) 723 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 724 #define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP) 725 #define RAIL_TX_POWER_MODE_2P4_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_MP) 726 #endif//_SILICON_LABS_32B_SERIES_2_CONFIG == 1 727 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) 728 #define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP) 729 #define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP) 730 #endif//((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) 731 #define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) 732 #define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST) 733 #endif//RAIL_SUPPORTS_2P4GHZ_BAND 734 735 #if RAIL_SUPPORTS_SUBGHZ_BAND 736 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 737 #define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) 738 #else//!RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 739 #define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP) 740 #define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG) 741 #define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP) 742 #define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP) 743 #define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP) 744 #endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 745 #define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST) 746 #endif//RAIL_SUPPORTS_SUBGHZ_BAND 747 #if RAIL_SUPPORTS_OFDM_PA 748 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 749 #define RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) 750 #define RAIL_TX_POWER_MODE_OFDM_PA ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA) 751 #endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 752 #endif//RAIL_SUPPORTS_OFDM_PA 753 #endif//DOXYGEN_SHOULD_SKIP_THIS 754 755 /** Convenience macro for any mapping table mode. */ 756 #define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ 757 (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ 758 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) 759 760 /** Convenience macro to check if the power mode supports raw setting. */ 761 #define RAIL_POWER_MODE_SUPPORTS_RAW_SETTING(x) \ 762 (((x) != RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ 763 && ((x) != RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) 764 /** @} */ // end of group PA_EFR32XG2X 765 766 /****************************************************************************** 767 * RX Channel Hopping 768 *****************************************************************************/ 769 /** 770 * @addtogroup Rx_Channel_Hopping_EFR32XG2X EFR32xG2x 771 * @ingroup Rx_Channel_Hopping 772 * @{ 773 * @brief EFR32xG2x-specific RX channel hopping. 774 */ 775 776 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8 777 /// The static amount of memory needed per channel for channel hopping, measured 778 /// in 32 bit words, regardless of the size of radio configuration structures. 779 #define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (65U) 780 #else 781 /// The static amount of memory needed per channel for channel hopping, measured 782 /// in 32 bit words, regardless of the size of radio configuration structures. 783 #define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (56U) 784 #endif 785 786 #if (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ 787 > RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE) 788 #error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE" 789 #endif 790 791 /** @} */ // end of group Rx_Channel_Hopping_EFR32XG2X 792 793 /****************************************************************************** 794 * Sleep Structures 795 *****************************************************************************/ 796 /** 797 * @addtogroup Sleep_EFR32XG2X EFR32xG2x 798 * @ingroup Sleep 799 * @{ 800 * @brief EFR32xG2x-specific Sleeping. 801 */ 802 803 /// Default PRS channel to use when configuring sleep 804 #define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) 805 806 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ 807 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ 808 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) 809 /// Default RTCC channel to use when configuring sleep 810 #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U) 811 #else 812 /// Default RTCC channel to use when configuring sleep 813 #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) 814 #endif 815 816 /** @} */ // end of group Sleep_EFR32XG2X 817 818 /****************************************************************************** 819 * State Transitions 820 *****************************************************************************/ 821 /** 822 * @addtogroup State_Transitions_EFR32XG2X EFR32xG2x 823 * @ingroup State_Transitions 824 * @{ 825 * @brief EFR32xG2x-specific State Transitions. 826 */ 827 828 /** 829 * @def RAIL_MINIMUM_TRANSITION_US 830 * @brief The minimum value for a consistent RAIL transition 831 * @note Transitions may need to be slower than this when using longer 832 * \ref RAIL_TxPowerConfig_t::rampTime values 833 */ 834 #define RAIL_MINIMUM_TRANSITION_US (100U) 835 836 /** 837 * @def RAIL_MAXIMUM_TRANSITION_US 838 * @brief The maximum value for a consistent RAIL transition 839 */ 840 #define RAIL_MAXIMUM_TRANSITION_US (1000000U) 841 842 /** 843 * Internal Radio State type mapping for EFR32 chips. 844 */ 845 typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; 846 847 /** @} */ // end of group State_Transitions_EFR32XG2X 848 849 #ifdef __cplusplus 850 } 851 #endif 852 853 #endif //__RAIL_TYPES_H__ 854 855 #endif //__RAIL_CHIP_SPECIFIC_H_ 856 857 #endif //SLI_LIBRARY_BUILD 858
