1 /*
2  * @brief IOH Architecture B mnemonics
3  *
4  * @note
5  * Copyright 2014, 2019, NXP
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products.  This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights.  NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers.  This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef _FSL_SMARTDMA_PRV_H_
33 #define _FSL_SMARTDMA_PRV_H_
34 
35 #include "fsl_common.h"
36 
37 #define SMARTDMA_INPUT_SOURCE_0 0
38 #define SMARTDMA_INPUT_SOURCE_1 1
39 #define SMARTDMA_INPUT_SOURCE_2 2
40 #define SMARTDMA_INPUT_SOURCE_3 3
41 #define SMARTDMA_INPUT_SOURCE_4 4
42 #define SMARTDMA_INPUT_SOURCE_5 5
43 #define SMARTDMA_INPUT_SOURCE_6 6
44 #define SMARTDMA_INPUT_SOURCE_7 7
45 
46 #define BS0(c) (c << 8)
47 #define BS1(c) (c << 11)
48 #define BS2(c) (c << 14)
49 #define BS3(c) (c << 17)
50 #define BS4(c) (c << 20)
51 #define BS5(c) (c << 23)
52 #define BS6(c) (c << 26)
53 #define BS7(c) (c << 29)
54 
55 #define SMARTDMA_DISABLE_EMERGENCY_BIT 8
56 
57 #define SMARTDMA_HANDSHAKE_EVENT  0
58 #define SMARTDMA_HANDSHAKE_ENABLE 1
59 
60 #define SMARTDMA_MASK_RESP       2
61 #define SMARTDMA_ENABLE_AHBBUF   3
62 #define SMARTDMA_ENABLE_GPISYNCH 4
63 
64 typedef enum
65 {
66     ezh_trap_low  = 1,
67     ezh_trap_high = 0
68 } trap_pol;
69 
70 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
71 /*                                      SMARTDMA ARCH B */
72 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
73 
74 #define R0  0x00
75 #define R1  0x01
76 #define R2  0x02
77 #define R3  0x03
78 #define R4  0x04
79 #define R5  0x05
80 #define R6  0x06
81 #define R7  0x07
82 #define GPO 0x08
83 #define GPD 0x09
84 #define CFS 0x0a
85 #define CFM 0x0b
86 #define SP  0x0c
87 #define PC  0x0d
88 #define GPI 0x0e
89 #define RA  0x0f
90 
91 /* Conditional Flags */
92 #define EU  0x0
93 #define ZE  0x1
94 #define NZ  0x2
95 #define PO  0x3
96 #define NE  0x4
97 #define AZ  0x5
98 #define ZB  0x6
99 #define CA  0x7
100 #define NC  0x8
101 #define CZ  0x9
102 #define SPO 0xa
103 #define SNE 0xb
104 #define NBS 0xc
105 #define NEX 0xd
106 #define BS  0xe
107 #define EX  0xf
108 
109 #define UNS 0xa
110 #define NZS 0xb
111 
112 #define VECT0 0x1
113 #define VECT1 0x2
114 #define VECT2 0x4
115 #define VECT3 0x8
116 #define VECT4 0x10
117 #define VECT5 0x20
118 #define VECT6 0x40
119 #define VECT7 0x80
120 
121 /* Bit Slice Mux cfg */
122 
123 #define BS_1      0
124 #define BS_RISE   1
125 #define BS_FALL   2
126 #define BS_CHANGE 3
127 #define BS_SIG    4
128 #define BS_SIGN   5
129 #define BS_0      6
130 #define BS_EVENT  7
131 
132 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
133 /*                                      Unconditional OpCodes */
134 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
135 
136 #define E_GOSUB(a30)       DCD 0x03 + a30
137 #define E_NOP              DCD 0x12
138 #define E_INT_TRIGGER(x24) DCD 0x14 + (x24 << 8)
139 
140 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
141 /*                                       E_GOTO */
142 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
143 /* the pre-processor/linker will calculate it this way (<< relative not allowed) */
144 #define E_GOTO(a21)                                                                                                 \
145     DCD 0x15 + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
146         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
147         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
148         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
149         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
150         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
151         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
152         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
153         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
154         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
155         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
156         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
157         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
158         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
159         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
160         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
161         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
162         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
163         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
164         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
165         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
166         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
167         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
168         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
169         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
170         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
171         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
172         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
173         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21
174 
175 #define E_GOTO_REG(raddr) DCD 0x15 + (raddr << 14)
176 
177 /* the pre-processor/linker will calculate it this way (<< relative not allowed) */
178 #define E_GOTOL(a21)                                                                                                \
179     DCD 0x15 + (1 << 10) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
180         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
181         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
182         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
183         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
184         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
185         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
186         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
187         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
188         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
189         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
190         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
191         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
192         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
193         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
194         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
195         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
196         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
197         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
198         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
199         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
200         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
201         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
202         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
203         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
204         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
205         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
206         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
207         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21
208 
209 #define E_GOTO_REGL(raddr) DCD 0x15 + (raddr << 14) + (1 << 10)
210 
211 #define E_COND_GOTO(cond, a21)                                                                                        \
212     DCD 0x15 + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
213         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
214         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
215         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
216         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
217         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
218         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
219         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
220         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
221         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
222         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
223         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
224         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
225         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
226         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
227         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
228         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
229         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
230         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
231         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
232         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
233         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
234         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
235         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
236         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
237         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
238         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
239         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
240         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21
241 
242 #define E_COND_GOTO_REG(cond, raddr) DCD 0x15 + (raddr << 14) + (cond << 5)
243 
244 /* the pre-processor/linker will calculate it this way (<< relative not allowed) */
245 #define E_COND_GOTOL(cond, a21)                                                                                       \
246     DCD 0x15 + (1 << 10) + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \
247         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
248         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
249         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
250         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
251         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
252         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
253         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
254         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
255         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
256         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
257         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
258         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
259         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
260         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
261         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
262         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
263         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
264         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
265         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
266         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
267         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
268         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
269         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
270         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
271         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
272         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
273         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 +   \
274         a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21
275 
276 #define E_COND_GOTO_REGL(cond, raddr) DCD 0x15 + (raddr << 14) + (1 << 10) + (cond << 5)
277 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
278 /*                                       E_MOV */
279 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
280 
281 #define E_MOV(dest, source)             DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5)
282 #define E_MOVS(dest, source)            DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5)
283 #define E_COND_MOV(cond, dest, source)  DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5)
284 #define E_COND_MOVS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5)
285 
286 /* Invert */
287 #define E_MVN(dest, source)             DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) + (1 << 31)
288 #define E_MVNS(dest, source)            DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5) + (1 << 31)
289 #define E_COND_MVN(cond, dest, source)  DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) + (1 << 31)
290 #define E_COND_MVNS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5) + (1 << 31)
291 
292 /* Load  Immediate */
293 #define E_LOAD_IMM(dest, imm11s)            DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5)
294 #define E_LOAD_IMMS(dest, imm11s)           DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5)
295 #define E_COND_LOAD_IMM(cond, dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5)
296 #define E_COND_LOAD_IMMS(cond, dest, imm11s) \
297     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5)
298 
299 /* Load Shifted Immediate */
300 #define E_LOAD_SIMM(dest, imm11s, sam)                                                                \
301     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \
302         (((sam & 0x10) >> 4) << 19)
303 #define E_LOAD_SIMMS(dest, imm11s, sam)                                                                          \
304     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \
305         (((sam & 0x10) >> 4) << 19)
306 #define E_COND_LOAD_SIMM(cond, dest, imm11s, sam)                                                       \
307     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \
308         (((sam & 0x10) >> 4) << 19)
309 #define E_COND_LOAD_SIMMS(cond, dest, imm11s, sam)                                                                 \
310     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \
311         (((sam & 0x10) >> 4) << 19)
312 
313 /* Load  Inverted Immediate */
314 #define E_LOAD_IMMN(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + (1 << 31)
315 #define E_LOAD_IMMNS(dest, imm11s) \
316     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + (1 << 31)
317 #define E_COND_LOAD_IMMN(cond, dest, imm11s) \
318     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + (1 << 31)
319 #define E_COND_LOAD_IMMNS(cond, dest, imm11s) \
320     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + (1 << 31)
321 
322 /* Load Shifted then inverted Immediate */
323 #define E_LOAD_SIMMN(dest, imm11s, sam)                                                               \
324     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \
325         (((sam & 0x10) >> 4) << 19) + (1 << 31)
326 #define E_LOAD_SIMMNS(dest, imm11s, sam)                                                                         \
327     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \
328         (((sam & 0x10) >> 4) << 19) + (1 << 31)
329 #define E_COND_LOAD_SIMMN(cond, dest, imm11s, sam)                                                      \
330     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \
331         (((sam & 0x10) >> 4) << 19) + (1 << 31)
332 #define E_COND_LOAD_SIMMNS(cond, dest, imm11s, sam)                                                                \
333     DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \
334         (((sam & 0x10) >> 4) << 19) + (1 << 31)
335 
336 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
337 /*                                       E_AHB_READ Codes */
338 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
339 
340 /*                                                        opcode    Ptr PostIncrement (0 means pre-inc)   Rdata Dest */
341 /*                                                        Pointer       WData Source        Offset UpdatePointer */
342 /*                                                        SizeWord    Signed Access  Cond */
343 
344 /* LDR (Load, Load Byte, LoadByteSigned) */
345 #define E_LDR(dest, source, offset8s)                                                                            \
346     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \
347         (EU << 5)
348 #define E_LDRB(dest, source, offset8s)                                                                           \
349     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \
350         (EU << 5)
351 #define E_LDRBS(dest, source, offset8s)                                                                          \
352     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \
353         (EU << 5)
354 
355 /* Conditional LDR (Load, Load Byte, LoadByteSigned) */
356 #define E_COND_LDR(cond, dest, source, offset8s)                                                                 \
357     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \
358         (cond << 5)
359 #define E_COND_LDRB(cond, dest, source, offset8s)                                                                \
360     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \
361         (cond << 5)
362 #define E_COND_LDRBS(cond, dest, source, offset8s)                                                               \
363     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \
364         (cond << 5)
365 
366 /* With Update Pointer */
367 #define E_LDR_PRE(dest, source, offset8s)                                                                        \
368     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \
369         (EU << 5)
370 #define E_LDRB_PRE(dest, source, offset8s)                                                                       \
371     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \
372         (EU << 5)
373 #define E_LDRBS_PRE(dest, source, offset8s)                                                                      \
374     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \
375         (EU << 5)
376 #define E_COND_LDR_PRE(cond, dest, source, offset8s)                                                             \
377     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \
378         (cond << 5)
379 #define E_COND_LDRB_PRE(cond, dest, source, offset8s)                                                            \
380     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \
381         (cond << 5)
382 #define E_COND_LDRBS_PRE(cond, dest, source, offset8s)                                                           \
383     DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \
384         (cond << 5)
385 
386 /* With Update Pointer (Post Increment pointer) */
387 #define E_LDR_POST(dest, source, offset8s)                                                                       \
388     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \
389         (EU << 5)
390 #define E_LDRB_POST(dest, source, offset8s)                                                                      \
391     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \
392         (EU << 5)
393 #define E_LDRBS_POST(dest, source, offset8s)                                                                     \
394     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \
395         (EU << 5)
396 #define E_COND_LDR_POST(cond, dest, source, offset8s)                                                            \
397     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \
398         (cond << 5)
399 #define E_COND_LDRB_POST(cond, dest, source, offset8s)                                                           \
400     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \
401         (cond << 5)
402 #define E_COND_LDRBS_POST(cond, dest, source, offset8s)                                                          \
403     DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \
404         (cond << 5)
405 
406 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
407 /*                                       E_AHB_WRITE Codes */
408 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
409 
410 /*                                                       opcode    Ptr PostIncrement (0 means pre-inc)   Rdata Dest */
411 /*                                                       Pointer       WData Source        offset8s UpdatePointer */
412 /*                                                       SizeWord    Signed Access  Cond */
413 
414 /* STR (Load, Load Byte, LoadByteSigned) */
415 #define E_STR(raddr, rdata, offset8s)                                                                            \
416     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \
417         (EU << 5)
418 #define E_STRB(raddr, rdata, offset8s)                                                                           \
419     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \
420         (EU << 5)
421 
422 /* Conditional STR (Load, Load Byte, LoadByteSigned) */
423 #define E_COND_STR(cond, raddr, rdata, offset8s)                                                                 \
424     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \
425         (cond << 5)
426 #define E_COND_STRB(cond, raddr, rdata, offset8s)                                                                \
427     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \
428         (cond << 5)
429 
430 /* With Update Pointer */
431 #define E_STR_PRE(raddr, rdata, offset8s)                                                                        \
432     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \
433         (EU << 5)
434 #define E_STRB_PRE(raddr, rdata, offset8s)                                                                       \
435     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \
436         (EU << 5)
437 #define E_COND_STR_PRE(cond, raddr, rdata, offset8s)                                                             \
438     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \
439         (cond << 5)
440 #define E_COND_STRB_PRE(cond, raddr, rdata, offset8s)                                                            \
441     DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \
442         (cond << 5)
443 
444 /* With Update Pointer (Post Increment pointer) */
445 #define E_STR_POST(raddr, rdata, offset8s)                                                                       \
446     DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \
447         (EU << 5)
448 #define E_STRB_POST(raddr, rdata, offset8s)                                                                      \
449     DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \
450         (EU << 5)
451 #define E_COND_STR_POST(cond, raddr, rdata, offset8s)                                                            \
452     DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \
453         (cond << 5)
454 #define E_COND_STRB_POST(cond, raddr, rdata, offset8s)                                                           \
455     DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \
456         (cond << 5)
457 
458 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
459 /*                                      Stack Operations (built up from E_LDR and E_STR codes */
460 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
461 
462 /*                                                       opcode    Ptr PostIncrement (0 means pre-inc)   Rdata Dest */
463 /*                                                       Pointer       WData Source        Offset          UpdatePointer
464  */
465 /*                                                       SizeWord    Signed Access  Cond */
466 
467 #define E_PUSH(source) \
468     DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (EU << 5)
469 #define E_POP(dest) \
470     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (EU << 5)
471 #define E_PUSHB(source) \
472     DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (EU << 5)
473 #define E_POPB(dest) \
474     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (EU << 5)
475 
476 #define E_POPBS(dest) \
477     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (EU << 5)
478 
479 #define E_COND_PUSH(cond, source) \
480     DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (cond << 5)
481 #define E_COND_POP(cond, dest) \
482     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (cond << 5)
483 #define E_COND_PUSHB(cond, source) \
484     DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (cond << 5)
485 #define E_COND_POPB(cond, dest) \
486     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (cond << 5)
487 
488 #define E_COND_POPBS(cond, dest) \
489     DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (cond << 5)
490 
491 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
492 /*                                       E_PER_READ Codes */
493 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
494 
495 /*                                                         opcode      Dest       Address                        Cond */
496 
497 #define E_PER_READ(dest, addr20)            DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (EU << 5)
498 #define E_COND_PER_READ(cond, dest, addr20) DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (cond << 5)
499 
500 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
501 /*                                       E_PER_WRITE Codes */
502 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
503 
504 /*                                                         opcode      Dest       Address                        Cond */
505 
506 #define E_PER_WRITE(source, addr20) \
507     DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (EU << 5)
508 #define E_COND_PER_WRITE(cond, source, addr20) \
509     DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (cond << 5)
510 
511 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
512 /*                                       E_ADD Codes */
513 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
514 
515 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
516  */
517 /*                                                         Imm            Use_Imm      Invert Result       Shift Amount
518  */
519 /*                                                         Shift/Rotate    Left/Right   Flip */
520 
521 /* Add reg to reg */
522 #define E_ADD(dest, src1, src2)            DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
523 #define E_ADDS(dest, src1, src2)           DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
524 #define E_COND_ADD(cond, dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
525 #define E_COND_ADDS(cond, dest, src1, src2) \
526     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
527 
528 /* Add reg to reg and invert result */
529 #define E_ADDN(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
530 #define E_ADDNS(dest, src1, src2) \
531     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
532 #define E_COND_ADDN(cond, dest, src1, src2) \
533     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
534 #define E_COND_ADDNS(cond, dest, src1, src2) \
535     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
536 
537 /* Add imm12s to reg */
538 #define E_ADD_IMM(dest, src1, imm12s) DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
539 #define E_ADD_IMMS(dest, src1, imm12s) \
540     DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
541 #define E_COND_ADD_IMM(cond, dest, src1, imm12s) \
542     DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
543 #define E_COND_ADD_IMMS(cond, dest, src1, imm12s) \
544     DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
545 
546 /* Add imm12s to reg and invert result */
547 #define E_ADDN_IMM(dest, src1, imm12s) \
548     DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
549 #define E_ADDN_IMMS(dest, src1, imm12s) \
550     DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
551 #define E_COND_ADDN_IMM(cond, dest, src1, imm12s) \
552     DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
553 #define E_COND_ADDN_IMMS(cond, dest, src1, imm12s) \
554     DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
555 
556 /* Add reg to reg with Post Shift Left */
557 #define E_ADD_LSL(dest, src1, src2, shift5)                                                                  \
558     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
559         (0 << 30) + (0 << 31)
560 #define E_ADD_LSLS(dest, src1, src2, shift5)                                                                \
561     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
562         (0 << 29) + (0 << 30) + (0 << 31)
563 #define E_COND_ADD_LSL(cond, dest, src1, src2, shift5)                                                         \
564     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
565         (0 << 30) + (0 << 31)
566 #define E_COND_ADD_LSLS(cond, dest, src1, src2, shift5)                                                       \
567     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
568         (0 << 29) + (0 << 30) + (0 << 31)
569 
570 /* Add reg to reg and invert result with Post Shift Left */
571 #define E_ADDN_LSL(dest, src1, src2, shift5)                                                                 \
572     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
573         (0 << 29) + (0 << 30) + (0 << 31)
574 #define E_ADDN_LSLS(dest, src1, src2, shift5)                                                 \
575     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
576         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
577 #define E_COND_ADDN_LSL(cond, dest, src1, src2, shift5)                                                        \
578     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
579         (0 << 29) + (0 << 30) + (0 << 31)
580 #define E_COND_ADDN_LSLS(cond, dest, src1, src2, shift5)                                        \
581     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
582         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
583 
584 /* Add reg to reg with Post Shift Right */
585 #define E_ADD_LSR(dest, src1, src2, shift5)                                                                  \
586     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
587         (1 << 30) + (0 << 31)
588 #define E_ADD_LSRS(dest, src1, src2, shift5)                                                                \
589     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
590         (0 << 29) + (1 << 30) + (0 << 31)
591 #define E_COND_ADD_LSR(cond, dest, src1, src2, shift5)                                                         \
592     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
593         (1 << 30) + (0 << 31)
594 #define E_COND_ADD_LSRS(cond, dest, src1, src2, shift5)                                                       \
595     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
596         (0 << 29) + (1 << 30) + (0 << 31)
597 
598 /* Add reg to reg and invert result with Post Shift Right */
599 #define E_ADDN_LSR(dest, src1, src2, shift5)                                                                 \
600     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
601         (0 << 29) + (1 << 30) + (0 << 31)
602 #define E_ADDN_LSRS(dest, src1, src2, shift5)                                                 \
603     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
604         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
605 #define E_COND_ADDN_LSR(cond, dest, src1, src2, shift5)                                                        \
606     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
607         (0 << 29) + (1 << 30) + (0 << 31)
608 #define E_COND_ADDN_LSRS(cond, dest, src1, src2, shift5)                                        \
609     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
610         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
611 
612 /* Add reg to reg with Post Arith Shift Right */
613 #define E_ADD_ASR(dest, src1, src2, shift5)                                                                  \
614     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
615         (0 << 30) + (0 << 31)
616 #define E_ADD_ASRS(dest, src1, src2, shift5)                                                                \
617     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
618         (1 << 29) + (0 << 30) + (0 << 31)
619 #define E_COND_ADD_ASR(cond, dest, src1, src2, shift5)                                                         \
620     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
621         (0 << 30) + (0 << 31)
622 #define E_COND_ADD_ASRS(cond, dest, src1, src2, shift5)                                                       \
623     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
624         (1 << 29) + (0 << 30) + (0 << 31)
625 
626 /* Add reg to reg and invert result with Post Arith Shift Right */
627 #define E_ADDN_ASR(dest, src1, src2, shift5)                                                                 \
628     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
629         (1 << 29) + (0 << 30) + (0 << 31)
630 #define E_ADDN_ASRS(dest, src1, src2, shift5)                                                 \
631     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
632         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
633 #define E_COND_ADDN_ASR(cond, dest, src1, src2, shift5)                                                        \
634     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
635         (1 << 29) + (0 << 30) + (0 << 31)
636 #define E_COND_ADDN_ASRS(cond, dest, src1, src2, shift5)                                        \
637     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
638         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
639 
640 /* Add reg to reg with Post ROR */
641 #define E_ADD_ROR(dest, src1, src2, shift5)                                                                  \
642     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
643         (1 << 30) + (0 << 31)
644 #define E_ADD_RORS(dest, src1, src2, shift5)                                                                \
645     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
646         (1 << 29) + (1 << 30) + (0 << 31)
647 #define E_COND_ADD_ROR(cond, dest, src1, src2, shift5)                                                         \
648     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
649         (1 << 30) + (0 << 31)
650 #define E_COND_ADD_RORS(cond, dest, src1, src2, shift5)                                                       \
651     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
652         (1 << 29) + (1 << 30) + (0 << 31)
653 
654 /* Add reg to reg and invert result with ROR */
655 #define E_ADDN_ROR(dest, src1, src2, shift5)                                                                 \
656     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
657         (1 << 29) + (1 << 30) + (0 << 31)
658 #define E_ADDN_RORS(dest, src1, src2, shift5)                                                 \
659     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
660         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
661 #define E_COND_ADDN_ROR(cond, dest, src1, src2, shift5)                                                        \
662     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
663         (1 << 29) + (1 << 30) + (0 << 31)
664 #define E_COND_ADDN_RORS(cond, dest, src1, src2, shift5)                                        \
665     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
666         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
667 
668 /* Add reg to reg with Flip */
669 #define E_ADD_F(dest, src1, src2)                                                                                   \
670     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
671         (1 << 31)
672 #define E_ADD_FS(dest, src1, src2)                                                                                 \
673     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
674         (0 << 30) + (1 << 31)
675 #define E_COND_ADD_F(cond, dest, src1, src2)                                                                          \
676     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
677         (1 << 31)
678 #define E_COND_ADD_FS(cond, dest, src1, src2)                                                                        \
679     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
680         (0 << 30) + (1 << 31)
681 
682 /* Add reg to reg and invert result with Flip */
683 #define E_ADDN_F(dest, src1, src2)                                                                                  \
684     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
685         (0 << 30) + (1 << 31)
686 #define E_ADDN_FS(dest, src1, src2)                                                                                \
687     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
688         (0 << 29) + (0 << 30) + (1 << 31)
689 #define E_COND_ADDN_F(cond, dest, src1, src2)                                                                         \
690     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
691         (0 << 30) + (1 << 31)
692 #define E_COND_ADDN_FS(cond, dest, src1, src2)                                                                       \
693     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
694         (0 << 29) + (0 << 30) + (1 << 31)
695 
696 /* Add reg to reg with Post Shift Left */
697 #define E_ADD_FLSL(dest, src1, src2, shift5)                                                                 \
698     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
699         (0 << 30) + (1 << 31)
700 #define E_ADD_FLSLS(dest, src1, src2, shift5)                                                               \
701     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
702         (0 << 29) + (0 << 30) + (1 << 31)
703 #define E_COND_ADD_FLSL(cond, dest, src1, src2, shift5)                                                        \
704     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
705         (0 << 30) + (1 << 31)
706 #define E_COND_ADD_FLSLS(cond, dest, src1, src2, shift5)                                                      \
707     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
708         (0 << 29) + (0 << 30) + (1 << 31)
709 
710 /* Add reg to reg and invert result with Post Shift Left */
711 #define E_ADDN_FLSL(dest, src1, src2, shift5)                                                                \
712     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
713         (0 << 29) + (0 << 30) + (1 << 31)
714 #define E_ADDN_FLSLS(dest, src1, src2, shift5)                                                \
715     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
716         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
717 #define E_COND_ADDN_FLSL(cond, dest, src1, src2, shift5)                                                       \
718     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
719         (0 << 29) + (0 << 30) + (1 << 31)
720 #define E_COND_ADDN_FLSLS(cond, dest, src1, src2, shift5)                                       \
721     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
722         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
723 
724 /* Add reg to reg with Post Shift Right */
725 #define E_ADD_FLSR(dest, src1, src2, shift5)                                                                 \
726     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
727         (1 << 30) + (1 << 31)
728 #define E_ADD_FLSRS(dest, src1, src2, shift5)                                                               \
729     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
730         (0 << 29) + (1 << 30) + (1 << 31)
731 #define E_COND_ADD_FLSR(cond, dest, src1, src2, shift5)                                                        \
732     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
733         (1 << 30) + (1 << 31)
734 #define E_COND_ADD_FLSRS(cond, dest, src1, src2, shift5)                                                      \
735     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
736         (0 << 29) + (1 << 30) + (1 << 31)
737 
738 /* Add reg to reg and invert result with Post Shift Right */
739 #define E_ADDN_FLSR(dest, src1, src2, shift5)                                                                \
740     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
741         (0 << 29) + (1 << 30) + (1 << 31)
742 #define E_ADDN_FLSRS(dest, src1, src2, shift5)                                                \
743     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
744         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
745 #define E_COND_ADDN_FLSR(cond, dest, src1, src2, shift5)                                                       \
746     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
747         (0 << 29) + (1 << 30) + (1 << 31)
748 #define E_COND_ADDN_FLSRS(cond, dest, src1, src2, shift5)                                       \
749     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
750         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
751 
752 /* Add reg to reg with Post Arith Shift Right */
753 #define E_ADD_FASR(dest, src1, src2, shift5)                                                                 \
754     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
755         (0 << 30) + (1 << 31)
756 #define E_ADD_FASRS(dest, src1, src2, shift5)                                                               \
757     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
758         (1 << 29) + (0 << 30) + (1 << 31)
759 #define E_COND_ADD_FASR(cond, dest, src1, src2, shift5)                                                        \
760     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
761         (0 << 30) + (1 << 31)
762 #define E_COND_ADD_FASRS(cond, dest, src1, src2, shift5)                                                      \
763     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
764         (1 << 29) + (0 << 30) + (1 << 31)
765 
766 /* Add reg to reg and invert result with Post Arith Shift Right */
767 #define E_ADDN_FASR(dest, src1, src2, shift5)                                                                \
768     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
769         (1 << 29) + (0 << 30) + (1 << 31)
770 #define E_ADDN_FASRS(dest, src1, src2, shift5)                                                \
771     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
772         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
773 #define E_COND_ADDN_FASR(cond, dest, src1, src2, shift5)                                                       \
774     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
775         (1 << 29) + (0 << 30) + (1 << 31)
776 #define E_COND_ADDN_FASRS(cond, dest, src1, src2, shift5)                                       \
777     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
778         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
779 
780 /* Add reg to reg with Post ROR */
781 #define E_ADD_FROR(dest, src1, src2, shift5)                                                                 \
782     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
783         (1 << 30) + (1 << 31)
784 #define E_ADD_FRORS(dest, src1, src2, shift5)                                                               \
785     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
786         (1 << 29) + (1 << 30) + (1 << 31)
787 #define E_COND_ADD_FROR(cond, dest, src1, src2, shift5)                                                        \
788     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
789         (1 << 30) + (1 << 31)
790 #define E_COND_ADD_FRORS(cond, dest, src1, src2, shift5)                                                      \
791     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
792         (1 << 29) + (1 << 30) + (1 << 31)
793 
794 /* Add reg to reg and invert result with ROR */
795 #define E_ADDN_FROR(dest, src1, src2, shift5)                                                                \
796     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
797         (1 << 29) + (1 << 30) + (1 << 31)
798 #define E_ADDN_FRORS(dest, src1, src2, shift5)                                                \
799     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
800         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
801 #define E_COND_ADDN_FROR(cond, dest, src1, src2, shift5)                                                       \
802     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
803         (1 << 29) + (1 << 30) + (1 << 31)
804 #define E_COND_ADDN_FRORS(cond, dest, src1, src2, shift5)                                       \
805     DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
806         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
807 
808 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
809 /*                                       E_SUB Codes */
810 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
811 
812 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
813  */
814 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
815 
816 /* sub reg from reg */
817 #define E_SUB(dest, src1, src2)            DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
818 #define E_SUBS(dest, src1, src2)           DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
819 #define E_COND_SUB(cond, dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
820 #define E_COND_SUBS(cond, dest, src1, src2) \
821     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
822 
823 /* sub reg from reg and invert result */
824 #define E_SUBN(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
825 #define E_SUBNS(dest, src1, src2) \
826     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
827 #define E_COND_SUBN(cond, dest, src1, src2) \
828     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
829 #define E_COND_SUBNS(cond, dest, src1, src2) \
830     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
831 
832 /* sub imm12s from reg */
833 #define E_SUB_IMM(dest, src1, imm12s) DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
834 #define E_SUB_IMMS(dest, src1, imm12s) \
835     DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
836 #define E_COND_SUB_IMM(cond, dest, src1, imm12s) \
837     DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
838 #define E_COND_SUB_IMMS(cond, dest, src1, imm12s) \
839     DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
840 
841 /* sub imm12s from reg and invert result */
842 #define E_SUBN_IMM(dest, src1, imm12s) \
843     DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
844 #define E_SUBN_IMMS(dest, src1, imm12s) \
845     DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
846 #define E_COND_SUBN_IMM(cond, dest, src1, imm12s) \
847     DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
848 #define E_COND_SUBN_IMMS(cond, dest, src1, imm12s) \
849     DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
850 
851 /* SUB reg to reg with Post Shift Left */
852 #define E_SUB_LSL(dest, src1, src2, shift5)                                                                  \
853     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
854         (0 << 30) + (0 << 31)
855 #define E_SUB_LSLS(dest, src1, src2, shift5)                                                                \
856     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
857         (0 << 29) + (0 << 30) + (0 << 31)
858 #define E_COND_SUB_LSL(cond, dest, src1, src2, shift5)                                                         \
859     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
860         (0 << 30) + (0 << 31)
861 #define E_COND_SUB_LSLS(cond, dest, src1, src2, shift5)                                                       \
862     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
863         (0 << 29) + (0 << 30) + (0 << 31)
864 
865 /* SUB reg to reg and invert result with Post Shift Left */
866 #define E_SUBN_LSL(dest, src1, src2, shift5)                                                                 \
867     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
868         (0 << 29) + (0 << 30) + (0 << 31)
869 #define E_SUBN_LSLS(dest, src1, src2, shift5)                                                 \
870     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
871         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
872 #define E_COND_SUBN_LSL(cond, dest, src1, src2, shift5)                                                        \
873     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
874         (0 << 29) + (0 << 30) + (0 << 31)
875 #define E_COND_SUBN_LSLS(cond, dest, src1, src2, shift5)                                        \
876     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
877         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
878 
879 /* SUB reg to reg with Post Shift Right */
880 #define E_SUB_LSR(dest, src1, src2, shift5)                                                                  \
881     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
882         (1 << 30) + (0 << 31)
883 #define E_SUB_LSRS(dest, src1, src2, shift5)                                                                \
884     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
885         (0 << 29) + (1 << 30) + (0 << 31)
886 #define E_COND_SUB_LSR(cond, dest, src1, src2, shift5)                                                         \
887     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
888         (1 << 30) + (0 << 31)
889 #define E_COND_SUB_LSRS(cond, dest, src1, src2, shift5)                                                       \
890     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
891         (0 << 29) + (1 << 30) + (0 << 31)
892 
893 /* SUB reg to reg and invert result with Post Shift Right */
894 #define E_SUBN_LSR(dest, src1, src2, shift5)                                                                 \
895     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
896         (0 << 29) + (1 << 30) + (0 << 31)
897 #define E_SUBN_LSRS(dest, src1, src2, shift5)                                                 \
898     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
899         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
900 #define E_COND_SUBN_LSR(cond, dest, src1, src2, shift5)                                                        \
901     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
902         (0 << 29) + (1 << 30) + (0 << 31)
903 #define E_COND_SUBN_LSRS(cond, dest, src1, src2, shift5)                                        \
904     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
905         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
906 
907 /* SUB reg to reg with Post Arith Shift Right */
908 #define E_SUB_ASR(dest, src1, src2, shift5)                                                                  \
909     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
910         (0 << 30) + (0 << 31)
911 #define E_SUB_ASRS(dest, src1, src2, shift5)                                                                \
912     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
913         (1 << 29) + (0 << 30) + (0 << 31)
914 #define E_COND_SUB_ASR(cond, dest, src1, src2, shift5)                                                         \
915     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
916         (0 << 30) + (0 << 31)
917 #define E_COND_SUB_ASRS(cond, dest, src1, src2, shift5)                                                       \
918     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
919         (1 << 29) + (0 << 30) + (0 << 31)
920 
921 /* SUB reg to reg and invert result with Post Arith Shift Right */
922 #define E_SUBN_ASR(dest, src1, src2, shift5)                                                                 \
923     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
924         (1 << 29) + (0 << 30) + (0 << 31)
925 #define E_SUBN_ASRS(dest, src1, src2, shift5)                                                 \
926     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
927         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
928 #define E_COND_SUBN_ASR(cond, dest, src1, src2, shift5)                                                        \
929     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
930         (1 << 29) + (0 << 30) + (0 << 31)
931 #define E_COND_SUBN_ASRS(cond, dest, src1, src2, shift5)                                        \
932     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
933         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
934 
935 /* SUB reg to reg with Post ROR */
936 #define E_SUB_ROR(dest, src1, src2, shift5)                                                                  \
937     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
938         (1 << 30) + (0 << 31)
939 #define E_SUB_RORS(dest, src1, src2, shift5)                                                                \
940     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
941         (1 << 29) + (1 << 30) + (0 << 31)
942 #define E_COND_SUB_ROR(cond, dest, src1, src2, shift5)                                                         \
943     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
944         (1 << 30) + (0 << 31)
945 #define E_COND_SUB_RORS(cond, dest, src1, src2, shift5)                                                       \
946     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
947         (1 << 29) + (1 << 30) + (0 << 31)
948 
949 /* SUB reg to reg and invert result with ROR */
950 #define E_SUBN_ROR(dest, src1, src2, shift5)                                                                 \
951     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
952         (1 << 29) + (1 << 30) + (0 << 31)
953 #define E_SUBN_RORS(dest, src1, src2, shift5)                                                 \
954     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
955         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
956 #define E_COND_SUBN_ROR(cond, dest, src1, src2, shift5)                                                        \
957     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
958         (1 << 29) + (1 << 30) + (0 << 31)
959 #define E_COND_SUBN_RORS(cond, dest, src1, src2, shift5)                                        \
960     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
961         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
962 
963 /* Flip Endianness and then shift5/Rotate */
964 
965 /* Sub reg to reg with Flip */
966 #define E_SUB_F(dest, src1, src2)                                                                                   \
967     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
968         (1 << 31)
969 #define E_SUB_FS(dest, src1, src2)                                                                                 \
970     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
971         (0 << 30) + (1 << 31)
972 #define E_COND_SUB_F(cond, dest, src1, src2)                                                                          \
973     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
974         (1 << 31)
975 #define E_COND_SUB_FS(cond, dest, src1, src2)                                                                        \
976     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
977         (0 << 30) + (1 << 31)
978 
979 /* Sub reg to reg and invert result with Flip */
980 #define E_SUBN_F(dest, src1, src2)                                                                                  \
981     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
982         (0 << 30) + (1 << 31)
983 #define E_SUBN_FS(dest, src1, src2)                                                                                \
984     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
985         (0 << 29) + (0 << 30) + (1 << 31)
986 #define E_COND_SUBN_F(cond, dest, src1, src2)                                                                         \
987     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
988         (0 << 30) + (1 << 31)
989 #define E_COND_SUBN_FS(cond, dest, src1, src2)                                                                       \
990     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
991         (0 << 29) + (0 << 30) + (1 << 31)
992 
993 /* SUB reg to reg with Post Shift Left */
994 #define E_SUB_FLSL(dest, src1, src2, shift5)                                                                 \
995     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
996         (0 << 30) + (1 << 31)
997 #define E_SUB_FLSLS(dest, src1, src2, shift5)                                                               \
998     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
999         (0 << 29) + (0 << 30) + (1 << 31)
1000 #define E_COND_SUB_FLSL(cond, dest, src1, src2, shift5)                                                        \
1001     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1002         (0 << 30) + (1 << 31)
1003 #define E_COND_SUB_FLSLS(cond, dest, src1, src2, shift5)                                                      \
1004     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1005         (0 << 29) + (0 << 30) + (1 << 31)
1006 
1007 /* SUB reg to reg and invert result with Post Shift Left */
1008 #define E_SUBN_FLSL(dest, src1, src2, shift5)                                                                \
1009     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1010         (0 << 29) + (0 << 30) + (1 << 31)
1011 #define E_SUBN_FLSLS(dest, src1, src2, shift5)                                                \
1012     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1013         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1014 #define E_COND_SUBN_FLSL(cond, dest, src1, src2, shift5)                                                       \
1015     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1016         (0 << 29) + (0 << 30) + (1 << 31)
1017 #define E_COND_SUBN_FLSLS(cond, dest, src1, src2, shift5)                                       \
1018     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1019         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1020 
1021 /* SUB reg to reg with Post Shift Right */
1022 #define E_SUB_FLSR(dest, src1, src2, shift5)                                                                 \
1023     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1024         (1 << 30) + (1 << 31)
1025 #define E_SUB_FLSRS(dest, src1, src2, shift5)                                                               \
1026     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1027         (0 << 29) + (1 << 30) + (1 << 31)
1028 #define E_COND_SUB_FLSR(cond, dest, src1, src2, shift5)                                                        \
1029     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1030         (1 << 30) + (1 << 31)
1031 #define E_COND_SUB_FLSRS(cond, dest, src1, src2, shift5)                                                      \
1032     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1033         (0 << 29) + (1 << 30) + (1 << 31)
1034 
1035 /* SUB reg to reg and invert result with Post Shift Right */
1036 #define E_SUBN_FLSR(dest, src1, src2, shift5)                                                                \
1037     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1038         (0 << 29) + (1 << 30) + (1 << 31)
1039 #define E_SUBN_FLSRS(dest, src1, src2, shift5)                                                \
1040     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1041         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1042 #define E_COND_SUBN_FLSR(cond, dest, src1, src2, shift5)                                                       \
1043     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1044         (0 << 29) + (1 << 30) + (1 << 31)
1045 #define E_COND_SUBN_FLSRS(cond, dest, src1, src2, shift5)                                       \
1046     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1047         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1048 
1049 /* SUB reg to reg with Post Arith Shift Right */
1050 #define E_SUB_FASR(dest, src1, src2, shift5)                                                                 \
1051     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1052         (0 << 30) + (1 << 31)
1053 #define E_SUB_FASRS(dest, src1, src2, shift5)                                                               \
1054     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1055         (1 << 29) + (0 << 30) + (1 << 31)
1056 #define E_COND_SUB_FASR(cond, dest, src1, src2, shift5)                                                        \
1057     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1058         (0 << 30) + (1 << 31)
1059 #define E_COND_SUB_FASRS(cond, dest, src1, src2, shift5)                                                      \
1060     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1061         (1 << 29) + (0 << 30) + (1 << 31)
1062 
1063 /* SUB reg to reg and invert result with Post Arith Shift Right */
1064 #define E_SUBN_FASR(dest, src1, src2, shift5)                                                                \
1065     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1066         (1 << 29) + (0 << 30) + (1 << 31)
1067 #define E_SUBN_FASRS(dest, src1, src2, shift5)                                                \
1068     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1069         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1070 #define E_COND_SUBN_FASR(cond, dest, src1, src2, shift5)                                                       \
1071     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1072         (1 << 29) + (0 << 30) + (1 << 31)
1073 #define E_COND_SUBN_FASRS(cond, dest, src1, src2, shift5)                                       \
1074     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1075         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1076 
1077 /* SUB reg to reg with Post ROR */
1078 #define E_SUB_FROR(dest, src1, src2, shift5)                                                                 \
1079     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1080         (1 << 30) + (1 << 31)
1081 #define E_SUB_FRORS(dest, src1, src2, shift5)                                                               \
1082     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1083         (1 << 29) + (1 << 30) + (1 << 31)
1084 #define E_COND_SUB_FROR(cond, dest, src1, src2, shift5)                                                        \
1085     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1086         (1 << 30) + (1 << 31)
1087 #define E_COND_SUB_FRORS(cond, dest, src1, src2, shift5)                                                      \
1088     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1089         (1 << 29) + (1 << 30) + (1 << 31)
1090 
1091 /* SUB reg to reg and invert result with ROR */
1092 #define E_SUBN_FROR(dest, src1, src2, shift5)                                                                \
1093     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1094         (1 << 29) + (1 << 30) + (1 << 31)
1095 #define E_SUBN_FRORS(dest, src1, src2, shift5)                                                \
1096     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1097         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1098 #define E_COND_SUBN_FROR(cond, dest, src1, src2, shift5)                                                       \
1099     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1100         (1 << 29) + (1 << 30) + (1 << 31)
1101 #define E_COND_SUBN_FRORS(cond, dest, src1, src2, shift5)                                       \
1102     DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1103         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1104 
1105 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1106 /*                                       E_ADC Codes */
1107 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1108 
1109 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
1110  */
1111 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
1112 
1113 /* carry add reg from reg */
1114 #define E_ADC(dest, src1, src2)            DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
1115 #define E_ADCS(dest, src1, src2)           DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
1116 #define E_COND_ADC(cond, dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
1117 #define E_COND_ADCS(cond, dest, src1, src2) \
1118     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
1119 
1120 /* carry add reg from reg and invert result */
1121 #define E_ADCN(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
1122 #define E_ADCNS(dest, src1, src2) \
1123     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
1124 #define E_COND_ADCN(cond, dest, src1, src2) \
1125     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
1126 #define E_COND_ADCNS(cond, dest, src1, src2) \
1127     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
1128 
1129 /* carry add imm12s from reg */
1130 #define E_ADC_IMM(dest, src1, imm12s) DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
1131 #define E_ADC_IMMS(dest, src1, imm12s) \
1132     DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
1133 #define E_COND_ADC_IMM(cond, dest, src1, imm12s) \
1134     DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
1135 #define E_COND_ADC_IMMS(cond, dest, src1, imm12s) \
1136     DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
1137 
1138 /* carry add imm12s from reg and invert result */
1139 #define E_ADCN_IMM(dest, src1, imm12s) \
1140     DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1141 #define E_ADCN_IMMS(dest, src1, imm12s) \
1142     DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1143 #define E_COND_ADCN_IMM(cond, dest, src1, imm12s) \
1144     DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1145 #define E_COND_ADCN_IMMS(cond, dest, src1, imm12s) \
1146     DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1147 
1148 /* ADC reg to reg with Post Shift Left */
1149 #define E_ADC_LSL(dest, src1, src2, shift5)                                                                  \
1150     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1151         (0 << 30) + (0 << 31)
1152 #define E_ADC_LSLS(dest, src1, src2, shift5)                                                                \
1153     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1154         (0 << 29) + (0 << 30) + (0 << 31)
1155 #define E_COND_ADC_LSL(cond, dest, src1, src2, shift5)                                                         \
1156     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1157         (0 << 30) + (0 << 31)
1158 #define E_COND_ADC_LSLS(cond, dest, src1, src2, shift5)                                                       \
1159     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1160         (0 << 29) + (0 << 30) + (0 << 31)
1161 
1162 /* ADC reg to reg and invert result with Post Shift Left */
1163 #define E_ADCN_LSL(dest, src1, src2, shift5)                                                                 \
1164     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1165         (0 << 29) + (0 << 30) + (0 << 31)
1166 #define E_ADCN_LSLS(dest, src1, src2, shift5)                                                 \
1167     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1168         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1169 #define E_COND_ADCN_LSL(cond, dest, src1, src2, shift5)                                                        \
1170     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1171         (0 << 29) + (0 << 30) + (0 << 31)
1172 #define E_COND_ADCN_LSLS(cond, dest, src1, src2, shift5)                                        \
1173     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1174         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1175 
1176 /* ADC reg to reg with Post Shift Right */
1177 #define E_ADC_LSR(dest, src1, src2, shift5)                                                                  \
1178     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1179         (1 << 30) + (0 << 31)
1180 #define E_ADC_LSRS(dest, src1, src2, shift5)                                                                \
1181     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1182         (0 << 29) + (1 << 30) + (0 << 31)
1183 #define E_COND_ADC_LSR(cond, dest, src1, src2, shift5)                                                         \
1184     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1185         (1 << 30) + (0 << 31)
1186 #define E_COND_ADC_LSRS(cond, dest, src1, src2, shift5)                                                       \
1187     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1188         (0 << 29) + (1 << 30) + (0 << 31)
1189 
1190 /* ADC reg to reg and invert result with Post Shift Right */
1191 #define E_ADCN_LSR(dest, src1, src2, shift5)                                                                 \
1192     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1193         (0 << 29) + (1 << 30) + (0 << 31)
1194 #define E_ADCN_LSRS(dest, src1, src2, shift5)                                                 \
1195     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1196         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1197 #define E_COND_ADCN_LSR(cond, dest, src1, src2, shift5)                                                        \
1198     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1199         (0 << 29) + (1 << 30) + (0 << 31)
1200 #define E_COND_ADCN_LSRS(cond, dest, src1, src2, shift5)                                        \
1201     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1202         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1203 
1204 /* ADC reg to reg with Post Arith Shift Right */
1205 #define E_ADC_ASR(dest, src1, src2, shift5)                                                                  \
1206     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1207         (0 << 30) + (0 << 31)
1208 #define E_ADC_ASRS(dest, src1, src2, shift5)                                                                \
1209     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1210         (1 << 29) + (0 << 30) + (0 << 31)
1211 #define E_COND_ADC_ASR(cond, dest, src1, src2, shift5)                                                         \
1212     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1213         (0 << 30) + (0 << 31)
1214 #define E_COND_ADC_ASRS(cond, dest, src1, src2, shift5)                                                       \
1215     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1216         (1 << 29) + (0 << 30) + (0 << 31)
1217 
1218 /* ADC reg to reg and invert result with Post Arith Shift Right */
1219 #define E_ADCN_ASR(dest, src1, src2, shift5)                                                                 \
1220     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1221         (1 << 29) + (0 << 30) + (0 << 31)
1222 #define E_ADCN_ASRS(dest, src1, src2, shift5)                                                 \
1223     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1224         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1225 #define E_COND_ADCN_ASR(cond, dest, src1, src2, shift5)                                                        \
1226     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1227         (1 << 29) + (0 << 30) + (0 << 31)
1228 #define E_COND_ADCN_ASRS(cond, dest, src1, src2, shift5)                                        \
1229     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1230         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1231 
1232 /* ADC reg to reg with Post ROR */
1233 #define E_ADC_ROR(dest, src1, src2, shift5)                                                                  \
1234     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1235         (1 << 30) + (0 << 31)
1236 #define E_ADC_RORS(dest, src1, src2, shift5)                                                                \
1237     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1238         (1 << 29) + (1 << 30) + (0 << 31)
1239 #define E_COND_ADC_ROR(cond, dest, src1, src2, shift5)                                                         \
1240     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1241         (1 << 30) + (0 << 31)
1242 #define E_COND_ADC_RORS(cond, dest, src1, src2, shift5)                                                       \
1243     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1244         (1 << 29) + (1 << 30) + (0 << 31)
1245 
1246 /* ADC reg to reg and invert result with ROR */
1247 #define E_ADCN_ROR(dest, src1, src2, shift5)                                                                 \
1248     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1249         (1 << 29) + (1 << 30) + (0 << 31)
1250 #define E_ADCN_RORS(dest, src1, src2, shift5)                                                 \
1251     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1252         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1253 #define E_COND_ADCN_ROR(cond, dest, src1, src2, shift5)                                                        \
1254     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1255         (1 << 29) + (1 << 30) + (0 << 31)
1256 #define E_COND_ADCN_RORS(cond, dest, src1, src2, shift5)                                        \
1257     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1258         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1259 
1260 /* Flip Endianness and then shift5/Rotate */
1261 
1262 /* adc reg to reg with Flip */
1263 #define E_ADC_F(dest, src1, src2)                                                                                   \
1264     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1265         (1 << 31)
1266 #define E_ADC_FS(dest, src1, src2)                                                                                 \
1267     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1268         (0 << 30) + (1 << 31)
1269 #define E_COND_ADC_F(cond, dest, src1, src2)                                                                          \
1270     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1271         (1 << 31)
1272 #define E_COND_ADC_FS(cond, dest, src1, src2)                                                                        \
1273     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1274         (0 << 30) + (1 << 31)
1275 
1276 /* ADC reg to reg and invert result with Flip */
1277 #define E_ADCN_F(dest, src1, src2)                                                                                  \
1278     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1279         (0 << 30) + (1 << 31)
1280 #define E_ADCN_FS(dest, src1, src2)                                                                                \
1281     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1282         (0 << 29) + (0 << 30) + (1 << 31)
1283 #define E_COND_ADCN_F(cond, dest, src1, src2)                                                                         \
1284     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1285         (0 << 30) + (1 << 31)
1286 #define E_COND_ADCN_FS(cond, dest, src1, src2)                                                                       \
1287     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1288         (0 << 29) + (0 << 30) + (1 << 31)
1289 
1290 /* ADC reg to reg with Post Shift Left */
1291 #define E_ADC_FLSL(dest, src1, src2, shift5)                                                                 \
1292     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1293         (0 << 30) + (1 << 31)
1294 #define E_ADC_FLSLS(dest, src1, src2, shift5)                                                               \
1295     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1296         (0 << 29) + (0 << 30) + (1 << 31)
1297 #define E_COND_ADC_FLSL(cond, dest, src1, src2, shift5)                                                        \
1298     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1299         (0 << 30) + (1 << 31)
1300 #define E_COND_ADC_FLSLS(cond, dest, src1, src2, shift5)                                                      \
1301     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1302         (0 << 29) + (0 << 30) + (1 << 31)
1303 
1304 /* ADC reg to reg and invert result with Post Shift Left */
1305 #define E_ADCN_FLSL(dest, src1, src2, shift5)                                                                \
1306     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1307         (0 << 29) + (0 << 30) + (1 << 31)
1308 #define E_ADCN_FLSLS(dest, src1, src2, shift5)                                                \
1309     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1310         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1311 #define E_COND_ADCN_FLSL(cond, dest, src1, src2, shift5)                                                       \
1312     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1313         (0 << 29) + (0 << 30) + (1 << 31)
1314 #define E_COND_ADCN_FLSLS(cond, dest, src1, src2, shift5)                                       \
1315     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1316         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1317 
1318 /* ADC reg to reg with Post Shift Right */
1319 #define E_ADC_FLSR(dest, src1, src2, shift5)                                                                 \
1320     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1321         (1 << 30) + (1 << 31)
1322 #define E_ADC_FLSRS(dest, src1, src2, shift5)                                                               \
1323     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1324         (0 << 29) + (1 << 30) + (1 << 31)
1325 #define E_COND_ADC_FLSR(cond, dest, src1, src2, shift5)                                                        \
1326     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1327         (1 << 30) + (1 << 31)
1328 #define E_COND_ADC_FLSRS(cond, dest, src1, src2, shift5)                                                      \
1329     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1330         (0 << 29) + (1 << 30) + (1 << 31)
1331 
1332 /* ADC reg to reg and invert result with Post Shift Right */
1333 #define E_ADCN_FLSR(dest, src1, src2, shift5)                                                                \
1334     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1335         (0 << 29) + (1 << 30) + (1 << 31)
1336 #define E_ADCN_FLSRS(dest, src1, src2, shift5)                                                \
1337     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1338         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1339 #define E_COND_ADCN_FLSR(cond, dest, src1, src2, shift5)                                                       \
1340     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1341         (0 << 29) + (1 << 30) + (1 << 31)
1342 #define E_COND_ADCN_FLSRS(cond, dest, src1, src2, shift5)                                       \
1343     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1344         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1345 
1346 /* ADC reg to reg with Post Arith Shift Right */
1347 #define E_ADC_FASR(dest, src1, src2, shift5)                                                                 \
1348     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1349         (0 << 30) + (1 << 31)
1350 #define E_ADC_FASRS(dest, src1, src2, shift5)                                                               \
1351     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1352         (1 << 29) + (0 << 30) + (1 << 31)
1353 #define E_COND_ADC_FASR(cond, dest, src1, src2, shift5)                                                        \
1354     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1355         (0 << 30) + (1 << 31)
1356 #define E_COND_ADC_FASRS(cond, dest, src1, src2, shift5)                                                      \
1357     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1358         (1 << 29) + (0 << 30) + (1 << 31)
1359 
1360 /* ADC reg to reg and invert result with Post Arith Shift Right */
1361 #define E_ADCN_FASR(dest, src1, src2, shift5)                                                                \
1362     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1363         (1 << 29) + (0 << 30) + (1 << 31)
1364 #define E_ADCN_FASRS(dest, src1, src2, shift5)                                                \
1365     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1366         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1367 #define E_COND_ADCN_FASR(cond, dest, src1, src2, shift5)                                                       \
1368     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1369         (1 << 29) + (0 << 30) + (1 << 31)
1370 #define E_COND_ADCN_FASRS(cond, dest, src1, src2, shift5)                                       \
1371     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1372         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1373 
1374 /* ADC reg to reg with Post ROR */
1375 #define E_ADC_FROR(dest, src1, src2, shift5)                                                                 \
1376     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1377         (1 << 30) + (1 << 31)
1378 #define E_ADC_FRORS(dest, src1, src2, shift5)                                                               \
1379     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1380         (1 << 29) + (1 << 30) + (1 << 31)
1381 #define E_COND_ADC_FROR(cond, dest, src1, src2, shift5)                                                        \
1382     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1383         (1 << 30) + (1 << 31)
1384 #define E_COND_ADC_FRORS(cond, dest, src1, src2, shift5)                                                      \
1385     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1386         (1 << 29) + (1 << 30) + (1 << 31)
1387 
1388 /* ADC reg to reg and invert result with ROR */
1389 #define E_ADCN_FROR(dest, src1, src2, shift5)                                                                \
1390     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1391         (1 << 29) + (1 << 30) + (1 << 31)
1392 #define E_ADCN_FRORS(dest, src1, src2, shift5)                                                \
1393     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1394         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1395 #define E_COND_ADCN_FROR(cond, dest, src1, src2, shift5)                                                       \
1396     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1397         (1 << 29) + (1 << 30) + (1 << 31)
1398 #define E_COND_ADCN_FRORS(cond, dest, src1, src2, shift5)                                       \
1399     DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1400         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1401 
1402 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1403 /*                                       E_SBC Codes */
1404 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1405 
1406 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
1407  */
1408 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
1409 
1410 /* carry sub reg from reg */
1411 #define E_SBC(dest, src1, src2)            DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
1412 #define E_SBCS(dest, src1, src2)           DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
1413 #define E_COND_SBC(cond, dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
1414 #define E_COND_SBCS(cond, dest, src1, src2) \
1415     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
1416 
1417 /* carry sub reg from reg and invert result */
1418 #define E_SBCN(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
1419 #define E_SBCNS(dest, src1, src2) \
1420     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
1421 #define E_COND_SBCN(cond, dest, src1, src2) \
1422     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
1423 #define E_COND_SBCNS(cond, dest, src1, src2) \
1424     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
1425 
1426 /* carry sub imm12s from reg */
1427 #define E_SBC_IMM(dest, src1, imm12s) DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
1428 #define E_SBC_IMMS(dest, src1, imm12s) \
1429     DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
1430 #define E_COND_SBC_IMM(cond, dest, src1, imm12s) \
1431     DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
1432 #define E_COND_SBC_IMMS(cond, dest, src1, imm12s) \
1433     DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
1434 
1435 /* carry sub imm12s from reg and invert result */
1436 #define E_SBCN_IMM(dest, src1, imm12s) \
1437     DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1438 #define E_SBCN_IMMS(dest, src1, imm12s) \
1439     DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1440 #define E_COND_SBCN_IMM(cond, dest, src1, imm12s) \
1441     DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1442 #define E_COND_SBCN_IMMS(cond, dest, src1, imm12s) \
1443     DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1444 
1445 /* SBC reg to reg with Post Shift Left */
1446 #define E_SBC_LSL(dest, src1, src2, shift5)                                                                  \
1447     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1448         (0 << 30) + (0 << 31)
1449 #define E_SBC_LSLS(dest, src1, src2, shift5)                                                                \
1450     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1451         (0 << 29) + (0 << 30) + (0 << 31)
1452 #define E_COND_SBC_LSL(cond, dest, src1, src2, shift5)                                                         \
1453     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1454         (0 << 30) + (0 << 31)
1455 #define E_COND_SBC_LSLS(cond, dest, src1, src2, shift5)                                                       \
1456     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1457         (0 << 29) + (0 << 30) + (0 << 31)
1458 
1459 /* SBC reg to reg and invert result with Post Shift Left */
1460 #define E_SBCN_LSL(dest, src1, src2, shift5)                                                                 \
1461     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1462         (0 << 29) + (0 << 30) + (0 << 31)
1463 #define E_SBCN_LSLS(dest, src1, src2, shift5)                                                 \
1464     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1465         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1466 #define E_COND_SBCN_LSL(cond, dest, src1, src2, shift5)                                                        \
1467     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1468         (0 << 29) + (0 << 30) + (0 << 31)
1469 #define E_COND_SBCN_LSLS(cond, dest, src1, src2, shift5)                                        \
1470     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1471         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1472 
1473 /* SBC reg to reg with Post Shift Right */
1474 #define E_SBC_LSR(dest, src1, src2, shift5)                                                                  \
1475     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1476         (1 << 30) + (0 << 31)
1477 #define E_SBC_LSRS(dest, src1, src2, shift5)                                                                \
1478     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1479         (0 << 29) + (1 << 30) + (0 << 31)
1480 #define E_COND_SBC_LSR(cond, dest, src1, src2, shift5)                                                         \
1481     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1482         (1 << 30) + (0 << 31)
1483 #define E_COND_SBC_LSRS(cond, dest, src1, src2, shift5)                                                       \
1484     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1485         (0 << 29) + (1 << 30) + (0 << 31)
1486 
1487 /* SBC reg to reg and invert result with Post Shift Right */
1488 #define E_SBCN_LSR(dest, src1, src2, shift5)                                                                 \
1489     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1490         (0 << 29) + (1 << 30) + (0 << 31)
1491 #define E_SBCN_LSRS(dest, src1, src2, shift5)                                                 \
1492     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1493         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1494 #define E_COND_SBCN_LSR(cond, dest, src1, src2, shift5)                                                        \
1495     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1496         (0 << 29) + (1 << 30) + (0 << 31)
1497 #define E_COND_SBCN_LSRS(cond, dest, src1, src2, shift5)                                        \
1498     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1499         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1500 
1501 /* SBC reg to reg with Post Arith Shift Right */
1502 #define E_SBC_ASR(dest, src1, src2, shift5)                                                                  \
1503     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1504         (0 << 30) + (0 << 31)
1505 #define E_SBC_ASRS(dest, src1, src2, shift5)                                                                \
1506     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1507         (1 << 29) + (0 << 30) + (0 << 31)
1508 #define E_COND_SBC_ASR(cond, dest, src1, src2, shift5)                                                         \
1509     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1510         (0 << 30) + (0 << 31)
1511 #define E_COND_SBC_ASRS(cond, dest, src1, src2, shift5)                                                       \
1512     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1513         (1 << 29) + (0 << 30) + (0 << 31)
1514 
1515 /* SBC reg to reg and invert result with Post Arith Shift Right */
1516 #define E_SBCN_ASR(dest, src1, src2, shift5)                                                                 \
1517     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1518         (1 << 29) + (0 << 30) + (0 << 31)
1519 #define E_SBCN_ASRS(dest, src1, src2, shift5)                                                 \
1520     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1521         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1522 #define E_COND_SBCN_ASR(cond, dest, src1, src2, shift5)                                                        \
1523     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1524         (1 << 29) + (0 << 30) + (0 << 31)
1525 #define E_COND_SBCN_ASRS(cond, dest, src1, src2, shift5)                                        \
1526     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1527         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1528 
1529 /* SBC reg to reg with Post ROR */
1530 #define E_SBC_ROR(dest, src1, src2, shift5)                                                                  \
1531     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1532         (1 << 30) + (0 << 31)
1533 #define E_SBC_RORS(dest, src1, src2, shift5)                                                                \
1534     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1535         (1 << 29) + (1 << 30) + (0 << 31)
1536 #define E_COND_SBC_ROR(cond, dest, src1, src2, shift5)                                                         \
1537     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1538         (1 << 30) + (0 << 31)
1539 #define E_COND_SBC_RORS(cond, dest, src1, src2, shift5)                                                       \
1540     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1541         (1 << 29) + (1 << 30) + (0 << 31)
1542 
1543 /* SBC reg to reg and invert result with ROR */
1544 #define E_SBCN_ROR(dest, src1, src2, shift5)                                                                 \
1545     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1546         (1 << 29) + (1 << 30) + (0 << 31)
1547 #define E_SBCN_RORS(dest, src1, src2, shift5)                                                 \
1548     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1549         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1550 #define E_COND_SBCN_ROR(cond, dest, src1, src2, shift5)                                                        \
1551     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1552         (1 << 29) + (1 << 30) + (0 << 31)
1553 #define E_COND_SBCN_RORS(cond, dest, src1, src2, shift5)                                        \
1554     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1555         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1556 
1557 /* Flip Endianness and then shift5/Rotate */
1558 
1559 /* SBC reg to reg with Flip */
1560 #define E_SBC_F(dest, src1, src2)                                                                                   \
1561     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1562         (1 << 31)
1563 #define E_SBC_FS(dest, src1, src2)                                                                                 \
1564     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1565         (0 << 30) + (1 << 31)
1566 #define E_COND_SBC_F(cond, dest, src1, src2)                                                                          \
1567     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1568         (1 << 31)
1569 #define E_COND_SBC_FS(cond, dest, src1, src2)                                                                        \
1570     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1571         (0 << 30) + (1 << 31)
1572 
1573 /* SBC reg to reg and invert result with Flip */
1574 #define E_SBCN_F(dest, src1, src2)                                                                                  \
1575     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1576         (0 << 30) + (1 << 31)
1577 #define E_SBCN_FS(dest, src1, src2)                                                                                \
1578     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1579         (0 << 29) + (0 << 30) + (1 << 31)
1580 #define E_COND_SBCN_F(cond, dest, src1, src2)                                                                         \
1581     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1582         (0 << 30) + (1 << 31)
1583 #define E_COND_SBCN_FS(cond, dest, src1, src2)                                                                       \
1584     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1585         (0 << 29) + (0 << 30) + (1 << 31)
1586 
1587 /* SBC reg to reg with Post Shift Left */
1588 #define E_SBC_FLSL(dest, src1, src2, shift5)                                                                 \
1589     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1590         (0 << 30) + (1 << 31)
1591 #define E_SBC_FLSLS(dest, src1, src2, shift5)                                                               \
1592     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1593         (0 << 29) + (0 << 30) + (1 << 31)
1594 #define E_COND_SBC_FLSL(cond, dest, src1, src2, shift5)                                                        \
1595     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1596         (0 << 30) + (1 << 31)
1597 #define E_COND_SBC_FLSLS(cond, dest, src1, src2, shift5)                                                      \
1598     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1599         (0 << 29) + (0 << 30) + (1 << 31)
1600 
1601 /* SBC reg to reg and invert result with Post Shift Left */
1602 #define E_SBCN_FLSL(dest, src1, src2, shift5)                                                                \
1603     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1604         (0 << 29) + (0 << 30) + (1 << 31)
1605 #define E_SBCN_FLSLS(dest, src1, src2, shift5)                                                \
1606     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1607         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1608 #define E_COND_SBCN_FLSL(cond, dest, src1, src2, shift5)                                                       \
1609     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1610         (0 << 29) + (0 << 30) + (1 << 31)
1611 #define E_COND_SBCN_FLSLS(cond, dest, src1, src2, shift5)                                       \
1612     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1613         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1614 
1615 /* SBC reg to reg with Post Shift Right */
1616 #define E_SBC_FLSR(dest, src1, src2, shift5)                                                                 \
1617     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1618         (1 << 30) + (1 << 31)
1619 #define E_SBC_FLSRS(dest, src1, src2, shift5)                                                               \
1620     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1621         (0 << 29) + (1 << 30) + (1 << 31)
1622 #define E_COND_SBC_FLSR(cond, dest, src1, src2, shift5)                                                        \
1623     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1624         (1 << 30) + (1 << 31)
1625 #define E_COND_SBC_FLSRS(cond, dest, src1, src2, shift5)                                                      \
1626     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1627         (0 << 29) + (1 << 30) + (1 << 31)
1628 
1629 /* SBC reg to reg and invert result with Post Shift Right */
1630 #define E_SBCN_FLSR(dest, src1, src2, shift5)                                                                \
1631     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1632         (0 << 29) + (1 << 30) + (1 << 31)
1633 #define E_SBCN_FLSRS(dest, src1, src2, shift5)                                                \
1634     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1635         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1636 #define E_COND_SBCN_FLSR(cond, dest, src1, src2, shift5)                                                       \
1637     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1638         (0 << 29) + (1 << 30) + (1 << 31)
1639 #define E_COND_SBCN_FLSRS(cond, dest, src1, src2, shift5)                                       \
1640     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1641         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1642 
1643 /* SBC reg to reg with Post Arith Shift Right */
1644 #define E_SBC_FASR(dest, src1, src2, shift5)                                                                 \
1645     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1646         (0 << 30) + (1 << 31)
1647 #define E_SBC_FASRS(dest, src1, src2, shift5)                                                               \
1648     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1649         (1 << 29) + (0 << 30) + (1 << 31)
1650 #define E_COND_SBC_FASR(cond, dest, src1, src2, shift5)                                                        \
1651     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1652         (0 << 30) + (1 << 31)
1653 #define E_COND_SBC_FASRS(cond, dest, src1, src2, shift5)                                                      \
1654     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1655         (1 << 29) + (0 << 30) + (1 << 31)
1656 
1657 /* SBC reg to reg and invert result with Post Arith Shift Right */
1658 #define E_SBCN_FASR(dest, src1, src2, shift5)                                                                \
1659     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1660         (1 << 29) + (0 << 30) + (1 << 31)
1661 #define E_SBCN_FASRS(dest, src1, src2, shift5)                                                \
1662     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1663         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1664 #define E_COND_SBCN_FASR(cond, dest, src1, src2, shift5)                                                       \
1665     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1666         (1 << 29) + (0 << 30) + (1 << 31)
1667 #define E_COND_SBCN_FASRS(cond, dest, src1, src2, shift5)                                       \
1668     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1669         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1670 
1671 /* SBC reg to reg with Post ROR */
1672 #define E_SBC_FROR(dest, src1, src2, shift5)                                                                 \
1673     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1674         (1 << 30) + (1 << 31)
1675 #define E_SBC_FRORS(dest, src1, src2, shift5)                                                               \
1676     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1677         (1 << 29) + (1 << 30) + (1 << 31)
1678 #define E_COND_SBC_FROR(cond, dest, src1, src2, shift5)                                                        \
1679     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1680         (1 << 30) + (1 << 31)
1681 #define E_COND_SBC_FRORS(cond, dest, src1, src2, shift5)                                                      \
1682     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1683         (1 << 29) + (1 << 30) + (1 << 31)
1684 
1685 /* SBC reg to reg and invert result with ROR */
1686 #define E_SBCN_FROR(dest, src1, src2, shift5)                                                                \
1687     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1688         (1 << 29) + (1 << 30) + (1 << 31)
1689 #define E_SBCN_FRORS(dest, src1, src2, shift5)                                                \
1690     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1691         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1692 #define E_COND_SBCN_FROR(cond, dest, src1, src2, shift5)                                                       \
1693     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1694         (1 << 29) + (1 << 30) + (1 << 31)
1695 #define E_COND_SBCN_FRORS(cond, dest, src1, src2, shift5)                                       \
1696     DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1697         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1698 
1699 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1700 /*                                       E_OR Codes */
1701 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1702 
1703 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
1704  */
1705 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
1706 
1707 /* or reg with reg */
1708 #define E_OR(dest, src1, src2)             DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
1709 #define E_ORS(dest, src1, src2)            DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
1710 #define E_COND_OR(cond, dest, src1, src2)  DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
1711 #define E_COND_ORS(cond, dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
1712 
1713 /* or reg with reg and invert result */
1714 #define E_ORN(dest, src1, src2)  DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
1715 #define E_ORNS(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
1716 #define E_COND_ORN(cond, dest, src1, src2) \
1717     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
1718 #define E_COND_ORNS(cond, dest, src1, src2) \
1719     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
1720 
1721 /* or imm12s with reg */
1722 #define E_OR_IMM(dest, src1, imm12s) DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
1723 #define E_OR_IMMS(dest, src1, imm12s) \
1724     DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
1725 #define E_COND_OR_IMM(cond, dest, src1, imm12s) \
1726     DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
1727 #define E_COND_OR_IMMS(cond, dest, src1, imm12s) \
1728     DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
1729 
1730 /* or imm12s with reg and invert result */
1731 #define E_ORN_IMM(dest, src1, imm12s) \
1732     DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1733 #define E_ORN_IMMS(dest, src1, imm12s) \
1734     DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1735 #define E_COND_ORN_IMM(cond, dest, src1, imm12s) \
1736     DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1737 #define E_COND_ORN_IMMS(cond, dest, src1, imm12s) \
1738     DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
1739 
1740 /* OR reg to reg with Post Shift Left */
1741 #define E_OR_LSL(dest, src1, src2, shift5)                                                                   \
1742     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1743         (0 << 30) + (0 << 31)
1744 #define E_OR_LSLS(dest, src1, src2, shift5)                                                                 \
1745     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1746         (0 << 29) + (0 << 30) + (0 << 31)
1747 #define E_COND_OR_LSL(cond, dest, src1, src2, shift5)                                                          \
1748     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1749         (0 << 30) + (0 << 31)
1750 #define E_COND_OR_LSLS(cond, dest, src1, src2, shift5)                                                        \
1751     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1752         (0 << 29) + (0 << 30) + (0 << 31)
1753 
1754 /* OR reg to reg and invert result with Post Shift Left */
1755 #define E_ORN_LSL(dest, src1, src2, shift5)                                                                  \
1756     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1757         (0 << 29) + (0 << 30) + (0 << 31)
1758 #define E_ORN_LSLS(dest, src1, src2, shift5)                                                  \
1759     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1760         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1761 #define E_COND_ORN_LSL(cond, dest, src1, src2, shift5)                                                         \
1762     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1763         (0 << 29) + (0 << 30) + (0 << 31)
1764 #define E_COND_ORN_LSLS(cond, dest, src1, src2, shift5)                                         \
1765     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1766         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
1767 
1768 /* OR reg to reg with Post Shift Right */
1769 #define E_OR_LSR(dest, src1, src2, shift5)                                                                   \
1770     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1771         (1 << 30) + (0 << 31)
1772 #define E_OR_LSRS(dest, src1, src2, shift5)                                                                 \
1773     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1774         (0 << 29) + (1 << 30) + (0 << 31)
1775 #define E_COND_OR_LSR(cond, dest, src1, src2, shift5)                                                          \
1776     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1777         (1 << 30) + (0 << 31)
1778 #define E_COND_OR_LSRS(cond, dest, src1, src2, shift5)                                                        \
1779     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1780         (0 << 29) + (1 << 30) + (0 << 31)
1781 
1782 /* OR reg to reg and invert result with Post Shift Right */
1783 #define E_ORN_LSR(dest, src1, src2, shift5)                                                                  \
1784     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1785         (0 << 29) + (1 << 30) + (0 << 31)
1786 #define E_ORN_LSRS(dest, src1, src2, shift5)                                                  \
1787     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1788         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1789 #define E_COND_ORN_LSR(cond, dest, src1, src2, shift5)                                                         \
1790     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1791         (0 << 29) + (1 << 30) + (0 << 31)
1792 #define E_COND_ORN_LSRS(cond, dest, src1, src2, shift5)                                         \
1793     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1794         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
1795 
1796 /* OR reg to reg with Post Arith Shift Right */
1797 #define E_OR_ASR(dest, src1, src2, shift5)                                                                   \
1798     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1799         (0 << 30) + (0 << 31)
1800 #define E_OR_ASRS(dest, src1, src2, shift5)                                                                 \
1801     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1802         (1 << 29) + (0 << 30) + (0 << 31)
1803 #define E_COND_OR_ASR(cond, dest, src1, src2, shift5)                                                          \
1804     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1805         (0 << 30) + (0 << 31)
1806 #define E_COND_OR_ASRS(cond, dest, src1, src2, shift5)                                                        \
1807     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1808         (1 << 29) + (0 << 30) + (0 << 31)
1809 
1810 /* OR reg to reg and invert result with Post Arith Shift Right */
1811 #define E_ORN_ASR(dest, src1, src2, shift5)                                                                  \
1812     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1813         (1 << 29) + (0 << 30) + (0 << 31)
1814 #define E_ORN_ASRS(dest, src1, src2, shift5)                                                  \
1815     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1816         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1817 #define E_COND_ORN_ASR(cond, dest, src1, src2, shift5)                                                         \
1818     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1819         (1 << 29) + (0 << 30) + (0 << 31)
1820 #define E_COND_ORN_ASRS(cond, dest, src1, src2, shift5)                                         \
1821     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1822         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
1823 
1824 /* OR reg to reg with Post ROR */
1825 #define E_OR_ROR(dest, src1, src2, shift5)                                                                   \
1826     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1827         (1 << 30) + (0 << 31)
1828 #define E_OR_RORS(dest, src1, src2, shift5)                                                                 \
1829     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1830         (1 << 29) + (1 << 30) + (0 << 31)
1831 #define E_COND_OR_ROR(cond, dest, src1, src2, shift5)                                                          \
1832     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1833         (1 << 30) + (0 << 31)
1834 #define E_COND_OR_RORS(cond, dest, src1, src2, shift5)                                                        \
1835     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1836         (1 << 29) + (1 << 30) + (0 << 31)
1837 
1838 /* OR reg to reg and invert result with ROR */
1839 #define E_ORN_ROR(dest, src1, src2, shift5)                                                                  \
1840     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1841         (1 << 29) + (1 << 30) + (0 << 31)
1842 #define E_ORN_RORS(dest, src1, src2, shift5)                                                  \
1843     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1844         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1845 #define E_COND_ORN_ROR(cond, dest, src1, src2, shift5)                                                         \
1846     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1847         (1 << 29) + (1 << 30) + (0 << 31)
1848 #define E_COND_ORN_RORS(cond, dest, src1, src2, shift5)                                         \
1849     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1850         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
1851 /* Flip Endianness and then shift5/Rotate */
1852 
1853 /* OR reg to reg with Flip */
1854 #define E_OR_F(dest, src1, src2)                                                                                    \
1855     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1856         (1 << 31)
1857 #define E_OR_FS(dest, src1, src2)                                                                                  \
1858     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1859         (0 << 30) + (1 << 31)
1860 #define E_COND_OR_F(cond, dest, src1, src2)                                                                           \
1861     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
1862         (1 << 31)
1863 #define E_COND_OR_FS(cond, dest, src1, src2)                                                                         \
1864     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
1865         (0 << 30) + (1 << 31)
1866 
1867 /* OR reg to reg and invert result with Flip */
1868 #define E_ORN_F(dest, src1, src2)                                                                                   \
1869     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1870         (0 << 30) + (1 << 31)
1871 #define E_ORN_FS(dest, src1, src2)                                                                                 \
1872     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1873         (0 << 29) + (0 << 30) + (1 << 31)
1874 #define E_COND_ORN_F(cond, dest, src1, src2)                                                                          \
1875     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
1876         (0 << 30) + (1 << 31)
1877 #define E_COND_ORN_FS(cond, dest, src1, src2)                                                                        \
1878     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
1879         (0 << 29) + (0 << 30) + (1 << 31)
1880 
1881 /* OR reg to reg with Post Shift Left */
1882 #define E_OR_FLSL(dest, src1, src2, shift5)                                                                  \
1883     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1884         (0 << 30) + (1 << 31)
1885 #define E_OR_FLSLS(dest, src1, src2, shift5)                                                                \
1886     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1887         (0 << 29) + (0 << 30) + (1 << 31)
1888 #define E_COND_OR_FLSL(cond, dest, src1, src2, shift5)                                                         \
1889     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1890         (0 << 30) + (1 << 31)
1891 #define E_COND_OR_FLSLS(cond, dest, src1, src2, shift5)                                                       \
1892     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1893         (0 << 29) + (0 << 30) + (1 << 31)
1894 
1895 /* OR reg to reg and invert result with Post Shift Left */
1896 #define E_ORN_FLSL(dest, src1, src2, shift5)                                                                 \
1897     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1898         (0 << 29) + (0 << 30) + (1 << 31)
1899 #define E_ORN_FLSLS(dest, src1, src2, shift5)                                                 \
1900     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1901         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1902 #define E_COND_ORN_FLSL(cond, dest, src1, src2, shift5)                                                        \
1903     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1904         (0 << 29) + (0 << 30) + (1 << 31)
1905 #define E_COND_ORN_FLSLS(cond, dest, src1, src2, shift5)                                        \
1906     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1907         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
1908 
1909 /* OR reg to reg with Post Shift Right */
1910 #define E_OR_FLSR(dest, src1, src2, shift5)                                                                  \
1911     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1912         (1 << 30) + (1 << 31)
1913 #define E_OR_FLSRS(dest, src1, src2, shift5)                                                                \
1914     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1915         (0 << 29) + (1 << 30) + (1 << 31)
1916 #define E_COND_OR_FLSR(cond, dest, src1, src2, shift5)                                                         \
1917     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
1918         (1 << 30) + (1 << 31)
1919 #define E_COND_OR_FLSRS(cond, dest, src1, src2, shift5)                                                       \
1920     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1921         (0 << 29) + (1 << 30) + (1 << 31)
1922 
1923 /* OR reg to reg and invert result with Post Shift Right */
1924 #define E_ORN_FLSR(dest, src1, src2, shift5)                                                                 \
1925     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1926         (0 << 29) + (1 << 30) + (1 << 31)
1927 #define E_ORN_FLSRS(dest, src1, src2, shift5)                                                 \
1928     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1929         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1930 #define E_COND_ORN_FLSR(cond, dest, src1, src2, shift5)                                                        \
1931     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1932         (0 << 29) + (1 << 30) + (1 << 31)
1933 #define E_COND_ORN_FLSRS(cond, dest, src1, src2, shift5)                                        \
1934     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1935         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
1936 
1937 /* OR reg to reg with Post Arith Shift Right */
1938 #define E_OR_FASR(dest, src1, src2, shift5)                                                                  \
1939     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1940         (0 << 30) + (1 << 31)
1941 #define E_OR_FASRS(dest, src1, src2, shift5)                                                                \
1942     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1943         (1 << 29) + (0 << 30) + (1 << 31)
1944 #define E_COND_OR_FASR(cond, dest, src1, src2, shift5)                                                         \
1945     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1946         (0 << 30) + (1 << 31)
1947 #define E_COND_OR_FASRS(cond, dest, src1, src2, shift5)                                                       \
1948     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1949         (1 << 29) + (0 << 30) + (1 << 31)
1950 
1951 /* OR reg to reg and invert result with Post Arith Shift Right */
1952 #define E_ORN_FASR(dest, src1, src2, shift5)                                                                 \
1953     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1954         (1 << 29) + (0 << 30) + (1 << 31)
1955 #define E_ORN_FASRS(dest, src1, src2, shift5)                                                 \
1956     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1957         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1958 #define E_COND_ORN_FASR(cond, dest, src1, src2, shift5)                                                        \
1959     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1960         (1 << 29) + (0 << 30) + (1 << 31)
1961 #define E_COND_ORN_FASRS(cond, dest, src1, src2, shift5)                                        \
1962     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1963         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
1964 
1965 /* OR reg to reg with Post ROR */
1966 #define E_OR_FROR(dest, src1, src2, shift5)                                                                  \
1967     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1968         (1 << 30) + (1 << 31)
1969 #define E_OR_FRORS(dest, src1, src2, shift5)                                                                \
1970     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
1971         (1 << 29) + (1 << 30) + (1 << 31)
1972 #define E_COND_OR_FROR(cond, dest, src1, src2, shift5)                                                         \
1973     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
1974         (1 << 30) + (1 << 31)
1975 #define E_COND_OR_FRORS(cond, dest, src1, src2, shift5)                                                       \
1976     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
1977         (1 << 29) + (1 << 30) + (1 << 31)
1978 
1979 /* OR reg to reg and invert result with ROR */
1980 #define E_ORN_FROR(dest, src1, src2, shift5)                                                                 \
1981     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1982         (1 << 29) + (1 << 30) + (1 << 31)
1983 #define E_ORN_FRORS(dest, src1, src2, shift5)                                                 \
1984     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
1985         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1986 #define E_COND_ORN_FROR(cond, dest, src1, src2, shift5)                                                        \
1987     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
1988         (1 << 29) + (1 << 30) + (1 << 31)
1989 #define E_COND_ORN_FRORS(cond, dest, src1, src2, shift5)                                        \
1990     DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
1991         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
1992 
1993 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1994 /*                                       E_AND Codes */
1995 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
1996 
1997 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
1998  */
1999 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
2000 
2001 /* AND reg with reg */
2002 #define E_AND(dest, src1, src2)            DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
2003 #define E_ANDS(dest, src1, src2)           DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
2004 #define E_COND_AND(cond, dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
2005 #define E_COND_ANDS(cond, dest, src1, src2) \
2006     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
2007 
2008 /* AND reg with reg and invert result */
2009 #define E_ANDN(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
2010 #define E_ANDNS(dest, src1, src2) \
2011     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
2012 #define E_COND_ANDN(cond, dest, src1, src2) \
2013     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
2014 #define E_COND_ANDNS(cond, dest, src1, src2) \
2015     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
2016 
2017 /* AND imm12s with reg */
2018 #define E_AND_IMM(dest, src1, imm12s) DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
2019 #define E_AND_IMMS(dest, src1, imm12s) \
2020     DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
2021 #define E_COND_AND_IMM(cond, dest, src1, imm12s) \
2022     DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
2023 #define E_COND_AND_IMMS(cond, dest, src1, imm12s) \
2024     DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
2025 
2026 /* AND imm12s with reg and invert result */
2027 #define E_ANDN_IMM(dest, src1, imm12s) \
2028     DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2029 #define E_ANDN_IMMS(dest, src1, imm12s) \
2030     DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2031 #define E_COND_ANDN_IMM(cond, dest, src1, imm12s) \
2032     DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2033 #define E_COND_ANDN_IMMS(cond, dest, src1, imm12s) \
2034     DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2035 
2036 /* AND reg to reg with Post Shift Left */
2037 #define E_AND_LSL(dest, src1, src2, shift5)                                                                  \
2038     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2039         (0 << 30) + (0 << 31)
2040 #define E_AND_LSLS(dest, src1, src2, shift5)                                                                \
2041     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2042         (0 << 29) + (0 << 30) + (0 << 31)
2043 #define E_COND_AND_LSL(cond, dest, src1, src2, shift5)                                                         \
2044     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2045         (0 << 30) + (0 << 31)
2046 #define E_COND_AND_LSLS(cond, dest, src1, src2, shift5)                                                       \
2047     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2048         (0 << 29) + (0 << 30) + (0 << 31)
2049 
2050 /* AND reg to reg and invert result with Post Shift Left */
2051 #define E_ANDN_LSL(dest, src1, src2, shift5)                                                                 \
2052     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2053         (0 << 29) + (0 << 30) + (0 << 31)
2054 #define E_ANDN_LSLS(dest, src1, src2, shift5)                                                 \
2055     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2056         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
2057 #define E_COND_ANDN_LSL(cond, dest, src1, src2, shift5)                                                        \
2058     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2059         (0 << 29) + (0 << 30) + (0 << 31)
2060 #define E_COND_ANDN_LSLS(cond, dest, src1, src2, shift5)                                        \
2061     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2062         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
2063 
2064 /* AND reg to reg with Post Shift Right */
2065 #define E_AND_LSR(dest, src1, src2, shift5)                                                                  \
2066     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2067         (1 << 30) + (0 << 31)
2068 #define E_AND_LSRS(dest, src1, src2, shift5)                                                                \
2069     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2070         (0 << 29) + (1 << 30) + (0 << 31)
2071 #define E_COND_AND_LSR(cond, dest, src1, src2, shift5)                                                         \
2072     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2073         (1 << 30) + (0 << 31)
2074 #define E_COND_AND_LSRS(cond, dest, src1, src2, shift5)                                                       \
2075     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2076         (0 << 29) + (1 << 30) + (0 << 31)
2077 
2078 /* AND reg to reg and invert result with Post Shift Right */
2079 #define E_ANDN_LSR(dest, src1, src2, shift5)                                                                 \
2080     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2081         (0 << 29) + (1 << 30) + (0 << 31)
2082 #define E_ANDN_LSRS(dest, src1, src2, shift5)                                                 \
2083     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2084         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
2085 #define E_COND_ANDN_LSR(cond, dest, src1, src2, shift5)                                                        \
2086     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2087         (0 << 29) + (1 << 30) + (0 << 31)
2088 #define E_COND_ANDN_LSRS(cond, dest, src1, src2, shift5)                                        \
2089     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2090         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
2091 
2092 /* AND reg to reg with Post Arith Shift Right */
2093 #define E_AND_ASR(dest, src1, src2, shift5)                                                                  \
2094     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2095         (0 << 30) + (0 << 31)
2096 #define E_AND_ASRS(dest, src1, src2, shift5)                                                                \
2097     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2098         (1 << 29) + (0 << 30) + (0 << 31)
2099 #define E_COND_AND_ASR(cond, dest, src1, src2, shift5)                                                         \
2100     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2101         (0 << 30) + (0 << 31)
2102 #define E_COND_AND_ASRS(cond, dest, src1, src2, shift5)                                                       \
2103     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2104         (1 << 29) + (0 << 30) + (0 << 31)
2105 
2106 /* AND reg to reg and invert result with Post Arith Shift Right */
2107 #define E_ANDN_ASR(dest, src1, src2, shift5)                                                                 \
2108     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2109         (1 << 29) + (0 << 30) + (0 << 31)
2110 #define E_ANDN_ASRS(dest, src1, src2, shift5)                                                 \
2111     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2112         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
2113 #define E_COND_ANDN_ASR(cond, dest, src1, src2, shift5)                                                        \
2114     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2115         (1 << 29) + (0 << 30) + (0 << 31)
2116 #define E_COND_ANDN_ASRS(cond, dest, src1, src2, shift5)                                        \
2117     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2118         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
2119 
2120 /* AND reg to reg with Post ROR */
2121 #define E_AND_ROR(dest, src1, src2, shift5)                                                                  \
2122     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2123         (1 << 30) + (0 << 31)
2124 #define E_AND_RORS(dest, src1, src2, shift5)                                                                \
2125     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2126         (1 << 29) + (1 << 30) + (0 << 31)
2127 #define E_COND_AND_ROR(cond, dest, src1, src2, shift5)                                                         \
2128     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2129         (1 << 30) + (0 << 31)
2130 #define E_COND_AND_RORS(cond, dest, src1, src2, shift5)                                                       \
2131     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2132         (1 << 29) + (1 << 30) + (0 << 31)
2133 
2134 /* AND reg to reg and invert result with ROR */
2135 #define E_ANDN_ROR(dest, src1, src2, shift5)                                                                 \
2136     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2137         (1 << 29) + (1 << 30) + (0 << 31)
2138 #define E_ANDN_RORS(dest, src1, src2, shift5)                                                 \
2139     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2140         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
2141 #define E_COND_ANDN_ROR(cond, dest, src1, src2, shift5)                                                        \
2142     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2143         (1 << 29) + (1 << 30) + (0 << 31)
2144 #define E_COND_ANDN_RORS(cond, dest, src1, src2, shift5)                                        \
2145     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2146         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
2147 
2148 /* Flip Endianness and then shift5/Rotate */
2149 
2150 /* AND reg to reg with Flip */
2151 #define E_AND_F(dest, src1, src2)                                                                                   \
2152     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
2153         (1 << 31)
2154 #define E_AND_FS(dest, src1, src2)                                                                                 \
2155     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
2156         (0 << 30) + (1 << 31)
2157 #define E_COND_AND_F(cond, dest, src1, src2)                                                                          \
2158     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
2159         (1 << 31)
2160 #define E_COND_AND_FS(cond, dest, src1, src2)                                                                        \
2161     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
2162         (0 << 30) + (1 << 31)
2163 
2164 /* AND reg to reg and invert result with Flip */
2165 #define E_ANDN_F(dest, src1, src2)                                                                                  \
2166     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
2167         (0 << 30) + (1 << 31)
2168 #define E_ANDN_FS(dest, src1, src2)                                                                                \
2169     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
2170         (0 << 29) + (0 << 30) + (1 << 31)
2171 #define E_COND_ANDN_F(cond, dest, src1, src2)                                                                         \
2172     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
2173         (0 << 30) + (1 << 31)
2174 #define E_COND_ANDN_FS(cond, dest, src1, src2)                                                                       \
2175     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
2176         (0 << 29) + (0 << 30) + (1 << 31)
2177 
2178 /* AND reg to reg with Post Shift Left */
2179 #define E_AND_FLSL(dest, src1, src2, shift5)                                                                 \
2180     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2181         (0 << 30) + (1 << 31)
2182 #define E_AND_FLSLS(dest, src1, src2, shift5)                                                               \
2183     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2184         (0 << 29) + (0 << 30) + (1 << 31)
2185 #define E_COND_AND_FLSL(cond, dest, src1, src2, shift5)                                                        \
2186     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2187         (0 << 30) + (1 << 31)
2188 #define E_COND_AND_FLSLS(cond, dest, src1, src2, shift5)                                                      \
2189     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2190         (0 << 29) + (0 << 30) + (1 << 31)
2191 
2192 /* AND reg to reg and invert result with Post Shift Left */
2193 #define E_ANDN_FLSL(dest, src1, src2, shift5)                                                                \
2194     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2195         (0 << 29) + (0 << 30) + (1 << 31)
2196 #define E_ANDN_FLSLS(dest, src1, src2, shift5)                                                \
2197     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2198         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
2199 #define E_COND_ANDN_FLSL(cond, dest, src1, src2, shift5)                                                       \
2200     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2201         (0 << 29) + (0 << 30) + (1 << 31)
2202 #define E_COND_ANDN_FLSLS(cond, dest, src1, src2, shift5)                                       \
2203     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2204         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
2205 
2206 /* AND reg to reg with Post Shift Right */
2207 #define E_AND_FLSR(dest, src1, src2, shift5)                                                                 \
2208     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2209         (1 << 30) + (1 << 31)
2210 #define E_AND_FLSRS(dest, src1, src2, shift5)                                                               \
2211     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2212         (0 << 29) + (1 << 30) + (1 << 31)
2213 #define E_COND_AND_FLSR(cond, dest, src1, src2, shift5)                                                        \
2214     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2215         (1 << 30) + (1 << 31)
2216 #define E_COND_AND_FLSRS(cond, dest, src1, src2, shift5)                                                      \
2217     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2218         (0 << 29) + (1 << 30) + (1 << 31)
2219 
2220 /* AND reg to reg and invert result with Post Shift Right */
2221 #define E_ANDN_FLSR(dest, src1, src2, shift5)                                                                \
2222     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2223         (0 << 29) + (1 << 30) + (1 << 31)
2224 #define E_ANDN_FLSRS(dest, src1, src2, shift5)                                                \
2225     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2226         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
2227 #define E_COND_ANDN_FLSR(cond, dest, src1, src2, shift5)                                                       \
2228     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2229         (0 << 29) + (1 << 30) + (1 << 31)
2230 #define E_COND_ANDN_FLSRS(cond, dest, src1, src2, shift5)                                       \
2231     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2232         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
2233 
2234 /* AND reg to reg with Post Arith Shift Right */
2235 #define E_AND_FASR(dest, src1, src2, shift5)                                                                 \
2236     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2237         (0 << 30) + (1 << 31)
2238 #define E_AND_FASRS(dest, src1, src2, shift5)                                                               \
2239     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2240         (1 << 29) + (0 << 30) + (1 << 31)
2241 #define E_COND_AND_FASR(cond, dest, src1, src2, shift5)                                                        \
2242     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2243         (0 << 30) + (1 << 31)
2244 #define E_COND_AND_FASRS(cond, dest, src1, src2, shift5)                                                      \
2245     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2246         (1 << 29) + (0 << 30) + (1 << 31)
2247 
2248 /* AND reg to reg and invert result with Post Arith Shift Right */
2249 #define E_ANDN_FASR(dest, src1, src2, shift5)                                                                \
2250     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2251         (1 << 29) + (0 << 30) + (1 << 31)
2252 #define E_ANDN_FASRS(dest, src1, src2, shift5)                                                \
2253     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2254         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
2255 #define E_COND_ANDN_FASR(cond, dest, src1, src2, shift5)                                                       \
2256     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2257         (1 << 29) + (0 << 30) + (1 << 31)
2258 #define E_COND_ANDN_FASRS(cond, dest, src1, src2, shift5)                                       \
2259     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2260         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
2261 
2262 /* AND reg to reg with Post ROR */
2263 #define E_AND_FROR(dest, src1, src2, shift5)                                                                 \
2264     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2265         (1 << 30) + (1 << 31)
2266 #define E_AND_FRORS(dest, src1, src2, shift5)                                                               \
2267     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2268         (1 << 29) + (1 << 30) + (1 << 31)
2269 #define E_COND_AND_FROR(cond, dest, src1, src2, shift5)                                                        \
2270     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2271         (1 << 30) + (1 << 31)
2272 #define E_COND_AND_FRORS(cond, dest, src1, src2, shift5)                                                      \
2273     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2274         (1 << 29) + (1 << 30) + (1 << 31)
2275 
2276 /* AND reg to reg and invert result with ROR */
2277 #define E_ANDN_FROR(dest, src1, src2, shift5)                                                                \
2278     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2279         (1 << 29) + (1 << 30) + (1 << 31)
2280 #define E_ANDN_FRORS(dest, src1, src2, shift5)                                                \
2281     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2282         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
2283 #define E_COND_ANDN_FROR(cond, dest, src1, src2, shift5)                                                       \
2284     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2285         (1 << 29) + (1 << 30) + (1 << 31)
2286 #define E_COND_ANDN_FRORS(cond, dest, src1, src2, shift5)                                       \
2287     DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2288         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
2289 
2290 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2291 /*                                       E_XOR Codes */
2292 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2293 
2294 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
2295  */
2296 /*                                                         Imm            Use_Imm      Invert Result    Shift Result */
2297 
2298 /* XOR reg with reg */
2299 #define E_XOR(dest, src1, src2)            DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5)
2300 #define E_XORS(dest, src1, src2)           DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5)
2301 #define E_COND_XOR(cond, dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5)
2302 #define E_COND_XORS(cond, dest, src1, src2) \
2303     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5)
2304 
2305 /* XOR reg with reg XOR invert result */
2306 #define E_XORN(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19)
2307 #define E_XORNS(dest, src1, src2) \
2308     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19)
2309 #define E_COND_XORN(cond, dest, src1, src2) \
2310     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19)
2311 #define E_COND_XORNS(cond, dest, src1, src2) \
2312     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19)
2313 
2314 /* XOR imm12s with reg */
2315 #define E_XOR_IMM(dest, src1, imm12s) DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18)
2316 #define E_XOR_IMMS(dest, src1, imm12s) \
2317     DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18)
2318 #define E_COND_XOR_IMM(cond, dest, src1, imm12s) \
2319     DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18)
2320 #define E_COND_XOR_IMMS(cond, dest, src1, imm12s) \
2321     DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18)
2322 
2323 /* XOR imm12s with reg XOR invert result */
2324 #define E_XORN_IMM(dest, src1, imm12s) \
2325     DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2326 #define E_XORN_IMMS(dest, src1, imm12s) \
2327     DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2328 #define E_COND_XORN_IMM(cond, dest, src1, imm12s) \
2329     DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2330 #define E_COND_XORN_IMMS(cond, dest, src1, imm12s) \
2331     DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19)
2332 
2333 /* XOR reg to reg with Post Shift Left */
2334 #define E_XOR_LSL(dest, src1, src2, shift5)                                                                  \
2335     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2336         (0 << 30) + (0 << 31)
2337 #define E_XOR_LSLS(dest, src1, src2, shift5)                                                                \
2338     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2339         (0 << 29) + (0 << 30) + (0 << 31)
2340 #define E_COND_XOR_LSL(cond, dest, src1, src2, shift5)                                                         \
2341     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2342         (0 << 30) + (0 << 31)
2343 #define E_COND_XOR_LSLS(cond, dest, src1, src2, shift5)                                                       \
2344     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2345         (0 << 29) + (0 << 30) + (0 << 31)
2346 
2347 /* XOR reg to reg XOR invert result with Post Shift Left */
2348 #define E_XORN_LSL(dest, src1, src2, shift5)                                                                 \
2349     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2350         (0 << 29) + (0 << 30) + (0 << 31)
2351 #define E_XORN_LSLS(dest, src1, src2, shift5)                                                 \
2352     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2353         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
2354 #define E_COND_XORN_LSL(cond, dest, src1, src2, shift5)                                                        \
2355     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2356         (0 << 29) + (0 << 30) + (0 << 31)
2357 #define E_COND_XORN_LSLS(cond, dest, src1, src2, shift5)                                        \
2358     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2359         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31)
2360 
2361 /* XOR reg to reg with Post Shift Right */
2362 #define E_XOR_LSR(dest, src1, src2, shift5)                                                                  \
2363     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2364         (1 << 30) + (0 << 31)
2365 #define E_XOR_LSRS(dest, src1, src2, shift5)                                                                \
2366     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2367         (0 << 29) + (1 << 30) + (0 << 31)
2368 #define E_COND_XOR_LSR(cond, dest, src1, src2, shift5)                                                         \
2369     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2370         (1 << 30) + (0 << 31)
2371 #define E_COND_XOR_LSRS(cond, dest, src1, src2, shift5)                                                       \
2372     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2373         (0 << 29) + (1 << 30) + (0 << 31)
2374 
2375 /* XOR reg to reg XOR invert result with Post Shift Right */
2376 #define E_XORN_LSR(dest, src1, src2, shift5)                                                                 \
2377     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2378         (0 << 29) + (1 << 30) + (0 << 31)
2379 #define E_XORN_LSRS(dest, src1, src2, shift5)                                                 \
2380     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2381         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
2382 #define E_COND_XORN_LSR(cond, dest, src1, src2, shift5)                                                        \
2383     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2384         (0 << 29) + (1 << 30) + (0 << 31)
2385 #define E_COND_XORN_LSRS(cond, dest, src1, src2, shift5)                                        \
2386     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2387         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31)
2388 
2389 /* XOR reg to reg with Post Arith Shift Right */
2390 #define E_XOR_ASR(dest, src1, src2, shift5)                                                                  \
2391     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2392         (0 << 30) + (0 << 31)
2393 #define E_XOR_ASRS(dest, src1, src2, shift5)                                                                \
2394     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2395         (1 << 29) + (0 << 30) + (0 << 31)
2396 #define E_COND_XOR_ASR(cond, dest, src1, src2, shift5)                                                         \
2397     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2398         (0 << 30) + (0 << 31)
2399 #define E_COND_XOR_ASRS(cond, dest, src1, src2, shift5)                                                       \
2400     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2401         (1 << 29) + (0 << 30) + (0 << 31)
2402 
2403 /* XOR reg to reg XOR invert result with Post Arith Shift Right */
2404 #define E_XORN_ASR(dest, src1, src2, shift5)                                                                 \
2405     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2406         (1 << 29) + (0 << 30) + (0 << 31)
2407 #define E_XORN_ASRS(dest, src1, src2, shift5)                                                 \
2408     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2409         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
2410 #define E_COND_XORN_ASR(cond, dest, src1, src2, shift5)                                                        \
2411     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2412         (1 << 29) + (0 << 30) + (0 << 31)
2413 #define E_COND_XORN_ASRS(cond, dest, src1, src2, shift5)                                        \
2414     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2415         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31)
2416 
2417 /* XOR reg to reg with Post ROR */
2418 #define E_XOR_ROR(dest, src1, src2, shift5)                                                                  \
2419     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2420         (1 << 30) + (0 << 31)
2421 #define E_XOR_RORS(dest, src1, src2, shift5)                                                                \
2422     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2423         (1 << 29) + (1 << 30) + (0 << 31)
2424 #define E_COND_XOR_ROR(cond, dest, src1, src2, shift5)                                                         \
2425     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2426         (1 << 30) + (0 << 31)
2427 #define E_COND_XOR_RORS(cond, dest, src1, src2, shift5)                                                       \
2428     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2429         (1 << 29) + (1 << 30) + (0 << 31)
2430 
2431 /* XOR reg to reg XOR invert result with ROR */
2432 #define E_XORN_ROR(dest, src1, src2, shift5)                                                                 \
2433     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2434         (1 << 29) + (1 << 30) + (0 << 31)
2435 #define E_XORN_RORS(dest, src1, src2, shift5)                                                 \
2436     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2437         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
2438 #define E_COND_XORN_ROR(cond, dest, src1, src2, shift5)                                                        \
2439     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2440         (1 << 29) + (1 << 30) + (0 << 31)
2441 #define E_COND_XORN_RORS(cond, dest, src1, src2, shift5)                                        \
2442     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2443         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31)
2444 
2445 /* Flip Endianness and then shift5/Rotate */
2446 
2447 /* XOR reg to reg with Flip */
2448 #define E_XOR_F(dest, src1, src2)                                                                                   \
2449     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
2450         (1 << 31)
2451 #define E_XOR_FS(dest, src1, src2)                                                                                 \
2452     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
2453         (0 << 30) + (1 << 31)
2454 #define E_COND_XOR_F(cond, dest, src1, src2)                                                                          \
2455     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \
2456         (1 << 31)
2457 #define E_COND_XOR_FS(cond, dest, src1, src2)                                                                        \
2458     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \
2459         (0 << 30) + (1 << 31)
2460 
2461 /* XOR reg to reg and invert result with Flip */
2462 #define E_XORN_F(dest, src1, src2)                                                                                  \
2463     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
2464         (0 << 30) + (1 << 31)
2465 #define E_XORN_FS(dest, src1, src2)                                                                                \
2466     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
2467         (0 << 29) + (0 << 30) + (1 << 31)
2468 #define E_COND_XORN_F(cond, dest, src1, src2)                                                                         \
2469     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \
2470         (0 << 30) + (1 << 31)
2471 #define E_COND_XORN_FS(cond, dest, src1, src2)                                                                       \
2472     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \
2473         (0 << 29) + (0 << 30) + (1 << 31)
2474 
2475 /* XOR reg to reg with Post Shift Left */
2476 #define E_XOR_FLSL(dest, src1, src2, shift5)                                                                 \
2477     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2478         (0 << 30) + (1 << 31)
2479 #define E_XOR_FLSLS(dest, src1, src2, shift5)                                                               \
2480     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2481         (0 << 29) + (0 << 30) + (1 << 31)
2482 #define E_COND_XOR_FLSL(cond, dest, src1, src2, shift5)                                                        \
2483     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2484         (0 << 30) + (1 << 31)
2485 #define E_COND_XOR_FLSLS(cond, dest, src1, src2, shift5)                                                      \
2486     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2487         (0 << 29) + (0 << 30) + (1 << 31)
2488 
2489 /* XOR reg to reg XOR invert result with Post Shift Left */
2490 #define E_XORN_FLSL(dest, src1, src2, shift5)                                                                \
2491     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2492         (0 << 29) + (0 << 30) + (1 << 31)
2493 #define E_XORN_FLSLS(dest, src1, src2, shift5)                                                \
2494     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2495         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
2496 #define E_COND_XORN_FLSL(cond, dest, src1, src2, shift5)                                                       \
2497     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2498         (0 << 29) + (0 << 30) + (1 << 31)
2499 #define E_COND_XORN_FLSLS(cond, dest, src1, src2, shift5)                                       \
2500     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2501         ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31)
2502 
2503 /* XOR reg to reg with Post Shift Right */
2504 #define E_XOR_FLSR(dest, src1, src2, shift5)                                                                 \
2505     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2506         (1 << 30) + (1 << 31)
2507 #define E_XOR_FLSRS(dest, src1, src2, shift5)                                                               \
2508     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2509         (0 << 29) + (1 << 30) + (1 << 31)
2510 #define E_COND_XOR_FLSR(cond, dest, src1, src2, shift5)                                                        \
2511     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2512         (1 << 30) + (1 << 31)
2513 #define E_COND_XOR_FLSRS(cond, dest, src1, src2, shift5)                                                      \
2514     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2515         (0 << 29) + (1 << 30) + (1 << 31)
2516 
2517 /* XOR reg to reg XOR invert result with Post Shift Right */
2518 #define E_XORN_FLSR(dest, src1, src2, shift5)                                                                \
2519     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2520         (0 << 29) + (1 << 30) + (1 << 31)
2521 #define E_XORN_FLSRS(dest, src1, src2, shift5)                                                \
2522     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2523         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
2524 #define E_COND_XORN_FLSR(cond, dest, src1, src2, shift5)                                                       \
2525     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2526         (0 << 29) + (1 << 30) + (1 << 31)
2527 #define E_COND_XORN_FLSRS(cond, dest, src1, src2, shift5)                                       \
2528     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2529         ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31)
2530 
2531 /* XOR reg to reg with Post Arith Shift Right */
2532 #define E_XOR_FASR(dest, src1, src2, shift5)                                                                 \
2533     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2534         (0 << 30) + (1 << 31)
2535 #define E_XOR_FASRS(dest, src1, src2, shift5)                                                               \
2536     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2537         (1 << 29) + (0 << 30) + (1 << 31)
2538 #define E_COND_XOR_FASR(cond, dest, src1, src2, shift5)                                                        \
2539     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2540         (0 << 30) + (1 << 31)
2541 #define E_COND_XOR_FASRS(cond, dest, src1, src2, shift5)                                                      \
2542     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2543         (1 << 29) + (0 << 30) + (1 << 31)
2544 
2545 /* XOR reg to reg XOR invert result with Post Arith Shift Right */
2546 #define E_XORN_FASR(dest, src1, src2, shift5)                                                                \
2547     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2548         (1 << 29) + (0 << 30) + (1 << 31)
2549 #define E_XORN_FASRS(dest, src1, src2, shift5)                                                \
2550     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2551         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
2552 #define E_COND_XORN_FASR(cond, dest, src1, src2, shift5)                                                       \
2553     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2554         (1 << 29) + (0 << 30) + (1 << 31)
2555 #define E_COND_XORN_FASRS(cond, dest, src1, src2, shift5)                                       \
2556     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2557         ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31)
2558 
2559 /* XOR reg to reg with Post ROR */
2560 #define E_XOR_FROR(dest, src1, src2, shift5)                                                                 \
2561     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2562         (1 << 30) + (1 << 31)
2563 #define E_XOR_FRORS(dest, src1, src2, shift5)                                                               \
2564     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2565         (1 << 29) + (1 << 30) + (1 << 31)
2566 #define E_COND_XOR_FROR(cond, dest, src1, src2, shift5)                                                        \
2567     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \
2568         (1 << 30) + (1 << 31)
2569 #define E_COND_XOR_FRORS(cond, dest, src1, src2, shift5)                                                      \
2570     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2571         (1 << 29) + (1 << 30) + (1 << 31)
2572 
2573 /* XOR reg to reg XOR invert result with ROR */
2574 #define E_XORN_FROR(dest, src1, src2, shift5)                                                                \
2575     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2576         (1 << 29) + (1 << 30) + (1 << 31)
2577 #define E_XORN_FRORS(dest, src1, src2, shift5)                                                \
2578     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \
2579         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
2580 #define E_COND_XORN_FROR(cond, dest, src1, src2, shift5)                                                       \
2581     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \
2582         (1 << 29) + (1 << 30) + (1 << 31)
2583 #define E_COND_XORN_FRORS(cond, dest, src1, src2, shift5)                                       \
2584     DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \
2585         ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31)
2586 
2587 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2588 /*                                       E_Shift Codes */
2589 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2590 
2591 /*                                                         opcode      Dest            Src1              r2shift SFlag
2592  */
2593 /*                                                         Cond         Imm                    Extra Operation */
2594 /*                                                         Left/Right   Shift/Rotate */
2595 
2596 /* Logical Shift */
2597 #define E_LSL(dest, r2shift, shift5)                                                                         \
2598     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2599         (0 << 19) + (0 << 18)
2600 #define E_LSR(dest, r2shift, shift5)                                                                         \
2601     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2602         (1 << 19) + (0 << 18)
2603 /* Logical Shift and Set Flag */
2604 #define E_LSLS(dest, r2shift, shift5)                                                                        \
2605     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2606         (0 << 19) + (0 << 18)
2607 #define E_LSRS(dest, r2shift, shift5)                                                                        \
2608     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2609         (1 << 19) + (0 << 18)
2610 
2611 /* Logical Shift and then AND */
2612 #define E_LSL_AND(dest, roperand, r2shift, shift5)                                                                  \
2613     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2614         (1 << 29) + (0 << 19) + (0 << 18)
2615 #define E_LSR_AND(dest, roperand, r2shift, shift5)                                                                  \
2616     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2617         (1 << 29) + (1 << 19) + (0 << 18)
2618 /* Logical Shift and Set Flag then AND */
2619 #define E_LSL_ANDS(dest, roperand, r2shift, shift5)                                                                 \
2620     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2621         (1 << 29) + (0 << 19) + (0 << 18)
2622 #define E_LSR_ANDS(dest, roperand, r2shift, shift5)                                                                 \
2623     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2624         (1 << 29) + (1 << 19) + (0 << 18)
2625 
2626 /* Logical Shift and then OR */
2627 #define E_LSL_OR(dest, roperand, r2shift, shift5)                                                                   \
2628     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2629         (2 << 29) + (0 << 19) + (0 << 18)
2630 #define E_LSR_OR(dest, roperand, r2shift, shift5)                                                                   \
2631     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2632         (2 << 29) + (1 << 19) + (0 << 18)
2633 /* Logical Shift and Set Flag then OR */
2634 #define E_LSL_ORS(dest, roperand, r2shift, shift5)                                                                  \
2635     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2636         (2 << 29) + (0 << 19) + (0 << 18)
2637 #define E_LSR_ORS(dest, roperand, r2shift, shift5)                                                                  \
2638     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2639         (2 << 29) + (1 << 19) + (0 << 18)
2640 
2641 /* Logical Shift and then XOR */
2642 #define E_LSL_XOR(dest, roperand, r2shift, shift5)                                                                  \
2643     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2644         (3 << 29) + (0 << 19) + (0 << 18)
2645 #define E_LSR_XOR(dest, roperand, r2shift, shift5)                                                                  \
2646     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2647         (3 << 29) + (1 << 19) + (0 << 18)
2648 /* Logical Shift and Set Flag then XOR */
2649 #define E_LSL_XORS(dest, roperand, r2shift, shift5)                                                                 \
2650     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2651         (3 << 29) + (0 << 19) + (0 << 18)
2652 #define E_LSR_XORS(dest, roperand, r2shift, shift5)                                                                 \
2653     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2654         (3 << 29) + (1 << 19) + (0 << 18)
2655 
2656 /* Logical Shift and then ADD */
2657 #define E_LSL_ADD(dest, roperand, r2shift, shift5)                                                                  \
2658     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2659         (4 << 29) + (0 << 19) + (0 << 18)
2660 #define E_LSR_ADD(dest, roperand, r2shift, shift5)                                                                  \
2661     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2662         (4 << 29) + (1 << 19) + (0 << 18)
2663 /* Logical Shift and Set Flag then ADD */
2664 #define E_LSL_ADDS(dest, roperand, r2shift, shift5)                                                                 \
2665     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2666         (4 << 29) + (0 << 19) + (0 << 18)
2667 #define E_LSR_ADDS(dest, roperand, r2shift, shift5)                                                                 \
2668     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2669         (4 << 29) + (1 << 19) + (0 << 18)
2670 
2671 /* Logical Shift and then SUB */
2672 #define E_LSL_SUB(dest, roperand, r2shift, shift5)                                                                  \
2673     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2674         (5 << 29) + (0 << 19) + (0 << 18)
2675 #define E_LSR_SUB(dest, roperand, r2shift, shift5)                                                                  \
2676     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2677         (5 << 29) + (1 << 19) + (0 << 18)
2678 /* Logical Shift and Set Flag then SUB */
2679 #define E_LSL_SUBS(dest, roperand, r2shift, shift5)                                                                 \
2680     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2681         (5 << 29) + (0 << 19) + (0 << 18)
2682 #define E_LSR_SUBS(dest, roperand, r2shift, shift5)                                                                 \
2683     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2684         (5 << 29) + (1 << 19) + (0 << 18)
2685 
2686 /* Logical Shift and then ADC */
2687 #define E_LSL_ADC(dest, roperand, r2shift, shift5)                                                                  \
2688     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2689         (6 << 29) + (0 << 19) + (0 << 18)
2690 #define E_LSR_ADC(dest, roperand, r2shift, shift5)                                                                  \
2691     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2692         (6 << 29) + (1 << 19) + (0 << 18)
2693 /* Logical Shift and Set Flag then ADC */
2694 #define E_LSL_ADCS(dest, roperand, r2shift, shift5)                                                                 \
2695     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2696         (6 << 29) + (0 << 19) + (0 << 18)
2697 #define E_LSR_ADCS(dest, roperand, r2shift, shift5)                                                                 \
2698     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2699         (6 << 29) + (1 << 19) + (0 << 18)
2700 
2701 /* Logical Shift and then SBC */
2702 #define E_LSL_SBC(dest, roperand, r2shift, shift5)                                                                  \
2703     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2704         (7 << 29) + (0 << 19) + (0 << 18)
2705 #define E_LSR_SBC(dest, roperand, r2shift, shift5)                                                                  \
2706     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2707         (7 << 29) + (1 << 19) + (0 << 18)
2708 /* Logical Shift and Set Flag then SBC */
2709 #define E_LSL_SBCS(dest, roperand, r2shift, shift5)                                                                 \
2710     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2711         (7 << 29) + (0 << 19) + (0 << 18)
2712 #define E_LSR_SBCS(dest, roperand, r2shift, shift5)                                                                 \
2713     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2714         (7 << 29) + (1 << 19) + (0 << 18)
2715 
2716 /* Conditional */
2717 /* Logical Shift */
2718 #define E_COND_LSL(cond, dest, r2shift, shift5)                                                                \
2719     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2720         (0 << 19) + (0 << 18)
2721 #define E_COND_LSR(cond, dest, r2shift, shift5)                                                                \
2722     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2723         (1 << 19) + (0 << 18)
2724 /* Logical Shift and Set Flag */
2725 #define E_COND_LSLS(cond, dest, r2shift, shift5)                                                               \
2726     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2727         (0 << 19) + (0 << 18)
2728 #define E_COND_LSRS(cond, dest, r2shift, shift5)                                                               \
2729     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2730         (1 << 19) + (0 << 18)
2731 
2732 /* Logical Shift and then AND */
2733 #define E_COND_LSL_AND(cond, dest, roperand, r2shift, shift5)                                                         \
2734     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2735         (1 << 29) + (0 << 19) + (0 << 18)
2736 #define E_COND_LSR_AND(cond, dest, roperand, r2shift, shift5)                                                         \
2737     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2738         (1 << 29) + (1 << 19) + (0 << 18)
2739 /* Logical Shift and Set Flag then AND */
2740 #define E_COND_LSL_ANDS(cond, dest, roperand, r2shift, shift5)                                                        \
2741     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2742         (1 << 29) + (0 << 19) + (0 << 18)
2743 #define E_COND_LSR_ANDS(cond, dest, roperand, r2shift, shift5)                                                        \
2744     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2745         (1 << 29) + (1 << 19) + (0 << 18)
2746 
2747 /* Logical Shift and then OR */
2748 #define E_COND_LSL_OR(cond, dest, roperand, r2shift, shift5)                                                          \
2749     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2750         (2 << 29) + (0 << 19) + (0 << 18)
2751 #define E_COND_LSR_OR(cond, dest, roperand, r2shift, shift5)                                                          \
2752     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2753         (2 << 29) + (1 << 19) + (0 << 18)
2754 /* Logical Shift and Set Flag then OR */
2755 #define E_COND_LSL_ORS(cond, dest, roperand, r2shift, shift5)                                                         \
2756     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2757         (2 << 29) + (0 << 19) + (0 << 18)
2758 #define E_COND_LSR_ORS(cond, dest, roperand, r2shift, shift5)                                                         \
2759     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2760         (2 << 29) + (1 << 19) + (0 << 18)
2761 
2762 /* Logical Shift and then XOR */
2763 #define E_COND_LSL_XOR(cond, dest, roperand, r2shift, shift5)                                                         \
2764     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2765         (3 << 29) + (0 << 19) + (0 << 18)
2766 #define E_COND_LSR_XOR(cond, dest, roperand, r2shift, shift5)                                                         \
2767     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2768         (3 << 29) + (1 << 19) + (0 << 18)
2769 /* Logical Shift and Set Flag then XOR */
2770 #define E_COND_LSL_XORS(cond, dest, roperand, r2shift, shift5)                                                        \
2771     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2772         (3 << 29) + (0 << 19) + (0 << 18)
2773 #define E_COND_LSR_XORS(cond, dest, roperand, r2shift, shift5)                                                        \
2774     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2775         (3 << 29) + (1 << 19) + (0 << 18)
2776 
2777 /* Logical Shift and then ADD */
2778 #define E_COND_LSL_ADD(cond, dest, roperand, r2shift, shift5)                                                         \
2779     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2780         (4 << 29) + (0 << 19) + (0 << 18)
2781 #define E_COND_LSR_ADD(cond, dest, roperand, r2shift, shift5)                                                         \
2782     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2783         (4 << 29) + (1 << 19) + (0 << 18)
2784 /* Logical Shift and Set Flag then ADD */
2785 #define E_COND_LSL_ADDS(cond, dest, roperand, r2shift, shift5)                                                        \
2786     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2787         (4 << 29) + (0 << 19) + (0 << 18)
2788 #define E_COND_LSR_ADDS(cond, dest, roperand, r2shift, shift5)                                                        \
2789     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2790         (4 << 29) + (1 << 19) + (0 << 18)
2791 
2792 /* Logical Shift and then SUB */
2793 #define E_COND_LSL_SUB(cond, dest, roperand, r2shift, shift5)                                                         \
2794     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2795         (5 << 29) + (0 << 19) + (0 << 18)
2796 #define E_COND_LSR_SUB(cond, dest, roperand, r2shift, shift5)                                                         \
2797     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2798         (5 << 29) + (1 << 19) + (0 << 18)
2799 /* Logical Shift and Set Flag then SUB */
2800 #define E_COND_LSL_SUBS(cond, dest, roperand, r2shift, shift5)                                                        \
2801     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2802         (5 << 29) + (0 << 19) + (0 << 18)
2803 #define E_COND_LSR_SUBS(cond, dest, roperand, r2shift, shift5)                                                        \
2804     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2805         (5 << 29) + (1 << 19) + (0 << 18)
2806 
2807 /* Logical Shift and then ADC */
2808 #define E_COND_LSL_ADC(cond, dest, roperand, r2shift, shift5)                                                         \
2809     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2810         (6 << 29) + (0 << 19) + (0 << 18)
2811 #define E_COND_LSR_ADC(cond, dest, roperand, r2shift, shift5)                                                         \
2812     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2813         (6 << 29) + (1 << 19) + (0 << 18)
2814 /* Logical Shift and Set Flag then ADC */
2815 #define E_COND_LSL_ADCS(cond, dest, roperand, r2shift, shift5)                                                        \
2816     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2817         (6 << 29) + (0 << 19) + (0 << 18)
2818 #define E_COND_LSR_ADCS(cond, dest, roperand, r2shift, shift5)                                                        \
2819     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2820         (6 << 29) + (1 << 19) + (0 << 18)
2821 
2822 /* Logical Shift and then SBC */
2823 #define E_COND_LSL_SBC(cond, dest, roperand, r2shift, shift5)                                                         \
2824     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2825         (7 << 29) + (0 << 19) + (0 << 18)
2826 #define E_COND_LSR_SBC(cond, dest, roperand, r2shift, shift5)                                                         \
2827     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2828         (7 << 29) + (1 << 19) + (0 << 18)
2829 /* Logical Shift and Set Flag then SBC */
2830 #define E_COND_LSL_SBCS(cond, dest, roperand, r2shift, shift5)                                                        \
2831     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2832         (7 << 29) + (0 << 19) + (0 << 18)
2833 #define E_COND_LSR_SBCS(cond, dest, roperand, r2shift, shift5)                                                        \
2834     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2835         (7 << 29) + (1 << 19) + (0 << 18)
2836 
2837 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2838 /*                                       E_ROTATE Codes */
2839 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2840 
2841 /*                                                         opcode      Dest            Src1              r2shift SFlag
2842  */
2843 /*                                                         Cond         Imm                   Extra Operation Left/Right
2844  */
2845 /*                                                         Shift/Rotate */
2846 
2847 /* Rotate */
2848 #define E_ROR(dest, r2shift, shift5)                                                                         \
2849     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2850         (1 << 19) + (1 << 18)
2851 /* Rotate and Set Flag */
2852 #define E_RORS(dest, r2shift, shift5)                                                                        \
2853     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2854         (1 << 19) + (1 << 18)
2855 
2856 /* Rotate and then AND */
2857 #define E_ROR_AND(dest, roperand, r2shift, shift5)                                                                  \
2858     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2859         (1 << 29) + (1 << 19) + (1 << 18)
2860 /* Rotate and Set Flag then AND */
2861 #define E_ROR_ANDS(dest, roperand, r2shift, shift5)                                                                 \
2862     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2863         (1 << 29) + (1 << 19) + (1 << 18)
2864 
2865 /* Rotate and then OR */
2866 #define E_ROR_OR(dest, roperand, r2shift, shift5)                                                                   \
2867     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2868         (2 << 29) + (1 << 19) + (1 << 18)
2869 /* Rotate and Set Flag then OR */
2870 #define E_ROR_ORS(dest, roperand, r2shift, shift5)                                                                  \
2871     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2872         (2 << 29) + (1 << 19) + (1 << 18)
2873 
2874 /* Rotate and then XOR */
2875 #define E_ROR_XOR(dest, roperand, r2shift, shift5)                                                                  \
2876     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2877         (3 << 29) + (1 << 19) + (1 << 18)
2878 /* Rotate and Set Flag then XOR */
2879 #define E_ROR_XORS(dest, roperand, r2shift, shift5)                                                                 \
2880     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2881         (3 << 29) + (1 << 19) + (1 << 18)
2882 
2883 /* Rotate and then ADD */
2884 #define E_ROR_ADD(dest, roperand, r2shift, shift5)                                                                  \
2885     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2886         (4 << 29) + (1 << 19) + (1 << 18)
2887 /* Rotate and Set Flag then ADD */
2888 #define E_ROR_ADDS(dest, roperand, r2shift, shift5)                                                                 \
2889     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2890         (4 << 29) + (1 << 19) + (1 << 18)
2891 
2892 /* Rotate and then SUB */
2893 #define E_ROR_SUB(dest, roperand, r2shift, shift5)                                                                  \
2894     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2895         (5 << 29) + (1 << 19) + (1 << 18)
2896 /* Rotate and Set Flag then SUB */
2897 #define E_ROR_SUBS(dest, roperand, r2shift, shift5)                                                                 \
2898     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2899         (5 << 29) + (1 << 19) + (1 << 18)
2900 
2901 /* Rotate and then ADC */
2902 #define E_ROR_ADC(dest, roperand, r2shift, shift5)                                                                  \
2903     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2904         (6 << 29) + (1 << 19) + (1 << 18)
2905 /* Rotate and Set Flag then ADC */
2906 #define E_ROR_ADCS(dest, roperand, r2shift, shift5)                                                                 \
2907     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2908         (6 << 29) + (1 << 19) + (1 << 18)
2909 
2910 /* Rotate and then SBC */
2911 #define E_ROR_SBC(dest, roperand, r2shift, shift5)                                                                  \
2912     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2913         (7 << 29) + (1 << 19) + (1 << 18)
2914 /* Rotate and Set Flag then SBC */
2915 #define E_ROR_SBCS(dest, roperand, r2shift, shift5)                                                                 \
2916     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
2917         (7 << 29) + (1 << 19) + (1 << 18)
2918 
2919 /* Conditional */
2920 /* Rotate */
2921 #define E_COND_ROR(cond, dest, r2shift, shift5)                                                                \
2922     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2923         (1 << 19) + (1 << 18)
2924 /* Rotate and Set Flag */
2925 #define E_COND_RORS(cond, dest, r2shift, shift5)                                                               \
2926     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
2927         (1 << 19) + (1 << 18)
2928 
2929 /* Rotate and then AND */
2930 #define E_COND_ROR_AND(cond, dest, roperand, r2shift, shift5)                                                         \
2931     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2932         (1 << 29) + (1 << 19) + (1 << 18)
2933 /* Rotate and Set Flag then AND */
2934 #define E_COND_ROR_ANDS(cond, dest, roperand, r2shift, shift5)                                                        \
2935     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2936         (1 << 29) + (1 << 19) + (1 << 18)
2937 
2938 /* Rotate and then OR */
2939 #define E_COND_ROR_OR(cond, dest, roperand, r2shift, shift5)                                                          \
2940     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2941         (2 << 29) + (1 << 19) + (1 << 18)
2942 /* Rotate and Set Flag then OR */
2943 #define E_COND_ROR_ORS(cond, dest, roperand, r2shift, shift5)                                                         \
2944     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2945         (2 << 29) + (1 << 19) + (1 << 18)
2946 
2947 /* Rotate and then XOR */
2948 #define E_COND_ROR_XOR(cond, dest, roperand, r2shift, shift5)                                                         \
2949     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2950         (3 << 29) + (1 << 19) + (1 << 18)
2951 /* Rotate and Set Flag then XOR */
2952 #define E_COND_ROR_XORS(cond, dest, roperand, r2shift, shift5)                                                        \
2953     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2954         (3 << 29) + (1 << 19) + (1 << 18)
2955 
2956 /* Rotate and then ADD */
2957 #define E_COND_ROR_ADD(cond, dest, roperand, r2shift, shift5)                                                         \
2958     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2959         (4 << 29) + (1 << 19) + (1 << 18)
2960 /* Rotate and Set Flag then ADD */
2961 #define E_COND_ROR_ADDS(cond, dest, roperand, r2shift, shift5)                                                        \
2962     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2963         (4 << 29) + (1 << 19) + (1 << 18)
2964 
2965 /* Rotate and then SUB */
2966 #define E_COND_ROR_SUB(cond, dest, roperand, r2shift, shift5)                                                         \
2967     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2968         (5 << 29) + (1 << 19) + (1 << 18)
2969 /* Rotate and Set Flag then SUB */
2970 #define E_COND_ROR_SUBS(cond, dest, roperand, r2shift, shift5)                                                        \
2971     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2972         (5 << 29) + (1 << 19) + (1 << 18)
2973 
2974 /* Rotate and then ADC */
2975 #define E_COND_ROR_ADC(cond, dest, roperand, r2shift, shift5)                                                         \
2976     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2977         (6 << 29) + (1 << 19) + (1 << 18)
2978 /* Rotate and Set Flag then ADC */
2979 #define E_COND_ROR_ADCS(cond, dest, roperand, r2shift, shift5)                                                        \
2980     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2981         (6 << 29) + (1 << 19) + (1 << 18)
2982 
2983 /* Rotate and then SBC */
2984 #define E_COND_ROR_SBC(cond, dest, roperand, r2shift, shift5)                                                         \
2985     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2986         (7 << 29) + (1 << 19) + (1 << 18)
2987 /* Rotate and Set Flag then SBC */
2988 #define E_COND_ROR_SBCS(cond, dest, roperand, r2shift, shift5)                                                        \
2989     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
2990         (7 << 29) + (1 << 19) + (1 << 18)
2991 
2992 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2993 /*                                       Arithmetical Shift Codes */
2994 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
2995 
2996 /*                                                         opcode      Dest            Src1              r2shift SFlag
2997  */
2998 /*                                                         Cond         Imm                   Extra Operation Left/Right
2999  */
3000 /*                                                         Shift/Rotate  Arith/Shift */
3001 
3002 /* Arith Shift Right */
3003 #define E_ASR(dest, r2shift, shift5)                                                                         \
3004     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3005         (0 << 19) + (1 << 18)
3006 /* Arith Shift Right and Set Flag */
3007 #define E_ASRS(dest, r2shift, shift5)                                                                        \
3008     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3009         (0 << 19) + (1 << 18)
3010 
3011 /* Arith Shift Right and then AND */
3012 #define E_ASR_AND(dest, roperand, r2shift, shift5)                                                                  \
3013     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3014         (1 << 29) + (0 << 19) + (1 << 18)
3015 /* Arith Shift Right and Set Flag then AND */
3016 #define E_ASR_ANDS(dest, roperand, r2shift, shift5)                                                                 \
3017     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3018         (1 << 29) + (0 << 19) + (1 << 18)
3019 
3020 /* Arith Shift Right and then OR */
3021 #define E_ASR_OR(dest, roperand, r2shift, shift5)                                                                   \
3022     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3023         (2 << 29) + (0 << 19) + (1 << 18)
3024 /* Arith Shift Right and Set Flag then OR */
3025 #define E_ASR_ORS(dest, roperand, r2shift, shift5)                                                                  \
3026     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3027         (2 << 29) + (0 << 19) + (1 << 18)
3028 
3029 /* Arith Shift Right and then XOR */
3030 #define E_ASR_XOR(dest, roperand, r2shift, shift5)                                                                  \
3031     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3032         (3 << 29) + (0 << 19) + (1 << 18)
3033 /* Arith Shift Right and Set Flag then XOR */
3034 #define E_ASR_XORS(dest, roperand, r2shift, shift5)                                                                 \
3035     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3036         (3 << 29) + (0 << 19) + (1 << 18)
3037 
3038 /* Arith Shift Right and then ADD */
3039 #define E_ASR_ADD(dest, roperand, r2shift, shift5)                                                                  \
3040     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3041         (4 << 29) + (0 << 19) + (1 << 18)
3042 /* Arith Shift Right and Set Flag then ADD */
3043 #define E_ASR_ADDS(dest, roperand, r2shift, shift5)                                                                 \
3044     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3045         (4 << 29) + (0 << 19) + (1 << 18)
3046 
3047 /* Arith Shift Right and then SUB */
3048 #define E_ASR_SUB(dest, roperand, r2shift, shift5)                                                                  \
3049     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3050         (5 << 29) + (0 << 19) + (1 << 18)
3051 /* Arith Shift Right and Set Flag then SUB */
3052 #define E_ASR_SUBS(dest, roperand, r2shift, shift5)                                                                 \
3053     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3054         (5 << 29) + (0 << 19) + (1 << 18)
3055 
3056 /* Arith Shift Right and then ADC */
3057 #define E_ASR_ADC(dest, roperand, r2shift, shift5)                                                                  \
3058     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3059         (6 << 29) + (0 << 19) + (1 << 18)
3060 /* Arith Shift Right and Set Flag then ADC */
3061 #define E_ASR_ADCS(dest, roperand, r2shift, shift5)                                                                 \
3062     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3063         (6 << 29) + (0 << 19) + (1 << 18)
3064 
3065 /* Arith Shift Right and then SBC */
3066 #define E_ASR_SBC(dest, roperand, r2shift, shift5)                                                                  \
3067     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3068         (7 << 29) + (0 << 19) + (1 << 18)
3069 /* Arith Shift Right and Set Flag then SBC */
3070 #define E_ASR_SBCS(dest, roperand, r2shift, shift5)                                                                 \
3071     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3072         (7 << 29) + (0 << 19) + (1 << 18)
3073 
3074 /* Conditional */
3075 /* Conditional Arith Shift */
3076 #define E_COND_ASR(cond, dest, r2shift, shift5)                                                                \
3077     DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3078         (0 << 19) + (1 << 18)
3079 /* Conditional Arith Shift and Set Flag */
3080 #define E_COND_ASRS(cond, dest, r2shift, shift5)                                                               \
3081     DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3082         (0 << 19) + (1 << 18)
3083 
3084 /* Conditional Arith Shift and then AND */
3085 #define E_COND_ASR_AND(cond, dest, roperand, r2shift, shift5)                                                         \
3086     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3087         (1 << 29) + (0 << 19) + (1 << 18)
3088 /* Conditional Arith Shift and Set Flag then AND */
3089 #define E_COND_ASR_ANDS(cond, dest, roperand, r2shift, shift5)                                                        \
3090     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3091         (1 << 29) + (0 << 19) + (1 << 18)
3092 
3093 /* Conditional Arith Shift and then OR */
3094 #define E_COND_ASR_OR(cond, dest, roperand, r2shift, shift5)                                                          \
3095     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3096         (2 << 29) + (0 << 19) + (1 << 18)
3097 /* Conditional Arith Shift and Set Flag then OR */
3098 #define E_COND_ASR_ORS(cond, dest, roperand, r2shift, shift5)                                                         \
3099     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3100         (2 << 29) + (0 << 19) + (1 << 18)
3101 
3102 /* Conditional Arith Shift and then XOR */
3103 #define E_COND_ASR_XOR(cond, dest, roperand, r2shift, shift5)                                                         \
3104     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3105         (3 << 29) + (0 << 19) + (1 << 18)
3106 /* Conditional Arith Shift and Set Flag then XOR */
3107 #define E_COND_ASR_XORS(cond, dest, roperand, r2shift, shift5)                                                        \
3108     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3109         (3 << 29) + (0 << 19) + (1 << 18)
3110 
3111 /* Conditional Arith Shift and then ADD */
3112 #define E_COND_ASR_ADD(cond, dest, roperand, r2shift, shift5)                                                         \
3113     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3114         (4 << 29) + (0 << 19) + (1 << 18)
3115 /* Conditional Arith Shift and Set Flag then ADD */
3116 #define E_COND_ASR_ADDS(cond, dest, roperand, r2shift, shift5)                                                        \
3117     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3118         (4 << 29) + (0 << 19) + (1 << 18)
3119 
3120 /* Conditional Arith Shift and then SUB */
3121 #define E_COND_ASR_SUB(cond, dest, roperand, r2shift, shift5)                                                         \
3122     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3123         (5 << 29) + (0 << 19) + (1 << 18)
3124 /* Conditional Arith Shift and Set Flag then SUB */
3125 #define E_COND_ASR_SUBS(cond, dest, roperand, r2shift, shift5)                                                        \
3126     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3127         (5 << 29) + (0 << 19) + (1 << 18)
3128 
3129 /* Conditional Arith Shift and then ADC */
3130 #define E_COND_ASR_ADC(cond, dest, roperand, r2shift, shift5)                                                         \
3131     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3132         (6 << 29) + (0 << 19) + (1 << 18)
3133 /* Conditional Arith Shift and Set Flag then ADC */
3134 #define E_COND_ASR_ADCS(cond, dest, roperand, r2shift, shift5)                                                        \
3135     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3136         (6 << 29) + (0 << 19) + (1 << 18)
3137 
3138 /* Conditional Arith Shift and then SBC */
3139 #define E_COND_ASR_SBC(cond, dest, roperand, r2shift, shift5)                                                         \
3140     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3141         (7 << 29) + (0 << 19) + (1 << 18)
3142 /* Conditional Arith Shift and Set Flag then SBC */
3143 #define E_COND_ASR_SBCS(cond, dest, roperand, r2shift, shift5)                                                        \
3144     DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3145         (7 << 29) + (0 << 19) + (1 << 18)
3146 
3147 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3148 /*                                       Flip Opcodes */
3149 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3150 /*                                                         opcode      Dest            Src1              r2shift SFlag
3151  */
3152 /*                                                         Cond         Imm                   Extra Operation Endian/bit
3153  */
3154 /*                                                         ARITH  Arith/Shift */
3155 
3156 /* Flip Endian , ASR Right */
3157 #define E_FEND_ASR(dest, r2shift, shift5)                                                                    \
3158     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3159         (0 << 18) + (1 << 19)
3160 /* Flip Endian , ASR Right ,Set Flag */
3161 #define E_FEND_ASRS(dest, r2shift, shift5)                                                                   \
3162     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3163         (0 << 18) + (1 << 19)
3164 
3165 /* Flip Endian , ASR Right , AND */
3166 #define E_FEND_ASR_AND(dest, roperand, r2shift, shift5)                                                             \
3167     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3168         (1 << 29) + (0 << 18) + (1 << 19)
3169 /* Flip Endian , ASR Right ,Set Flag then AND */
3170 #define E_FEND_ASR_ANDS(dest, roperand, r2shift, shift5)                                                            \
3171     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3172         (1 << 29) + (0 << 18) + (1 << 19)
3173 
3174 /* Flip Endian , ASR Right , OR */
3175 #define E_FEND_ASR_OR(dest, roperand, r2shift, shift5)                                                              \
3176     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3177         (2 << 29) + (0 << 18) + (1 << 19)
3178 /* Flip Endian , ASR Right ,Set Flag then OR */
3179 #define E_FEND_ASR_ORS(dest, roperand, r2shift, shift5)                                                             \
3180     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3181         (2 << 29) + (0 << 18) + (1 << 19)
3182 
3183 /* Flip Endian , ASR Right , XOR */
3184 #define E_FEND_ASR_XOR(dest, roperand, r2shift, shift5)                                                             \
3185     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3186         (3 << 29) + (0 << 18) + (1 << 19)
3187 /* Flip Endian , ASR Right ,Set Flag then XOR */
3188 #define E_FEND_ASR_XORS(dest, roperand, r2shift, shift5)                                                            \
3189     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3190         (3 << 29) + (0 << 18) + (1 << 19)
3191 
3192 /* Flip Endian , ASR Right , ADD */
3193 #define E_FEND_ASR_ADD(dest, roperand, r2shift, shift5)                                                             \
3194     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3195         (4 << 29) + (0 << 18) + (1 << 19)
3196 /* Flip Endian , ASR Right ,Set Flag then ADD */
3197 #define E_FEND_ASR_ADDS(dest, roperand, r2shift, shift5)                                                            \
3198     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3199         (4 << 29) + (0 << 18) + (1 << 19)
3200 
3201 /* Flip Endian , ASR Right , SUB */
3202 #define E_FEND_ASR_SUB(dest, roperand, r2shift, shift5)                                                             \
3203     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3204         (5 << 29) + (0 << 18) + (1 << 19)
3205 /* Flip Endian , ASR Right ,Set Flag then SUB */
3206 #define E_FEND_ASR_SUBS(dest, roperand, r2shift, shift5)                                                            \
3207     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3208         (5 << 29) + (0 << 18) + (1 << 19)
3209 
3210 /* Flip Endian , ASR Right , ADC */
3211 #define E_FEND_ASR_ADC(dest, roperand, r2shift, shift5)                                                             \
3212     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3213         (6 << 29) + (0 << 18) + (1 << 19)
3214 /* Flip Endian , ASR Right ,Set Flag then ADC */
3215 #define E_FEND_ASR_ADCS(dest, roperand, r2shift, shift5)                                                            \
3216     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3217         (6 << 29) + (0 << 18) + (1 << 19)
3218 
3219 /* Flip Endian , ASR Right , SBC */
3220 #define E_FEND_ASR_SBC(dest, roperand, r2shift, shift5)                                                             \
3221     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3222         (7 << 29) + (0 << 18) + (1 << 19)
3223 /* Flip Endian , ASR Right ,Set Flag then SBC */
3224 #define E_FEND_ASR_SBCS(dest, roperand, r2shift, shift5)                                                            \
3225     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3226         (7 << 29) + (0 << 18) + (1 << 19)
3227 
3228 /* Conditional */
3229 /* Conditional Flip Endian , ASR */
3230 #define E_COND_FEND_ASR(cond, dest, r2shift, shift5)                                                           \
3231     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3232         (0 << 18) + (1 << 19)
3233 /* Conditional Flip Endian , ASR ,Set Flag */
3234 #define E_COND_FEND_ASRS(cond, dest, r2shift, shift5)                                                          \
3235     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3236         (0 << 18) + (1 << 19)
3237 
3238 /* Conditional Flip Endian , ASR , AND */
3239 #define E_COND_FEND_ASR_AND(cond, dest, roperand, r2shift, shift5)                                                    \
3240     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3241         (1 << 29) + (0 << 18) + (1 << 19)
3242 /* Conditional Flip Endian , ASR ,Set Flag then AND */
3243 #define E_COND_FEND_ASR_ANDS(cond, dest, roperand, r2shift, shift5)                                                   \
3244     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3245         (1 << 29) + (0 << 18) + (1 << 19)
3246 
3247 /* Conditional Flip Endian , ASR , OR */
3248 #define E_COND_FEND_ASR_OR(cond, dest, roperand, r2shift, shift5)                                                     \
3249     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3250         (2 << 29) + (0 << 18) + (1 << 19)
3251 /* Conditional Flip Endian , ASR ,Set Flag then OR */
3252 #define E_COND_FEND_ASR_ORS(cond, dest, roperand, r2shift, shift5)                                                    \
3253     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3254         (2 << 29) + (0 << 18) + (1 << 19)
3255 
3256 /* Conditional Flip Endian , ASR , XOR */
3257 #define E_COND_FEND_ASR_XOR(cond, dest, roperand, r2shift, shift5)                                                    \
3258     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3259         (3 << 29) + (0 << 18) + (1 << 19)
3260 /* Conditional Flip Endian , ASR ,Set Flag then XOR */
3261 #define E_COND_FEND_ASR_XORS(cond, dest, roperand, r2shift, shift5)                                                   \
3262     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3263         (3 << 29) + (0 << 18) + (1 << 19)
3264 
3265 /* Conditional Flip Endian , ASR , ADD */
3266 #define E_COND_FEND_ASR_ADD(cond, dest, roperand, r2shift, shift5)                                                    \
3267     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3268         (4 << 29) + (0 << 18) + (1 << 19)
3269 /* Conditional Flip Endian , ASR ,Set Flag then ADD */
3270 #define E_COND_FEND_ASR_ADDS(cond, dest, roperand, r2shift, shift5)                                                   \
3271     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3272         (4 << 29) + (0 << 18) + (1 << 19)
3273 
3274 /* Conditional Flip Endian , ASR , SUB */
3275 #define E_COND_FEND_ASR_SUB(cond, dest, roperand, r2shift, shift5)                                                    \
3276     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3277         (5 << 29) + (0 << 18) + (1 << 19)
3278 /* Conditional Flip Endian , ASR ,Set Flag then SUB */
3279 #define E_COND_FEND_ASR_SUBS(cond, dest, roperand, r2shift, shift5)                                                   \
3280     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3281         (5 << 29) + (0 << 18) + (1 << 19)
3282 
3283 /* Conditional Flip Endian , ASR , ADC */
3284 #define E_COND_FEND_ASR_ADC(cond, dest, roperand, r2shift, shift5)                                                    \
3285     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3286         (6 << 29) + (0 << 18) + (1 << 19)
3287 /* Conditional Flip Endian , ASR ,Set Flag then ADC */
3288 #define E_COND_FEND_ASR_ADCS(cond, dest, roperand, r2shift, shift5)                                                   \
3289     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3290         (6 << 29) + (0 << 18) + (1 << 19)
3291 
3292 /* Conditional Flip Endian , ASR , SBC */
3293 #define E_COND_FEND_ASR_SBC(cond, dest, roperand, r2shift, shift5)                                                    \
3294     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3295         (7 << 29) + (0 << 18) + (1 << 19)
3296 /* Conditional Flip Endian , ASR ,Set Flag then SBC */
3297 #define E_COND_FEND_ASR_SBCS(cond, dest, roperand, r2shift, shift5)                                                   \
3298     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3299         (7 << 29) + (0 << 18) + (1 << 19)
3300 
3301 /* Bitwise Flip ASR */
3302 
3303 /* Flip Bitwise , ASR Right */
3304 #define E_FBIT_ASR(dest, r2shift, shift5)                                                                    \
3305     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3306         (1 << 18) + (1 << 19)
3307 /* Flip Bitwise , ASR Right ,Set Flag */
3308 #define E_FBIT_ASRS(dest, r2shift, shift5)                                                                   \
3309     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3310         (1 << 18) + (1 << 19)
3311 
3312 /* Flip Bitwise , ASR Right , AND */
3313 #define E_FBIT_ASR_AND(dest, roperand, r2shift, shift5)                                                             \
3314     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3315         (1 << 29) + (1 << 18) + (1 << 19)
3316 /* Flip Bitwise , ASR Right ,Set Flag then AND */
3317 #define E_FBIT_ASR_ANDS(dest, roperand, r2shift, shift5)                                                            \
3318     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3319         (1 << 29) + (1 << 18) + (1 << 19)
3320 
3321 /* Flip Bitwise , ASR Right , OR */
3322 #define E_FBIT_ASR_OR(dest, roperand, r2shift, shift5)                                                              \
3323     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3324         (2 << 29) + (1 << 18) + (1 << 19)
3325 /* Flip Bitwise , ASR Right ,Set Flag then OR */
3326 #define E_FBIT_ASR_ORS(dest, roperand, r2shift, shift5)                                                             \
3327     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3328         (2 << 29) + (1 << 18) + (1 << 19)
3329 
3330 /* Flip Bitwise , ASR Right , XOR */
3331 #define E_FBIT_ASR_XOR(dest, roperand, r2shift, shift5)                                                             \
3332     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3333         (3 << 29) + (1 << 18) + (1 << 19)
3334 /* Flip Bitwise , ASR Right ,Set Flag then XOR */
3335 #define E_FBIT_ASR_XORS(dest, roperand, r2shift, shift5)                                                            \
3336     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3337         (3 << 29) + (1 << 18) + (1 << 19)
3338 
3339 /* Flip Bitwise , ASR Right , ADD */
3340 #define E_FBIT_ASR_ADD(dest, roperand, r2shift, shift5)                                                             \
3341     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3342         (4 << 29) + (1 << 18) + (1 << 19)
3343 /* Flip Bitwise , ASR Right ,Set Flag then ADD */
3344 #define E_FBIT_ASR_ADDS(dest, roperand, r2shift, shift5)                                                            \
3345     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3346         (4 << 29) + (1 << 18) + (1 << 19)
3347 
3348 /* Flip Bitwise , ASR Right , SUB */
3349 #define E_FBIT_ASR_SUB(dest, roperand, r2shift, shift5)                                                             \
3350     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3351         (5 << 29) + (1 << 18) + (1 << 19)
3352 /* Flip Bitwise , ASR Right ,Set Flag then SUB */
3353 #define E_FBIT_ASR_SUBS(dest, roperand, r2shift, shift5)                                                            \
3354     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3355         (5 << 29) + (1 << 18) + (1 << 19)
3356 
3357 /* Flip Bitwise , ASR Right , ADC */
3358 #define E_FBIT_ASR_ADC(dest, roperand, r2shift, shift5)                                                             \
3359     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3360         (6 << 29) + (1 << 18) + (1 << 19)
3361 /* Flip Bitwise , ASR Right ,Set Flag then ADC */
3362 #define E_FBIT_ASR_ADCS(dest, roperand, r2shift, shift5)                                                            \
3363     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3364         (6 << 29) + (1 << 18) + (1 << 19)
3365 
3366 /* Flip Bitwise , ASR Right , SBC */
3367 #define E_FBIT_ASR_SBC(dest, roperand, r2shift, shift5)                                                             \
3368     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3369         (7 << 29) + (1 << 18) + (1 << 19)
3370 /* Flip Bitwise , ASR Right ,Set Flag then SBC */
3371 #define E_FBIT_ASR_SBCS(dest, roperand, r2shift, shift5)                                                            \
3372     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3373         (7 << 29) + (1 << 18) + (1 << 19)
3374 
3375 /* Conditional */
3376 /* Conditional Flip Bitwise , ASR */
3377 #define E_COND_FBIT_ASR(cond, dest, r2shift, shift5)                                                           \
3378     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3379         (1 << 18) + (1 << 19)
3380 /* Conditional Flip Bitwise , ASR ,Set Flag */
3381 #define E_COND_FBIT_ASRS(cond, dest, r2shift, shift5)                                                          \
3382     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3383         (1 << 18) + (1 << 19)
3384 
3385 /* Conditional Flip Bitwise , ASR , AND */
3386 #define E_COND_FBIT_ASR_AND(cond, dest, roperand, r2shift, shift5)                                                    \
3387     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3388         (1 << 29) + (1 << 18) + (1 << 19)
3389 /* Conditional Flip Bitwise , ASR ,Set Flag then AND */
3390 #define E_COND_FBIT_ASR_ANDS(cond, dest, roperand, r2shift, shift5)                                                   \
3391     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3392         (1 << 29) + (1 << 18) + (1 << 19)
3393 
3394 /* Conditional Flip Bitwise , ASR , OR */
3395 #define E_COND_FBIT_ASR_OR(cond, dest, roperand, r2shift, shift5)                                                     \
3396     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3397         (2 << 29) + (1 << 18) + (1 << 19)
3398 /* Conditional Flip Bitwise , ASR ,Set Flag then OR */
3399 #define E_COND_FBIT_ASR_ORS(cond, dest, roperand, r2shift, shift5)                                                    \
3400     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3401         (2 << 29) + (1 << 18) + (1 << 19)
3402 
3403 /* Conditional Flip Bitwise , ASR , XOR */
3404 #define E_COND_FBIT_ASR_XOR(cond, dest, roperand, r2shift, shift5)                                                    \
3405     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3406         (3 << 29) + (1 << 18) + (1 << 19)
3407 /* Conditional Flip Bitwise , ASR ,Set Flag then XOR */
3408 #define E_COND_FBIT_ASR_XORS(cond, dest, roperand, r2shift, shift5)                                                   \
3409     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3410         (3 << 29) + (1 << 18) + (1 << 19)
3411 
3412 /* Conditional Flip Bitwise , ASR , ADD */
3413 #define E_COND_FBIT_ASR_ADD(cond, dest, roperand, r2shift, shift5)                                                    \
3414     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3415         (4 << 29) + (1 << 18) + (1 << 19)
3416 /* Conditional Flip Bitwise , ASR ,Set Flag then ADD */
3417 #define E_COND_FBIT_ASR_ADDS(cond, dest, roperand, r2shift, shift5)                                                   \
3418     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3419         (4 << 29) + (1 << 18) + (1 << 19)
3420 
3421 /* Conditional Flip Bitwise , ASR , SUB */
3422 #define E_COND_FBIT_ASR_SUB(cond, dest, roperand, r2shift, shift5)                                                    \
3423     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3424         (5 << 29) + (1 << 18) + (1 << 19)
3425 /* Conditional Flip Bitwise , ASR ,Set Flag then SUB */
3426 #define E_COND_FBIT_ASR_SUBS(cond, dest, roperand, r2shift, shift5)                                                   \
3427     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3428         (5 << 29) + (1 << 18) + (1 << 19)
3429 
3430 /* Conditional Flip Bitwise , ASR , ADC */
3431 #define E_COND_FBIT_ASR_ADC(cond, dest, roperand, r2shift, shift5)                                                    \
3432     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3433         (6 << 29) + (1 << 18) + (1 << 19)
3434 /* Conditional Flip Bitwise , ASR ,Set Flag then ADC */
3435 #define E_COND_FBIT_ASR_ADCS(cond, dest, roperand, r2shift, shift5)                                                   \
3436     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3437         (6 << 29) + (1 << 18) + (1 << 19)
3438 
3439 /* Conditional Flip Bitwise , ASR , SBC */
3440 #define E_COND_FBIT_ASR_SBC(cond, dest, roperand, r2shift, shift5)                                                    \
3441     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3442         (7 << 29) + (1 << 18) + (1 << 19)
3443 /* Conditional Flip Bitwise , ASR ,Set Flag then SBC */
3444 #define E_COND_FBIT_ASR_SBCS(cond, dest, roperand, r2shift, shift5)                                                   \
3445     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3446         (7 << 29) + (1 << 18) + (1 << 19)
3447 
3448 /* Flip Endian , LSR Right */
3449 #define E_FEND_LSR(dest, r2shift, shift5)                                                                    \
3450     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3451         (0 << 18) + (0 << 19)
3452 /* Flip Endian , LSR Right ,Set Flag */
3453 #define E_FEND_LSRS(dest, r2shift, shift5)                                                                   \
3454     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3455         (0 << 18) + (0 << 19)
3456 
3457 /* Flip Endian , LSR Right , AND */
3458 #define E_FEND_LSR_AND(dest, roperand, r2shift, shift5)                                                             \
3459     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3460         (1 << 29) + (0 << 18) + (0 << 19)
3461 /* Flip Endian , LSR Right ,Set Flag then AND */
3462 #define E_FEND_LSR_ANDS(dest, roperand, r2shift, shift5)                                                            \
3463     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3464         (1 << 29) + (0 << 18) + (0 << 19)
3465 
3466 /* Flip Endian , LSR Right , OR */
3467 #define E_FEND_LSR_OR(dest, roperand, r2shift, shift5)                                                              \
3468     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3469         (2 << 29) + (0 << 18) + (0 << 19)
3470 /* Flip Endian , LSR Right ,Set Flag then OR */
3471 #define E_FEND_LSR_ORS(dest, roperand, r2shift, shift5)                                                             \
3472     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3473         (2 << 29) + (0 << 18) + (0 << 19)
3474 
3475 /* Flip Endian , LSR Right , XOR */
3476 #define E_FEND_LSR_XOR(dest, roperand, r2shift, shift5)                                                             \
3477     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3478         (3 << 29) + (0 << 18) + (0 << 19)
3479 /* Flip Endian , LSR Right ,Set Flag then XOR */
3480 #define E_FEND_LSR_XORS(dest, roperand, r2shift, shift5)                                                            \
3481     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3482         (3 << 29) + (0 << 18) + (0 << 19)
3483 
3484 /* Flip Endian , LSR Right , ADD */
3485 #define E_FEND_LSR_ADD(dest, roperand, r2shift, shift5)                                                             \
3486     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3487         (4 << 29) + (0 << 18) + (0 << 19)
3488 /* Flip Endian , LSR Right ,Set Flag then ADD */
3489 #define E_FEND_LSR_ADDS(dest, roperand, r2shift, shift5)                                                            \
3490     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3491         (4 << 29) + (0 << 18) + (0 << 19)
3492 
3493 /* Flip Endian , LSR Right , SUB */
3494 #define E_FEND_LSR_SUB(dest, roperand, r2shift, shift5)                                                             \
3495     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3496         (5 << 29) + (0 << 18) + (0 << 19)
3497 /* Flip Endian , LSR Right ,Set Flag then SUB */
3498 #define E_FEND_LSR_SUBS(dest, roperand, r2shift, shift5)                                                            \
3499     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3500         (5 << 29) + (0 << 18) + (0 << 19)
3501 
3502 /* Flip Endian , LSR Right , ADC */
3503 #define E_FEND_LSR_ADC(dest, roperand, r2shift, shift5)                                                             \
3504     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3505         (6 << 29) + (0 << 18) + (0 << 19)
3506 /* Flip Endian , LSR Right ,Set Flag then ADC */
3507 #define E_FEND_LSR_ADCS(dest, roperand, r2shift, shift5)                                                            \
3508     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3509         (6 << 29) + (0 << 18) + (0 << 19)
3510 
3511 /* Flip Endian , LSR Right , SBC */
3512 #define E_FEND_LSR_SBC(dest, roperand, r2shift, shift5)                                                             \
3513     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3514         (7 << 29) + (0 << 18) + (0 << 19)
3515 /* Flip Endian , LSR Right ,Set Flag then SBC */
3516 #define E_FEND_LSR_SBCS(dest, roperand, r2shift, shift5)                                                            \
3517     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3518         (7 << 29) + (0 << 18) + (0 << 19)
3519 
3520 /* Conditional */
3521 /* Conditional Flip Endian , LSR */
3522 #define E_COND_FEND_LSR(cond, dest, r2shift, shift5)                                                           \
3523     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3524         (0 << 18) + (0 << 19)
3525 /* Conditional Flip Endian , LSR ,Set Flag */
3526 #define E_COND_FEND_LSRS(cond, dest, r2shift, shift5)                                                          \
3527     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3528         (0 << 18) + (0 << 19)
3529 
3530 /* Conditional Flip Endian , LSR , AND */
3531 #define E_COND_FEND_LSR_AND(cond, dest, roperand, r2shift, shift5)                                                    \
3532     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3533         (1 << 29) + (0 << 18) + (0 << 19)
3534 /* Conditional Flip Endian , LSR ,Set Flag then AND */
3535 #define E_COND_FEND_LSR_ANDS(cond, dest, roperand, r2shift, shift5)                                                   \
3536     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3537         (1 << 29) + (0 << 18) + (0 << 19)
3538 
3539 /* Conditional Flip Endian , LSR , OR */
3540 #define E_COND_FEND_LSR_OR(cond, dest, roperand, r2shift, shift5)                                                     \
3541     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3542         (2 << 29) + (0 << 18) + (0 << 19)
3543 /* Conditional Flip Endian , LSR ,Set Flag then OR */
3544 #define E_COND_FEND_LSR_ORS(cond, dest, roperand, r2shift, shift5)                                                    \
3545     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3546         (2 << 29) + (0 << 18) + (0 << 19)
3547 
3548 /* Conditional Flip Endian , LSR , XOR */
3549 #define E_COND_FEND_LSR_XOR(cond, dest, roperand, r2shift, shift5)                                                    \
3550     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3551         (3 << 29) + (0 << 18) + (0 << 19)
3552 /* Conditional Flip Endian , LSR ,Set Flag then XOR */
3553 #define E_COND_FEND_LSR_XORS(cond, dest, roperand, r2shift, shift5)                                                   \
3554     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3555         (3 << 29) + (0 << 18) + (0 << 19)
3556 
3557 /* Conditional Flip Endian , LSR , ADD */
3558 #define E_COND_FEND_LSR_ADD(cond, dest, roperand, r2shift, shift5)                                                    \
3559     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3560         (4 << 29) + (0 << 18) + (0 << 19)
3561 /* Conditional Flip Endian , LSR ,Set Flag then ADD */
3562 #define E_COND_FEND_LSR_ADDS(cond, dest, roperand, r2shift, shift5)                                                   \
3563     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3564         (4 << 29) + (0 << 18) + (0 << 19)
3565 
3566 /* Conditional Flip Endian , LSR , SUB */
3567 #define E_COND_FEND_LSR_SUB(cond, dest, roperand, r2shift, shift5)                                                    \
3568     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3569         (5 << 29) + (0 << 18) + (0 << 19)
3570 /* Conditional Flip Endian , LSR ,Set Flag then SUB */
3571 #define E_COND_FEND_LSR_SUBS(cond, dest, roperand, r2shift, shift5)                                                   \
3572     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3573         (5 << 29) + (0 << 18) + (0 << 19)
3574 
3575 /* Conditional Flip Endian , LSR , ADC */
3576 #define E_COND_FEND_LSR_ADC(cond, dest, roperand, r2shift, shift5)                                                    \
3577     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3578         (6 << 29) + (0 << 18) + (0 << 19)
3579 /* Conditional Flip Endian , LSR ,Set Flag then ADC */
3580 #define E_COND_FEND_LSR_ADCS(cond, dest, roperand, r2shift, shift5)                                                   \
3581     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3582         (6 << 29) + (0 << 18) + (0 << 19)
3583 
3584 /* Conditional Flip Endian , LSR , SBC */
3585 #define E_COND_FEND_LSR_SBC(cond, dest, roperand, r2shift, shift5)                                                    \
3586     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3587         (7 << 29) + (0 << 18) + (0 << 19)
3588 /* Conditional Flip Endian , LSR ,Set Flag then SBC */
3589 #define E_COND_FEND_LSR_SBCS(cond, dest, roperand, r2shift, shift5)                                                   \
3590     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3591         (7 << 29) + (0 << 18) + (0 << 19)
3592 
3593 /* Bitwise Flip LSR */
3594 
3595 /* Flip Bitwise , LSR Right */
3596 #define E_FBIT_LSR(dest, r2shift, shift5)                                                                    \
3597     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3598         (1 << 18) + (0 << 19)
3599 /* Flip Bitwise , LSR Right ,Set Flag */
3600 #define E_FBIT_LSRS(dest, r2shift, shift5)                                                                   \
3601     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3602         (1 << 18) + (0 << 19)
3603 
3604 /* Flip Bitwise , LSR Right , AND */
3605 #define E_FBIT_LSR_AND(dest, roperand, r2shift, shift5)                                                             \
3606     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3607         (1 << 29) + (1 << 18) + (0 << 19)
3608 /* Flip Bitwise , LSR Right ,Set Flag then AND */
3609 #define E_FBIT_LSR_ANDS(dest, roperand, r2shift, shift5)                                                            \
3610     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3611         (1 << 29) + (1 << 18) + (0 << 19)
3612 
3613 /* Flip Bitwise , LSR Right , OR */
3614 #define E_FBIT_LSR_OR(dest, roperand, r2shift, shift5)                                                              \
3615     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3616         (2 << 29) + (1 << 18) + (0 << 19)
3617 /* Flip Bitwise , LSR Right ,Set Flag then OR */
3618 #define E_FBIT_LSR_ORS(dest, roperand, r2shift, shift5)                                                             \
3619     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3620         (2 << 29) + (1 << 18) + (0 << 19)
3621 
3622 /* Flip Bitwise , LSR Right , XOR */
3623 #define E_FBIT_LSR_XOR(dest, roperand, r2shift, shift5)                                                             \
3624     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3625         (3 << 29) + (1 << 18) + (0 << 19)
3626 /* Flip Bitwise , LSR Right ,Set Flag then XOR */
3627 #define E_FBIT_LSR_XORS(dest, roperand, r2shift, shift5)                                                            \
3628     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3629         (3 << 29) + (1 << 18) + (0 << 19)
3630 
3631 /* Flip Bitwise , LSR Right , ADD */
3632 #define E_FBIT_LSR_ADD(dest, roperand, r2shift, shift5)                                                             \
3633     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3634         (4 << 29) + (1 << 18) + (0 << 19)
3635 /* Flip Bitwise , LSR Right ,Set Flag then ADD */
3636 #define E_FBIT_LSR_ADDS(dest, roperand, r2shift, shift5)                                                            \
3637     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3638         (4 << 29) + (1 << 18) + (0 << 19)
3639 
3640 /* Flip Bitwise , LSR Right , SUB */
3641 #define E_FBIT_LSR_SUB(dest, roperand, r2shift, shift5)                                                             \
3642     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3643         (5 << 29) + (1 << 18) + (0 << 19)
3644 /* Flip Bitwise , LSR Right ,Set Flag then SUB */
3645 #define E_FBIT_LSR_SUBS(dest, roperand, r2shift, shift5)                                                            \
3646     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3647         (5 << 29) + (1 << 18) + (0 << 19)
3648 
3649 /* Flip Bitwise , LSR Right , ADC */
3650 #define E_FBIT_LSR_ADC(dest, roperand, r2shift, shift5)                                                             \
3651     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3652         (6 << 29) + (1 << 18) + (0 << 19)
3653 /* Flip Bitwise , LSR Right ,Set Flag then ADC */
3654 #define E_FBIT_LSR_ADCS(dest, roperand, r2shift, shift5)                                                            \
3655     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3656         (6 << 29) + (1 << 18) + (0 << 19)
3657 
3658 /* Flip Bitwise , LSR Right , SBC */
3659 #define E_FBIT_LSR_SBC(dest, roperand, r2shift, shift5)                                                             \
3660     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3661         (7 << 29) + (1 << 18) + (0 << 19)
3662 /* Flip Bitwise , LSR Right ,Set Flag then SBC */
3663 #define E_FBIT_LSR_SBCS(dest, roperand, r2shift, shift5)                                                            \
3664     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \
3665         (7 << 29) + (1 << 18) + (0 << 19)
3666 
3667 /* Conditional */
3668 /* Conditional Flip Bitwise , LSR */
3669 #define E_COND_FBIT_LSR(cond, dest, r2shift, shift5)                                                           \
3670     DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3671         (1 << 18) + (0 << 19)
3672 /* Conditional Flip Bitwise , LSR ,Set Flag */
3673 #define E_COND_FBIT_LSRS(cond, dest, r2shift, shift5)                                                          \
3674     DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \
3675         (1 << 18) + (0 << 19)
3676 
3677 /* Conditional Flip Bitwise , LSR , AND */
3678 #define E_COND_FBIT_LSR_AND(cond, dest, roperand, r2shift, shift5)                                                    \
3679     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3680         (1 << 29) + (1 << 18) + (0 << 19)
3681 /* Conditional Flip Bitwise , LSR ,Set Flag then AND */
3682 #define E_COND_FBIT_LSR_ANDS(cond, dest, roperand, r2shift, shift5)                                                   \
3683     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3684         (1 << 29) + (1 << 18) + (0 << 19)
3685 
3686 /* Conditional Flip Bitwise , LSR , OR */
3687 #define E_COND_FBIT_LSR_OR(cond, dest, roperand, r2shift, shift5)                                                     \
3688     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3689         (2 << 29) + (1 << 18) + (0 << 19)
3690 /* Conditional Flip Bitwise , LSR ,Set Flag then OR */
3691 #define E_COND_FBIT_LSR_ORS(cond, dest, roperand, r2shift, shift5)                                                    \
3692     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3693         (2 << 29) + (1 << 18) + (0 << 19)
3694 
3695 /* Conditional Flip Bitwise , LSR , XOR */
3696 #define E_COND_FBIT_LSR_XOR(cond, dest, roperand, r2shift, shift5)                                                    \
3697     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3698         (3 << 29) + (1 << 18) + (0 << 19)
3699 /* Conditional Flip Bitwise , LSR ,Set Flag then XOR */
3700 #define E_COND_FBIT_LSR_XORS(cond, dest, roperand, r2shift, shift5)                                                   \
3701     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3702         (3 << 29) + (1 << 18) + (0 << 19)
3703 
3704 /* Conditional Flip Bitwise , LSR , ADD */
3705 #define E_COND_FBIT_LSR_ADD(cond, dest, roperand, r2shift, shift5)                                                    \
3706     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3707         (4 << 29) + (1 << 18) + (0 << 19)
3708 /* Conditional Flip Bitwise , LSR ,Set Flag then ADD */
3709 #define E_COND_FBIT_LSR_ADDS(cond, dest, roperand, r2shift, shift5)                                                   \
3710     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3711         (4 << 29) + (1 << 18) + (0 << 19)
3712 
3713 /* Conditional Flip Bitwise , LSR , SUB */
3714 #define E_COND_FBIT_LSR_SUB(cond, dest, roperand, r2shift, shift5)                                                    \
3715     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3716         (5 << 29) + (1 << 18) + (0 << 19)
3717 /* Conditional Flip Bitwise , LSR ,Set Flag then SUB */
3718 #define E_COND_FBIT_LSR_SUBS(cond, dest, roperand, r2shift, shift5)                                                   \
3719     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3720         (5 << 29) + (1 << 18) + (0 << 19)
3721 
3722 /* Conditional Flip Bitwise , LSR , ADC */
3723 #define E_COND_FBIT_LSR_ADC(cond, dest, roperand, r2shift, shift5)                                                    \
3724     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3725         (6 << 29) + (1 << 18) + (0 << 19)
3726 /* Conditional Flip Bitwise , LSR ,Set Flag then ADC */
3727 #define E_COND_FBIT_LSR_ADCS(cond, dest, roperand, r2shift, shift5)                                                   \
3728     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3729         (6 << 29) + (1 << 18) + (0 << 19)
3730 
3731 /* Conditional Flip Bitwise , LSR , SBC */
3732 #define E_COND_FBIT_LSR_SBC(cond, dest, roperand, r2shift, shift5)                                                    \
3733     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3734         (7 << 29) + (1 << 18) + (0 << 19)
3735 /* Conditional Flip Bitwise , LSR ,Set Flag then SBC */
3736 #define E_COND_FBIT_LSR_SBCS(cond, dest, roperand, r2shift, shift5)                                                   \
3737     DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \
3738         (7 << 29) + (1 << 18) + (0 << 19)
3739 
3740 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3741 /*                                       E_ANDOR */
3742 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3743 /*                                                         opcode      Dest            Src1               src2 SFlag */
3744 /*                                                         Cond         SRC3 */
3745 
3746 /* ANDOR */
3747 #define E_ANDOR(dest, rsrc, rand, ror) \
3748     DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (EU << 5) + (ror << 24)
3749 #define E_ANDORS(dest, rsrc, rand, ror) \
3750     DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (EU << 5) + (ror << 24)
3751 #define E_COND_ANDOR(cond, dest, rsrc, rand, ror) \
3752     DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (cond << 5) + (ror << 24)
3753 #define E_COND_ANDORS(cond, dest, rsrc, rand, ror) \
3754     DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (cond << 5) + (ror << 24)
3755 
3756 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3757 /*                                       E_Shift byte reg Codes */
3758 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
3759 
3760 /*                                                         opcode      Dest            Src1              src2 SFlag Cond
3761  */
3762 /*                                                         Imm                    Extra Operation    Left/Right */
3763 /*                                                         Shift/Rotate    Invert */
3764 
3765 /* Logical Shift */
3766 #define E_RLSL(dest, r2shift, rshift)                                                                        \
3767     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3768         (0 << 19) + (0 << 18)
3769 #define E_RLSR(dest, r2shift, rshift)                                                                        \
3770     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3771         (1 << 19) + (0 << 18)
3772 /* Logical Shift and Set Flag */
3773 #define E_RLSLS(dest, r2shift, rshift)                                                                       \
3774     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3775         (0 << 19) + (0 << 18)
3776 #define E_RLSRS(dest, r2shift, rshift)                                                                       \
3777     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3778         (1 << 19) + (0 << 18)
3779 
3780 /* Logical Shift and then AND */
3781 #define E_RLSL_AND(dest, roperand, r2shift, rshift)                                                                 \
3782     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3783         (1 << 29) + (0 << 19) + (0 << 18)
3784 #define E_RLSR_AND(dest, roperand, r2shift, rshift)                                                                 \
3785     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3786         (1 << 29) + (1 << 19) + (0 << 18)
3787 /* Logical Shift and Set Flag then AND */
3788 #define E_RLSL_ANDS(dest, roperand, r2shift, rshift)                                                                \
3789     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3790         (1 << 29) + (0 << 19) + (0 << 18)
3791 #define E_RLSR_ANDS(dest, roperand, r2shift, rshift)                                                                \
3792     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3793         (1 << 29) + (1 << 19) + (0 << 18)
3794 
3795 /* Logical Shift and then OR */
3796 #define E_RLSL_OR(dest, roperand, r2shift, rshift)                                                                  \
3797     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3798         (2 << 29) + (0 << 19) + (0 << 18)
3799 #define E_RLSR_OR(dest, roperand, r2shift, rshift)                                                                  \
3800     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3801         (2 << 29) + (1 << 19) + (0 << 18)
3802 /* Logical Shift and Set Flag then OR */
3803 #define E_RLSL_ORS(dest, roperand, r2shift, rshift)                                                                 \
3804     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3805         (2 << 29) + (0 << 19) + (0 << 18)
3806 #define E_RLSR_ORS(dest, roperand, r2shift, rshift)                                                                 \
3807     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3808         (2 << 29) + (1 << 19) + (0 << 18)
3809 
3810 /* Logical Shift and then XOR */
3811 #define E_RLSL_XOR(dest, roperand, r2shift, rshift)                                                                 \
3812     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3813         (3 << 29) + (0 << 19) + (0 << 18)
3814 #define E_RLSR_XOR(dest, roperand, r2shift, rshift)                                                                 \
3815     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3816         (3 << 29) + (1 << 19) + (0 << 18)
3817 /* Logical Shift and Set Flag then XOR */
3818 #define E_RLSL_XORS(dest, roperand, r2shift, rshift)                                                                \
3819     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3820         (3 << 29) + (0 << 19) + (0 << 18)
3821 #define E_RLSR_XORS(dest, roperand, r2shift, rshift)                                                                \
3822     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3823         (3 << 29) + (1 << 19) + (0 << 18)
3824 
3825 /* Logical Shift and then ADD */
3826 #define E_RLSL_ADD(dest, roperand, r2shift, rshift)                                                                 \
3827     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3828         (4 << 29) + (0 << 19) + (0 << 18)
3829 #define E_RLSR_ADD(dest, roperand, r2shift, rshift)                                                                 \
3830     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3831         (4 << 29) + (1 << 19) + (0 << 18)
3832 /* Logical Shift and Set Flag then ADD */
3833 #define E_RLSL_ADDS(dest, roperand, r2shift, rshift)                                                                \
3834     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3835         (4 << 29) + (0 << 19) + (0 << 18)
3836 #define E_RLSR_ADDS(dest, roperand, r2shift, rshift)                                                                \
3837     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3838         (4 << 29) + (1 << 19) + (0 << 18)
3839 
3840 /* Logical Shift and then SUB */
3841 #define E_RLSL_SUB(dest, roperand, r2shift, rshift)                                                                 \
3842     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3843         (5 << 29) + (0 << 19) + (0 << 18)
3844 #define E_RLSR_SUB(dest, roperand, r2shift, rshift)                                                                 \
3845     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3846         (5 << 29) + (1 << 19) + (0 << 18)
3847 /* Logical Shift and Set Flag then SUB */
3848 #define E_RLSL_SUBS(dest, roperand, r2shift, rshift)                                                                \
3849     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3850         (5 << 29) + (0 << 19) + (0 << 18)
3851 #define E_RLSR_SUBS(dest, roperand, r2shift, rshift)                                                                \
3852     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3853         (5 << 29) + (1 << 19) + (0 << 18)
3854 
3855 /* Logical Shift and then ADC */
3856 #define E_RLSL_ADC(dest, roperand, r2shift, rshift)                                                                 \
3857     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3858         (6 << 29) + (0 << 19) + (0 << 18)
3859 #define E_RLSR_ADC(dest, roperand, r2shift, rshift)                                                                 \
3860     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3861         (6 << 29) + (1 << 19) + (0 << 18)
3862 /* Logical Shift and Set Flag then ADC */
3863 #define E_RLSL_ADCS(dest, roperand, r2shift, rshift)                                                                \
3864     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3865         (6 << 29) + (0 << 19) + (0 << 18)
3866 #define E_RLSR_ADCS(dest, roperand, r2shift, rshift)                                                                \
3867     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3868         (6 << 29) + (1 << 19) + (0 << 18)
3869 
3870 /* Logical Shift and then SBC */
3871 #define E_RLSL_SBC(dest, roperand, r2shift, rshift)                                                                 \
3872     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3873         (7 << 29) + (0 << 19) + (0 << 18)
3874 #define E_RLSR_SBC(dest, roperand, r2shift, rshift)                                                                 \
3875     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3876         (7 << 29) + (1 << 19) + (0 << 18)
3877 /* Logical Shift and Set Flag then SBC */
3878 #define E_RLSL_SBCS(dest, roperand, r2shift, rshift)                                                                \
3879     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3880         (7 << 29) + (0 << 19) + (0 << 18)
3881 #define E_RLSR_SBCS(dest, roperand, r2shift, rshift)                                                                \
3882     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
3883         (7 << 29) + (1 << 19) + (0 << 18)
3884 
3885 /* Conditional */
3886 /* Logical Shift */
3887 #define E_COND_RLSL(cond, dest, r2shift, rshift)                                                               \
3888     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3889         (0 << 19) + (0 << 18)
3890 #define E_COND_RLSR(cond, dest, r2shift, rshift)                                                               \
3891     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3892         (1 << 19) + (0 << 18)
3893 /* Logical Shift and Set Flag */
3894 #define E_COND_RLSLS(cond, dest, r2shift, rshift)                                                              \
3895     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3896         (0 << 19) + (0 << 18)
3897 #define E_COND_RLSRS(cond, dest, r2shift, rshift)                                                              \
3898     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
3899         (1 << 19) + (0 << 18)
3900 
3901 /* Logical Shift and then AND */
3902 #define E_COND_RLSL_AND(cond, dest, roperand, r2shift, rshift)                                                        \
3903     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3904         (1 << 29) + (0 << 19) + (0 << 18)
3905 #define E_COND_RLSR_AND(cond, dest, roperand, r2shift, rshift)                                                        \
3906     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3907         (1 << 29) + (1 << 19) + (0 << 18)
3908 /* Logical Shift and Set Flag then AND */
3909 #define E_COND_RLSL_ANDS(cond, dest, roperand, r2shift, rshift)                                                       \
3910     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3911         (1 << 29) + (0 << 19) + (0 << 18)
3912 #define E_COND_RLSR_ANDS(cond, dest, roperand, r2shift, rshift)                                                       \
3913     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3914         (1 << 29) + (1 << 19) + (0 << 18)
3915 
3916 /* Logical Shift and then OR */
3917 #define E_COND_RLSL_OR(cond, dest, roperand, r2shift, rshift)                                                         \
3918     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3919         (2 << 29) + (0 << 19) + (0 << 18)
3920 #define E_COND_RLSR_OR(cond, dest, roperand, r2shift, rshift)                                                         \
3921     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3922         (2 << 29) + (1 << 19) + (0 << 18)
3923 /* Logical Shift and Set Flag then OR */
3924 #define E_COND_RLSL_ORS(cond, dest, roperand, r2shift, rshift)                                                        \
3925     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3926         (2 << 29) + (0 << 19) + (0 << 18)
3927 #define E_COND_RLSR_ORS(cond, dest, roperand, r2shift, rshift)                                                        \
3928     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3929         (2 << 29) + (1 << 19) + (0 << 18)
3930 
3931 /* Logical Shift and then XOR */
3932 #define E_COND_RLSL_XOR(cond, dest, roperand, r2shift, rshift)                                                        \
3933     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3934         (3 << 29) + (0 << 19) + (0 << 18)
3935 #define E_COND_RLSR_XOR(cond, dest, roperand, r2shift, rshift)                                                        \
3936     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3937         (3 << 29) + (1 << 19) + (0 << 18)
3938 /* Logical Shift and Set Flag then XOR */
3939 #define E_COND_RLSL_XORS(cond, dest, roperand, r2shift, rshift)                                                       \
3940     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3941         (3 << 29) + (0 << 19) + (0 << 18)
3942 #define E_COND_RLSR_XORS(cond, dest, roperand, r2shift, rshift)                                                       \
3943     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3944         (3 << 29) + (1 << 19) + (0 << 18)
3945 
3946 /* Logical Shift and then ADD */
3947 #define E_COND_RLSL_ADD(cond, dest, roperand, r2shift, rshift)                                                        \
3948     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3949         (4 << 29) + (0 << 19) + (0 << 18)
3950 #define E_COND_RLSR_ADD(cond, dest, roperand, r2shift, rshift)                                                        \
3951     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3952         (4 << 29) + (1 << 19) + (0 << 18)
3953 /* Logical Shift and Set Flag then ADD */
3954 #define E_COND_RLSL_ADDS(cond, dest, roperand, r2shift, rshift)                                                       \
3955     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3956         (4 << 29) + (0 << 19) + (0 << 18)
3957 #define E_COND_RLSR_ADDS(cond, dest, roperand, r2shift, rshift)                                                       \
3958     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3959         (4 << 29) + (1 << 19) + (0 << 18)
3960 
3961 /* Logical Shift and then SUB */
3962 #define E_COND_RLSL_SUB(cond, dest, roperand, r2shift, rshift)                                                        \
3963     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3964         (5 << 29) + (0 << 19) + (0 << 18)
3965 #define E_COND_RLSR_SUB(cond, dest, roperand, r2shift, rshift)                                                        \
3966     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3967         (5 << 29) + (1 << 19) + (0 << 18)
3968 /* Logical Shift and Set Flag then SUB */
3969 #define E_COND_RLSL_SUBS(cond, dest, roperand, r2shift, rshift)                                                       \
3970     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3971         (5 << 29) + (0 << 19) + (0 << 18)
3972 #define E_COND_RLSR_SUBS(cond, dest, roperand, r2shift, rshift)                                                       \
3973     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3974         (5 << 29) + (1 << 19) + (0 << 18)
3975 
3976 /* Logical Shift and then ADC */
3977 #define E_COND_RLSL_ADC(cond, dest, roperand, r2shift, rshift)                                                        \
3978     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3979         (6 << 29) + (0 << 19) + (0 << 18)
3980 #define E_COND_RLSR_ADC(cond, dest, roperand, r2shift, rshift)                                                        \
3981     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3982         (6 << 29) + (1 << 19) + (0 << 18)
3983 /* Logical Shift and Set Flag then ADC */
3984 #define E_COND_RLSL_ADCS(cond, dest, roperand, r2shift, rshift)                                                       \
3985     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3986         (6 << 29) + (0 << 19) + (0 << 18)
3987 #define E_COND_RLSR_ADCS(cond, dest, roperand, r2shift, rshift)                                                       \
3988     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3989         (6 << 29) + (1 << 19) + (0 << 18)
3990 
3991 /* Logical Shift and then SBC */
3992 #define E_COND_RLSL_SBC(cond, dest, roperand, r2shift, rshift)                                                        \
3993     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3994         (7 << 29) + (0 << 19) + (0 << 18)
3995 #define E_COND_RLSR_SBC(cond, dest, roperand, r2shift, rshift)                                                        \
3996     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
3997         (7 << 29) + (1 << 19) + (0 << 18)
3998 /* Logical Shift and Set Flag then SBC */
3999 #define E_COND_RLSL_SBCS(cond, dest, roperand, r2shift, rshift)                                                       \
4000     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4001         (7 << 29) + (0 << 19) + (0 << 18)
4002 #define E_COND_RLSR_SBCS(cond, dest, roperand, r2shift, rshift)                                                       \
4003     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4004         (7 << 29) + (1 << 19) + (0 << 18)
4005 
4006 /*                                                         opcode      Dest            Src1              r2shift SFlag
4007  */
4008 /*                                                         Cond         Imm                    Extra Operation */
4009 /*                                                         Left/Right   Shift/Rotate  POSTshift */
4010 
4011 /* Logical Shift and then AND */
4012 #define E_AND_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4013     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4014         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4015 #define E_AND_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4016     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4017         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4018 /* Logical Shift and Set Flag then AND */
4019 #define E_AND_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4020     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4021         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4022 #define E_AND_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4023     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4024         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4025 
4026 /* Logical Shift and then OR */
4027 #define E_OR_RLSL(dest, roperand, r2shift, rshift)                                                                  \
4028     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4029         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4030 #define E_OR_RLSR(dest, roperand, r2shift, rshift)                                                                  \
4031     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4032         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4033 /* Logical Shift and Set Flag then OR */
4034 #define E_OR_RLSLS(dest, roperand, r2shift, rshift)                                                                 \
4035     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4036         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4037 #define E_OR_RLSRS(dest, roperand, r2shift, rshift)                                                                 \
4038     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4039         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4040 
4041 /* Logical Shift and then XOR */
4042 #define E_XOR_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4043     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4044         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4045 #define E_XOR_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4046     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4047         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4048 /* Logical Shift and Set Flag then XOR */
4049 #define E_XOR_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4050     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4051         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4052 #define E_XOR_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4053     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4054         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4055 
4056 /* Logical Shift and then ADD */
4057 #define E_ADD_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4058     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4059         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4060 #define E_ADD_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4061     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4062         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4063 /* Logical Shift and Set Flag then ADD */
4064 #define E_ADD_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4065     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4066         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4067 #define E_ADD_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4068     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4069         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4070 
4071 /* Logical Shift and then SUB */
4072 #define E_SUB_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4073     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4074         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4075 #define E_SUB_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4076     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4077         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4078 /* Logical Shift and Set Flag then SUB */
4079 #define E_SUB_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4080     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4081         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4082 #define E_SUB_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4083     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4084         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4085 
4086 /* Logical Shift and then ADC */
4087 #define E_ADC_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4088     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4089         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4090 #define E_ADC_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4091     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4092         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4093 /* Logical Shift and Set Flag then ADC */
4094 #define E_ADC_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4095     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4096         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4097 #define E_ADC_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4098     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4099         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4100 
4101 /* Logical Shift and then SBC */
4102 #define E_SBC_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4103     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4104         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4105 #define E_SBC_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4106     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4107         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4108 /* Logical Shift and Set Flag then SBC */
4109 #define E_SBC_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4110     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4111         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4112 #define E_SBC_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4113     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4114         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4115 
4116 /* Conditional */
4117 
4118 /* Logical Shift and then AND */
4119 #define E_COND_AND_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4120     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4121         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4122 #define E_COND_AND_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4123     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4124         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4125 /* Logical Shift and Set Flag then AND */
4126 #define E_COND_AND_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4127     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4128         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4129 #define E_COND_AND_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4130     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4131         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4132 
4133 /* Logical Shift and then OR */
4134 #define E_COND_OR_RLSL(cond, dest, roperand, r2shift, rshift)                                                         \
4135     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4136         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4137 #define E_COND_OR_RLSR(cond, dest, roperand, r2shift, rshift)                                                         \
4138     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4139         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4140 /* Logical Shift and Set Flag then OR */
4141 #define E_COND_OR_RLSLS(cond, dest, roperand, r2shift, rshift)                                                        \
4142     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4143         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4144 #define E_COND_OR_RLSRS(cond, dest, roperand, r2shift, rshift)                                                        \
4145     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4146         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4147 
4148 /* Logical Shift and then XOR */
4149 #define E_COND_XOR_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4150     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4151         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4152 #define E_COND_XOR_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4153     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4154         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4155 /* Logical Shift and Set Flag then XOR */
4156 #define E_COND_XOR_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4157     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4158         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4159 #define E_COND_XOR_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4160     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4161         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4162 
4163 /* Logical Shift and then ADD */
4164 #define E_COND_ADD_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4165     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4166         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4167 #define E_COND_ADD_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4168     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4169         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4170 /* Logical Shift and Set Flag then ADD */
4171 #define E_COND_ADD_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4172     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4173         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4174 #define E_COND_ADD_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4175     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4176         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4177 
4178 /* Logical Shift and then SUB */
4179 #define E_COND_SUB_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4180     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4181         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4182 #define E_COND_SUB_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4183     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4184         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4185 /* Logical Shift and Set Flag then SUB */
4186 #define E_COND_SUB_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4187     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4188         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4189 #define E_COND_SUB_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4190     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4191         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4192 
4193 /* Logical Shift and then ADC */
4194 #define E_COND_ADC_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4195     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4196         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4197 #define E_COND_ADC_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4198     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4199         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4200 /* Logical Shift and Set Flag then ADC */
4201 #define E_COND_ADC_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4202     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4203         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4204 #define E_COND_ADC_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4205     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4206         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4207 
4208 /* Logical Shift and then SBC */
4209 #define E_COND_SBC_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4210     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4211         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4212 #define E_COND_SBC_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4213     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4214         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4215 /* Logical Shift and Set Flag then SBC */
4216 #define E_COND_SBC_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4217     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4218         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28)
4219 #define E_COND_SBC_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4220     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4221         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28)
4222 
4223 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4224 /*                                       E_Shift byte reg with inversion */
4225 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4226 
4227 /* Logical Shift */
4228 #define E_RLSLN(dest, r2shift, rshift)                                                                       \
4229     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4230         (0 << 19) + (0 << 18) + (1 << 27)
4231 #define E_RLSRN(dest, r2shift, rshift)                                                                       \
4232     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4233         (1 << 19) + (0 << 18) + (1 << 27)
4234 /* Logical Shift and Set Flag */
4235 #define E_RLSLNS(dest, r2shift, rshift)                                                                      \
4236     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4237         (0 << 19) + (0 << 18) + (1 << 27)
4238 #define E_RLSRNS(dest, r2shift, rshift)                                                                      \
4239     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4240         (1 << 19) + (0 << 18) + (1 << 27)
4241 
4242 /* Logical Shift and then AND */
4243 #define E_RLSL_ANDN(dest, roperand, r2shift, rshift)                                                                \
4244     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4245         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4246 #define E_RLSR_ANDN(dest, roperand, r2shift, rshift)                                                                \
4247     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4248         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4249 /* Logical Shift and Set Flag then AND */
4250 #define E_RLSL_ANDNS(dest, roperand, r2shift, rshift)                                                               \
4251     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4252         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4253 #define E_RLSR_ANDNS(dest, roperand, r2shift, rshift)                                                               \
4254     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4255         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4256 
4257 /* Logical Shift and then OR */
4258 #define E_RLSL_ORN(dest, roperand, r2shift, rshift)                                                                 \
4259     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4260         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4261 #define E_RLSR_ORN(dest, roperand, r2shift, rshift)                                                                 \
4262     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4263         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4264 /* Logical Shift and Set Flag then OR */
4265 #define E_RLSL_ORNS(dest, roperand, r2shift, rshift)                                                                \
4266     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4267         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4268 #define E_RLSR_ORNS(dest, roperand, r2shift, rshift)                                                                \
4269     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4270         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4271 
4272 /* Logical Shift and then XOR */
4273 #define E_RLSL_XORN(dest, roperand, r2shift, rshift)                                                                \
4274     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4275         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4276 #define E_RLSR_XORN(dest, roperand, r2shift, rshift)                                                                \
4277     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4278         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4279 /* Logical Shift and Set Flag then XOR */
4280 #define E_RLSL_XORNS(dest, roperand, r2shift, rshift)                                                               \
4281     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4282         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4283 #define E_RLSR_XORNS(dest, roperand, r2shift, rshift)                                                               \
4284     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4285         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4286 
4287 /* Logical Shift and then ADD */
4288 #define E_RLSL_ADDN(dest, roperand, r2shift, rshift)                                                                \
4289     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4290         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4291 #define E_RLSR_ADDN(dest, roperand, r2shift, rshift)                                                                \
4292     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4293         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4294 /* Logical Shift and Set Flag then ADD */
4295 #define E_RLSL_ADDNS(dest, roperand, r2shift, rshift)                                                               \
4296     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4297         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4298 #define E_RLSR_ADDNS(dest, roperand, r2shift, rshift)                                                               \
4299     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4300         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4301 
4302 /* Logical Shift and then SUB */
4303 #define E_RLSL_SUBN(dest, roperand, r2shift, rshift)                                                                \
4304     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4305         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4306 #define E_RLSR_SUBN(dest, roperand, r2shift, rshift)                                                                \
4307     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4308         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4309 /* Logical Shift and Set Flag then SUB */
4310 #define E_RLSL_SUBNS(dest, roperand, r2shift, rshift)                                                               \
4311     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4312         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4313 #define E_RLSR_SUBNS(dest, roperand, r2shift, rshift)                                                               \
4314     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4315         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4316 
4317 /* Logical Shift and then ADC */
4318 #define E_RLSL_ADCN(dest, roperand, r2shift, rshift)                                                                \
4319     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4320         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4321 #define E_RLSR_ADCN(dest, roperand, r2shift, rshift)                                                                \
4322     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4323         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4324 /* Logical Shift and Set Flag then ADC */
4325 #define E_RLSL_ADCNS(dest, roperand, r2shift, rshift)                                                               \
4326     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4327         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4328 #define E_RLSR_ADCNS(dest, roperand, r2shift, rshift)                                                               \
4329     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4330         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4331 
4332 /* Logical Shift and then SBC */
4333 #define E_RLSL_SBCN(dest, roperand, r2shift, rshift)                                                                \
4334     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4335         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4336 #define E_RLSR_SBCN(dest, roperand, r2shift, rshift)                                                                \
4337     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4338         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4339 /* Logical Shift and Set Flag then SBC */
4340 #define E_RLSL_SBCNS(dest, roperand, r2shift, rshift)                                                               \
4341     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4342         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4343 #define E_RLSR_SBCNS(dest, roperand, r2shift, rshift)                                                               \
4344     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4345         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4346 
4347 /* Conditional */
4348 /* Logical Shift */
4349 #define E_COND_RLSLN(cond, dest, r2shift, rshift)                                                              \
4350     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4351         (0 << 19) + (0 << 18) + (1 << 27)
4352 #define E_COND_RLSRN(cond, dest, r2shift, rshift)                                                              \
4353     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4354         (1 << 19) + (0 << 18) + (1 << 27)
4355 /* Logical Shift and Set Flag */
4356 #define E_COND_RLSLNS(cond, dest, r2shift, rshift)                                                             \
4357     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4358         (0 << 19) + (0 << 18) + (1 << 27)
4359 #define E_COND_RLSRNS(cond, dest, r2shift, rshift)                                                             \
4360     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4361         (1 << 19) + (0 << 18) + (1 << 27)
4362 
4363 /* Logical Shift and then AND */
4364 #define E_COND_RLSL_ANDN(cond, dest, roperand, r2shift, rshift)                                                       \
4365     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4366         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4367 #define E_COND_RLSR_ANDN(cond, dest, roperand, r2shift, rshift)                                                       \
4368     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4369         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4370 /* Logical Shift and Set Flag then AND */
4371 #define E_COND_RLSL_ANDNS(cond, dest, roperand, r2shift, rshift)                                                      \
4372     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4373         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4374 #define E_COND_RLSR_ANDNS(cond, dest, roperand, r2shift, rshift)                                                      \
4375     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4376         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4377 
4378 /* Logical Shift and then OR */
4379 #define E_COND_RLSL_ORN(cond, dest, roperand, r2shift, rshift)                                                        \
4380     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4381         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4382 #define E_COND_RLSR_ORN(cond, dest, roperand, r2shift, rshift)                                                        \
4383     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4384         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4385 /* Logical Shift and Set Flag then OR */
4386 #define E_COND_RLSL_ORNS(cond, dest, roperand, r2shift, rshift)                                                       \
4387     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4388         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4389 #define E_COND_RLSR_ORNS(cond, dest, roperand, r2shift, rshift)                                                       \
4390     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4391         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4392 
4393 /* Logical Shift and then XOR */
4394 #define E_COND_RLSL_XORN(cond, dest, roperand, r2shift, rshift)                                                       \
4395     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4396         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4397 #define E_COND_RLSR_XORN(cond, dest, roperand, r2shift, rshift)                                                       \
4398     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4399         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4400 /* Logical Shift and Set Flag then XOR */
4401 #define E_COND_RLSL_XORNS(cond, dest, roperand, r2shift, rshift)                                                      \
4402     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4403         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4404 #define E_COND_RLSR_XORNS(cond, dest, roperand, r2shift, rshift)                                                      \
4405     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4406         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4407 
4408 /* Logical Shift and then ADD */
4409 #define E_COND_RLSL_ADDN(cond, dest, roperand, r2shift, rshift)                                                       \
4410     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4411         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4412 #define E_COND_RLSR_ADDN(cond, dest, roperand, r2shift, rshift)                                                       \
4413     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4414         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4415 /* Logical Shift and Set Flag then ADD */
4416 #define E_COND_RLSL_ADDNS(cond, dest, roperand, r2shift, rshift)                                                      \
4417     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4418         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4419 #define E_COND_RLSR_ADDNS(cond, dest, roperand, r2shift, rshift)                                                      \
4420     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4421         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4422 
4423 /* Logical Shift and then SUB */
4424 #define E_COND_RLSL_SUBN(cond, dest, roperand, r2shift, rshift)                                                       \
4425     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4426         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4427 #define E_COND_RLSR_SUBN(cond, dest, roperand, r2shift, rshift)                                                       \
4428     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4429         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4430 /* Logical Shift and Set Flag then SUB */
4431 #define E_COND_RLSL_SUBNS(cond, dest, roperand, r2shift, rshift)                                                      \
4432     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4433         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4434 #define E_COND_RLSR_SUBNS(cond, dest, roperand, r2shift, rshift)                                                      \
4435     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4436         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4437 
4438 /* Logical Shift and then ADC */
4439 #define E_COND_RLSL_ADCN(cond, dest, roperand, r2shift, rshift)                                                       \
4440     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4441         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4442 #define E_COND_RLSR_ADCN(cond, dest, roperand, r2shift, rshift)                                                       \
4443     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4444         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4445 /* Logical Shift and Set Flag then ADC */
4446 #define E_COND_RLSL_ADCNS(cond, dest, roperand, r2shift, rshift)                                                      \
4447     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4448         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4449 #define E_COND_RLSR_ADCNS(cond, dest, roperand, r2shift, rshift)                                                      \
4450     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4451         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4452 
4453 /* Logical Shift and then SBC */
4454 #define E_COND_RLSL_SBCN(cond, dest, roperand, r2shift, rshift)                                                       \
4455     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4456         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4457 #define E_COND_RLSR_SBCN(cond, dest, roperand, r2shift, rshift)                                                       \
4458     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4459         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4460 /* Logical Shift and Set Flag then SBC */
4461 #define E_COND_RLSL_SBCNS(cond, dest, roperand, r2shift, rshift)                                                      \
4462     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4463         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27)
4464 #define E_COND_RLSR_SBCNS(cond, dest, roperand, r2shift, rshift)                                                      \
4465     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4466         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27)
4467 
4468 /*                                                         opcode      Dest            Src1              r2shift SFlag
4469  */
4470 /*                                                         Cond         Imm                    Extra Operation */
4471 /*                                                         Left/Right   Shift/Rotate   Inv  POSTshift */
4472 
4473 /* Logical Shift and then AND */
4474 #define E_ANDN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4475     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4476         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4477 #define E_ANDN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4478     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4479         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4480 /* Logical Shift and Set Flag then AND */
4481 #define E_ANDN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4482     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4483         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4484 #define E_ANDN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4485     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4486         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4487 
4488 /* Logical Shift and then OR */
4489 #define E_ORN_RLSL(dest, roperand, r2shift, rshift)                                                                 \
4490     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4491         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4492 #define E_ORN_RLSR(dest, roperand, r2shift, rshift)                                                                 \
4493     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4494         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4495 /* Logical Shift and Set Flag then OR */
4496 #define E_ORN_RLSLS(dest, roperand, r2shift, rshift)                                                                \
4497     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4498         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4499 #define E_ORN_RLSRS(dest, roperand, r2shift, rshift)                                                                \
4500     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4501         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4502 
4503 /* Logical Shift and then XOR */
4504 #define E_XORN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4505     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4506         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4507 #define E_XORN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4508     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4509         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4510 /* Logical Shift and Set Flag then XOR */
4511 #define E_XORN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4512     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4513         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4514 #define E_XORN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4515     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4516         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4517 
4518 /* Logical Shift and then ADD */
4519 #define E_ADDN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4520     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4521         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4522 #define E_ADDN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4523     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4524         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4525 /* Logical Shift and Set Flag then ADD */
4526 #define E_ADDN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4527     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4528         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4529 #define E_ADDN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4530     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4531         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4532 
4533 /* Logical Shift and then SUB */
4534 #define E_SUBN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4535     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4536         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4537 #define E_SUBN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4538     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4539         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4540 /* Logical Shift and Set Flag then SUB */
4541 #define E_SUBN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4542     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4543         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4544 #define E_SUBN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4545     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4546         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4547 
4548 /* Logical Shift and then ADC */
4549 #define E_ADCN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4550     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4551         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4552 #define E_ADCN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4553     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4554         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4555 /* Logical Shift and Set Flag then ADC */
4556 #define E_ADCN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4557     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4558         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4559 #define E_ADCN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4560     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4561         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4562 
4563 /* Logical Shift and then SBC */
4564 #define E_SBCN_RLSL(dest, roperand, r2shift, rshift)                                                                \
4565     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4566         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4567 #define E_SBCN_RLSR(dest, roperand, r2shift, rshift)                                                                \
4568     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4569         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4570 /* Logical Shift and Set Flag then SBC */
4571 #define E_SBCN_RLSLS(dest, roperand, r2shift, rshift)                                                               \
4572     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4573         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4574 #define E_SBCN_RLSRS(dest, roperand, r2shift, rshift)                                                               \
4575     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4576         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4577 
4578 /* Conditional */
4579 
4580 /* Logical Shift and then AND */
4581 #define E_COND_ANDN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4582     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4583         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4584 #define E_COND_ANDN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4585     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4586         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4587 /* Logical Shift and Set Flag then AND */
4588 #define E_COND_ANDN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4589     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4590         (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4591 #define E_COND_ANDN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4592     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4593         (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4594 
4595 /* Logical Shift and then OR */
4596 #define E_COND_ORN_RLSL(cond, dest, roperand, r2shift, rshift)                                                        \
4597     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4598         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4599 #define E_COND_ORN_RLSR(cond, dest, roperand, r2shift, rshift)                                                        \
4600     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4601         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4602 /* Logical Shift and Set Flag then OR */
4603 #define E_COND_ORN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                       \
4604     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4605         (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4606 #define E_COND_ORN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                       \
4607     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4608         (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4609 
4610 /* Logical Shift and then XOR */
4611 #define E_COND_XORN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4612     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4613         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4614 #define E_COND_XORN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4615     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4616         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4617 /* Logical Shift and Set Flag then XOR */
4618 #define E_COND_XORN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4619     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4620         (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4621 #define E_COND_XORN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4622     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4623         (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4624 
4625 /* Logical Shift and then ADD */
4626 #define E_COND_ADDN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4627     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4628         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4629 #define E_COND_ADDN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4630     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4631         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4632 /* Logical Shift and Set Flag then ADD */
4633 #define E_COND_ADDN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4634     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4635         (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4636 #define E_COND_ADDN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4637     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4638         (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4639 
4640 /* Logical Shift and then SUB */
4641 #define E_COND_SUBN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4642     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4643         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4644 #define E_COND_SUBN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4645     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4646         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4647 /* Logical Shift and Set Flag then SUB */
4648 #define E_COND_SUBN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4649     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4650         (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4651 #define E_COND_SUBN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4652     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4653         (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4654 
4655 /* Logical Shift and then ADC */
4656 #define E_COND_ADCN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4657     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4658         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4659 #define E_COND_ADCN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4660     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4661         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4662 /* Logical Shift and Set Flag then ADC */
4663 #define E_COND_ADCN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4664     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4665         (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4666 #define E_COND_ADCN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4667     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4668         (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4669 
4670 /* Logical Shift and then SBC */
4671 #define E_COND_SBCN_RLSL(cond, dest, roperand, r2shift, rshift)                                                       \
4672     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4673         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4674 #define E_COND_SBCN_RLSR(cond, dest, roperand, r2shift, rshift)                                                       \
4675     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4676         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4677 /* Logical Shift and Set Flag then SBC */
4678 #define E_COND_SBCN_RLSLS(cond, dest, roperand, r2shift, rshift)                                                      \
4679     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4680         (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4681 #define E_COND_SBCN_RLSRS(cond, dest, roperand, r2shift, rshift)                                                      \
4682     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4683         (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28)
4684 
4685 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4686 /*                                       E_ROTATE by Reg Codes */
4687 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4688 
4689 /*                                                         opcode      Dest            Src1              r2shift SFlag
4690  */
4691 /*                                                         Cond         Imm                   Extra Operation Left/Right
4692  */
4693 /*                                                         Shift/Rotate */
4694 
4695 /* Rotate */
4696 #define E_RROR(dest, r2shift, rshift)                                                                        \
4697     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4698         (1 << 19) + (1 << 18)
4699 /* Rotate and Set Flag */
4700 #define E_RRORS(dest, r2shift, rshift)                                                                       \
4701     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4702         (1 << 19) + (1 << 18)
4703 
4704 /* Rotate and then AND */
4705 #define E_RROR_AND(dest, roperand, r2shift, rshift)                                                                 \
4706     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4707         (1 << 29) + (1 << 19) + (1 << 18)
4708 /* Rotate and Set Flag then AND */
4709 #define E_RROR_ANDS(dest, roperand, r2shift, rshift)                                                                \
4710     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4711         (1 << 29) + (1 << 19) + (1 << 18)
4712 
4713 /* Rotate and then OR */
4714 #define E_RROR_OR(dest, roperand, r2shift, rshift)                                                                  \
4715     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4716         (2 << 29) + (1 << 19) + (1 << 18)
4717 /* Rotate and Set Flag then OR */
4718 #define E_RROR_ORS(dest, roperand, r2shift, rshift)                                                                 \
4719     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4720         (2 << 29) + (1 << 19) + (1 << 18)
4721 
4722 /* Rotate and then XOR */
4723 #define E_RROR_XOR(dest, roperand, r2shift, rshift)                                                                 \
4724     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4725         (3 << 29) + (1 << 19) + (1 << 18)
4726 /* Rotate and Set Flag then XOR */
4727 #define E_RROR_XORS(dest, roperand, r2shift, rshift)                                                                \
4728     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4729         (3 << 29) + (1 << 19) + (1 << 18)
4730 
4731 /* Rotate and then ADD */
4732 #define E_RROR_ADD(dest, roperand, r2shift, rshift)                                                                 \
4733     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4734         (4 << 29) + (1 << 19) + (1 << 18)
4735 /* Rotate and Set Flag then ADD */
4736 #define E_RROR_ADDS(dest, roperand, r2shift, rshift)                                                                \
4737     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4738         (4 << 29) + (1 << 19) + (1 << 18)
4739 
4740 /* Rotate and then SUB */
4741 #define E_RROR_SUB(dest, roperand, r2shift, rshift)                                                                 \
4742     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4743         (5 << 29) + (1 << 19) + (1 << 18)
4744 /* Rotate and Set Flag then SUB */
4745 #define E_RROR_SUBS(dest, roperand, r2shift, rshift)                                                                \
4746     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4747         (5 << 29) + (1 << 19) + (1 << 18)
4748 
4749 /* Rotate and then ADC */
4750 #define E_RROR_ADC(dest, roperand, r2shift, rshift)                                                                 \
4751     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4752         (6 << 29) + (1 << 19) + (1 << 18)
4753 /* Rotate and Set Flag then ADC */
4754 #define E_RROR_ADCS(dest, roperand, r2shift, rshift)                                                                \
4755     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4756         (6 << 29) + (1 << 19) + (1 << 18)
4757 
4758 /* Rotate and then SBC */
4759 #define E_RROR_SBC(dest, roperand, r2shift, rshift)                                                                 \
4760     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4761         (7 << 29) + (1 << 19) + (1 << 18)
4762 /* Rotate and Set Flag then SBC */
4763 #define E_RROR_SBCS(dest, roperand, r2shift, rshift)                                                                \
4764     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4765         (7 << 29) + (1 << 19) + (1 << 18)
4766 
4767 /* Conditional */
4768 /* Rotate */
4769 #define E_COND_RROR(cond, dest, r2shift, rshift)                                                               \
4770     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4771         (1 << 19) + (1 << 18)
4772 /* Rotate and Set Flag */
4773 #define E_COND_RRORS(cond, dest, r2shift, rshift)                                                              \
4774     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4775         (1 << 19) + (1 << 18)
4776 
4777 /* Rotate and then AND */
4778 #define E_COND_RROR_AND(cond, dest, roperand, r2shift, rshift)                                                        \
4779     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4780         (1 << 29) + (1 << 19) + (1 << 18)
4781 /* Rotate and Set Flag then AND */
4782 #define E_COND_RROR_ANDS(cond, dest, roperand, r2shift, rshift)                                                       \
4783     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4784         (1 << 29) + (1 << 19) + (1 << 18)
4785 
4786 /* Rotate and then OR */
4787 #define E_COND_RROR_OR(cond, dest, roperand, r2shift, rshift)                                                         \
4788     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4789         (2 << 29) + (1 << 19) + (1 << 18)
4790 /* Rotate and Set Flag then OR */
4791 #define E_COND_RROR_ORS(cond, dest, roperand, r2shift, rshift)                                                        \
4792     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4793         (2 << 29) + (1 << 19) + (1 << 18)
4794 
4795 /* Rotate and then XOR */
4796 #define E_COND_RROR_XOR(cond, dest, roperand, r2shift, rshift)                                                        \
4797     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4798         (3 << 29) + (1 << 19) + (1 << 18)
4799 /* Rotate and Set Flag then XOR */
4800 #define E_COND_RROR_XORS(cond, dest, roperand, r2shift, rshift)                                                       \
4801     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4802         (3 << 29) + (1 << 19) + (1 << 18)
4803 
4804 /* Rotate and then ADD */
4805 #define E_COND_RROR_ADD(cond, dest, roperand, r2shift, rshift)                                                        \
4806     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4807         (4 << 29) + (1 << 19) + (1 << 18)
4808 /* Rotate and Set Flag then ADD */
4809 #define E_COND_RROR_ADDS(cond, dest, roperand, r2shift, rshift)                                                       \
4810     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4811         (4 << 29) + (1 << 19) + (1 << 18)
4812 
4813 /* Rotate and then SUB */
4814 #define E_COND_RROR_SUB(cond, dest, roperand, r2shift, rshift)                                                        \
4815     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4816         (5 << 29) + (1 << 19) + (1 << 18)
4817 /* Rotate and Set Flag then SUB */
4818 #define E_COND_RROR_SUBS(cond, dest, roperand, r2shift, rshift)                                                       \
4819     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4820         (5 << 29) + (1 << 19) + (1 << 18)
4821 
4822 /* Rotate and then ADC */
4823 #define E_COND_RROR_ADC(cond, dest, roperand, r2shift, rshift)                                                        \
4824     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4825         (6 << 29) + (1 << 19) + (1 << 18)
4826 /* Rotate and Set Flag then ADC */
4827 #define E_COND_RROR_ADCS(cond, dest, roperand, r2shift, rshift)                                                       \
4828     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4829         (6 << 29) + (1 << 19) + (1 << 18)
4830 
4831 /* Rotate and then SBC */
4832 #define E_COND_RROR_SBC(cond, dest, roperand, r2shift, rshift)                                                        \
4833     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4834         (7 << 29) + (1 << 19) + (1 << 18)
4835 /* Rotate and Set Flag then SBC */
4836 #define E_COND_RROR_SBCS(cond, dest, roperand, r2shift, rshift)                                                       \
4837     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4838         (7 << 29) + (1 << 19) + (1 << 18)
4839 
4840 /* Rotate and then AND */
4841 #define E_AND_RROR(dest, roperand, r2shift, rshift)                                                                 \
4842     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4843         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4844 /* Rotate and Set Flag then AND */
4845 #define E_AND_RRORS(dest, roperand, r2shift, rshift)                                                                \
4846     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4847         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4848 
4849 /* Rotate and then OR */
4850 #define E_OR_RROR(dest, roperand, r2shift, rshift)                                                                  \
4851     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4852         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4853 /* Rotate and Set Flag then OR */
4854 #define E_OR_RRORS(dest, roperand, r2shift, rshift)                                                                 \
4855     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4856         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4857 
4858 /* Rotate and then XOR */
4859 #define E_XOR_RROR(dest, roperand, r2shift, rshift)                                                                 \
4860     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4861         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4862 /* Rotate and Set Flag then XOR */
4863 #define E_XOR_RRORS(dest, roperand, r2shift, rshift)                                                                \
4864     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4865         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4866 
4867 /* Rotate and then ADD */
4868 #define E_ADD_RROR(dest, roperand, r2shift, rshift)                                                                 \
4869     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4870         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4871 /* Rotate and Set Flag then ADD */
4872 #define E_ADD_RRORS(dest, roperand, r2shift, rshift)                                                                \
4873     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4874         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4875 
4876 /* Rotate and then SUB */
4877 #define E_SUB_RROR(dest, roperand, r2shift, rshift)                                                                 \
4878     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4879         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4880 /* Rotate and Set Flag then SUB */
4881 #define E_SUB_RRORS(dest, roperand, r2shift, rshift)                                                                \
4882     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4883         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4884 
4885 /* Rotate and then ADC */
4886 #define E_ADC_RROR(dest, roperand, r2shift, rshift)                                                                 \
4887     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4888         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4889 /* Rotate and Set Flag then ADC */
4890 #define E_ADC_RRORS(dest, roperand, r2shift, rshift)                                                                \
4891     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4892         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4893 
4894 /* Rotate and then SBC */
4895 #define E_SBC_RROR(dest, roperand, r2shift, rshift)                                                                 \
4896     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4897         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4898 /* Rotate and Set Flag then SBC */
4899 #define E_SBC_RRORS(dest, roperand, r2shift, rshift)                                                                \
4900     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4901         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4902 
4903 /* Conditional */
4904 
4905 /* Rotate and then AND */
4906 #define E_COND_AND_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4907     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4908         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4909 /* Rotate and Set Flag then AND */
4910 #define E_COND_AND_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4911     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4912         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4913 
4914 /* Rotate and then OR */
4915 #define E_COND_OR_RROR(cond, dest, roperand, r2shift, rshift)                                                         \
4916     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4917         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4918 /* Rotate and Set Flag then OR */
4919 #define E_COND_OR_RRORS(cond, dest, roperand, r2shift, rshift)                                                        \
4920     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4921         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4922 
4923 /* Rotate and then XOR */
4924 #define E_COND_XOR_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4925     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4926         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4927 /* Rotate and Set Flag then XOR */
4928 #define E_COND_XOR_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4929     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4930         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4931 
4932 /* Rotate and then ADD */
4933 #define E_COND_ADD_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4934     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4935         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4936 /* Rotate and Set Flag then ADD */
4937 #define E_COND_ADD_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4938     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4939         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4940 
4941 /* Rotate and then SUB */
4942 #define E_COND_SUB_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4943     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4944         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4945 /* Rotate and Set Flag then SUB */
4946 #define E_COND_SUB_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4947     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4948         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4949 
4950 /* Rotate and then ADC */
4951 #define E_COND_ADC_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4952     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4953         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4954 /* Rotate and Set Flag then ADC */
4955 #define E_COND_ADC_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4956     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4957         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4958 
4959 /* Rotate and then SBC */
4960 #define E_COND_SBC_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
4961     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4962         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4963 /* Rotate and Set Flag then SBC */
4964 #define E_COND_SBC_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
4965     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
4966         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28)
4967 
4968 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4969 /*                                       E_ROTATE by Reg Codes and invert ALU result */
4970 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
4971 
4972 /*                                                         opcode      Dest            Src1              r2shift SFlag
4973  */
4974 /*                                                         Cond         Imm                   Extra Operation Left/Right
4975  */
4976 /*                                                         Shift/Rotate */
4977 
4978 /* Rotate */
4979 #define E_RRORN(dest, r2shift, rshift)                                                                       \
4980     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4981         (1 << 19) + (1 << 18) + (1 << 27)
4982 /* Rotate and Set Flag */
4983 #define E_RRORNS(dest, r2shift, rshift)                                                                      \
4984     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
4985         (1 << 19) + (1 << 18) + (1 << 27)
4986 
4987 /* Rotate and then AND */
4988 #define E_RROR_ANDN(dest, roperand, r2shift, rshift)                                                                \
4989     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4990         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
4991 /* Rotate and Set Flag then AND */
4992 #define E_RROR_ANDNS(dest, roperand, r2shift, rshift)                                                               \
4993     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4994         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
4995 
4996 /* Rotate and then OR */
4997 #define E_RROR_ORN(dest, roperand, r2shift, rshift)                                                                 \
4998     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
4999         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5000 /* Rotate and Set Flag then OR */
5001 #define E_RROR_ORNS(dest, roperand, r2shift, rshift)                                                                \
5002     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5003         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5004 
5005 /* Rotate and then XOR */
5006 #define E_RROR_XORN(dest, roperand, r2shift, rshift)                                                                \
5007     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5008         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5009 /* Rotate and Set Flag then XOR */
5010 #define E_RROR_XORNS(dest, roperand, r2shift, rshift)                                                               \
5011     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5012         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5013 
5014 /* Rotate and then ADD */
5015 #define E_RROR_ADDN(dest, roperand, r2shift, rshift)                                                                \
5016     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5017         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5018 /* Rotate and Set Flag then ADD */
5019 #define E_RROR_ADDNS(dest, roperand, r2shift, rshift)                                                               \
5020     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5021         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5022 
5023 /* Rotate and then SUB */
5024 #define E_RROR_SUBN(dest, roperand, r2shift, rshift)                                                                \
5025     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5026         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5027 /* Rotate and Set Flag then SUB */
5028 #define E_RROR_SUBNS(dest, roperand, r2shift, rshift)                                                               \
5029     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5030         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5031 
5032 /* Rotate and then ADC */
5033 #define E_RROR_ADCN(dest, roperand, r2shift, rshift)                                                                \
5034     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5035         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5036 /* Rotate and Set Flag then ADC */
5037 #define E_RROR_ADCNS(dest, roperand, r2shift, rshift)                                                               \
5038     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5039         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5040 
5041 /* Rotate and then SBC */
5042 #define E_RROR_SBCN(dest, roperand, r2shift, rshift)                                                                \
5043     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5044         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5045 /* Rotate and Set Flag then SBC */
5046 #define E_RROR_SBCNS(dest, roperand, r2shift, rshift)                                                               \
5047     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5048         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5049 
5050 /* Conditional */
5051 /* Rotate */
5052 #define E_COND_RRORN(cond, dest, r2shift, rshift)                                                              \
5053     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5054         (1 << 19) + (1 << 18) + (1 << 27)
5055 /* Rotate and Set Flag */
5056 #define E_COND_RRORNS(cond, dest, r2shift, rshift)                                                             \
5057     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5058         (1 << 19) + (1 << 18) + (1 << 27)
5059 
5060 /* Rotate and then AND */
5061 #define E_COND_RROR_ANDN(cond, dest, roperand, r2shift, rshift)                                                       \
5062     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5063         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5064 /* Rotate and Set Flag then AND */
5065 #define E_COND_RROR_ANDNS(cond, dest, roperand, r2shift, rshift)                                                      \
5066     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5067         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5068 
5069 /* Rotate and then OR */
5070 #define E_COND_RROR_ORN(cond, dest, roperand, r2shift, rshift)                                                        \
5071     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5072         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5073 /* Rotate and Set Flag then OR */
5074 #define E_COND_RROR_ORNS(cond, dest, roperand, r2shift, rshift)                                                       \
5075     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5076         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5077 
5078 /* Rotate and then XOR */
5079 #define E_COND_RROR_XORN(cond, dest, roperand, r2shift, rshift)                                                       \
5080     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5081         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5082 /* Rotate and Set Flag then XOR */
5083 #define E_COND_RROR_XORNS(cond, dest, roperand, r2shift, rshift)                                                      \
5084     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5085         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5086 
5087 /* Rotate and then ADD */
5088 #define E_COND_RROR_ADDN(cond, dest, roperand, r2shift, rshift)                                                       \
5089     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5090         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5091 /* Rotate and Set Flag then ADD */
5092 #define E_COND_RROR_ADDNS(cond, dest, roperand, r2shift, rshift)                                                      \
5093     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5094         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5095 
5096 /* Rotate and then SUB */
5097 #define E_COND_RROR_SUBN(cond, dest, roperand, r2shift, rshift)                                                       \
5098     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5099         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5100 /* Rotate and Set Flag then SUB */
5101 #define E_COND_RROR_SUBNS(cond, dest, roperand, r2shift, rshift)                                                      \
5102     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5103         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5104 
5105 /* Rotate and then ADC */
5106 #define E_COND_RROR_ADCN(cond, dest, roperand, r2shift, rshift)                                                       \
5107     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5108         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5109 /* Rotate and Set Flag then ADC */
5110 #define E_COND_RROR_ADCNS(cond, dest, roperand, r2shift, rshift)                                                      \
5111     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5112         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5113 
5114 /* Rotate and then SBC */
5115 #define E_COND_RROR_SBCN(cond, dest, roperand, r2shift, rshift)                                                       \
5116     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5117         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5118 /* Rotate and Set Flag then SBC */
5119 #define E_COND_RROR_SBCNS(cond, dest, roperand, r2shift, rshift)                                                      \
5120     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5121         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27)
5122 
5123 /* Rotate and then AND */
5124 #define E_ANDN_RROR(dest, roperand, r2shift, rshift)                                                                \
5125     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5126         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5127 /* Rotate and Set Flag then AND */
5128 #define E_ANDN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5129     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5130         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5131 
5132 /* Rotate and then OR */
5133 #define E_ORN_RROR(dest, roperand, r2shift, rshift)                                                                 \
5134     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5135         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5136 /* Rotate and Set Flag then OR */
5137 #define E_ORN_RRORS(dest, roperand, r2shift, rshift)                                                                \
5138     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5139         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5140 
5141 /* Rotate and then XOR */
5142 #define E_XORN_RROR(dest, roperand, r2shift, rshift)                                                                \
5143     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5144         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5145 /* Rotate and Set Flag then XOR */
5146 #define E_XORN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5147     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5148         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5149 
5150 /* Rotate and then ADD */
5151 #define E_ADDN_RROR(dest, roperand, r2shift, rshift)                                                                \
5152     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5153         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5154 /* Rotate and Set Flag then ADD */
5155 #define E_ADDN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5156     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5157         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5158 
5159 /* Rotate and then SUB */
5160 #define E_SUBN_RROR(dest, roperand, r2shift, rshift)                                                                \
5161     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5162         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5163 /* Rotate and Set Flag then SUB */
5164 #define E_SUBN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5165     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5166         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5167 
5168 /* Rotate and then ADC */
5169 #define E_ADCN_RROR(dest, roperand, r2shift, rshift)                                                                \
5170     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5171         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5172 /* Rotate and Set Flag then ADC */
5173 #define E_ADCN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5174     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5175         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5176 
5177 /* Rotate and then SBC */
5178 #define E_SBCN_RROR(dest, roperand, r2shift, rshift)                                                                \
5179     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5180         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5181 /* Rotate and Set Flag then SBC */
5182 #define E_SBCN_RRORS(dest, roperand, r2shift, rshift)                                                               \
5183     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5184         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5185 
5186 /* Conditional */
5187 
5188 /* Rotate and then AND */
5189 #define E_COND_ANDN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5190     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5191         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5192 /* Rotate and Set Flag then AND */
5193 #define E_COND_ANDN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5194     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5195         (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5196 
5197 /* Rotate and then OR */
5198 #define E_COND_ORN_RROR(cond, dest, roperand, r2shift, rshift)                                                        \
5199     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5200         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5201 /* Rotate and Set Flag then OR */
5202 #define E_COND_ORN_RRORS(cond, dest, roperand, r2shift, rshift)                                                       \
5203     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5204         (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5205 
5206 /* Rotate and then XOR */
5207 #define E_COND_XORN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5208     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5209         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5210 /* Rotate and Set Flag then XOR */
5211 #define E_COND_XORN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5212     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5213         (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5214 
5215 /* Rotate and then ADD */
5216 #define E_COND_ADDN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5217     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5218         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5219 /* Rotate and Set Flag then ADD */
5220 #define E_COND_ADDN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5221     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5222         (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5223 
5224 /* Rotate and then SUB */
5225 #define E_COND_SUBN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5226     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5227         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5228 /* Rotate and Set Flag then SUB */
5229 #define E_COND_SUBN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5230     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5231         (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5232 
5233 /* Rotate and then ADC */
5234 #define E_COND_ADCN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5235     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5236         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5237 /* Rotate and Set Flag then ADC */
5238 #define E_COND_ADCN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5239     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5240         (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5241 
5242 /* Rotate and then SBC */
5243 #define E_COND_SBCN_RROR(cond, dest, roperand, r2shift, rshift)                                                       \
5244     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5245         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5246 /* Rotate and Set Flag then SBC */
5247 #define E_COND_SBCN_RRORS(cond, dest, roperand, r2shift, rshift)                                                      \
5248     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5249         (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5250 
5251 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5252 /*                                       Arithmetical Shift Codes */
5253 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5254 
5255 /*                                                         opcode      Dest            Src1              r2shift SFlag
5256  */
5257 /*                                                         Cond         Imm                   Extra Operation Left/Right
5258  */
5259 /*                                                         Shift/Rotate  Arith/Shift */
5260 
5261 /* Arith Shift Right */
5262 #define E_RASR(dest, r2shift, rshift)                                                                        \
5263     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5264         (0 << 19) + (1 << 18)
5265 /* Arith Shift Right and Set Flag */
5266 #define E_RASRS(dest, r2shift, rshift)                                                                       \
5267     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5268         (0 << 19) + (1 << 18)
5269 
5270 /* Arith Shift Right and then AND */
5271 #define E_RASR_AND(dest, roperand, r2shift, rshift)                                                                 \
5272     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5273         (1 << 29) + (0 << 19) + (1 << 18)
5274 /* Arith Shift Right and Set Flag then AND */
5275 #define E_RASR_ANDS(dest, roperand, r2shift, rshift)                                                                \
5276     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5277         (1 << 29) + (0 << 19) + (1 << 18)
5278 
5279 /* Arith Shift Right and then OR */
5280 #define E_RASR_OR(dest, roperand, r2shift, rshift)                                                                  \
5281     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5282         (2 << 29) + (0 << 19) + (1 << 18)
5283 /* Arith Shift Right and Set Flag then OR */
5284 #define E_RASR_ORS(dest, roperand, r2shift, rshift)                                                                 \
5285     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5286         (2 << 29) + (0 << 19) + (1 << 18)
5287 
5288 /* Arith Shift Right and then XOR */
5289 #define E_RASR_XOR(dest, roperand, r2shift, rshift)                                                                 \
5290     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5291         (3 << 29) + (0 << 19) + (1 << 18)
5292 /* Arith Shift Right and Set Flag then XOR */
5293 #define E_RASR_XORS(dest, roperand, r2shift, rshift)                                                                \
5294     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5295         (3 << 29) + (0 << 19) + (1 << 18)
5296 
5297 /* Arith Shift Right and then ADD */
5298 #define E_RASR_ADD(dest, roperand, r2shift, rshift)                                                                 \
5299     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5300         (4 << 29) + (0 << 19) + (1 << 18)
5301 /* Arith Shift Right and Set Flag then ADD */
5302 #define E_RASR_ADDS(dest, roperand, r2shift, rshift)                                                                \
5303     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5304         (4 << 29) + (0 << 19) + (1 << 18)
5305 
5306 /* Arith Shift Right and then SUB */
5307 #define E_RASR_SUB(dest, roperand, r2shift, rshift)                                                                 \
5308     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5309         (5 << 29) + (0 << 19) + (1 << 18)
5310 /* Arith Shift Right and Set Flag then SUB */
5311 #define E_RASR_SUBS(dest, roperand, r2shift, rshift)                                                                \
5312     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5313         (5 << 29) + (0 << 19) + (1 << 18)
5314 
5315 /* Arith Shift Right and then ADC */
5316 #define E_RASR_ADC(dest, roperand, r2shift, rshift)                                                                 \
5317     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5318         (6 << 29) + (0 << 19) + (1 << 18)
5319 /* Arith Shift Right and Set Flag then ADC */
5320 #define E_RASR_ADCS(dest, roperand, r2shift, rshift)                                                                \
5321     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5322         (6 << 29) + (0 << 19) + (1 << 18)
5323 
5324 /* Arith Shift Right and then SBC */
5325 #define E_RASR_SBC(dest, roperand, r2shift, rshift)                                                                 \
5326     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5327         (7 << 29) + (0 << 19) + (1 << 18)
5328 /* Arith Shift Right and Set Flag then SBC */
5329 #define E_RASR_SBCS(dest, roperand, r2shift, rshift)                                                                \
5330     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5331         (7 << 29) + (0 << 19) + (1 << 18)
5332 
5333 /* Conditional */
5334 /* Conditional Arith Shift */
5335 #define E_COND_RASR(cond, dest, r2shift, rshift)                                                               \
5336     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5337         (0 << 19) + (1 << 18)
5338 /* Conditional Arith Shift and Set Flag */
5339 #define E_COND_RASRS(cond, dest, r2shift, rshift)                                                              \
5340     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5341         (0 << 19) + (1 << 18)
5342 
5343 /* Conditional Arith Shift and then AND */
5344 #define E_COND_RASR_AND(cond, dest, roperand, r2shift, rshift)                                                        \
5345     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5346         (1 << 29) + (0 << 19) + (1 << 18)
5347 /* Conditional Arith Shift and Set Flag then AND */
5348 #define E_COND_RASR_ANDS(cond, dest, roperand, r2shift, rshift)                                                       \
5349     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5350         (1 << 29) + (0 << 19) + (1 << 18)
5351 
5352 /* Conditional Arith Shift and then OR */
5353 #define E_COND_RASR_OR(cond, dest, roperand, r2shift, rshift)                                                         \
5354     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5355         (2 << 29) + (0 << 19) + (1 << 18)
5356 /* Conditional Arith Shift and Set Flag then OR */
5357 #define E_COND_RASR_ORS(cond, dest, roperand, r2shift, rshift)                                                        \
5358     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5359         (2 << 29) + (0 << 19) + (1 << 18)
5360 
5361 /* Conditional Arith Shift and then XOR */
5362 #define E_COND_RASR_XOR(cond, dest, roperand, r2shift, rshift)                                                        \
5363     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5364         (3 << 29) + (0 << 19) + (1 << 18)
5365 /* Conditional Arith Shift and Set Flag then XOR */
5366 #define E_COND_RASR_XORS(cond, dest, roperand, r2shift, rshift)                                                       \
5367     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5368         (3 << 29) + (0 << 19) + (1 << 18)
5369 
5370 /* Conditional Arith Shift and then ADD */
5371 #define E_COND_RASR_ADD(cond, dest, roperand, r2shift, rshift)                                                        \
5372     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5373         (4 << 29) + (0 << 19) + (1 << 18)
5374 /* Conditional Arith Shift and Set Flag then ADD */
5375 #define E_COND_RASR_ADDS(cond, dest, roperand, r2shift, rshift)                                                       \
5376     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5377         (4 << 29) + (0 << 19) + (1 << 18)
5378 
5379 /* Conditional Arith Shift and then SUB */
5380 #define E_COND_RASR_SUB(cond, dest, roperand, r2shift, rshift)                                                        \
5381     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5382         (5 << 29) + (0 << 19) + (1 << 18)
5383 /* Conditional Arith Shift and Set Flag then SUB */
5384 #define E_COND_RASR_SUBS(cond, dest, roperand, r2shift, rshift)                                                       \
5385     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5386         (5 << 29) + (0 << 19) + (1 << 18)
5387 
5388 /* Conditional Arith Shift and then ADC */
5389 #define E_COND_RASR_ADC(cond, dest, roperand, r2shift, rshift)                                                        \
5390     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5391         (6 << 29) + (0 << 19) + (1 << 18)
5392 /* Conditional Arith Shift and Set Flag then ADC */
5393 #define E_COND_RASR_ADCS(cond, dest, roperand, r2shift, rshift)                                                       \
5394     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5395         (6 << 29) + (0 << 19) + (1 << 18)
5396 
5397 /* Conditional Arith Shift and then SBC */
5398 #define E_COND_RASR_SBC(cond, dest, roperand, r2shift, rshift)                                                        \
5399     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5400         (7 << 29) + (0 << 19) + (1 << 18)
5401 /* Conditional Arith Shift and Set Flag then SBC */
5402 #define E_COND_RASR_SBCS(cond, dest, roperand, r2shift, rshift)                                                       \
5403     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5404         (7 << 29) + (0 << 19) + (1 << 18)
5405 
5406 /* Arith Shift Right and then AND */
5407 #define E_AND_RASR(dest, roperand, r2shift, rshift)                                                                 \
5408     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5409         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5410 /* Arith Shift Right and Set Flag then AND */
5411 #define E_AND_RASRS(dest, roperand, r2shift, rshift)                                                                \
5412     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5413         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5414 
5415 /* Arith Shift Right and then OR */
5416 #define E_OR_RASR(dest, roperand, r2shift, rshift)                                                                  \
5417     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5418         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5419 /* Arith Shift Right and Set Flag then OR */
5420 #define E_OR_RASRS(dest, roperand, r2shift, rshift)                                                                 \
5421     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5422         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5423 
5424 /* Arith Shift Right and then XOR */
5425 #define E_XOR_RASR(dest, roperand, r2shift, rshift)                                                                 \
5426     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5427         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5428 /* Arith Shift Right and Set Flag then XOR */
5429 #define E_XOR_RASRS(dest, roperand, r2shift, rshift)                                                                \
5430     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5431         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5432 
5433 /* Arith Shift Right and then ADD */
5434 #define E_ADD_RASR(dest, roperand, r2shift, rshift)                                                                 \
5435     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5436         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5437 /* Arith Shift Right and Set Flag then ADD */
5438 #define E_ADD_RASRS(dest, roperand, r2shift, rshift)                                                                \
5439     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5440         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5441 
5442 /* Arith Shift Right and then SUB */
5443 #define E_SUB_RASR(dest, roperand, r2shift, rshift)                                                                 \
5444     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5445         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5446 /* Arith Shift Right and Set Flag then SUB */
5447 #define E_SUB_RASRS(dest, roperand, r2shift, rshift)                                                                \
5448     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5449         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5450 
5451 /* Arith Shift Right and then ADC */
5452 #define E_ADC_RASR(dest, roperand, r2shift, rshift)                                                                 \
5453     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5454         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5455 /* Arith Shift Right and Set Flag then ADC */
5456 #define E_ADC_RASRS(dest, roperand, r2shift, rshift)                                                                \
5457     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5458         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5459 
5460 /* Arith Shift Right and then SBC */
5461 #define E_SBC_RASR(dest, roperand, r2shift, rshift)                                                                 \
5462     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5463         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5464 /* Arith Shift Right and Set Flag then SBC */
5465 #define E_SBC_RASRS(dest, roperand, r2shift, rshift)                                                                \
5466     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5467         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5468 
5469 /* Conditional */
5470 
5471 /* Conditional Arith Shift and then AND */
5472 #define E_COND_AND_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5473     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5474         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5475 /* Conditional Arith Shift and Set Flag then AND */
5476 #define E_COND_AND_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5477     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5478         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5479 
5480 /* Conditional Arith Shift and then OR */
5481 #define E_COND_OR_RASR(cond, dest, roperand, r2shift, rshift)                                                         \
5482     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5483         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5484 /* Conditional Arith Shift and Set Flag then OR */
5485 #define E_COND_OR_RASRS(cond, dest, roperand, r2shift, rshift)                                                        \
5486     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5487         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5488 
5489 /* Conditional Arith Shift and then XOR */
5490 #define E_COND_XOR_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5491     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5492         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5493 /* Conditional Arith Shift and Set Flag then XOR */
5494 #define E_COND_XOR_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5495     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5496         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5497 
5498 /* Conditional Arith Shift and then ADD */
5499 #define E_COND_ADD_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5500     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5501         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5502 /* Conditional Arith Shift and Set Flag then ADD */
5503 #define E_COND_ADD_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5504     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5505         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5506 
5507 /* Conditional Arith Shift and then SUB */
5508 #define E_COND_SUB_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5509     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5510         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5511 /* Conditional Arith Shift and Set Flag then SUB */
5512 #define E_COND_SUB_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5513     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5514         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5515 
5516 /* Conditional Arith Shift and then ADC */
5517 #define E_COND_ADC_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5518     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5519         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5520 /* Conditional Arith Shift and Set Flag then ADC */
5521 #define E_COND_ADC_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5522     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5523         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5524 
5525 /* Conditional Arith Shift and then SBC */
5526 #define E_COND_SBC_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5527     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5528         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5529 /* Conditional Arith Shift and Set Flag then SBC */
5530 #define E_COND_SBC_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5531     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5532         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28)
5533 
5534 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5535 /*                                       Arithmetical Shift Codes with invert ALU */
5536 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5537 
5538 /*                                                         opcode      Dest            Src1              r2shift SFlag
5539  */
5540 /*                                                         Cond         Imm                   Extra Operation Left/Right
5541  */
5542 /*                                                         Shift/Rotate  pOSTShift */
5543 
5544 /* Arith Shift Right */
5545 #define E_RASRN(dest, r2shift, rshift)                                                                       \
5546     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5547         (0 << 19) + (1 << 18) + (1 << 27)
5548 /* Arith Shift Right and Set Flag */
5549 #define E_RASRNS(dest, r2shift, rshift)                                                                      \
5550     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5551         (0 << 19) + (1 << 18) + (1 << 27)
5552 
5553 /* Arith Shift Right and then AND */
5554 #define E_RASR_ANDN(dest, roperand, r2shift, rshift)                                                                \
5555     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5556         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5557 /* Arith Shift Right and Set Flag then AND */
5558 #define E_RASR_ANDNS(dest, roperand, r2shift, rshift)                                                               \
5559     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5560         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5561 
5562 /* Arith Shift Right and then OR */
5563 #define E_RASR_ORN(dest, roperand, r2shift, rshift)                                                                 \
5564     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5565         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5566 /* Arith Shift Right and Set Flag then OR */
5567 #define E_RASR_ORNS(dest, roperand, r2shift, rshift)                                                                \
5568     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5569         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5570 
5571 /* Arith Shift Right and then XOR */
5572 #define E_RASR_XORN(dest, roperand, r2shift, rshift)                                                                \
5573     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5574         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5575 /* Arith Shift Right and Set Flag then XOR */
5576 #define E_RASR_XORNS(dest, roperand, r2shift, rshift)                                                               \
5577     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5578         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5579 
5580 /* Arith Shift Right and then ADD */
5581 #define E_RASR_ADDN(dest, roperand, r2shift, rshift)                                                                \
5582     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5583         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5584 /* Arith Shift Right and Set Flag then ADD */
5585 #define E_RASR_ADDNS(dest, roperand, r2shift, rshift)                                                               \
5586     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5587         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5588 
5589 /* Arith Shift Right and then SUB */
5590 #define E_RASR_SUBN(dest, roperand, r2shift, rshift)                                                                \
5591     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5592         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5593 /* Arith Shift Right and Set Flag then SUB */
5594 #define E_RASR_SUBNS(dest, roperand, r2shift, rshift)                                                               \
5595     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5596         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5597 
5598 /* Arith Shift Right and then ADC */
5599 #define E_RASR_ADCN(dest, roperand, r2shift, rshift)                                                                \
5600     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5601         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5602 /* Arith Shift Right and Set Flag then ADC */
5603 #define E_RASR_ADCNS(dest, roperand, r2shift, rshift)                                                               \
5604     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5605         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5606 
5607 /* Arith Shift Right and then SBC */
5608 #define E_RASR_SBCN(dest, roperand, r2shift, rshift)                                                                \
5609     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5610         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5611 /* Arith Shift Right and Set Flag then SBC */
5612 #define E_RASR_SBCNS(dest, roperand, r2shift, rshift)                                                               \
5613     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5614         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5615 
5616 /* Conditional */
5617 /* Conditional Arith Shift */
5618 #define E_COND_RASRN(cond, dest, r2shift, rshift)                                                              \
5619     DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5620         (0 << 19) + (1 << 18) + (1 << 27)
5621 /* Conditional Arith Shift and Set Flag */
5622 #define E_COND_RASRNS(cond, dest, r2shift, rshift)                                                             \
5623     DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \
5624         (0 << 19) + (1 << 18) + (1 << 27)
5625 
5626 /* Conditional Arith Shift and then AND */
5627 #define E_COND_RASR_ANDN(cond, dest, roperand, r2shift, rshift)                                                       \
5628     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5629         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5630 /* Conditional Arith Shift and Set Flag then AND */
5631 #define E_COND_RASR_ANDNS(cond, dest, roperand, r2shift, rshift)                                                      \
5632     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5633         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5634 
5635 /* Conditional Arith Shift and then OR */
5636 #define E_COND_RASR_ORN(cond, dest, roperand, r2shift, rshift)                                                        \
5637     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5638         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5639 /* Conditional Arith Shift and Set Flag then OR */
5640 #define E_COND_RASR_ORNS(cond, dest, roperand, r2shift, rshift)                                                       \
5641     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5642         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5643 
5644 /* Conditional Arith Shift and then XOR */
5645 #define E_COND_RASR_XORN(cond, dest, roperand, r2shift, rshift)                                                       \
5646     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5647         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5648 /* Conditional Arith Shift and Set Flag then XOR */
5649 #define E_COND_RASR_XORNS(cond, dest, roperand, r2shift, rshift)                                                      \
5650     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5651         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5652 
5653 /* Conditional Arith Shift and then ADD */
5654 #define E_COND_RASR_ADDN(cond, dest, roperand, r2shift, rshift)                                                       \
5655     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5656         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5657 /* Conditional Arith Shift and Set Flag then ADD */
5658 #define E_COND_RASR_ADDNS(cond, dest, roperand, r2shift, rshift)                                                      \
5659     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5660         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5661 
5662 /* Conditional Arith Shift and then SUB */
5663 #define E_COND_RASR_SUBN(cond, dest, roperand, r2shift, rshift)                                                       \
5664     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5665         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5666 /* Conditional Arith Shift and Set Flag then SUB */
5667 #define E_COND_RASR_SUBNS(cond, dest, roperand, r2shift, rshift)                                                      \
5668     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5669         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5670 
5671 /* Conditional Arith Shift and then ADC */
5672 #define E_COND_RASR_ADCN(cond, dest, roperand, r2shift, rshift)                                                       \
5673     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5674         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5675 /* Conditional Arith Shift and Set Flag then ADC */
5676 #define E_COND_RASR_ADCNS(cond, dest, roperand, r2shift, rshift)                                                      \
5677     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5678         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5679 
5680 /* Conditional Arith Shift and then SBC */
5681 #define E_COND_RASR_SBCN(cond, dest, roperand, r2shift, rshift)                                                       \
5682     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5683         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5684 /* Conditional Arith Shift and Set Flag then SBC */
5685 #define E_COND_RASR_SBCNS(cond, dest, roperand, r2shift, rshift)                                                      \
5686     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5687         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27)
5688 
5689 /* Arith Shift Right and then AND */
5690 #define E_ANDN_RASR(dest, roperand, r2shift, rshift)                                                                \
5691     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5692         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5693 /* Arith Shift Right and Set Flag then AND */
5694 #define E_ANDN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5695     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5696         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5697 
5698 /* Arith Shift Right and then OR */
5699 #define E_ORN_RASR(dest, roperand, r2shift, rshift)                                                                 \
5700     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5701         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5702 /* Arith Shift Right and Set Flag then OR */
5703 #define E_ORN_RASRS(dest, roperand, r2shift, rshift)                                                                \
5704     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5705         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5706 
5707 /* Arith Shift Right and then XOR */
5708 #define E_XORN_RASR(dest, roperand, r2shift, rshift)                                                                \
5709     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5710         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5711 /* Arith Shift Right and Set Flag then XOR */
5712 #define E_XORN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5713     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5714         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5715 
5716 /* Arith Shift Right and then ADD */
5717 #define E_ADDN_RASR(dest, roperand, r2shift, rshift)                                                                \
5718     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5719         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5720 /* Arith Shift Right and Set Flag then ADD */
5721 #define E_ADDN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5722     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5723         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5724 
5725 /* Arith Shift Right and then SUB */
5726 #define E_SUBN_RASR(dest, roperand, r2shift, rshift)                                                                \
5727     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5728         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5729 /* Arith Shift Right and Set Flag then SUB */
5730 #define E_SUBN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5731     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5732         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5733 
5734 /* Arith Shift Right and then ADC */
5735 #define E_ADCN_RASR(dest, roperand, r2shift, rshift)                                                                \
5736     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5737         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5738 /* Arith Shift Right and Set Flag then ADC */
5739 #define E_ADCN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5740     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5741         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5742 
5743 /* Arith Shift Right and then SBC */
5744 #define E_SBCN_RASR(dest, roperand, r2shift, rshift)                                                                \
5745     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5746         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5747 /* Arith Shift Right and Set Flag then SBC */
5748 #define E_SBCN_RASRS(dest, roperand, r2shift, rshift)                                                               \
5749     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \
5750         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5751 
5752 /* Conditional */
5753 
5754 /* Conditional Arith Shift and then AND */
5755 #define E_COND_ANDN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5756     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5757         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5758 /* Conditional Arith Shift and Set Flag then AND */
5759 #define E_COND_ANDN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5760     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5761         (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5762 
5763 /* Conditional Arith Shift and then OR */
5764 #define E_COND_ORN_RASR(cond, dest, roperand, r2shift, rshift)                                                        \
5765     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5766         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5767 /* Conditional Arith Shift and Set Flag then OR */
5768 #define E_COND_ORN_RASRS(cond, dest, roperand, r2shift, rshift)                                                       \
5769     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5770         (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5771 
5772 /* Conditional Arith Shift and then XOR */
5773 #define E_COND_XORN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5774     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5775         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5776 /* Conditional Arith Shift and Set Flag then XOR */
5777 #define E_COND_XORN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5778     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5779         (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5780 
5781 /* Conditional Arith Shift and then ADD */
5782 #define E_COND_ADDN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5783     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5784         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5785 /* Conditional Arith Shift and Set Flag then ADD */
5786 #define E_COND_ADDN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5787     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5788         (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5789 
5790 /* Conditional Arith Shift and then SUB */
5791 #define E_COND_SUBN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5792     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5793         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5794 /* Conditional Arith Shift and Set Flag then SUB */
5795 #define E_COND_SUBN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5796     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5797         (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5798 
5799 /* Conditional Arith Shift and then ADC */
5800 #define E_COND_ADCN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5801     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5802         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5803 /* Conditional Arith Shift and Set Flag then ADC */
5804 #define E_COND_ADCN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5805     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5806         (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5807 
5808 /* Conditional Arith Shift and then SBC */
5809 #define E_COND_SBCN_RASR(cond, dest, roperand, r2shift, rshift)                                                       \
5810     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5811         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5812 /* Conditional Arith Shift and Set Flag then SBC */
5813 #define E_COND_SBCN_RASRS(cond, dest, roperand, r2shift, rshift)                                                      \
5814     DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \
5815         (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28)
5816 
5817 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5818 /*                                       Bit Manipulate */
5819 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5820 /*                                                         opcode      Dest            Src1               src2 SFlag */
5821 /*                                                         Cond         Imm                  Extra Operation ShiftByByte
5822  */
5823 /*                                                         Neg/Pos Mask */
5824 
5825 /* Bit test by byte */
5826 #define E_BTST(dest, rdata, rbit)                                                                           \
5827     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \
5828         (1 << 18) + (1 << 31)
5829 #define E_BCLR(dest, rdata, rbit)                                                                           \
5830     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \
5831         (1 << 18) + (0 << 31)
5832 #define E_BSET(dest, rdata, rbit)                                                                           \
5833     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \
5834         (1 << 18) + (1 << 31)
5835 #define E_BTOG(dest, rdata, rbit)                                                                           \
5836     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \
5837         (1 << 18) + (1 << 31)
5838 
5839 /* Bit test by byte with set flags */
5840 #define E_BTSTS(dest, rdata, rbit)                                                                          \
5841     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \
5842         (1 << 18) + (1 << 31)
5843 #define E_BCLRS(dest, rdata, rbit)                                                                          \
5844     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \
5845         (1 << 18) + (0 << 31)
5846 #define E_BSETS(dest, rdata, rbit)                                                                          \
5847     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \
5848         (1 << 18) + (1 << 31)
5849 #define E_BTOGS(dest, rdata, rbit)                                                                          \
5850     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \
5851         (1 << 18) + (1 << 31)
5852 
5853 /* Conditional Bit test by byte */
5854 #define E_COND_BTST(cond, dest, rdata, rbit)                                                                  \
5855     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \
5856         (1 << 18) + (1 << 31)
5857 #define E_COND_BCLR(cond, dest, rdata, rbit)                                                                  \
5858     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \
5859         (1 << 18) + (0 << 31)
5860 #define E_COND_BSET(cond, dest, rdata, rbit)                                                                  \
5861     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \
5862         (1 << 18) + (1 << 31)
5863 #define E_COND_BTOG(cond, dest, rdata, rbit)                                                                  \
5864     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \
5865         (1 << 18) + (1 << 31)
5866 
5867 /* Conditional Bit test by byte with set flags */
5868 #define E_COND_BTSTS(cond, dest, rdata, rbit)                                                                 \
5869     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \
5870         (1 << 18) + (1 << 31)
5871 #define E_COND_BCLRS(cond, dest, rdata, rbit)                                                                 \
5872     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \
5873         (1 << 18) + (0 << 31)
5874 #define E_COND_BSETS(cond, dest, rdata, rbit)                                                                 \
5875     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \
5876         (1 << 18) + (1 << 31)
5877 #define E_COND_BTOGS(cond, dest, rdata, rbit)                                                                 \
5878     DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \
5879         (1 << 18) + (1 << 31)
5880 
5881 /* Bit test by imm */
5882 #define E_BTST_IMM(dest, rdata, bit5)                                                                                \
5883     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5884         (1 << 31)
5885 #define E_BCLR_IMM(dest, rdata, bit5)                                                                                \
5886     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5887         (0 << 31)
5888 #define E_BSET_IMM(dest, rdata, bit5)                                                                                \
5889     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \
5890         (1 << 31)
5891 #define E_BTOG_IMM(dest, rdata, bit5)                                                                                \
5892     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \
5893         (1 << 31)
5894 
5895 /* Bit test by imm with set flags */
5896 #define E_BTST_IMMS(dest, rdata, bit5)                                                                               \
5897     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5898         (1 << 31)
5899 #define E_BCLR_IMMS(dest, rdata, bit5)                                                                               \
5900     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5901         (0 << 31)
5902 #define E_BSET_IMMS(dest, rdata, bit5)                                                                               \
5903     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \
5904         (1 << 31)
5905 #define E_BTOG_IMMS(dest, rdata, bit5)                                                                               \
5906     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \
5907         (1 << 31)
5908 
5909 /* Conditional Bit test by imm */
5910 #define E_COND_BTST_IMM(cond, dest, rdata, bit5)                                                                       \
5911     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5912         (1 << 31)
5913 #define E_COND_BCLR_IMM(cond, dest, rdata, bit5)                                                                       \
5914     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5915         (0 << 31)
5916 #define E_COND_BSET_IMM(cond, dest, rdata, bit5)                                                                       \
5917     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \
5918         (1 << 31)
5919 #define E_COND_BTOG_IMM(cond, dest, rdata, bit5)                                                                       \
5920     DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \
5921         (1 << 31)
5922 
5923 /* Conditional Bit test by imm with set flags */
5924 #define E_COND_BTST_IMMS(cond, dest, rdata, bit5)                                                                      \
5925     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5926         (1 << 31)
5927 #define E_COND_BCLR_IMMS(cond, dest, rdata, bit5)                                                                      \
5928     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \
5929         (0 << 31)
5930 #define E_COND_BSET_IMMS(cond, dest, rdata, bit5)                                                                      \
5931     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \
5932         (1 << 31)
5933 #define E_COND_BTOG_IMMS(cond, dest, rdata, bit5)                                                                      \
5934     DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \
5935         (1 << 31)
5936 
5937 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5938 /*                                      Tight Loop */
5939 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5940 
5941 #define E_TIGHT_LOOP(rend, rcount)            DCD 0x1A + (rend << 14) + (rcount << 20)
5942 #define E_COND_TIGHT_LOOP(cond, rend, rcount) DCD 0x1A + (rend << 14) + (rcount << 20) + (cond << 5)
5943 
5944 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5945 /*                                    Boolean Detect */
5946 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
5947 /*                                                                Opcode     Dest           Vector/Single NoUpdateRA */
5948 /*                                                                LargeVectors    Cond              Table */
5949 
5950 #define E_HOLD            DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (EU << 5)
5951 #define E_COND_HOLD(cond) DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (cond << 5)
5952 
5953 /* Small Vector Versions */
5954 #define E_VECTORED_HOLD(table) DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20)
5955 #define E_COND_VECTORED_HOLD(cond, table) \
5956     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20)
5957 #define E_VECTORED_HOLD_NRA(table) \
5958     DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20)
5959 #define E_COND_VECTORED_HOLD_NRA \
5960     (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + (table << 20)
5961 
5962 /* Large Vector Versions */
5963 #define E_VECTORED_HOLD_LV(table) \
5964     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20)
5965 #define E_COND_VECTORED_HOLD_LV(cond, table) \
5966     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20)
5967 #define E_VECTORED_HOLD_LV_NRA(table) \
5968     DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20)
5969 #define E_COND_VECTORED_HOLD_LV_NRA \
5970     (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + (table << 20)
5971 
5972 /*/ Accelarated Vectored_hold */
5973 /* Small Vector Versions */
5974 #define E_ACC_VECTORED_HOLD(table, vectors)                                                               \
5975     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \
5976         (vectors << 24)
5977 #define E_COND_ACC_VECTORED_HOLD(cond, table, vectors)                                                      \
5978     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \
5979         (vectors << 24)
5980 #define E_ACC_VECTORED_HOLD_NRA(table, vectors)                                                           \
5981     DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \
5982         (vectors << 24)
5983 #define E_COND_ACC_VECTORED_HOLD_NRA                                                                    \
5984     (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + \
5985         (table << 20) + (1 << 9) + (vectors << 24)
5986 
5987 /* Large Vector Versions */
5988 #define E_ACC_VECTORED_HOLD_LV(table, vectors)                                                            \
5989     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \
5990         (vectors << 24)
5991 #define E_COND_ACC_VECTORED_HOLD_LV(cond, table, vectors)                                                   \
5992     DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \
5993         (vectors << 24)
5994 #define E_ACC_VECTORED_HOLD_LV_NRA(table, vectors)                                                        \
5995     DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \
5996         (vectors << 24)
5997 #define E_COND_ACC_VECTORED_HOLD_LV_NRA                                                                 \
5998     (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + \
5999         (table << 20) + (1 << 9) + (vectors << 24)
6000 
6001 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6002 /*                                       Reg offset Read */
6003 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6004 
6005 /*                                                        opcode      Rdata Dest       Pointer         WData Source */
6006 /*                                                        Offset             SizeWord    Signed Access  Cond Write */
6007 
6008 /* LDR (Load, Load Byte, LoadByteSigned) */
6009 #define E_LDR_REG(dest, source, offset) \
6010     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (EU << 5)
6011 #define E_LDR_REGB(dest, source, offset) \
6012     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (EU << 5)
6013 #define E_LDR_REGBS(dest, source, offset) \
6014     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (EU << 5)
6015 
6016 /* Conditional LDR (Load, Load Byte, LoadByteSigned) */
6017 #define E_COND_LDR_REG(cond, dest, source, offset) \
6018     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (cond << 5)
6019 #define E_COND_LDR_REGB(cond, dest, source, offset) \
6020     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (cond << 5)
6021 #define E_COND_LDR_REGBS(cond, dest, source, offset) \
6022     DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (cond << 5)
6023 
6024 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6025 /*                                       Reg offset Write */
6026 /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6027 
6028 /*                                                       opcode      Rdata Dest         Pointer       WData Source */
6029 /*                                                       Offset             SizeWord    Signed Access  Cond Write */
6030 
6031 /* STR (Load, Load Byte, LoadByteSigned) */
6032 #define E_STR_REG(raddr, rdata, roffset) \
6033     DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (EU << 5) + (1 << 30)
6034 #define E_STR_REGB(raddr, rdata, roffset) \
6035     DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (EU << 5) + (1 << 30)
6036 
6037 /* Conditional STR (Load, Load Byte, LoadByteSigned) */
6038 #define E_COND_STR_REG(cond, raddr, rdata, roffset) \
6039     DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (cond << 5) + (1 << 30)
6040 #define E_COND_STR_REGB(cond, raddr, rdata, roffset) \
6041     DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (cond << 5) + (1 << 30)
6042 
6043 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6044 /*                                     GPO modify Byte */
6045 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6046 
6047 #define E_MODIFY_GPO_BYTE(andmask, ormask, xormask) DCD 0x1E + (andmask << 8) + (ormask << 16) + (xormask << 24)
6048 
6049 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6050 /*                                    HeartBeat opcodes */
6051 /*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
6052 
6053 #define E_HEART_RYTHM_IMM(val16imm) DCD 0x32 + (val16imm << 16)
6054 #define E_HEART_RYTHM(r16bit)       DCD 0x32 + (r16bit << 14) + (1 << 9)
6055 #define E_SYNCH_ALL_TO_BEAT(on1imm) DCD 0x52 + (on1imm << 31)
6056 #define E_WAIT_FOR_BEAT             DCD 0x72
6057 
6058 #endif
6059