1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2022 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_QuadSPI.h
10  * @version 1.8
11  * @date 2022-07-13
12  * @brief Peripheral Access Layer for S32Z2_QuadSPI
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_QuadSPI_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_QuadSPI_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- QuadSPI Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
68  * @{
69  */
70 
71 /** QuadSPI - Size of Registers Arrays */
72 #define QuadSPI_RBDR_COUNT                        64u
73 #define QuadSPI_LUT_COUNT                         80u
74 #define QuadSPI_FRAD_COUNT                        8u
75 #define QuadSPI_MDAD_COUNT                        2u
76 
77 /** QuadSPI - Register Layout Typedef */
78 typedef struct {
79   __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
80   uint8_t RESERVED_0[4];
81   __IO uint32_t IPCR;                              /**< IP Configuration Register, offset: 0x8 */
82   __IO uint32_t FLSHCR;                            /**< Flash Memory Configuration Register, offset: 0xC */
83   __IO uint32_t BUF0CR;                            /**< Buffer 0 Configuration Register, offset: 0x10 */
84   __IO uint32_t BUF1CR;                            /**< Buffer 1 Configuration Register, offset: 0x14 */
85   __IO uint32_t BUF2CR;                            /**< Buffer 2 Configuration Register, offset: 0x18 */
86   __IO uint32_t BUF3CR;                            /**< Buffer 3 Configuration Register, offset: 0x1C */
87   __IO uint32_t BFGENCR;                           /**< Buffer Generic Configuration Register, offset: 0x20 */
88   __IO uint32_t SOCCR;                             /**< SOC Configuration Register, offset: 0x24 */
89   uint8_t RESERVED_1[8];
90   __IO uint32_t BUF0IND;                           /**< Buffer 0 Top Index Register, offset: 0x30 */
91   __IO uint32_t BUF1IND;                           /**< Buffer 1 Top Index Register, offset: 0x34 */
92   __IO uint32_t BUF2IND;                           /**< Buffer 2 Top Index Register, offset: 0x38 */
93   uint8_t RESERVED_2[20];
94   __IO uint32_t AWRCR;                             /**< AHB Write Configuration Register, offset: 0x50 */
95   uint8_t RESERVED_3[12];
96   __IO uint32_t DLLCRA;                            /**< DLL Flash Memory A Configuration Register, offset: 0x60 */
97   __IO uint32_t DLLCRB;                            /**< DLL Flash Memory B Configuration Register, offset: 0x64 */
98   uint8_t RESERVED_4[4];
99   __IO uint32_t PARITYCR;                          /**< Parity Configuration Register, offset: 0x6C */
100   uint8_t RESERVED_5[144];
101   __IO uint32_t SFAR;                              /**< Serial Flash Memory Address Register, offset: 0x100 */
102   __IO uint32_t SFACR;                             /**< Serial Flash Memory Address Configuration Register, offset: 0x104 */
103   __IO uint32_t SMPR;                              /**< Sampling Register, offset: 0x108 */
104   __I  uint32_t RBSR;                              /**< RX Buffer Status Register, offset: 0x10C */
105   __IO uint32_t RBCT;                              /**< RX Buffer Control Register, offset: 0x110 */
106   uint8_t RESERVED_6[12];
107   __I  uint32_t AWRSR;                             /**< AHB Write Status Register, offset: 0x120 */
108   uint8_t RESERVED_7[8];
109   __I  uint32_t DLLSR;                             /**< DLL Status Register, offset: 0x12C */
110   __IO uint32_t DLCR;                              /**< Data Learning Configuration Register, offset: 0x130 */
111   __I  uint32_t DLSR_FA;                           /**< Data Learning Status Flash Memory A Register, offset: 0x134 */
112   __I  uint32_t DLSR_FB;                           /**< Data Learning Status Flash Memory B Register, offset: 0x138 */
113   uint8_t RESERVED_8[20];
114   __I  uint32_t TBSR;                              /**< TX Buffer Status Register, offset: 0x150 */
115   __IO uint32_t TBDR;                              /**< TX Buffer Data Register, offset: 0x154 */
116   __IO uint32_t TBCT;                              /**< TX Buffer Control Register, offset: 0x158 */
117   __I  uint32_t SR;                                /**< Status Register, offset: 0x15C */
118   __IO uint32_t FR;                                /**< Flag Register, offset: 0x160 */
119   __IO uint32_t RSER;                              /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
120   uint8_t RESERVED_9[4];
121   __IO uint32_t SPTRCLR;                           /**< Sequence Pointer Clear Register, offset: 0x16C */
122   uint8_t RESERVED_10[16];
123   __IO uint32_t SFA1AD;                            /**< Serial Flash Memory A1 Top Address Register, offset: 0x180 */
124   __IO uint32_t SFA2AD;                            /**< Serial Flash Memory A2 Top Address Register, offset: 0x184 */
125   __IO uint32_t SFB1AD;                            /**< Serial Flash Memory B1 Top Address Register, offset: 0x188 */
126   __IO uint32_t SFB2AD;                            /**< Serial Flash Memory B2 Top Address Register, offset: 0x18C */
127   __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0x190 */
128   __I  uint32_t FAILA_ADDR;                        /**< Flash Memory A Failing Address Status Register, offset: 0x194 */
129   __I  uint32_t FAILB_ADDR;                        /**< flash Memory B Failing Address Status Register, offset: 0x198 */
130   uint8_t RESERVED_11[100];
131   __I  uint32_t RBDR[QuadSPI_RBDR_COUNT];          /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
132   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x300 */
133   __IO uint32_t LCKCR;                             /**< LUT Lock Configuration Register, offset: 0x304 */
134   uint8_t RESERVED_12[8];
135   __IO uint32_t LUT[QuadSPI_LUT_COUNT];            /**< LUT Register, array offset: 0x310, array step: 0x4 */
136   uint8_t RESERVED_13[944];
137   struct {                                         /* offset: 0x800, array step: 0x20 */
138     __IO uint32_t WORD0;                             /**< Flash Region Start Address, array offset: 0x800, array step: 0x20 */
139     __IO uint32_t WORD1;                             /**< Flash Region End Address, array offset: 0x804, array step: 0x20 */
140     __IO uint32_t WORD2;                             /**< Flash Region Privileges, array offset: 0x808, array step: 0x20 */
141     __IO uint32_t WORD3;                             /**< Flash Region Lock Control, array offset: 0x80C, array step: 0x20 */
142     __I  uint32_t WORD4;                             /**< Flash Region Compare Address Status, array offset: 0x810, array step: 0x20 */
143     __I  uint32_t WORD5;                             /**< Flash Region Compare Status Data, array offset: 0x814, array step: 0x20 */
144     uint8_t RESERVED_0[8];
145   } FRAD[QuadSPI_FRAD_COUNT];
146   struct {                                         /* offset: 0x900, array step: 0x10 */
147     __IO uint32_t TGMDAD;                            /**< Target Group n Master Domain Access Descriptor, array offset: 0x900, array step: 0x10 */
148     __I  uint32_t TGSFAR;                            /**< Target Group n SFAR Address, array offset: 0x904, array step: 0x10 */
149     __IO uint32_t TGSFARS;                           /**< Target Group n SFAR Status, array offset: 0x908, array step: 0x10 */
150     __IO uint32_t TGIPCRS;                           /**< Target Group n IPCR Status, array offset: 0x90C, array step: 0x10 */
151   } MDAD[QuadSPI_MDAD_COUNT];
152   __IO uint32_t MGC;                               /**< Master Global Configuration, offset: 0x920 */
153   __IO uint32_t MRC;                               /**< Master Read Command, offset: 0x924 */
154   __IO uint32_t MTO;                               /**< Master Timeout, offset: 0x928 */
155   __IO uint32_t FLSEQREQ;                          /**< FlashSeq Request, offset: 0x92C */
156   __I  uint32_t FSMSTAT;                           /**< FSM Status, offset: 0x930 */
157   __IO uint32_t IPSERROR;                          /**< IPS Error, offset: 0x934 */
158   __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x938 */
159   __IO uint32_t INT_EN;                            /**< Interrupt Enable, offset: 0x93C */
160 } QuadSPI_Type, *QuadSPI_MemMapPtr;
161 
162 /** Number of instances of the QuadSPI module. */
163 #define QuadSPI_INSTANCE_COUNT                   (2u)
164 
165 /* QuadSPI - Peripheral instance base addresses */
166 /** Peripheral QUADSPI_0 base address */
167 #define IP_QUADSPI_0_BASE                        (0x42320000u)
168 /** Peripheral QUADSPI_0 base pointer */
169 #define IP_QUADSPI_0                             ((QuadSPI_Type *)IP_QUADSPI_0_BASE)
170 /** Peripheral QUADSPI_1 base address */
171 #define IP_QUADSPI_1_BASE                        (0x42340000u)
172 /** Peripheral QUADSPI_1 base pointer */
173 #define IP_QUADSPI_1                             ((QuadSPI_Type *)IP_QUADSPI_1_BASE)
174 /** Array initializer of QuadSPI peripheral base addresses */
175 #define IP_QuadSPI_BASE_ADDRS                    { IP_QUADSPI_0_BASE, IP_QUADSPI_1_BASE }
176 /** Array initializer of QuadSPI peripheral base pointers */
177 #define IP_QuadSPI_BASE_PTRS                     { IP_QUADSPI_0, IP_QUADSPI_1 }
178 
179 /* ----------------------------------------------------------------------------
180    -- QuadSPI Register Masks
181    ---------------------------------------------------------------------------- */
182 
183 /*!
184  * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
185  * @{
186  */
187 
188 /*! @name MCR - Module Configuration Register */
189 /*! @{ */
190 
191 #define QuadSPI_MCR_SWRSTSD_MASK                 (0x1U)
192 #define QuadSPI_MCR_SWRSTSD_SHIFT                (0U)
193 #define QuadSPI_MCR_SWRSTSD_WIDTH                (1U)
194 #define QuadSPI_MCR_SWRSTSD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK)
195 
196 #define QuadSPI_MCR_SWRSTHD_MASK                 (0x2U)
197 #define QuadSPI_MCR_SWRSTHD_SHIFT                (1U)
198 #define QuadSPI_MCR_SWRSTHD_WIDTH                (1U)
199 #define QuadSPI_MCR_SWRSTHD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
200 
201 #define QuadSPI_MCR_DQS_OUT_EN_MASK              (0x10U)
202 #define QuadSPI_MCR_DQS_OUT_EN_SHIFT             (4U)
203 #define QuadSPI_MCR_DQS_OUT_EN_WIDTH             (1U)
204 #define QuadSPI_MCR_DQS_OUT_EN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_OUT_EN_SHIFT)) & QuadSPI_MCR_DQS_OUT_EN_MASK)
205 
206 #define QuadSPI_MCR_DQS_EN_MASK                  (0x40U)
207 #define QuadSPI_MCR_DQS_EN_SHIFT                 (6U)
208 #define QuadSPI_MCR_DQS_EN_WIDTH                 (1U)
209 #define QuadSPI_MCR_DQS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK)
210 
211 #define QuadSPI_MCR_DDR_EN_MASK                  (0x80U)
212 #define QuadSPI_MCR_DDR_EN_SHIFT                 (7U)
213 #define QuadSPI_MCR_DDR_EN_WIDTH                 (1U)
214 #define QuadSPI_MCR_DDR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK)
215 
216 #define QuadSPI_MCR_VAR_LAT_EN_MASK              (0x100U)
217 #define QuadSPI_MCR_VAR_LAT_EN_SHIFT             (8U)
218 #define QuadSPI_MCR_VAR_LAT_EN_WIDTH             (1U)
219 #define QuadSPI_MCR_VAR_LAT_EN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_VAR_LAT_EN_SHIFT)) & QuadSPI_MCR_VAR_LAT_EN_MASK)
220 
221 #define QuadSPI_MCR_CLR_RXF_MASK                 (0x400U)
222 #define QuadSPI_MCR_CLR_RXF_SHIFT                (10U)
223 #define QuadSPI_MCR_CLR_RXF_WIDTH                (1U)
224 #define QuadSPI_MCR_CLR_RXF(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK)
225 
226 #define QuadSPI_MCR_CLR_TXF_MASK                 (0x800U)
227 #define QuadSPI_MCR_CLR_TXF_SHIFT                (11U)
228 #define QuadSPI_MCR_CLR_TXF_WIDTH                (1U)
229 #define QuadSPI_MCR_CLR_TXF(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK)
230 
231 #define QuadSPI_MCR_DLPEN_MASK                   (0x1000U)
232 #define QuadSPI_MCR_DLPEN_SHIFT                  (12U)
233 #define QuadSPI_MCR_DLPEN_WIDTH                  (1U)
234 #define QuadSPI_MCR_DLPEN(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DLPEN_SHIFT)) & QuadSPI_MCR_DLPEN_MASK)
235 
236 #define QuadSPI_MCR_MDIS_MASK                    (0x4000U)
237 #define QuadSPI_MCR_MDIS_SHIFT                   (14U)
238 #define QuadSPI_MCR_MDIS_WIDTH                   (1U)
239 #define QuadSPI_MCR_MDIS(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK)
240 
241 #define QuadSPI_MCR_ISD2FA_MASK                  (0x10000U)
242 #define QuadSPI_MCR_ISD2FA_SHIFT                 (16U)
243 #define QuadSPI_MCR_ISD2FA_WIDTH                 (1U)
244 #define QuadSPI_MCR_ISD2FA(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD2FA_SHIFT)) & QuadSPI_MCR_ISD2FA_MASK)
245 
246 #define QuadSPI_MCR_ISD3FA_MASK                  (0x20000U)
247 #define QuadSPI_MCR_ISD3FA_SHIFT                 (17U)
248 #define QuadSPI_MCR_ISD3FA_WIDTH                 (1U)
249 #define QuadSPI_MCR_ISD3FA(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)
250 
251 #define QuadSPI_MCR_ISD2FB_MASK                  (0x40000U)
252 #define QuadSPI_MCR_ISD2FB_SHIFT                 (18U)
253 #define QuadSPI_MCR_ISD2FB_WIDTH                 (1U)
254 #define QuadSPI_MCR_ISD2FB(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD2FB_SHIFT)) & QuadSPI_MCR_ISD2FB_MASK)
255 
256 #define QuadSPI_MCR_ISD3FB_MASK                  (0x80000U)
257 #define QuadSPI_MCR_ISD3FB_SHIFT                 (19U)
258 #define QuadSPI_MCR_ISD3FB_WIDTH                 (1U)
259 #define QuadSPI_MCR_ISD3FB(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FB_SHIFT)) & QuadSPI_MCR_ISD3FB_MASK)
260 
261 #define QuadSPI_MCR_DQS_FA_SEL_MASK              (0x3000000U)
262 #define QuadSPI_MCR_DQS_FA_SEL_SHIFT             (24U)
263 #define QuadSPI_MCR_DQS_FA_SEL_WIDTH             (2U)
264 #define QuadSPI_MCR_DQS_FA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_FA_SEL_SHIFT)) & QuadSPI_MCR_DQS_FA_SEL_MASK)
265 
266 #define QuadSPI_MCR_CKN_FA_EN_MASK               (0x4000000U)
267 #define QuadSPI_MCR_CKN_FA_EN_SHIFT              (26U)
268 #define QuadSPI_MCR_CKN_FA_EN_WIDTH              (1U)
269 #define QuadSPI_MCR_CKN_FA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CKN_FA_EN_SHIFT)) & QuadSPI_MCR_CKN_FA_EN_MASK)
270 
271 #define QuadSPI_MCR_CK2_DCARS_FA_MASK            (0x8000000U)
272 #define QuadSPI_MCR_CK2_DCARS_FA_SHIFT           (27U)
273 #define QuadSPI_MCR_CK2_DCARS_FA_WIDTH           (1U)
274 #define QuadSPI_MCR_CK2_DCARS_FA(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CK2_DCARS_FA_SHIFT)) & QuadSPI_MCR_CK2_DCARS_FA_MASK)
275 
276 #define QuadSPI_MCR_DQS_FB_SEL_MASK              (0x30000000U)
277 #define QuadSPI_MCR_DQS_FB_SEL_SHIFT             (28U)
278 #define QuadSPI_MCR_DQS_FB_SEL_WIDTH             (2U)
279 #define QuadSPI_MCR_DQS_FB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_FB_SEL_SHIFT)) & QuadSPI_MCR_DQS_FB_SEL_MASK)
280 
281 #define QuadSPI_MCR_CKN_FB_EN_MASK               (0x40000000U)
282 #define QuadSPI_MCR_CKN_FB_EN_SHIFT              (30U)
283 #define QuadSPI_MCR_CKN_FB_EN_WIDTH              (1U)
284 #define QuadSPI_MCR_CKN_FB_EN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CKN_FB_EN_SHIFT)) & QuadSPI_MCR_CKN_FB_EN_MASK)
285 
286 #define QuadSPI_MCR_CK2_DCARS_FB_MASK            (0x80000000U)
287 #define QuadSPI_MCR_CK2_DCARS_FB_SHIFT           (31U)
288 #define QuadSPI_MCR_CK2_DCARS_FB_WIDTH           (1U)
289 #define QuadSPI_MCR_CK2_DCARS_FB(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CK2_DCARS_FB_SHIFT)) & QuadSPI_MCR_CK2_DCARS_FB_MASK)
290 /*! @} */
291 
292 /*! @name IPCR - IP Configuration Register */
293 /*! @{ */
294 
295 #define QuadSPI_IPCR_IDATSZ_MASK                 (0xFFFFU)
296 #define QuadSPI_IPCR_IDATSZ_SHIFT                (0U)
297 #define QuadSPI_IPCR_IDATSZ_WIDTH                (16U)
298 #define QuadSPI_IPCR_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK)
299 
300 #define QuadSPI_IPCR_PAR_EN_MASK                 (0x10000U)
301 #define QuadSPI_IPCR_PAR_EN_SHIFT                (16U)
302 #define QuadSPI_IPCR_PAR_EN_WIDTH                (1U)
303 #define QuadSPI_IPCR_PAR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK)
304 
305 #define QuadSPI_IPCR_SEQID_MASK                  (0xF000000U)
306 #define QuadSPI_IPCR_SEQID_SHIFT                 (24U)
307 #define QuadSPI_IPCR_SEQID_WIDTH                 (4U)
308 #define QuadSPI_IPCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
309 /*! @} */
310 
311 /*! @name FLSHCR - Flash Memory Configuration Register */
312 /*! @{ */
313 
314 #define QuadSPI_FLSHCR_TCSS_MASK                 (0xFU)
315 #define QuadSPI_FLSHCR_TCSS_SHIFT                (0U)
316 #define QuadSPI_FLSHCR_TCSS_WIDTH                (4U)
317 #define QuadSPI_FLSHCR_TCSS(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK)
318 
319 #define QuadSPI_FLSHCR_TCSH_MASK                 (0xF00U)
320 #define QuadSPI_FLSHCR_TCSH_SHIFT                (8U)
321 #define QuadSPI_FLSHCR_TCSH_WIDTH                (4U)
322 #define QuadSPI_FLSHCR_TCSH(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK)
323 
324 #define QuadSPI_FLSHCR_TDH_MASK                  (0x30000U)
325 #define QuadSPI_FLSHCR_TDH_SHIFT                 (16U)
326 #define QuadSPI_FLSHCR_TDH_WIDTH                 (2U)
327 #define QuadSPI_FLSHCR_TDH(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
328 /*! @} */
329 
330 /*! @name BUF0CR - Buffer 0 Configuration Register */
331 /*! @{ */
332 
333 #define QuadSPI_BUF0CR_MSTRID_MASK               (0x3FU)
334 #define QuadSPI_BUF0CR_MSTRID_SHIFT              (0U)
335 #define QuadSPI_BUF0CR_MSTRID_WIDTH              (6U)
336 #define QuadSPI_BUF0CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK)
337 
338 #define QuadSPI_BUF0CR_ADATSZ_MASK               (0xFF00U)
339 #define QuadSPI_BUF0CR_ADATSZ_SHIFT              (8U)
340 #define QuadSPI_BUF0CR_ADATSZ_WIDTH              (8U)
341 #define QuadSPI_BUF0CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK)
342 /*! @} */
343 
344 /*! @name BUF1CR - Buffer 1 Configuration Register */
345 /*! @{ */
346 
347 #define QuadSPI_BUF1CR_MSTRID_MASK               (0x3FU)
348 #define QuadSPI_BUF1CR_MSTRID_SHIFT              (0U)
349 #define QuadSPI_BUF1CR_MSTRID_WIDTH              (6U)
350 #define QuadSPI_BUF1CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK)
351 
352 #define QuadSPI_BUF1CR_ADATSZ_MASK               (0xFF00U)
353 #define QuadSPI_BUF1CR_ADATSZ_SHIFT              (8U)
354 #define QuadSPI_BUF1CR_ADATSZ_WIDTH              (8U)
355 #define QuadSPI_BUF1CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK)
356 /*! @} */
357 
358 /*! @name BUF2CR - Buffer 2 Configuration Register */
359 /*! @{ */
360 
361 #define QuadSPI_BUF2CR_MSTRID_MASK               (0x3FU)
362 #define QuadSPI_BUF2CR_MSTRID_SHIFT              (0U)
363 #define QuadSPI_BUF2CR_MSTRID_WIDTH              (6U)
364 #define QuadSPI_BUF2CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK)
365 
366 #define QuadSPI_BUF2CR_ADATSZ_MASK               (0xFF00U)
367 #define QuadSPI_BUF2CR_ADATSZ_SHIFT              (8U)
368 #define QuadSPI_BUF2CR_ADATSZ_WIDTH              (8U)
369 #define QuadSPI_BUF2CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK)
370 /*! @} */
371 
372 /*! @name BUF3CR - Buffer 3 Configuration Register */
373 /*! @{ */
374 
375 #define QuadSPI_BUF3CR_MSTRID_MASK               (0x3FU)
376 #define QuadSPI_BUF3CR_MSTRID_SHIFT              (0U)
377 #define QuadSPI_BUF3CR_MSTRID_WIDTH              (6U)
378 #define QuadSPI_BUF3CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK)
379 
380 #define QuadSPI_BUF3CR_ADATSZ_MASK               (0x3FF00U)
381 #define QuadSPI_BUF3CR_ADATSZ_SHIFT              (8U)
382 #define QuadSPI_BUF3CR_ADATSZ_WIDTH              (10U)
383 #define QuadSPI_BUF3CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK)
384 
385 #define QuadSPI_BUF3CR_ALLMST_MASK               (0x80000000U)
386 #define QuadSPI_BUF3CR_ALLMST_SHIFT              (31U)
387 #define QuadSPI_BUF3CR_ALLMST_WIDTH              (1U)
388 #define QuadSPI_BUF3CR_ALLMST(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK)
389 /*! @} */
390 
391 /*! @name BFGENCR - Buffer Generic Configuration Register */
392 /*! @{ */
393 
394 #define QuadSPI_BFGENCR_SEQID_MASK               (0xF000U)
395 #define QuadSPI_BFGENCR_SEQID_SHIFT              (12U)
396 #define QuadSPI_BFGENCR_SEQID_WIDTH              (4U)
397 #define QuadSPI_BFGENCR_SEQID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK)
398 
399 #define QuadSPI_BFGENCR_PAR_EN_MASK              (0x10000U)
400 #define QuadSPI_BFGENCR_PAR_EN_SHIFT             (16U)
401 #define QuadSPI_BFGENCR_PAR_EN_WIDTH             (1U)
402 #define QuadSPI_BFGENCR_PAR_EN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK)
403 
404 #define QuadSPI_BFGENCR_SEQID_WR_EN_MASK         (0x20000U)
405 #define QuadSPI_BFGENCR_SEQID_WR_EN_SHIFT        (17U)
406 #define QuadSPI_BFGENCR_SEQID_WR_EN_WIDTH        (1U)
407 #define QuadSPI_BFGENCR_SEQID_WR_EN(x)           (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_WR_EN_SHIFT)) & QuadSPI_BFGENCR_SEQID_WR_EN_MASK)
408 
409 #define QuadSPI_BFGENCR_SEQID_WR_MASK            (0xF0000000U)
410 #define QuadSPI_BFGENCR_SEQID_WR_SHIFT           (28U)
411 #define QuadSPI_BFGENCR_SEQID_WR_WIDTH           (4U)
412 #define QuadSPI_BFGENCR_SEQID_WR(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_WR_SHIFT)) & QuadSPI_BFGENCR_SEQID_WR_MASK)
413 /*! @} */
414 
415 /*! @name SOCCR - SOC Configuration Register */
416 /*! @{ */
417 
418 #define QuadSPI_SOCCR_SOCCFG_MASK                (0xFFFFFFU)
419 #define QuadSPI_SOCCR_SOCCFG_SHIFT               (0U)
420 #define QuadSPI_SOCCR_SOCCFG_WIDTH               (24U)
421 #define QuadSPI_SOCCR_SOCCFG(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)
422 /*! @} */
423 
424 /*! @name BUF0IND - Buffer 0 Top Index Register */
425 /*! @{ */
426 
427 #define QuadSPI_BUF0IND_TPINDX0_MASK             (0x7F8U)
428 #define QuadSPI_BUF0IND_TPINDX0_SHIFT            (3U)
429 #define QuadSPI_BUF0IND_TPINDX0_WIDTH            (8U)
430 #define QuadSPI_BUF0IND_TPINDX0(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK)
431 /*! @} */
432 
433 /*! @name BUF1IND - Buffer 1 Top Index Register */
434 /*! @{ */
435 
436 #define QuadSPI_BUF1IND_TPINDX1_MASK             (0x7F8U)
437 #define QuadSPI_BUF1IND_TPINDX1_SHIFT            (3U)
438 #define QuadSPI_BUF1IND_TPINDX1_WIDTH            (8U)
439 #define QuadSPI_BUF1IND_TPINDX1(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK)
440 /*! @} */
441 
442 /*! @name BUF2IND - Buffer 2 Top Index Register */
443 /*! @{ */
444 
445 #define QuadSPI_BUF2IND_TPINDX2_MASK             (0x7F8U)
446 #define QuadSPI_BUF2IND_TPINDX2_SHIFT            (3U)
447 #define QuadSPI_BUF2IND_TPINDX2_WIDTH            (8U)
448 #define QuadSPI_BUF2IND_TPINDX2(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
449 /*! @} */
450 
451 /*! @name AWRCR - AHB Write Configuration Register */
452 /*! @{ */
453 
454 #define QuadSPI_AWRCR_AWTRGLVL_MASK              (0xFFU)
455 #define QuadSPI_AWRCR_AWTRGLVL_SHIFT             (0U)
456 #define QuadSPI_AWRCR_AWTRGLVL_WIDTH             (8U)
457 #define QuadSPI_AWRCR_AWTRGLVL(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_AWRCR_AWTRGLVL_SHIFT)) & QuadSPI_AWRCR_AWTRGLVL_MASK)
458 
459 #define QuadSPI_AWRCR_PPW_RD_DIS_MASK            (0x4000U)
460 #define QuadSPI_AWRCR_PPW_RD_DIS_SHIFT           (14U)
461 #define QuadSPI_AWRCR_PPW_RD_DIS_WIDTH           (1U)
462 #define QuadSPI_AWRCR_PPW_RD_DIS(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_AWRCR_PPW_RD_DIS_SHIFT)) & QuadSPI_AWRCR_PPW_RD_DIS_MASK)
463 
464 #define QuadSPI_AWRCR_PPW_WR_DIS_MASK            (0x8000U)
465 #define QuadSPI_AWRCR_PPW_WR_DIS_SHIFT           (15U)
466 #define QuadSPI_AWRCR_PPW_WR_DIS_WIDTH           (1U)
467 #define QuadSPI_AWRCR_PPW_WR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_AWRCR_PPW_WR_DIS_SHIFT)) & QuadSPI_AWRCR_PPW_WR_DIS_MASK)
468 /*! @} */
469 
470 /*! @name DLLCRA - DLL Flash Memory A Configuration Register */
471 /*! @{ */
472 
473 #define QuadSPI_DLLCRA_SLV_UPD_MASK              (0x1U)
474 #define QuadSPI_DLLCRA_SLV_UPD_SHIFT             (0U)
475 #define QuadSPI_DLLCRA_SLV_UPD_WIDTH             (1U)
476 #define QuadSPI_DLLCRA_SLV_UPD(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_UPD_SHIFT)) & QuadSPI_DLLCRA_SLV_UPD_MASK)
477 
478 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK       (0x2U)
479 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT      (1U)
480 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_WIDTH      (1U)
481 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT)) & QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK)
482 
483 #define QuadSPI_DLLCRA_SLV_EN_MASK               (0x4U)
484 #define QuadSPI_DLLCRA_SLV_EN_SHIFT              (2U)
485 #define QuadSPI_DLLCRA_SLV_EN_WIDTH              (1U)
486 #define QuadSPI_DLLCRA_SLV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_EN_SHIFT)) & QuadSPI_DLLCRA_SLV_EN_MASK)
487 
488 #define QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK      (0x8U)
489 #define QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_SHIFT     (3U)
490 #define QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_WIDTH     (1U)
491 #define QuadSPI_DLLCRA_SLAVE_AUTO_UPDT(x)        (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_SHIFT)) & QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK)
492 
493 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK       (0xF00U)
494 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_SHIFT      (8U)
495 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_WIDTH      (4U)
496 #define QuadSPI_DLLCRA_SLV_DLY_COARSE(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)) & QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK)
497 
498 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK       (0x7000U)
499 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT      (12U)
500 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_WIDTH      (3U)
501 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)) & QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
502 
503 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK      (0xF0000U)
504 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT     (16U)
505 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_WIDTH     (4U)
506 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)) & QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK)
507 
508 #define QuadSPI_DLLCRA_DLLRES_MASK               (0xF00000U)
509 #define QuadSPI_DLLCRA_DLLRES_SHIFT              (20U)
510 #define QuadSPI_DLLCRA_DLLRES_WIDTH              (4U)
511 #define QuadSPI_DLLCRA_DLLRES(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_DLLRES_SHIFT)) & QuadSPI_DLLCRA_DLLRES_MASK)
512 
513 #define QuadSPI_DLLCRA_DLL_REFCNTR_MASK          (0xF000000U)
514 #define QuadSPI_DLLCRA_DLL_REFCNTR_SHIFT         (24U)
515 #define QuadSPI_DLLCRA_DLL_REFCNTR_WIDTH         (4U)
516 #define QuadSPI_DLLCRA_DLL_REFCNTR(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_DLL_REFCNTR_SHIFT)) & QuadSPI_DLLCRA_DLL_REFCNTR_MASK)
517 
518 #define QuadSPI_DLLCRA_FREQEN_MASK               (0x40000000U)
519 #define QuadSPI_DLLCRA_FREQEN_SHIFT              (30U)
520 #define QuadSPI_DLLCRA_FREQEN_WIDTH              (1U)
521 #define QuadSPI_DLLCRA_FREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_FREQEN_SHIFT)) & QuadSPI_DLLCRA_FREQEN_MASK)
522 
523 #define QuadSPI_DLLCRA_DLLEN_MASK                (0x80000000U)
524 #define QuadSPI_DLLCRA_DLLEN_SHIFT               (31U)
525 #define QuadSPI_DLLCRA_DLLEN_WIDTH               (1U)
526 #define QuadSPI_DLLCRA_DLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_DLLEN_SHIFT)) & QuadSPI_DLLCRA_DLLEN_MASK)
527 /*! @} */
528 
529 /*! @name DLLCRB - DLL Flash Memory B Configuration Register */
530 /*! @{ */
531 
532 #define QuadSPI_DLLCRB_SLV_UPD_MASK              (0x1U)
533 #define QuadSPI_DLLCRB_SLV_UPD_SHIFT             (0U)
534 #define QuadSPI_DLLCRB_SLV_UPD_WIDTH             (1U)
535 #define QuadSPI_DLLCRB_SLV_UPD(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_UPD_SHIFT)) & QuadSPI_DLLCRB_SLV_UPD_MASK)
536 
537 #define QuadSPI_DLLCRB_SLV_DLL_BYPASS_MASK       (0x2U)
538 #define QuadSPI_DLLCRB_SLV_DLL_BYPASS_SHIFT      (1U)
539 #define QuadSPI_DLLCRB_SLV_DLL_BYPASS_WIDTH      (1U)
540 #define QuadSPI_DLLCRB_SLV_DLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_DLL_BYPASS_SHIFT)) & QuadSPI_DLLCRB_SLV_DLL_BYPASS_MASK)
541 
542 #define QuadSPI_DLLCRB_SLV_EN_MASK               (0x4U)
543 #define QuadSPI_DLLCRB_SLV_EN_SHIFT              (2U)
544 #define QuadSPI_DLLCRB_SLV_EN_WIDTH              (1U)
545 #define QuadSPI_DLLCRB_SLV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_EN_SHIFT)) & QuadSPI_DLLCRB_SLV_EN_MASK)
546 
547 #define QuadSPI_DLLCRB_SLAVE_AUTO_UPDT_MASK      (0x8U)
548 #define QuadSPI_DLLCRB_SLAVE_AUTO_UPDT_SHIFT     (3U)
549 #define QuadSPI_DLLCRB_SLAVE_AUTO_UPDT_WIDTH     (1U)
550 #define QuadSPI_DLLCRB_SLAVE_AUTO_UPDT(x)        (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLAVE_AUTO_UPDT_SHIFT)) & QuadSPI_DLLCRB_SLAVE_AUTO_UPDT_MASK)
551 
552 #define QuadSPI_DLLCRB_SLV_DLY_COARSE_MASK       (0xF00U)
553 #define QuadSPI_DLLCRB_SLV_DLY_COARSE_SHIFT      (8U)
554 #define QuadSPI_DLLCRB_SLV_DLY_COARSE_WIDTH      (4U)
555 #define QuadSPI_DLLCRB_SLV_DLY_COARSE(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_DLY_COARSE_SHIFT)) & QuadSPI_DLLCRB_SLV_DLY_COARSE_MASK)
556 
557 #define QuadSPI_DLLCRB_SLV_DLY_OFFSET_MASK       (0x7000U)
558 #define QuadSPI_DLLCRB_SLV_DLY_OFFSET_SHIFT      (12U)
559 #define QuadSPI_DLLCRB_SLV_DLY_OFFSET_WIDTH      (3U)
560 #define QuadSPI_DLLCRB_SLV_DLY_OFFSET(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_DLY_OFFSET_SHIFT)) & QuadSPI_DLLCRB_SLV_DLY_OFFSET_MASK)
561 
562 #define QuadSPI_DLLCRB_SLV_FINE_OFFSET_MASK      (0xF0000U)
563 #define QuadSPI_DLLCRB_SLV_FINE_OFFSET_SHIFT     (16U)
564 #define QuadSPI_DLLCRB_SLV_FINE_OFFSET_WIDTH     (4U)
565 #define QuadSPI_DLLCRB_SLV_FINE_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_SLV_FINE_OFFSET_SHIFT)) & QuadSPI_DLLCRB_SLV_FINE_OFFSET_MASK)
566 
567 #define QuadSPI_DLLCRB_DLLRES_MASK               (0xF00000U)
568 #define QuadSPI_DLLCRB_DLLRES_SHIFT              (20U)
569 #define QuadSPI_DLLCRB_DLLRES_WIDTH              (4U)
570 #define QuadSPI_DLLCRB_DLLRES(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_DLLRES_SHIFT)) & QuadSPI_DLLCRB_DLLRES_MASK)
571 
572 #define QuadSPI_DLLCRB_DLL_REFCNTR_MASK          (0xF000000U)
573 #define QuadSPI_DLLCRB_DLL_REFCNTR_SHIFT         (24U)
574 #define QuadSPI_DLLCRB_DLL_REFCNTR_WIDTH         (4U)
575 #define QuadSPI_DLLCRB_DLL_REFCNTR(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_DLL_REFCNTR_SHIFT)) & QuadSPI_DLLCRB_DLL_REFCNTR_MASK)
576 
577 #define QuadSPI_DLLCRB_FREQEN_MASK               (0x40000000U)
578 #define QuadSPI_DLLCRB_FREQEN_SHIFT              (30U)
579 #define QuadSPI_DLLCRB_FREQEN_WIDTH              (1U)
580 #define QuadSPI_DLLCRB_FREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_FREQEN_SHIFT)) & QuadSPI_DLLCRB_FREQEN_MASK)
581 
582 #define QuadSPI_DLLCRB_DLLEN_MASK                (0x80000000U)
583 #define QuadSPI_DLLCRB_DLLEN_SHIFT               (31U)
584 #define QuadSPI_DLLCRB_DLLEN_WIDTH               (1U)
585 #define QuadSPI_DLLCRB_DLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRB_DLLEN_SHIFT)) & QuadSPI_DLLCRB_DLLEN_MASK)
586 /*! @} */
587 
588 /*! @name PARITYCR - Parity Configuration Register */
589 /*! @{ */
590 
591 #define QuadSPI_PARITYCR_CRCBIN_FA_MASK          (0x20U)
592 #define QuadSPI_PARITYCR_CRCBIN_FA_SHIFT         (5U)
593 #define QuadSPI_PARITYCR_CRCBIN_FA_WIDTH         (1U)
594 #define QuadSPI_PARITYCR_CRCBIN_FA(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCBIN_FA_SHIFT)) & QuadSPI_PARITYCR_CRCBIN_FA_MASK)
595 
596 #define QuadSPI_PARITYCR_CRCBEN_FA_MASK          (0x40U)
597 #define QuadSPI_PARITYCR_CRCBEN_FA_SHIFT         (6U)
598 #define QuadSPI_PARITYCR_CRCBEN_FA_WIDTH         (1U)
599 #define QuadSPI_PARITYCR_CRCBEN_FA(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCBEN_FA_SHIFT)) & QuadSPI_PARITYCR_CRCBEN_FA_MASK)
600 
601 #define QuadSPI_PARITYCR_CRCEN_FA_MASK           (0x80U)
602 #define QuadSPI_PARITYCR_CRCEN_FA_SHIFT          (7U)
603 #define QuadSPI_PARITYCR_CRCEN_FA_WIDTH          (1U)
604 #define QuadSPI_PARITYCR_CRCEN_FA(x)             (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCEN_FA_SHIFT)) & QuadSPI_PARITYCR_CRCEN_FA_MASK)
605 
606 #define QuadSPI_PARITYCR_BYTE_SIZE_FA_MASK       (0x100U)
607 #define QuadSPI_PARITYCR_BYTE_SIZE_FA_SHIFT      (8U)
608 #define QuadSPI_PARITYCR_BYTE_SIZE_FA_WIDTH      (1U)
609 #define QuadSPI_PARITYCR_BYTE_SIZE_FA(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_BYTE_SIZE_FA_SHIFT)) & QuadSPI_PARITYCR_BYTE_SIZE_FA_MASK)
610 
611 #define QuadSPI_PARITYCR_CHUNKSIZE_FA_MASK       (0x7E00U)
612 #define QuadSPI_PARITYCR_CHUNKSIZE_FA_SHIFT      (9U)
613 #define QuadSPI_PARITYCR_CHUNKSIZE_FA_WIDTH      (6U)
614 #define QuadSPI_PARITYCR_CHUNKSIZE_FA(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CHUNKSIZE_FA_SHIFT)) & QuadSPI_PARITYCR_CHUNKSIZE_FA_MASK)
615 
616 #define QuadSPI_PARITYCR_CRC_WNDW_FA_MASK        (0x8000U)
617 #define QuadSPI_PARITYCR_CRC_WNDW_FA_SHIFT       (15U)
618 #define QuadSPI_PARITYCR_CRC_WNDW_FA_WIDTH       (1U)
619 #define QuadSPI_PARITYCR_CRC_WNDW_FA(x)          (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRC_WNDW_FA_SHIFT)) & QuadSPI_PARITYCR_CRC_WNDW_FA_MASK)
620 
621 #define QuadSPI_PARITYCR_CRCBIN_FB_MASK          (0x200000U)
622 #define QuadSPI_PARITYCR_CRCBIN_FB_SHIFT         (21U)
623 #define QuadSPI_PARITYCR_CRCBIN_FB_WIDTH         (1U)
624 #define QuadSPI_PARITYCR_CRCBIN_FB(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCBIN_FB_SHIFT)) & QuadSPI_PARITYCR_CRCBIN_FB_MASK)
625 
626 #define QuadSPI_PARITYCR_CRCBEN_FB_MASK          (0x400000U)
627 #define QuadSPI_PARITYCR_CRCBEN_FB_SHIFT         (22U)
628 #define QuadSPI_PARITYCR_CRCBEN_FB_WIDTH         (1U)
629 #define QuadSPI_PARITYCR_CRCBEN_FB(x)            (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCBEN_FB_SHIFT)) & QuadSPI_PARITYCR_CRCBEN_FB_MASK)
630 
631 #define QuadSPI_PARITYCR_CRCEN_FB_MASK           (0x800000U)
632 #define QuadSPI_PARITYCR_CRCEN_FB_SHIFT          (23U)
633 #define QuadSPI_PARITYCR_CRCEN_FB_WIDTH          (1U)
634 #define QuadSPI_PARITYCR_CRCEN_FB(x)             (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRCEN_FB_SHIFT)) & QuadSPI_PARITYCR_CRCEN_FB_MASK)
635 
636 #define QuadSPI_PARITYCR_BYTE_SIZE_FB_MASK       (0x1000000U)
637 #define QuadSPI_PARITYCR_BYTE_SIZE_FB_SHIFT      (24U)
638 #define QuadSPI_PARITYCR_BYTE_SIZE_FB_WIDTH      (1U)
639 #define QuadSPI_PARITYCR_BYTE_SIZE_FB(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_BYTE_SIZE_FB_SHIFT)) & QuadSPI_PARITYCR_BYTE_SIZE_FB_MASK)
640 
641 #define QuadSPI_PARITYCR_CHUNKSIZE_FB_MASK       (0x7E000000U)
642 #define QuadSPI_PARITYCR_CHUNKSIZE_FB_SHIFT      (25U)
643 #define QuadSPI_PARITYCR_CHUNKSIZE_FB_WIDTH      (6U)
644 #define QuadSPI_PARITYCR_CHUNKSIZE_FB(x)         (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CHUNKSIZE_FB_SHIFT)) & QuadSPI_PARITYCR_CHUNKSIZE_FB_MASK)
645 
646 #define QuadSPI_PARITYCR_CRC_WNDW_FB_MASK        (0x80000000U)
647 #define QuadSPI_PARITYCR_CRC_WNDW_FB_SHIFT       (31U)
648 #define QuadSPI_PARITYCR_CRC_WNDW_FB_WIDTH       (1U)
649 #define QuadSPI_PARITYCR_CRC_WNDW_FB(x)          (((uint32_t)(((uint32_t)(x)) << QuadSPI_PARITYCR_CRC_WNDW_FB_SHIFT)) & QuadSPI_PARITYCR_CRC_WNDW_FB_MASK)
650 /*! @} */
651 
652 /*! @name SFAR - Serial Flash Memory Address Register */
653 /*! @{ */
654 
655 #define QuadSPI_SFAR_SFADR_MASK                  (0xFFFFFFFFU)
656 #define QuadSPI_SFAR_SFADR_SHIFT                 (0U)
657 #define QuadSPI_SFAR_SFADR_WIDTH                 (32U)
658 #define QuadSPI_SFAR_SFADR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK)
659 /*! @} */
660 
661 /*! @name SFACR - Serial Flash Memory Address Configuration Register */
662 /*! @{ */
663 
664 #define QuadSPI_SFACR_CAS_MASK                   (0xFU)
665 #define QuadSPI_SFACR_CAS_SHIFT                  (0U)
666 #define QuadSPI_SFACR_CAS_WIDTH                  (4U)
667 #define QuadSPI_SFACR_CAS(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK)
668 
669 #define QuadSPI_SFACR_PPWB_MASK                  (0x1F00U)
670 #define QuadSPI_SFACR_PPWB_SHIFT                 (8U)
671 #define QuadSPI_SFACR_PPWB_WIDTH                 (5U)
672 #define QuadSPI_SFACR_PPWB(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_PPWB_SHIFT)) & QuadSPI_SFACR_PPWB_MASK)
673 
674 #define QuadSPI_SFACR_WA_MASK                    (0x10000U)
675 #define QuadSPI_SFACR_WA_SHIFT                   (16U)
676 #define QuadSPI_SFACR_WA_WIDTH                   (1U)
677 #define QuadSPI_SFACR_WA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK)
678 
679 #define QuadSPI_SFACR_BYTE_SWAP_MASK             (0x20000U)
680 #define QuadSPI_SFACR_BYTE_SWAP_SHIFT            (17U)
681 #define QuadSPI_SFACR_BYTE_SWAP_WIDTH            (1U)
682 #define QuadSPI_SFACR_BYTE_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_BYTE_SWAP_SHIFT)) & QuadSPI_SFACR_BYTE_SWAP_MASK)
683 /*! @} */
684 
685 /*! @name SMPR - Sampling Register */
686 /*! @{ */
687 
688 #define QuadSPI_SMPR_FSPHS_MASK                  (0x20U)
689 #define QuadSPI_SMPR_FSPHS_SHIFT                 (5U)
690 #define QuadSPI_SMPR_FSPHS_WIDTH                 (1U)
691 #define QuadSPI_SMPR_FSPHS(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK)
692 
693 #define QuadSPI_SMPR_FSDLY_MASK                  (0x40U)
694 #define QuadSPI_SMPR_FSDLY_SHIFT                 (6U)
695 #define QuadSPI_SMPR_FSDLY_WIDTH                 (1U)
696 #define QuadSPI_SMPR_FSDLY(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK)
697 
698 #define QuadSPI_SMPR_DLLFSMPFA_MASK              (0x7000000U)
699 #define QuadSPI_SMPR_DLLFSMPFA_SHIFT             (24U)
700 #define QuadSPI_SMPR_DLLFSMPFA_WIDTH             (3U)
701 #define QuadSPI_SMPR_DLLFSMPFA(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DLLFSMPFA_SHIFT)) & QuadSPI_SMPR_DLLFSMPFA_MASK)
702 
703 #define QuadSPI_SMPR_DLLFSMPFB_MASK              (0x70000000U)
704 #define QuadSPI_SMPR_DLLFSMPFB_SHIFT             (28U)
705 #define QuadSPI_SMPR_DLLFSMPFB_WIDTH             (3U)
706 #define QuadSPI_SMPR_DLLFSMPFB(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DLLFSMPFB_SHIFT)) & QuadSPI_SMPR_DLLFSMPFB_MASK)
707 /*! @} */
708 
709 /*! @name RBSR - RX Buffer Status Register */
710 /*! @{ */
711 
712 #define QuadSPI_RBSR_RDBFL_MASK                  (0xFFU)
713 #define QuadSPI_RBSR_RDBFL_SHIFT                 (0U)
714 #define QuadSPI_RBSR_RDBFL_WIDTH                 (8U)
715 #define QuadSPI_RBSR_RDBFL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK)
716 
717 #define QuadSPI_RBSR_RDCTR_MASK                  (0xFFFF0000U)
718 #define QuadSPI_RBSR_RDCTR_SHIFT                 (16U)
719 #define QuadSPI_RBSR_RDCTR_WIDTH                 (16U)
720 #define QuadSPI_RBSR_RDCTR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK)
721 /*! @} */
722 
723 /*! @name RBCT - RX Buffer Control Register */
724 /*! @{ */
725 
726 #define QuadSPI_RBCT_WMRK_MASK                   (0x7FU)
727 #define QuadSPI_RBCT_WMRK_SHIFT                  (0U)
728 #define QuadSPI_RBCT_WMRK_WIDTH                  (7U)
729 #define QuadSPI_RBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK)
730 /*! @} */
731 
732 /*! @name AWRSR - AHB Write Status Register */
733 /*! @{ */
734 
735 #define QuadSPI_AWRSR_SEQAUJOIN_MASK             (0x4U)
736 #define QuadSPI_AWRSR_SEQAUJOIN_SHIFT            (2U)
737 #define QuadSPI_AWRSR_SEQAUJOIN_WIDTH            (1U)
738 #define QuadSPI_AWRSR_SEQAUJOIN(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_AWRSR_SEQAUJOIN_SHIFT)) & QuadSPI_AWRSR_SEQAUJOIN_MASK)
739 /*! @} */
740 
741 /*! @name DLLSR - DLL Status Register */
742 /*! @{ */
743 
744 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK   (0xFU)
745 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT  (0U)
746 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_WIDTH  (4U)
747 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL(x)     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK)
748 
749 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK     (0xF0U)
750 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT    (4U)
751 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_WIDTH    (4U)
752 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL(x)       (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK)
753 
754 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK   (0x1000U)
755 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT  (12U)
756 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_WIDTH  (1U)
757 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW(x)     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK)
758 
759 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK        (0x2000U)
760 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_SHIFT       (13U)
761 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_WIDTH       (1U)
762 #define QuadSPI_DLLSR_DLLA_RANGE_ERR(x)          (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_RANGE_ERR_SHIFT)) & QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK)
763 
764 #define QuadSPI_DLLSR_SLVA_LOCK_MASK             (0x4000U)
765 #define QuadSPI_DLLSR_SLVA_LOCK_SHIFT            (14U)
766 #define QuadSPI_DLLSR_SLVA_LOCK_WIDTH            (1U)
767 #define QuadSPI_DLLSR_SLVA_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_SLVA_LOCK_SHIFT)) & QuadSPI_DLLSR_SLVA_LOCK_MASK)
768 
769 #define QuadSPI_DLLSR_DLLA_LOCK_MASK             (0x8000U)
770 #define QuadSPI_DLLSR_DLLA_LOCK_SHIFT            (15U)
771 #define QuadSPI_DLLSR_DLLA_LOCK_WIDTH            (1U)
772 #define QuadSPI_DLLSR_DLLA_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_LOCK_SHIFT)) & QuadSPI_DLLSR_DLLA_LOCK_MASK)
773 
774 #define QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL_MASK   (0xF0000U)
775 #define QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL_SHIFT  (16U)
776 #define QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL_WIDTH  (4U)
777 #define QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL(x)     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLB_SLV_COARSE_VAL_MASK)
778 
779 #define QuadSPI_DLLSR_DLLB_SLV_FINE_VAL_MASK     (0xF00000U)
780 #define QuadSPI_DLLSR_DLLB_SLV_FINE_VAL_SHIFT    (20U)
781 #define QuadSPI_DLLSR_DLLB_SLV_FINE_VAL_WIDTH    (4U)
782 #define QuadSPI_DLLSR_DLLB_SLV_FINE_VAL(x)       (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLB_SLV_FINE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLB_SLV_FINE_VAL_MASK)
783 
784 #define QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK   (0x10000000U)
785 #define QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_SHIFT  (28U)
786 #define QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_WIDTH  (1U)
787 #define QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW(x)     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK)
788 
789 #define QuadSPI_DLLSR_DLLB_RANGE_ERR_MASK        (0x20000000U)
790 #define QuadSPI_DLLSR_DLLB_RANGE_ERR_SHIFT       (29U)
791 #define QuadSPI_DLLSR_DLLB_RANGE_ERR_WIDTH       (1U)
792 #define QuadSPI_DLLSR_DLLB_RANGE_ERR(x)          (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLB_RANGE_ERR_SHIFT)) & QuadSPI_DLLSR_DLLB_RANGE_ERR_MASK)
793 
794 #define QuadSPI_DLLSR_SLVB_LOCK_MASK             (0x40000000U)
795 #define QuadSPI_DLLSR_SLVB_LOCK_SHIFT            (30U)
796 #define QuadSPI_DLLSR_SLVB_LOCK_WIDTH            (1U)
797 #define QuadSPI_DLLSR_SLVB_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_SLVB_LOCK_SHIFT)) & QuadSPI_DLLSR_SLVB_LOCK_MASK)
798 
799 #define QuadSPI_DLLSR_DLLB_LOCK_MASK             (0x80000000U)
800 #define QuadSPI_DLLSR_DLLB_LOCK_SHIFT            (31U)
801 #define QuadSPI_DLLSR_DLLB_LOCK_WIDTH            (1U)
802 #define QuadSPI_DLLSR_DLLB_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLB_LOCK_SHIFT)) & QuadSPI_DLLSR_DLLB_LOCK_MASK)
803 /*! @} */
804 
805 /*! @name DLCR - Data Learning Configuration Register */
806 /*! @{ */
807 
808 #define QuadSPI_DLCR_DLP_SEL_FA_MASK             (0xC000U)
809 #define QuadSPI_DLCR_DLP_SEL_FA_SHIFT            (14U)
810 #define QuadSPI_DLCR_DLP_SEL_FA_WIDTH            (2U)
811 #define QuadSPI_DLCR_DLP_SEL_FA(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLCR_DLP_SEL_FA_SHIFT)) & QuadSPI_DLCR_DLP_SEL_FA_MASK)
812 
813 #define QuadSPI_DLCR_DL_NONDLP_FLSH_MASK         (0x1000000U)
814 #define QuadSPI_DLCR_DL_NONDLP_FLSH_SHIFT        (24U)
815 #define QuadSPI_DLCR_DL_NONDLP_FLSH_WIDTH        (1U)
816 #define QuadSPI_DLCR_DL_NONDLP_FLSH(x)           (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLCR_DL_NONDLP_FLSH_SHIFT)) & QuadSPI_DLCR_DL_NONDLP_FLSH_MASK)
817 
818 #define QuadSPI_DLCR_DLP_SEL_FB_MASK             (0xC0000000U)
819 #define QuadSPI_DLCR_DLP_SEL_FB_SHIFT            (30U)
820 #define QuadSPI_DLCR_DLP_SEL_FB_WIDTH            (2U)
821 #define QuadSPI_DLCR_DLP_SEL_FB(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLCR_DLP_SEL_FB_SHIFT)) & QuadSPI_DLCR_DLP_SEL_FB_MASK)
822 /*! @} */
823 
824 /*! @name DLSR_FA - Data Learning Status Flash Memory A Register */
825 /*! @{ */
826 
827 #define QuadSPI_DLSR_FA_NEG_EDGE_MASK            (0xFFU)
828 #define QuadSPI_DLSR_FA_NEG_EDGE_SHIFT           (0U)
829 #define QuadSPI_DLSR_FA_NEG_EDGE_WIDTH           (8U)
830 #define QuadSPI_DLSR_FA_NEG_EDGE(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_NEG_EDGE_SHIFT)) & QuadSPI_DLSR_FA_NEG_EDGE_MASK)
831 
832 #define QuadSPI_DLSR_FA_POS_EDGE_MASK            (0xFF00U)
833 #define QuadSPI_DLSR_FA_POS_EDGE_SHIFT           (8U)
834 #define QuadSPI_DLSR_FA_POS_EDGE_WIDTH           (8U)
835 #define QuadSPI_DLSR_FA_POS_EDGE(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_POS_EDGE_SHIFT)) & QuadSPI_DLSR_FA_POS_EDGE_MASK)
836 
837 #define QuadSPI_DLSR_FA_DLPFFA_MASK              (0x80000000U)
838 #define QuadSPI_DLSR_FA_DLPFFA_SHIFT             (31U)
839 #define QuadSPI_DLSR_FA_DLPFFA_WIDTH             (1U)
840 #define QuadSPI_DLSR_FA_DLPFFA(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_DLPFFA_SHIFT)) & QuadSPI_DLSR_FA_DLPFFA_MASK)
841 /*! @} */
842 
843 /*! @name DLSR_FB - Data Learning Status Flash Memory B Register */
844 /*! @{ */
845 
846 #define QuadSPI_DLSR_FB_NEG_EDGE_MASK            (0xFFU)
847 #define QuadSPI_DLSR_FB_NEG_EDGE_SHIFT           (0U)
848 #define QuadSPI_DLSR_FB_NEG_EDGE_WIDTH           (8U)
849 #define QuadSPI_DLSR_FB_NEG_EDGE(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FB_NEG_EDGE_SHIFT)) & QuadSPI_DLSR_FB_NEG_EDGE_MASK)
850 
851 #define QuadSPI_DLSR_FB_POS_EDGE_MASK            (0xFF00U)
852 #define QuadSPI_DLSR_FB_POS_EDGE_SHIFT           (8U)
853 #define QuadSPI_DLSR_FB_POS_EDGE_WIDTH           (8U)
854 #define QuadSPI_DLSR_FB_POS_EDGE(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FB_POS_EDGE_SHIFT)) & QuadSPI_DLSR_FB_POS_EDGE_MASK)
855 
856 #define QuadSPI_DLSR_FB_DLPFFB_MASK              (0x80000000U)
857 #define QuadSPI_DLSR_FB_DLPFFB_SHIFT             (31U)
858 #define QuadSPI_DLSR_FB_DLPFFB_WIDTH             (1U)
859 #define QuadSPI_DLSR_FB_DLPFFB(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FB_DLPFFB_SHIFT)) & QuadSPI_DLSR_FB_DLPFFB_MASK)
860 /*! @} */
861 
862 /*! @name TBSR - TX Buffer Status Register */
863 /*! @{ */
864 
865 #define QuadSPI_TBSR_TRBFL_MASK                  (0x1FFU)
866 #define QuadSPI_TBSR_TRBFL_SHIFT                 (0U)
867 #define QuadSPI_TBSR_TRBFL_WIDTH                 (9U)
868 #define QuadSPI_TBSR_TRBFL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK)
869 
870 #define QuadSPI_TBSR_TRCTR_MASK                  (0xFFFF0000U)
871 #define QuadSPI_TBSR_TRCTR_SHIFT                 (16U)
872 #define QuadSPI_TBSR_TRCTR_WIDTH                 (16U)
873 #define QuadSPI_TBSR_TRCTR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK)
874 /*! @} */
875 
876 /*! @name TBDR - TX Buffer Data Register */
877 /*! @{ */
878 
879 #define QuadSPI_TBDR_TXDATA_MASK                 (0xFFFFFFFFU)
880 #define QuadSPI_TBDR_TXDATA_SHIFT                (0U)
881 #define QuadSPI_TBDR_TXDATA_WIDTH                (32U)
882 #define QuadSPI_TBDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK)
883 /*! @} */
884 
885 /*! @name TBCT - TX Buffer Control Register */
886 /*! @{ */
887 
888 #define QuadSPI_TBCT_WMRK_MASK                   (0xFFU)
889 #define QuadSPI_TBCT_WMRK_SHIFT                  (0U)
890 #define QuadSPI_TBCT_WMRK_WIDTH                  (8U)
891 #define QuadSPI_TBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK)
892 /*! @} */
893 
894 /*! @name SR - Status Register */
895 /*! @{ */
896 
897 #define QuadSPI_SR_BUSY_MASK                     (0x1U)
898 #define QuadSPI_SR_BUSY_SHIFT                    (0U)
899 #define QuadSPI_SR_BUSY_WIDTH                    (1U)
900 #define QuadSPI_SR_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK)
901 
902 #define QuadSPI_SR_IP_ACC_MASK                   (0x2U)
903 #define QuadSPI_SR_IP_ACC_SHIFT                  (1U)
904 #define QuadSPI_SR_IP_ACC_WIDTH                  (1U)
905 #define QuadSPI_SR_IP_ACC(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK)
906 
907 #define QuadSPI_SR_AHB_ACC_MASK                  (0x4U)
908 #define QuadSPI_SR_AHB_ACC_SHIFT                 (2U)
909 #define QuadSPI_SR_AHB_ACC_WIDTH                 (1U)
910 #define QuadSPI_SR_AHB_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK)
911 
912 #define QuadSPI_SR_AWRACC_MASK                   (0x10U)
913 #define QuadSPI_SR_AWRACC_SHIFT                  (4U)
914 #define QuadSPI_SR_AWRACC_WIDTH                  (1U)
915 #define QuadSPI_SR_AWRACC(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AWRACC_SHIFT)) & QuadSPI_SR_AWRACC_MASK)
916 
917 #define QuadSPI_SR_AHBTRN_MASK                   (0x40U)
918 #define QuadSPI_SR_AHBTRN_SHIFT                  (6U)
919 #define QuadSPI_SR_AHBTRN_WIDTH                  (1U)
920 #define QuadSPI_SR_AHBTRN(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK)
921 
922 #define QuadSPI_SR_AHB0NE_MASK                   (0x80U)
923 #define QuadSPI_SR_AHB0NE_SHIFT                  (7U)
924 #define QuadSPI_SR_AHB0NE_WIDTH                  (1U)
925 #define QuadSPI_SR_AHB0NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
926 
927 #define QuadSPI_SR_AHB1NE_MASK                   (0x100U)
928 #define QuadSPI_SR_AHB1NE_SHIFT                  (8U)
929 #define QuadSPI_SR_AHB1NE_WIDTH                  (1U)
930 #define QuadSPI_SR_AHB1NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK)
931 
932 #define QuadSPI_SR_AHB2NE_MASK                   (0x200U)
933 #define QuadSPI_SR_AHB2NE_SHIFT                  (9U)
934 #define QuadSPI_SR_AHB2NE_WIDTH                  (1U)
935 #define QuadSPI_SR_AHB2NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK)
936 
937 #define QuadSPI_SR_AHB3NE_MASK                   (0x400U)
938 #define QuadSPI_SR_AHB3NE_SHIFT                  (10U)
939 #define QuadSPI_SR_AHB3NE_WIDTH                  (1U)
940 #define QuadSPI_SR_AHB3NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK)
941 
942 #define QuadSPI_SR_AHB0FUL_MASK                  (0x800U)
943 #define QuadSPI_SR_AHB0FUL_SHIFT                 (11U)
944 #define QuadSPI_SR_AHB0FUL_WIDTH                 (1U)
945 #define QuadSPI_SR_AHB0FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
946 
947 #define QuadSPI_SR_AHB1FUL_MASK                  (0x1000U)
948 #define QuadSPI_SR_AHB1FUL_SHIFT                 (12U)
949 #define QuadSPI_SR_AHB1FUL_WIDTH                 (1U)
950 #define QuadSPI_SR_AHB1FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK)
951 
952 #define QuadSPI_SR_AHB2FUL_MASK                  (0x2000U)
953 #define QuadSPI_SR_AHB2FUL_SHIFT                 (13U)
954 #define QuadSPI_SR_AHB2FUL_WIDTH                 (1U)
955 #define QuadSPI_SR_AHB2FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK)
956 
957 #define QuadSPI_SR_AHB3FUL_MASK                  (0x4000U)
958 #define QuadSPI_SR_AHB3FUL_SHIFT                 (14U)
959 #define QuadSPI_SR_AHB3FUL_WIDTH                 (1U)
960 #define QuadSPI_SR_AHB3FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK)
961 
962 #define QuadSPI_SR_RXWE_MASK                     (0x10000U)
963 #define QuadSPI_SR_RXWE_SHIFT                    (16U)
964 #define QuadSPI_SR_RXWE_WIDTH                    (1U)
965 #define QuadSPI_SR_RXWE(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
966 
967 #define QuadSPI_SR_RXFULL_MASK                   (0x80000U)
968 #define QuadSPI_SR_RXFULL_SHIFT                  (19U)
969 #define QuadSPI_SR_RXFULL_WIDTH                  (1U)
970 #define QuadSPI_SR_RXFULL(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
971 
972 #define QuadSPI_SR_RXDMA_MASK                    (0x800000U)
973 #define QuadSPI_SR_RXDMA_SHIFT                   (23U)
974 #define QuadSPI_SR_RXDMA_WIDTH                   (1U)
975 #define QuadSPI_SR_RXDMA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK)
976 
977 #define QuadSPI_SR_TXEDA_MASK                    (0x1000000U)
978 #define QuadSPI_SR_TXEDA_SHIFT                   (24U)
979 #define QuadSPI_SR_TXEDA_WIDTH                   (1U)
980 #define QuadSPI_SR_TXEDA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK)
981 
982 #define QuadSPI_SR_TXFULL_MASK                   (0x8000000U)
983 #define QuadSPI_SR_TXFULL_SHIFT                  (27U)
984 #define QuadSPI_SR_TXFULL_WIDTH                  (1U)
985 #define QuadSPI_SR_TXFULL(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
986 /*! @} */
987 
988 /*! @name FR - Flag Register */
989 /*! @{ */
990 
991 #define QuadSPI_FR_TFF_MASK                      (0x1U)
992 #define QuadSPI_FR_TFF_SHIFT                     (0U)
993 #define QuadSPI_FR_TFF_WIDTH                     (1U)
994 #define QuadSPI_FR_TFF(x)                        (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK)
995 
996 #define QuadSPI_FR_IPIEF_MASK                    (0x40U)
997 #define QuadSPI_FR_IPIEF_SHIFT                   (6U)
998 #define QuadSPI_FR_IPIEF_WIDTH                   (1U)
999 #define QuadSPI_FR_IPIEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK)
1000 
1001 #define QuadSPI_FR_PPWF_MASK                     (0x100U)
1002 #define QuadSPI_FR_PPWF_SHIFT                    (8U)
1003 #define QuadSPI_FR_PPWF_WIDTH                    (1U)
1004 #define QuadSPI_FR_PPWF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_PPWF_SHIFT)) & QuadSPI_FR_PPWF_MASK)
1005 
1006 #define QuadSPI_FR_CRCBEF_MASK                   (0x200U)
1007 #define QuadSPI_FR_CRCBEF_SHIFT                  (9U)
1008 #define QuadSPI_FR_CRCBEF_WIDTH                  (1U)
1009 #define QuadSPI_FR_CRCBEF(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_CRCBEF_SHIFT)) & QuadSPI_FR_CRCBEF_MASK)
1010 
1011 #define QuadSPI_FR_CRCAEF_MASK                   (0x400U)
1012 #define QuadSPI_FR_CRCAEF_SHIFT                  (10U)
1013 #define QuadSPI_FR_CRCAEF_WIDTH                  (1U)
1014 #define QuadSPI_FR_CRCAEF(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_CRCAEF_SHIFT)) & QuadSPI_FR_CRCAEF_MASK)
1015 
1016 #define QuadSPI_FR_IUEF_MASK                     (0x800U)
1017 #define QuadSPI_FR_IUEF_SHIFT                    (11U)
1018 #define QuadSPI_FR_IUEF_WIDTH                    (1U)
1019 #define QuadSPI_FR_IUEF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK)
1020 
1021 #define QuadSPI_FR_ABOF_MASK                     (0x1000U)
1022 #define QuadSPI_FR_ABOF_SHIFT                    (12U)
1023 #define QuadSPI_FR_ABOF_WIDTH                    (1U)
1024 #define QuadSPI_FR_ABOF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK)
1025 
1026 #define QuadSPI_FR_AIBSEF_MASK                   (0x2000U)
1027 #define QuadSPI_FR_AIBSEF_SHIFT                  (13U)
1028 #define QuadSPI_FR_AIBSEF_WIDTH                  (1U)
1029 #define QuadSPI_FR_AIBSEF(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
1030 
1031 #define QuadSPI_FR_AITEF_MASK                    (0x4000U)
1032 #define QuadSPI_FR_AITEF_SHIFT                   (14U)
1033 #define QuadSPI_FR_AITEF_WIDTH                   (1U)
1034 #define QuadSPI_FR_AITEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK)
1035 
1036 #define QuadSPI_FR_AAEF_MASK                     (0x8000U)
1037 #define QuadSPI_FR_AAEF_SHIFT                    (15U)
1038 #define QuadSPI_FR_AAEF_WIDTH                    (1U)
1039 #define QuadSPI_FR_AAEF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AAEF_SHIFT)) & QuadSPI_FR_AAEF_MASK)
1040 
1041 #define QuadSPI_FR_RBDF_MASK                     (0x10000U)
1042 #define QuadSPI_FR_RBDF_SHIFT                    (16U)
1043 #define QuadSPI_FR_RBDF_WIDTH                    (1U)
1044 #define QuadSPI_FR_RBDF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK)
1045 
1046 #define QuadSPI_FR_RBOF_MASK                     (0x20000U)
1047 #define QuadSPI_FR_RBOF_SHIFT                    (17U)
1048 #define QuadSPI_FR_RBOF_WIDTH                    (1U)
1049 #define QuadSPI_FR_RBOF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK)
1050 
1051 #define QuadSPI_FR_ILLINE_MASK                   (0x800000U)
1052 #define QuadSPI_FR_ILLINE_SHIFT                  (23U)
1053 #define QuadSPI_FR_ILLINE_WIDTH                  (1U)
1054 #define QuadSPI_FR_ILLINE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
1055 
1056 #define QuadSPI_FR_DLLUNLCK_MASK                 (0x1000000U)
1057 #define QuadSPI_FR_DLLUNLCK_SHIFT                (24U)
1058 #define QuadSPI_FR_DLLUNLCK_WIDTH                (1U)
1059 #define QuadSPI_FR_DLLUNLCK(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLLUNLCK_SHIFT)) & QuadSPI_FR_DLLUNLCK_MASK)
1060 
1061 #define QuadSPI_FR_TBUF_MASK                     (0x4000000U)
1062 #define QuadSPI_FR_TBUF_SHIFT                    (26U)
1063 #define QuadSPI_FR_TBUF_WIDTH                    (1U)
1064 #define QuadSPI_FR_TBUF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK)
1065 
1066 #define QuadSPI_FR_TBFF_MASK                     (0x8000000U)
1067 #define QuadSPI_FR_TBFF_SHIFT                    (27U)
1068 #define QuadSPI_FR_TBFF_WIDTH                    (1U)
1069 #define QuadSPI_FR_TBFF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK)
1070 
1071 #define QuadSPI_FR_DLLABRT_MASK                  (0x10000000U)
1072 #define QuadSPI_FR_DLLABRT_SHIFT                 (28U)
1073 #define QuadSPI_FR_DLLABRT_WIDTH                 (1U)
1074 #define QuadSPI_FR_DLLABRT(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLLABRT_SHIFT)) & QuadSPI_FR_DLLABRT_MASK)
1075 
1076 #define QuadSPI_FR_DLPFF_MASK                    (0x80000000U)
1077 #define QuadSPI_FR_DLPFF_SHIFT                   (31U)
1078 #define QuadSPI_FR_DLPFF_WIDTH                   (1U)
1079 #define QuadSPI_FR_DLPFF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK)
1080 /*! @} */
1081 
1082 /*! @name RSER - Interrupt and DMA Request Select and Enable Register */
1083 /*! @{ */
1084 
1085 #define QuadSPI_RSER_TFIE_MASK                   (0x1U)
1086 #define QuadSPI_RSER_TFIE_SHIFT                  (0U)
1087 #define QuadSPI_RSER_TFIE_WIDTH                  (1U)
1088 #define QuadSPI_RSER_TFIE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK)
1089 
1090 #define QuadSPI_RSER_IPIEIE_MASK                 (0x40U)
1091 #define QuadSPI_RSER_IPIEIE_SHIFT                (6U)
1092 #define QuadSPI_RSER_IPIEIE_WIDTH                (1U)
1093 #define QuadSPI_RSER_IPIEIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK)
1094 
1095 #define QuadSPI_RSER_PPWIE_MASK                  (0x100U)
1096 #define QuadSPI_RSER_PPWIE_SHIFT                 (8U)
1097 #define QuadSPI_RSER_PPWIE_WIDTH                 (1U)
1098 #define QuadSPI_RSER_PPWIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_PPWIE_SHIFT)) & QuadSPI_RSER_PPWIE_MASK)
1099 
1100 #define QuadSPI_RSER_CRCBIE_MASK                 (0x200U)
1101 #define QuadSPI_RSER_CRCBIE_SHIFT                (9U)
1102 #define QuadSPI_RSER_CRCBIE_WIDTH                (1U)
1103 #define QuadSPI_RSER_CRCBIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_CRCBIE_SHIFT)) & QuadSPI_RSER_CRCBIE_MASK)
1104 
1105 #define QuadSPI_RSER_CRCAIE_MASK                 (0x400U)
1106 #define QuadSPI_RSER_CRCAIE_SHIFT                (10U)
1107 #define QuadSPI_RSER_CRCAIE_WIDTH                (1U)
1108 #define QuadSPI_RSER_CRCAIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_CRCAIE_SHIFT)) & QuadSPI_RSER_CRCAIE_MASK)
1109 
1110 #define QuadSPI_RSER_IUEIE_MASK                  (0x800U)
1111 #define QuadSPI_RSER_IUEIE_SHIFT                 (11U)
1112 #define QuadSPI_RSER_IUEIE_WIDTH                 (1U)
1113 #define QuadSPI_RSER_IUEIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK)
1114 
1115 #define QuadSPI_RSER_ABOIE_MASK                  (0x1000U)
1116 #define QuadSPI_RSER_ABOIE_SHIFT                 (12U)
1117 #define QuadSPI_RSER_ABOIE_WIDTH                 (1U)
1118 #define QuadSPI_RSER_ABOIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK)
1119 
1120 #define QuadSPI_RSER_AAIE_MASK                   (0x8000U)
1121 #define QuadSPI_RSER_AAIE_SHIFT                  (15U)
1122 #define QuadSPI_RSER_AAIE_WIDTH                  (1U)
1123 #define QuadSPI_RSER_AAIE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AAIE_SHIFT)) & QuadSPI_RSER_AAIE_MASK)
1124 
1125 #define QuadSPI_RSER_RBDIE_MASK                  (0x10000U)
1126 #define QuadSPI_RSER_RBDIE_SHIFT                 (16U)
1127 #define QuadSPI_RSER_RBDIE_WIDTH                 (1U)
1128 #define QuadSPI_RSER_RBDIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK)
1129 
1130 #define QuadSPI_RSER_RBOIE_MASK                  (0x20000U)
1131 #define QuadSPI_RSER_RBOIE_SHIFT                 (17U)
1132 #define QuadSPI_RSER_RBOIE_WIDTH                 (1U)
1133 #define QuadSPI_RSER_RBOIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK)
1134 
1135 #define QuadSPI_RSER_RBDDE_MASK                  (0x200000U)
1136 #define QuadSPI_RSER_RBDDE_SHIFT                 (21U)
1137 #define QuadSPI_RSER_RBDDE_WIDTH                 (1U)
1138 #define QuadSPI_RSER_RBDDE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK)
1139 
1140 #define QuadSPI_RSER_ILLINIE_MASK                (0x800000U)
1141 #define QuadSPI_RSER_ILLINIE_SHIFT               (23U)
1142 #define QuadSPI_RSER_ILLINIE_WIDTH               (1U)
1143 #define QuadSPI_RSER_ILLINIE(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK)
1144 
1145 #define QuadSPI_RSER_DLLULIE_MASK                (0x1000000U)
1146 #define QuadSPI_RSER_DLLULIE_SHIFT               (24U)
1147 #define QuadSPI_RSER_DLLULIE_WIDTH               (1U)
1148 #define QuadSPI_RSER_DLLULIE(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLLULIE_SHIFT)) & QuadSPI_RSER_DLLULIE_MASK)
1149 
1150 #define QuadSPI_RSER_TBFDE_MASK                  (0x2000000U)
1151 #define QuadSPI_RSER_TBFDE_SHIFT                 (25U)
1152 #define QuadSPI_RSER_TBFDE_WIDTH                 (1U)
1153 #define QuadSPI_RSER_TBFDE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK)
1154 
1155 #define QuadSPI_RSER_TBUIE_MASK                  (0x4000000U)
1156 #define QuadSPI_RSER_TBUIE_SHIFT                 (26U)
1157 #define QuadSPI_RSER_TBUIE_WIDTH                 (1U)
1158 #define QuadSPI_RSER_TBUIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK)
1159 
1160 #define QuadSPI_RSER_TBFIE_MASK                  (0x8000000U)
1161 #define QuadSPI_RSER_TBFIE_SHIFT                 (27U)
1162 #define QuadSPI_RSER_TBFIE_WIDTH                 (1U)
1163 #define QuadSPI_RSER_TBFIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK)
1164 
1165 #define QuadSPI_RSER_DLPFIE_MASK                 (0x80000000U)
1166 #define QuadSPI_RSER_DLPFIE_SHIFT                (31U)
1167 #define QuadSPI_RSER_DLPFIE_WIDTH                (1U)
1168 #define QuadSPI_RSER_DLPFIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK)
1169 /*! @} */
1170 
1171 /*! @name SPTRCLR - Sequence Pointer Clear Register */
1172 /*! @{ */
1173 
1174 #define QuadSPI_SPTRCLR_BFPTRC_MASK              (0x1U)
1175 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT             (0U)
1176 #define QuadSPI_SPTRCLR_BFPTRC_WIDTH             (1U)
1177 #define QuadSPI_SPTRCLR_BFPTRC(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK)
1178 
1179 #define QuadSPI_SPTRCLR_IPPTRC_MASK              (0x100U)
1180 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT             (8U)
1181 #define QuadSPI_SPTRCLR_IPPTRC_WIDTH             (1U)
1182 #define QuadSPI_SPTRCLR_IPPTRC(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK)
1183 
1184 #define QuadSPI_SPTRCLR_ABRT_CLR_MASK            (0x10000U)
1185 #define QuadSPI_SPTRCLR_ABRT_CLR_SHIFT           (16U)
1186 #define QuadSPI_SPTRCLR_ABRT_CLR_WIDTH           (1U)
1187 #define QuadSPI_SPTRCLR_ABRT_CLR(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_ABRT_CLR_SHIFT)) & QuadSPI_SPTRCLR_ABRT_CLR_MASK)
1188 
1189 #define QuadSPI_SPTRCLR_PREFETCH_DIS_MASK        (0x20000U)
1190 #define QuadSPI_SPTRCLR_PREFETCH_DIS_SHIFT       (17U)
1191 #define QuadSPI_SPTRCLR_PREFETCH_DIS_WIDTH       (1U)
1192 #define QuadSPI_SPTRCLR_PREFETCH_DIS(x)          (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_PREFETCH_DIS_SHIFT)) & QuadSPI_SPTRCLR_PREFETCH_DIS_MASK)
1193 
1194 #define QuadSPI_SPTRCLR_STREAM_EN_MASK           (0x40000U)
1195 #define QuadSPI_SPTRCLR_STREAM_EN_SHIFT          (18U)
1196 #define QuadSPI_SPTRCLR_STREAM_EN_WIDTH          (1U)
1197 #define QuadSPI_SPTRCLR_STREAM_EN(x)             (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_STREAM_EN_SHIFT)) & QuadSPI_SPTRCLR_STREAM_EN_MASK)
1198 
1199 #define QuadSPI_SPTRCLR_OTFAD_BNDRY_MASK         (0x3000000U)
1200 #define QuadSPI_SPTRCLR_OTFAD_BNDRY_SHIFT        (24U)
1201 #define QuadSPI_SPTRCLR_OTFAD_BNDRY_WIDTH        (2U)
1202 #define QuadSPI_SPTRCLR_OTFAD_BNDRY(x)           (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_OTFAD_BNDRY_SHIFT)) & QuadSPI_SPTRCLR_OTFAD_BNDRY_MASK)
1203 /*! @} */
1204 
1205 /*! @name SFA1AD - Serial Flash Memory A1 Top Address Register */
1206 /*! @{ */
1207 
1208 #define QuadSPI_SFA1AD_TPADA1_MASK               (0xFFFFFC00U)
1209 #define QuadSPI_SFA1AD_TPADA1_SHIFT              (10U)
1210 #define QuadSPI_SFA1AD_TPADA1_WIDTH              (22U)
1211 #define QuadSPI_SFA1AD_TPADA1(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK)
1212 /*! @} */
1213 
1214 /*! @name SFA2AD - Serial Flash Memory A2 Top Address Register */
1215 /*! @{ */
1216 
1217 #define QuadSPI_SFA2AD_TPADA2_MASK               (0xFFFFFC00U)
1218 #define QuadSPI_SFA2AD_TPADA2_SHIFT              (10U)
1219 #define QuadSPI_SFA2AD_TPADA2_WIDTH              (22U)
1220 #define QuadSPI_SFA2AD_TPADA2(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK)
1221 /*! @} */
1222 
1223 /*! @name SFB1AD - Serial Flash Memory B1 Top Address Register */
1224 /*! @{ */
1225 
1226 #define QuadSPI_SFB1AD_TPADB1_MASK               (0xFFFFFC00U)
1227 #define QuadSPI_SFB1AD_TPADB1_SHIFT              (10U)
1228 #define QuadSPI_SFB1AD_TPADB1_WIDTH              (22U)
1229 #define QuadSPI_SFB1AD_TPADB1(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK)
1230 /*! @} */
1231 
1232 /*! @name SFB2AD - Serial Flash Memory B2 Top Address Register */
1233 /*! @{ */
1234 
1235 #define QuadSPI_SFB2AD_TPADB2_MASK               (0xFFFFFC00U)
1236 #define QuadSPI_SFB2AD_TPADB2_SHIFT              (10U)
1237 #define QuadSPI_SFB2AD_TPADB2_WIDTH              (22U)
1238 #define QuadSPI_SFB2AD_TPADB2(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK)
1239 /*! @} */
1240 
1241 /*! @name DLPR - Data Learn Pattern Register */
1242 /*! @{ */
1243 
1244 #define QuadSPI_DLPR_DLPV_MASK                   (0xFFFFFFFFU)
1245 #define QuadSPI_DLPR_DLPV_SHIFT                  (0U)
1246 #define QuadSPI_DLPR_DLPV_WIDTH                  (32U)
1247 #define QuadSPI_DLPR_DLPV(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK)
1248 /*! @} */
1249 
1250 /*! @name FAILA_ADDR - Flash Memory A Failing Address Status Register */
1251 /*! @{ */
1252 
1253 #define QuadSPI_FAILA_ADDR_ADDR_MASK             (0xFFFFFFFFU)
1254 #define QuadSPI_FAILA_ADDR_ADDR_SHIFT            (0U)
1255 #define QuadSPI_FAILA_ADDR_ADDR_WIDTH            (32U)
1256 #define QuadSPI_FAILA_ADDR_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_FAILA_ADDR_ADDR_SHIFT)) & QuadSPI_FAILA_ADDR_ADDR_MASK)
1257 /*! @} */
1258 
1259 /*! @name FAILB_ADDR - flash Memory B Failing Address Status Register */
1260 /*! @{ */
1261 
1262 #define QuadSPI_FAILB_ADDR_ADDR_MASK             (0xFFFFFFFFU)
1263 #define QuadSPI_FAILB_ADDR_ADDR_SHIFT            (0U)
1264 #define QuadSPI_FAILB_ADDR_ADDR_WIDTH            (32U)
1265 #define QuadSPI_FAILB_ADDR_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_FAILB_ADDR_ADDR_SHIFT)) & QuadSPI_FAILB_ADDR_ADDR_MASK)
1266 /*! @} */
1267 
1268 /*! @name RBDR - RX Buffer Data Register */
1269 /*! @{ */
1270 
1271 #define QuadSPI_RBDR_RXDATA_MASK                 (0xFFFFFFFFU)
1272 #define QuadSPI_RBDR_RXDATA_SHIFT                (0U)
1273 #define QuadSPI_RBDR_RXDATA_WIDTH                (32U)
1274 #define QuadSPI_RBDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK)
1275 /*! @} */
1276 
1277 /*! @name LUTKEY - LUT Key Register */
1278 /*! @{ */
1279 
1280 #define QuadSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
1281 #define QuadSPI_LUTKEY_KEY_SHIFT                 (0U)
1282 #define QuadSPI_LUTKEY_KEY_WIDTH                 (32U)
1283 #define QuadSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK)
1284 /*! @} */
1285 
1286 /*! @name LCKCR - LUT Lock Configuration Register */
1287 /*! @{ */
1288 
1289 #define QuadSPI_LCKCR_LOCK_MASK                  (0x1U)
1290 #define QuadSPI_LCKCR_LOCK_SHIFT                 (0U)
1291 #define QuadSPI_LCKCR_LOCK_WIDTH                 (1U)
1292 #define QuadSPI_LCKCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
1293 
1294 #define QuadSPI_LCKCR_UNLOCK_MASK                (0x2U)
1295 #define QuadSPI_LCKCR_UNLOCK_SHIFT               (1U)
1296 #define QuadSPI_LCKCR_UNLOCK_WIDTH               (1U)
1297 #define QuadSPI_LCKCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK)
1298 /*! @} */
1299 
1300 /*! @name LUT - LUT Register */
1301 /*! @{ */
1302 
1303 #define QuadSPI_LUT_OPRND0_MASK                  (0xFFU)
1304 #define QuadSPI_LUT_OPRND0_SHIFT                 (0U)
1305 #define QuadSPI_LUT_OPRND0_WIDTH                 (8U)
1306 #define QuadSPI_LUT_OPRND0(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK)
1307 
1308 #define QuadSPI_LUT_PAD0_MASK                    (0x300U)
1309 #define QuadSPI_LUT_PAD0_SHIFT                   (8U)
1310 #define QuadSPI_LUT_PAD0_WIDTH                   (2U)
1311 #define QuadSPI_LUT_PAD0(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK)
1312 
1313 #define QuadSPI_LUT_INSTR0_MASK                  (0xFC00U)
1314 #define QuadSPI_LUT_INSTR0_SHIFT                 (10U)
1315 #define QuadSPI_LUT_INSTR0_WIDTH                 (6U)
1316 #define QuadSPI_LUT_INSTR0(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK)
1317 
1318 #define QuadSPI_LUT_OPRND1_MASK                  (0xFF0000U)
1319 #define QuadSPI_LUT_OPRND1_SHIFT                 (16U)
1320 #define QuadSPI_LUT_OPRND1_WIDTH                 (8U)
1321 #define QuadSPI_LUT_OPRND1(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK)
1322 
1323 #define QuadSPI_LUT_PAD1_MASK                    (0x3000000U)
1324 #define QuadSPI_LUT_PAD1_SHIFT                   (24U)
1325 #define QuadSPI_LUT_PAD1_WIDTH                   (2U)
1326 #define QuadSPI_LUT_PAD1(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK)
1327 
1328 #define QuadSPI_LUT_INSTR1_MASK                  (0xFC000000U)
1329 #define QuadSPI_LUT_INSTR1_SHIFT                 (26U)
1330 #define QuadSPI_LUT_INSTR1_WIDTH                 (6U)
1331 #define QuadSPI_LUT_INSTR1(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK)
1332 /*! @} */
1333 
1334 /*! @name WORD0 - Flash Region Start Address */
1335 /*! @{ */
1336 
1337 #define QuadSPI_WORD0_STARTADR_MASK              (0xFFFF0000U)
1338 #define QuadSPI_WORD0_STARTADR_SHIFT             (16U)
1339 #define QuadSPI_WORD0_STARTADR_WIDTH             (16U)
1340 #define QuadSPI_WORD0_STARTADR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD0_STARTADR_SHIFT)) & QuadSPI_WORD0_STARTADR_MASK)
1341 /*! @} */
1342 
1343 /*! @name WORD1 - Flash Region End Address */
1344 /*! @{ */
1345 
1346 #define QuadSPI_WORD1_ENDADR_MASK                (0xFFFF0000U)
1347 #define QuadSPI_WORD1_ENDADR_SHIFT               (16U)
1348 #define QuadSPI_WORD1_ENDADR_WIDTH               (16U)
1349 #define QuadSPI_WORD1_ENDADR(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD1_ENDADR_SHIFT)) & QuadSPI_WORD1_ENDADR_MASK)
1350 /*! @} */
1351 
1352 /*! @name WORD2 - Flash Region Privileges */
1353 /*! @{ */
1354 
1355 #define QuadSPI_WORD2_MD0ACP_MASK                (0x7U)
1356 #define QuadSPI_WORD2_MD0ACP_SHIFT               (0U)
1357 #define QuadSPI_WORD2_MD0ACP_WIDTH               (3U)
1358 #define QuadSPI_WORD2_MD0ACP(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD2_MD0ACP_SHIFT)) & QuadSPI_WORD2_MD0ACP_MASK)
1359 
1360 #define QuadSPI_WORD2_MD1ACP_MASK                (0x38U)
1361 #define QuadSPI_WORD2_MD1ACP_SHIFT               (3U)
1362 #define QuadSPI_WORD2_MD1ACP_WIDTH               (3U)
1363 #define QuadSPI_WORD2_MD1ACP(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD2_MD1ACP_SHIFT)) & QuadSPI_WORD2_MD1ACP_MASK)
1364 
1365 #define QuadSPI_WORD2_EALO_MASK                  (0x3F000000U)
1366 #define QuadSPI_WORD2_EALO_SHIFT                 (24U)
1367 #define QuadSPI_WORD2_EALO_WIDTH                 (6U)
1368 #define QuadSPI_WORD2_EALO(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD2_EALO_SHIFT)) & QuadSPI_WORD2_EALO_MASK)
1369 /*! @} */
1370 
1371 /*! @name WORD3 - Flash Region Lock Control */
1372 /*! @{ */
1373 
1374 #define QuadSPI_WORD3_EAL_MASK                   (0x3000000U)
1375 #define QuadSPI_WORD3_EAL_SHIFT                  (24U)
1376 #define QuadSPI_WORD3_EAL_WIDTH                  (2U)
1377 #define QuadSPI_WORD3_EAL(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD3_EAL_SHIFT)) & QuadSPI_WORD3_EAL_MASK)
1378 
1379 #define QuadSPI_WORD3_LOCK_MASK                  (0x60000000U)
1380 #define QuadSPI_WORD3_LOCK_SHIFT                 (29U)
1381 #define QuadSPI_WORD3_LOCK_WIDTH                 (2U)
1382 #define QuadSPI_WORD3_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD3_LOCK_SHIFT)) & QuadSPI_WORD3_LOCK_MASK)
1383 
1384 #define QuadSPI_WORD3_VLD_MASK                   (0x80000000U)
1385 #define QuadSPI_WORD3_VLD_SHIFT                  (31U)
1386 #define QuadSPI_WORD3_VLD_WIDTH                  (1U)
1387 #define QuadSPI_WORD3_VLD(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD3_VLD_SHIFT)) & QuadSPI_WORD3_VLD_MASK)
1388 /*! @} */
1389 
1390 /*! @name WORD4 - Flash Region Compare Address Status */
1391 /*! @{ */
1392 
1393 #define QuadSPI_WORD4_CMP_ADDR_MASK              (0xFFFFFFFFU)
1394 #define QuadSPI_WORD4_CMP_ADDR_SHIFT             (0U)
1395 #define QuadSPI_WORD4_CMP_ADDR_WIDTH             (32U)
1396 #define QuadSPI_WORD4_CMP_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD4_CMP_ADDR_SHIFT)) & QuadSPI_WORD4_CMP_ADDR_MASK)
1397 /*! @} */
1398 
1399 /*! @name WORD5 - Flash Region Compare Status Data */
1400 /*! @{ */
1401 
1402 #define QuadSPI_WORD5_CMP_MDID_MASK              (0x3FU)
1403 #define QuadSPI_WORD5_CMP_MDID_SHIFT             (0U)
1404 #define QuadSPI_WORD5_CMP_MDID_WIDTH             (6U)
1405 #define QuadSPI_WORD5_CMP_MDID(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD5_CMP_MDID_SHIFT)) & QuadSPI_WORD5_CMP_MDID_MASK)
1406 
1407 #define QuadSPI_WORD5_CMP_SA_MASK                (0x40U)
1408 #define QuadSPI_WORD5_CMP_SA_SHIFT               (6U)
1409 #define QuadSPI_WORD5_CMP_SA_WIDTH               (1U)
1410 #define QuadSPI_WORD5_CMP_SA(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD5_CMP_SA_SHIFT)) & QuadSPI_WORD5_CMP_SA_MASK)
1411 
1412 #define QuadSPI_WORD5_CMP_PA_MASK                (0x80U)
1413 #define QuadSPI_WORD5_CMP_PA_SHIFT               (7U)
1414 #define QuadSPI_WORD5_CMP_PA_WIDTH               (1U)
1415 #define QuadSPI_WORD5_CMP_PA(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD5_CMP_PA_SHIFT)) & QuadSPI_WORD5_CMP_PA_MASK)
1416 
1417 #define QuadSPI_WORD5_CMP_ERR_MASK               (0x20000000U)
1418 #define QuadSPI_WORD5_CMP_ERR_SHIFT              (29U)
1419 #define QuadSPI_WORD5_CMP_ERR_WIDTH              (1U)
1420 #define QuadSPI_WORD5_CMP_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD5_CMP_ERR_SHIFT)) & QuadSPI_WORD5_CMP_ERR_MASK)
1421 
1422 #define QuadSPI_WORD5_CMPVALID_MASK              (0x40000000U)
1423 #define QuadSPI_WORD5_CMPVALID_SHIFT             (30U)
1424 #define QuadSPI_WORD5_CMPVALID_WIDTH             (1U)
1425 #define QuadSPI_WORD5_CMPVALID(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_WORD5_CMPVALID_SHIFT)) & QuadSPI_WORD5_CMPVALID_MASK)
1426 /*! @} */
1427 
1428 /*! @name TGMDAD - Target Group n Master Domain Access Descriptor */
1429 /*! @{ */
1430 
1431 #define QuadSPI_TGMDAD_MIDMATCH_MASK             (0x3FU)
1432 #define QuadSPI_TGMDAD_MIDMATCH_SHIFT            (0U)
1433 #define QuadSPI_TGMDAD_MIDMATCH_WIDTH            (6U)
1434 #define QuadSPI_TGMDAD_MIDMATCH(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_MIDMATCH_SHIFT)) & QuadSPI_TGMDAD_MIDMATCH_MASK)
1435 
1436 #define QuadSPI_TGMDAD_MASK_MASK                 (0xFC0U)
1437 #define QuadSPI_TGMDAD_MASK_SHIFT                (6U)
1438 #define QuadSPI_TGMDAD_MASK_WIDTH                (6U)
1439 #define QuadSPI_TGMDAD_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_MASK_SHIFT)) & QuadSPI_TGMDAD_MASK_MASK)
1440 
1441 #define QuadSPI_TGMDAD_MASKTYPE_MASK             (0x1000U)
1442 #define QuadSPI_TGMDAD_MASKTYPE_SHIFT            (12U)
1443 #define QuadSPI_TGMDAD_MASKTYPE_WIDTH            (1U)
1444 #define QuadSPI_TGMDAD_MASKTYPE(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_MASKTYPE_SHIFT)) & QuadSPI_TGMDAD_MASKTYPE_MASK)
1445 
1446 #define QuadSPI_TGMDAD_SA_MASK                   (0xC000U)
1447 #define QuadSPI_TGMDAD_SA_SHIFT                  (14U)
1448 #define QuadSPI_TGMDAD_SA_WIDTH                  (2U)
1449 #define QuadSPI_TGMDAD_SA(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_SA_SHIFT)) & QuadSPI_TGMDAD_SA_MASK)
1450 
1451 #define QuadSPI_TGMDAD_LCK_MASK                  (0x20000000U)
1452 #define QuadSPI_TGMDAD_LCK_SHIFT                 (29U)
1453 #define QuadSPI_TGMDAD_LCK_WIDTH                 (1U)
1454 #define QuadSPI_TGMDAD_LCK(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_LCK_SHIFT)) & QuadSPI_TGMDAD_LCK_MASK)
1455 
1456 #define QuadSPI_TGMDAD_VLD_MASK                  (0x80000000U)
1457 #define QuadSPI_TGMDAD_VLD_SHIFT                 (31U)
1458 #define QuadSPI_TGMDAD_VLD_WIDTH                 (1U)
1459 #define QuadSPI_TGMDAD_VLD(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGMDAD_VLD_SHIFT)) & QuadSPI_TGMDAD_VLD_MASK)
1460 /*! @} */
1461 
1462 /*! @name TGSFAR - Target Group n SFAR Address */
1463 /*! @{ */
1464 
1465 #define QuadSPI_TGSFAR_SFARADDR_MASK             (0xFFFFFFFFU)
1466 #define QuadSPI_TGSFAR_SFARADDR_SHIFT            (0U)
1467 #define QuadSPI_TGSFAR_SFARADDR_WIDTH            (32U)
1468 #define QuadSPI_TGSFAR_SFARADDR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFAR_SFARADDR_SHIFT)) & QuadSPI_TGSFAR_SFARADDR_MASK)
1469 /*! @} */
1470 
1471 /*! @name TGSFARS - Target Group n SFAR Status */
1472 /*! @{ */
1473 
1474 #define QuadSPI_TGSFARS_TG_MID_MASK              (0x3FU)
1475 #define QuadSPI_TGSFARS_TG_MID_SHIFT             (0U)
1476 #define QuadSPI_TGSFARS_TG_MID_WIDTH             (6U)
1477 #define QuadSPI_TGSFARS_TG_MID(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_TG_MID_SHIFT)) & QuadSPI_TGSFARS_TG_MID_MASK)
1478 
1479 #define QuadSPI_TGSFARS_SA_MASK                  (0x400U)
1480 #define QuadSPI_TGSFARS_SA_SHIFT                 (10U)
1481 #define QuadSPI_TGSFARS_SA_WIDTH                 (1U)
1482 #define QuadSPI_TGSFARS_SA(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_SA_SHIFT)) & QuadSPI_TGSFARS_SA_MASK)
1483 
1484 #define QuadSPI_TGSFARS_PA_MASK                  (0x1000U)
1485 #define QuadSPI_TGSFARS_PA_SHIFT                 (12U)
1486 #define QuadSPI_TGSFARS_PA_WIDTH                 (1U)
1487 #define QuadSPI_TGSFARS_PA(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_PA_SHIFT)) & QuadSPI_TGSFARS_PA_MASK)
1488 
1489 #define QuadSPI_TGSFARS_CLR_MASK                 (0x20000000U)
1490 #define QuadSPI_TGSFARS_CLR_SHIFT                (29U)
1491 #define QuadSPI_TGSFARS_CLR_WIDTH                (1U)
1492 #define QuadSPI_TGSFARS_CLR(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_CLR_SHIFT)) & QuadSPI_TGSFARS_CLR_MASK)
1493 
1494 #define QuadSPI_TGSFARS_ERR_MASK                 (0x40000000U)
1495 #define QuadSPI_TGSFARS_ERR_SHIFT                (30U)
1496 #define QuadSPI_TGSFARS_ERR_WIDTH                (1U)
1497 #define QuadSPI_TGSFARS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_ERR_SHIFT)) & QuadSPI_TGSFARS_ERR_MASK)
1498 
1499 #define QuadSPI_TGSFARS_VLD_MASK                 (0x80000000U)
1500 #define QuadSPI_TGSFARS_VLD_SHIFT                (31U)
1501 #define QuadSPI_TGSFARS_VLD_WIDTH                (1U)
1502 #define QuadSPI_TGSFARS_VLD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGSFARS_VLD_SHIFT)) & QuadSPI_TGSFARS_VLD_MASK)
1503 /*! @} */
1504 
1505 /*! @name TGIPCRS - Target Group n IPCR Status */
1506 /*! @{ */
1507 
1508 #define QuadSPI_TGIPCRS_IDATSZ_MASK              (0xFFFFU)
1509 #define QuadSPI_TGIPCRS_IDATSZ_SHIFT             (0U)
1510 #define QuadSPI_TGIPCRS_IDATSZ_WIDTH             (16U)
1511 #define QuadSPI_TGIPCRS_IDATSZ(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_IDATSZ_SHIFT)) & QuadSPI_TGIPCRS_IDATSZ_MASK)
1512 
1513 #define QuadSPI_TGIPCRS_SEQID_MASK               (0xF0000U)
1514 #define QuadSPI_TGIPCRS_SEQID_SHIFT              (16U)
1515 #define QuadSPI_TGIPCRS_SEQID_WIDTH              (4U)
1516 #define QuadSPI_TGIPCRS_SEQID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_SEQID_SHIFT)) & QuadSPI_TGIPCRS_SEQID_MASK)
1517 
1518 #define QuadSPI_TGIPCRS_PAR_MASK                 (0x100000U)
1519 #define QuadSPI_TGIPCRS_PAR_SHIFT                (20U)
1520 #define QuadSPI_TGIPCRS_PAR_WIDTH                (1U)
1521 #define QuadSPI_TGIPCRS_PAR(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_PAR_SHIFT)) & QuadSPI_TGIPCRS_PAR_MASK)
1522 
1523 #define QuadSPI_TGIPCRS_CLR_MASK                 (0x10000000U)
1524 #define QuadSPI_TGIPCRS_CLR_SHIFT                (28U)
1525 #define QuadSPI_TGIPCRS_CLR_WIDTH                (1U)
1526 #define QuadSPI_TGIPCRS_CLR(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_CLR_SHIFT)) & QuadSPI_TGIPCRS_CLR_MASK)
1527 
1528 #define QuadSPI_TGIPCRS_ERR_MASK                 (0x60000000U)
1529 #define QuadSPI_TGIPCRS_ERR_SHIFT                (29U)
1530 #define QuadSPI_TGIPCRS_ERR_WIDTH                (2U)
1531 #define QuadSPI_TGIPCRS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_ERR_SHIFT)) & QuadSPI_TGIPCRS_ERR_MASK)
1532 
1533 #define QuadSPI_TGIPCRS_VLD_MASK                 (0x80000000U)
1534 #define QuadSPI_TGIPCRS_VLD_SHIFT                (31U)
1535 #define QuadSPI_TGIPCRS_VLD_WIDTH                (1U)
1536 #define QuadSPI_TGIPCRS_VLD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TGIPCRS_VLD_SHIFT)) & QuadSPI_TGIPCRS_VLD_MASK)
1537 /*! @} */
1538 
1539 /*! @name MGC - Master Global Configuration */
1540 /*! @{ */
1541 
1542 #define QuadSPI_MGC_GCLCKMID_MASK                (0x3FU)
1543 #define QuadSPI_MGC_GCLCKMID_SHIFT               (0U)
1544 #define QuadSPI_MGC_GCLCKMID_WIDTH               (6U)
1545 #define QuadSPI_MGC_GCLCKMID(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MGC_GCLCKMID_SHIFT)) & QuadSPI_MGC_GCLCKMID_MASK)
1546 
1547 #define QuadSPI_MGC_GCLCK_MASK                   (0xC00U)
1548 #define QuadSPI_MGC_GCLCK_SHIFT                  (10U)
1549 #define QuadSPI_MGC_GCLCK_WIDTH                  (2U)
1550 #define QuadSPI_MGC_GCLCK(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_MGC_GCLCK_SHIFT)) & QuadSPI_MGC_GCLCK_MASK)
1551 
1552 #define QuadSPI_MGC_GVLDFRAD_MASK                (0x8000000U)
1553 #define QuadSPI_MGC_GVLDFRAD_SHIFT               (27U)
1554 #define QuadSPI_MGC_GVLDFRAD_WIDTH               (1U)
1555 #define QuadSPI_MGC_GVLDFRAD(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MGC_GVLDFRAD_SHIFT)) & QuadSPI_MGC_GVLDFRAD_MASK)
1556 
1557 #define QuadSPI_MGC_GVLDMDAD_MASK                (0x20000000U)
1558 #define QuadSPI_MGC_GVLDMDAD_SHIFT               (29U)
1559 #define QuadSPI_MGC_GVLDMDAD_WIDTH               (1U)
1560 #define QuadSPI_MGC_GVLDMDAD(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MGC_GVLDMDAD_SHIFT)) & QuadSPI_MGC_GVLDMDAD_MASK)
1561 
1562 #define QuadSPI_MGC_GVLD_MASK                    (0x80000000U)
1563 #define QuadSPI_MGC_GVLD_SHIFT                   (31U)
1564 #define QuadSPI_MGC_GVLD_WIDTH                   (1U)
1565 #define QuadSPI_MGC_GVLD(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_MGC_GVLD_SHIFT)) & QuadSPI_MGC_GVLD_MASK)
1566 /*! @} */
1567 
1568 /*! @name MRC - Master Read Command */
1569 /*! @{ */
1570 
1571 #define QuadSPI_MRC_READ_CMD0_MASK               (0x3FU)
1572 #define QuadSPI_MRC_READ_CMD0_SHIFT              (0U)
1573 #define QuadSPI_MRC_READ_CMD0_WIDTH              (6U)
1574 #define QuadSPI_MRC_READ_CMD0(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_READ_CMD0_SHIFT)) & QuadSPI_MRC_READ_CMD0_MASK)
1575 
1576 #define QuadSPI_MRC_READ_CMD1_MASK               (0x3F00U)
1577 #define QuadSPI_MRC_READ_CMD1_SHIFT              (8U)
1578 #define QuadSPI_MRC_READ_CMD1_WIDTH              (6U)
1579 #define QuadSPI_MRC_READ_CMD1(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_READ_CMD1_SHIFT)) & QuadSPI_MRC_READ_CMD1_MASK)
1580 
1581 #define QuadSPI_MRC_READ_CMD2_MASK               (0x3F0000U)
1582 #define QuadSPI_MRC_READ_CMD2_SHIFT              (16U)
1583 #define QuadSPI_MRC_READ_CMD2_WIDTH              (6U)
1584 #define QuadSPI_MRC_READ_CMD2(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_READ_CMD2_SHIFT)) & QuadSPI_MRC_READ_CMD2_MASK)
1585 
1586 #define QuadSPI_MRC_VLDCMD02_MASK                (0x400000U)
1587 #define QuadSPI_MRC_VLDCMD02_SHIFT               (22U)
1588 #define QuadSPI_MRC_VLDCMD02_WIDTH               (1U)
1589 #define QuadSPI_MRC_VLDCMD02(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_VLDCMD02_SHIFT)) & QuadSPI_MRC_VLDCMD02_MASK)
1590 
1591 #define QuadSPI_MRC_READ_CMD3_MASK               (0x3F000000U)
1592 #define QuadSPI_MRC_READ_CMD3_SHIFT              (24U)
1593 #define QuadSPI_MRC_READ_CMD3_WIDTH              (6U)
1594 #define QuadSPI_MRC_READ_CMD3(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_READ_CMD3_SHIFT)) & QuadSPI_MRC_READ_CMD3_MASK)
1595 
1596 #define QuadSPI_MRC_VLDCMD03_MASK                (0x40000000U)
1597 #define QuadSPI_MRC_VLDCMD03_SHIFT               (30U)
1598 #define QuadSPI_MRC_VLDCMD03_WIDTH               (1U)
1599 #define QuadSPI_MRC_VLDCMD03(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MRC_VLDCMD03_SHIFT)) & QuadSPI_MRC_VLDCMD03_MASK)
1600 /*! @} */
1601 
1602 /*! @name MTO - Master Timeout */
1603 /*! @{ */
1604 
1605 #define QuadSPI_MTO_WRITE_TO_MASK                (0xFFFFFFFFU)
1606 #define QuadSPI_MTO_WRITE_TO_SHIFT               (0U)
1607 #define QuadSPI_MTO_WRITE_TO_WIDTH               (32U)
1608 #define QuadSPI_MTO_WRITE_TO(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_MTO_WRITE_TO_SHIFT)) & QuadSPI_MTO_WRITE_TO_MASK)
1609 /*! @} */
1610 
1611 /*! @name FLSEQREQ - FlashSeq Request */
1612 /*! @{ */
1613 
1614 #define QuadSPI_FLSEQREQ_REQ_MID_MASK            (0x3FU)
1615 #define QuadSPI_FLSEQREQ_REQ_MID_SHIFT           (0U)
1616 #define QuadSPI_FLSEQREQ_REQ_MID_WIDTH           (6U)
1617 #define QuadSPI_FLSEQREQ_REQ_MID(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_REQ_MID_SHIFT)) & QuadSPI_FLSEQREQ_REQ_MID_MASK)
1618 
1619 #define QuadSPI_FLSEQREQ_REQ_TG_MASK             (0x40U)
1620 #define QuadSPI_FLSEQREQ_REQ_TG_SHIFT            (6U)
1621 #define QuadSPI_FLSEQREQ_REQ_TG_WIDTH            (1U)
1622 #define QuadSPI_FLSEQREQ_REQ_TG(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_REQ_TG_SHIFT)) & QuadSPI_FLSEQREQ_REQ_TG_MASK)
1623 
1624 #define QuadSPI_FLSEQREQ_SA_MASK                 (0x100U)
1625 #define QuadSPI_FLSEQREQ_SA_SHIFT                (8U)
1626 #define QuadSPI_FLSEQREQ_SA_WIDTH                (1U)
1627 #define QuadSPI_FLSEQREQ_SA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_SA_SHIFT)) & QuadSPI_FLSEQREQ_SA_MASK)
1628 
1629 #define QuadSPI_FLSEQREQ_PA_MASK                 (0x200U)
1630 #define QuadSPI_FLSEQREQ_PA_SHIFT                (9U)
1631 #define QuadSPI_FLSEQREQ_PA_WIDTH                (1U)
1632 #define QuadSPI_FLSEQREQ_PA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_PA_SHIFT)) & QuadSPI_FLSEQREQ_PA_MASK)
1633 
1634 #define QuadSPI_FLSEQREQ_FRAD_MASK               (0x7000U)
1635 #define QuadSPI_FLSEQREQ_FRAD_SHIFT              (12U)
1636 #define QuadSPI_FLSEQREQ_FRAD_WIDTH              (3U)
1637 #define QuadSPI_FLSEQREQ_FRAD(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_FRAD_SHIFT)) & QuadSPI_FLSEQREQ_FRAD_MASK)
1638 
1639 #define QuadSPI_FLSEQREQ_SEQID_MASK              (0xF0000U)
1640 #define QuadSPI_FLSEQREQ_SEQID_SHIFT             (16U)
1641 #define QuadSPI_FLSEQREQ_SEQID_WIDTH             (4U)
1642 #define QuadSPI_FLSEQREQ_SEQID(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_SEQID_SHIFT)) & QuadSPI_FLSEQREQ_SEQID_MASK)
1643 
1644 #define QuadSPI_FLSEQREQ_CMD_MASK                (0x400000U)
1645 #define QuadSPI_FLSEQREQ_CMD_SHIFT               (22U)
1646 #define QuadSPI_FLSEQREQ_CMD_WIDTH               (1U)
1647 #define QuadSPI_FLSEQREQ_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_CMD_SHIFT)) & QuadSPI_FLSEQREQ_CMD_MASK)
1648 
1649 #define QuadSPI_FLSEQREQ_TIMEOUT_MASK            (0x8000000U)
1650 #define QuadSPI_FLSEQREQ_TIMEOUT_SHIFT           (27U)
1651 #define QuadSPI_FLSEQREQ_TIMEOUT_WIDTH           (1U)
1652 #define QuadSPI_FLSEQREQ_TIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_TIMEOUT_SHIFT)) & QuadSPI_FLSEQREQ_TIMEOUT_MASK)
1653 
1654 #define QuadSPI_FLSEQREQ_CLR_MASK                (0x20000000U)
1655 #define QuadSPI_FLSEQREQ_CLR_SHIFT               (29U)
1656 #define QuadSPI_FLSEQREQ_CLR_WIDTH               (1U)
1657 #define QuadSPI_FLSEQREQ_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_CLR_SHIFT)) & QuadSPI_FLSEQREQ_CLR_MASK)
1658 
1659 #define QuadSPI_FLSEQREQ_VLD_MASK                (0x80000000U)
1660 #define QuadSPI_FLSEQREQ_VLD_SHIFT               (31U)
1661 #define QuadSPI_FLSEQREQ_VLD_WIDTH               (1U)
1662 #define QuadSPI_FLSEQREQ_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSEQREQ_VLD_SHIFT)) & QuadSPI_FLSEQREQ_VLD_MASK)
1663 /*! @} */
1664 
1665 /*! @name FSMSTAT - FSM Status */
1666 /*! @{ */
1667 
1668 #define QuadSPI_FSMSTAT_STATE_MASK               (0x3U)
1669 #define QuadSPI_FSMSTAT_STATE_SHIFT              (0U)
1670 #define QuadSPI_FSMSTAT_STATE_WIDTH              (2U)
1671 #define QuadSPI_FSMSTAT_STATE(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_FSMSTAT_STATE_SHIFT)) & QuadSPI_FSMSTAT_STATE_MASK)
1672 
1673 #define QuadSPI_FSMSTAT_MID_MASK                 (0x3F00U)
1674 #define QuadSPI_FSMSTAT_MID_SHIFT                (8U)
1675 #define QuadSPI_FSMSTAT_MID_WIDTH                (6U)
1676 #define QuadSPI_FSMSTAT_MID(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FSMSTAT_MID_SHIFT)) & QuadSPI_FSMSTAT_MID_MASK)
1677 
1678 #define QuadSPI_FSMSTAT_CMD_MASK                 (0x10000U)
1679 #define QuadSPI_FSMSTAT_CMD_SHIFT                (16U)
1680 #define QuadSPI_FSMSTAT_CMD_WIDTH                (1U)
1681 #define QuadSPI_FSMSTAT_CMD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FSMSTAT_CMD_SHIFT)) & QuadSPI_FSMSTAT_CMD_MASK)
1682 
1683 #define QuadSPI_FSMSTAT_VLD_MASK                 (0x80000000U)
1684 #define QuadSPI_FSMSTAT_VLD_SHIFT                (31U)
1685 #define QuadSPI_FSMSTAT_VLD_WIDTH                (1U)
1686 #define QuadSPI_FSMSTAT_VLD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FSMSTAT_VLD_SHIFT)) & QuadSPI_FSMSTAT_VLD_MASK)
1687 /*! @} */
1688 
1689 /*! @name IPSERROR - IPS Error */
1690 /*! @{ */
1691 
1692 #define QuadSPI_IPSERROR_MID_MASK                (0x3FU)
1693 #define QuadSPI_IPSERROR_MID_SHIFT               (0U)
1694 #define QuadSPI_IPSERROR_MID_WIDTH               (6U)
1695 #define QuadSPI_IPSERROR_MID(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_MID_SHIFT)) & QuadSPI_IPSERROR_MID_MASK)
1696 
1697 #define QuadSPI_IPSERROR_TG0LCK_MASK             (0x100U)
1698 #define QuadSPI_IPSERROR_TG0LCK_SHIFT            (8U)
1699 #define QuadSPI_IPSERROR_TG0LCK_WIDTH            (1U)
1700 #define QuadSPI_IPSERROR_TG0LCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG0LCK_SHIFT)) & QuadSPI_IPSERROR_TG0LCK_MASK)
1701 
1702 #define QuadSPI_IPSERROR_TG1LCK_MASK             (0x200U)
1703 #define QuadSPI_IPSERROR_TG1LCK_SHIFT            (9U)
1704 #define QuadSPI_IPSERROR_TG1LCK_WIDTH            (1U)
1705 #define QuadSPI_IPSERROR_TG1LCK(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG1LCK_SHIFT)) & QuadSPI_IPSERROR_TG1LCK_MASK)
1706 
1707 #define QuadSPI_IPSERROR_TG0SEC_MASK             (0x400U)
1708 #define QuadSPI_IPSERROR_TG0SEC_SHIFT            (10U)
1709 #define QuadSPI_IPSERROR_TG0SEC_WIDTH            (1U)
1710 #define QuadSPI_IPSERROR_TG0SEC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG0SEC_SHIFT)) & QuadSPI_IPSERROR_TG0SEC_MASK)
1711 
1712 #define QuadSPI_IPSERROR_TG1SEC_MASK             (0x800U)
1713 #define QuadSPI_IPSERROR_TG1SEC_SHIFT            (11U)
1714 #define QuadSPI_IPSERROR_TG1SEC_WIDTH            (1U)
1715 #define QuadSPI_IPSERROR_TG1SEC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG1SEC_SHIFT)) & QuadSPI_IPSERROR_TG1SEC_MASK)
1716 
1717 #define QuadSPI_IPSERROR_TG0MID_MASK             (0x1000U)
1718 #define QuadSPI_IPSERROR_TG0MID_SHIFT            (12U)
1719 #define QuadSPI_IPSERROR_TG0MID_WIDTH            (1U)
1720 #define QuadSPI_IPSERROR_TG0MID(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG0MID_SHIFT)) & QuadSPI_IPSERROR_TG0MID_MASK)
1721 
1722 #define QuadSPI_IPSERROR_TG1MID_MASK             (0x2000U)
1723 #define QuadSPI_IPSERROR_TG1MID_SHIFT            (13U)
1724 #define QuadSPI_IPSERROR_TG1MID_WIDTH            (1U)
1725 #define QuadSPI_IPSERROR_TG1MID(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_TG1MID_SHIFT)) & QuadSPI_IPSERROR_TG1MID_MASK)
1726 
1727 #define QuadSPI_IPSERROR_MDADPROG_MASK           (0x4000U)
1728 #define QuadSPI_IPSERROR_MDADPROG_SHIFT          (14U)
1729 #define QuadSPI_IPSERROR_MDADPROG_WIDTH          (1U)
1730 #define QuadSPI_IPSERROR_MDADPROG(x)             (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_MDADPROG_SHIFT)) & QuadSPI_IPSERROR_MDADPROG_MASK)
1731 
1732 #define QuadSPI_IPSERROR_FRADPROG_MASK           (0x8000U)
1733 #define QuadSPI_IPSERROR_FRADPROG_SHIFT          (15U)
1734 #define QuadSPI_IPSERROR_FRADPROG_WIDTH          (1U)
1735 #define QuadSPI_IPSERROR_FRADPROG(x)             (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_FRADPROG_SHIFT)) & QuadSPI_IPSERROR_FRADPROG_MASK)
1736 
1737 #define QuadSPI_IPSERROR_CLR_MASK                (0x20000000U)
1738 #define QuadSPI_IPSERROR_CLR_SHIFT               (29U)
1739 #define QuadSPI_IPSERROR_CLR_WIDTH               (1U)
1740 #define QuadSPI_IPSERROR_CLR(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPSERROR_CLR_SHIFT)) & QuadSPI_IPSERROR_CLR_MASK)
1741 /*! @} */
1742 
1743 /*! @name ERRSTAT - Error Status */
1744 /*! @{ */
1745 
1746 #define QuadSPI_ERRSTAT_FRADMTCH_MASK            (0x1U)
1747 #define QuadSPI_ERRSTAT_FRADMTCH_SHIFT           (0U)
1748 #define QuadSPI_ERRSTAT_FRADMTCH_WIDTH           (1U)
1749 #define QuadSPI_ERRSTAT_FRADMTCH(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRADMTCH_SHIFT)) & QuadSPI_ERRSTAT_FRADMTCH_MASK)
1750 
1751 #define QuadSPI_ERRSTAT_FRAD0ACC_MASK            (0x2U)
1752 #define QuadSPI_ERRSTAT_FRAD0ACC_SHIFT           (1U)
1753 #define QuadSPI_ERRSTAT_FRAD0ACC_WIDTH           (1U)
1754 #define QuadSPI_ERRSTAT_FRAD0ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD0ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD0ACC_MASK)
1755 
1756 #define QuadSPI_ERRSTAT_FRAD1ACC_MASK            (0x4U)
1757 #define QuadSPI_ERRSTAT_FRAD1ACC_SHIFT           (2U)
1758 #define QuadSPI_ERRSTAT_FRAD1ACC_WIDTH           (1U)
1759 #define QuadSPI_ERRSTAT_FRAD1ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD1ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD1ACC_MASK)
1760 
1761 #define QuadSPI_ERRSTAT_FRAD2ACC_MASK            (0x8U)
1762 #define QuadSPI_ERRSTAT_FRAD2ACC_SHIFT           (3U)
1763 #define QuadSPI_ERRSTAT_FRAD2ACC_WIDTH           (1U)
1764 #define QuadSPI_ERRSTAT_FRAD2ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD2ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD2ACC_MASK)
1765 
1766 #define QuadSPI_ERRSTAT_FRAD3ACC_MASK            (0x10U)
1767 #define QuadSPI_ERRSTAT_FRAD3ACC_SHIFT           (4U)
1768 #define QuadSPI_ERRSTAT_FRAD3ACC_WIDTH           (1U)
1769 #define QuadSPI_ERRSTAT_FRAD3ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD3ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD3ACC_MASK)
1770 
1771 #define QuadSPI_ERRSTAT_FRAD4ACC_MASK            (0x20U)
1772 #define QuadSPI_ERRSTAT_FRAD4ACC_SHIFT           (5U)
1773 #define QuadSPI_ERRSTAT_FRAD4ACC_WIDTH           (1U)
1774 #define QuadSPI_ERRSTAT_FRAD4ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD4ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD4ACC_MASK)
1775 
1776 #define QuadSPI_ERRSTAT_FRAD5ACC_MASK            (0x40U)
1777 #define QuadSPI_ERRSTAT_FRAD5ACC_SHIFT           (6U)
1778 #define QuadSPI_ERRSTAT_FRAD5ACC_WIDTH           (1U)
1779 #define QuadSPI_ERRSTAT_FRAD5ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD5ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD5ACC_MASK)
1780 
1781 #define QuadSPI_ERRSTAT_FRAD6ACC_MASK            (0x80U)
1782 #define QuadSPI_ERRSTAT_FRAD6ACC_SHIFT           (7U)
1783 #define QuadSPI_ERRSTAT_FRAD6ACC_WIDTH           (1U)
1784 #define QuadSPI_ERRSTAT_FRAD6ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD6ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD6ACC_MASK)
1785 
1786 #define QuadSPI_ERRSTAT_FRAD7ACC_MASK            (0x100U)
1787 #define QuadSPI_ERRSTAT_FRAD7ACC_SHIFT           (8U)
1788 #define QuadSPI_ERRSTAT_FRAD7ACC_WIDTH           (1U)
1789 #define QuadSPI_ERRSTAT_FRAD7ACC(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_FRAD7ACC_SHIFT)) & QuadSPI_ERRSTAT_FRAD7ACC_MASK)
1790 
1791 #define QuadSPI_ERRSTAT_IPS_ERR_MASK             (0x200U)
1792 #define QuadSPI_ERRSTAT_IPS_ERR_SHIFT            (9U)
1793 #define QuadSPI_ERRSTAT_IPS_ERR_WIDTH            (1U)
1794 #define QuadSPI_ERRSTAT_IPS_ERR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_IPS_ERR_SHIFT)) & QuadSPI_ERRSTAT_IPS_ERR_MASK)
1795 
1796 #define QuadSPI_ERRSTAT_TG0SFAR_MASK             (0x400U)
1797 #define QuadSPI_ERRSTAT_TG0SFAR_SHIFT            (10U)
1798 #define QuadSPI_ERRSTAT_TG0SFAR_WIDTH            (1U)
1799 #define QuadSPI_ERRSTAT_TG0SFAR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_TG0SFAR_SHIFT)) & QuadSPI_ERRSTAT_TG0SFAR_MASK)
1800 
1801 #define QuadSPI_ERRSTAT_TG1SFAR_MASK             (0x800U)
1802 #define QuadSPI_ERRSTAT_TG1SFAR_SHIFT            (11U)
1803 #define QuadSPI_ERRSTAT_TG1SFAR_WIDTH            (1U)
1804 #define QuadSPI_ERRSTAT_TG1SFAR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_TG1SFAR_SHIFT)) & QuadSPI_ERRSTAT_TG1SFAR_MASK)
1805 
1806 #define QuadSPI_ERRSTAT_TG0IPCR_MASK             (0x1000U)
1807 #define QuadSPI_ERRSTAT_TG0IPCR_SHIFT            (12U)
1808 #define QuadSPI_ERRSTAT_TG0IPCR_WIDTH            (1U)
1809 #define QuadSPI_ERRSTAT_TG0IPCR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_TG0IPCR_SHIFT)) & QuadSPI_ERRSTAT_TG0IPCR_MASK)
1810 
1811 #define QuadSPI_ERRSTAT_TG1IPCR_MASK             (0x2000U)
1812 #define QuadSPI_ERRSTAT_TG1IPCR_SHIFT            (13U)
1813 #define QuadSPI_ERRSTAT_TG1IPCR_WIDTH            (1U)
1814 #define QuadSPI_ERRSTAT_TG1IPCR(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_TG1IPCR_SHIFT)) & QuadSPI_ERRSTAT_TG1IPCR_MASK)
1815 
1816 #define QuadSPI_ERRSTAT_TO_ERR_MASK              (0x4000U)
1817 #define QuadSPI_ERRSTAT_TO_ERR_SHIFT             (14U)
1818 #define QuadSPI_ERRSTAT_TO_ERR_WIDTH             (1U)
1819 #define QuadSPI_ERRSTAT_TO_ERR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_ERRSTAT_TO_ERR_SHIFT)) & QuadSPI_ERRSTAT_TO_ERR_MASK)
1820 /*! @} */
1821 
1822 /*! @name INT_EN - Interrupt Enable */
1823 /*! @{ */
1824 
1825 #define QuadSPI_INT_EN_FRADMTCH_MASK             (0x1U)
1826 #define QuadSPI_INT_EN_FRADMTCH_SHIFT            (0U)
1827 #define QuadSPI_INT_EN_FRADMTCH_WIDTH            (1U)
1828 #define QuadSPI_INT_EN_FRADMTCH(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRADMTCH_SHIFT)) & QuadSPI_INT_EN_FRADMTCH_MASK)
1829 
1830 #define QuadSPI_INT_EN_FRAD0ACC_MASK             (0x2U)
1831 #define QuadSPI_INT_EN_FRAD0ACC_SHIFT            (1U)
1832 #define QuadSPI_INT_EN_FRAD0ACC_WIDTH            (1U)
1833 #define QuadSPI_INT_EN_FRAD0ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD0ACC_SHIFT)) & QuadSPI_INT_EN_FRAD0ACC_MASK)
1834 
1835 #define QuadSPI_INT_EN_FRAD1ACC_MASK             (0x4U)
1836 #define QuadSPI_INT_EN_FRAD1ACC_SHIFT            (2U)
1837 #define QuadSPI_INT_EN_FRAD1ACC_WIDTH            (1U)
1838 #define QuadSPI_INT_EN_FRAD1ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD1ACC_SHIFT)) & QuadSPI_INT_EN_FRAD1ACC_MASK)
1839 
1840 #define QuadSPI_INT_EN_FRAD2ACC_MASK             (0x8U)
1841 #define QuadSPI_INT_EN_FRAD2ACC_SHIFT            (3U)
1842 #define QuadSPI_INT_EN_FRAD2ACC_WIDTH            (1U)
1843 #define QuadSPI_INT_EN_FRAD2ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD2ACC_SHIFT)) & QuadSPI_INT_EN_FRAD2ACC_MASK)
1844 
1845 #define QuadSPI_INT_EN_FRAD3ACC_MASK             (0x10U)
1846 #define QuadSPI_INT_EN_FRAD3ACC_SHIFT            (4U)
1847 #define QuadSPI_INT_EN_FRAD3ACC_WIDTH            (1U)
1848 #define QuadSPI_INT_EN_FRAD3ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD3ACC_SHIFT)) & QuadSPI_INT_EN_FRAD3ACC_MASK)
1849 
1850 #define QuadSPI_INT_EN_FRAD4ACC_MASK             (0x20U)
1851 #define QuadSPI_INT_EN_FRAD4ACC_SHIFT            (5U)
1852 #define QuadSPI_INT_EN_FRAD4ACC_WIDTH            (1U)
1853 #define QuadSPI_INT_EN_FRAD4ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD4ACC_SHIFT)) & QuadSPI_INT_EN_FRAD4ACC_MASK)
1854 
1855 #define QuadSPI_INT_EN_FRAD5ACC_MASK             (0x40U)
1856 #define QuadSPI_INT_EN_FRAD5ACC_SHIFT            (6U)
1857 #define QuadSPI_INT_EN_FRAD5ACC_WIDTH            (1U)
1858 #define QuadSPI_INT_EN_FRAD5ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD5ACC_SHIFT)) & QuadSPI_INT_EN_FRAD5ACC_MASK)
1859 
1860 #define QuadSPI_INT_EN_FRAD6ACC_MASK             (0x80U)
1861 #define QuadSPI_INT_EN_FRAD6ACC_SHIFT            (7U)
1862 #define QuadSPI_INT_EN_FRAD6ACC_WIDTH            (1U)
1863 #define QuadSPI_INT_EN_FRAD6ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD6ACC_SHIFT)) & QuadSPI_INT_EN_FRAD6ACC_MASK)
1864 
1865 #define QuadSPI_INT_EN_FRAD7ACC_MASK             (0x100U)
1866 #define QuadSPI_INT_EN_FRAD7ACC_SHIFT            (8U)
1867 #define QuadSPI_INT_EN_FRAD7ACC_WIDTH            (1U)
1868 #define QuadSPI_INT_EN_FRAD7ACC(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_FRAD7ACC_SHIFT)) & QuadSPI_INT_EN_FRAD7ACC_MASK)
1869 
1870 #define QuadSPI_INT_EN_IPS_ERR_MASK              (0x200U)
1871 #define QuadSPI_INT_EN_IPS_ERR_SHIFT             (9U)
1872 #define QuadSPI_INT_EN_IPS_ERR_WIDTH             (1U)
1873 #define QuadSPI_INT_EN_IPS_ERR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_IPS_ERR_SHIFT)) & QuadSPI_INT_EN_IPS_ERR_MASK)
1874 
1875 #define QuadSPI_INT_EN_TG0SFAR_MASK              (0x400U)
1876 #define QuadSPI_INT_EN_TG0SFAR_SHIFT             (10U)
1877 #define QuadSPI_INT_EN_TG0SFAR_WIDTH             (1U)
1878 #define QuadSPI_INT_EN_TG0SFAR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_TG0SFAR_SHIFT)) & QuadSPI_INT_EN_TG0SFAR_MASK)
1879 
1880 #define QuadSPI_INT_EN_TG1SFAR_MASK              (0x800U)
1881 #define QuadSPI_INT_EN_TG1SFAR_SHIFT             (11U)
1882 #define QuadSPI_INT_EN_TG1SFAR_WIDTH             (1U)
1883 #define QuadSPI_INT_EN_TG1SFAR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_TG1SFAR_SHIFT)) & QuadSPI_INT_EN_TG1SFAR_MASK)
1884 
1885 #define QuadSPI_INT_EN_TG0IPCR_MASK              (0x1000U)
1886 #define QuadSPI_INT_EN_TG0IPCR_SHIFT             (12U)
1887 #define QuadSPI_INT_EN_TG0IPCR_WIDTH             (1U)
1888 #define QuadSPI_INT_EN_TG0IPCR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_TG0IPCR_SHIFT)) & QuadSPI_INT_EN_TG0IPCR_MASK)
1889 
1890 #define QuadSPI_INT_EN_TG1IPCR_MASK              (0x2000U)
1891 #define QuadSPI_INT_EN_TG1IPCR_SHIFT             (13U)
1892 #define QuadSPI_INT_EN_TG1IPCR_WIDTH             (1U)
1893 #define QuadSPI_INT_EN_TG1IPCR(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_TG1IPCR_SHIFT)) & QuadSPI_INT_EN_TG1IPCR_MASK)
1894 
1895 #define QuadSPI_INT_EN_TO_ERR_MASK               (0x4000U)
1896 #define QuadSPI_INT_EN_TO_ERR_SHIFT              (14U)
1897 #define QuadSPI_INT_EN_TO_ERR_WIDTH              (1U)
1898 #define QuadSPI_INT_EN_TO_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_INT_EN_TO_ERR_SHIFT)) & QuadSPI_INT_EN_TO_ERR_MASK)
1899 /*! @} */
1900 
1901 /*!
1902  * @}
1903  */ /* end of group QuadSPI_Register_Masks */
1904 
1905 /*!
1906  * @}
1907  */ /* end of group QuadSPI_Peripheral_Access_Layer */
1908 
1909 #endif  /* #if !defined(S32Z2_QuadSPI_H_) */
1910