Home
last modified time | relevance | path

Searched defs:QuadSPI_MCR_DDR_EN_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h211 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18341 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19314 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17843 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17845 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25195 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25194 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46247 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44074 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46247 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46247 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46247 #define QuadSPI_MCR_DDR_EN_MASK (0x80U) macro
/hal_nxp-3.5.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30517 #define QuadSPI_MCR_DDR_EN_MASK 0x80u macro
/hal_nxp-3.5.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37717 #define QuadSPI_MCR_DDR_EN_MASK 0x80u macro