1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Qspi_Ip_Hyperflash.c
9 *
10 * @addtogroup FLS
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18
19 /*==================================================================================================
20 * INCLUDE FILES
21 ==================================================================================================*/
22 #include "OsIf.h"
23 #include "Qspi_Ip.h"
24 #include "Qspi_Ip_Common.h"
25 #include "Qspi_Ip_Controller.h"
26 #include "Qspi_Ip_HyperflashRegs.h"
27 #include "Qspi_Ip_Hyperflash.h"
28
29
30 /*==================================================================================================
31 * SOURCE FILE VERSION INFORMATION
32 ==================================================================================================*/
33 #define QSPI_IP_HYPERFLASH_VENDOR_ID_C 43
34 #define QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C 4
35 #define QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C 7
36 #define QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C 0
37 #define QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C 3
38 #define QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C 0
39 #define QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C 0
40
41 #if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
42
43 /*==================================================================================================
44 * FILE VERSION CHECKS
45 ==================================================================================================*/
46 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
47 /* Check if current file and OsIf.h header file are of the same Autosar version */
48 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
49 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
50 )
51 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and OsIf.h are different"
52 #endif
53 #endif
54
55 /* Check if current file and Qspi_Ip header file are of the same vendor */
56 #if (QSPI_IP_HYPERFLASH_VENDOR_ID_C != QSPI_IP_VENDOR_ID_H)
57 #error "Qspi_Ip_Hyperflash.c and Qspi_Ip.h have different vendor ids"
58 #endif
59 /* Check if current file and Qspi_Ip header file are of the same Autosar version */
60 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
61 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
62 (QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
63 )
64 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip.h are different"
65 #endif
66 /* Check if current file and Qspi_Ip header file are of the same Software version */
67 #if ((QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_H) || \
68 (QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_H) || \
69 (QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_H) \
70 )
71 #error "Software Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip.h are different"
72 #endif
73
74 /* Check if current file and Qspi_Ip_Common header file are of the same vendor */
75 #if (QSPI_IP_HYPERFLASH_VENDOR_ID_C != QSPI_IP_COMMON_VENDOR_ID_H)
76 #error "Qspi_Ip_Hyperflash.c and Qspi_Ip_Common.h have different vendor ids"
77 #endif
78 /* Check if current file and Qspi_Ip_Common header file are of the same Autosar version */
79 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
80 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
81 (QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
82 )
83 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Common.h are different"
84 #endif
85 /* Check if current file and Qspi_Ip_Common header file are of the same Software version */
86 #if ((QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
87 (QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
88 (QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
89 )
90 #error "Software Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Common.h are different"
91 #endif
92
93 /* Check if current file and Qspi_Ip_Controller header file are of the same vendor */
94 #if (QSPI_IP_HYPERFLASH_VENDOR_ID_C != QSPI_IP_CONTROLLER_VENDOR_ID_H)
95 #error "Qspi_Ip_Hyperflash.c and Qspi_Ip_Controller.h have different vendor ids"
96 #endif
97 /* Check if current file and Qspi_Ip_Controller header file are of the same Autosar version */
98 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H) || \
99 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H) || \
100 (QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H) \
101 )
102 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Controller.h are different"
103 #endif
104 /* Check if current file and Qspi_Ip_Controller header file are of the same Software version */
105 #if ((QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H) || \
106 (QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H) || \
107 (QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C != QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H) \
108 )
109 #error "Software Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Controller.h are different"
110 #endif
111
112 /* Check if current file and Qspi_Ip_HyperflashRegs header file are of the same vendor */
113 #if (QSPI_IP_HYPERFLASH_VENDOR_ID_C != QSPI_IP_HYPERFLASHREGS_VENDOR_ID_H)
114 #error "Qspi_Ip_Hyperflash.c and Qspi_Ip_HyperflashRegs.h have different vendor ids"
115 #endif
116 /* Check if current file and Qspi_Ip_HyperflashRegs header file are of the same Autosar version */
117 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != QSPI_IP_HYPERFLASHREGS_AR_RELEASE_MAJOR_VERSION_H) || \
118 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != QSPI_IP_HYPERFLASHREGS_AR_RELEASE_MINOR_VERSION_H) || \
119 (QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_HYPERFLASHREGS_AR_RELEASE_REVISION_VERSION_H) \
120 )
121 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_HyperflashRegs.h are different"
122 #endif
123 /* Check if current file and Qspi_Ip_HyperflashRegs header file are of the same Software version */
124 #if ((QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C != QSPI_IP_HYPERFLASHREGS_SW_MAJOR_VERSION_H) || \
125 (QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C != QSPI_IP_HYPERFLASHREGS_SW_MINOR_VERSION_H) || \
126 (QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C != QSPI_IP_HYPERFLASHREGS_SW_PATCH_VERSION_H) \
127 )
128 #error "Software Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_HyperflashRegs.h are different"
129 #endif
130
131 /* Check if current file and Qspi_Ip_Hyperflash header file are of the same vendor */
132 #if (QSPI_IP_HYPERFLASH_VENDOR_ID_C != QSPI_IP_HYPERFLASH_VENDOR_ID_H)
133 #error "Qspi_Ip_Hyperflash.c and Qspi_Ip_Hyperflash.h have different vendor ids"
134 #endif
135 /* Check if current file and Qspi_Ip_Hyperflash header file are of the same Autosar version */
136 #if ((QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_C != QSPI_IP_HYPERFLASH_AR_RELEASE_MAJOR_VERSION_H) || \
137 (QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_C != QSPI_IP_HYPERFLASH_AR_RELEASE_MINOR_VERSION_H) || \
138 (QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_HYPERFLASH_AR_RELEASE_REVISION_VERSION_H) \
139 )
140 #error "AutoSar Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Hyperflash.h are different"
141 #endif
142 /* Check if current file and Qspi_Ip_Hyperflash header file are of the same Software version */
143 #if ((QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_C != QSPI_IP_HYPERFLASH_SW_MAJOR_VERSION_H) || \
144 (QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_C != QSPI_IP_HYPERFLASH_SW_MINOR_VERSION_H) || \
145 (QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_C != QSPI_IP_HYPERFLASH_SW_PATCH_VERSION_H) \
146 )
147 #error "Software Version Numbers of Qspi_Ip_Hyperflash.c and Qspi_Ip_Hyperflash.h are different"
148 #endif
149
150 /*******************************************************************************
151 * Variables
152 ******************************************************************************/
153
154 /* HyperFlash commands */
155 typedef enum
156 {
157 QSPI_IP_HF_READ = 0xA0, /* Read command with continuous burst type */
158 QSPI_IP_HF_WRITE = 0x00, /* Write command with continuous burst type */
159 QSPI_IP_HF_RDSR = 0x70, /* Status register read */
160 QSPI_IP_HF_SRC = 0x71, /* Status register clear */
161 QSPI_IP_HF_EDPD = 0xB9, /* Enter Deep Power-Down */
162 QSPI_IP_HF_PPORTR = 0x34, /* Program Power-On Reset Timer Register */
163 QSPI_IP_HF_RPORTR = 0x3C, /* Read Power-On Reset Timer Register */
164 QSPI_IP_HF_LDICR = 0x36, /* Load Interrupt Configuration Register */
165 QSPI_IP_HF_RDICR = 0xC4, /* Read Interrupt Configuration Register */
166 QSPI_IP_HF_LDISR = 0x37, /* Load Interrupt Status Register */
167 QSPI_IP_HF_RDISR = 0xC5, /* Read Interrupt Status Register */
168 QSPI_IP_HF_LDVCR = 0x38, /* Load Volatile Configuration Register */
169 QSPI_IP_HF_RDVCR = 0xC7, /* Read Volatile Configuration Register */
170 QSPI_IP_HF_PNVCR = 0x39, /* Program Non-Volatile Configuration Register */
171 QSPI_IP_HF_ENVCR = 0xC8, /* Erase Non-Volatile Configuration Register */
172 QSPI_IP_HF_RDNVCR = 0xC6, /* Read Non-Volatile Configuration Register */
173 QSPI_IP_HF_WP = 0xA0, /* Word Program */
174 QSPI_IP_HF_WB = 0x25, /* Write to Buffer */
175 QSPI_IP_HF_PBF = 0x29, /* Program Buffer to Flash */
176 QSPI_IP_HF_WBAR = 0xF0, /* Write to Buffer Abort Reset */
177 QSPI_IP_HF_CE = 0x10, /* Chip erase */
178 QSPI_IP_HF_SE = 0x30, /* Sector Erase */
179 QSPI_IP_HF_BC = 0x33, /* Blank check */
180 QSPI_IP_HF_EES = 0xD0, /* Evaluate Erase Status */
181 QSPI_IP_HF_ES = 0xB0, /* Erase Suspend */
182 QSPI_IP_HF_ER = 0x30, /* Erase Resume */
183 QSPI_IP_HF_PS = 0x51, /* Program Suspend */
184 QSPI_IP_HF_PR = 0x50, /* Program Resume */
185 QSPI_IP_HF_RESET = 0xF0, /* Software reset */
186 QSPI_IP_HF_CFIE = 0x98, /* CIF enter */
187 } Qspi_Ip_HyperFlashCommandsType;
188
189
190 #define FLS_START_SEC_VAR_INIT_UNSPECIFIED
191 #include "Fls_MemMap.h"
192
193
194 /* Hyperflash virtual LUT */
195 Qspi_Ip_InstrOpType QSPI_IP_HF_LUT_NAME[QSPI_IP_HF_LUT_SIZE] =
196 {
197 /* 0: QSPI_IP_HF_LUT_COMMON_555_AA: pre-read with operand AA */
198 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
199 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
200 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
201 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
202 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0xAA),
203 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
204 /* 6: QSPI_IP_HF_LUT_COMMON_2AA_55: pre-read with operand 55 */
205 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
206 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
207 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
208 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
209 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x55),
210 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
211 /* 12: QSPI_IP_HF_LUT_READ: Read command */
212 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_READ),
213 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
214 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)16U),
215 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_DUMMY | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x4), /* dummy cycles to be patched in before use*/
216 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_READ_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x4),
217 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
218 /* 18: QSPI_IP_HF_LUT_WRITE: write command */
219 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
220 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
221 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)16U),
222 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_WRITE_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x2),
223 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
224 /* 23: QSPI_IP_HF_LUT_RDSR: Read status register */
225 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
226 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
227 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
228 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
229 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_RDSR),
230 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
231 /* 29: QSPI_IP_HF_LUT_RDSR_SEQ2 */
232 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_READ),
233 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
234 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)16U),
235 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_DUMMY | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x4), /* dummy cycles to be patched in before use*/
236 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_READ_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x4),
237 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
238 /* 35: QSPI_IP_HF_LUT_WP: Word Program */
239 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
240 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
241 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
242 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
243 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WP),
244 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
245 /* 41: QSPI_IP_HF_LUT_WP_SEQ1: Last sequence word program */
246 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
247 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x18),
248 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
249 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_WRITE_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x2),
250 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
251 /* 46: QSPI_IP_HF_LUT_CMD_80: pre-read with operand 0x80 */
252 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
253 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
254 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
255 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
256 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x80),
257 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
258 /* 52: QSPI_IP_HF_LUT_CMD_AA: pre-command with operand 0xAA */
259 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
260 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
261 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
262 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
263 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0xAA),
264 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
265 /* 58: QSPI_IP_HF_LUT_CMD_55: pre-command with operand 0x55 */
266 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
267 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
268 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
269 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
270 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x55),
271 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
272 /* 64: QSPI_IP_HF_LUT_SE: sector erase */
273 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
274 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
275 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
276 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
277 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_SE),
278 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
279 /* 70: QSPI_IP_HF_LUT_CE: chip erase */
280 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
281 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
282 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
283 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
284 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_CE),
285 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
286 /* 76: QSPI_IP_HF_LUT_RST: reset */
287 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
288 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
289 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
290 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
291 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_RESET),
292 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
293 /* 82: QSPI_IP_HF_LUT_SRC: Clear Status Register Command */
294 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
295 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
296 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
297 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
298 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_SRC),
299 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
300 /* 88: QSPI_IP_HF_LUT_BC: blank check command */
301 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
302 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
303 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
304 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
305 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_BC),
306 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
307 /* 94: QSPI_IP_HF_LUT_CMD_25: pre-read with operand 0x25 */
308 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
309 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
310 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
311 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
312 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8) QSPI_IP_HF_WB),
313 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
314 /* 100: QSPI_IP_HF_LUT_WC: sector address and word count */
315 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
316 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
317 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
318 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
319 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)(1U - 1U)), /* wordCount to be patched in before use */
320 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
321 /* 106: QSPI_IP_HF_LUT_WB: Write to buffer */
322 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
323 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x18),
324 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
325 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_WRITE_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x2),
326 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
327 /* 111: QSPI_IP_HF_LUT_PBF: Write to buffer */
328 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
329 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
330 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
331 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
332 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_PBF),
333 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
334 /* 117: QSPI_IP_HF_LUT_PS: Program suspend */
335 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
336 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
337 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
338 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
339 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_PS),
340 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
341 /* 123: QSPI_IP_HF_LUT_PR: Program resume */
342 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
343 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
344 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
345 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
346 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_PR),
347 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
348 /* 129: QSPI_IP_HF_LUT_ES: Erase suspend */
349 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
350 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
351 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
352 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
353 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_ES),
354 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
355 /* 135: QSPI_IP_HF_LUT_ER: Erase resume */
356 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
357 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
358 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
359 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
360 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_ER),
361 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
362 /* 141:QSPI_IP_HF_LUT_RDNVCR: Read Non-Volatile Configuration Register */
363 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
364 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
365 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
366 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
367 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8) QSPI_IP_HF_RDNVCR),
368 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
369 /* 147: QSPI_IP_HF_LUT_ENVCR: Erase Non-Volatile Configuration Register LUT */
370 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
371 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
372 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
373 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
374 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_ENVCR),
375 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
376 /* 153: QSPI_IP_HF_LUT_PNVCR: Program Non-Volatile Configuration Register LUT */
377 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
378 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
379 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
380 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
381 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_PNVCR),
382 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
383 /* 159: QSPI_IP_HF_LUT_LDVCR: Load Volatile Configuration Register LUT */
384 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_WRITE),
385 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)24U),
386 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x10),
387 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)0x00),
388 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)(uint8)QSPI_IP_HF_LDVCR),
389 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP),
390 /* 165: QSPI_IP_HF_LUT_CMD_98: pre-command with operand 0x98 (Enter CFI) */
391 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_WRITE),
392 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_ADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)24U),
393 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CADDR_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x10),
394 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)0x00),
395 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR | (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 | (Qspi_Ip_InstrOpType)QSPI_IP_HF_CFIE),
396 (Qspi_Ip_InstrOpType)(QSPI_IP_LUT_INSTR_STOP)
397 /* Total LUT size: 171 */
398 };
399
400 #define FLS_STOP_SEC_VAR_INIT_UNSPECIFIED
401 #include "Fls_MemMap.h"
402
403
404 /*******************************************************************************
405 * Functions
406 ******************************************************************************/
407
408 #define FLS_START_SEC_CODE
409 #include "Fls_MemMap.h"
410
411
412 /*FUNCTION**********************************************************************
413 *
414 * Function Name : Qspi_Ip_HyperflashUnlockCycles12
415 * Description : Sends the unlock cycles 1 and 2 before erase and write commands
416 *
417 *END**************************************************************************/
Qspi_Ip_HyperflashSendUnlockCycles12(uint32 instance)418 static Qspi_Ip_StatusType Qspi_Ip_HyperflashSendUnlockCycles12(uint32 instance)
419 {
420 Qspi_Ip_StatusType status;
421
422 /* Send unlock cycle 1 */
423 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_COMMON_555_AA, 0xAAA);
424 if (STATUS_QSPI_IP_SUCCESS == status)
425 {
426 /* Send unlock cycle 2 */
427 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_COMMON_2AA_55, 0x554);
428 }
429
430 return status;
431 }
432
433
434 /*FUNCTION**********************************************************************
435 *
436 * Function Name : Qspi_Ip_HyperflashPatchReadCommand
437 * Description : Patch a read command with the configured dummy cycles count
438 *
439 *END**************************************************************************/
Qspi_Ip_HyperflashPatchReadCommand(uint32 instance,uint16 lut)440 void Qspi_Ip_HyperflashPatchReadCommand(uint32 instance,
441 uint16 lut
442 )
443 {
444 const Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
445 uint8 dummyCycles;
446
447 /* Get dummy cycles */
448 dummyCycles = (uint8)state->configuration->hfConfig->readLatency + 4U;
449 /* Patch command - set dummy cycles */
450 Qspi_Ip_HyperflashLutTable[lut + 3U] = (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_DUMMY |
451 (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 |
452 (Qspi_Ip_InstrOpType)dummyCycles);
453 }
454
455
456 /*FUNCTION**********************************************************************
457 *
458 * Function Name : Qspi_Ip_HyperflashPatchRunReadCommand
459 * Description : Runs a read command after fixing the dummy cycles count
460 *
461 *END**************************************************************************/
Qspi_Ip_HyperflashPatchRunReadCommand(uint32 instance,uint16 lut,uint32 addr,uint8 * data,uint32 size)462 static Qspi_Ip_StatusType Qspi_Ip_HyperflashPatchRunReadCommand(uint32 instance,
463 uint16 lut,
464 uint32 addr,
465 uint8 * data,
466 uint32 size
467 )
468 {
469 /* Patch command - set dummy cycles */
470 Qspi_Ip_HyperflashPatchReadCommand(instance, lut);
471
472 /* Launch read command */
473 return Qspi_Ip_RunReadCommand(instance, lut, addr, data, NULL_PTR, size);
474 }
475
476
477 /*FUNCTION**********************************************************************
478 *
479 * Function Name : Qspi_Ip_HyperflashInitConfigRegister
480 * Description : Initializes configuration register
481 *
482 *END**************************************************************************/
Qspi_Ip_HyperflashGetConfigurationValue(const Qspi_Ip_HyperFlashConfigType * config)483 static uint16 Qspi_Ip_HyperflashGetConfigurationValue(const Qspi_Ip_HyperFlashConfigType *config)
484 {
485 uint16 regVal;
486
487 const uint8 RWDSLowOnDualError = (config->RWDSLowOnDualError) ? 1U : 0U;
488 const uint8 secureRegionUnlocked = (config->secureRegionUnlocked)? 1U : 0U;
489
490 regVal = (uint16)((uint16)QSPI_IP_HF_xVCR_BL((uint8)0x3U) |
491 (uint16)QSPI_IP_HF_xVCR_RWDS(RWDSLowOnDualError) |
492 (uint16)QSPI_IP_HF_xVCR_RL((uint8)config->readLatency) |
493 (uint16)QSPI_IP_HF_xVCR_PSM((uint8)config->paramSectorMap) |
494 (uint16)QSPI_IP_HF_xVCR_SSR(secureRegionUnlocked) |
495 (uint16)QSPI_IP_HF_xVCR_FRZ(1U) |
496 (uint16)QSPI_IP_HF_xVCR_DS((uint8)config->outputDriverStrength) |
497 ((uint16)QSPI_IP_HF_xVCR_RESERVED_BIT_3) |
498 ((uint16)QSPI_IP_HF_xVCR_RESERVED_BIT_16));
499
500 return regVal;
501 }
502
503 /*FUNCTION**********************************************************************
504 *
505 * Function Name : Qspi_Ip_HyperflashGetStatusRegister
506 * Description : Reads status register of the flash device.
507 *
508 *END**************************************************************************/
Qspi_Ip_HyperflashGetStatusRegister(uint32 instance,uint16 * readValue)509 static Qspi_Ip_StatusType Qspi_Ip_HyperflashGetStatusRegister(uint32 instance,
510 uint16 * readValue
511 )
512 {
513 Qspi_Ip_StatusType status;
514
515 /* Trigger pre-read command */
516 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_RDSR, 0xAAA);
517 if (STATUS_QSPI_IP_SUCCESS == status)
518 {
519 status = Qspi_Ip_HyperflashPatchRunReadCommand(instance, QSPI_IP_HF_LUT_RDSR_SEQ2, 0U, (uint8 *)readValue, 2U);
520 }
521
522 return status;
523 }
524
525 /*FUNCTION**********************************************************************
526 *
527 * Function Name : Qspi_Ip_HyperflashWaitDeviceReady
528 * Description : Waits device to be ready
529 *
530 *END**************************************************************************/
Qspi_Ip_HyperflashWaitDeviceReady(uint32 instance)531 static Qspi_Ip_StatusType Qspi_Ip_HyperflashWaitDeviceReady(uint32 instance)
532 {
533 uint16 readValue = 0U; /* Initilize with busy state */
534 Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
535 uint32 u32ElapsedTicks = 0U;
536 uint32 u32TimeoutTicks;
537 uint32 u32CurrentTicks;
538
539 /* Prepare timeout counter */
540 u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_FLS_INIT_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
541 u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
542
543 do
544 {
545 status = Qspi_Ip_HyperflashGetStatusRegister(instance, &readValue);
546 u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
547
548 if ((status == STATUS_QSPI_IP_ERROR) || ((readValue & QSPI_IP_HF_SR_DRB_MASK) != 0U))
549 {
550 /* status == STATUS_QSPI_IP_ERROR or hardware is ready */
551 break;
552 }
553 }
554 while (u32ElapsedTicks < u32TimeoutTicks);
555
556 if (((readValue & QSPI_IP_HF_SR_DRB_MASK) == 0U) && (status == STATUS_QSPI_IP_SUCCESS))
557 {
558 status = STATUS_QSPI_IP_BUSY;
559 }
560
561 return status;
562 }
563
564 /*FUNCTION**********************************************************************
565 *
566 * Function Name : Qspi_Ip_HyperflashStatusRegisterClear
567 * Description : Clears the Status Register. This function clears the error status of an
568 * embedded operation. It is necessary to clear the error status in order to
569 * return to normal operation, ready for a new read or command write.
570 *
571 *END**************************************************************************/
Qspi_Ip_HyperflashStatusRegisterClear(uint32 instance)572 static Qspi_Ip_StatusType Qspi_Ip_HyperflashStatusRegisterClear(uint32 instance)
573 {
574 Qspi_Ip_StatusType status;
575
576 /* Send Clear Status Register command */
577 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_SRC, 0xAAA);
578
579 return status;
580 }
581
582 /*FUNCTION**********************************************************************
583 *
584 * Function Name : Qspi_Ip_HyperflashStatusRegisterDecode
585 * Description : Decodes the device status according to the last command executed
586 *
587 *END**************************************************************************/
Qspi_Ip_HyperflashStatusRegisterDecode(uint16 SRValue,Qspi_Ip_LastCommandType lastCommand)588 static Qspi_Ip_StatusType Qspi_Ip_HyperflashStatusRegisterDecode(uint16 SRValue,
589 Qspi_Ip_LastCommandType lastCommand
590 )
591 {
592 Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
593 uint16 checkValue = 0U;
594
595 switch (lastCommand)
596 {
597 case QSPI_IP_LAST_COMMAND_ERASE:
598 /* If ESB is set, last erase operation failed. Used also for blank check command */
599 checkValue = SRValue & QSPI_IP_HF_SR_ESB_MASK;
600 break;
601
602 case QSPI_IP_LAST_COMMAND_WRITE:
603 /* If PSB is set, last programming operation failed */
604 checkValue = SRValue & QSPI_IP_HF_SR_PSB_MASK;
605 break;
606
607 case QSPI_IP_LAST_COMMAND_WRITE_BUFFER_ABORT:
608 /* If WBASB 0, programming operation was not aborted */
609 checkValue = (~SRValue) & QSPI_IP_HF_SR_WBASB_MASK;
610 break;
611
612 case QSPI_IP_LAST_COMMAND_WRITE_SUSPEND:
613 /* If PSSB 0, no programming operation is suspended */
614 checkValue = (~SRValue) & QSPI_IP_HF_SR_PSSB_MASK;
615 break;
616
617 case QSPI_IP_LAST_COMMAND_ERASE_SUSPEND:
618 /* If ESSB 0, no erase operation is suspended */
619 checkValue = (~SRValue) & QSPI_IP_HF_SR_ESSB_MASK;
620 break;
621
622 case QSPI_IP_LAST_COMMAND_CRC_SUSPEND:
623 /* If CRCSSB 0, CRC operation is not suspended */
624 checkValue = (~SRValue) & QSPI_IP_HF_SR_CRCSSB_MASK;
625 break;
626
627 case QSPI_IP_LAST_COMMAND_SECTOR_ERASE_STATUS:
628 /* If ESTAT 0, previous erase did not complete successfully */
629 checkValue = (~SRValue) & QSPI_IP_HF_SR_ESTAT_MASK;
630 break;
631
632 default: /* QSPI_IP_LAST_COMMAND_NONE */
633 /* Do nothing */
634 break;
635 }
636
637 /* If the check different than zero, there is an error */
638 if (checkValue != 0U)
639 {
640 status = STATUS_QSPI_IP_ERROR;
641 }
642
643 return status;
644 }
645
646
647 /*FUNCTION**********************************************************************
648 *
649 * Function Name : Qspi_Ip_HyperflashGetMemoryStatus
650 * Description : Get the flash device status according to the last command executed
651 *
652 *END**************************************************************************/
Qspi_Ip_HyperflashGetMemoryStatus(uint32 instance)653 Qspi_Ip_StatusType Qspi_Ip_HyperflashGetMemoryStatus(uint32 instance)
654 {
655 const Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
656 Qspi_Ip_StatusType status;
657 uint16 SRValue = 0U;
658
659 /* Read status register */
660 status = Qspi_Ip_HyperflashGetStatusRegister(instance, &SRValue);
661
662 if (STATUS_QSPI_IP_SUCCESS == status)
663 {
664 /* Check if device is busy */
665 if ((SRValue & QSPI_IP_HF_SR_DRB_MASK) == 0U)
666 {
667 status = STATUS_QSPI_IP_BUSY;
668 }
669 }
670
671 if (STATUS_QSPI_IP_SUCCESS == status)
672 {
673 /* Clear Status Register */
674 status = Qspi_Ip_HyperflashStatusRegisterClear(instance);
675 }
676
677 if (STATUS_QSPI_IP_SUCCESS == status)
678 {
679 /* Decode Status Register */
680 status = Qspi_Ip_HyperflashStatusRegisterDecode(SRValue, state->lastCommand);
681 }
682
683 return status;
684 }
685
686 /*FUNCTION******************************************************************************
687 *
688 * Function Name : Qspi_Ip_HyperflashEraseNonVolatileConfigurationRegister
689 * Description : Erases the non-volatile configuration register.
690 *
691 *END***********************************************************************************/
Qspi_Ip_HyperflashEraseNonVolatileConfigurationRegister(uint32 instance)692 static Qspi_Ip_StatusType Qspi_Ip_HyperflashEraseNonVolatileConfigurationRegister(uint32 instance)
693 {
694 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
695 Qspi_Ip_StatusType status;
696
697 /* Send unclock cycles 1 & 2 */
698 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
699
700 if (STATUS_QSPI_IP_SUCCESS == status)
701 {
702 /* Erase Nonvolatile Configuration Registers */
703 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_ENVCR, 0xAAA);
704 state->lastCommand = QSPI_IP_LAST_COMMAND_ERASE;
705 }
706
707 return status;
708 }
709
710
711 /*FUNCTION******************************************************************************
712 *
713 * Function Name : Qspi_Ip_HyperflashProgramNonVolatileConfigurationRegister
714 * Description : Programs the Non-volatile configuration register of the flash device.
715 *
716 *END***********************************************************************************/
Qspi_Ip_HyperflashProgramNonVolatileConfigurationRegister(uint32 instance,const uint16 * data)717 static Qspi_Ip_StatusType Qspi_Ip_HyperflashProgramNonVolatileConfigurationRegister(uint32 instance,
718 const uint16 *data
719 )
720 {
721 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
722 Qspi_Ip_StatusType status;
723
724 /* Send unclock cycles 1 & 2 */
725 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
726
727 if (STATUS_QSPI_IP_SUCCESS == status)
728 {
729 /* Third cycle */
730 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_PNVCR, 0xAAA);
731 }
732
733 if (STATUS_QSPI_IP_SUCCESS == status)
734 {
735 /* Fourth cycle */
736 status = Qspi_Ip_RunWriteCommand(instance, QSPI_IP_HF_LUT_WRITE, 0U, (const uint8 *)data, 2U);
737 state->lastCommand = QSPI_IP_LAST_COMMAND_WRITE;
738 }
739
740 return status;
741 }
742
743 /*FUNCTION**********************************************************************
744 *
745 * Function Name : Qspi_Ip_HyperflashGetNonVolatileConfigurationRegister
746 * Description : Reads the non-volatile configuration register
747 *
748 *END**************************************************************************/
Qspi_Ip_HyperflashGetNonVolatileConfigurationRegister(uint32 instance,uint16 * dataRead)749 static Qspi_Ip_StatusType Qspi_Ip_HyperflashGetNonVolatileConfigurationRegister(uint32 instance,
750 uint16 * dataRead
751 )
752 {
753 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
754 Qspi_Ip_StatusType status;
755
756 /* Send unclock cycles 1 & 2 */
757 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
758
759 if (STATUS_QSPI_IP_SUCCESS == status)
760 {
761 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_RDNVCR, 0xAAA);
762 }
763
764 if (STATUS_QSPI_IP_SUCCESS == status)
765 {
766 status = Qspi_Ip_HyperflashPatchRunReadCommand(instance, QSPI_IP_HF_LUT_READ, 0U, (uint8 *)dataRead, 2U);
767 state->lastCommand = QSPI_IP_LAST_COMMAND_NONE;
768 }
769
770 return status;
771 }
772
773
774 /*FUNCTION**********************************************************************
775 *
776 * Function Name : Qspi_Ip_HyperflashLoadVolatileConfigurationRegister
777 * Description : Loads volatile configuration register with the data provided
778 *
779 *END**************************************************************************/
Qspi_Ip_HyperflashLoadVolatileConfigurationRegister(uint32 instance,const uint16 * data)780 static Qspi_Ip_StatusType Qspi_Ip_HyperflashLoadVolatileConfigurationRegister(uint32 instance,
781 const uint16 * data
782 )
783 {
784 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
785 Qspi_Ip_StatusType status;
786
787 /* Send unclock cycles 1 & 2 */
788 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
789
790 if (STATUS_QSPI_IP_SUCCESS == status)
791 {
792 /* Third cycle */
793 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_LDVCR, 0xAAA);
794 }
795
796 if (STATUS_QSPI_IP_SUCCESS == status)
797 {
798 /* Fourth cycle */
799 status = Qspi_Ip_RunWriteCommand(instance, QSPI_IP_HF_LUT_WRITE, 0U, (const uint8 *)data, 2U);
800 state->lastCommand = QSPI_IP_LAST_COMMAND_WRITE;
801 }
802
803 return status;
804 }
805
806
807 /*FUNCTION**********************************************************************
808 *
809 * Function Name : Qspi_Ip_HyperflashSectorBlankCheck
810 * Description : Checks if a specified sector is erased
811 *
812 *END**************************************************************************/
Qspi_Ip_HyperflashSectorBlankCheck(uint32 instance,uint32 sectorAddress)813 Qspi_Ip_StatusType Qspi_Ip_HyperflashSectorBlankCheck(uint32 instance,
814 uint32 sectorAddress
815 )
816 {
817 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
818 Qspi_Ip_StatusType status;
819 uint32 startAddr;
820
821 /* Calculate starting address of the address provided */
822 startAddr = (uint32)(sectorAddress & ~(QSPI_IP_HYPERFLASH_SECTOR_SIZE - 1U));
823
824 /* Write at address 0x555 of the sector specified */
825 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_BC, (startAddr + (uint32)0xAAA));
826 if (STATUS_QSPI_IP_SUCCESS == status)
827 {
828 state->lastCommand = QSPI_IP_LAST_COMMAND_ERASE;
829 }
830
831 return status;
832 }
833
834 /*FUNCTION**********************************************************************
835 *
836 * Function Name : Qspi_Ip_HyperflashSectorErase
837 * Description : Erase a specified sector (4KB or 256KB) in hyperflash.
838 *
839 *END**************************************************************************/
Qspi_Ip_HyperflashSectorErase(uint32 instance,uint32 sectorAddress)840 Qspi_Ip_StatusType Qspi_Ip_HyperflashSectorErase(uint32 instance,
841 uint32 sectorAddress
842 )
843 {
844 Qspi_Ip_StatusType status;
845
846 /* Send unclock cycles 1 & 2 */
847 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
848
849 if (STATUS_QSPI_IP_SUCCESS == status)
850 {
851 /* Command Cycle 1 */
852 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_80, 0xAAA);
853 }
854
855 if (STATUS_QSPI_IP_SUCCESS == status)
856 {
857 /* Command Cycle 2 */
858 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_AA, 0xAAA);
859 }
860
861 if (STATUS_QSPI_IP_SUCCESS == status)
862 {
863 /* Command Cycle 3 */
864 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_55, 0x554);
865 }
866
867 if (STATUS_QSPI_IP_SUCCESS == status)
868 {
869 /* Specify the address for erasure */
870 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_SE, sectorAddress);
871 }
872
873 return status;
874 }
875
876
877 /*FUNCTION**********************************************************************
878 *
879 * Function Name : Qspi_Ip_HyperflashProgramBufferToFlashConfirm
880 * Description : Program buffer to flash confirm command
881 *END**************************************************************************/
Qspi_Ip_HyperflashProgramBufferToFlashConfirm(uint32 instance,uint32 sectorAddr)882 static Qspi_Ip_StatusType Qspi_Ip_HyperflashProgramBufferToFlashConfirm(uint32 instance,
883 uint32 sectorAddr
884 )
885 {
886 Qspi_Ip_StateType *state = &Qspi_Ip_MemoryStateStructure[instance];
887 Qspi_Ip_StatusType status;
888
889 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_PBF, sectorAddr);
890 state->lastCommand = QSPI_IP_LAST_COMMAND_NONE;
891
892 return status;
893 }
894
895 /*FUNCTION**********************************************************************
896 *
897 * Function Name : Qspi_Ip_HyperflashChipErase
898 * Description : Erases the entire chip
899 *
900 *END**************************************************************************/
Qspi_Ip_HyperflashChipErase(uint32 instance)901 Qspi_Ip_StatusType Qspi_Ip_HyperflashChipErase(uint32 instance)
902 {
903 Qspi_Ip_StatusType status;
904
905 /* Send unclock cycles 1 & 2 */
906 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
907
908 if (STATUS_QSPI_IP_SUCCESS == status)
909 {
910 /* Send set-up command */
911 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_80, 0xAAA);
912 }
913
914 if (STATUS_QSPI_IP_SUCCESS == status)
915 {
916 /* Two additional unlock write cycles */
917 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
918 }
919
920 if (STATUS_QSPI_IP_SUCCESS == status)
921 {
922 /* Send Chip Erase command */
923 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CE, 0xAAA);
924 }
925
926 return status;
927 }
928
929 /*FUNCTION**********************************************************************
930 *
931 * Function Name : Qspi_Ip_HyperflashProgram
932 * Description : Writes from 1 up to 512 bytes to write buffer.
933 * The address provided should be in the same line buffer.
934 *
935 *END**************************************************************************/
Qspi_Ip_HyperflashProgram(uint32 instance,uint32 address,const uint8 * data,uint32 size)936 Qspi_Ip_StatusType Qspi_Ip_HyperflashProgram(uint32 instance,
937 uint32 address,
938 const uint8 * data,
939 uint32 size
940 )
941 {
942 Qspi_Ip_StatusType status;
943 const uint32 sectorAddress = address & ~(QSPI_IP_HYPERFLASH_SECTOR_SIZE - 1U);
944 uint32 selectAddress = address;
945 const uint8 * dataPtr = data;
946
947 /* Get the padding information */
948 const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
949 const uint32 qspiInstance = state->connection->qspiInstance;
950 const uint32 padding = (uint32)Qspi_Ip_MemoryPadding[qspiInstance];
951 const uint32 prePadding = padding >> 4U;
952 const uint32 postPadding = padding & 0x0FU;
953 Qspi_Ip_MemoryPadding[qspiInstance] = 0U; /* Clear all padding*/
954
955 /* Calculate the word count to program */
956 uint32 byteCnt = size;
957 const uint32 byteTotal = byteCnt + prePadding + postPadding;
958 const uint32 wordCnt = (byteTotal >> 1U) - 1U; /* minus 1 */
959
960 /* Send unclock cycles 1 & 2 */
961 status = Qspi_Ip_HyperflashSendUnlockCycles12(instance);
962
963 if (STATUS_QSPI_IP_SUCCESS == status)
964 {
965 /* Send pre-read with operand 0x25, third cycle */
966 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_25, sectorAddress);
967 }
968
969 if (STATUS_QSPI_IP_SUCCESS == status)
970 {
971 /* Patch LUT sequence with number of words to program minus 1 */
972 Qspi_Ip_HyperflashLutTable[QSPI_IP_HF_LUT_WC + 4U] =
973 (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)QSPI_IP_LUT_INSTR_CMD_DDR |
974 (Qspi_Ip_InstrOpType)QSPI_IP_LUT_PADS_8 |
975 (Qspi_Ip_InstrOpType)wordCnt);
976
977 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_WC, sectorAddress);
978 }
979
980 /* Load each Address/Data pair */
981 if (STATUS_QSPI_IP_SUCCESS == status)
982 {
983 /* The start address is unaligned */
984 if (prePadding != 0U)
985 {
986 /* Set prePadding */
987 Qspi_Ip_MemoryPadding[qspiInstance] = (uint8)(prePadding << 4UL);
988 /* Load the first data byte */
989 status = Qspi_Ip_RunWriteCommand(instance, QSPI_IP_HF_LUT_WB, selectAddress, dataPtr, 1U);
990 /* Move to the next data */
991 selectAddress += 2U;
992 dataPtr = &dataPtr[1U];
993 byteCnt -= 1U;
994 }
995
996 /* Loop for aligned cases */
997 while ((byteCnt >= 2U) && (STATUS_QSPI_IP_SUCCESS == status))
998 {
999 /* Load each word */
1000 status = Qspi_Ip_RunWriteCommand(instance, QSPI_IP_HF_LUT_WB, selectAddress, dataPtr, 2U);
1001 /* Move to the next data */
1002 selectAddress += 2U;
1003 dataPtr = &dataPtr[2U];
1004 byteCnt -= 2U;
1005 }
1006
1007 /* The end address is unaligned */
1008 if ((postPadding != 0U) && (STATUS_QSPI_IP_SUCCESS == status))
1009 {
1010 /* Set postPadding */
1011 Qspi_Ip_MemoryPadding[qspiInstance] = (uint8)postPadding;
1012 /* Load the last data byte */
1013 status = Qspi_Ip_RunWriteCommand(instance, QSPI_IP_HF_LUT_WB, selectAddress, dataPtr, 1U);
1014 }
1015 }
1016
1017 if (STATUS_QSPI_IP_SUCCESS == status)
1018 {
1019 /* Write Program Buffer to Flash Confirm */
1020 status = Qspi_Ip_HyperflashProgramBufferToFlashConfirm(instance, sectorAddress);
1021 }
1022
1023 return status;
1024 }
1025
1026
1027 /*FUNCTION**********************************************************************
1028 *
1029 * Function Name : Qspi_Ip_HyperflashReadId
1030 * Description : Read manufacturer ID from hyper flash.
1031 *
1032 *END**************************************************************************/
Qspi_Ip_HyperflashReadId(uint32 instance,uint32 wordAddress,uint8 * data,uint32 size)1033 Qspi_Ip_StatusType Qspi_Ip_HyperflashReadId(uint32 instance,
1034 uint32 wordAddress,
1035 uint8 * data,
1036 uint32 size
1037 )
1038 {
1039 Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
1040 Qspi_Ip_StatusType status;
1041
1042 /* CFI enter */
1043 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_CMD_98, 0xAAA);
1044
1045 if (STATUS_QSPI_IP_SUCCESS == status)
1046 {
1047 /* Read the ID at the designated word location (convert to byte address) */
1048 status = Qspi_Ip_HyperflashPatchRunReadCommand(instance,
1049 QSPI_IP_HF_LUT_READ,
1050 wordAddress << 1U,
1051 data,
1052 size);
1053 }
1054
1055 if (STATUS_QSPI_IP_SUCCESS == status)
1056 {
1057 /* ASO Exit: back to flash memory array */
1058 status = Qspi_Ip_RunCommand(instance, QSPI_IP_HF_LUT_RST, 0U);
1059 state->lastCommand = QSPI_IP_LAST_COMMAND_NONE;
1060 }
1061
1062 return status;
1063 }
1064
1065
1066 /*FUNCTION**********************************************************************
1067 *
1068 * Function Name : Qspi_Ip_HyperflashInitConfigurationRegister
1069 * Description : Sets up Volatile and Non-Volatile configuration registers
1070 *
1071 *END**************************************************************************/
Qspi_Ip_HyperflashInitConfigurationRegister(uint32 instance)1072 static Qspi_Ip_StatusType Qspi_Ip_HyperflashInitConfigurationRegister(uint32 instance)
1073 {
1074 const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
1075 Qspi_Ip_StatusType status;
1076 uint16 readValue;
1077 uint16 writeVCR;
1078
1079 /* Compute new configuration value */
1080 writeVCR = Qspi_Ip_HyperflashGetConfigurationValue(state->configuration->hfConfig);
1081
1082 /* Read Non-Volatile Configuration Register */
1083 status = Qspi_Ip_HyperflashGetNonVolatileConfigurationRegister(instance, &readValue);
1084
1085 if ((STATUS_QSPI_IP_SUCCESS == status) && (writeVCR != readValue))
1086 {
1087 /* Write the Non-Volatile register only if current configuration is different from the previous one */
1088
1089 /* Erase the NVCR */
1090 status = Qspi_Ip_HyperflashEraseNonVolatileConfigurationRegister(instance);
1091 if (STATUS_QSPI_IP_SUCCESS == status)
1092 {
1093 /* Wait until Configuration register is erased */
1094 status = Qspi_Ip_HyperflashWaitDeviceReady(instance);
1095 }
1096
1097 if (STATUS_QSPI_IP_SUCCESS == status)
1098 {
1099 /* Loads value into non-volatile configuration register */
1100 status = Qspi_Ip_HyperflashProgramNonVolatileConfigurationRegister(instance, &writeVCR);
1101 }
1102
1103 if (STATUS_QSPI_IP_SUCCESS == status)
1104 {
1105 /* Wait until Configuration register is programmed */
1106 status = Qspi_Ip_HyperflashWaitDeviceReady(instance);
1107 }
1108 }
1109
1110 if (STATUS_QSPI_IP_SUCCESS == status)
1111 {
1112 /* Load values into volatile configuration register */
1113 status = Qspi_Ip_HyperflashLoadVolatileConfigurationRegister(instance, &writeVCR);
1114 }
1115
1116 if (STATUS_QSPI_IP_SUCCESS == status)
1117 {
1118 /* Wait until Configuration register is updated */
1119 status = Qspi_Ip_HyperflashWaitDeviceReady(instance);
1120 }
1121
1122 return status;
1123 }
1124
1125
1126 /*FUNCTION**********************************************************************
1127 *
1128 * Function Name : Qspi_Ip_HyperflashInit
1129 * Description : Initializes the hyper flash memory
1130 *
1131 *END**************************************************************************/
Qspi_Ip_HyperflashInit(uint32 instance)1132 Qspi_Ip_StatusType Qspi_Ip_HyperflashInit(uint32 instance)
1133 {
1134 Qspi_Ip_StatusType status;
1135 uint16 readValue;
1136
1137 /* Check status register */
1138 status = Qspi_Ip_HyperflashGetStatusRegister(instance, &readValue);
1139 if (STATUS_QSPI_IP_SUCCESS == status)
1140 {
1141 /* Check if device is ready */
1142 if ((readValue & QSPI_IP_HF_SR_DRB_MASK) == 0U)
1143 {
1144 status = STATUS_QSPI_IP_BUSY;
1145 }
1146 }
1147
1148 if (STATUS_QSPI_IP_SUCCESS == status)
1149 {
1150 /* Set up Volatile and Non-Volatile Configuration Registers */
1151 status = Qspi_Ip_HyperflashInitConfigurationRegister(instance);
1152 }
1153
1154 return status;
1155 }
1156
1157
1158 #define FLS_STOP_SEC_CODE
1159 #include "Fls_MemMap.h"
1160
1161
1162 #endif /* QSPI_IP_MEM_INSTANCE_COUNT */
1163
1164 #ifdef __cplusplus
1165 }
1166 #endif
1167
1168 /** @} */
1169
1170
