1 /**************************************************************************//** 2 * @file qspi_reg.h 3 * @version V1.00 4 * @brief QSPI register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __QSPI_REG_H__ 10 #define __QSPI_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/ 19 /** 20 @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI) 21 Memory Mapped Structure for QSPI Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var QSPI_T::CTL 31 * Offset: 0x00 QSPI Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |SPIEN |QSPI Transfer Control Enable Bit 36 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 37 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 38 * | | |0 = Transfer control Disabled. 39 * | | |1 = Transfer control Enabled. 40 * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. 41 * |[1] |RXNEG |Receive on Negative Edge 42 * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. 43 * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. 44 * |[2] |TXNEG |Transmit on Negative Edge 45 * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. 46 * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. 47 * | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]). 48 * |[3] |CLKPOL |Clock Polarity 49 * | | |0 = QSPI bus clock is idle low. 50 * | | |1 = QSPI bus clock is idle high. 51 * |[7:4] |SUSPITV |Suspend Interval 52 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer 53 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 54 * | | |The default value is 0x3 55 * | | |The period of the suspend interval is obtained according to the following equation. 56 * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle 57 * | | |Example: 58 * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. 59 * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. 60 * | | |..... 61 * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. 62 * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. 63 * | | |Note: In TX DTR mode, SUSPITV equals to 0x0. 64 * |[12:8] |DWIDTH |Data Width 65 * | | |This field specifies how many bits can be transmitted / received in one transaction 66 * | | |The minimum bit length is 8 bits and can up to 32 bits. 67 * | | |DWIDTH = 0x08 .... 8 bits. 68 * | | |DWIDTH = 0x09 .... 9 bits. 69 * | | |..... 70 * | | |DWIDTH = 0x1F .... 31 bits. 71 * | | |DWIDTH = 0x00 .... 32 bits. 72 * | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode 73 * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3. 74 * |[13] |LSB |Send LSB First 75 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 76 * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). 77 * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit 78 * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer 79 * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 80 * | | |0 = QSPI operates in full-duplex transfer. 81 * | | |1 = QSPI operates in half-duplex transfer. 82 * |[15] |RXONLY |Receive-only Mode Enable Bit 83 * | | |This bit field is only available in Master mode 84 * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. 85 * | | |0 = Receive-only mode Disabled. 86 * | | |1 = Receive-only mode Enabled. 87 * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit 88 * | | |0 = 2-Bit Transfer mode Disabled. 89 * | | |1 = 2-Bit Transfer mode Enabled. 90 * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data 91 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 92 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 93 * | | |0 = QSPI unit transfer interrupt Disabled. 94 * | | |1 = QSPI unit transfer interrupt Enabled. 95 * |[18] |SLAVE |Slave Mode Control 96 * | | |0 = Master mode. 97 * | | |1 = Slave mode. 98 * |[19] |REORDER |Byte Reorder Function Enable Bit 99 * | | |0 = Byte Reorder function Disabled. 100 * | | |1 = Byte Reorder function Enabled 101 * | | |A byte suspend interval will be inserted among each byte 102 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 103 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 104 * |[20] |DATDIR |Data Port Direction Control 105 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 106 * | | |0 = QSPI data is input direction. 107 * | | |1 = QSPI data is output direction. 108 * |[21] |DUALIOEN |Dual I/O Mode Enable Bit 109 * | | |0 = Dual I/O mode Disabled. 110 * | | |1 = Dual I/O mode Enabled. 111 * |[22] |QUADIOEN |Quad I/O Mode Enable Bit 112 * | | |0 = Quad I/O mode Disabled. 113 * | | |1 = Quad I/O mode Enabled. 114 * |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit 115 * | | |0 = TX DTR mode Disabled. 116 * | | |1 = TX DTR mode Enabled. 117 * | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode. 118 * @var QSPI_T::CLKDIV 119 * Offset: 0x04 QSPI Clock Divider Register 120 * --------------------------------------------------------------------------------------------------- 121 * |Bits |Field |Descriptions 122 * | :----: | :----: | :---- | 123 * |[8:0] |DIVIDER |Clock Divider 124 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master 125 * | | |The frequency is obtained according to the following equation. 126 * | | |where 127 * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 128 * | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register. 129 * @var QSPI_T::SSCTL 130 * Offset: 0x08 QSPI Slave Select Control Register 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[0] |SS |Slave Selection Control 135 * | | |If AUTOSS bit is cleared to 0, 136 * | | |0 = Set the QSPIx_SS line to inactive state. 137 * | | |1 = Set the QSPIx_SS line to active state. 138 * | | |If the AUTOSS bit is set to 1, 139 * | | |0 = Keep the QSPIx_SS line at inactive state. 140 * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 141 * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). 142 * | | |Note: Master mode only. 143 * |[2] |SSACTPOL |Slave Selection Active Polarity 144 * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). 145 * | | |0 = The slave selection signal QSPIx_SS is active low. 146 * | | |1 = The slave selection signal QSPIx_SS is active high. 147 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit 148 * | | |0 = Automatic slave selection function Disabled 149 * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). 150 * | | |1 = Automatic slave selection function Enabled. 151 * | | |Note: Master mode only. 152 * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit 153 * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. 154 * | | |0 = 4-wire bi-direction interface. 155 * | | |1 = 3-wire bi-direction interface. 156 * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit 157 * | | |0 = Slave mode time-out interrupt Disabled. 158 * | | |1 = Slave mode time-out interrupt Enabled. 159 * |[6] |SLVTORST |Slave Mode Time-out Reset Control 160 * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. 161 * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. 162 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 163 * | | |0 = Slave mode bit count error interrupt Disabled. 164 * | | |1 = Slave mode bit count error interrupt Enabled. 165 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 166 * | | |0 = Slave mode TX under run interrupt Disabled. 167 * | | |1 = Slave mode TX under run interrupt Enabled. 168 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 169 * | | |0 = Slave select active interrupt Disabled. 170 * | | |1 = Slave select active interrupt Enabled. 171 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 172 * | | |0 = Slave select inactive interrupt Disabled. 173 * | | |1 = Slave select inactive interrupt Enabled. 174 * |[31:16] |SLVTOCNT |Slave Mode Time-out Period 175 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active 176 * | | |The clock source of the time-out counter is Slave peripheral clock 177 * | | |If the value is 0, it indicates the slave mode time-out function is disabled. 178 * @var QSPI_T::PDMACTL 179 * Offset: 0x0C QSPI PDMA Control Register 180 * --------------------------------------------------------------------------------------------------- 181 * |Bits |Field |Descriptions 182 * | :----: | :----: | :---- | 183 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 184 * | | |0 = Transmit PDMA function Disabled. 185 * | | |1 = Transmit PDMA function Enabled. 186 * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 187 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 188 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 189 * | | |0 = Receive PDMA function Disabled. 190 * | | |1 = Receive PDMA function Enabled. 191 * |[2] |PDMARST |PDMA Reset 192 * | | |0 = No effect. 193 * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. 194 * @var QSPI_T::FIFOCTL 195 * Offset: 0x10 QSPI FIFO Control Register 196 * --------------------------------------------------------------------------------------------------- 197 * |Bits |Field |Descriptions 198 * | :----: | :----: | :---- | 199 * |[0] |RXRST |Receive Reset 200 * | | |0 = No effect. 201 * | | |1 = Reset receive FIFO pointer and receive circuit 202 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 203 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 204 * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. 205 * |[1] |TXRST |Transmit Reset 206 * | | |0 = No effect. 207 * | | |1 = Reset transmit FIFO pointer and transmit circuit 208 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 209 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 210 * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. 211 * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. 212 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 213 * | | |0 = RX FIFO threshold interrupt Disabled. 214 * | | |1 = RX FIFO threshold interrupt Enabled. 215 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 216 * | | |0 = TX FIFO threshold interrupt Disabled. 217 * | | |1 = TX FIFO threshold interrupt Enabled. 218 * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit 219 * | | |0 = Receive time-out interrupt Disabled. 220 * | | |1 = Receive time-out interrupt Enabled. 221 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 222 * | | |0 = Receive FIFO overrun interrupt Disabled. 223 * | | |1 = Receive FIFO overrun interrupt Enabled. 224 * |[6] |TXUFPOL |TX Underflow Data Polarity 225 * | | |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode. 226 * | | |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode. 227 * | | |Note: 228 * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 229 * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 230 * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. 231 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 232 * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 233 * | | |This bit is used to enable the TX underflow interrupt. 234 * | | |0 = Slave TX underflow interrupt Disabled. 235 * | | |1 = Slave TX underflow interrupt Enabled. 236 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 237 * | | |0 = No effect. 238 * | | |1 = Clear receive FIFO pointer 239 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 240 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 241 * | | |Note: The RX shift register will not be cleared. 242 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 243 * | | |0 = No effect. 244 * | | |1 = Clear transmit FIFO pointer 245 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 246 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 247 * | | |Note: The TX shift register will not be cleared. 248 * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error 249 * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode. 250 * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode 251 * | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. 252 * | | |Note: Slave mode only. 253 * |[26:24] |RXTH |Receive FIFO Threshold 254 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 255 * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. 256 * |[30:28] |TXTH |Transmit FIFO Threshold 257 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 258 * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. 259 * @var QSPI_T::STATUS 260 * Offset: 0x14 QSPI Status Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[0] |BUSY |Busy Status (Read Only) 265 * | | |0 = QSPI controller is in idle state. 266 * | | |1 = QSPI controller is in busy state. 267 * | | |The following listing are the bus busy conditions: 268 * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. 269 * | | |b 270 * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 271 * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. 272 * | | |d. 273 * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. 274 * | | |e. 275 * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 276 * | | |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF 277 * | | |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point. 278 * |[1] |UNITIF |Unit Transfer Interrupt Flag 279 * | | |0 = No transaction has been finished since this bit was cleared to 0. 280 * | | |1 = QSPI controller has finished one unit transfer. 281 * | | |Note: This bit will be cleared by writing 1 to it. 282 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 283 * | | |0 = Slave select active interrupt was cleared or not occurred. 284 * | | |1 = Slave select active interrupt event occurred. 285 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 286 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 287 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 288 * | | |1 = Slave select inactive interrupt event occurred. 289 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 290 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 291 * | | |0 = The slave select line status is 0. 292 * | | |1 = The slave select line status is 1. 293 * | | |Note: This bit is only available in Slave mode 294 * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. 295 * |[5] |SLVTOIF |Slave Time-out Interrupt Flag 296 * | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started 297 * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. 298 * | | |0 = Slave time-out is not active. 299 * | | |1 = Slave time-out is active. 300 * | | |Note: This bit will be cleared by writing 1 to it. 301 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 302 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 303 * | | |0 = No Slave mode bit count error event. 304 * | | |1 = Slave mode bit count error event occurs. 305 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 306 * | | |This bit will be cleared by writing 1 to it. 307 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 308 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 309 * | | |0 = No Slave TX under run event. 310 * | | |1 = Slave TX under run event occurs. 311 * | | |Note: This bit will be cleared by writing 1 to it. 312 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 313 * | | |0 = Receive FIFO buffer is not empty. 314 * | | |1 = Receive FIFO buffer is empty. 315 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 316 * | | |0 = Receive FIFO buffer is not full. 317 * | | |1 = Receive FIFO buffer is full. 318 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 319 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 320 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 321 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 322 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 323 * | | |0 = No FIFO is overrun. 324 * | | |1 = Receive FIFO is overrun. 325 * | | |Note: This bit will be cleared by writing 1 to it. 326 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 327 * | | |0 = No receive FIFO time-out event. 328 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode 329 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 330 * | | |Note: This bit will be cleared by writing 1 to it. 331 * |[15] |SPIENSTS |QSPI Enable Status (Read Only) 332 * | | |0 = The QSPI controller is disabled. 333 * | | |1 = The QSPI controller is enabled. 334 * | | |Note: The QSPI peripheral clock is asynchronous with the system clock 335 * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. 336 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 337 * | | |0 = Transmit FIFO buffer is not empty. 338 * | | |1 = Transmit FIFO buffer is empty. 339 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 340 * | | |0 = Transmit FIFO buffer is not full. 341 * | | |1 = Transmit FIFO buffer is full. 342 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 343 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 344 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 345 * |[19] |TXUFIF |TX Underflow Interrupt Flag 346 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 347 * | | |0 = No effect. 348 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 349 * | | |Note 1: This bit will be cleared by writing 1 to it. 350 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 351 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 352 * | | |0 = The reset function of TXRST or RXRST is done. 353 * | | |1 = Doing the reset function of TXRST or RXRST. 354 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 355 * | | |User can check the status of this bit to monitor the reset function is doing or done. 356 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 357 * | | |This bit field indicates the valid data count of receive FIFO buffer. 358 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 359 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 360 * @var QSPI_T::STATUS2 361 * Offset: 0x18 QSPI Status2 Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data 366 * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode 367 * | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled. 368 * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]). 369 * | | |Note 2: Slave mode only. 370 * @var QSPI_T::TX 371 * Offset: 0x20 QSPI Data Transmit Register 372 * --------------------------------------------------------------------------------------------------- 373 * |Bits |Field |Descriptions 374 * | :----: | :----: | :---- | 375 * |[31:0] |TX |Data Transmit Register 376 * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers 377 * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode. 378 * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. 379 * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. 380 * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 381 * @var QSPI_T::RX 382 * Offset: 0x30 QSPI Data Receive Register 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[31:0] |RX |Data Receive Register (Read Only) 387 * | | |There are 8-level FIFO buffers in this controller. 388 * | | |The data receive register holds the data received from QSPI data input pin. 389 * | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 390 */ 391 __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ 392 __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ 393 __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ 394 __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ 395 __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ 396 __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ 397 __I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */ 398 __I uint32_t RESERVE0[1]; 399 __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ 400 __I uint32_t RESERVE1[3]; 401 __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ 402 403 } QSPI_T; 404 405 /** 406 @addtogroup QSPI_CONST QSPI Bit Field Definition 407 Constant Definitions for QSPI Controller 408 @{ 409 */ 410 411 #define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */ 412 #define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */ 413 414 #define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ 415 #define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ 416 417 #define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ 418 #define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ 419 420 #define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ 421 #define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ 422 423 #define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ 424 #define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ 425 426 #define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ 427 #define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ 428 429 #define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ 430 #define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ 431 432 #define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ 433 #define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ 434 435 #define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ 436 #define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ 437 438 #define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ 439 #define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ 440 441 #define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ 442 #define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ 443 444 #define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ 445 #define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ 446 447 #define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ 448 #define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ 449 450 #define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ 451 #define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ 452 453 #define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ 454 #define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ 455 456 #define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ 457 #define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ 458 459 #define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */ 460 #define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */ 461 462 #define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ 463 #define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ 464 465 #define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ 466 #define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ 467 468 #define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ 469 #define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ 470 471 #define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ 472 #define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ 473 474 #define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ 475 #define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ 476 477 #define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ 478 #define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ 479 480 #define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ 481 #define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ 482 483 #define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ 484 #define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ 485 486 #define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ 487 #define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ 488 489 #define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ 490 #define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ 491 492 #define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ 493 #define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ 494 495 #define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ 496 #define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ 497 498 #define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ 499 #define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ 500 501 #define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ 502 #define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ 503 504 #define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ 505 #define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ 506 507 #define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ 508 #define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ 509 510 #define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ 511 #define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ 512 513 #define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ 514 #define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ 515 516 #define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ 517 #define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ 518 519 #define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ 520 #define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ 521 522 #define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ 523 #define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ 524 525 #define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ 526 #define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ 527 528 #define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ 529 #define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ 530 531 #define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ 532 #define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ 533 534 #define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ 535 #define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ 536 537 #define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */ 538 #define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */ 539 540 #define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ 541 #define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ 542 543 #define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ 544 #define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ 545 546 #define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ 547 #define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ 548 549 #define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ 550 #define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ 551 552 #define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ 553 #define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ 554 555 #define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ 556 #define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ 557 558 #define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ 559 #define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ 560 561 #define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ 562 #define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ 563 564 #define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ 565 #define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ 566 567 #define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ 568 #define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ 569 570 #define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ 571 #define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ 572 573 #define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ 574 #define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ 575 576 #define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ 577 #define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ 578 579 #define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ 580 #define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ 581 582 #define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ 583 #define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ 584 585 #define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */ 586 #define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */ 587 588 #define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ 589 #define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ 590 591 #define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ 592 #define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ 593 594 #define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ 595 #define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ 596 597 #define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ 598 #define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ 599 600 #define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ 601 #define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ 602 603 #define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ 604 #define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ 605 606 #define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ 607 #define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ 608 609 #define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */ 610 #define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */ 611 612 #define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ 613 #define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ 614 615 #define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ 616 #define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ 617 618 /**@}*/ /* QSPI_CONST */ 619 /**@}*/ /* end of QSPI register group */ 620 /**@}*/ /* end of REGISTER group */ 621 622 #endif /* __QSPI_REG_H__ */ 623
