1 /**************************************************************************//** 2 * @file qspi.h 3 * @version V3.00 4 * @brief M480 series QSPI driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __QSPI_H__ 10 #define __QSPI_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup QSPI_Driver QSPI Driver 23 @{ 24 */ 25 26 /** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants 27 @{ 28 */ 29 30 #define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ 31 #define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ 32 #define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ 33 #define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ 34 35 #define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ 36 #define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ 37 38 #define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ 39 #define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ 40 #define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ 41 42 /* QSPI Interrupt Mask */ 43 #define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ 44 #define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ 45 #define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ 46 #define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ 47 #define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ 48 #define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ 49 #define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ 50 #define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ 51 #define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ 52 #define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ 53 54 /* QSPI Status Mask */ 55 #define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ 56 #define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ 57 #define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ 58 #define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ 59 #define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ 60 #define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ 61 #define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */ 62 #define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ 63 64 /*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ 65 66 67 /** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions 68 @{ 69 */ 70 71 /** 72 * @brief Clear the unit transfer interrupt flag. 73 * @param[in] qspi The pointer of the specified QSPI module. 74 * @return None. 75 * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. 76 * \hideinitializer 77 */ 78 #define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) 79 80 /** 81 * @brief Trigger RX PDMA function. 82 * @param[in] qspi The pointer of the specified QSPI module. 83 * @return None. 84 * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. 85 * \hideinitializer 86 */ 87 #define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) 88 89 /** 90 * @brief Trigger TX PDMA function. 91 * @param[in] qspi The pointer of the specified QSPI module. 92 * @return None. 93 * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. 94 * \hideinitializer 95 */ 96 #define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) 97 98 /** 99 * @brief Disable RX PDMA transfer. 100 * @param[in] qspi The pointer of the specified QSPI module. 101 * @return None. 102 * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. 103 * \hideinitializer 104 */ 105 #define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) 106 107 /** 108 * @brief Disable TX PDMA transfer. 109 * @param[in] qspi The pointer of the specified QSPI module. 110 * @return None. 111 * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. 112 * \hideinitializer 113 */ 114 #define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) 115 116 /** 117 * @brief Get the count of available data in RX FIFO. 118 * @param[in] qspi The pointer of the specified QSPI module. 119 * @return The count of available data in RX FIFO. 120 * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. 121 * \hideinitializer 122 */ 123 #define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) 124 125 /** 126 * @brief Get the RX FIFO empty flag. 127 * @param[in] qspi The pointer of the specified QSPI module. 128 * @retval 0 RX FIFO is not empty. 129 * @retval 1 RX FIFO is empty. 130 * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. 131 * \hideinitializer 132 */ 133 #define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) 134 135 /** 136 * @brief Get the TX FIFO empty flag. 137 * @param[in] qspi The pointer of the specified QSPI module. 138 * @retval 0 TX FIFO is not empty. 139 * @retval 1 TX FIFO is empty. 140 * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. 141 * \hideinitializer 142 */ 143 #define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) 144 145 /** 146 * @brief Get the TX FIFO full flag. 147 * @param[in] qspi The pointer of the specified QSPI module. 148 * @retval 0 TX FIFO is not full. 149 * @retval 1 TX FIFO is full. 150 * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. 151 * \hideinitializer 152 */ 153 #define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) 154 155 /** 156 * @brief Get the datum read from RX register. 157 * @param[in] qspi The pointer of the specified QSPI module. 158 * @return Data in RX register. 159 * @details Read QSPI_RX register to get the received datum. 160 * \hideinitializer 161 */ 162 #define QSPI_READ_RX(qspi) ((qspi)->RX) 163 164 /** 165 * @brief Write datum to TX register. 166 * @param[in] qspi The pointer of the specified QSPI module. 167 * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. 168 * @return None. 169 * @details Write u32TxData to QSPI_TX register. 170 * \hideinitializer 171 */ 172 #define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) 173 174 /** 175 * @brief Set QSPIx_SS pin to high state. 176 * @param[in] qspi The pointer of the specified QSPI module. 177 * @return None. 178 * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. 179 * \hideinitializer 180 */ 181 #define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) 182 183 /** 184 * @brief Set QSPIx_SS pin to low state. 185 * @param[in] qspi The pointer of the specified QSPI module. 186 * @return None. 187 * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. 188 * \hideinitializer 189 */ 190 #define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) 191 192 /** 193 * @brief Enable Byte Reorder function. 194 * @param[in] qspi The pointer of the specified QSPI module. 195 * @return None. 196 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). 197 * \hideinitializer 198 */ 199 #define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) 200 201 /** 202 * @brief Disable Byte Reorder function. 203 * @param[in] qspi The pointer of the specified QSPI module. 204 * @return None. 205 * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. 206 * \hideinitializer 207 */ 208 #define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) 209 210 /** 211 * @brief Set the length of suspend interval. 212 * @param[in] qspi The pointer of the specified QSPI module. 213 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. 214 * @return None. 215 * @details Set the length of suspend interval according to u32SuspCycle. 216 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). 217 * \hideinitializer 218 */ 219 #define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) 220 221 /** 222 * @brief Set the QSPI transfer sequence with LSB first. 223 * @param[in] qspi The pointer of the specified QSPI module. 224 * @return None. 225 * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. 226 * \hideinitializer 227 */ 228 #define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) 229 230 /** 231 * @brief Set the QSPI transfer sequence with MSB first. 232 * @param[in] qspi The pointer of the specified SPI module. 233 * @return None. 234 * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. 235 * \hideinitializer 236 */ 237 #define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) 238 239 /** 240 * @brief Set the data width of a QSPI transaction. 241 * @param[in] qspi The pointer of the specified QSPI module. 242 * @param[in] u32Width The bit width of one transaction. 243 * @return None. 244 * @details The data width can be 8 ~ 32 bits. 245 * \hideinitializer 246 */ 247 #define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) 248 249 /** 250 * @brief Get the QSPI busy state. 251 * @param[in] qspi The pointer of the specified QSPI module. 252 * @retval 0 QSPI controller is not busy. 253 * @retval 1 QSPI controller is busy. 254 * @details This macro will return the busy state of QSPI controller. 255 * \hideinitializer 256 */ 257 #define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) 258 259 /** 260 * @brief Enable QSPI controller. 261 * @param[in] qspi The pointer of the specified QSPI module. 262 * @return None. 263 * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. 264 * \hideinitializer 265 */ 266 #define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) 267 268 /** 269 * @brief Disable QSPI controller. 270 * @param[in] qspi The pointer of the specified QSPI module. 271 * @return None. 272 * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. 273 * \hideinitializer 274 */ 275 #define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) 276 277 /** 278 * @brief Disable QSPI Dual IO function. 279 * @param[in] qspi is the base address of QSPI module. 280 * @return none 281 * \hideinitializer 282 */ 283 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) 284 285 /** 286 * @brief Enable Dual IO function and set QSPI Dual IO direction to input. 287 * @param[in] qspi is the base address of QSPI module. 288 * @return none 289 * \hideinitializer 290 */ 291 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) 292 293 /** 294 * @brief Enable Dual IO function and set QSPI Dual IO direction to output. 295 * @param[in] qspi is the base address of QSPI module. 296 * @return none 297 * \hideinitializer 298 */ 299 #define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) 300 301 /** 302 * @brief Disable QSPI Dual IO function. 303 * @param[in] qspi is the base address of QSPI module. 304 * @return none 305 * \hideinitializer 306 */ 307 #define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) 308 309 /** 310 * @brief Set QSPI Quad IO direction to input. 311 * @param[in] qspi is the base address of QSPI module. 312 * @return none 313 * \hideinitializer 314 */ 315 #define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) 316 317 /** 318 * @brief Set QSPI Quad IO direction to output. 319 * @param[in] qspi is the base address of QSPI module. 320 * @return none 321 * \hideinitializer 322 */ 323 #define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) 324 325 326 327 328 /* Function prototype declaration */ 329 uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); 330 void QSPI_Close(QSPI_T *qspi); 331 void QSPI_ClearRxFIFO(QSPI_T *qspi); 332 void QSPI_ClearTxFIFO(QSPI_T *qspi); 333 void QSPI_DisableAutoSS(QSPI_T *qspi); 334 void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); 335 uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); 336 void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); 337 uint32_t QSPI_GetBusClock(QSPI_T *qspi); 338 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); 339 void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); 340 uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); 341 void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); 342 uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); 343 344 345 /*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ 346 347 /*@}*/ /* end of group QSPI_Driver */ 348 349 /*@}*/ /* end of group Standard_Driver */ 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif 356 357 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 358
