1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef QSPI_IP_HYPERFLASHTYPES_H 8 #define QSPI_IP_HYPERFLASHTYPES_H 9 10 /** 11 * @file Qspi_Ip_HyperflashTypes.h 12 * 13 * @addtogroup IPV_QSPI QSPI IPV Driver 14 * @{ 15 */ 16 17 /* implements Qspi_Ip_HyperflashTypes.h_Artifact */ 18 19 #ifdef __cplusplus 20 extern "C"{ 21 #endif 22 23 /*================================================================================================== 24 * INCLUDE FILES 25 ==================================================================================================*/ 26 #include "StandardTypes.h" 27 28 29 /*================================================================================================== 30 * SOURCE FILE VERSION INFORMATION 31 ==================================================================================================*/ 32 #define QSPI_IP_HYPERFLASHTYPES_VENDOR_ID 43 33 #define QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MAJOR_VERSION 4 34 #define QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MINOR_VERSION 7 35 #define QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_REVISION_VERSION 0 36 #define QSPI_IP_HYPERFLASHTYPES_SW_MAJOR_VERSION 3 37 #define QSPI_IP_HYPERFLASHTYPES_SW_MINOR_VERSION 0 38 #define QSPI_IP_HYPERFLASHTYPES_SW_PATCH_VERSION 0 39 40 41 /*================================================================================================== 42 * FILE VERSION CHECKS 43 ==================================================================================================*/ 44 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 45 /* Check if Qspi_Ip_HyperflashTypes header file and StandardTypes.h header file are of the same Autosar version */ 46 #if ((QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 47 (QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION) \ 48 ) 49 #error "Autosar Version Numbers of Qspi_Ip_HyperflashTypes.h and StandardTypes.h are different" 50 #endif 51 #endif 52 53 54 /******************************************************************************* 55 * Definitions 56 ******************************************************************************/ 57 58 /* Address of the sector selected. Address bits AMAX-A17 for 256KB sectors and AMAX-A11 for 4KB parameter sectors 59 Parameter-sectors need A[16:11] to identify the target address during erase and program command sequences 60 Unused bits are "no matter" (memory device will ignore them), so just use the smallest size in both cases 61 */ 62 #define QSPI_IP_HYPERFLASH_SECTOR_SIZE 0x1000U /* 4096-byte */ 63 64 65 /* LUT entries used for hyperflash command sequences */ 66 #define QSPI_IP_HF_LUT_COMMON_555_AA 0U /* Pre-command with address 0x555 and operand 0xAA */ 67 #define QSPI_IP_HF_LUT_COMMON_2AA_55 6U /* Pre-command with address 0x2AA and operand 0x55 */ 68 #define QSPI_IP_HF_LUT_READ 12U /* Read data linear */ 69 #define QSPI_IP_HF_LUT_WRITE 18U /* Write data */ 70 #define QSPI_IP_HF_LUT_RDSR 23U /* Read status register */ 71 #define QSPI_IP_HF_LUT_RDSR_SEQ2 29U /* Read status register second sequence */ 72 #define QSPI_IP_HF_LUT_WP 35U /* Word Programming */ 73 #define QSPI_IP_HF_LUT_WP_SEQ1 41U /* Word Programming second sequence */ 74 75 #define QSPI_IP_HF_LUT_CMD_80 46U 76 #define QSPI_IP_HF_LUT_CMD_AA 52U 77 #define QSPI_IP_HF_LUT_CMD_55 58U 78 #define QSPI_IP_HF_LUT_SE 64U 79 #define QSPI_IP_HF_LUT_CE 70U 80 #define QSPI_IP_HF_LUT_RST 76U 81 #define QSPI_IP_HF_LUT_SRC 82U 82 #define QSPI_IP_HF_LUT_BC 88U 83 #define QSPI_IP_HF_LUT_CMD_25 94U 84 #define QSPI_IP_HF_LUT_WC 100U 85 #define QSPI_IP_HF_LUT_WB 106U 86 #define QSPI_IP_HF_LUT_PBF 111U 87 #define QSPI_IP_HF_LUT_PS 117U /* Program suspend */ 88 #define QSPI_IP_HF_LUT_PR 123U /* Program resume */ 89 #define QSPI_IP_HF_LUT_ES 129U /* Erase suspend */ 90 #define QSPI_IP_HF_LUT_ER 135U /* Erase resume */ 91 #define QSPI_IP_HF_LUT_RDNVCR 141U 92 #define QSPI_IP_HF_LUT_ENVCR 147U 93 #define QSPI_IP_HF_LUT_PNVCR 153U 94 #define QSPI_IP_HF_LUT_LDVCR 159U 95 #define QSPI_IP_HF_LUT_CMD_98 165U 96 97 #define QSPI_IP_HF_LUT_SIZE 171U 98 #define QSPI_IP_HF_LUT_NAME Qspi_Ip_HyperflashLutTable 99 100 /* Number of commands in the software reset sequence */ 101 #define QSPI_IP_HF_RST_CNT 1U 102 103 104 /******************************************************************************* 105 * Enumerations. 106 ******************************************************************************/ 107 108 /*! 109 * @brief Parameter sector map 110 * 111 * This structure is used to configure how the Parameter-Sectors are used and how they are mapped into the address map. 112 */ 113 typedef enum 114 { 115 QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_LOW = 0x00U, 116 QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_HIGH = 0x01U, 117 QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_LOW = 0x02U, 118 QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_HIGH = 0x03U 119 } Qspi_Ip_HyperflashParamSectorMapType; 120 121 122 /*! 123 * @brief Drive strength 124 * 125 * Hyperflash driver strength settings. 126 */ 127 typedef enum 128 { 129 QSPI_IP_HF_DRV_STRENGTH_000 = 0x00U, /*!< Typical Impedance for 1.8V: 27, Typical Impedance 3V: 20 */ 130 QSPI_IP_HF_DRV_STRENGTH_001 = 0x01U, /*!< Typical Impedance for 1.8V: 117, Typical Impedance 3V: 71 */ 131 QSPI_IP_HF_DRV_STRENGTH_002 = 0x02U, /*!< Typical Impedance for 1.8V: 68, Typical Impedance 3V: 40 */ 132 QSPI_IP_HF_DRV_STRENGTH_003 = 0x03U, /*!< Typical Impedance for 1.8V: 45, Typical Impedance 3V: 27 */ 133 QSPI_IP_HF_DRV_STRENGTH_004 = 0x04U, /*!< Typical Impedance for 1.8V: 34, Typical Impedance 3V: 20 */ 134 QSPI_IP_HF_DRV_STRENGTH_005 = 0x05U, /*!< Typical Impedance for 1.8V: 27, Typical Impedance 3V: 16 */ 135 QSPI_IP_HF_DRV_STRENGTH_006 = 0x06U, /*!< Typical Impedance for 1.8V: 24, Typical Impedance 3V: 14 */ 136 QSPI_IP_HF_DRV_STRENGTH_007 = 0x07U /*!< Typical Impedance for 1.8V: 20, Typical Impedance 3V: 12 */ 137 } Qspi_Ip_HyperflashDrvStrengthType; 138 139 140 /*! 141 * @brief Read latency 142 * 143 */ 144 typedef enum 145 { 146 QSPI_IP_HF_READ_LATENCY_5_CLOCKS = 0U, /*!< Read latency 5 clocks */ 147 QSPI_IP_HF_READ_LATENCY_6_CLOCKS = 1U, /*!< Read latency 6 clocks */ 148 QSPI_IP_HF_READ_LATENCY_7_CLOCKS = 2U, /*!< Read latency 7 clocks */ 149 QSPI_IP_HF_READ_LATENCY_8_CLOCKS = 3U, /*!< Read latency 8 clocks */ 150 QSPI_IP_HF_READ_LATENCY_9_CLOCKS = 4U, /*!< Read latency 9 clocks */ 151 QSPI_IP_HF_READ_LATENCY_10_CLOCKS = 5U, /*!< Read latency 10 clocks */ 152 QSPI_IP_HF_READ_LATENCY_11_CLOCKS = 6U, /*!< Read latency 11 clocks */ 153 QSPI_IP_HF_READ_LATENCY_12_CLOCKS = 7U, /*!< Read latency 12 clocks */ 154 QSPI_IP_HF_READ_LATENCY_13_CLOCKS = 8U, /*!< Read latency 13 clocks */ 155 QSPI_IP_HF_READ_LATENCY_14_CLOCKS = 9U, /*!< Read latency 14 clocks */ 156 QSPI_IP_HF_READ_LATENCY_15_CLOCKS = 10U, /*!< Read latency 15 clocks */ 157 QSPI_IP_HF_READ_LATENCY_16_CLOCKS = 11U /*!< Read latency 16 clocks */ 158 } Qspi_Ip_HyperflashReadLatencyType; 159 160 161 /* ASO entries */ 162 typedef enum 163 { 164 QSPI_IP_HF_PASSWORD_ASO_ENTRY = 0x60, /*!< Password ASO Entry command */ 165 QSPI_IP_HF_PPB_ASO_ENTRY = 0xC0, /*!< PPB ASO Entry command */ 166 QSPI_IP_HF_PPB_LOCK_ASO_ENTRY = 0x50, /*!< PPB Lock ASO Entry command */ 167 QSPI_IP_HF_DYB_ASO_ENTRY = 0xE0, /*!< DYB ASO Entry command */ 168 QSPI_IP_HF_ECC_ASO_ENTRY = 0x75, /*!< ECC ASO Entry command */ 169 QSPI_IP_HF_SSR_ASO_ENTRY = 0x88, /*!< Secure Silicon Region command */ 170 QSPI_IP_HF_CRC_ASO_ENTRY = 0x78, /*!< CRC ASO Entry command */ 171 QSPI_IP_HF_ASPR_ASO_ENTRY = 0x40, /*!< ASP Configuration Register ASO entry command */ 172 QSPI_IP_HF_FLASH_MEMORY_ARRAY = 0x00 /*!< No ASO entry */ 173 } Qspi_Ip_HyperflashAsoEntryCommandsType; 174 175 176 /*! 177 * @brief Sector protection type 178 * 179 */ 180 typedef enum 181 { 182 QSPI_IP_HF_SECTOR_UNLOCKED = 1U, /* Sector is not protected */ 183 QSPI_IP_HF_SECTOR_LOCKED_BY_PPB = 2U, /* Sector is protected by PPB bit */ 184 QSPI_IP_HF_SECTOR_LOCKED_BY_DYB = 3U, /* Sector is protected by DYB bit */ 185 QSPI_IP_HF_SECTOR_LOCKED_BY_PPB_DYB = 4U /* Sector is protected by PPB and DYB bits */ 186 } Qspi_Ip_HyperflashSectorProtectionType; 187 188 189 /******************************************************************************* 190 * Structures 191 ******************************************************************************/ 192 193 /*! 194 * @brief Hyperflash configuration structure 195 * 196 * This structure is used to provide configuration parameters for HyperFlash 197 * at initialization time. 198 */ 199 typedef struct 200 { 201 Qspi_Ip_HyperflashDrvStrengthType outputDriverStrength; /*!< Output driver level of the device */ 202 boolean RWDSLowOnDualError; /*!< Specifies if RWDS will stall upon Dual Error Detect */ 203 boolean secureRegionUnlocked; /*!< If true, the secure silicon region will be locked */ 204 Qspi_Ip_HyperflashReadLatencyType readLatency; /*!< Read latency */ 205 Qspi_Ip_HyperflashParamSectorMapType paramSectorMap; /*!< Parameter sector mapping */ 206 uint32 deviceIdWordAddress; /*!< The word address of the device Id in ASO */ 207 } Qspi_Ip_HyperFlashConfigType; 208 209 210 #ifdef __cplusplus 211 } 212 #endif 213 214 /** @} */ 215 216 #endif /* QSPI_IP_HYPERFLASHTYPES_H */ 217
