1 /*
2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include "cc_pal_mutex.h"
10 #include "cc_pal_abort.h"
11 #include "aes_driver.h"
12 #include "driver_defs.h"
13 #include "cc_hal.h"
14 #include "cc_hal_plat.h"
15 #include "cc_sram_map.h"
16 #include "cc_regs.h"
17 #include "dx_crys_kernel.h"
18 #include "dx_nvm.h"
19 #include "cc_otp_defs.h"
20 #include "mbedtls_cc_mng_int.h"
21 #include "cc_util_pm.h"
22 #include "cc_int_general_defs.h"
23
24 #define SET_ZEROS(buff, size) {\
25 uint32_t i = 0;\
26 for (i = 0; i< size; i++) {\
27 buff[i] = 0x0;\
28 }\
29 }
30
31
32 extern CC_PalMutex CCSymCryptoMutex;
33
34
35 /******************************************************************************
36 * PRIVATE FUNCTIONS
37 ******************************************************************************/
38
39 /* Note: InitAes is private function and it is called only by the driver! */
InitAes(AesContext_t * aesCtx)40 static drvError_t InitAes(AesContext_t *aesCtx)
41 {
42 uint32_t aesCtrl = 0;
43 uint32_t irrVal = 0;
44 cryptoDirection_t dir;
45
46 /* verify user context pointer */
47 if ( aesCtx == NULL ) {
48 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
49 }
50
51 /* verify aes valid mode */
52 switch (aesCtx->mode) {
53 case CIPHER_ECB:
54 case CIPHER_CBC:
55 case CIPHER_CTR:
56 case CIPHER_CBC_MAC:
57 case CIPHER_CMAC:
58 case CIPHER_OFB:
59 break;
60 default:
61 return AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
62 }
63
64 /* verify aes valid dir */
65 if ( (aesCtx->dir != CRYPTO_DIRECTION_ENCRYPT) &&
66 (aesCtx->dir != CRYPTO_DIRECTION_DECRYPT) ) {
67 return AES_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR;
68 }
69
70 /* verify aes valid input addr type */
71 if ( (aesCtx->inputDataAddrType != SRAM_ADDR) &&
72 (aesCtx->inputDataAddrType != DLLI_ADDR) ) {
73 return AES_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR;
74 }
75
76 /* verify aes valid output addr type for ecb, cbc, ctr */
77 if ( (aesCtx->outputDataAddrType != SRAM_ADDR) &&
78 (aesCtx->outputDataAddrType != DLLI_ADDR) ) {
79 return AES_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR;
80 }
81
82 /* make sure sym engines are ready to use */
83 CC_HAL_WAIT_ON_CRYPTO_BUSY();
84
85 /* clear all interrupts before starting the engine */
86 CC_HalClearInterruptBit(0xFFFFFFFFUL);
87
88 /* mask dma interrupts which are not required */
89 irrVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR));
90 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SRAM_TO_DIN_MASK, irrVal, 1);
91 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_SRAM_MASK, irrVal, 1);
92 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, MEM_TO_DIN_MASK, irrVal, 1);
93 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, DOUT_TO_MEM_MASK, irrVal, 1);
94 CC_REG_FLD_SET(HOST_RGF, HOST_IMR, SYM_DMA_COMPLETED_MASK, irrVal, 0);
95 CC_HalMaskInterrupt(irrVal);
96
97 /* configure DIN-AES-DOUT */
98 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, CRYPTO_CTL) ,CONFIG_DIN_AES_DOUT_VAL);
99
100 /* Zero AES_REMAINING_BYTES */
101 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES) ,0);
102
103 /* configure AES direction (in case of CMAC - force only encrypt) */
104 if ((aesCtx->mode == CIPHER_CBC_MAC) || (aesCtx->mode == CIPHER_CMAC))
105 dir = CRYPTO_DIRECTION_ENCRYPT;
106 else
107 dir = aesCtx->dir;
108 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, DEC_KEY0, aesCtrl, dir);
109
110 /* configure AES mode */
111 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, MODE_KEY0, aesCtrl, aesCtx->mode);
112 switch (aesCtx->keySizeId) {
113 case KEY_SIZE_128_BIT:
114 case KEY_SIZE_192_BIT:
115 case KEY_SIZE_256_BIT:
116 /* NK_KEY0 and NK_KEY1 are configured, only NK_KEY0 is in use (no tunneling in cc3x)*/
117 CC_REG_FLD_SET(HOST_RGF, AES_CONTROL, NK_KEY0, aesCtrl, aesCtx->keySizeId);
118 break;
119 default:
120 return AES_DRV_ILLEGAL_KEY_SIZE_ERROR;
121 }
122 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CONTROL) ,aesCtrl);
123
124 /* initiate CMAC sub-keys calculation */
125 if (aesCtx->mode == CIPHER_CMAC) {
126 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CMAC_INIT) ,0x1);
127 }
128
129 return AES_DRV_OK;
130 }
131
LoadAesKey(AesContext_t * aesCtx)132 static drvError_t LoadAesKey(AesContext_t *aesCtx)
133 {
134 uint32_t error = 0;
135 uint32_t isKeyInUse = 0;
136
137 /* verify user context pointer */
138 if ( aesCtx == NULL ) {
139 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
140 }
141
142 switch (aesCtx->cryptoKey) {
143 case USER_KEY:
144 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_0) ,aesCtx->keyBuf[0]);
145 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_1) ,aesCtx->keyBuf[1]);
146 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_2) ,aesCtx->keyBuf[2]);
147 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_3) ,aesCtx->keyBuf[3]);
148 if (aesCtx->keySizeId == KEY_SIZE_192_BIT || aesCtx->keySizeId == KEY_SIZE_256_BIT) {
149 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_4) ,aesCtx->keyBuf[4]);
150 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_5) ,aesCtx->keyBuf[5]);
151 }
152 if (aesCtx->keySizeId == KEY_SIZE_256_BIT)
153 {
154 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_6) ,aesCtx->keyBuf[6]);
155 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_KEY_0_7) ,aesCtx->keyBuf[7]);
156 }
157 break;
158 case RKEK_KEY:
159 /* Verify no integrity error */
160 CC_IS_KEY_ERROR(KDR, error);
161 if (error == CC_TRUE) {
162 return AES_DRV_ILLEGAL_KEY_INTEGRITY_ERROR;
163 }
164 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_CRYPTOKEY_SEL) ,aesCtx->cryptoKey);
165 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_SK), 0x1);
166 break;
167 case KCP_KEY:
168 /* Verify key is in use */
169 CC_IS_OTP_KEY_IN_USE(OEM, KCP, error, isKeyInUse);
170 if ( (error != CC_OK) || (isKeyInUse != CC_TRUE) ) {
171 return AES_DRV_ILLEGAL_KEY_USE_ERROR;
172 }
173
174 /* Verify key is not locked */
175 CC_IS_KEY_LOCKED(KCP, error);
176 if (error == CC_TRUE) {
177 return AES_DRV_ILLEGAL_KEY_LOCK_ERROR;
178 }
179
180 /* Verify no integrity error */
181 CC_IS_KEY_ERROR(PROV, error);
182 if (error == CC_TRUE) {
183 return AES_DRV_ILLEGAL_KEY_INTEGRITY_ERROR;
184 }
185
186 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_CRYPTOKEY_SEL) ,aesCtx->cryptoKey);
187 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_SK), 0x1);
188 break;
189 case KPICV_KEY:
190 /* Verify key is in use */
191 CC_IS_OTP_KEY_IN_USE(MANUFACTURE, KPICV, error, isKeyInUse);
192 if ( (error != CC_OK) || (isKeyInUse != CC_TRUE) ) {
193 return AES_DRV_ILLEGAL_KEY_USE_ERROR;
194 }
195
196 /* Verify key is not locked */
197 CC_IS_KEY_LOCKED(KPICV, error);
198 if (error == CC_TRUE) {
199 return AES_DRV_ILLEGAL_KEY_LOCK_ERROR;
200 }
201
202 /* Verify no integrity error */
203 CC_IS_KEY_ERROR(KPICV, error);
204 if (error == CC_TRUE) {
205 return AES_DRV_ILLEGAL_KEY_INTEGRITY_ERROR;
206 }
207 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_CRYPTOKEY_SEL) ,aesCtx->cryptoKey);
208 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_SK), 0x1);
209 break;
210 case RTL_KEY:
211 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_CRYPTOKEY_SEL) ,1);
212 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_SK), 0x1);
213 break;
214 default:
215 return AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
216
217 }
218
219 /* For all HW keys, check if fatal error bit is set to ON */
220 if (aesCtx->cryptoKey != USER_KEY) {
221 CC_IS_FATAL_ERR_ON(error);
222 if (error == CC_TRUE) {
223 return AES_DRV_ILLEGAL_FATAL_ERR_BIT_ERROR;
224 }
225 }
226 return AES_DRV_OK;
227 }
228
LoadIVState(AesContext_t * aesCtx)229 static drvError_t LoadIVState(AesContext_t *aesCtx)
230 {
231 /* verify user context pointer */
232 if ( aesCtx == NULL ) {
233 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
234 }
235
236 /* write the initial counter value according to mode */
237 switch (aesCtx->mode) {
238 case(CIPHER_CTR):
239 case(CIPHER_OFB):
240 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_0) ,aesCtx->ivBuf[0]);
241 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_1) ,aesCtx->ivBuf[1]);
242 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_2) ,aesCtx->ivBuf[2]);
243 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_3) ,aesCtx->ivBuf[3]);
244 break;
245 case(CIPHER_CMAC):
246 case(CIPHER_CBC):
247 case(CIPHER_CBC_MAC):
248 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_0) ,aesCtx->ivBuf[0]);
249 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_1) ,aesCtx->ivBuf[1]);
250 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_2) ,aesCtx->ivBuf[2]);
251 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_3) ,aesCtx->ivBuf[3]);
252 case(CIPHER_ECB):
253 break;
254 default:
255 return AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
256 }
257
258 return AES_DRV_OK;
259 }
260
StoreIVState(AesContext_t * aesCtx)261 static drvError_t StoreIVState(AesContext_t *aesCtx)
262 {
263 /* verify user context pointer */
264 if ( aesCtx == NULL ) {
265 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
266 }
267
268 /* write the initial counter value according to mode */
269 switch (aesCtx->mode) {
270 case(CIPHER_CTR):
271 case(CIPHER_OFB):
272 aesCtx->ivBuf[0] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_0));
273 aesCtx->ivBuf[1] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_1));
274 aesCtx->ivBuf[2] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_2));
275 aesCtx->ivBuf[3] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CTR_0_3));
276 break;
277 case(CIPHER_CMAC):
278 case(CIPHER_CBC):
279 case(CIPHER_CBC_MAC):
280 aesCtx->ivBuf[0] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_0));
281 aesCtx->ivBuf[1] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_1));
282 aesCtx->ivBuf[2] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_2));
283 aesCtx->ivBuf[3] = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_IV_0_3));
284 case(CIPHER_ECB):
285 break;
286 default:
287 return AES_DRV_ILLEGAL_OPERATION_MODE_ERROR;
288 }
289
290 return AES_DRV_OK;
291
292 }
293
finalizeCmac(AesContext_t * aesCtx,CCBuffInfo_t * pInputBuffInfo,uint32_t blockSize)294 static drvError_t finalizeCmac(AesContext_t *aesCtx, CCBuffInfo_t *pInputBuffInfo, uint32_t blockSize)
295 {
296 drvError_t drvRc = AES_DRV_OK;
297 uint32_t irrVal = 0;
298 uint32_t regVal = 0;
299 uint32_t inputDataAddr;
300
301 /* check input parameters */
302 if (pInputBuffInfo == NULL) {
303 return AES_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR;
304 }
305
306
307 if (((aesCtx->inputDataAddrType == SRAM_ADDR) && (blockSize >= CC_SRAM_MAX_SIZE)) ||
308 ((aesCtx->inputDataAddrType == DLLI_ADDR) && (blockSize >= DLLI_MAX_BUFF_SIZE))) {
309 return AES_DRV_ILLEGAL_MEM_SIZE_ERROR;
310 }
311
312 // In ARM CryptoCell 3xx we can't have last block == 0, since as NIST 800-38B says:
313 // "the final block in the partition is replaced with the exclusive-OR of the final block with the first subkey"
314 // In ARM CryptoCell 3xx we enable/disable the AES clock for every block, so HW doesn't keep the first key and nither does the driver.
315 // so we dont have the first key and we cant xor with it.
316 if ((blockSize == 0) && (aesCtx->dataBlockType != FIRST_BLOCK)) {
317 return AES_DRV_ILLEGAL_MEM_SIZE_ERROR;
318 }
319
320 /* lock mutex for more aes hw operation */
321 drvRc = CC_PalMutexLock(&CCSymCryptoMutex, CC_INFINITE);
322 if (drvRc != 0) {
323 CC_PalAbort("Fail to acquire mutex\n");
324 }
325
326 /* increase CC counter at the beginning of each operation */
327 drvRc = CC_IS_WAKE;
328 if (drvRc != 0) {
329 CC_PalAbort("Fail to increase PM counter\n");
330 }
331
332 /* enable clock */
333 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_ENABLE);
334 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_ENABLE);
335
336 drvRc = InitAes(aesCtx);
337 if (drvRc != AES_DRV_OK) {
338 goto FinishExit;
339 }
340
341 /* load AES key and iv length and digest */
342 drvRc = LoadAesKey(aesCtx);
343 if (drvRc != 0){
344 goto FinishExit;
345 }
346
347 drvRc = LoadIVState(aesCtx);
348 if (drvRc != 0){
349 goto FinishExit;
350 }
351
352 /* initiate CMAC sub-keys calculation */
353 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CMAC_INIT) ,0x1);
354 /* set the remaining bytes */
355 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_REMAINING_BYTES) ,blockSize);
356
357 inputDataAddr = pInputBuffInfo->dataBuffAddr;
358
359 /* configure the HW with the correct data buffer attributes (secure/non-secure) */
360 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_READ_HNONSEC, regVal, pInputBuffInfo->dataBuffNs);
361 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AHBM_HNONSEC) ,regVal);
362
363
364 if (blockSize == 0) {
365 if (aesCtx->dataBlockType == FIRST_BLOCK) {
366 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CMAC_SIZE0_KICK) ,0x1);
367 }
368 } else {
369 /* configure source address and size, set the relevant IRR bit */
370 if (aesCtx->inputDataAddrType == DLLI_ADDR) {
371 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD0) ,inputDataAddr);
372 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD1) ,blockSize);
373 } else {
374 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_SRC_ADDR) ,inputDataAddr);
375 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DIN_SRAM_BYTES_LEN) ,blockSize);
376 }
377 /* set dma completion bit in irr */
378 CC_REG_FLD_SET(HOST_RGF, HOST_IRR, SYM_DMA_COMPLETED, irrVal, 1);
379 drvRc = CC_HalWaitInterrupt(irrVal);
380 if (drvRc != 0){
381 goto FinishExit;
382 }
383 }
384
385 /* get machine state */
386 StoreIVState(aesCtx);
387 /* Note: the upper layer should copy the mac result to outputDataAddr using PAL */
388
389 FinishExit:
390 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_DISABLE);
391 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_DISABLE);
392
393 /* decrease CC counter at the end of each operation */
394 if (CC_IS_IDLE != 0) {
395 CC_PalAbort("Fail to decrease PM counter\n");
396 }
397
398 /* release mutex */
399 if (CC_PalMutexUnlock(&CCSymCryptoMutex) != 0) {
400 CC_PalAbort("Fail to release mutex\n");
401 }
402
403 return drvRc;
404 }
405
406
407
408 /******************************************************************************
409 * PUBLIC FUNCTIONS
410 ******************************************************************************/
411
ProcessAesDrv(AesContext_t * aesCtx,CCBuffInfo_t * pInputBuffInfo,CCBuffInfo_t * pOutputBuffInfo,uint32_t blockSize)412 drvError_t ProcessAesDrv(AesContext_t *aesCtx, CCBuffInfo_t *pInputBuffInfo, CCBuffInfo_t *pOutputBuffInfo, uint32_t blockSize)
413 {
414 uint32_t irrVal = 0;
415 drvError_t drvRc = AES_DRV_OK;
416 uint32_t regVal = 0;
417 uint32_t inputDataAddr, outputDataAddr;
418
419 /* check input parameters */
420 if ( (pInputBuffInfo == NULL) || (pOutputBuffInfo == NULL)) {
421 return AES_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR;
422 }
423
424 /* verify user context pointer */
425 if ( aesCtx == NULL ) {
426 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
427 }
428 if (((aesCtx->inputDataAddrType == SRAM_ADDR) && (blockSize >= CC_SRAM_MAX_SIZE)) ||
429 ((aesCtx->inputDataAddrType == DLLI_ADDR) && (blockSize >= DLLI_MAX_BUFF_SIZE))) {
430 return AES_DRV_ILLEGAL_MEM_SIZE_ERROR;
431 }
432
433 /* lock mutex for more aes hw operation */
434 drvRc = CC_PalMutexLock(&CCSymCryptoMutex, CC_INFINITE);
435 if (drvRc != 0) {
436 CC_PalAbort("Fail to acquire mutex\n");
437 }
438
439 /* increase CC counter at the beginning of each operation */
440 drvRc = CC_IS_WAKE;
441 if (drvRc != 0) {
442 CC_PalAbort("Fail to increase PM counter\n");
443 }
444
445 /* enable clock */
446 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_ENABLE);
447 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_ENABLE);
448
449 drvRc = InitAes(aesCtx);
450 if (drvRc != AES_DRV_OK) {
451 goto ProcessExit;
452 }
453
454 drvRc = LoadAesKey(aesCtx);
455 if (drvRc != AES_DRV_OK){
456 goto ProcessExit;
457 }
458
459 drvRc = LoadIVState(aesCtx);
460 if (drvRc != AES_DRV_OK) {
461 goto ProcessExit;
462 }
463
464 inputDataAddr = pInputBuffInfo->dataBuffAddr;
465 outputDataAddr = pOutputBuffInfo->dataBuffAddr;
466
467 /* configure the HW with the correct data buffer attributes (secure/non-secure) */
468 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_READ_HNONSEC, regVal, pInputBuffInfo->dataBuffNs);
469 CC_REG_FLD_SET(HOST_RGF, AHBM_HNONSEC, AHB_WRITE_HNONSEC, regVal, pOutputBuffInfo->dataBuffNs);
470 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AHBM_HNONSEC) ,regVal);
471
472 if ((aesCtx->mode != CIPHER_CBC_MAC) && (aesCtx->mode != CIPHER_CMAC)) {
473 /* configure destination address and size in case of ecb or cbc or ctr */
474 /* and set dout bit in irr */
475 if (aesCtx->outputDataAddrType == DLLI_ADDR) {
476 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD0) ,outputDataAddr);
477 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DST_LLI_WORD1) ,blockSize);
478 } else {
479 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DEST_ADDR) ,outputDataAddr);
480 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DOUT_SRAM_BYTES_LEN) ,blockSize);
481 }
482 }
483
484 /* configure source address and size */
485 if (aesCtx->inputDataAddrType == DLLI_ADDR) {
486 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD0) ,inputDataAddr);
487 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRC_LLI_WORD1) ,blockSize);
488 } else {
489 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_SRC_ADDR) ,inputDataAddr);
490 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DIN_SRAM_BYTES_LEN) ,blockSize);
491 }
492
493 /* set dma completion bit in irr */
494 CC_REG_FLD_SET(HOST_RGF, HOST_IRR, SYM_DMA_COMPLETED, irrVal, 1);
495 drvRc = CC_HalWaitInterrupt(irrVal);
496 if (drvRc != 0){
497 goto ProcessExit;
498 }
499
500 /* get machine state */
501 StoreIVState(aesCtx);
502
503 /* at least one block of data processed */
504 aesCtx->dataBlockType = MIDDLE_BLOCK;
505
506 ProcessExit:
507 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, AES_CLK_ENABLE) ,SET_CLOCK_DISABLE);
508 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, DMA_CLK_ENABLE) ,SET_CLOCK_DISABLE);
509
510 /* decrease CC counter at the end of each operation */
511 if (CC_IS_IDLE != 0) {
512 CC_PalAbort("Fail to decrease PM counter\n");
513 }
514
515 /* release mutex */
516 if (CC_PalMutexUnlock(&CCSymCryptoMutex) != 0) {
517 CC_PalAbort("Fail to release mutex\n");
518 }
519
520 return drvRc;
521 }
522
523
FinishAesDrv(AesContext_t * aesCtx,CCBuffInfo_t * pInputBuffInfo,CCBuffInfo_t * pOutputBuffInfo,uint32_t blockSize)524 drvError_t FinishAesDrv(AesContext_t *aesCtx, CCBuffInfo_t *pInputBuffInfo, CCBuffInfo_t *pOutputBuffInfo, uint32_t blockSize)
525 {
526 drvError_t drvRc = AES_DRV_OK;
527
528 /* check input parameters */
529 if ( (pInputBuffInfo == NULL) || (pOutputBuffInfo == NULL)) {
530 return AES_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR;
531 }
532
533 /* verify user context pointer */
534 if ( aesCtx == NULL ) {
535 return AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR;
536 }
537
538 switch (aesCtx->mode) {
539 case CIPHER_CMAC:
540 drvRc = finalizeCmac(aesCtx, pInputBuffInfo, blockSize);
541 break;
542 default:
543 if (blockSize == 0) {
544 if ((aesCtx->mode == CIPHER_CBC_MAC) && (aesCtx->dataBlockType == FIRST_BLOCK)) { // according to ISO/IEC 9797-1 sec 6.1.3
545 blockSize = sizeof(aesCtx->tempBuff);
546 SET_ZEROS(aesCtx->tempBuff, blockSize);
547 pInputBuffInfo->dataBuffAddr = (uint32_t)aesCtx->tempBuff;
548 } else
549 return AES_DRV_OK;
550 }
551 drvRc = ProcessAesDrv(aesCtx, pInputBuffInfo, pOutputBuffInfo, blockSize);
552 }
553
554 return drvRc;
555 }
556
557
558
559
560
