1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8 #ifndef RSA_HWDEFS_H 9 #define RSA_HWDEFS_H 10 11 /* 12 * All the includes that are needed for code using this module to 13 * compile correctly should be #included here. 14 */ 15 #include "secureboot_general_hwdefs.h" 16 #include "cc_pka_hw_plat_defs.h" 17 18 #ifdef __cplusplus 19 extern "C" 20 { 21 #endif 22 23 24 /************************ Defines ******************************/ 25 26 /* PKA big word size in bits */ 27 #define RSA_PKA_BIG_WORD_SIZE_IN_BITS CC_PKA_WORD_SIZE_IN_BITS 28 #define RSA_PKA_BIG_WORD_SIZE_IN_BYTES (RSA_PKA_BIG_WORD_SIZE_IN_BITS/8) 29 #define RSA_PKA_BIG_WORD_SIZE_IN_32_BIT_WORDS (RSA_PKA_BIG_WORD_SIZE_IN_BITS/32) 30 31 #define RSA_PKA_EXTRA_BITS PKA_EXTRA_BITS 32 33 /* PKA max count of SRAM registers: */ 34 #define RSA_HW_PKI_PKA_MAX_COUNT_OF_PHYS_MEM_REGS PKA_MAX_COUNT_OF_PHYS_MEM_REGS 35 36 /* The maximal size of allowed PKA physical registers memory including tables */ 37 #define RSA_PKA_MAX_REGS_MEM_SIZE_BYTES (6 * 1024) 38 39 /* SRAM definitions */ 40 #define RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR g_SramPkaAddr 41 42 /* The maximal count of allowed sizes of PKA operands or register-variables */ 43 #define RSA_PKA_MAX_COUNT_OF_REGS_SIZES 8 /*PKA_MAX_COUNT_OF_REGS_SIZES */ 44 #define RSA_PKA_MAX_COUNT_OF_ADDITIONAL_REGS 10 45 #define RSA_PKA_SRAM_REGS_MEM_OFFSET_WORDS RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR 46 47 48 /* PKA OPCODE register fields positions (low bit position) */ 49 #define RSA_HW_PKI_PKA_OPCODE_TAG_POS 0 50 #define RSA_HW_PKI_PKA_OPCODE_RESULT_POS 6 51 #define RSA_HW_PKI_PKA_OPCODE_R_DISCARD_POS 11 52 #define RSA_HW_PKI_PKA_OPCODE_OPERAND_2_POS 12 53 #define RSA_HW_PKI_PKA_OPCODE_OPERAND_2_IMMED_POS 17 54 #define RSA_HW_PKI_PKA_OPCODE_OPERAND_1_POS 18 55 #define RSA_HW_PKI_PKA_OPCODE_OPERAND_1_IMMED_POS 23 56 #define RSA_HW_PKI_PKA_OPCODE_LEN_POS 24 57 #define RSA_HW_PKI_PKA_OPCODE_OPERATION_ID_POS 27 58 59 60 /* PKA N_NP_T0_T1 register fields positions (low bit position) */ 61 #define RSA_HW_PKI_PKA_N_NP_T0_T1_REG_N_POS DX_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_BIT_SHIFT 62 #define RSA_HW_PKI_PKA_N_NP_T0_T1_REG_NP_POS DX_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_BIT_SHIFT 63 #define RSA_HW_PKI_PKA_N_NP_T0_T1_REG_T0_POS DX_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_BIT_SHIFT 64 #define RSA_HW_PKI_PKA_N_NP_T0_T1_REG_T1_POS DX_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_BIT_SHIFT 65 66 /* PKA N_NP_T0_T1 register default (reset) value: N=0, NP=1, T0=30, T1=31 */ 67 #define PKA_N 0UL 68 #define PKA_NP 1UL 69 #define PKA_T0 30UL 70 #define PKA_T1 31UL 71 #define RSA_HW_PKI_PKA_N_NP_T0_T1_REG_DEFAULT_VAL ( PKA_N << RSA_HW_PKI_PKA_N_NP_T0_T1_REG_N_POS | \ 72 PKA_NP << RSA_HW_PKI_PKA_N_NP_T0_T1_REG_NP_POS | \ 73 PKA_T0 << RSA_HW_PKI_PKA_N_NP_T0_T1_REG_T0_POS | \ 74 PKA_T1 << RSA_HW_PKI_PKA_N_NP_T0_T1_REG_T1_POS ) 75 76 /* PKA control values */ 77 #define RSA_PKA_PIPE_READY 1 78 #define RSA_PKA_OP_DONE 1 79 #define RSA_PKA_SW_REST 1 80 81 /* Machine Opcodes definitions (according to HW CRS ) */ 82 #define PkaSepDone 0x00 83 #define PkaAdd 0x04 84 #define PkaAddIm 0x04 85 #define PkaSub 0x05 86 #define PkaSubIm 0x05 87 #define PkaNeg 0x05 88 #define PkaModAdd 0x06 89 #define PkaModAddIm 0x06 90 #define PkaModSub 0x07 91 #define PkaModSubIm 0x07 92 #define PkaModNeg 0x07 93 #define PkaAND 0x08 94 #define PkaTest0 0x08 95 #define PkaClr0 0x08 96 #define PkaClr 0x08 97 #define PkaOR 0x09 98 #define PkaCopy 0x09 99 #define PkaSetBit0 0x09 100 #define PkaXOR 0x0A 101 #define PkaFlip0 0x0A 102 #define PkaInvertBits 0x0A 103 #define PkaCompare 0x0A 104 #define PkaSHR0 0x0C 105 #define PkaSHR1 0x0D 106 #define PkaSHL0 0x0E 107 #define PkaSHL1 0x0F 108 #define PkaLMul 0x10 109 #define PkaModMul 0x11 110 #define PkaModMulNR 0x12 111 #define PkaModExp 0x13 112 #define PkaDiv 0x14 113 #define PkaModInv 0x15 114 #define PkaHMul 0x17 115 #define PkaModMulAcc 0x18 116 #define PkaModMulAccN 0x19 117 #define PkaSepInt 0x1A 118 #define PkaReduce 0x1B 119 120 #define PKA_MAX_OPCODE 0x1B 121 122 123 /* ********************** MACROS ******************************* */ 124 125 126 /* Full register (operation) size including extra bits + one PKA-word (64 or * 127 * 128 bits), rounded up to PKA words. */ 128 #define GET_FULL_OP_SIZE_PKA_WORDS(opSizeInBits) (((opSizeInBits)/RSA_PKA_BIG_WORD_SIZE_IN_BITS + (((opSizeInBits) & (RSA_PKA_BIG_WORD_SIZE_IN_BITS-1)) > 0)) + 1) 129 130 /*************************************************************/ 131 /* Macros for waiting PKA machine ready states */ 132 /*************************************************************/ 133 134 /* defining a macro for waiting to the PKA_PIPE_READY */ 135 #define RSA_PKA_WAIT_ON_PKA_PIPE_READY(VirtualHwBaseAddr) \ 136 do \ 137 { \ 138 volatile uint32_t output_reg_val; \ 139 do \ 140 { \ 141 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_PIPE_RDY), output_reg_val ); \ 142 }while( (output_reg_val & 0x01) != RSA_PKA_PIPE_READY ); \ 143 }while(0) 144 145 /* defining a macro for waiting to the PKA_OP_DONE */ 146 #define RSA_PKA_WAIT_ON_PKA_DONE(VirtualHwBaseAddr) \ 147 do \ 148 { \ 149 volatile uint32_t output_reg_val; \ 150 do \ 151 { \ 152 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_DONE), output_reg_val); \ 153 }while( (output_reg_val & 0x01) != RSA_PKA_OP_DONE ); \ 154 }while(0) 155 156 /******************************************************************/ 157 /* Macros for setting and reading sizes from PKA regsSizesTable */ 158 /******************************************************************/ 159 160 161 /* ReadRegSizeInTable: Readss the size from regsSizesTable entry */ 162 #define RSA_PKA_ReadRegSize(SizeBits, EntryNum, VirtualHwBaseAddr) \ 163 RSA_PKA_WAIT_ON_PKA_DONE( VirtualHwBaseAddr ); \ 164 SB_HAL_READ_REGISTER( (SB_REG_ADDR(VirtualHwBaseAddr,PKA_L0) + 4*(EntryNum)), \ 165 (SizeBits) ) 166 167 /******************************************************************/ 168 /* Macros for setting and reading addresses of PKA data registers */ 169 /******************************************************************/ 170 171 /*The following macros are used for setting and reading the data registers addresses in mapping table.*/ 172 173 /* GetRegAddress: Returns the physical address of register VirtReg from mapping table */ 174 #define RSA_PKA_GetRegAddress(VirtReg, VirtualHwBaseAddr) \ 175 ( *((volatile uint32_t*)(SB_REG_ADDR(VirtualHwBaseAddr,MEMORY_MAP0) + 4*(VirtReg))) ) 176 177 /******************************************************************/ 178 /* Macros for setting Full PKI opcode */ 179 /******************************************************************/ 180 181 #define RSA_PKA_FullOpCode( Opcode,LenID,IsAImmed,OpA,IsBImmed,OpB,ResDiscard,Res,Tag ) \ 182 ( ((Opcode)) << RSA_HW_PKI_PKA_OPCODE_OPERATION_ID_POS | \ 183 ((LenID)) << RSA_HW_PKI_PKA_OPCODE_LEN_POS | \ 184 ((IsAImmed)) << RSA_HW_PKI_PKA_OPCODE_OPERAND_1_IMMED_POS | \ 185 ((OpA)) << RSA_HW_PKI_PKA_OPCODE_OPERAND_1_POS | \ 186 ((IsBImmed)) << RSA_HW_PKI_PKA_OPCODE_OPERAND_2_IMMED_POS | \ 187 ((OpB)) << RSA_HW_PKI_PKA_OPCODE_OPERAND_2_POS | \ 188 ((ResDiscard)) << RSA_HW_PKI_PKA_OPCODE_R_DISCARD_POS | \ 189 ((Res)) << RSA_HW_PKI_PKA_OPCODE_RESULT_POS | \ 190 ((Tag)) << RSA_HW_PKI_PKA_OPCODE_TAG_POS ) 191 192 /******************************************************************/ 193 /* Macros for reading and loading PKA memory data */ 194 /******************************************************************/ 195 196 /* MACRO DEFINITIONS FOR WORKING WITH INDIRECT ACCESS TO SRAM PKA DATA REGISTERS */ 197 198 /*These registers not included in the HW_CC definitions because they are HOST registers */ 199 #ifdef CC_SB_INDIRECT_SRAM_ACCESS 200 /* MACRO DEFINITIONS FOR WORKING WITH INDIRECT ACCESS TO SRAM PKA DATA REGISTERS */ 201 202 #define RSA_PKA_SRAM_WRITE_CLR(VirtualHwBaseAddr, SizeWords) \ 203 for(; ii < 4*(((SizeWords)+3)/4) ; ii++) { \ 204 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), 0); \ 205 } 206 207 #ifndef BIG__ENDIAN 208 /* macro to load a value to SRAM with 32-bit access */ 209 #define RSA_HW_PKI_HW_LOAD_VALUE_TO_PKA_MEM(VirtualHwBaseAddr, Addr, Val) \ 210 do \ 211 { \ 212 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_ADDR), ((Addr)+ RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 213 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), (Val)); \ 214 }while(0) 215 #else 216 #define RSA_HW_PKI_HW_LOAD_VALUE_TO_PKA_MEM(VirtualHwBaseAddr, Addr, Val) \ 217 do \ 218 { \ 219 uint32_t tempVal; \ 220 UTIL_ReverseMemCopy((uint8_t*)&tempVal , (uint8_t*)&Val , sizeof(uint32_t) ); \ 221 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_ADDR), ((Addr)+ RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 222 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), (tempVal)); \ 223 }while(0) 224 #endif 225 226 #ifndef BIG__ENDIAN 227 /* macro to load block to SRAM memory */ 228 #define RSA_HW_PKI_HW_LOAD_BLOCK_TO_PKA_MEM(VirtualHwBaseAddr, Addr, ptr, SizeWords) \ 229 do \ 230 { \ 231 uint32_t ii; \ 232 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_ADDR), ((Addr)+RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 233 for(ii = 0; ii < (SizeWords); ii++) \ 234 { \ 235 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), ((uint32_t*)(ptr))[ii]); \ 236 } \ 237 RSA_PKA_SRAM_WRITE_CLR(VirtualHwBaseAddr, SizeWords) \ 238 }while(0) 239 /* defining a macro to load a block to the PKA data memory */ 240 241 #else 242 #define RSA_HW_PKI_HW_LOAD_BLOCK_TO_PKA_MEM(VirtualHwBaseAddr, Addr, ptr, SizeWords) \ 243 do \ 244 { \ 245 uint32_t ii; \ 246 uint32_t tempWord; \ 247 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_ADDR), ((Addr)+RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 248 for(ii = 0; ii < (SizeWords); ii++) \ 249 { \ 250 UTIL_ReverseMemCopy((uint8_t*)&tempWord , (uint8_t*)&(ptr)[ii] , sizeof(uint32_t) ); \ 251 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), tempWord); \ 252 } \ 253 RSA_PKA_SRAM_WRITE_CLR(VirtualHwBaseAddr, SizeWords) \ 254 }while(0) 255 #endif 256 257 /* macro to clear PKA memory: Addr must be alighned to PKA_WORD size */ 258 #define RSA_HW_PKI_HW_CLEAR_PKA_MEM(VirtualHwBaseAddr, Addr, SizeWords) \ 259 do \ 260 { \ 261 uint32_t ii; \ 262 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_ADDR), (Addr)); \ 263 for( ii = 0; ii < (uint32_t)(SizeWords); ii++ ) \ 264 { \ 265 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_WDATA), 0x0UL ); \ 266 }\ 267 RSA_PKA_SRAM_WRITE_CLR(VirtualHwBaseAddr, (SizeWords)); \ 268 }while(0) 269 270 #ifndef BIG__ENDIAN 271 /* macro to read a value from the PKA data memory */ 272 #define RSA_HW_PKI_HW_READ_VALUE_FROM_PKA_MEM(VirtualHwBaseAddr, Addr, Val) \ 273 do \ 274 { \ 275 volatile uint32_t dummy; \ 276 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RADDR), ((Addr)+ RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 277 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RDATA), (dummy)); \ 278 (Val) = dummy; \ 279 }while(0) 280 #else 281 #define RSA_HW_PKI_HW_READ_VALUE_FROM_PKA_MEM(VirtualHwBaseAddr, Addr, Val) \ 282 do \ 283 { \ 284 volatile uint32_t dummy; \ 285 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RADDR), ((Addr)+ RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)); \ 286 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RDATA), (dummy)); \ 287 (Val) = dummy; \ 288 UTIL_ReverseBuff((uint8_t*)&Val , sizeof(uint32_t) ); \ 289 }while(0) 290 #endif 291 292 #ifndef BIG__ENDIAN 293 /* defining a macro to read a block from the PKA data memory */ 294 #define RSA_HW_PKI_HW_READ_BLOCK_FROM_PKA_MEM(VirtualHwBaseAddr, Addr, ptr, SizeWords) \ 295 do \ 296 { \ 297 uint32_t ii; \ 298 volatile uint32_t dummy; \ 299 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RADDR), (Addr)); \ 300 for(ii = 0; ii < (SizeWords); ii++) \ 301 { \ 302 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RDATA), (dummy));\ 303 ((uint32_t*)(ptr))[ii] = (dummy); \ 304 } \ 305 }while(0) 306 #else 307 #define RSA_HW_PKI_HW_READ_BLOCK_FROM_PKA_MEM(VirtualHwBaseAddr, Addr, ptr, SizeWords) \ 308 do \ 309 { \ 310 uint32_t ii; \ 311 volatile uint32_t dummy; \ 312 SB_HAL_WRITE_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RADDR), (Addr)); \ 313 for(ii = 0; ii < (SizeWords); ii++) \ 314 { \ 315 SB_HAL_READ_REGISTER( SB_REG_ADDR(VirtualHwBaseAddr, PKA_SRAM_RDATA), (dummy));\ 316 ((uint32_t*)(ptr))[ii] = (dummy); \ 317 UTIL_ReverseBuff((uint8_t*)&(ptr)[ii] , sizeof(uint32_t) ); \ 318 } \ 319 }while(0) 320 #endif 321 322 #else //CC_SB_INDIRECT_SRAM_ACCESS=0 => direct access 323 /* MACRO DEFINITIONS FOR WORKING WITH INDIRECT ACCESS TO SRAM PKA DATA REGISTERS */ 324 325 /*These registers not included in the HW_CC definitions because they are HOST registers */ 326 327 /* defining a macro to load a value to the PKA data memory */ 328 #define RSA_HW_PKI_HW_LOAD_VALUE_TO_PKA_MEM( VirtualHwBaseAddr , Addr , Val ) \ 329 do \ 330 { \ 331 *(uint32_t*)(((Addr) + RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR)) = (uint32_t)Val; \ 332 }while(0) 333 334 335 /* defining a macro to load a block to the PKA data memory */ 336 #define RSA_HW_PKI_HW_LOAD_BLOCK_TO_PKA_MEM( VirtualHwBaseAddr , Addr , ptr , SizeWords ) \ 337 do \ 338 { \ 339 UTIL_MemCopy((uint8_t*)((Addr) + RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR),(uint8_t*)(ptr),(SizeWords)*sizeof(uint32_t)); \ 340 }while(0) 341 342 343 /* defining a macro to clear PKA data memory */ 344 #define RSA_HW_PKI_HW_CLEAR_PKA_MEM( VirtualHwBaseAddr , Addr , SizeWords ) \ 345 do \ 346 { \ 347 UTIL_MemSet((uint8_t*)((Addr) + RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR),0x0,(SizeWords)*sizeof(uint32_t)); \ 348 }while(0) 349 350 351 /* defining a macro to read a value from the PKA data memory */ 352 #define RSA_HW_PKI_HW_READ_VALUE_FROM_PKA_MEM( VirtualHwBaseAddr , Addr , Val ) \ 353 do \ 354 { \ 355 Val = *(uint32_t*)((Addr) + RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR); \ 356 }while(0) 357 358 359 /* defining a macro to read a block from the PKA data memory */ 360 #define RSA_HW_PKI_HW_READ_BLOCK_FROM_PKA_MEM( VirtualHwBaseAddr , Addr , ptr , SizeWords ) \ 361 do \ 362 { \ 363 UTIL_MemCopy((uint8_t*)(ptr),(uint8_t*)((Addr) + RSA_HW_PKI_PKA_DATA_REGS_MEMORY_OFFSET_ADDR),(SizeWords)*sizeof(uint32_t)); \ 364 }while(0) 365 366 #endif //CC_SB_INDIRECT_SRAM_ACCESS 367 368 369 /************************ Defines ******************************/ 370 371 /* ********************** Macros ******************************* */ 372 373 /************************ Enums ********************************/ 374 375 #ifdef __cplusplus 376 } 377 #endif 378 379 #endif 380 381 382
