1 /** 2 * \file 3 * 4 * \brief Component description for PICOUART 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_PICOUART_COMPONENT_ 30 #define _SAM4L_PICOUART_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PICOUART */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_PICOUART Pico UART */ 36 /*@{*/ 37 38 #define PICOUART_I8403 39 #define REV_PICOUART 0x101 40 41 /* -------- PICOUART_CR : (PICOUART Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 Enable */ 46 uint32_t DIS:1; /*!< bit: 1 Disable */ 47 uint32_t :30; /*!< bit: 2..31 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } PICOUART_CR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define PICOUART_CR_OFFSET 0x00 /**< \brief (PICOUART_CR offset) Control Register */ 54 #define PICOUART_CR_RESETVALUE _U_(0x00000000); /**< \brief (PICOUART_CR reset_value) Control Register */ 55 56 #define PICOUART_CR_EN_Pos 0 /**< \brief (PICOUART_CR) Enable */ 57 #define PICOUART_CR_EN (_U_(0x1) << PICOUART_CR_EN_Pos) 58 #define PICOUART_CR_DIS_Pos 1 /**< \brief (PICOUART_CR) Disable */ 59 #define PICOUART_CR_DIS (_U_(0x1) << PICOUART_CR_DIS_Pos) 60 #define PICOUART_CR_MASK _U_(0x00000003) /**< \brief (PICOUART_CR) MASK Register */ 61 62 /* -------- PICOUART_CFG : (PICOUART Offset: 0x04) (R/W 32) Configuration Register -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint32_t SOURCE:2; /*!< bit: 0.. 1 Source Enable Mode */ 67 uint32_t ACTION:1; /*!< bit: 2 Action to perform */ 68 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 69 uint32_t MATCH:8; /*!< bit: 8..15 Data Match */ 70 uint32_t :16; /*!< bit: 16..31 Reserved */ 71 } bit; /*!< Structure used for bit access */ 72 uint32_t reg; /*!< Type used for register access */ 73 } PICOUART_CFG_Type; 74 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 #define PICOUART_CFG_OFFSET 0x04 /**< \brief (PICOUART_CFG offset) Configuration Register */ 77 #define PICOUART_CFG_RESETVALUE _U_(0x00000000); /**< \brief (PICOUART_CFG reset_value) Configuration Register */ 78 79 #define PICOUART_CFG_SOURCE_Pos 0 /**< \brief (PICOUART_CFG) Source Enable Mode */ 80 #define PICOUART_CFG_SOURCE_Msk (_U_(0x3) << PICOUART_CFG_SOURCE_Pos) 81 #define PICOUART_CFG_SOURCE(value) (PICOUART_CFG_SOURCE_Msk & ((value) << PICOUART_CFG_SOURCE_Pos)) 82 #define PICOUART_CFG_ACTION_Pos 2 /**< \brief (PICOUART_CFG) Action to perform */ 83 #define PICOUART_CFG_ACTION (_U_(0x1) << PICOUART_CFG_ACTION_Pos) 84 #define PICOUART_CFG_MATCH_Pos 8 /**< \brief (PICOUART_CFG) Data Match */ 85 #define PICOUART_CFG_MATCH_Msk (_U_(0xFF) << PICOUART_CFG_MATCH_Pos) 86 #define PICOUART_CFG_MATCH(value) (PICOUART_CFG_MATCH_Msk & ((value) << PICOUART_CFG_MATCH_Pos)) 87 #define PICOUART_CFG_MASK _U_(0x0000FF07) /**< \brief (PICOUART_CFG) MASK Register */ 88 89 /* -------- PICOUART_SR : (PICOUART Offset: 0x08) (R/ 32) Status Register -------- */ 90 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 91 typedef union { 92 struct { 93 uint32_t EN:1; /*!< bit: 0 Enable Interrupt Status */ 94 uint32_t DRDY:1; /*!< bit: 1 Data Ready Interrupt Status */ 95 uint32_t :30; /*!< bit: 2..31 Reserved */ 96 } bit; /*!< Structure used for bit access */ 97 uint32_t reg; /*!< Type used for register access */ 98 } PICOUART_SR_Type; 99 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 100 101 #define PICOUART_SR_OFFSET 0x08 /**< \brief (PICOUART_SR offset) Status Register */ 102 #define PICOUART_SR_RESETVALUE _U_(0x00000000); /**< \brief (PICOUART_SR reset_value) Status Register */ 103 104 #define PICOUART_SR_EN_Pos 0 /**< \brief (PICOUART_SR) Enable Interrupt Status */ 105 #define PICOUART_SR_EN (_U_(0x1) << PICOUART_SR_EN_Pos) 106 #define PICOUART_SR_DRDY_Pos 1 /**< \brief (PICOUART_SR) Data Ready Interrupt Status */ 107 #define PICOUART_SR_DRDY (_U_(0x1) << PICOUART_SR_DRDY_Pos) 108 #define PICOUART_SR_MASK _U_(0x00000003) /**< \brief (PICOUART_SR) MASK Register */ 109 110 /* -------- PICOUART_RHR : (PICOUART Offset: 0x0C) (R/ 32) Receive Holding Register -------- */ 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 112 typedef union { 113 struct { 114 uint32_t CDATA:32; /*!< bit: 0..31 Received Data */ 115 } bit; /*!< Structure used for bit access */ 116 uint32_t reg; /*!< Type used for register access */ 117 } PICOUART_RHR_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define PICOUART_RHR_OFFSET 0x0C /**< \brief (PICOUART_RHR offset) Receive Holding Register */ 121 #define PICOUART_RHR_RESETVALUE _U_(0x00000000); /**< \brief (PICOUART_RHR reset_value) Receive Holding Register */ 122 123 #define PICOUART_RHR_CDATA_Pos 0 /**< \brief (PICOUART_RHR) Received Data */ 124 #define PICOUART_RHR_CDATA_Msk (_U_(0xFFFFFFFF) << PICOUART_RHR_CDATA_Pos) 125 #define PICOUART_RHR_CDATA(value) (PICOUART_RHR_CDATA_Msk & ((value) << PICOUART_RHR_CDATA_Pos)) 126 #define PICOUART_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PICOUART_RHR) MASK Register */ 127 128 /* -------- PICOUART_VERSION : (PICOUART Offset: 0x20) (R/ 32) Version Register -------- */ 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 130 typedef union { 131 struct { 132 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 133 uint32_t :4; /*!< bit: 12..15 Reserved */ 134 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 135 uint32_t :12; /*!< bit: 20..31 Reserved */ 136 } bit; /*!< Structure used for bit access */ 137 uint32_t reg; /*!< Type used for register access */ 138 } PICOUART_VERSION_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define PICOUART_VERSION_OFFSET 0x20 /**< \brief (PICOUART_VERSION offset) Version Register */ 142 #define PICOUART_VERSION_RESETVALUE _U_(0x00000101); /**< \brief (PICOUART_VERSION reset_value) Version Register */ 143 144 #define PICOUART_VERSION_VERSION_Pos 0 /**< \brief (PICOUART_VERSION) Version Number */ 145 #define PICOUART_VERSION_VERSION_Msk (_U_(0xFFF) << PICOUART_VERSION_VERSION_Pos) 146 #define PICOUART_VERSION_VERSION(value) (PICOUART_VERSION_VERSION_Msk & ((value) << PICOUART_VERSION_VERSION_Pos)) 147 #define PICOUART_VERSION_VARIANT_Pos 16 /**< \brief (PICOUART_VERSION) Variant Number */ 148 #define PICOUART_VERSION_VARIANT_Msk (_U_(0xF) << PICOUART_VERSION_VARIANT_Pos) 149 #define PICOUART_VERSION_VARIANT(value) (PICOUART_VERSION_VARIANT_Msk & ((value) << PICOUART_VERSION_VARIANT_Pos)) 150 #define PICOUART_VERSION_MASK _U_(0x000F0FFF) /**< \brief (PICOUART_VERSION) MASK Register */ 151 152 /** \brief PICOUART hardware registers */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef struct { 155 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 156 __IO uint32_t CFG; /**< \brief Offset: 0x04 (R/W 32) Configuration Register */ 157 __I uint32_t SR; /**< \brief Offset: 0x08 (R/ 32) Status Register */ 158 __I uint32_t RHR; /**< \brief Offset: 0x0C (R/ 32) Receive Holding Register */ 159 RoReg8 Reserved1[0x10]; 160 __I uint32_t VERSION; /**< \brief Offset: 0x20 (R/ 32) Version Register */ 161 } Picouart; 162 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 163 164 /*@}*/ 165 166 #endif /* _SAM4L_PICOUART_COMPONENT_ */ 167
