1 /* 2 * Copyright (c) 2021-2022 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FPGA_ZYNQMP_H 8 #define ZEPHYR_DRIVERS_FPGA_ZYNQMP_H 9 10 #define PCAP_STATUS (*(volatile uint32_t *) (0xFFCA3010)) 11 #define PCAP_RESET (*(volatile uint32_t *) (0xFFCA300C)) 12 #define PCAP_CTRL (*(volatile uint32_t *) (0xFFCA3008)) 13 #define PCAP_RDWR (*(volatile uint32_t *) (0xFFCA3004)) 14 #define PMU_REQ_PWRUP_TRIG (*(volatile uint32_t *) (0xFFD80120)) 15 #define PCAP_PROG (*(volatile uint32_t *) (0xFFCA3000)) 16 #define CSU_SSS_CFG (*(volatile uint32_t *) (0xFFCA0008)) 17 #define CSUDMA_SRC_ADDR (*(volatile uint32_t *) (0xFFC80000)) 18 #define CSUDMA_SRC_SIZE (*(volatile uint32_t *) (0xFFC80004)) 19 #define CSUDMA_SRC_I_STS (*(volatile uint32_t *) (0xFFC80014)) 20 #define CSUDMA_SRC_ADDR_MSB (*(volatile uint32_t *) (0xFFC80028)) 21 #define PWR_STATUS (*(volatile uint32_t *) (0xFFD80110)) 22 #define PMU_GLOBAL_ISO_STATUS (*(volatile uint32_t *) (0xFFD80310)) 23 #define PMU_GLOBAL_PWRUP_EN (*(volatile uint32_t *) (0xFFD80118)) 24 #define PCAP_CLK_CTRL (*(volatile uint32_t *) (0xFF5E00A4)) 25 #define PMU_GLOBAL_ISO_INT_EN (*(volatile uint32_t *) (0xFFD80318)) 26 #define PMU_GLOBAL_ISO_TRIG (*(volatile uint32_t *) (0xFFD80320)) 27 #define IDCODE (*(volatile uint32_t *) (0xFFCA0040)) 28 #define BITSTREAM ((volatile uint32_t *) (0x01000000)) 29 30 #define PWR_PL_MASK 0x800000U 31 #define ISO_MASK 0x4U 32 #define PCAP_RESET_MASK 0x1U 33 #define PCAP_PROG_RESET_MASK 0x0U 34 #define PCAP_PR_MASK 0x1U 35 #define PCAP_WRITE_MASK 0x0U 36 #define PCAP_PL_INIT_MASK 0x4U 37 #define PCAP_CLKACT_MASK 0x1000000U 38 #define PCAP_PCAP_SSS_MASK 0x5U 39 #define PCAP_PL_DONE_MASK 0x8U 40 #define PCAP_CFG_RESET 0x40U 41 #define CSUDMA_I_STS_DONE_MASK 0x2U 42 #define CSUDMA_SRC_ADDR_MASK 0xFFFFFFFCU 43 #define CSUDMA_SRC_SIZE_SHIFT 0x2U 44 45 #define IDCODE_MASK 0xFFFFFFF 46 #define ZU2_IDCODE 0x4711093 47 #define ZU3_IDCODE 0x4710093 48 #define ZU4_IDCODE 0x4721093 49 #define ZU5_IDCODE 0x4720093 50 #define ZU6_IDCODE 0x4739093 51 #define ZU7_IDCODE 0x4730093 52 #define ZU9_IDCODE 0x4738093 53 #define ZU11_IDCODE 0x4740093 54 #define ZU15_IDCODE 0x4750093 55 #define ZU17_IDCODE 0x4759093 56 #define ZU19_IDCODE 0x4758093 57 #define ZU21_IDCODE 0x47E1093 58 #define ZU25_IDCODE 0x47E5093 59 #define ZU27_IDCODE 0x47E4093 60 #define ZU28_IDCODE 0x47E0093 61 #define ZU29_IDCODE 0x47E2093 62 #define ZU39_IDCODE 0x47E6093 63 #define ZU43_IDCODE 0x47FD093 64 #define ZU46_IDCODE 0x47F8093 65 #define ZU47_IDCODE 0x47FF093 66 #define ZU48_IDCODE 0x47FB093 67 #define ZU49_IDCODE 0x47FE093 68 69 #define XLNX_BITSTREAM_SECTION_LENGTH(data) (*(data + 1) | *data << 0x8U); 70 71 #endif /* ZEPHYR_DRIVERS_FPGA_ZYNQMP_H */ 72
