1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_PWR_EX_H 21 #define STM32U5xx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PWR PVM configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PVMType; /*!< Specifies which voltage is monitored. 50 This parameter can be a value of 51 @ref PWREx_PVM_Type. */ 52 53 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 54 This parameter can be a value of 55 @ref PWREx_PVM_Mode. */ 56 } PWR_PVMTypeDef; 57 /** 58 * @} 59 */ 60 61 /* Exported constants --------------------------------------------------------*/ 62 63 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 64 * @{ 65 */ 66 67 /** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type 68 * @{ 69 */ 70 #define PWR_UVM PWR_SVMCR_UVMEN /*!< Independent USB voltage monitor (VDDUSB versus 1.2 V) */ 71 #define PWR_IO2VM PWR_SVMCR_IO2VMEN /*!< Independent VDDIO2 voltage monitor (VDDIO2 versus 0.9 V) */ 72 #define PWR_AVM1 PWR_SVMCR_AVM1EN /*!< Independent VDDA voltage monitor (VDDA versus 1.6 V) */ 73 #define PWR_AVM2 PWR_SVMCR_AVM2EN /*!< Independent VDDA voltage monitor (VDDA versus 1.8 V) */ 74 /** 75 * @} 76 */ 77 78 /** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode 79 * @{ 80 */ 81 #define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ 82 #define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ 83 #define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ 84 #define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 85 #define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ 86 #define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ 87 #define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ 88 /** 89 * @} 90 */ 91 92 /** @defgroup PWREx_SRD_State PWREx SRD Domain State 93 * @{ 94 */ 95 #define PWR_SRD_DOMAIN_STOP (0U) /*!< SRD in Stop mode when system goes to Stop 0/1/2 mode */ 96 #define PWR_SRD_DOMAIN_RUN PWR_CR2_SRDRUN /*!< SRD in Run mode when system goes to Stop 0/1/2 mode */ 97 /** 98 * @} 99 */ 100 101 /** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended RAM Contents Stop Retention 102 * @{ 103 */ 104 /* SRAM1 pages retention defines */ 105 #define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 106 #define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 107 #define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 108 #if defined (PWR_CR4_SRAM1PDS4) 109 #define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 110 #define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 111 #define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 112 #define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 113 #define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 114 #define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 115 #define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 116 #define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 117 #define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 118 #define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 119 #else 120 #define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 121 #endif /* defined (PWR_CR4_SRAM1PDS4) */ 122 123 /* SRAM2 pages retention defines */ 124 #define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ 125 #define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ 126 #define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ 127 128 #if defined (PWR_CR2_SRAM3PDS1) 129 /* SRAM3 pages retention defines */ 130 #define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 131 #define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 132 #define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 133 #define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 134 #define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 135 #define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 136 #define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 137 #define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 138 #if defined (PWR_CR4_SRAM3PDS9) 139 #define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 140 #define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 141 #define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 142 #define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 143 #define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 144 #define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 145 #else 146 #define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 147 #endif /* defined (PWR_CR4_SRAM3PDS9) */ 148 #endif /* PWR_CR2_SRAM3PDS1 */ 149 150 /* SRAM4 page retention defines */ 151 #define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ 152 153 #if defined (PWR_CR4_SRAM5PDS1) 154 /* SRAM5 pages retention defines */ 155 #define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 156 #define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 157 #define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 158 #define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 159 #define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 160 #define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 161 #define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 162 #define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 163 #define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 164 #define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 165 #define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 166 #define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 167 #define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 168 #define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 169 #endif /* defined (PWR_CR4_SRAM5PDS1) */ 170 171 #if defined (PWR_CR5_SRAM6PDS1) 172 /* SRAM5 pages retention defines */ 173 #define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 174 #define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 175 #define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 176 #define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 177 #define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 178 #define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 179 #define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 180 #define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ 181 #define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ 182 #endif /* defined (PWR_CR5_SRAM6PDS1) */ 183 184 /* Cache RAMs retention defines */ 185 #define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ 186 #define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ 187 #if defined (PWR_CR2_DC2RAMPDS) 188 #define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */ 189 #endif /* defined (PWR_CR2_DC2RAMPDS) */ 190 191 #if defined (PWR_CR2_DMA2DRAMPDS) 192 /* DMA2D RAM retention defines */ 193 #define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 194 #endif /* PWR_CR2_DMA2DRAMPDS */ 195 196 /* FMAC, FDCAN and USB RAMs retention defines */ 197 #define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 198 199 /* PKA32 RAM retention defines */ 200 #define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 201 202 #if defined (PWR_CR2_GPRAMPDS) 203 /* Graphic peripherals RAM retention defines */ 204 #define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */ 205 #endif /* defined (PWR_CR2_GPRAMPDS) */ 206 207 #if defined (PWR_CR2_DSIRAMPDS) 208 /* DSI RAM retention defines */ 209 #define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 210 #endif /* defined (PWR_CR2_DSIRAMPDS) */ 211 212 #if defined (PWR_CR2_JPEGRAMPDS) 213 /* JPEG RAM retention defines */ 214 #define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */ 215 #endif /* defined (PWR_CR2_JPEGRAMPDS) */ 216 /** 217 * @} 218 */ 219 220 /** @defgroup PWREx_SRAM2_Contents_Standby_Retention PWR Extended SRAM2 Contents Standby Retention 221 * @note For some products of the U5 family (please see the Reference Manual), 222 * the SRAM2 content is preserved based on the same defines in Stop 3 mode. 223 * @{ 224 */ 225 #define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ 226 #define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ 227 #define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ 228 /** 229 * @} 230 */ 231 232 /** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention 233 * @{ 234 */ 235 #define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ 236 #define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ 237 #if defined (PWR_CR1_SRAM3PD) 238 #define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ 239 #endif /* PWR_CR1_SRAM3PD */ 240 #define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ 241 #if defined (PWR_CR1_SRAM5PD) 242 #define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */ 243 #endif /* defined (PWR_CR1_SRAM5PD) */ 244 #if defined (PWR_CR1_SRAM6PD) 245 #define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */ 246 #endif /* defined (PWR_CR1_SRAM6PD) */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration 252 * @{ 253 */ 254 #define PWR_LDO_SUPPLY (0U) /*!< LDO supply */ 255 #define PWR_SMPS_SUPPLY (PWR_CR3_REGSEL) /*!< SMPS supply */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale 261 * @{ 262 */ 263 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1) /*!< Voltage scaling range 1 */ 264 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ 265 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ 266 #define PWR_REGULATOR_VOLTAGE_SCALE4 (0U) /*!< Voltage scaling range 4 */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection 272 * @{ 273 */ 274 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */ 275 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port 281 * @{ 282 */ 283 #define PWR_GPIO_A (0x00U) /*!< GPIO port A */ 284 #define PWR_GPIO_B (0x01U) /*!< GPIO port B */ 285 #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ 286 #define PWR_GPIO_D (0x03U) /*!< GPIO port D */ 287 #define PWR_GPIO_E (0x04U) /*!< GPIO port E */ 288 #if defined (PWR_PUCRF_PU0) 289 #define PWR_GPIO_F (0x05U) /*!< GPIO port F */ 290 #endif /* PWR_PUCRF_PU0 */ 291 #define PWR_GPIO_G (0x06U) /*!< GPIO port G */ 292 #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ 293 #if defined (PWR_PUCRI_PU0) 294 #define PWR_GPIO_I (0x08U) /*!< GPIO port I */ 295 #endif /* PWR_PUCRI_PU0 */ 296 #if defined (PWR_PUCRJ_PU0) 297 #define PWR_GPIO_J (0x09U) /*!< GPIO port J */ 298 #endif /* defined (PWR_PUCRJ_PU0) */ 299 /** 300 * @} 301 */ 302 303 /** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask 304 * @{ 305 */ 306 #define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */ 307 #define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */ 308 #define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */ 309 #define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */ 310 #define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */ 311 #define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */ 312 #define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */ 313 #define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */ 314 #define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */ 315 #define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */ 316 #define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */ 317 #define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */ 318 #define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */ 319 #define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */ 320 #define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */ 321 #define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */ 322 /** 323 * @} 324 */ 325 326 /** 327 * @} 328 */ 329 330 /* Exported macros -----------------------------------------------------------*/ 331 332 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 333 * @{ 334 */ 335 336 /** 337 * @brief Enable the UVM Extended Interrupt Line. 338 * @retval None. 339 */ 340 #define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) 341 342 /** 343 * @brief Disable the UVM Extended Interrupt Line. 344 * @retval None. 345 */ 346 #define __HAL_PWR_UVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) 347 348 /** 349 * @brief Enable the UVM Event Line. 350 * @retval None. 351 */ 352 #define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) 353 354 /** 355 * @brief Disable the UVM Event Line. 356 * @retval None. 357 */ 358 #define __HAL_PWR_UVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) 359 360 /** 361 * @brief Enable the UVM Extended Interrupt Rising Trigger. 362 * @retval None. 363 */ 364 #define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) 365 366 /** 367 * @brief Disable the UVM Extended Interrupt Rising Trigger. 368 * @retval None. 369 */ 370 #define __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) 371 372 /** 373 * @brief Enable the UVM Extended Interrupt Falling Trigger. 374 * @retval None. 375 */ 376 #define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) 377 378 /** 379 * @brief Disable the UVM Extended Interrupt Falling Trigger. 380 * @retval None. 381 */ 382 #define __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) 383 384 /** 385 * @brief Enable the UVM Extended Interrupt Rising & Falling Trigger. 386 * @retval None. 387 */ 388 #define __HAL_PWR_UVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ 389 do \ 390 { \ 391 __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); \ 392 __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); \ 393 } while(0) 394 395 /** 396 * @brief Disable the UVM Extended Interrupt Rising & Falling Trigger. 397 * @retval None. 398 */ 399 #define __HAL_PWR_UVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ 400 do \ 401 { \ 402 __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); \ 403 __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); \ 404 } while(0) 405 406 /** 407 * @brief Generate a Software Interrupt on UVM EXTI Line. 408 * @retval None 409 */ 410 #define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM) 411 412 /** 413 * @brief Check whether the specified UVM EXTI flag is set or not. 414 * @retval EXTI UVM Line Status. 415 */ 416 #define __HAL_PWR_UVM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_UVM) 417 418 /** 419 * @brief Clear the UVM EXTI flag. 420 * @retval None. 421 */ 422 #define __HAL_PWR_UVM_EXTI_CLEAR_FLAG() \ 423 do \ 424 { \ 425 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); \ 426 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); \ 427 } while(0) 428 429 /** 430 * @brief Enable the IO2VM Extended Interrupt Line. 431 * @retval None. 432 */ 433 #define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) 434 435 /** 436 * @brief Disable the IO2VM Extended Interrupt Line. 437 * @retval None. 438 */ 439 #define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) 440 441 /** 442 * @brief Enable the IO2VM Event Line. 443 * @retval None. 444 */ 445 #define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) 446 447 /** 448 * @brief Disable the IO2VM Event Line. 449 * @retval None. 450 */ 451 #define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) 452 453 /** 454 * @brief Enable the IO2VM Extended Interrupt Rising Trigger. 455 * @retval None. 456 */ 457 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) 458 459 /** 460 * @brief Disable the IO2VM Extended Interrupt Rising Trigger. 461 * @retval None. 462 */ 463 #define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) 464 465 /** 466 * @brief Enable the IO2VM Extended Interrupt Falling Trigger. 467 * @retval None. 468 */ 469 #define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) 470 471 /** 472 * @brief Disable the IO2VM Extended Interrupt Falling Trigger. 473 * @retval None. 474 */ 475 #define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) 476 477 /** 478 * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger. 479 * @retval None. 480 */ 481 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ 482 do \ 483 { \ 484 __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \ 485 __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \ 486 } while(0) 487 488 /** 489 * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger. 490 * @retval None. 491 */ 492 #define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ 493 do \ 494 { \ 495 __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \ 496 __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \ 497 } while(0) 498 499 /** 500 * @brief Generate a Software Interrupt on IO2VM EXTI Line. 501 * @retval None 502 */ 503 #define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM) 504 505 /** 506 * @brief Check whether the specified IO2VM EXTI flag is set or not. 507 * @retval EXTI IO2VM Line Status. 508 */ 509 #define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_IO2VM) 510 511 /** 512 * @brief Clear the IO2VM EXTI flag. 513 * @retval None. 514 */ 515 #define __HAL_PWR_IO2VM_EXTI_CLEAR_FLAG() \ 516 do \ 517 { \ 518 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); \ 519 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); \ 520 } while(0) 521 522 /** 523 * @brief Enable the AVM1 Extended Interrupt Line. 524 * @retval None. 525 */ 526 #define __HAL_PWR_AVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) 527 528 /** 529 * @brief Disable the AVM1 Extended Interrupt Line. 530 * @retval None. 531 */ 532 #define __HAL_PWR_AVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) 533 534 /** 535 * @brief Enable the AVM1 Event Line. 536 * @retval None. 537 */ 538 #define __HAL_PWR_AVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) 539 540 /** 541 * @brief Disable the AVM1 Event Line. 542 * @retval None. 543 */ 544 #define __HAL_PWR_AVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) 545 546 /** 547 * @brief Enable the AVM1 Extended Interrupt Rising Trigger. 548 * @retval None. 549 */ 550 #define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) 551 552 /** 553 * @brief Disable the AVM1 Extended Interrupt Rising Trigger. 554 * @retval None. 555 */ 556 #define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) 557 558 /** 559 * @brief Enable the AVM1 Extended Interrupt Falling Trigger. 560 * @retval None. 561 */ 562 #define __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) 563 564 /** 565 * @brief Disable the AVM1 Extended Interrupt Falling Trigger. 566 * @retval None. 567 */ 568 #define __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) 569 570 /** 571 * @brief Enable the AVM1 Extended Interrupt Rising & Falling Trigger. 572 * @retval None. 573 */ 574 #define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 575 do \ 576 { \ 577 __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); \ 578 __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); \ 579 } while(0) 580 581 /** 582 * @brief Disable the AVM1 Extended Interrupt Rising & Falling Trigger. 583 * @retval None. 584 */ 585 #define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 586 do \ 587 { \ 588 __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); \ 589 __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); \ 590 } while(0) 591 592 /** 593 * @brief Generate a Software Interrupt on AVM1 EXTI Line. 594 * @retval None 595 */ 596 #define __HAL_PWR_AVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM1) 597 598 /** 599 * @brief Check whether the specified AVM1 EXTI flag is set or not. 600 * @retval EXTI AVM1 Line Status. 601 */ 602 #define __HAL_PWR_AVM1_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM1) 603 604 /** 605 * @brief Clear the AVM1 EXTI flag. 606 * @retval None. 607 */ 608 #define __HAL_PWR_AVM1_EXTI_CLEAR_FLAG() \ 609 do \ 610 { \ 611 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); \ 612 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); \ 613 } while(0) 614 615 /** 616 * @brief Enable the AVM2 Extended Interrupt Line. 617 * @retval None. 618 */ 619 #define __HAL_PWR_AVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) 620 621 /** 622 * @brief Disable the AVM2 Extended Interrupt Line. 623 * @retval None. 624 */ 625 #define __HAL_PWR_AVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) 626 627 /** 628 * @brief Enable the AVM2 Event Line. 629 * @retval None. 630 */ 631 #define __HAL_PWR_AVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) 632 633 /** 634 * @brief Disable the AVM2 Event Line. 635 * @retval None. 636 */ 637 #define __HAL_PWR_AVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) 638 639 /** 640 * @brief Enable the AVM2 Extended Interrupt Rising Trigger. 641 * @retval None. 642 */ 643 #define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) 644 645 /** 646 * @brief Disable the AVM2 Extended Interrupt Rising Trigger. 647 * @retval None. 648 */ 649 #define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) 650 651 /** 652 * @brief Enable the AVM2 Extended Interrupt Falling Trigger. 653 * @retval None. 654 */ 655 #define __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) 656 657 /** 658 * @brief Disable the AVM2 Extended Interrupt Falling Trigger. 659 * @retval None. 660 */ 661 #define __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) 662 663 /** 664 * @brief Enable the AVM2 Extended Interrupt Rising & Falling Trigger. 665 * @retval None. 666 */ 667 #define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 668 do \ 669 { \ 670 __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); \ 671 __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); \ 672 } while(0) 673 674 /** 675 * @brief Disable the AVM2 Extended Interrupt Rising & Falling Trigger. 676 * @retval None. 677 */ 678 #define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 679 do \ 680 { \ 681 __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); \ 682 __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); \ 683 } while(0) 684 685 /** 686 * @brief Generate a Software Interrupt on AVM2 EXTI Line. 687 * @retval None 688 */ 689 #define __HAL_PWR_AVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM2) 690 691 /** 692 * @brief Check whether the specified AVM2 EXTI flag is set or not. 693 * @retval EXTI AVM2 Line Status. 694 */ 695 #define __HAL_PWR_AVM2_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM2) 696 697 /** 698 * @brief Clear the AVM2 EXTI flag. 699 * @retval None. 700 */ 701 #define __HAL_PWR_AVM2_EXTI_CLEAR_FLAG() \ 702 do \ 703 { \ 704 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); \ 705 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); \ 706 } while(0) 707 708 /** 709 * @brief Configure the main internal regulator output voltage. 710 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but 711 * doesn't check whether or not VOSREADY flag is set. User may resort 712 * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state. 713 * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a 714 * tradeoff between performance and power consumption. 715 * This parameter can be one of the following values : 716 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. 717 * Provides a typical output voltage at 1.2 V. 718 * Used when system clock frequency is up to 160 MHz. 719 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. 720 * Provides a typical output voltage at 1.1 V. 721 * Used when system clock frequency is up to 100 MHz. 722 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. 723 * Provides a typical output voltage at 1.0 V. 724 * Used when system clock frequency is up to 50 MHz. 725 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. 726 * Provides a typical output voltage at 0.9 V. 727 * Used when system clock frequency is up to 24 MHz. 728 * @retval None. 729 */ 730 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 731 do \ 732 { \ 733 __IO uint32_t tmpreg; \ 734 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ 735 tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ 736 UNUSED(tmpreg); \ 737 } while(0) 738 /** 739 * @} 740 */ 741 742 /* Private constants ---------------------------------------------------------*/ 743 744 /** @addtogroup PWREx_Private_Constants PWR Extended Private Constants 745 * @{ 746 */ 747 /* PVM extended interrupts and event lines defines */ 748 #define PWR_EXTI_LINE_UVM (0x00080000UL) /* UVM EXTI Line */ 749 #define PWR_EXTI_LINE_IO2VM (0x00100000UL) /* IO2VM EXTI Line */ 750 #define PWR_EXTI_LINE_AVM1 (0x00200000UL) /* AVM1 EXTI Line */ 751 #define PWR_EXTI_LINE_AVM2 (0x00400000UL) /* AVM2 EXTI Line */ 752 753 /* SRAM retention IDs */ 754 #define SRAM_ID_MASK (0xFFFFUL << 16U) 755 #define SRAM1_ID (0x01UL << 16U) 756 #define SRAM2_ID (0x01UL << 17U) 757 #if defined (PWR_CR2_SRAM3PDS1) 758 #define SRAM3_ID (0x01UL << 18U) 759 #endif /* PWR_CR2_SRAM3PDS1 */ 760 #define SRAM4_ID (0x01UL << 19U) 761 #define ICACHERAM_ID (0x01UL << 20U) 762 #define DCACHE1RAM_ID (0x01UL << 21U) 763 #if defined (PWR_CR2_DMA2DRAMPDS) 764 #define DMA2DRAM_ID (0x01UL << 22U) 765 #endif /* PWR_CR2_DMA2DRAMPDS */ 766 #define PERIPHRAM_ID (0x01UL << 23U) 767 #define PKARAM_ID (0x01UL << 24U) 768 #if defined (PWR_CR2_DC2RAMPDS) 769 #define DCACHE2RAM_ID (0x01UL << 25U) 770 #endif /* defined (PWR_CR2_DC2RAMPDS) */ 771 #if defined (PWR_CR2_GPRAMPDS) 772 #define GRAPHIPRAM_ID (0x01UL << 26U) 773 #endif /* defined (PWR_CR2_GPRAMPDS) */ 774 #if defined (PWR_CR2_DSIRAMPDS) 775 #define DSIRAM_ID (0x01UL << 27U) 776 #endif /* defined (PWR_CR2_DSIRAMPDS) */ 777 #if defined (PWR_CR4_SRAM5PDS1) 778 #define SRAM5_ID (0x01UL << 28U) 779 #endif /* defined (PWR_CR4_SRAM5PDS1) */ 780 #if defined (PWR_CR5_SRAM6PDS1) 781 #define SRAM6_ID (0x01UL << 29U) 782 #endif /* defined (PWR_CR5_SRAM6PDS1) */ 783 #if defined (PWR_CR2_JPEGRAMPDS) 784 #define JPEGRAM_ID (0x01UL << 30U) 785 #endif /* defined (PWR_CR2_JPEGRAMPDS)*/ 786 787 /* SRAM page retention IDs */ 788 #define PAGE01_ID (0x01UL << 0U) 789 #define PAGE02_ID (0x01UL << 1U) 790 #define PAGE03_ID (0x01UL << 2U) 791 #define PAGE04_ID (0x01UL << 3U) 792 #define PAGE05_ID (0x01UL << 4U) 793 #define PAGE06_ID (0x01UL << 5U) 794 #define PAGE07_ID (0x01UL << 6U) 795 #define PAGE08_ID (0x01UL << 7U) 796 #define PAGE09_ID (0x01UL << 8U) 797 #define PAGE10_ID (0x01UL << 9U) 798 #define PAGE11_ID (0x01UL << 10U) 799 #define PAGE12_ID (0x01UL << 11U) 800 #define PAGE13_ID (0x01UL << 12U) 801 802 /* All available RAM retention in Run mode define */ 803 #if defined (PWR_CR1_SRAM6PD) 804 #define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ 805 PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ 806 PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN) 807 #elif defined (PWR_CR1_SRAM5PD) 808 #define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ 809 PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ 810 PWR_SRAM5_FULL_RUN) 811 #elif defined (PWR_CR2_SRAM3PDS1) 812 #define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ 813 PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN) 814 #else 815 #define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ 816 PWR_SRAM4_FULL_RUN) 817 #endif /* defined (PWR_CR1_SRAM5PD) */ 818 /** 819 * @} 820 */ 821 822 /* Private macros --------------------------------------------------------*/ 823 824 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 825 * @{ 826 */ 827 /* PVM type check macro */ 828 #define IS_PWR_PVM_TYPE(TYPE) \ 829 (((TYPE) == PWR_UVM ) ||\ 830 ((TYPE) == PWR_IO2VM) ||\ 831 ((TYPE) == PWR_AVM1) ||\ 832 ((TYPE) == PWR_AVM2)) 833 834 /* PVM mode check macro */ 835 #define IS_PWR_PVM_MODE(MODE) \ 836 (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 837 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 838 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 839 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 840 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 841 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 842 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 843 844 /* SRD state check macro */ 845 #define IS_PWR_SRD_STATE(SRD_STATE) \ 846 (((SRD_STATE) == PWR_SRD_DOMAIN_STOP) ||\ 847 ((SRD_STATE) == PWR_SRD_DOMAIN_RUN)) 848 849 /* Supply selection check macro */ 850 #define IS_PWR_SUPPLY(PWR_SOURCE) \ 851 (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 852 ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) 853 854 /* Voltage scaling range check macro */ 855 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \ 856 (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ 857 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\ 858 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3) ||\ 859 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE4)) 860 861 /* Battery charging resistor selection check macro */ 862 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \ 863 (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 864 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 865 866 /* GPIO port check macro */ 867 #if defined (PWR_PUCRJ_PU0) 868 #define IS_PWR_GPIO_PORT(GPIO_PORT) \ 869 (((GPIO_PORT) == PWR_GPIO_A) ||\ 870 ((GPIO_PORT) == PWR_GPIO_B) ||\ 871 ((GPIO_PORT) == PWR_GPIO_C) ||\ 872 ((GPIO_PORT) == PWR_GPIO_D) ||\ 873 ((GPIO_PORT) == PWR_GPIO_E) ||\ 874 ((GPIO_PORT) == PWR_GPIO_F) ||\ 875 ((GPIO_PORT) == PWR_GPIO_G) ||\ 876 ((GPIO_PORT) == PWR_GPIO_H) ||\ 877 ((GPIO_PORT) == PWR_GPIO_I) ||\ 878 ((GPIO_PORT) == PWR_GPIO_J)) 879 #elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0) 880 #define IS_PWR_GPIO_PORT(GPIO_PORT) \ 881 (((GPIO_PORT) == PWR_GPIO_A) ||\ 882 ((GPIO_PORT) == PWR_GPIO_B) ||\ 883 ((GPIO_PORT) == PWR_GPIO_C) ||\ 884 ((GPIO_PORT) == PWR_GPIO_D) ||\ 885 ((GPIO_PORT) == PWR_GPIO_E) ||\ 886 ((GPIO_PORT) == PWR_GPIO_F) ||\ 887 ((GPIO_PORT) == PWR_GPIO_G) ||\ 888 ((GPIO_PORT) == PWR_GPIO_H) ||\ 889 ((GPIO_PORT) == PWR_GPIO_I)) 890 #else 891 #define IS_PWR_GPIO_PORT(GPIO_PORT) \ 892 (((GPIO_PORT) == PWR_GPIO_A) ||\ 893 ((GPIO_PORT) == PWR_GPIO_B) ||\ 894 ((GPIO_PORT) == PWR_GPIO_C) ||\ 895 ((GPIO_PORT) == PWR_GPIO_D) ||\ 896 ((GPIO_PORT) == PWR_GPIO_E) ||\ 897 ((GPIO_PORT) == PWR_GPIO_G) ||\ 898 ((GPIO_PORT) == PWR_GPIO_H)) 899 #endif /* defined (PWR_PUCRJ_PU0) */ 900 901 /* GPIO pin mask check macro */ 902 #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ 903 ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) 904 905 /* SRAM2 retention in Standby mode check macro */ 906 #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ 907 (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\ 908 ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\ 909 ((CONTENT) == PWR_SRAM2_FULL_STANDBY)) 910 911 /* RAMs retention in Stop mode check macros */ 912 #define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ 913 ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 914 915 #define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ 916 ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 917 918 #if defined (PWR_CR2_SRAM3PDS1) 919 #define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ 920 ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 921 #endif /* PWR_CR2_SRAM3PDS1 */ 922 923 #define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ 924 ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 925 926 #if defined (PWR_CR4_SRAM5PDS1) 927 #define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \ 928 ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 929 #endif /* defined (PWR_CR4_SRAM5PDS1) */ 930 931 #if defined (PWR_CR5_SRAM6PDS1) 932 #define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \ 933 ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 934 #endif /* defined (PWR_CR5_SRAM6PDS1) */ 935 936 #define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ 937 ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 938 939 #define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ 940 ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 941 942 #if defined (PWR_CR2_DC2RAMPDS) 943 #define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \ 944 ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 945 #endif /* defined (PWR_CR2_DC2RAMPDS) */ 946 947 #if defined (PWR_CR2_DMA2DRAMPDS) 948 #define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ 949 ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 950 #endif /* PWR_CR2_DMA2DRAMPDS */ 951 952 #define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ 953 ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 954 955 #define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ 956 ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 957 958 #if defined (PWR_CR2_GPRAMPDS) 959 #define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \ 960 ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 961 #endif /* defined (PWR_CR2_GPRAMPDS) */ 962 963 #if defined (PWR_CR2_DSIRAMPDS) 964 #define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \ 965 ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 966 #endif /* defined (PWR_CR2_DSIRAMPDS) */ 967 968 #if defined (PWR_CR2_JPEGRAMPDS) 969 #define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \ 970 ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) 971 #endif /* defined (PWR_CR2_DSIRAMPDS) */ 972 973 /* RAMs retention in Run mode check macro */ 974 #define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ 975 ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U)) 976 /** 977 * @} 978 */ 979 980 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 981 * @{ 982 */ 983 984 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 985 * @{ 986 */ 987 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 988 uint32_t HAL_PWREx_GetVoltageRange(void); 989 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); 990 uint32_t HAL_PWREx_GetSupplyConfig(void); 991 void HAL_PWREx_EnableFastSoftStart(void); 992 void HAL_PWREx_DisableFastSoftStart(void); 993 /** 994 * @} 995 */ 996 997 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 998 * @{ 999 */ 1000 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 1001 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 1002 void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry); 1003 void HAL_PWREx_EnterSHUTDOWNMode(void); 1004 void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState); 1005 void HAL_PWREx_EnableUltraLowPowerMode(void); 1006 void HAL_PWREx_DisableUltraLowPowerMode(void); 1007 void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin); 1008 void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin); 1009 /** 1010 * @} 1011 */ 1012 1013 /** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions 1014 * @{ 1015 */ 1016 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); 1017 void HAL_PWREx_DisableBatteryCharging(void); 1018 void HAL_PWREx_EnableVddUSB(void); 1019 void HAL_PWREx_DisableVddUSB(void); 1020 void HAL_PWREx_EnableVddIO2(void); 1021 void HAL_PWREx_DisableVddIO2(void); 1022 void HAL_PWREx_EnableVddA(void); 1023 void HAL_PWREx_DisableVddA(void); 1024 void HAL_PWREx_EnableUVM(void); 1025 void HAL_PWREx_DisableUVM(void); 1026 void HAL_PWREx_EnableIO2VM(void); 1027 void HAL_PWREx_DisableIO2VM(void); 1028 void HAL_PWREx_EnableAVM1(void); 1029 void HAL_PWREx_DisableAVM1(void); 1030 void HAL_PWREx_EnableAVM2(void); 1031 void HAL_PWREx_DisableAVM2(void); 1032 #if defined (PWR_VOSR_USBPWREN) 1033 HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void); 1034 void HAL_PWREx_DisableUSBHSTranceiverSupply(void); 1035 #endif /* defined (PWR_VOSR_USBPWREN) */ 1036 #if defined (PWR_CR1_FORCE_USBPWR) 1037 void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void); 1038 void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void); 1039 #endif /* defined (PWR_CR1_FORCE_USBPWR) */ 1040 #if defined (PWR_VOSR_VDD11USBDIS) 1041 void HAL_PWREx_EnableVDD11USB(void); 1042 void HAL_PWREx_DisableVDD11USB(void); 1043 #endif /* defined (PWR_VOSR_VDD11USBDIS) */ 1044 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); 1045 void HAL_PWREx_EnableMonitoring(void); 1046 void HAL_PWREx_DisableMonitoring(void); 1047 void HAL_PWREx_EnableUCPDStandbyMode(void); 1048 void HAL_PWREx_DisableUCPDStandbyMode(void); 1049 void HAL_PWREx_EnableUCPDDeadBattery(void); 1050 void HAL_PWREx_DisableUCPDDeadBattery(void); 1051 void HAL_PWREx_PVD_PVM_IRQHandler(void); 1052 void HAL_PWREx_UVMCallback(void); 1053 void HAL_PWREx_IO2VMCallback(void); 1054 void HAL_PWREx_AVM1Callback(void); 1055 void HAL_PWREx_AVM2Callback(void); 1056 /** 1057 * @} 1058 */ 1059 1060 /** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions 1061 * @{ 1062 */ 1063 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); 1064 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); 1065 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); 1066 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); 1067 void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection); 1068 void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection); 1069 void HAL_PWREx_EnableFlashFastWakeUp(void); 1070 void HAL_PWREx_DisableFlashFastWakeUp(void); 1071 void HAL_PWREx_EnableSRAM4FastWakeUp(void); 1072 void HAL_PWREx_DisableSRAM4FastWakeUp(void); 1073 HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void); 1074 void HAL_PWREx_DisableBkupRAMRetention(void); 1075 /** 1076 * @} 1077 */ 1078 1079 /** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions 1080 * @{ 1081 */ 1082 void HAL_PWREx_EnablePullUpPullDownConfig(void); 1083 void HAL_PWREx_DisablePullUpPullDownConfig(void); 1084 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 1085 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); 1086 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 1087 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); 1088 /** 1089 * @} 1090 */ 1091 1092 /** 1093 * @} 1094 */ 1095 1096 /** 1097 * @} 1098 */ 1099 1100 /** 1101 * @} 1102 */ 1103 1104 #ifdef __cplusplus 1105 } 1106 #endif /* __cplusplus */ 1107 1108 1109 #endif /* STM32U5xx_HAL_PWR_EX_H */ 1110
