1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_PWR_EX_H 38 #define __STM32L4xx_HAL_PWR_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup PWREx 52 * @{ 53 */ 54 55 56 /* Exported types ------------------------------------------------------------*/ 57 58 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 59 * @{ 60 */ 61 62 63 /** 64 * @brief PWR PVM configuration structure definition 65 */ 66 typedef struct 67 { 68 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 69 This parameter can be a value of @ref PWREx_PVM_Type. 70 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 71 @if STM32L486xx 72 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 73 @endif 74 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 75 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ 76 77 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 78 This parameter can be a value of @ref PWREx_PVM_Mode. */ 79 }PWR_PVMTypeDef; 80 81 /** 82 * @} 83 */ 84 85 /* Exported constants --------------------------------------------------------*/ 86 87 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 88 * @{ 89 */ 90 91 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 92 * @{ 93 */ 94 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 95 /** 96 * @} 97 */ 98 99 100 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 101 * @{ 102 */ 103 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 104 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 105 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 106 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 107 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 108 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 109 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 110 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 111 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 112 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 113 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 114 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 115 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 116 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 117 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 118 /** 119 * @} 120 */ 121 122 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 123 * @{ 124 */ 125 #if defined(PWR_CR2_PVME1) 126 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 127 #endif /* PWR_CR2_PVME1 */ 128 #if defined(PWR_CR2_PVME2) 129 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ 130 #endif /* PWR_CR2_PVME2 */ 131 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 132 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 133 /** 134 * @} 135 */ 136 137 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 138 * @{ 139 */ 140 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 141 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 142 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 143 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 144 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 145 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 146 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 147 /** 148 * @} 149 */ 150 151 152 153 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 154 * @{ 155 */ 156 #if defined(PWR_CR5_R1MODE) 157 #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ 158 #endif 159 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ 160 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 161 /** 162 * @} 163 */ 164 165 166 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 167 * @{ 168 */ 169 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 170 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 171 /** 172 * @} 173 */ 174 175 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 176 * @{ 177 */ 178 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 179 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 180 /** 181 * @} 182 */ 183 184 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 185 * @{ 186 */ 187 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 188 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 189 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 190 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 191 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 192 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 193 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 194 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 195 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 196 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 197 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 198 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 199 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 200 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */ 201 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */ 202 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ 203 /** 204 * @} 205 */ 206 207 /** @defgroup PWREx_GPIO GPIO port 208 * @{ 209 */ 210 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 211 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 212 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 213 #if defined(GPIOD_BASE) 214 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 215 #endif 216 #if defined(GPIOE_BASE) 217 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 218 #endif 219 #if defined(GPIOF_BASE) 220 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 221 #endif 222 #if defined(GPIOG_BASE) 223 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 224 #endif 225 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 226 #if defined(GPIOI_BASE) 227 #define PWR_GPIO_I 0x00000008U /*!< GPIO port I */ 228 #endif 229 /** 230 * @} 231 */ 232 233 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 234 * @{ 235 */ 236 #if defined(PWR_CR2_PVME1) 237 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 238 #endif /* PWR_CR2_PVME1 */ 239 #if defined(PWR_CR2_PVME2) 240 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 241 #endif /* PWR_CR2_PVME2 */ 242 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 243 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 244 /** 245 * @} 246 */ 247 248 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 249 * @{ 250 */ 251 #if defined(PWR_CR2_PVME1) 252 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 253 #endif /* PWR_CR2_PVME1 */ 254 #if defined(PWR_CR2_PVME2) 255 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 256 #endif /* PWR_CR2_PVME2 */ 257 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 258 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup PWREx_Flag PWR Status Flags 264 * Elements values convention: 0000 0000 0XXY YYYYb 265 * - Y YYYY : Flag position in the XX register (5 bits) 266 * - XX : Status register (2 bits) 267 * - 01: SR1 register 268 * - 10: SR2 register 269 * The only exception is PWR_FLAG_WU, encompassing all 270 * wake-up flags and set to PWR_SR1_WUF. 271 * @{ 272 */ 273 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 274 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 275 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 276 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 277 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 278 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 279 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 280 #if defined(PWR_SR1_EXT_SMPS_RDY) 281 #define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */ 282 #endif /* PWR_SR1_EXT_SMPS_RDY */ 283 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ 284 285 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 286 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 287 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 288 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 289 #if defined(PWR_CR2_PVME1) 290 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 291 #endif /* PWR_CR2_PVME1 */ 292 #if defined(PWR_CR2_PVME2) 293 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 294 #endif /* PWR_CR2_PVME2 */ 295 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 296 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 297 /** 298 * @} 299 */ 300 301 /** 302 * @} 303 */ 304 305 /* Exported macros -----------------------------------------------------------*/ 306 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 307 * @{ 308 */ 309 310 #if defined(PWR_CR2_PVME1) 311 /** 312 * @brief Enable the PVM1 Extended Interrupt Line. 313 * @retval None 314 */ 315 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 316 317 /** 318 * @brief Disable the PVM1 Extended Interrupt Line. 319 * @retval None 320 */ 321 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 322 323 /** 324 * @brief Enable the PVM1 Event Line. 325 * @retval None 326 */ 327 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 328 329 /** 330 * @brief Disable the PVM1 Event Line. 331 * @retval None 332 */ 333 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 334 335 /** 336 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 337 * @retval None 338 */ 339 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 340 341 /** 342 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 343 * @retval None 344 */ 345 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 346 347 /** 348 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 349 * @retval None 350 */ 351 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 352 353 354 /** 355 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 356 * @retval None 357 */ 358 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 359 360 361 /** 362 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 363 * @retval None 364 */ 365 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 366 do { \ 367 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 368 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 369 } while(0) 370 371 /** 372 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 373 * @retval None 374 */ 375 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 376 do { \ 377 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 378 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 379 } while(0) 380 381 /** 382 * @brief Generate a Software interrupt on selected EXTI line. 383 * @retval None 384 */ 385 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 386 387 /** 388 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 389 * @retval EXTI PVM1 Line Status. 390 */ 391 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) 392 393 /** 394 * @brief Clear the PVM1 EXTI flag. 395 * @retval None 396 */ 397 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) 398 399 #endif /* PWR_CR2_PVME1 */ 400 401 402 #if defined(PWR_CR2_PVME2) 403 /** 404 * @brief Enable the PVM2 Extended Interrupt Line. 405 * @retval None 406 */ 407 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 408 409 /** 410 * @brief Disable the PVM2 Extended Interrupt Line. 411 * @retval None 412 */ 413 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 414 415 /** 416 * @brief Enable the PVM2 Event Line. 417 * @retval None 418 */ 419 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 420 421 /** 422 * @brief Disable the PVM2 Event Line. 423 * @retval None 424 */ 425 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 426 427 /** 428 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 429 * @retval None 430 */ 431 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 432 433 /** 434 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 435 * @retval None 436 */ 437 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 438 439 /** 440 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 441 * @retval None 442 */ 443 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 444 445 446 /** 447 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 448 * @retval None 449 */ 450 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 451 452 453 /** 454 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 455 * @retval None 456 */ 457 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 458 do { \ 459 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 460 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 461 } while(0) 462 463 /** 464 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 465 * @retval None 466 */ 467 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 468 do { \ 469 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 470 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 471 } while(0) 472 473 /** 474 * @brief Generate a Software interrupt on selected EXTI line. 475 * @retval None 476 */ 477 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 478 479 /** 480 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 481 * @retval EXTI PVM2 Line Status. 482 */ 483 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) 484 485 /** 486 * @brief Clear the PVM2 EXTI flag. 487 * @retval None 488 */ 489 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) 490 491 #endif /* PWR_CR2_PVME2 */ 492 493 494 /** 495 * @brief Enable the PVM3 Extended Interrupt Line. 496 * @retval None 497 */ 498 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 499 500 /** 501 * @brief Disable the PVM3 Extended Interrupt Line. 502 * @retval None 503 */ 504 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 505 506 /** 507 * @brief Enable the PVM3 Event Line. 508 * @retval None 509 */ 510 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 511 512 /** 513 * @brief Disable the PVM3 Event Line. 514 * @retval None 515 */ 516 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 517 518 /** 519 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 520 * @retval None 521 */ 522 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 523 524 /** 525 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 526 * @retval None 527 */ 528 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 529 530 /** 531 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 532 * @retval None 533 */ 534 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 535 536 537 /** 538 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 539 * @retval None 540 */ 541 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 542 543 544 /** 545 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 546 * @retval None 547 */ 548 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 549 do { \ 550 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 551 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 552 } while(0) 553 554 /** 555 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 556 * @retval None 557 */ 558 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 559 do { \ 560 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 561 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 562 } while(0) 563 564 /** 565 * @brief Generate a Software interrupt on selected EXTI line. 566 * @retval None 567 */ 568 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 569 570 /** 571 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 572 * @retval EXTI PVM3 Line Status. 573 */ 574 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) 575 576 /** 577 * @brief Clear the PVM3 EXTI flag. 578 * @retval None 579 */ 580 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) 581 582 583 584 585 /** 586 * @brief Enable the PVM4 Extended Interrupt Line. 587 * @retval None 588 */ 589 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 590 591 /** 592 * @brief Disable the PVM4 Extended Interrupt Line. 593 * @retval None 594 */ 595 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 596 597 /** 598 * @brief Enable the PVM4 Event Line. 599 * @retval None 600 */ 601 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 602 603 /** 604 * @brief Disable the PVM4 Event Line. 605 * @retval None 606 */ 607 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 608 609 /** 610 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 611 * @retval None 612 */ 613 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 614 615 /** 616 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 617 * @retval None 618 */ 619 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 620 621 /** 622 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 623 * @retval None 624 */ 625 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 626 627 628 /** 629 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 630 * @retval None 631 */ 632 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 633 634 635 /** 636 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 637 * @retval None 638 */ 639 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 640 do { \ 641 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 642 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 643 } while(0) 644 645 /** 646 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 647 * @retval None 648 */ 649 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 650 do { \ 651 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 652 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 653 } while(0) 654 655 /** 656 * @brief Generate a Software interrupt on selected EXTI line. 657 * @retval None 658 */ 659 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 660 661 /** 662 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 663 * @retval EXTI PVM4 Line Status. 664 */ 665 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) 666 667 /** 668 * @brief Clear the PVM4 EXTI flag. 669 * @retval None 670 */ 671 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) 672 673 674 /** 675 * @brief Configure the main internal regulator output voltage. 676 * @param __REGULATOR__: specifies the regulator output voltage to achieve 677 * a tradeoff between performance and power consumption. 678 * This parameter can be one of the following values: 679 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 680 * typical output voltage at 1.2 V, 681 * system frequency up to 80 MHz. 682 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 683 * typical output voltage at 1.0 V, 684 * system frequency up to 26 MHz. 685 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 686 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 687 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 688 * @retval None 689 */ 690 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 691 __IO uint32_t tmpreg; \ 692 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 693 /* Delay after an RCC peripheral clock enabling */ \ 694 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 695 UNUSED(tmpreg); \ 696 } while(0) 697 698 /** 699 * @} 700 */ 701 702 /* Private macros --------------------------------------------------------*/ 703 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 704 * @{ 705 */ 706 707 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 708 ((PIN) == PWR_WAKEUP_PIN2) || \ 709 ((PIN) == PWR_WAKEUP_PIN3) || \ 710 ((PIN) == PWR_WAKEUP_PIN4) || \ 711 ((PIN) == PWR_WAKEUP_PIN5) || \ 712 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 713 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 714 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 715 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 716 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 717 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 718 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 719 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 720 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 721 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 722 723 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 724 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 725 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 726 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 727 ((TYPE) == PWR_PVM_2) ||\ 728 ((TYPE) == PWR_PVM_3) ||\ 729 ((TYPE) == PWR_PVM_4)) 730 #elif defined (STM32L471xx) 731 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ 732 ((TYPE) == PWR_PVM_3) ||\ 733 ((TYPE) == PWR_PVM_4)) 734 #endif 735 736 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) 737 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 738 ((TYPE) == PWR_PVM_3) ||\ 739 ((TYPE) == PWR_PVM_4)) 740 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) 741 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ 742 ((TYPE) == PWR_PVM_4)) 743 #endif 744 745 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 746 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 747 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 748 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 749 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 750 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 751 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 752 753 #if defined(PWR_CR5_R1MODE) 754 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ 755 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 756 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 757 #else 758 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 759 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 760 #endif 761 762 763 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 764 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 765 766 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 767 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 768 769 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 770 771 772 #if defined (STM32L412xx) || defined (STM32L422xx) 773 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 774 ((GPIO) == PWR_GPIO_B) ||\ 775 ((GPIO) == PWR_GPIO_C) ||\ 776 ((GPIO) == PWR_GPIO_D) ||\ 777 ((GPIO) == PWR_GPIO_H)) 778 #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ 779 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 780 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 781 ((GPIO) == PWR_GPIO_B) ||\ 782 ((GPIO) == PWR_GPIO_C) ||\ 783 ((GPIO) == PWR_GPIO_D) ||\ 784 ((GPIO) == PWR_GPIO_E) ||\ 785 ((GPIO) == PWR_GPIO_H)) 786 #elif defined (STM32L432xx) || defined (STM32L442xx) 787 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 788 ((GPIO) == PWR_GPIO_B) ||\ 789 ((GPIO) == PWR_GPIO_C) ||\ 790 ((GPIO) == PWR_GPIO_H)) 791 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 792 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 793 ((GPIO) == PWR_GPIO_B) ||\ 794 ((GPIO) == PWR_GPIO_C) ||\ 795 ((GPIO) == PWR_GPIO_D) ||\ 796 ((GPIO) == PWR_GPIO_E) ||\ 797 ((GPIO) == PWR_GPIO_F) ||\ 798 ((GPIO) == PWR_GPIO_G) ||\ 799 ((GPIO) == PWR_GPIO_H)) 800 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ 801 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 802 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 803 ((GPIO) == PWR_GPIO_B) ||\ 804 ((GPIO) == PWR_GPIO_C) ||\ 805 ((GPIO) == PWR_GPIO_D) ||\ 806 ((GPIO) == PWR_GPIO_E) ||\ 807 ((GPIO) == PWR_GPIO_F) ||\ 808 ((GPIO) == PWR_GPIO_G) ||\ 809 ((GPIO) == PWR_GPIO_H) ||\ 810 ((GPIO) == PWR_GPIO_I)) 811 #endif 812 813 814 /** 815 * @} 816 */ 817 818 819 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 820 * @{ 821 */ 822 823 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 824 * @{ 825 */ 826 827 828 /* Peripheral Control functions **********************************************/ 829 uint32_t HAL_PWREx_GetVoltageRange(void); 830 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 831 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 832 void HAL_PWREx_DisableBatteryCharging(void); 833 #if defined(PWR_CR2_USV) 834 void HAL_PWREx_EnableVddUSB(void); 835 void HAL_PWREx_DisableVddUSB(void); 836 #endif /* PWR_CR2_USV */ 837 #if defined(PWR_CR2_IOSV) 838 void HAL_PWREx_EnableVddIO2(void); 839 void HAL_PWREx_DisableVddIO2(void); 840 #endif /* PWR_CR2_IOSV */ 841 void HAL_PWREx_EnableInternalWakeUpLine(void); 842 void HAL_PWREx_DisableInternalWakeUpLine(void); 843 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 844 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 845 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 846 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 847 void HAL_PWREx_EnablePullUpPullDownConfig(void); 848 void HAL_PWREx_DisablePullUpPullDownConfig(void); 849 void HAL_PWREx_EnableSRAM2ContentRetention(void); 850 void HAL_PWREx_DisableSRAM2ContentRetention(void); 851 #if defined(PWR_CR1_RRSTP) 852 void HAL_PWREx_EnableSRAM3ContentRetention(void); 853 void HAL_PWREx_DisableSRAM3ContentRetention(void); 854 #endif /* PWR_CR1_RRSTP */ 855 #if defined(PWR_CR3_DSIPDEN) 856 void HAL_PWREx_EnableDSIPinsPDActivation(void); 857 void HAL_PWREx_DisableDSIPinsPDActivation(void); 858 #endif /* PWR_CR3_DSIPDEN */ 859 #if defined(PWR_CR2_PVME1) 860 void HAL_PWREx_EnablePVM1(void); 861 void HAL_PWREx_DisablePVM1(void); 862 #endif /* PWR_CR2_PVME1 */ 863 #if defined(PWR_CR2_PVME2) 864 void HAL_PWREx_EnablePVM2(void); 865 void HAL_PWREx_DisablePVM2(void); 866 #endif /* PWR_CR2_PVME2 */ 867 void HAL_PWREx_EnablePVM3(void); 868 void HAL_PWREx_DisablePVM3(void); 869 void HAL_PWREx_EnablePVM4(void); 870 void HAL_PWREx_DisablePVM4(void); 871 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 872 #if defined(PWR_CR3_EN_ULP) 873 void HAL_PWREx_EnableBORPVD_ULP(void); 874 void HAL_PWREx_DisableBORPVD_ULP(void); 875 #endif /* PWR_CR3_EN_ULP */ 876 #if defined(PWR_CR4_EXT_SMPS_ON) 877 void HAL_PWREx_EnableExtSMPS_0V95(void); 878 void HAL_PWREx_DisableExtSMPS_0V95(void); 879 #endif /* PWR_CR4_EXT_SMPS_ON */ 880 881 882 /* Low Power modes configuration functions ************************************/ 883 void HAL_PWREx_EnableLowPowerRunMode(void); 884 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 885 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 886 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 887 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 888 void HAL_PWREx_EnterSHUTDOWNMode(void); 889 890 void HAL_PWREx_PVD_PVM_IRQHandler(void); 891 #if defined(PWR_CR2_PVME1) 892 void HAL_PWREx_PVM1Callback(void); 893 #endif /* PWR_CR2_PVME1 */ 894 #if defined(PWR_CR2_PVME2) 895 void HAL_PWREx_PVM2Callback(void); 896 #endif /* PWR_CR2_PVME2 */ 897 void HAL_PWREx_PVM3Callback(void); 898 void HAL_PWREx_PVM4Callback(void); 899 900 /** 901 * @} 902 */ 903 904 /** 905 * @} 906 */ 907 908 /** 909 * @} 910 */ 911 912 /** 913 * @} 914 */ 915 916 #ifdef __cplusplus 917 } 918 #endif 919 920 921 #endif /* __STM32L4xx_HAL_PWR_EX_H */ 922 923 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 924
