1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_PWR_EX_H 22 #define STM32L5xx_HAL_PWR_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup PWREx 36 * @{ 37 */ 38 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 43 * @{ 44 */ 45 46 47 /** 48 * @brief PWR PVM configuration structure definition 49 */ 50 typedef struct 51 { 52 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 53 This parameter can be a value of @ref PWREx_PVM_Type. 54 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 55 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 56 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 57 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 1.8 V. */ 58 59 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 60 This parameter can be a value of @ref PWREx_PVM_Mode. */ 61 } PWR_PVMTypeDef; 62 63 /** 64 * @} 65 */ 66 67 /* Exported constants --------------------------------------------------------*/ 68 69 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 70 * @{ 71 */ 72 73 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 74 * @{ 75 */ 76 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 77 /** 78 * @} 79 */ 80 81 82 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 83 * @{ 84 */ 85 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 86 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 87 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 88 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 89 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 90 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 91 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 92 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 93 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 94 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 95 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WUPP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 96 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WUPP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 97 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WUPP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 98 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WUPP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 99 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WUPP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 100 /** 101 * @} 102 */ 103 104 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 105 * @{ 106 */ 107 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 108 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V */ 109 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 110 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 1.8 V */ 111 /** 112 * @} 113 */ 114 115 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 116 * @{ 117 */ 118 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 119 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 120 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 121 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 122 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 123 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 124 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 125 /** 126 * @} 127 */ 128 129 130 131 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 132 * @{ 133 */ 134 #define PWR_REGULATOR_VOLTAGE_SCALE0 0U /*!< Voltage scaling range 0 */ 135 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ 136 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 137 /** 138 * @} 139 */ 140 141 142 /** @defgroup PWREx_SMPS_Mode PWR SMPS step down converter mode 143 * @{ 144 */ 145 #define PWR_SMPS_HIGH_POWER 0U /*!< SMPS step down converter in high-power mode (default) */ 146 #define PWR_SMPS_LOW_POWER PWR_CR4_SMPSLPEN /*!< SMPS step down converter in low-power mode */ 147 #define PWR_SMPS_BYPASS PWR_CR4_SMPSBYP /*!< SMPS step down converter in bypass mode */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup PWREx_EXT_SMPS_MAIN_REG_READY PWR SMPS main regulator ready for external SMPS 153 * @{ 154 */ 155 #define PWR_MAINREG_READY_FOR_EXTSMPS PWR_SR1_EXTSMPSRDY /*!< Main Regulator ready for use with external SMPS */ 156 #define PWR_MAINREG_NOT_READY_FOR_EXTSMPS 0U /*!< Main Regulator not ready for use with external SMPS */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 162 * @{ 163 */ 164 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 165 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 166 /** 167 * @} 168 */ 169 170 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 171 * @{ 172 */ 173 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 174 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 175 /** 176 * @} 177 */ 178 179 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 180 * @{ 181 */ 182 #define PWR_GPIO_BIT_0 PWR_PUCRA_PU0 /*!< GPIO port I/O pin 0 */ 183 #define PWR_GPIO_BIT_1 PWR_PUCRA_PU1 /*!< GPIO port I/O pin 1 */ 184 #define PWR_GPIO_BIT_2 PWR_PUCRA_PU2 /*!< GPIO port I/O pin 2 */ 185 #define PWR_GPIO_BIT_3 PWR_PUCRA_PU3 /*!< GPIO port I/O pin 3 */ 186 #define PWR_GPIO_BIT_4 PWR_PUCRA_PU4 /*!< GPIO port I/O pin 4 */ 187 #define PWR_GPIO_BIT_5 PWR_PUCRA_PU5 /*!< GPIO port I/O pin 5 */ 188 #define PWR_GPIO_BIT_6 PWR_PUCRA_PU6 /*!< GPIO port I/O pin 6 */ 189 #define PWR_GPIO_BIT_7 PWR_PUCRA_PU7 /*!< GPIO port I/O pin 7 */ 190 #define PWR_GPIO_BIT_8 PWR_PUCRA_PU8 /*!< GPIO port I/O pin 8 */ 191 #define PWR_GPIO_BIT_9 PWR_PUCRA_PU9 /*!< GPIO port I/O pin 9 */ 192 #define PWR_GPIO_BIT_10 PWR_PUCRA_PU10 /*!< GPIO port I/O pin 10 */ 193 #define PWR_GPIO_BIT_11 PWR_PUCRA_PU11 /*!< GPIO port I/O pin 11 */ 194 #define PWR_GPIO_BIT_12 PWR_PUCRA_PU12 /*!< GPIO port I/O pin 12 */ 195 #define PWR_GPIO_BIT_13 PWR_PUCRA_PU13 /*!< GPIO port I/O pin 13 */ 196 #define PWR_GPIO_BIT_14 PWR_PUCRA_PU14 /*!< GPIO port I/O pin 14 */ 197 #define PWR_GPIO_BIT_15 PWR_PUCRA_PU15 /*!< GPIO port I/O pin 15 */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup PWREx_GPIO GPIO port 203 * @{ 204 */ 205 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 206 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 207 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 208 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 209 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 210 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 211 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 212 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 218 * @{ 219 */ 220 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 221 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 222 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 223 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 229 * @{ 230 */ 231 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 232 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 233 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 234 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup PWREx_Flag PWR Status Flags 240 * Elements values convention: 0000 0000 0XXY YYYYb 241 * - Y YYYY : Flag position in the XX register (5 bits) 242 * - XX : Status register (2 bits) 243 * - 01: SR1 register 244 * - 10: SR2 register 245 * The only exception is PWR_FLAG_WU, encompassing all 246 * wake-up flags and set to PWR_SR1_WUF. 247 * @{ 248 */ 249 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 250 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 251 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 252 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 253 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 254 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 255 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 256 #define PWR_FLAG_SMPS_BYPASS_RDY ((uint32_t)0x002C) /*!< SMPS bypass mode ready */ 257 #define PWR_FLAG_EXT_SMPS_RDY ((uint32_t)0x002D) /*!< External SMPS mode ready */ 258 #define PWR_FLAG_SMPS_HP_RDY ((uint32_t)0x002E) /*!< SMPS high-power mode ready */ 259 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 260 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 261 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 262 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 263 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 264 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 265 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 266 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup PWREx_SecureMode PWREx Secure Mode 272 * @note Only available when system implements security (TZEN=1) 273 * @{ 274 */ 275 #define PWR_SECURE_NONE 0U /*!< No security on PWR resources (default) */ 276 #define PWR_SECURE_ALL 0x0F1FU /*!< Security on all PWR resources */ 277 278 #define PWR_SECURE_WUP PWR_SECCFGR_WUPSEC /*!< All Wakeup pins secure configuration */ 279 #define PWR_SECURE_WUP1 PWR_SECCFGR_WUP1SEC /*!< Wakeup pin 1 secure configuration */ 280 #define PWR_SECURE_WUP2 PWR_SECCFGR_WUP2SEC /*!< Wakeup pin 2 secure configuration */ 281 #define PWR_SECURE_WUP3 PWR_SECCFGR_WUP3SEC /*!< Wakeup pin 3 secure configuration */ 282 #define PWR_SECURE_WUP4 PWR_SECCFGR_WUP4SEC /*!< Wakeup pin 4 secure configuration */ 283 #define PWR_SECURE_WUP5 PWR_SECCFGR_WUP5SEC /*!< Wakeup pin 5 secure configuration */ 284 #define PWR_SECURE_LPM PWR_SECCFGR_LPMSEC /*!< Low-power mode secure configuration */ 285 #define PWR_SECURE_VDM PWR_SECCFGR_VDMSEC /*!< Voltage Detection and Monitoring secure configuration */ 286 #define PWR_SECURE_VB PWR_SECCFGR_VBSEC /*!< VBAT mode secure configuration */ 287 #define PWR_SECURE_APC PWR_SECCFGR_APCSEC /*!< Pull-up/down Control secure configuration */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup PWREx_SRAM2_Contents_Retention PWR SRAM2 Content Retention 293 * @{ 294 */ 295 #define PWR_NO_SRAM2_RETENTION 0U /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost)*/ 296 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< : Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept) */ 297 #define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4kB of SRAM2 is powered by the low-power regulator in Standby mode (4kB of SRAM2 content is kept) */ 298 /** 299 * @} 300 */ 301 302 /** 303 * @} 304 */ 305 306 /* Exported macros -----------------------------------------------------------*/ 307 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 308 * @{ 309 */ 310 311 /** 312 * @brief Enable the PVM1 Extended Interrupt Line. 313 * @retval None 314 */ 315 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 316 317 /** 318 * @brief Disable the PVM1 Extended Interrupt Line. 319 * @retval None 320 */ 321 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 322 323 /** 324 * @brief Enable the PVM1 Event Line. 325 * @retval None 326 */ 327 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 328 329 /** 330 * @brief Disable the PVM1 Event Line. 331 * @retval None 332 */ 333 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 334 335 /** 336 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 337 * @retval None 338 */ 339 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 340 341 /** 342 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 343 * @retval None 344 */ 345 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 346 347 /** 348 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 349 * @retval None 350 */ 351 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 352 353 354 /** 355 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 356 * @retval None 357 */ 358 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 359 360 361 /** 362 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 363 * @retval None 364 */ 365 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 366 do { \ 367 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 368 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 369 } while(0) 370 371 /** 372 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 373 * @retval None 374 */ 375 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 376 do { \ 377 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 378 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 379 } while(0) 380 381 /** 382 * @brief Generate a Software interrupt on selected EXTI line. 383 * @retval None 384 */ 385 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 386 387 /** 388 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 389 * @retval EXTI PVM1 Line Status. 390 */ 391 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM1) 392 393 /** 394 * @brief Clear the PVM1 EXTI flag. 395 * @retval None 396 */ 397 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() \ 398 do { \ 399 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM1); \ 400 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM1); \ 401 } while(0) 402 403 404 /** 405 * @brief Enable the PVM2 Extended Interrupt Line. 406 * @retval None 407 */ 408 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 409 410 /** 411 * @brief Disable the PVM2 Extended Interrupt Line. 412 * @retval None 413 */ 414 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 415 416 /** 417 * @brief Enable the PVM2 Event Line. 418 * @retval None 419 */ 420 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 421 422 /** 423 * @brief Disable the PVM2 Event Line. 424 * @retval None 425 */ 426 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 427 428 /** 429 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 430 * @retval None 431 */ 432 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 433 434 /** 435 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 436 * @retval None 437 */ 438 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 439 440 /** 441 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 442 * @retval None 443 */ 444 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 445 446 447 /** 448 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 449 * @retval None 450 */ 451 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 452 453 454 /** 455 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 456 * @retval None 457 */ 458 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 459 do { \ 460 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 461 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 462 } while(0) 463 464 /** 465 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 466 * @retval None 467 */ 468 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 469 do { \ 470 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 471 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 472 } while(0) 473 474 /** 475 * @brief Generate a Software interrupt on selected EXTI line. 476 * @retval None 477 */ 478 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 479 480 /** 481 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 482 * @retval EXTI PVM2 Line Status. 483 */ 484 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM2) 485 486 /** 487 * @brief Clear the PVM2 EXTI flag. 488 * @retval None 489 */ 490 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() \ 491 do { \ 492 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM2); \ 493 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM2); \ 494 } while(0) 495 496 497 /** 498 * @brief Enable the PVM3 Extended Interrupt Line. 499 * @retval None 500 */ 501 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 502 503 /** 504 * @brief Disable the PVM3 Extended Interrupt Line. 505 * @retval None 506 */ 507 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 508 509 /** 510 * @brief Enable the PVM3 Event Line. 511 * @retval None 512 */ 513 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 514 515 /** 516 * @brief Disable the PVM3 Event Line. 517 * @retval None 518 */ 519 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 520 521 /** 522 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 523 * @retval None 524 */ 525 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 526 527 /** 528 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 529 * @retval None 530 */ 531 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 532 533 /** 534 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 535 * @retval None 536 */ 537 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 538 539 540 /** 541 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 542 * @retval None 543 */ 544 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 545 546 547 /** 548 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 549 * @retval None 550 */ 551 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 552 do { \ 553 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 554 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 555 } while(0) 556 557 /** 558 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 559 * @retval None 560 */ 561 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 562 do { \ 563 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 564 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 565 } while(0) 566 567 /** 568 * @brief Generate a Software interrupt on selected EXTI line. 569 * @retval None 570 */ 571 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 572 573 /** 574 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 575 * @retval EXTI PVM3 Line Status. 576 */ 577 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM3) 578 579 /** 580 * @brief Clear the PVM3 EXTI flag. 581 * @retval None 582 */ 583 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() \ 584 do { \ 585 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM3); \ 586 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM3); \ 587 } while(0) 588 589 590 591 /** 592 * @brief Enable the PVM4 Extended Interrupt Line. 593 * @retval None 594 */ 595 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 596 597 /** 598 * @brief Disable the PVM4 Extended Interrupt Line. 599 * @retval None 600 */ 601 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 602 603 /** 604 * @brief Enable the PVM4 Event Line. 605 * @retval None 606 */ 607 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 608 609 /** 610 * @brief Disable the PVM4 Event Line. 611 * @retval None 612 */ 613 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 614 615 /** 616 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 617 * @retval None 618 */ 619 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 620 621 /** 622 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 623 * @retval None 624 */ 625 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 626 627 /** 628 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 629 * @retval None 630 */ 631 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 632 633 634 /** 635 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 636 * @retval None 637 */ 638 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 639 640 641 /** 642 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 643 * @retval None 644 */ 645 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 646 do { \ 647 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 648 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 649 } while(0) 650 651 /** 652 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 653 * @retval None 654 */ 655 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 656 do { \ 657 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 658 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 659 } while(0) 660 661 /** 662 * @brief Generate a Software interrupt on selected EXTI line. 663 * @retval None 664 */ 665 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 666 667 /** 668 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 669 * @retval EXTI PVM4 Line Status. 670 */ 671 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM4) 672 673 /** 674 * @brief Clear the PVM4 EXTI flag. 675 * @retval None 676 */ 677 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() \ 678 do { \ 679 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM4); \ 680 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM4); \ 681 } while(0) 682 683 684 /** 685 * @brief Configure the main internal regulator output voltage. 686 * @param __REGULATOR__ specifies the regulator output voltage to achieve 687 * a tradeoff between performance and power consumption. 688 * This parameter can be one of the following values: 689 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 Regulator voltage output range 0 mode, 690 * typical output voltage at 1.28 V, 691 * system frequency up to 110 MHz. 692 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 693 * typical output voltage at 1.2 V, 694 * system frequency up to 80 MHz. 695 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 696 * typical output voltage at 1.0 V, 697 * system frequency up to 26 MHz. 698 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 699 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 700 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 701 * @retval None 702 */ 703 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 704 __IO uint32_t tmpreg; \ 705 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 706 /* Delay after an RCC peripheral clock enabling */ \ 707 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 708 UNUSED(tmpreg); \ 709 } while(0) 710 711 /** 712 * @} 713 */ 714 715 /* Private macros --------------------------------------------------------*/ 716 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 717 * @{ 718 */ 719 720 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 721 ((PIN) == PWR_WAKEUP_PIN2) || \ 722 ((PIN) == PWR_WAKEUP_PIN3) || \ 723 ((PIN) == PWR_WAKEUP_PIN4) || \ 724 ((PIN) == PWR_WAKEUP_PIN5) || \ 725 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 726 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 727 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 728 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 729 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 730 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 731 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 732 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 733 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 734 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 735 736 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 737 ((TYPE) == PWR_PVM_2) ||\ 738 ((TYPE) == PWR_PVM_3) ||\ 739 ((TYPE) == PWR_PVM_4)) 740 741 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 742 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 743 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 744 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 745 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 746 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 747 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 748 749 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ 750 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 751 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 752 753 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 754 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 755 756 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 757 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 758 759 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 760 761 762 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 763 ((GPIO) == PWR_GPIO_B) ||\ 764 ((GPIO) == PWR_GPIO_C) ||\ 765 ((GPIO) == PWR_GPIO_D) ||\ 766 ((GPIO) == PWR_GPIO_E) ||\ 767 ((GPIO) == PWR_GPIO_F) ||\ 768 ((GPIO) == PWR_GPIO_G) ||\ 769 ((GPIO) == PWR_GPIO_H)) 770 771 #define IS_PWR_SRAM2CONTENT_RETENTION(CONTENT) (((CONTENT) == PWR_NO_SRAM2_RETENTION) ||\ 772 ((CONTENT) == PWR_FULL_SRAM2_RETENTION) ||\ 773 ((CONTENT) == PWR_4KBYTES_SRAM2_RETENTION)) 774 775 #define IS_PWR_SMPS_MODE(__MODE__) (((__MODE__) == PWR_SMPS_HIGH_POWER) || \ 776 ((__MODE__) == PWR_SMPS_LOW_POWER) || \ 777 ((__MODE__) == PWR_SMPS_BYPASS)) 778 779 #define IS_PWR_SECURE_CONFIG(__CONFIG__) (((__CONFIG__) == PWR_SECURE_NONE) || \ 780 ((__CONFIG__) == PWR_SECURE_ALL) || \ 781 (((__CONFIG__) & PWR_SECURE_WUP) == PWR_SECURE_WUP) || \ 782 (((__CONFIG__) & PWR_SECURE_WUP1) == PWR_SECURE_WUP1) || \ 783 (((__CONFIG__) & PWR_SECURE_WUP2) == PWR_SECURE_WUP2) || \ 784 (((__CONFIG__) & PWR_SECURE_WUP3) == PWR_SECURE_WUP3) || \ 785 (((__CONFIG__) & PWR_SECURE_WUP4) == PWR_SECURE_WUP4) || \ 786 (((__CONFIG__) & PWR_SECURE_WUP5) == PWR_SECURE_WUP5) || \ 787 (((__CONFIG__) & PWR_SECURE_LPM) == PWR_SECURE_LPM) || \ 788 (((__CONFIG__) & PWR_SECURE_VDM) == PWR_SECURE_VDM) || \ 789 (((__CONFIG__) & PWR_SECURE_VB) == PWR_SECURE_VB) || \ 790 (((__CONFIG__) & PWR_SECURE_APC) == PWR_SECURE_APC)) 791 /** 792 * @} 793 */ 794 795 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 796 * @{ 797 */ 798 799 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 800 * @{ 801 */ 802 803 804 /* Peripheral Control functions **********************************************/ 805 uint32_t HAL_PWREx_GetVoltageRange(void); 806 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 807 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 808 void HAL_PWREx_DisableBatteryCharging(void); 809 void HAL_PWREx_EnableVddUSB(void); 810 void HAL_PWREx_DisableVddUSB(void); 811 void HAL_PWREx_EnableVddIO2(void); 812 void HAL_PWREx_DisableVddIO2(void); 813 void HAL_PWREx_EnableInternalWakeUpLine(void); 814 void HAL_PWREx_DisableInternalWakeUpLine(void); 815 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 816 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 817 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 818 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 819 void HAL_PWREx_EnablePullUpPullDownConfig(void); 820 void HAL_PWREx_DisablePullUpPullDownConfig(void); 821 void HAL_PWREx_EnablePVM1(void); 822 void HAL_PWREx_DisablePVM1(void); 823 void HAL_PWREx_EnablePVM2(void); 824 void HAL_PWREx_DisablePVM2(void); 825 void HAL_PWREx_EnablePVM3(void); 826 void HAL_PWREx_DisablePVM3(void); 827 void HAL_PWREx_EnablePVM4(void); 828 void HAL_PWREx_DisablePVM4(void); 829 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 830 831 /* Low Power modes configuration functions ************************************/ 832 void HAL_PWREx_EnableLowPowerRunMode(void); 833 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 834 void HAL_PWREx_EnableUltraLowPowerMode(void); 835 void HAL_PWREx_DisableUltraLowPowerMode(void); 836 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 837 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 838 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 839 void HAL_PWREx_EnterSHUTDOWNMode(void); 840 841 void HAL_PWREx_PVD_PVM_IRQHandler(void); 842 void HAL_PWREx_PVM1Callback(void); 843 void HAL_PWREx_PVM2Callback(void); 844 void HAL_PWREx_PVM3Callback(void); 845 void HAL_PWREx_PVM4Callback(void); 846 847 HAL_StatusTypeDef HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention); 848 void HAL_PWREx_EnableSRAM2ContentRetention(void); 849 void HAL_PWREx_DisableSRAM2ContentRetention(void); 850 851 void HAL_PWREx_EnableUCPDStandbyMode(void); 852 void HAL_PWREx_DisableUCPDStandbyMode(void); 853 void HAL_PWREx_EnableUCPDDeadBattery(void); 854 void HAL_PWREx_DisableUCPDDeadBattery(void); 855 856 /** 857 * @} 858 */ 859 860 /** @addtogroup PWREx_Exported_Functions_Group2 861 * @{ 862 */ 863 864 HAL_StatusTypeDef HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); 865 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); 866 uint32_t HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void); 867 void HAL_PWREx_SMPS_EnableFastStart(void); 868 void HAL_PWREx_SMPS_DisableFastStart(void); 869 870 void HAL_PWREx_SMPS_EnableExternal(void); 871 void HAL_PWREx_SMPS_DisableExternal(void); 872 void HAL_PWREx_SMPS_DisableBypassMode(void); 873 void HAL_PWREx_SMPS_EnableBypassMode(void); 874 875 /** 876 * @} 877 */ 878 879 /** 880 * @} 881 */ 882 883 /** 884 * @} 885 */ 886 887 /** 888 * @} 889 */ 890 891 #ifdef __cplusplus 892 } 893 #endif 894 895 896 #endif /* STM32L5xx_HAL_PWR_EX_H */ 897 898 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 899
