1 /**************************************************************************//** 2 * @file pwm_reg.h 3 * @version V1.00 4 * @brief PWM register definition header file 5 * 6 * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. 7 *****************************************************************************/ 8 #ifndef __PWM_REG_H__ 9 #define __PWM_REG_H__ 10 11 #if defined ( __CC_ARM ) 12 #pragma anon_unions 13 #endif 14 15 /** 16 @addtogroup REGISTER Control Register 17 @{ 18 */ 19 20 /** 21 @addtogroup PWM Pulse Width Modulation Controller (PWM) 22 Memory Mapped Structure for PWM Controller 23 @{ */ 24 25 typedef struct 26 { 27 /** 28 * @var CAPDAT_T::RCAPDAT 29 * Offset: 0x20C~0x238 PWM Rising Capture Data Register 0~5 30 * --------------------------------------------------------------------------------------------------- 31 * |Bits |Field |Descriptions 32 * | :----: | :----: | :---- | 33 * |[15:0] |RCAPDAT |PWM Rising Capture Data (Read Only) 34 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 35 * @var CAPDAT_T::FCAPDAT 36 * Offset: 0x210 PWM Falling Capture Data Register 0~5 37 * --------------------------------------------------------------------------------------------------- 38 * |Bits |Field |Descriptions 39 * | :----: | :----: | :---- | 40 * |[15:0] |FCAPDAT |PWWM Falling Capture Data (Read Only) 41 * | | |When falling capture condition happened, the PWWM counter value will be saved in this register. 42 */ 43 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] PWM Rising Capture Data Register 0~5 */ 44 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] PWM Falling Capture Data Register 0~5 */ 45 } CAPDAT_T; 46 47 typedef struct 48 { 49 50 /** 51 * @var PWM_T::CTL0 52 * Offset: 0x00 PWM Control Register 0 53 * --------------------------------------------------------------------------------------------------- 54 * |Bits |Field |Descriptions 55 * | :----: | :----: | :---- | 56 * |[0] |CTRLDn |Center Load Enable Bits 57 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 58 * | | |CMPDAT will load to CMPBUF at the center point of a period 59 * |[16] |IMMLDENn |Immediately Load Enable Bits 60 * | | |0 = PERIOD will load to PBUF at the end point of each period 61 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 62 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 63 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 64 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 65 * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. 66 * | | |0 = ICE debug mode counter halt Disable. 67 * | | |1 = ICE debug mode counter halt Enable. 68 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 69 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 70 * | | |0 = ICE debug mode acknowledgement effects PWM output. 71 * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged. 72 * | | |1 = ICE debug mode acknowledgement disabled. 73 * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not. 74 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 75 * @var PWM_T::CTL1 76 * Offset: 0x04 PWM Control Register 1 77 * --------------------------------------------------------------------------------------------------- 78 * |Bits |Field |Descriptions 79 * | :----: | :----: | :---- | 80 * |[1:0] |CNTTYPE0 |PWM Counter Behavior Type 0 81 * | | |The two bits control channel1 and channel0 82 * | | |00 = Up counter type (supported in capture mode). 83 * | | |01 = Down count type (supported in capture mode). 84 * | | |10 = Up-down counter type. 85 * | | |11 = Reserved. 86 * |[5:4] |CNTTYPE2 |PWM Counter Behavior Type 2 87 * | | |The two bits control channel3 and channel2 88 * | | |00 = Up counter type (supported in capture mode). 89 * | | |01 = Down count type (supported in capture mode). 90 * | | |10 = Up-down counter type. 91 * | | |11 = Reserved. 92 * |[9:8] |CNTTYPE4 |PWM Counter Behavior Type 4 93 * | | |The two bits control channel5 and channel4 94 * | | |00 = Up counter type (supported in capture mode). 95 * | | |01 = Down count type (supported in capture mode). 96 * | | |10 = Up-down counter type. 97 * | | |11 = Reserved. 98 * |[26:24] |OUTMODEn |PWM Output Mode 99 * | | |Each bit n controls the output mode of corresponding PWM channel n. 100 * | | |0 = PWM independent mode. 101 * | | |1 = PWM complementary mode. 102 * | | |Note: When operating in group function, these bits must all set to the same mode. 103 * @var PWM_T::CLKSRC 104 * Offset: 0x10 PWM Clock Source Register 105 * --------------------------------------------------------------------------------------------------- 106 * |Bits |Field |Descriptions 107 * | :----: | :----: | :---- | 108 * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select 109 * | | |000 = PWMx_CLK, x denotes 0 or 1. 110 * | | |001 = TIMER0 overflow. 111 * | | |010 = TIMER1 overflow. 112 * | | |011 = TIMER2 overflow. 113 * | | |100 = TIMER3 overflow. 114 * | | |Others = Reserved. 115 * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select 116 * | | |000 = PWMx_CLK, x denotes 0 or 1. 117 * | | |001 = TIMER0 overflow. 118 * | | |010 = TIMER1 overflow. 119 * | | |011 = TIMER2 overflow. 120 * | | |100 = TIMER3 overflow. 121 * | | |Others = Reserved. 122 * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select 123 * | | |000 = PWMx_CLK, x denotes 0 or 1. 124 * | | |001 = TIMER0 overflow. 125 * | | |010 = TIMER1 overflow. 126 * | | |011 = TIMER2 overflow. 127 * | | |100 = TIMER3 overflow. 128 * | | |Others = Reserved. 129 * @var PWM_T::CLKPSC0_1 130 * Offset: 0x14 PWM Clock Prescale Register 0/1 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[11:0] |CLKPSC |PWM Counter Clock Prescale 135 * | | |The clock of PWM counter is decided by clock prescaler 136 * | | |Each PWM pair share one PWM counter clock prescaler 137 * | | |The clock of PWM counter is divided by (CLKPSC+ 1) 138 * @var PWM_T::CLKPSC2_3 139 * Offset: 0x18 PWM Clock Prescale Register 2/3 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[11:0] |CLKPSC |PWM Counter Clock Prescale 144 * | | |The clock of PWM counter is decided by clock prescaler 145 * | | |Each PWM pair share one PWM counter clock prescaler 146 * | | |The clock of PWM counter is divided by (CLKPSC+ 1) 147 * @var PWM_T::CLKPSC4_5 148 * Offset: 0x1C PWM Clock Prescale Register 4/5 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[11:0] |CLKPSC |PWM Counter Clock Prescale 153 * | | |The clock of PWM counter is decided by clock prescaler 154 * | | |Each PWM pair share one PWM counter clock prescaler 155 * | | |The clock of PWM counter is divided by (CLKPSC+ 1) 156 * @var PWM_T::CNTEN 157 * Offset: 0x20 PWM Counter Enable Register 158 * --------------------------------------------------------------------------------------------------- 159 * |Bits |Field |Descriptions 160 * | :----: | :----: | :---- | 161 * |[0] |CNTEN0 |PWM Counter Enable Bit 0 162 * | | |0 = PWM Counter and clock prescaler Stop Running. 163 * | | |1 = PWM Counter and clock prescaler Start Running. 164 * |[2] |CNTEN2 |PWM Counter Enable Bit 2 165 * | | |0 = PWM Counter and clock prescaler Stop Running. 166 * | | |1 = PWM Counter and clock prescaler Start Running. 167 * |[4] |CNTEN4 |PWM Counter Enable Bit 4 168 * | | |0 = PWM Counter and clock prescaler Stop Running. 169 * | | |1 = PWM Counter and clock prescaler Start Running. 170 * @var PWM_T::CNTCLR 171 * Offset: 0x24 PWM Clear Counter Register 172 * --------------------------------------------------------------------------------------------------- 173 * |Bits |Field |Descriptions 174 * | :----: | :----: | :---- | 175 * |[0] |CNTCLR0 |Clear PWM Counter Control Bit 0 176 * | | |It is automatically cleared by hardware. 177 * | | |0 = No effect. 178 * | | |1 = Clear 16-bit PWM counter to 0000H. 179 * |[2] |CNTCLR2 |Clear PWM Counter Control Bit 2 180 * | | |It is automatically cleared by hardware. 181 * | | |0 = No effect. 182 * | | |1 = Clear 16-bit PWM counter to 0000H. 183 * |[4] |CNTCLR4 |Clear PWM Counter Control Bit 4 184 * | | |It is automatically cleared by hardware. 185 * | | |0 = No effect. 186 * | | |1 = Clear 16-bit PWM counter to 0000H. 187 * @var PWM_T::PERIOD[6] 188 * Offset: 0x30~0x44 PWM Period Register 0, 2, 4 189 * --------------------------------------------------------------------------------------------------- 190 * |Bits |Field |Descriptions 191 * | :----: | :----: | :---- | 192 * |[15:0] |PERIOD |PWM Period Register 193 * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0. 194 * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD. 195 * | | |PWM period time = (PERIOD+1) * PWM_CLK period. 196 * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 197 * | | |PWM period time = 2 * PERIOD * PWM_CLK period. 198 * @var PWM_T::CMPDAT[6] 199 * Offset: 0x50~0x64 PWM Comparator Register 0~5 200 * --------------------------------------------------------------------------------------------------- 201 * |Bits |Field |Descriptions 202 * | :----: | :----: | :---- | 203 * |[15:0] |CMP |PWM Comparator Register 204 * | | |CMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger EADC. 205 * | | |In independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point. 206 * | | |In complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 207 * @var PWM_T::DTCTL0_1 208 * Offset: 0x70 PWM Dead-time Control Register 0/1 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 213 * | | |The dead-time can be calculated from the following formula: 214 * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. 215 * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period * (CLKPSC+1). 216 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 217 * |[16] |DTEN |Enable Dead-time Insertion for PWM Pair (Write Protect) 218 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled 219 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 220 * | | |0 = Dead-time insertion Disabled on the pin pair. 221 * | | |1 = Dead-time insertion Enabled on the pin pair. 222 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 223 * | | |Note: PWM pair means PWM_CH0, PWM_CH1 are a pair, PWM_CH2, PWM_CH3 are a pair and PWM_CH4, PWM_CH5 are a pair. 224 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 225 * | | |0 = Dead-time clock source from PWM_CLK. 226 * | | |1 = Dead-time clock source from prescaler output. 227 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 228 * @var PWM_T::DTCTL2_3 229 * Offset: 0x74 PWM Dead-time Control Register 2/3 230 * --------------------------------------------------------------------------------------------------- 231 * |Bits |Field |Descriptions 232 * | :----: | :----: | :---- | 233 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 234 * | | |The dead-time can be calculated from the following formula: 235 * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. 236 * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period * (CLKPSC+1). 237 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 238 * |[16] |DTEN |Enable Dead-time Insertion for PWM Pair (Write Protect) 239 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled 240 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 241 * | | |0 = Dead-time insertion Disabled on the pin pair. 242 * | | |1 = Dead-time insertion Enabled on the pin pair. 243 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 244 * | | |Note: PWM pair means PWM_CH0, PWM_CH1 are a pair, PWM_CH2, PWM_CH3 are a pair and PWM_CH4, PWM_CH5 are a pair. 245 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 246 * | | |0 = Dead-time clock source from PWM_CLK. 247 * | | |1 = Dead-time clock source from prescaler output. 248 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 249 * @var PWM_T::DTCTL4_5 250 * Offset: 0x78 PWM Dead-time Control Register 4/5 251 * --------------------------------------------------------------------------------------------------- 252 * |Bits |Field |Descriptions 253 * | :----: | :----: | :---- | 254 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 255 * | | |The dead-time can be calculated from the following formula: 256 * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. 257 * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period * (CLKPSC+1). 258 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 259 * |[16] |DTEN |Enable Dead-time Insertion for PWM Pair (Write Protect) 260 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled 261 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 262 * | | |0 = Dead-time insertion Disabled on the pin pair. 263 * | | |1 = Dead-time insertion Enabled on the pin pair. 264 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 265 * | | |Note: PWM pair means PWM_CH0, PWM_CH1 are a pair, PWM_CH2, PWM_CH3 are a pair and PWM_CH4, PWM_CH5 are a pair. 266 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 267 * | | |0 = Dead-time clock source from PWM_CLK. 268 * | | |1 = Dead-time clock source from prescaler output. 269 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 270 * @var PWM_T::CNT[6] 271 * Offset: 0x90~0xA4 PWM Counter Register 0, 2, 4 272 * --------------------------------------------------------------------------------------------------- 273 * |Bits |Field |Descriptions 274 * | :----: | :----: | :---- | 275 * |[15:0] |CNT |PWM Data Register (Read Only) 276 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 277 * |[16] |DIRF |PWM Direction Indicator Flag (Read Only) 278 * | | |0 = Counter is counting down. 279 * | | |1 = Counter is counting up. 280 * @var PWM_T::WGCTL0 281 * Offset: 0xB0 PWM Generation Register 0 282 * --------------------------------------------------------------------------------------------------- 283 * |Bits |Field |Descriptions 284 * | :----: | :----: | :---- | 285 * |[1:0] |ZPCTL0 |PWM Zero Point Control 286 * | | |00 = Do nothing. 287 * | | |01 = PWM zero point output Low. 288 * | | |10 = PWM zero point output High. 289 * | | |11 = PWM zero point output Toggle. 290 * | | |Note: PWM can control output level when PWM counter counts to 0. 291 * |[3:2] |ZPCTL1 |PWM Zero Point Control 292 * | | |00 = Do nothing. 293 * | | |01 = PWM zero point output Low. 294 * | | |10 = PWM zero point output High. 295 * | | |11 = PWM zero point output Toggle. 296 * | | |Note: PWM can control output level when PWM counter counts to 0. 297 * |[5:4] |ZPCTL2 |PWM Zero Point Control 298 * | | |00 = Do nothing. 299 * | | |01 = PWM zero point output Low. 300 * | | |10 = PWM zero point output High. 301 * | | |11 = PWM zero point output Toggle. 302 * | | |Note: PWM can control output level when PWM counter counts to 0. 303 * |[7:6] |ZPCTL3 |PWM Zero Point Control 304 * | | |00 = Do nothing. 305 * | | |01 = PWM zero point output Low. 306 * | | |10 = PWM zero point output High. 307 * | | |11 = PWM zero point output Toggle. 308 * | | |Note: PWM can control output level when PWM counter counts to 0. 309 * |[9:8] |ZPCTL4 |PWM Zero Point Control 310 * | | |00 = Do nothing. 311 * | | |01 = PWM zero point output Low. 312 * | | |10 = PWM zero point output High. 313 * | | |11 = PWM zero point output Toggle. 314 * | | |Note: PWM can control output level when PWM counter counts to 0. 315 * |[11:10] |ZPCTL5 |PWM Zero Point Control 316 * | | |00 = Do nothing. 317 * | | |01 = PWM zero point output Low. 318 * | | |10 = PWM zero point output High. 319 * | | |11 = PWM zero point output Toggle. 320 * | | |Note: PWM can control output level when PWM counter counts to 0. 321 * |[17:16] |PRDPCTL0 |PWM Period/Center Point Control 322 * | | |00 = Do nothing. 323 * | | |01 = PWM period/center point output Low. 324 * | | |10 = PWM period/center point output High. 325 * | | |11 = PWM period/center point output Toggle. 326 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 327 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 328 * |[19:18] |PRDPCTL1 |PWM Period/Center Point Control 329 * | | |00 = Do nothing. 330 * | | |01 = PWM period/center point output Low. 331 * | | |10 = PWM period/center point output High. 332 * | | |11 = PWM period/center point output Toggle. 333 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 334 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 335 * |[21:20] |PRDPCTL2 |PWM Period/Center Point Control 336 * | | |00 = Do nothing. 337 * | | |01 = PWM period/center point output Low. 338 * | | |10 = PWM period/center point output High. 339 * | | |11 = PWM period/center point output Toggle. 340 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 341 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 342 * |[23:22] |PRDPCTL3 |PWM Period/Center Point Control 343 * | | |00 = Do nothing. 344 * | | |01 = PWM period/center point output Low. 345 * | | |10 = PWM period/center point output High. 346 * | | |11 = PWM period/center point output Toggle. 347 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 348 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 349 * |[25:24] |PRDPCTL4 |PWM Period/Center Point Control 350 * | | |00 = Do nothing. 351 * | | |01 = PWM period/center point output Low. 352 * | | |10 = PWM period/center point output High. 353 * | | |11 = PWM period/center point output Toggle. 354 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 355 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 356 * |[27:26] |PRDPCTL5 |PWM Period/Center Point Control 357 * | | |00 = Do nothing. 358 * | | |01 = PWM period/center point output Low. 359 * | | |10 = PWM period/center point output High. 360 * | | |11 = PWM period/center point output Toggle. 361 * | | |Note 1: PWM can control output level when PWM counter counts to (PERIODn+1). 362 * | | |Note 2: This bit is center point control when PWM counter operating in up-down counter type. 363 * @var PWM_T::WGCTL1 364 * Offset: 0xB4 PWM Generation Register 1 365 * --------------------------------------------------------------------------------------------------- 366 * |Bits |Field |Descriptions 367 * | :----: | :----: | :---- | 368 * |[1:0] |CMPUCTL0 |PWM Compare Up Point Control 369 * | | |00 = Do nothing. 370 * | | |01 = PWM compare up point output Low. 371 * | | |10 = PWM compare up point output High. 372 * | | |11 = PWM compare up point output Toggle. 373 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 374 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 375 * |[3:2] |CMPUCTL1 |PWM Compare Up Point Control 376 * | | |00 = Do nothing. 377 * | | |01 = PWM compare up point output Low. 378 * | | |10 = PWM compare up point output High. 379 * | | |11 = PWM compare up point output Toggle. 380 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 381 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 382 * |[5:4] |CMPUCTL2 |PWM Compare Up Point Control 383 * | | |00 = Do nothing. 384 * | | |01 = PWM compare up point output Low. 385 * | | |10 = PWM compare up point output High. 386 * | | |11 = PWM compare up point output Toggle. 387 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 388 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 389 * |[7:6] |CMPUCTL3 |PWM Compare Up Point Control 390 * | | |00 = Do nothing. 391 * | | |01 = PWM compare up point output Low. 392 * | | |10 = PWM compare up point output High. 393 * | | |11 = PWM compare up point output Toggle. 394 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 395 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 396 * |[9:8] |CMPUCTL4 |PWM Compare Up Point Control 397 * | | |00 = Do nothing. 398 * | | |01 = PWM compare up point output Low. 399 * | | |10 = PWM compare up point output High. 400 * | | |11 = PWM compare up point output Toggle. 401 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 402 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 403 * |[11:10] |CMPUCTL5 |PWM Compare Up Point Control 404 * | | |00 = Do nothing. 405 * | | |01 = PWM compare up point output Low. 406 * | | |10 = PWM compare up point output High. 407 * | | |11 = PWM compare up point output Toggle. 408 * | | |Note 1: PWM can control output level when PWM counter counts up to CMPDAT. 409 * | | |Note 2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 410 * |[17:16] |CMPDCTL0 |PWM Compare Down Point Control 411 * | | |00 = Do nothing. 412 * | | |01 = PWM compare down point output Low. 413 * | | |10 = PWM compare down point output High. 414 * | | |11 = PWM compare down point output Toggle. 415 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 416 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 417 * |[19:18] |CMPDCTL1 |PWM Compare Down Point Control 418 * | | |00 = Do nothing. 419 * | | |01 = PWM compare down point output Low. 420 * | | |10 = PWM compare down point output High. 421 * | | |11 = PWM compare down point output Toggle. 422 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 423 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 424 * |[21:20] |CMPDCTL2 |PWM Compare Down Point Control 425 * | | |00 = Do nothing. 426 * | | |01 = PWM compare down point output Low. 427 * | | |10 = PWM compare down point output High. 428 * | | |11 = PWM compare down point output Toggle. 429 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 430 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 431 * |[23:22] |CMPDCTL3 |PWM Compare Down Point Control 432 * | | |00 = Do nothing. 433 * | | |01 = PWM compare down point output Low. 434 * | | |10 = PWM compare down point output High. 435 * | | |11 = PWM compare down point output Toggle. 436 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 437 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 438 * |[25:24] |CMPDCTL4 |PWM Compare Down Point Control 439 * | | |00 = Do nothing. 440 * | | |01 = PWM compare down point output Low. 441 * | | |10 = PWM compare down point output High. 442 * | | |11 = PWM compare down point output Toggle. 443 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 444 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 445 * |[27:26] |CMPDCTL5 |PWM Compare Down Point Control 446 * | | |00 = Do nothing. 447 * | | |01 = PWM compare down point output Low. 448 * | | |10 = PWM compare down point output High. 449 * | | |11 = PWM compare down point output Toggle. 450 * | | |Note 1: PWM can control output level when PWM counter counts down to CMPDAT. 451 * | | |Note 2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 452 * @var PWM_T::MSKEN 453 * Offset: 0xB8 PWM Mask Enable Register 454 * --------------------------------------------------------------------------------------------------- 455 * |Bits |Field |Descriptions 456 * | :----: | :----: | :---- | 457 * |[0] |MSKEN0 |PWM Mask Enable Bits 458 * | | |The PWM output signal will be masked when this bit is enabled 459 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 460 * | | |0 = PWM output signal is non-masked. 461 * | | |1 = PWM output signal is masked and output MSKDATn data. 462 * |[1] |MSKEN1 |PWM Mask Enable Bits 463 * | | |The PWM output signal will be masked when this bit is enabled 464 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 465 * | | |0 = PWM output signal is non-masked. 466 * | | |1 = PWM output signal is masked and output MSKDATn data. 467 * |[2] |MSKEN2 |PWM Mask Enable Bits 468 * | | |The PWM output signal will be masked when this bit is enabled 469 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 470 * | | |0 = PWM output signal is non-masked. 471 * | | |1 = PWM output signal is masked and output MSKDATn data. 472 * |[3] |MSKEN3 |PWM Mask Enable Bits 473 * | | |The PWM output signal will be masked when this bit is enabled 474 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 475 * | | |0 = PWM output signal is non-masked. 476 * | | |1 = PWM output signal is masked and output MSKDATn data. 477 * |[4] |MSKEN4 |PWM Mask Enable Bits 478 * | | |The PWM output signal will be masked when this bit is enabled 479 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 480 * | | |0 = PWM output signal is non-masked. 481 * | | |1 = PWM output signal is masked and output MSKDATn data. 482 * |[5] |MSKEN5 |PWM Mask Enable Bits 483 * | | |The PWM output signal will be masked when this bit is enabled 484 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 485 * | | |0 = PWM output signal is non-masked. 486 * | | |1 = PWM output signal is masked and output MSKDATn data. 487 * @var PWM_T::MSK 488 * Offset: 0xBC PWM Mask Data Register 489 * --------------------------------------------------------------------------------------------------- 490 * |Bits |Field |Descriptions 491 * | :----: | :----: | :---- | 492 * |[0] |MSKDAT0 |PWM Mask Data Bit 493 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 494 * | | |Each bit n controls the corresponding PWM channel n. 495 * | | |0 = Output logic low to PWM channel n. 496 * | | |1 = Output logic high to PWM channel n. 497 * |[1] |MSKDAT1 |PWM Mask Data Bit 498 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 499 * | | |Each bit n controls the corresponding PWM channel n. 500 * | | |0 = Output logic low to PWM channel n. 501 * | | |1 = Output logic high to PWM channel n. 502 * |[2] |MSKDAT2 |PWM Mask Data Bit 503 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 504 * | | |Each bit n controls the corresponding PWM channel n. 505 * | | |0 = Output logic low to PWM channel n. 506 * | | |1 = Output logic high to PWM channel n. 507 * |[3] |MSKDAT3 |PWM Mask Data Bit 508 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 509 * | | |Each bit n controls the corresponding PWM channel n. 510 * | | |0 = Output logic low to PWM channel n. 511 * | | |1 = Output logic high to PWM channel n. 512 * |[4] |MSKDAT4 |PWM Mask Data Bit 513 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 514 * | | |Each bit n controls the corresponding PWM channel n. 515 * | | |0 = Output logic low to PWM channel n. 516 * | | |1 = Output logic high to PWM channel n. 517 * |[5] |MSKDAT5 |PWM Mask Data Bit 518 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled 519 * | | |Each bit n controls the corresponding PWM channel n. 520 * | | |0 = Output logic low to PWM channel n. 521 * | | |1 = Output logic high to PWM channel n. 522 * @var PWM_T::BNF 523 * Offset: 0xC0 PWM Brake Noise Filter Register 524 * --------------------------------------------------------------------------------------------------- 525 * |Bits |Field |Descriptions 526 * | :----: | :----: | :---- | 527 * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable Bit 528 * | | |0 = Noise filter of PWM Brake 0 Disabled. 529 * | | |1 = Noise filter of PWM Brake 0 Enabled. 530 * |[3:1] |BRK0FSEL |Brake 0 Edge Detector Filter Clock Selection 531 * | | |000 = Filter clock = HCLK. 532 * | | |001 = Filter clock = HCLK/2. 533 * | | |010 = Filter clock = HCLK/4. 534 * | | |011 = Filter clock = HCLK/8. 535 * | | |100 = Filter clock = HCLK/16. 536 * | | |101 = Filter clock = HCLK/32. 537 * | | |110 = Filter clock = HCLK/64. 538 * | | |111 = Filter clock = HCLK/128. 539 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count 540 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 541 * |[7] |BRK0PINV |Brake 0 Pin Inverse 542 * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector. 543 * | | |1 = The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector. 544 * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable Bit 545 * | | |0 = Noise filter of PWM Brake 1 Disabled. 546 * | | |1 = Noise filter of PWM Brake 1 Enabled. 547 * |[11:9] |BRK1FSEL |Brake 1 Edge Detector Filter Clock Selection 548 * | | |000 = Filter clock = HCLK. 549 * | | |001 = Filter clock = HCLK/2. 550 * | | |010 = Filter clock = HCLK/4. 551 * | | |011 = Filter clock = HCLK/8. 552 * | | |100 = Filter clock = HCLK/16. 553 * | | |101 = Filter clock = HCLK/32. 554 * | | |110 = Filter clock = HCLK/64. 555 * | | |111 = Filter clock = HCLK/128. 556 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count 557 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 558 * |[15] |BRK1PINV |Brake 1 Pin Inverse 559 * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector. 560 * | | |1 = The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector. 561 * |[16] |BK0SRC |Brake 0 Pin Source Select 562 * | | |For PWM0 setting: 563 * | | |0 = Brake 0 pin source come from PWM0_BRAKE0. 564 * | | |1 = Brake 0 pin source come from PWM1_BRAKE0. 565 * | | |For PWM1 setting: 566 * | | |0 = Brake 0 pin source come from PWM1_BRAKE0. 567 * | | |1 = Brake 0 pin source come from PWM0_BRAKE0. 568 * |[24] |BK1SRC |Brake 1 Pin Source Select 569 * | | |For PWM0 setting: 570 * | | |0 = Brake 1 pin source come from PWM0_BRAKE1. 571 * | | |1 = Brake 1 pin source come from PWM1_BRAKE1. 572 * | | |For PWM1 setting: 573 * | | |0 = Brake 1 pin source come from PWM1_BRAKE1. 574 * | | |1 = Brake 1 pin source come from PWM0_BRAKE1. 575 * @var PWM_T::FAILBRK 576 * Offset: 0xC4 PWM System Fail Brake Control Register 577 * --------------------------------------------------------------------------------------------------- 578 * |Bits |Field |Descriptions 579 * | :----: | :----: | :---- | 580 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit 581 * | | |0 = Brake Function triggered by CSS detection Disabled. 582 * | | |1 = Brake Function triggered by CSS detection Enabled. 583 * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit 584 * | | |0 = Brake Function triggered by BOD Disabled. 585 * | | |1 = Brake Function triggered by BOD Enabled. 586 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit 587 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 588 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 589 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit 590 * | | |0 = Brake Function triggered by Core lockup detection Disabled. 591 * | | |1 = Brake Function triggered by Core lockup detection Enabled. 592 * @var PWM_T::BRKCTL0_1 593 * Offset: 0xC8 PWM Brake Edge Detect Control Register 0/1 594 * --------------------------------------------------------------------------------------------------- 595 * |Bits |Field |Descriptions 596 * | :----: | :----: | :---- | 597 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 598 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 599 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 600 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 601 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 602 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 603 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 604 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 605 * |[2] |CPO2EBEN |Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect) 606 * | | |0 = ACMP2_O as edge-detect brake source Disabled. 607 * | | |1 = ACMP2_O as edge-detect brake source Enabled. 608 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 609 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 610 * | | |0 = BKP0 pin as edge-detect brake source Disabled. 611 * | | |1 = BKP0 pin as edge-detect brake source Enabled. 612 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 613 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 614 * | | |0 = BKP1 pin as edge-detect brake source Disabled. 615 * | | |1 = BKP1 pin as edge-detect brake source Enabled. 616 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 617 * |[6] |VBSNEBEN |UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect) 618 * | | |0 = UTCPD0 VBUS sink disable as edge-detect brake source Disabled. 619 * | | |1 = UTCPD0 VBUS sink disable as edge-detect brake source Enabled. 620 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 621 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 622 * | | |0 = System Fail condition as edge-detect brake source Disabled. 623 * | | |1 = System Fail condition as edge-detect brake source Enabled. 624 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 625 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 626 * | | |0 = ACMP0_O as level-detect brake source Disabled. 627 * | | |1 = ACMP0_O as level-detect brake source Enabled. 628 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 629 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 630 * | | |0 = ACMP1_O as level-detect brake source Disabled. 631 * | | |1 = ACMP1_O as level-detect brake source Enabled. 632 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 633 * |[10] |CPO2LBEN |Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect) 634 * | | |0 = ACMP2_O as level-detect brake source Disabled. 635 * | | |1 = ACMP2_O as level-detect brake source Enabled. 636 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 637 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 638 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 639 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. 640 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 641 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 642 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 643 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. 644 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 645 * |[14] |VBSNLBEN |UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect) 646 * | | |0 = UTCPD0 VBUS sink disable as level-detect brake source Disabled. 647 * | | |1 = UTCPD0 VBUS sink disable as level-detect brake source Enabled. 648 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 649 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 650 * | | |0 = System Fail condition as level-detect brake source Disabled. 651 * | | |1 = System Fail condition as level-detect brake source Enabled. 652 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 653 * |[17:16] |BRKAEVEN |PWM Brake Action Select for Even Channel (Write Protect) 654 * | | |00 = PWM even channel level-detect brake function not affect channel output. 655 * | | |01 = PWM even channel output tri-state when level-detect brake happened. 656 * | | |10 = PWM even channel output low level when level-detect brake happened. 657 * | | |11 = PWM even channel output high level when level-detect brake happened. 658 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 659 * |[19:18] |BRKAODD |PWM Brake Action Select for Odd Channel (Write Protect) 660 * | | |00 = PWM odd channel level-detect brake function not affect channel output. 661 * | | |01 = PWM odd channel output tri-state when level-detect brake happened. 662 * | | |10 = PWM odd channel output low level when level-detect brake happened. 663 * | | |11 = PWM odd channel output high level when level-detect brake happened. 664 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 665 * |[20] |EADC0EBEN |Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect) 666 * | | |0 = EADC0RM as edge-detect brake source Disabled. 667 * | | |1 = EADC0RM as edge-detect brake source Enabled. 668 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 669 * |[23] |VBSREBEN |UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect) 670 * | | |0 = UTCPD0 VBUS source disable as edge-detect brake source Disabled. 671 * | | |1 = UTCPD0 VBUS source disable as edge-detect brake source Enabled. 672 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 673 * |[28] |EADC0LBEN |Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect) 674 * | | |0 = EADC0RM as level-detect brake source Disabled. 675 * | | |1 = EADC0RM as level-detect brake source Enabled. 676 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 677 * |[31] |VBSRLBEN |UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect) 678 * | | |0 = UTCPD0 VBUS source disable as level-detect brake source Disabled. 679 * | | |1 = UTCPD0 VBUS source disable as level-detect brake source Enabled. 680 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 681 * @var PWM_T::BRKCTL2_3 682 * Offset: 0xCC PWM Brake Edge Detect Control Register 2/3 683 * --------------------------------------------------------------------------------------------------- 684 * |Bits |Field |Descriptions 685 * | :----: | :----: | :---- | 686 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 687 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 688 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 689 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 690 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 691 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 692 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 693 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 694 * |[2] |CPO2EBEN |Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect) 695 * | | |0 = ACMP2_O as edge-detect brake source Disabled. 696 * | | |1 = ACMP2_O as edge-detect brake source Enabled. 697 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 698 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 699 * | | |0 = BKP0 pin as edge-detect brake source Disabled. 700 * | | |1 = BKP0 pin as edge-detect brake source Enabled. 701 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 702 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 703 * | | |0 = BKP1 pin as edge-detect brake source Disabled. 704 * | | |1 = BKP1 pin as edge-detect brake source Enabled. 705 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 706 * |[6] |VBSNEBEN |UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect) 707 * | | |0 = UTCPD0 VBUS sink disable as edge-detect brake source Disabled. 708 * | | |1 = UTCPD0 VBUS sink disable as edge-detect brake source Enabled. 709 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 710 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 711 * | | |0 = System Fail condition as edge-detect brake source Disabled. 712 * | | |1 = System Fail condition as edge-detect brake source Enabled. 713 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 714 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 715 * | | |0 = ACMP0_O as level-detect brake source Disabled. 716 * | | |1 = ACMP0_O as level-detect brake source Enabled. 717 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 718 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 719 * | | |0 = ACMP1_O as level-detect brake source Disabled. 720 * | | |1 = ACMP1_O as level-detect brake source Enabled. 721 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 722 * |[10] |CPO2LBEN |Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect) 723 * | | |0 = ACMP2_O as level-detect brake source Disabled. 724 * | | |1 = ACMP2_O as level-detect brake source Enabled. 725 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 726 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 727 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 728 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. 729 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 730 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 731 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 732 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. 733 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 734 * |[14] |VBSNLBEN |UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect) 735 * | | |0 = UTCPD0 VBUS sink disable as level-detect brake source Disabled. 736 * | | |1 = UTCPD0 VBUS sink disable as level-detect brake source Enabled. 737 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 738 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 739 * | | |0 = System Fail condition as level-detect brake source Disabled. 740 * | | |1 = System Fail condition as level-detect brake source Enabled. 741 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 742 * |[17:16] |BRKAEVEN |PWM Brake Action Select for Even Channel (Write Protect) 743 * | | |00 = PWM even channel level-detect brake function not affect channel output. 744 * | | |01 = PWM even channel output tri-state when level-detect brake happened. 745 * | | |10 = PWM even channel output low level when level-detect brake happened. 746 * | | |11 = PWM even channel output high level when level-detect brake happened. 747 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 748 * |[19:18] |BRKAODD |PWM Brake Action Select for Odd Channel (Write Protect) 749 * | | |00 = PWM odd channel level-detect brake function not affect channel output. 750 * | | |01 = PWM odd channel output tri-state when level-detect brake happened. 751 * | | |10 = PWM odd channel output low level when level-detect brake happened. 752 * | | |11 = PWM odd channel output high level when level-detect brake happened. 753 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 754 * |[20] |EADC0EBEN |Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect) 755 * | | |0 = EADC0RM as edge-detect brake source Disabled. 756 * | | |1 = EADC0RM as edge-detect brake source Enabled. 757 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 758 * |[23] |VBSREBEN |UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect) 759 * | | |0 = UTCPD0 VBUS source disable as edge-detect brake source Disabled. 760 * | | |1 = UTCPD0 VBUS source disable as edge-detect brake source Enabled. 761 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 762 * |[28] |EADC0LBEN |Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect) 763 * | | |0 = EADC0RM as level-detect brake source Disabled. 764 * | | |1 = EADC0RM as level-detect brake source Enabled. 765 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 766 * |[31] |VBSRLBEN |UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect) 767 * | | |0 = UTCPD0 VBUS source disable as level-detect brake source Disabled. 768 * | | |1 = UTCPD0 VBUS source disable as level-detect brake source Enabled. 769 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 770 * @var PWM_T::BRKCTL4_5 771 * Offset: 0xD0 PWM Brake Edge Detect Control Register 4/5 772 * --------------------------------------------------------------------------------------------------- 773 * |Bits |Field |Descriptions 774 * | :----: | :----: | :---- | 775 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 776 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 777 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 778 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 779 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 780 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 781 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 782 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 783 * |[2] |CPO2EBEN |Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect) 784 * | | |0 = ACMP2_O as edge-detect brake source Disabled. 785 * | | |1 = ACMP2_O as edge-detect brake source Enabled. 786 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 787 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 788 * | | |0 = BKP0 pin as edge-detect brake source Disabled. 789 * | | |1 = BKP0 pin as edge-detect brake source Enabled. 790 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 791 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 792 * | | |0 = BKP1 pin as edge-detect brake source Disabled. 793 * | | |1 = BKP1 pin as edge-detect brake source Enabled. 794 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 795 * |[6] |VBSNEBEN |UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect) 796 * | | |0 = UTCPD0 VBUS sink disable as edge-detect brake source Disabled. 797 * | | |1 = UTCPD0 VBUS sink disable as edge-detect brake source Enabled. 798 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 799 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 800 * | | |0 = System Fail condition as edge-detect brake source Disabled. 801 * | | |1 = System Fail condition as edge-detect brake source Enabled. 802 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 803 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 804 * | | |0 = ACMP0_O as level-detect brake source Disabled. 805 * | | |1 = ACMP0_O as level-detect brake source Enabled. 806 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 807 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 808 * | | |0 = ACMP1_O as level-detect brake source Disabled. 809 * | | |1 = ACMP1_O as level-detect brake source Enabled. 810 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 811 * |[10] |CPO2LBEN |Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect) 812 * | | |0 = ACMP2_O as level-detect brake source Disabled. 813 * | | |1 = ACMP2_O as level-detect brake source Enabled. 814 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 815 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 816 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 817 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. 818 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 819 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 820 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 821 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. 822 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 823 * |[14] |VBSNLBEN |UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect) 824 * | | |0 = UTCPD0 VBUS sink disable as level-detect brake source Disabled. 825 * | | |1 = UTCPD0 VBUS sink disable as level-detect brake source Enabled. 826 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 827 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 828 * | | |0 = System Fail condition as level-detect brake source Disabled. 829 * | | |1 = System Fail condition as level-detect brake source Enabled. 830 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 831 * |[17:16] |BRKAEVEN |PWM Brake Action Select for Even Channel (Write Protect) 832 * | | |00 = PWM even channel level-detect brake function not affect channel output. 833 * | | |01 = PWM even channel output tri-state when level-detect brake happened. 834 * | | |10 = PWM even channel output low level when level-detect brake happened. 835 * | | |11 = PWM even channel output high level when level-detect brake happened. 836 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 837 * |[19:18] |BRKAODD |PWM Brake Action Select for Odd Channel (Write Protect) 838 * | | |00 = PWM odd channel level-detect brake function not affect channel output. 839 * | | |01 = PWM odd channel output tri-state when level-detect brake happened. 840 * | | |10 = PWM odd channel output low level when level-detect brake happened. 841 * | | |11 = PWM odd channel output high level when level-detect brake happened. 842 * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. 843 * |[20] |EADC0EBEN |Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect) 844 * | | |0 = EADC0RM as edge-detect brake source Disabled. 845 * | | |1 = EADC0RM as edge-detect brake source Enabled. 846 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 847 * |[23] |VBSREBEN |UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect) 848 * | | |0 = UTCPD0 VBUS source disable as edge-detect brake source Disabled. 849 * | | |1 = UTCPD0 VBUS source disable as edge-detect brake source Enabled. 850 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 851 * |[28] |EADC0LBEN |Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect) 852 * | | |0 = EADC0RM as level-detect brake source Disabled. 853 * | | |1 = EADC0RM as level-detect brake source Enabled. 854 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 855 * |[31] |VBSRLBEN |UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect) 856 * | | |0 = UTCPD0 VBUS source disable as level-detect brake source Disabled. 857 * | | |1 = UTCPD0 VBUS source disable as level-detect brake source Enabled. 858 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 859 * @var PWM_T::POLCTL 860 * Offset: 0xD4 PWM Pin Polar Inverse Register 861 * --------------------------------------------------------------------------------------------------- 862 * |Bits |Field |Descriptions 863 * | :----: | :----: | :---- | 864 * |[0] |PINV0 |PWM PIN Polar Inverse Control 865 * | | |The register controls polarity state of PWM output. 866 * | | |0 = PWM output polar inverse Disabled. 867 * | | |1 = PWM output polar inverse Enabled. 868 * |[1] |PINV1 |PWM PIN Polar Inverse Control 869 * | | |The register controls polarity state of PWM output. 870 * | | |0 = PWM output polar inverse Disabled. 871 * | | |1 = PWM output polar inverse Enabled. 872 * |[2] |PINV2 |PWM PIN Polar Inverse Control 873 * | | |The register controls polarity state of PWM output. 874 * | | |0 = PWM output polar inverse Disabled. 875 * | | |1 = PWM output polar inverse Enabled. 876 * |[3] |PINV3 |PWM PIN Polar Inverse Control 877 * | | |The register controls polarity state of PWM output. 878 * | | |0 = PWM output polar inverse Disabled. 879 * | | |1 = PWM output polar inverse Enabled. 880 * |[4] |PINV4 |PWM PIN Polar Inverse Control 881 * | | |The register controls polarity state of PWM output. 882 * | | |0 = PWM output polar inverse Disabled. 883 * | | |1 = PWM output polar inverse Enabled. 884 * |[5] |PINV5 |PWM PIN Polar Inverse Control 885 * | | |The register controls polarity state of PWM output. 886 * | | |0 = PWM output polar inverse Disabled. 887 * | | |1 = PWM output polar inverse Enabled. 888 * @var PWM_T::POEN 889 * Offset: 0xD8 PWM Output Enable Register 890 * --------------------------------------------------------------------------------------------------- 891 * |Bits |Field |Descriptions 892 * | :----: | :----: | :---- | 893 * |[0] |POEN0 |PWM Pin Output Enable Bits 894 * | | |0 = PWM pin at tri-state. 895 * | | |1 = PWM pin in output mode. 896 * |[1] |POEN1 |PWM Pin Output Enable Bits 897 * | | |0 = PWM pin at tri-state. 898 * | | |1 = PWM pin in output mode. 899 * |[2] |POEN2 |PWM Pin Output Enable Bits 900 * | | |0 = PWM pin at tri-state. 901 * | | |1 = PWM pin in output mode. 902 * |[3] |POEN3 |PWM Pin Output Enable Bits 903 * | | |0 = PWM pin at tri-state. 904 * | | |1 = PWM pin in output mode. 905 * |[4] |POEN4 |PWM Pin Output Enable Bits 906 * | | |0 = PWM pin at tri-state. 907 * | | |1 = PWM pin in output mode. 908 * |[5] |POEN5 |PWM Pin Output Enable Bits 909 * | | |0 = PWM pin at tri-state. 910 * | | |1 = PWM pin in output mode. 911 * @var PWM_T::SWBRK 912 * Offset: 0xDC PWM Software Brake Control Register 913 * --------------------------------------------------------------------------------------------------- 914 * |Bits |Field |Descriptions 915 * | :----: | :----: | :---- | 916 * |[0] |BRKETRG0 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) 917 * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. 918 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 919 * |[1] |BRKETRG2 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) 920 * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. 921 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 922 * |[2] |BRKETRG4 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) 923 * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. 924 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 925 * |[8] |BRKLTRG0 |PWM Level Brake Software Trigger (Write Only) (Write Protect) 926 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. 927 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 928 * |[9] |BRKLTRG2 |PWM Level Brake Software Trigger (Write Only) (Write Protect) 929 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. 930 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 931 * |[10] |BRKLTRG4 |PWM Level Brake Software Trigger (Write Only) (Write Protect) 932 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. 933 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 934 * @var PWM_T::INTEN0 935 * Offset: 0xE0 PWM Interrupt Enable Register 0 936 * --------------------------------------------------------------------------------------------------- 937 * |Bits |Field |Descriptions 938 * | :----: | :----: | :---- | 939 * |[0] |ZIEN0 |PWM Zero Point Interrupt Enable Bit 0 940 * | | |0 = Zero point interrupt Disabled. 941 * | | |1 = Zero point interrupt Enabled. 942 * | | |Note: Odd channels will read always 0 at complementary mode. 943 * |[2] |ZIEN2 |PWM Zero Point Interrupt Enable Bit 2 944 * | | |0 = Zero point interrupt Disabled. 945 * | | |1 = Zero point interrupt Enabled. 946 * | | |Note: Odd channels will read always 0 at complementary mode. 947 * |[4] |ZIEN4 |PWM Zero Point Interrupt Enable Bit 4 948 * | | |0 = Zero point interrupt Disabled. 949 * | | |1 = Zero point interrupt Enabled. 950 * | | |Note: Odd channels will read always 0 at complementary mode. 951 * |[8] |PIEN0 |PWM Period Point Interrupt Enable Bit 0 952 * | | |0 = Period point interrupt Disabled. 953 * | | |1 = Period point interrupt Enabled. 954 * | | |Note: When up-down counter type, period point means center point. 955 * |[10] |PIEN2 |PWM Period Point Interrupt Enable Bit 2 956 * | | |0 = Period point interrupt Disabled. 957 * | | |1 = Period point interrupt Enabled. 958 * | | |Note: When up-down counter type, period point means center point. 959 * |[12] |PIEN4 |PWM Period Point Interrupt Enable Bit 4 960 * | | |0 = Period point interrupt Disabled. 961 * | | |1 = Period point interrupt Enabled. 962 * | | |Note: When up-down counter type, period point means center point. 963 * |[16] |CMPUIEN0 |PWM Compare Up Count Interrupt Enable Bits 964 * | | |Each bit n controls the corresponding PWM channel n. 965 * | | |0 = Compare up count interrupt Disabled. 966 * | | |1 = Compare up count interrupt Enabled. 967 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 968 * |[17] |CMPUIEN1 |PWM Compare Up Count Interrupt Enable Bits 969 * | | |Each bit n controls the corresponding PWM channel n. 970 * | | |0 = Compare up count interrupt Disabled. 971 * | | |1 = Compare up count interrupt Enabled. 972 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 973 * |[18] |CMPUIEN2 |PWM Compare Up Count Interrupt Enable Bits 974 * | | |Each bit n controls the corresponding PWM channel n. 975 * | | |0 = Compare up count interrupt Disabled. 976 * | | |1 = Compare up count interrupt Enabled. 977 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 978 * |[19] |CMPUIEN3 |PWM Compare Up Count Interrupt Enable Bits 979 * | | |Each bit n controls the corresponding PWM channel n. 980 * | | |0 = Compare up count interrupt Disabled. 981 * | | |1 = Compare up count interrupt Enabled. 982 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 983 * |[20] |CMPUIEN4 |PWM Compare Up Count Interrupt Enable Bits 984 * | | |Each bit n controls the corresponding PWM channel n. 985 * | | |0 = Compare up count interrupt Disabled. 986 * | | |1 = Compare up count interrupt Enabled. 987 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 988 * |[21] |CMPUIEN5 |PWM Compare Up Count Interrupt Enable Bits 989 * | | |Each bit n controls the corresponding PWM channel n. 990 * | | |0 = Compare up count interrupt Disabled. 991 * | | |1 = Compare up count interrupt Enabled. 992 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 993 * |[24] |CMPDIEN0 |PWM Compare Down Count Interrupt Enable Bits 994 * | | |0 = Compare down count interrupt Disabled. 995 * | | |1 = Compare down count interrupt Enabled. 996 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 997 * |[25] |CMPDIEN1 |PWM Compare Down Count Interrupt Enable Bits 998 * | | |0 = Compare down count interrupt Disabled. 999 * | | |1 = Compare down count interrupt Enabled. 1000 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1001 * |[26] |CMPDIEN2 |PWM Compare Down Count Interrupt Enable Bits 1002 * | | |0 = Compare down count interrupt Disabled. 1003 * | | |1 = Compare down count interrupt Enabled. 1004 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1005 * |[27] |CMPDIEN3 |PWM Compare Down Count Interrupt Enable Bits 1006 * | | |0 = Compare down count interrupt Disabled. 1007 * | | |1 = Compare down count interrupt Enabled. 1008 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1009 * |[28] |CMPDIEN4 |PWM Compare Down Count Interrupt Enable Bits 1010 * | | |0 = Compare down count interrupt Disabled. 1011 * | | |1 = Compare down count interrupt Enabled. 1012 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1013 * |[29] |CMPDIEN5 |PWM Compare Down Count Interrupt Enable Bits 1014 * | | |0 = Compare down count interrupt Disabled. 1015 * | | |1 = Compare down count interrupt Enabled. 1016 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1017 * @var PWM_T::INTEN1 1018 * Offset: 0xE4 PWM Interrupt Enable Register 1 1019 * --------------------------------------------------------------------------------------------------- 1020 * |Bits |Field |Descriptions 1021 * | :----: | :----: | :---- | 1022 * |[0] |BRKEIEN0_1|PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1023 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1024 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. 1025 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1026 * |[1] |BRKEIEN2_3|PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1027 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. 1028 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. 1029 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1030 * |[2] |BRKEIEN4_5|PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1031 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. 1032 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. 1033 * | | |Note: This bitr is write protected. Refer to SYS_REGLCTL register. 1034 * |[8] |BRKLIEN0_1|PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1035 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. 1036 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. 1037 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1038 * |[9] |BRKLIEN2_3|PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1039 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. 1040 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. 1041 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1042 * |[10] |BRKLIEN4_5|PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1043 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. 1044 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. 1045 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1046 * @var PWM_T::INTSTS0 1047 * Offset: 0xE8 PWM Interrupt Flag Register 0 1048 * --------------------------------------------------------------------------------------------------- 1049 * |Bits |Field |Descriptions 1050 * | :----: | :----: | :---- | 1051 * |[0] |ZIF0 |PWM Zero Point Interrupt Flag 0 1052 * | | |This bit is set by hardware when PWM_CH0 counter reaches 0. 1053 * | | |Note: This bit can be cleared to 0 by software writing 1. 1054 * |[2] |ZIF2 |PWM Zero Point Interrupt Flag 2 1055 * | | |This bit is set by hardware when PWM_CH2 counter reaches 0. 1056 * | | |Note: This bit can be cleared to 0 by software writing 1. 1057 * |[4] |ZIF4 |PWM Zero Point Interrupt Flag 4 1058 * | | |This bit is set by hardware when PWM_CH4 counter reaches 0. 1059 * | | |Note: This bit can be cleared to 0 by software writing 1. 1060 * |[8] |PIF0 |PWM Period Point Interrupt Flag 0 1061 * | | |This bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0. 1062 * | | |Note: This bit can be cleared to 0 by software writing 1. 1063 * |[10] |PIF2 |PWM Period Point Interrupt Flag 2 1064 * | | |This bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2. 1065 * | | |Note: This bit can be cleared to 0 by software writing 1. 1066 * |[12] |PIF4 |PWM Period Point Interrupt Flag 4 1067 * | | |This bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4. 1068 * | | |Note: This bit can be cleared to 0 by software writing 1. 1069 * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag 1070 * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1071 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1072 * |[24] |CMPDIF0 |PWM Compare Down Count Interrupt Flag 1073 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1074 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1075 * |[25] |CMPDIF1 |PWM Compare Down Count Interrupt Flag 1076 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1077 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1078 * |[26] |CMPDIF2 |PWM Compare Down Count Interrupt Flag 1079 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1080 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1081 * |[27] |CMPDIF3 |PWM Compare Down Count Interrupt Flag 1082 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1083 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1084 * |[28] |CMPDIF4 |PWM Compare Down Count Interrupt Flag 1085 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1086 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1087 * |[29] |CMPDIF5 |PWM Compare Down Count Interrupt Flag 1088 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. 1089 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1090 * @var PWM_T::INTSTS1 1091 * Offset: 0xEC PWM Interrupt Flag Register 1 1092 * --------------------------------------------------------------------------------------------------- 1093 * |Bits |Field |Descriptions 1094 * | :----: | :----: | :---- | 1095 * |[0] |BRKEIF0 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1096 * | | |0 = PWM channel n edge-detect brake event do not happened. 1097 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1098 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1099 * |[1] |BRKEIF1 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1100 * | | |0 = PWM channel n edge-detect brake event do not happened. 1101 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1102 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1103 * |[2] |BRKEIF2 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1104 * | | |0 = PWM channel n edge-detect brake event do not happened. 1105 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1106 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1107 * |[3] |BRKEIF3 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1108 * | | |0 = PWM channel n edge-detect brake event do not happened. 1109 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1110 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1111 * |[4] |BRKEIF4 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1112 * | | |0 = PWM channel n edge-detect brake event do not happened. 1113 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1114 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1115 * |[5] |BRKEIF5 |PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) 1116 * | | |0 = PWM channel n edge-detect brake event do not happened. 1117 * | | |1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1118 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1119 * |[8] |BRKLIF0 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1120 * | | |0 = PWM channel n level-detect brake event do not happened. 1121 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1122 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1123 * |[9] |BRKLIF1 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1124 * | | |0 = PWM channel n level-detect brake event do not happened. 1125 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1126 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1127 * |[10] |BRKLIF2 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1128 * | | |0 = PWM channel n level-detect brake event do not happened. 1129 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1130 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1131 * |[11] |BRKLIF3 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1132 * | | |0 = PWM channel n level-detect brake event do not happened. 1133 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1134 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1135 * |[12] |BRKLIF4 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1136 * | | |0 = PWM channel n level-detect brake event do not happened. 1137 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1138 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1139 * |[13] |BRKLIF5 |PWM Channel n Level-detect Brake Interrupt Flag (Write Protect) 1140 * | | |0 = PWM channel n level-detect brake event do not happened. 1141 * | | |1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1142 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 1143 * |[16] |BRKESTS0 |PWM Channel n Edge-detect Brake Status (Read Only) 1144 * | | |0 = PWM channel n edge-detect brake state is released. 1145 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1146 * | | |Note: This bit is read only and auto cleared by hardware 1147 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1148 * | | |The PWM waveform will start output from next full PWM period. 1149 * |[17] |BRKESTS1 |PWM Channel n Edge-detect Brake Status (Read Only) 1150 * | | |0 = PWM channel n edge-detect brake state is released. 1151 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1152 * | | |Note: This bit is read only and auto cleared by hardware 1153 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1154 * | | |The PWM waveform will start output from next full PWM period. 1155 * |[18] |BRKESTS2 |PWM Channel n Edge-detect Brake Status (Read Only) 1156 * | | |0 = PWM channel n edge-detect brake state is released. 1157 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1158 * | | |Note: This bit is read only and auto cleared by hardware 1159 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1160 * | | |The PWM waveform will start output from next full PWM period. 1161 * |[19] |BRKESTS3 |PWM Channel n Edge-detect Brake Status (Read Only) 1162 * | | |0 = PWM channel n edge-detect brake state is released. 1163 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1164 * | | |Note: This bit is read only and auto cleared by hardware 1165 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1166 * | | |The PWM waveform will start output from next full PWM period. 1167 * |[20] |BRKESTS4 |PWM Channel n Edge-detect Brake Status (Read Only) 1168 * | | |0 = PWM channel n edge-detect brake state is released. 1169 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1170 * | | |Note: This bit is read only and auto cleared by hardware 1171 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1172 * | | |The PWM waveform will start output from next full PWM period. 1173 * |[21] |BRKESTS5 |PWM Channel n Edge-detect Brake Status (Read Only) 1174 * | | |0 = PWM channel n edge-detect brake state is released. 1175 * | | |1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1176 * | | |Note: This bit is read only and auto cleared by hardware 1177 * | | |When edge-detect brake interrupt flag is cleared, PWM will release brake state until current PWM period finished 1178 * | | |The PWM waveform will start output from next full PWM period. 1179 * |[24] |BRKLSTS0 |PWM Channel n Level-detect Brake Status (Read Only) 1180 * | | |0 = PWM channel n level-detect brake state is released. 1181 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1182 * | | |Note: This bit is read only and auto cleared by hardware 1183 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1184 * | | |The PWM waveform will start output from next full PWM period. 1185 * |[25] |BRKLSTS1 |PWM Channel n Level-detect Brake Status (Read Only) 1186 * | | |0 = PWM channel n level-detect brake state is released. 1187 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1188 * | | |Note: This bit is read only and auto cleared by hardware 1189 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1190 * | | |The PWM waveform will start output from next full PWM period. 1191 * |[26] |BRKLSTS2 |PWM Channel n Level-detect Brake Status (Read Only) 1192 * | | |0 = PWM channel n level-detect brake state is released. 1193 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1194 * | | |Note: This bit is read only and auto cleared by hardware 1195 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1196 * | | |The PWM waveform will start output from next full PWM period. 1197 * |[27] |BRKLSTS3 |PWM Channel n Level-detect Brake Status (Read Only) 1198 * | | |0 = PWM channel n level-detect brake state is released. 1199 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1200 * | | |Note: This bit is read only and auto cleared by hardware 1201 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1202 * | | |The PWM waveform will start output from next full PWM period. 1203 * |[28] |BRKLSTS4 |PWM Channel n Level-detect Brake Status (Read Only) 1204 * | | |0 = PWM channel n level-detect brake state is released. 1205 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1206 * | | |Note: This bit is read only and auto cleared by hardware 1207 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1208 * | | |The PWM waveform will start output from next full PWM period. 1209 * |[29] |BRKLSTS5 |PWM Channel n Level-detect Brake Status (Read Only) 1210 * | | |0 = PWM channel n level-detect brake state is released. 1211 * | | |1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state. 1212 * | | |Note: This bit is read only and auto cleared by hardware 1213 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished 1214 * | | |The PWM waveform will start output from next full PWM period. 1215 * @var PWM_T::DACTRGEN 1216 * Offset: 0xF4 PWM Trigger DAC Enable Register 1217 * --------------------------------------------------------------------------------------------------- 1218 * |Bits |Field |Descriptions 1219 * | :----: | :----: | :---- | 1220 * |[0] |ZTE0 |PWM Zero Point Trigger DAC Enable Bit 0 1221 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. 1222 * | | |0 = PWM period point trigger DAC function Disabled. 1223 * | | |1 = PWM period point trigger DAC function Enabled. 1224 * |[2] |ZTE2 |PWM Zero Point Trigger DAC Enable Bit 2 1225 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. 1226 * | | |0 = PWM period point trigger DAC function Disabled. 1227 * | | |1 = PWM period point trigger DAC function Enabled. 1228 * |[4] |ZTE4 |PWM Zero Point Trigger DAC Enable Bit 4 1229 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. 1230 * | | |0 = PWM period point trigger DAC function Disabled. 1231 * | | |1 = PWM period point trigger DAC function Enabled. 1232 * |[8] |PTE0 |PWM Period Point Trigger DAC Enable Bit 0 1233 * | | |PWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1. 1234 * | | |0 = PWM period point trigger DAC function Disabled. 1235 * | | |1 = PWM period point trigger DAC function Enabled. 1236 * |[10] |PTE2 |PWM Period Point Trigger DAC Enable Bit 2 1237 * | | |PWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1. 1238 * | | |0 = PWM period point trigger DAC function Disabled. 1239 * | | |1 = PWM period point trigger DAC function Enabled. 1240 * |[12] |PTE4 |PWM Period Point Trigger DAC Enable Bit 4 1241 * | | |PWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1. 1242 * | | |0 = PWM period point trigger DAC function Disabled. 1243 * | | |1 = PWM period point trigger DAC function Enabled. 1244 * |[16] |CUTRGEN0 |PWM Compare Up Count Point Trigger DAC Enable Bits 1245 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1246 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1247 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1248 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1249 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1250 * |[17] |CUTRGEN1 |PWM Compare Up Count Point Trigger DAC Enable Bits 1251 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1252 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1253 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1254 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1255 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1256 * |[18] |CUTRGEN2 |PWM Compare Up Count Point Trigger DAC Enable Bits 1257 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1258 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1259 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1260 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1261 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1262 * |[19] |CUTRGEN3 |PWM Compare Up Count Point Trigger DAC Enable Bits 1263 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1264 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1265 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1266 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1267 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1268 * |[20] |CUTRGEN4 |PWM Compare Up Count Point Trigger DAC Enable Bits 1269 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1270 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1271 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1272 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1273 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1274 * |[21] |CUTRGEN5 |PWM Compare Up Count Point Trigger DAC Enable Bits 1275 * | | |PWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1. 1276 * | | |0 = PWM Compare Up point trigger DAC function Disabled. 1277 * | | |1 = PWM Compare Up point trigger DAC function Enabled. 1278 * | | |Note 1: This bit should keep at 0 when PWM counter operating in down counter type. 1279 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1280 * |[24] |CDTRGEN0 |PWM Compare Down Count Point Trigger DAC Enable Bits 1281 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1282 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1283 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1284 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1285 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1286 * |[25] |CDTRGEN1 |PWM Compare Down Count Point Trigger DAC Enable Bits 1287 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1288 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1289 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1290 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1291 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1292 * |[26] |CDTRGEN2 |PWM Compare Down Count Point Trigger DAC Enable Bits 1293 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1294 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1295 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1296 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1297 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1298 * |[27] |CDTRGEN3 |PWM Compare Down Count Point Trigger DAC Enable Bits 1299 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1300 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1301 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1302 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1303 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1304 * |[28] |CDTRGEN4 |PWM Compare Down Count Point Trigger DAC Enable Bits 1305 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1306 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1307 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1308 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1309 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1310 * |[29] |CDTRGEN5 |PWM Compare Down Count Point Trigger DAC Enable Bits 1311 * | | |PWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1. 1312 * | | |0 = PWM Compare Down count point trigger DAC function Disabled. 1313 * | | |1 = PWM Compare Down count point trigger DAC function Enabled. 1314 * | | |Note 1: This bit should keep at 0 when PWM counter operating in up counter type. 1315 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1316 * @var PWM_T::EADCTS0 1317 * Offset: 0xF8 PWM Trigger EADC Source Select Register 0 1318 * --------------------------------------------------------------------------------------------------- 1319 * |Bits |Field |Descriptions 1320 * | :----: | :----: | :---- | 1321 * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select 1322 * | | |0000 = PWM_CH0 zero point. 1323 * | | |0001 = PWM_CH0 period point. 1324 * | | |0010 = PWM_CH0 zero or period point. 1325 * | | |0011 = PWM_CH0 up-count CMPDAT point. 1326 * | | |0100 = PWM_CH0 down-count CMPDAT point. 1327 * | | |0101 = Reserved. 1328 * | | |0110 = Reserved. 1329 * | | |0111 = Reserved. 1330 * | | |1000 = PWM_CH1 up-count CMPDAT point. 1331 * | | |1001 = PWM_CH1 down-count CMPDAT point. 1332 * | | |Others = reserved. 1333 * |[7] |TRGEN0 |PWM_CH0 Trigger EADC Enable Bit 1334 * | | |0 = PWM_CH0 Trigger EADC function Disabled. 1335 * | | |1 = PWM_CH0 Trigger EADC function Enabled. 1336 * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select 1337 * | | |0000 = PWM_CH0 zero point. 1338 * | | |0001 = PWM_CH0 period point. 1339 * | | |0010 = PWM_CH0 zero or period point. 1340 * | | |0011 = PWM_CH0 up-count CMPDAT point. 1341 * | | |0100 = PWM_CH0 down-count CMPDAT point. 1342 * | | |0101 = Reserved. 1343 * | | |0110 = Reserved. 1344 * | | |0111 = Reserved. 1345 * | | |1000 = PWM_CH1 up-count CMPDAT point. 1346 * | | |1001 = PWM_CH1 down-count CMPDAT point. 1347 * | | |Others = reserved. 1348 * |[15] |TRGEN1 |PWM_CH1 Trigger EADC Enable Bit 1349 * | | |0 = PWM_CH1 Trigger EADC function Disabled. 1350 * | | |1 = PWM_CH1 Trigger EADC function Enabled. 1351 * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select 1352 * | | |0000 = PWM_CH2 zero point. 1353 * | | |0001 = PWM_CH2 period point. 1354 * | | |0010 = PWM_CH2 zero or period point. 1355 * | | |0011 = PWM_CH2 up-count CMPDAT point. 1356 * | | |0100 = PWM_CH2 down-count CMPDAT point. 1357 * | | |0101 = Reserved. 1358 * | | |0110 = Reserved. 1359 * | | |0111 = Reserved. 1360 * | | |1000 = PWM_CH3 up-count CMPDAT point. 1361 * | | |1001 = PWM_CH3 down-count CMPDAT point. 1362 * | | |Others = reserved. 1363 * |[23] |TRGEN2 |PWM_CH2 Trigger EADC Enable Bit 1364 * | | |0 = PWM_CH2 Trigger EADC function Disabled. 1365 * | | |1 = PWM_CH2 Trigger EADC function Enabled. 1366 * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select 1367 * | | |0000 = PWM_CH2 zero point. 1368 * | | |0001 = PWM_CH2 period point. 1369 * | | |0010 = PWM_CH2 zero or period point. 1370 * | | |0011 = PWM_CH2 up-count CMPDAT point. 1371 * | | |0100 = PWM_CH2 down-count CMPDAT point. 1372 * | | |0101 = Reserved. 1373 * | | |0110 = Reserved. 1374 * | | |0111 = Reserved. 1375 * | | |1000 = PWM_CH3 up-count CMPDAT point. 1376 * | | |1001 = PWM_CH3 down-count CMPDAT point. 1377 * | | |Others = reserved. 1378 * |[31] |TRGEN3 |PWM_CH3 Trigger EADC Enable Bit 1379 * | | |0 = PWM_CH3 Trigger EADC function Disabled. 1380 * | | |1 = PWM_CH3 Trigger EADC function Enabled. 1381 * @var PWM_T::EADCTS1 1382 * Offset: 0xFC PWM Trigger EADC Source Select Register 1 1383 * --------------------------------------------------------------------------------------------------- 1384 * |Bits |Field |Descriptions 1385 * | :----: | :----: | :---- | 1386 * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select 1387 * | | |0000 = PWM_CH4 zero point. 1388 * | | |0001 = PWM_CH4 period point. 1389 * | | |0010 = PWM_CH4 zero or period point. 1390 * | | |0011 = PWM_CH4 up-count CMPDAT point. 1391 * | | |0100 = PWM_CH4 down-count CMPDAT point. 1392 * | | |0101 = Reserved. 1393 * | | |0110 = Reserved. 1394 * | | |0111 = Reserved. 1395 * | | |1000 = PWM_CH5 up-count CMPDAT point. 1396 * | | |1001 = PWM_CH5 down-count CMPDAT point. 1397 * | | |Others = reserved. 1398 * |[7] |TRGEN4 |PWM_CH4 Trigger EADC Enable Bit 1399 * | | |0 = PWM_CH4 Trigger EADC function Disabled. 1400 * | | |1 = PWM_CH4 Trigger EADC function Enabled. 1401 * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select 1402 * | | |0000 = PWM_CH4 zero point. 1403 * | | |0001 = PWM_CH4 period point. 1404 * | | |0010 = PWM_CH4 zero or period point. 1405 * | | |0011 = PWM_CH4 up-count CMPDAT point. 1406 * | | |0100 = PWM_CH4 down-count CMPDAT point. 1407 * | | |0101 = Reserved. 1408 * | | |0110 = Reserved. 1409 * | | |0111 = Reserved. 1410 * | | |1000 = PWM_CH5 up-count CMPDAT point. 1411 * | | |1001 = PWM_CH5 down-count CMPDAT point. 1412 * | | |Others = reserved. 1413 * |[15] |TRGEN5 |PWM_CH5 Trigger EADC Enable Bit 1414 * | | |0 = PWM_CH5 Trigger EADC function Disabled. 1415 * | | |1 = PWM_CH5 Trigger EADC function Enabled. 1416 * @var PWM_T::SSCTL 1417 * Offset: 0x110 PWM Synchronous Start Control Register 1418 * --------------------------------------------------------------------------------------------------- 1419 * |Bits |Field |Descriptions 1420 * | :----: | :----: | :---- | 1421 * |[0] |SSEN0 |PWM Synchronous Start Function Enable Bit 0 1422 * | | |When synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 1423 * | | |0 = PWM synchronous start function Disabled. 1424 * | | |1 = PWM synchronous start function Enabled. 1425 * |[2] |SSEN2 |PWM Synchronous Start Function Enable Bit 2 1426 * | | |When synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 1427 * | | |0 = PWM synchronous start function Disabled. 1428 * | | |1 = PWM synchronous start function Enabled. 1429 * |[4] |SSEN4 |PWM Synchronous Start Function Enable Bit 4 1430 * | | |When synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). 1431 * | | |0 = PWM synchronous start function Disabled. 1432 * | | |1 = PWM synchronous start function Enabled. 1433 * |[9:8] |SSRC |PWM Synchronous Start Source Select Bits 1434 * | | |00 = Synchronous start source come from EPWM0. 1435 * | | |01 = Synchronous start source come from EPWM1. 1436 * | | |10 = Synchronous start source come from PWM0. 1437 * | | |11 = Synchronous start source come from PWM1. 1438 * @var PWM_T::SSTRG 1439 * Offset: 0x114 PWM Synchronous Start Trigger Register 1440 * --------------------------------------------------------------------------------------------------- 1441 * |Bits |Field |Descriptions 1442 * | :----: | :----: | :---- | 1443 * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only) 1444 * | | |PWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time. 1445 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n = 0, 2, 4) if correlated PWM channel counter synchronous start function is enabled. 1446 * @var PWM_T::STATUS 1447 * Offset: 0x120 PWM Status Register 1448 * --------------------------------------------------------------------------------------------------- 1449 * |Bits |Field |Descriptions 1450 * | :----: | :----: | :---- | 1451 * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Flag 1452 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1453 * | | |1 = indicates the time-base counter reached its maximum value. 1454 * | | |Note: This bit can be cleared by software writing 1. 1455 * |[2] |CNTMAX2 |Time-base Counter 2 Equal to 0xFFFF Latched Flag 1456 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1457 * | | |1 = indicates the time-base counter reached its maximum value. 1458 * | | |Note: This bit can be cleared by software writing 1. 1459 * |[4] |CNTMAX4 |Time-base Counter 4 Equal to 0xFFFF Latched Flag 1460 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1461 * | | |1 = The time-base counter reached its maximum value. 1462 * | | |Note: This bit can be cleared by software writing 1. 1463 * |[16] |EADCTRG0 |EADC Start of Conversion Status 1464 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1465 * | | |1 = An EADC start of conversion trigger event has occurred. 1466 * | | |Note: This bit can be cleared by software writing 1. 1467 * |[17] |EADCTRG1 |EADC Start of Conversion Status 1468 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1469 * | | |1 = An EADC start of conversion trigger event has occurred. 1470 * | | |Note: This bit can be cleared by software writing 1. 1471 * |[18] |EADCTRG2 |EADC Start of Conversion Status 1472 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1473 * | | |1 = An EADC start of conversion trigger event has occurred. 1474 * | | |Note: This bit can be cleared by software writing 1. 1475 * |[19] |EADCTRG3 |EADC Start of Conversion Status 1476 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1477 * | | |1 = An EADC start of conversion trigger event has occurred. 1478 * | | |Note: This bit can be cleared by software writing 1. 1479 * |[20] |EADCTRG4 |EADC Start of Conversion Status 1480 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1481 * | | |1 = An EADC start of conversion trigger event has occurred. 1482 * | | |Note: This bit can be cleared by software writing 1. 1483 * |[21] |EADCTRG5 |EADC Start of Conversion Status 1484 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1485 * | | |1 = An EADC start of conversion trigger event has occurred. 1486 * | | |Note: This bit can be cleared by software writing 1. 1487 * |[23] |LPADCTRG |LPADC Start of Conversion Status 1488 * | | |0 = Indicates no LPADC start of conversion trigger event has occurred. 1489 * | | |1 = An LPADC start of conversion trigger event has occurred. 1490 * | | |Note: This bit can be cleared by software writing 1. 1491 * |[24] |DACTRGF |DAC Start of Conversion Flag 1492 * | | |0 = No DAC start of conversion trigger event has occurred. 1493 * | | |1 = A DAC start of conversion trigger event has occurred. 1494 * | | |Note: This bit can be cleared by software writing 1. 1495 * @var PWM_T::IFA[6] 1496 * Offset: 0x130 PWM Interrupt Flag Accumulator Register 0/2/4 1497 * --------------------------------------------------------------------------------------------------- 1498 * |Bits |Field |Descriptions 1499 * | :----: | :----: | :---- | 1500 * |[7:0] |IFACNT |PWM_CHn Interrupt Flag Counter 1501 * | | |The register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt 1502 * | | |PWM flag will be set in every IFACNT[15:0] times of PWM period. 1503 * |[24] |STPMOD |PWM_CHn Accumulator Stop Mode Enable Bits 1504 * | | |0 = PWM_CHn Stop Mode Disable. 1505 * | | |1 = PWM_CHn Stop Mode Enable. 1506 * |[29:28] |IFASEL |PWM_CHn Interrupt Flag Accumulator Source Select 1507 * | | |00 = PWM_CHn zero point. 1508 * | | |01 = PWM_CHn period in channel n. 1509 * | | |10 = PWM_CHn up-count compared point. 1510 * | | |11 = PWM_CHn down-count compared point. 1511 * |[31] |IFAEN |PWM_CHn Interrupt Flag Accumulator Enable Bits 1512 * | | |0 = PWM_CHn interrupt flag accumulator Disabled. 1513 * | | |1 = PWM_CHn interrupt flag accumulator Enabled. 1514 * @var PWM_T::AINTSTS 1515 * Offset: 0x150 PWM Accumulator Interrupt Flag Register 1516 * --------------------------------------------------------------------------------------------------- 1517 * |Bits |Field |Descriptions 1518 * | :----: | :----: | :---- | 1519 * |[0] |IFAIF0 |PWM_CH0 Interrupt Flag Accumulator Interrupt Flag 1520 * | | |Flag is set by hardware when condition match IFASEL in PWM_IFAn register, software can clear this bit by writing 1 to it. 1521 * |[2] |IFAIF2 |PWM_CH2 Interrupt Flag Accumulator Interrupt Flag 1522 * | | |Flag is set by hardware when condition match IFASEL in PWM_IFAn register, software can clear this bit by writing 1 to it. 1523 * |[4] |IFAIF4 |PWM_CH4 Interrupt Flag Accumulator Interrupt Flag 1524 * | | |Flag is set by hardware when condition match IFASEL in PWM_IFAn register, software can clear this bit by writing 1 to it. 1525 * @var PWM_T::AINTEN 1526 * Offset: 0x154 PWM Accumulator Interrupt Enable Register 1527 * --------------------------------------------------------------------------------------------------- 1528 * |Bits |Field |Descriptions 1529 * | :----: | :----: | :---- | 1530 * |[0] |IFAIEN0 |PWM_CH0 Interrupt Flag Accumulator Interrupt Enable Bits 1531 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1532 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1533 * |[2] |IFAIEN2 |PWM_CH2 Interrupt Flag Accumulator Interrupt Enable Bits 1534 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1535 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1536 * |[4] |IFAIEN4 |PWM_CH4 Interrupt Flag Accumulator Interrupt Enable Bits 1537 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1538 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1539 * @var PWM_T::APDMACTL 1540 * Offset: 0x158 PWM Accumulator PDMA Control Register 1541 * --------------------------------------------------------------------------------------------------- 1542 * |Bits |Field |Descriptions 1543 * | :----: | :----: | :---- | 1544 * |[0] |APDMAEN0 |Channel n Accumulator PDMA Enable Bits 1545 * | | |0 = Channel n PDMA function Disabled. 1546 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1547 * |[1] |APDMAEN1 |Channel n Accumulator PDMA Enable Bits 1548 * | | |0 = Channel n PDMA function Disabled. 1549 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1550 * |[2] |APDMAEN2 |Channel n Accumulator PDMA Enable Bits 1551 * | | |0 = Channel n PDMA function Disabled. 1552 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1553 * |[3] |APDMAEN3 |Channel n Accumulator PDMA Enable Bits 1554 * | | |0 = Channel n PDMA function Disabled. 1555 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1556 * |[4] |APDMAEN4 |Channel n Accumulator PDMA Enable Bits 1557 * | | |0 = Channel n PDMA function Disabled. 1558 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1559 * |[5] |APDMAEN5 |Channel n Accumulator PDMA Enable Bits 1560 * | | |0 = Channel n PDMA function Disabled. 1561 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1562 * @var PWM_T::CAPINEN 1563 * Offset: 0x200 PWM Capture Input Enable Register 1564 * --------------------------------------------------------------------------------------------------- 1565 * |Bits |Field |Descriptions 1566 * | :----: | :----: | :---- | 1567 * |[0] |CAPINEN0 |Capture Input Enable Bits 1568 * | | |0 = PWM Channel capture input path Disabled 1569 * | | |The input of PWM channel capture function is always regarded as 0. 1570 * | | |1 = PWM Channel capture input path Enabled 1571 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1572 * |[1] |CAPINEN1 |Capture Input Enable Bits 1573 * | | |0 = PWM Channel capture input path Disabled 1574 * | | |The input of PWM channel capture function is always regarded as 0. 1575 * | | |1 = PWM Channel capture input path Enabled 1576 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1577 * |[2] |CAPINEN2 |Capture Input Enable Bits 1578 * | | |0 = PWM Channel capture input path Disabled 1579 * | | |The input of PWM channel capture function is always regarded as 0. 1580 * | | |1 = PWM Channel capture input path Enabled 1581 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1582 * |[3] |CAPINEN3 |Capture Input Enable Bits 1583 * | | |0 = PWM Channel capture input path Disabled 1584 * | | |The input of PWM channel capture function is always regarded as 0. 1585 * | | |1 = PWM Channel capture input path Enabled 1586 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1587 * |[4] |CAPINEN4 |Capture Input Enable Bits 1588 * | | |0 = PWM Channel capture input path Disabled 1589 * | | |The input of PWM channel capture function is always regarded as 0. 1590 * | | |1 = PWM Channel capture input path Enabled 1591 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1592 * |[5] |CAPINEN5 |Capture Input Enable Bits 1593 * | | |0 = PWM Channel capture input path Disabled 1594 * | | |The input of PWM channel capture function is always regarded as 0. 1595 * | | |1 = PWM Channel capture input path Enabled 1596 * | | |The input of PWM channel capture function comes from correlative multifunction pin. 1597 * @var PWM_T::CAPCTL 1598 * Offset: 0x204 PWM Capture Control Register 1599 * --------------------------------------------------------------------------------------------------- 1600 * |Bits |Field |Descriptions 1601 * | :----: | :----: | :---- | 1602 * |[0] |CAPEN0 |Capture Function Enable Bits 1603 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1604 * | | |1 = Capture function Enabled 1605 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1606 * |[1] |CAPEN1 |Capture Function Enable Bits 1607 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1608 * | | |1 = Capture function Enabled 1609 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1610 * |[2] |CAPEN2 |Capture Function Enable Bits 1611 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1612 * | | |1 = Capture function Enabled 1613 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1614 * |[3] |CAPEN3 |Capture Function Enable Bits 1615 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1616 * | | |1 = Capture function Enabled 1617 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1618 * |[4] |CAPEN4 |Capture Function Enable Bits 1619 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1620 * | | |1 = Capture function Enabled 1621 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1622 * |[5] |CAPEN5 |Capture Function Enable Bits 1623 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1624 * | | |1 = Capture function Enabled 1625 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1626 * |[8] |CAPINV0 |Capture Inverter Enable Bits 1627 * | | |0 = Capture source inverter Disabled. 1628 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1629 * |[9] |CAPINV1 |Capture Inverter Enable Bits 1630 * | | |0 = Capture source inverter Disabled. 1631 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1632 * |[10] |CAPINV2 |Capture Inverter Enable Bits 1633 * | | |0 = Capture source inverter Disabled. 1634 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1635 * |[11] |CAPINV3 |Capture Inverter Enable Bits 1636 * | | |0 = Capture source inverter Disabled. 1637 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1638 * |[12] |CAPINV4 |Capture Inverter Enable Bits 1639 * | | |0 = Capture source inverter Disabled. 1640 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1641 * |[13] |CAPINV5 |Capture Inverter Enable Bits 1642 * | | |0 = Capture source inverter Disabled. 1643 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1644 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 1645 * | | |0 = Rising capture reload counter Disabled. 1646 * | | |1 = Rising capture reload counter Enabled. 1647 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 1648 * | | |0 = Rising capture reload counter Disabled. 1649 * | | |1 = Rising capture reload counter Enabled. 1650 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 1651 * | | |0 = Rising capture reload counter Disabled. 1652 * | | |1 = Rising capture reload counter Enabled. 1653 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 1654 * | | |0 = Rising capture reload counter Disabled. 1655 * | | |1 = Rising capture reload counter Enabled. 1656 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 1657 * | | |0 = Rising capture reload counter Disabled. 1658 * | | |1 = Rising capture reload counter Enabled. 1659 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 1660 * | | |0 = Rising capture reload counter Disabled. 1661 * | | |1 = Rising capture reload counter Enabled. 1662 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 1663 * | | |0 = Falling capture reload counter Disabled. 1664 * | | |1 = Falling capture reload counter Enabled. 1665 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 1666 * | | |0 = Falling capture reload counter Disabled. 1667 * | | |1 = Falling capture reload counter Enabled. 1668 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 1669 * | | |0 = Falling capture reload counter Disabled. 1670 * | | |1 = Falling capture reload counter Enabled. 1671 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 1672 * | | |0 = Falling capture reload counter Disabled. 1673 * | | |1 = Falling capture reload counter Enabled. 1674 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 1675 * | | |0 = Falling capture reload counter Disabled. 1676 * | | |1 = Falling capture reload counter Enabled. 1677 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 1678 * | | |0 = Falling capture reload counter Disabled. 1679 * | | |1 = Falling capture reload counter Enabled. 1680 * @var PWM_T::CAPSTS 1681 * Offset: 0x208 PWM Capture Status Register 1682 * --------------------------------------------------------------------------------------------------- 1683 * |Bits |Field |Descriptions 1684 * | :----: | :----: | :---- | 1685 * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1686 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1687 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1688 * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1689 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1690 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1691 * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1692 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1693 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1694 * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1695 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1696 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1697 * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1698 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1699 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1700 * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1701 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1702 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1703 * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1704 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1705 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1706 * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1707 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1708 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1709 * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1710 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1711 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1712 * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1713 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1714 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1715 * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1716 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1717 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1718 * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1719 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1720 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1721 * @var PWM_T::RCAPDAT0 1722 * Offset: 0x20C PWM Rising Capture Data Register 0 1723 * --------------------------------------------------------------------------------------------------- 1724 * |Bits |Field |Descriptions 1725 * | :----: | :----: | :---- | 1726 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1727 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1728 * @var PWM_T::FCAPDAT0 1729 * Offset: 0x210 PWM Falling Capture Data Register 0 1730 * --------------------------------------------------------------------------------------------------- 1731 * |Bits |Field |Descriptions 1732 * | :----: | :----: | :---- | 1733 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1734 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1735 * @var PWM_T::RCAPDAT1 1736 * Offset: 0x214 PWM Rising Capture Data Register 1 1737 * --------------------------------------------------------------------------------------------------- 1738 * |Bits |Field |Descriptions 1739 * | :----: | :----: | :---- | 1740 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1741 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1742 * @var PWM_T::FCAPDAT1 1743 * Offset: 0x218 PWM Falling Capture Data Register 1 1744 * --------------------------------------------------------------------------------------------------- 1745 * |Bits |Field |Descriptions 1746 * | :----: | :----: | :---- | 1747 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1748 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1749 * @var PWM_T::RCAPDAT2 1750 * Offset: 0x21C PWM Rising Capture Data Register 2 1751 * --------------------------------------------------------------------------------------------------- 1752 * |Bits |Field |Descriptions 1753 * | :----: | :----: | :---- | 1754 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1755 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1756 * @var PWM_T::FCAPDAT2 1757 * Offset: 0x220 PWM Falling Capture Data Register 2 1758 * --------------------------------------------------------------------------------------------------- 1759 * |Bits |Field |Descriptions 1760 * | :----: | :----: | :---- | 1761 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1762 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1763 * @var PWM_T::RCAPDAT3 1764 * Offset: 0x224 PWM Rising Capture Data Register 3 1765 * --------------------------------------------------------------------------------------------------- 1766 * |Bits |Field |Descriptions 1767 * | :----: | :----: | :---- | 1768 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1769 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1770 * @var PWM_T::FCAPDAT3 1771 * Offset: 0x228 PWM Falling Capture Data Register 3 1772 * --------------------------------------------------------------------------------------------------- 1773 * |Bits |Field |Descriptions 1774 * | :----: | :----: | :---- | 1775 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1776 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1777 * @var PWM_T::RCAPDAT4 1778 * Offset: 0x22C PWM Rising Capture Data Register 4 1779 * --------------------------------------------------------------------------------------------------- 1780 * |Bits |Field |Descriptions 1781 * | :----: | :----: | :---- | 1782 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1783 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1784 * @var PWM_T::FCAPDAT4 1785 * Offset: 0x230 PWM Falling Capture Data Register 4 1786 * --------------------------------------------------------------------------------------------------- 1787 * |Bits |Field |Descriptions 1788 * | :----: | :----: | :---- | 1789 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1790 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1791 * @var PWM_T::RCAPDAT5 1792 * Offset: 0x234 PWM Rising Capture Data Register 5 1793 * --------------------------------------------------------------------------------------------------- 1794 * |Bits |Field |Descriptions 1795 * | :----: | :----: | :---- | 1796 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only) 1797 * | | |When rising capture condition happened, the PWM counter value will be saved in this register. 1798 * @var PWM_T::FCAPDAT5 1799 * Offset: 0x238 PWM Falling Capture Data Register 5 1800 * --------------------------------------------------------------------------------------------------- 1801 * |Bits |Field |Descriptions 1802 * | :----: | :----: | :---- | 1803 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only) 1804 * | | |When falling capture condition happened, the PWM counter value will be saved in this register. 1805 * @var PWM_T::PDMACTL 1806 * Offset: 0x23C PWM PDMA Control Register 1807 * --------------------------------------------------------------------------------------------------- 1808 * |Bits |Field |Descriptions 1809 * | :----: | :----: | :---- | 1810 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable Bit 1811 * | | |0 = Channel 0/1 PDMA function Disabled. 1812 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. 1813 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1814 * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer 1815 * | | |00 = Reserved. 1816 * | | |01 = PWM_RCAPDAT0/1. 1817 * | | |10 = PWM_FCAPDAT0/1. 1818 * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1. 1819 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1820 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order 1821 * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. 1822 * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory. 1823 * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory. 1824 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1825 * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer 1826 * | | |0 = Channel0. 1827 * | | |1 = Channel1. 1828 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1829 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable Bit 1830 * | | |0 = Channel 2/3 PDMA function Disabled. 1831 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. 1832 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1833 * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 1834 * | | |00 = Reserved. 1835 * | | |01 = PWM_RCAPDAT2/3. 1836 * | | |10 = PWM_FCAPDAT2/3. 1837 * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3. 1838 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1839 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order 1840 * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. 1841 * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory. 1842 * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory. 1843 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1844 * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer 1845 * | | |0 = Channel2. 1846 * | | |1 = Channel3. 1847 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1848 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable Bit 1849 * | | |0 = Channel 4/5 PDMA function Disabled. 1850 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. 1851 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1852 * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer 1853 * | | |00 = Reserved. 1854 * | | |01 = PWM_RCAPDAT4/5. 1855 * | | |10 = PWM_FCAPDAT4/5. 1856 * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5. 1857 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1858 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order 1859 * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. 1860 * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory. 1861 * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory. 1862 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1863 * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer 1864 * | | |0 = Channel4. 1865 * | | |1 = Channel5. 1866 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1867 * @var PWM_T::PDMACAP0_1 1868 * Offset: 0x240 PWM Capture Channel 01 PDMA Register 1869 * --------------------------------------------------------------------------------------------------- 1870 * |Bits |Field |Descriptions 1871 * | :----: | :----: | :---- | 1872 * |[15:0] |CAPBUF |PWM Capture PDMA Register (Read Only) 1873 * | | |This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 1874 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1875 * @var PWM_T::PDMACAP2_3 1876 * Offset: 0x244 PWM Capture Channel 23 PDMA Register 1877 * --------------------------------------------------------------------------------------------------- 1878 * |Bits |Field |Descriptions 1879 * | :----: | :----: | :---- | 1880 * |[15:0] |CAPBUF |PWM Capture PDMA Register (Read Only) 1881 * | | |This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 1882 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1883 * @var PWM_T::PDMACAP4_5 1884 * Offset: 0x248 PWM Capture Channel 45 PDMA Register 1885 * --------------------------------------------------------------------------------------------------- 1886 * |Bits |Field |Descriptions 1887 * | :----: | :----: | :---- | 1888 * |[15:0] |CAPBUF |PWM Capture PDMA Register (Read Only) 1889 * | | |This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 1890 * | | |Note: If the PDMA function is not supported, this bit field will become invalid. 1891 * @var PWM_T::CAPIEN 1892 * Offset: 0x250 PWM Capture Interrupt Enable Register 1893 * --------------------------------------------------------------------------------------------------- 1894 * |Bits |Field |Descriptions 1895 * | :----: | :----: | :---- | 1896 * |[0] |CAPRIEN0 |PWM Capture Rising Latch Interrupt Enable Bits 1897 * | | |0 = Capture rising edge latch interrupt Disabled. 1898 * | | |1 = Capture rising edge latch interrupt Enabled. 1899 * |[1] |CAPRIEN1 |PWM Capture Rising Latch Interrupt Enable Bits 1900 * | | |0 = Capture rising edge latch interrupt Disabled. 1901 * | | |1 = Capture rising edge latch interrupt Enabled. 1902 * |[2] |CAPRIEN2 |PWM Capture Rising Latch Interrupt Enable Bits 1903 * | | |0 = Capture rising edge latch interrupt Disabled. 1904 * | | |1 = Capture rising edge latch interrupt Enabled. 1905 * |[3] |CAPRIEN3 |PWM Capture Rising Latch Interrupt Enable Bits 1906 * | | |0 = Capture rising edge latch interrupt Disabled. 1907 * | | |1 = Capture rising edge latch interrupt Enabled. 1908 * |[4] |CAPRIEN4 |PWM Capture Rising Latch Interrupt Enable Bits 1909 * | | |0 = Capture rising edge latch interrupt Disabled. 1910 * | | |1 = Capture rising edge latch interrupt Enabled. 1911 * |[5] |CAPRIEN5 |PWM Capture Rising Latch Interrupt Enable Bits 1912 * | | |0 = Capture rising edge latch interrupt Disabled. 1913 * | | |1 = Capture rising edge latch interrupt Enabled. 1914 * |[8] |CAPFIEN0 |PWM Capture Falling Latch Interrupt Enable Bits 1915 * | | |0 = Capture falling edge latch interrupt Disabled. 1916 * | | |1 = Capture falling edge latch interrupt Enabled. 1917 * |[9] |CAPFIEN1 |PWM Capture Falling Latch Interrupt Enable Bits 1918 * | | |0 = Capture falling edge latch interrupt Disabled. 1919 * | | |1 = Capture falling edge latch interrupt Enabled. 1920 * |[10] |CAPFIEN2 |PWM Capture Falling Latch Interrupt Enable Bits 1921 * | | |0 = Capture falling edge latch interrupt Disabled. 1922 * | | |1 = Capture falling edge latch interrupt Enabled. 1923 * |[11] |CAPFIEN3 |PWM Capture Falling Latch Interrupt Enable Bits 1924 * | | |0 = Capture falling edge latch interrupt Disabled. 1925 * | | |1 = Capture falling edge latch interrupt Enabled. 1926 * |[12] |CAPFIEN4 |PWM Capture Falling Latch Interrupt Enable Bits 1927 * | | |0 = Capture falling edge latch interrupt Disabled. 1928 * | | |1 = Capture falling edge latch interrupt Enabled. 1929 * |[13] |CAPFIEN5 |PWM Capture Falling Latch Interrupt Enable Bits 1930 * | | |0 = Capture falling edge latch interrupt Disabled. 1931 * | | |1 = Capture falling edge latch interrupt Enabled. 1932 * @var PWM_T::CAPIF 1933 * Offset: 0x254 PWM Capture Interrupt Flag Register 1934 * --------------------------------------------------------------------------------------------------- 1935 * |Bits |Field |Descriptions 1936 * | :----: | :----: | :---- | 1937 * |[0] |CRLIF0 |PWM Capture Rising Latch Interrupt Flag 1938 * | | |0 = No capture rising latch condition happened. 1939 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1940 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1941 * | | |Note 2: This bit is cleared by writing 1 to it. 1942 * |[1] |CRLIF1 |PWM Capture Rising Latch Interrupt Flag 1943 * | | |0 = No capture rising latch condition happened. 1944 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1945 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1946 * | | |Note 2: This bit is cleared by writing 1 to it. 1947 * |[2] |CRLIF2 |PWM Capture Rising Latch Interrupt Flag 1948 * | | |0 = No capture rising latch condition happened. 1949 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1950 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1951 * | | |Note 2: This bit is cleared by writing 1 to it. 1952 * |[3] |CRLIF3 |PWM Capture Rising Latch Interrupt Flag 1953 * | | |0 = No capture rising latch condition happened. 1954 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1955 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1956 * | | |Note 2: This bit is cleared by writing 1 to it. 1957 * |[4] |CRLIF4 |PWM Capture Rising Latch Interrupt Flag 1958 * | | |0 = No capture rising latch condition happened. 1959 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1960 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1961 * | | |Note 2: This bit is cleared by writing 1 to it. 1962 * |[5] |CRLIF5 |PWM Capture Rising Latch Interrupt Flag 1963 * | | |0 = No capture rising latch condition happened. 1964 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1965 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. 1966 * | | |Note 2: This bit is cleared by writing 1 to it. 1967 * |[8] |CFLIF0 |PWM Capture Falling Latch Interrupt Flag 1968 * | | |0 = No capture falling latch condition happened. 1969 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1970 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1971 * | | |Note 2: This bit is cleared by writing 1 to it. 1972 * |[9] |CFLIF1 |PWM Capture Falling Latch Interrupt Flag 1973 * | | |0 = No capture falling latch condition happened. 1974 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1975 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1976 * | | |Note 2: This bit is cleared by writing 1 to it. 1977 * |[10] |CFLIF2 |PWM Capture Falling Latch Interrupt Flag 1978 * | | |0 = No capture falling latch condition happened. 1979 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1980 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1981 * | | |Note 2: This bit is cleared by writing 1 to it. 1982 * |[11] |CFLIF3 |PWM Capture Falling Latch Interrupt Flag 1983 * | | |0 = No capture falling latch condition happened. 1984 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1985 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1986 * | | |Note 2: This bit is cleared by writing 1 to it. 1987 * |[12] |CFLIF4 |PWM Capture Falling Latch Interrupt Flag 1988 * | | |0 = No capture falling latch condition happened. 1989 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1990 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1991 * | | |Note 2: This bit is cleared by writing 1 to it. 1992 * |[13] |CFLIF5 |PWM Capture Falling Latch Interrupt Flag 1993 * | | |0 = No capture falling latch condition happened. 1994 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1995 * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. 1996 * | | |Note 2: This bit is cleared by writing 1 to it. 1997 * @var PWM_T::CAPNF[6] 1998 * Offset: 0x258 PWM Capture Input Noise Filter Register 0~5 1999 * --------------------------------------------------------------------------------------------------- 2000 * |Bits |Field |Descriptions 2001 * | :----: | :----: | :---- | 2002 * |[0] |CAPNFEN |Capture Noise Filter Enable 2003 * | | |0 = Capture Noise Filter function Disabled. 2004 * | | |1 = Capture Noise Filter function Enabled. 2005 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2006 * | | |000 = Filter clock = PCLK. 2007 * | | |001 = Filter clock = PCLK/2. 2008 * | | |010 = Filter clock = PCLK/4. 2009 * | | |011 = Filter clock = PCLK/8. 2010 * | | |100 = Filter clock = PCLK/16. 2011 * | | |101 = Filter clock = PCLK/32. 2012 * | | |110 = Filter clock = PCLK/64. 2013 * | | |111 = Filter clock = PCLK/128. 2014 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2015 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2016 * @var PWM_T::EXTETCTL0 2017 * Offset: 0x270 PWM External Event Trigger Control Register 0 2018 * --------------------------------------------------------------------------------------------------- 2019 * |Bits |Field |Descriptions 2020 * | :----: | :----: | :---- | 2021 * |[0] |EXTETEN |External Event Trigger Enable Bit 2022 * | | |0 = External Event Trigger function Disabled. 2023 * | | |1 = External Event Trigger function Enabled. 2024 * |[5:4] |CNTACTS |Counter Action Selection 2025 * | | |00 = Counter reset. 2026 * | | |01 = Counter start. 2027 * | | |10 = Counter reset and start. 2028 * | | |11 = Reseved. 2029 * |[11:8] |EXTTRGS |External Trigger Selection 2030 * | | |0000 = INT0. 2031 * | | |0001 = INT1. 2032 * | | |0010 = INT2. 2033 * | | |0011 = INT3. 2034 * | | |0100 = INT4. 2035 * | | |0101 = INT5. 2036 * | | |0110 = INT6. 2037 * | | |0111 = INT7. 2038 * | | |Other = Resrved. 2039 * @var PWM_T::EXTETCTL2 2040 * Offset: 0x278 PWM External Event Trigger Control Register 2 2041 * --------------------------------------------------------------------------------------------------- 2042 * |Bits |Field |Descriptions 2043 * | :----: | :----: | :---- | 2044 * |[0] |EXTETEN |External Event Trigger Enable Bit 2045 * | | |0 = External Event Trigger function Disabled. 2046 * | | |1 = External Event Trigger function Enabled. 2047 * |[5:4] |CNTACTS |Counter Action Selection 2048 * | | |00 = Counter reset. 2049 * | | |01 = Counter start. 2050 * | | |10 = Counter reset and start. 2051 * | | |11 = Reseved. 2052 * |[11:8] |EXTTRGS |External Trigger Selection 2053 * | | |0000 = INT0. 2054 * | | |0001 = INT1. 2055 * | | |0010 = INT2. 2056 * | | |0011 = INT3. 2057 * | | |0100 = INT4. 2058 * | | |0101 = INT5. 2059 * | | |0110 = INT6. 2060 * | | |0111 = INT7. 2061 * | | |Other = Resrved. 2062 * @var PWM_T::EXTETCTL4 2063 * Offset: 0x280 PWM External Event Trigger Control Register 4 2064 * --------------------------------------------------------------------------------------------------- 2065 * |Bits |Field |Descriptions 2066 * | :----: | :----: | :---- | 2067 * |[0] |EXTETEN |External Event Trigger Enable Bit 2068 * | | |0 = External Event Trigger function Disabled. 2069 * | | |1 = External Event Trigger function Enabled. 2070 * |[5:4] |CNTACTS |Counter Action Selection 2071 * | | |00 = Counter reset. 2072 * | | |01 = Counter start. 2073 * | | |10 = Counter reset and start. 2074 * | | |11 = Reseved. 2075 * |[11:8] |EXTTRGS |External Trigger Selection 2076 * | | |0000 = INT0. 2077 * | | |0001 = INT1. 2078 * | | |0010 = INT2. 2079 * | | |0011 = INT3. 2080 * | | |0100 = INT4. 2081 * | | |0101 = INT5. 2082 * | | |0110 = INT6. 2083 * | | |0111 = INT7. 2084 * | | |Other = Resrved. 2085 * @var PWM_T::SWEOFCTL 2086 * Offset: 0x288 PWM Software Event Output Force Control Register 2087 * --------------------------------------------------------------------------------------------------- 2088 * |Bits |Field |Descriptions 2089 * | :----: | :----: | :---- | 2090 * |[1:0] |OUTACTS0 |Output Action Selection 2091 * | | |00 = Do nothing. 2092 * | | |01 = PWM output Low. 2093 * | | |10 = PWM output High. 2094 * | | |11 = PWM output Toggle. 2095 * |[3:2] |OUTACTS1 |Output Action Selection 2096 * | | |00 = Do nothing. 2097 * | | |01 = PWM output Low. 2098 * | | |10 = PWM output High. 2099 * | | |11 = PWM output Toggle. 2100 * |[5:4] |OUTACTS2 |Output Action Selection 2101 * | | |00 = Do nothing. 2102 * | | |01 = PWM output Low. 2103 * | | |10 = PWM output High. 2104 * | | |11 = PWM output Toggle. 2105 * |[7:6] |OUTACTS3 |Output Action Selection 2106 * | | |00 = Do nothing. 2107 * | | |01 = PWM output Low. 2108 * | | |10 = PWM output High. 2109 * | | |11 = PWM output Toggle. 2110 * |[9:8] |OUTACTS4 |Output Action Selection 2111 * | | |00 = Do nothing. 2112 * | | |01 = PWM output Low. 2113 * | | |10 = PWM output High. 2114 * | | |11 = PWM output Toggle. 2115 * |[11:10] |OUTACTS5 |Output Action Selection 2116 * | | |00 = Do nothing. 2117 * | | |01 = PWM output Low. 2118 * | | |10 = PWM output High. 2119 * | | |11 = PWM output Toggle. 2120 * @var PWM_T::SWEOFTRG 2121 * Offset: 0x28C PWM Software Event Output Force Trigger Register 2122 * --------------------------------------------------------------------------------------------------- 2123 * |Bits |Field |Descriptions 2124 * | :----: | :----: | :---- | 2125 * |[0] |SWETRG0 |Software Event Trigger 2126 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2127 * | | |Note: This bit will auto cleared by hardware. 2128 * |[1] |SWETRG1 |Software Event Trigger 2129 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2130 * | | |Note: This bit will auto cleared by hardware. 2131 * |[2] |SWETRG2 |Software Event Trigger 2132 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2133 * | | |Note: This bit will auto cleared by hardware. 2134 * |[3] |SWETRG3 |Software Event Trigger 2135 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2136 * | | |Note: This bit will auto cleared by hardware. 2137 * |[4] |SWETRG4 |Software Event Trigger 2138 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2139 * | | |Note: This bit will auto cleared by hardware. 2140 * |[5] |SWETRG5 |Software Event Trigger 2141 * | | |Write 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting. 2142 * | | |Note: This bit will auto cleared by hardware. 2143 * @var PWM_T::PBUF0 2144 * Offset: 0x304 PWM PERIOD0 Buffer 2145 * --------------------------------------------------------------------------------------------------- 2146 * |Bits |Field |Descriptions 2147 * | :----: | :----: | :---- | 2148 * |[15:0] |PBUF |PWM Period Register Buffer (Read Only) 2149 * | | |Used as PERIOD active register. 2150 * @var PWM_T::PBUF2 2151 * Offset: 0x30C PWM PERIOD2 Buffer 2152 * --------------------------------------------------------------------------------------------------- 2153 * |Bits |Field |Descriptions 2154 * | :----: | :----: | :---- | 2155 * |[15:0] |PBUF |PWM Period Register Buffer (Read Only) 2156 * | | |Used as PERIOD active register. 2157 * @var PWM_T::PBUF4 2158 * Offset: 0x314 PWM PERIOD4 Buffer 2159 * --------------------------------------------------------------------------------------------------- 2160 * |Bits |Field |Descriptions 2161 * | :----: | :----: | :---- | 2162 * |[15:0] |PBUF |PWM Period Register Buffer (Read Only) 2163 * | | |Used as PERIOD active register. 2164 * @var PWM_T::CMPBUF[6] 2165 * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer 2166 * --------------------------------------------------------------------------------------------------- 2167 * |Bits |Field |Descriptions 2168 * | :----: | :----: | :---- | 2169 * |[15:0] |CMPBUF |PWM Comparator Register Buffer (Read Only) 2170 * | | |Used as CMP active register. 2171 * @var PWM_T::IFACNT[6] 2172 * Offset: 0x368 PWM Interrupt Flag Accumulator Counter 0/2/4 2173 * --------------------------------------------------------------------------------------------------- 2174 * |Bits |Field |Descriptions 2175 * | :----: | :----: | :---- | 2176 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 2177 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 2178 */ 2179 __IO uint32_t CTL0; /*!< [0x0000] PWM Control Register 0 */ 2180 __IO uint32_t CTL1; /*!< [0x0004] PWM Control Register 1 */ 2181 __I uint32_t RESERVE0[2]; 2182 __IO uint32_t CLKSRC; /*!< [0x0010] PWM Clock Source Register */ 2183 __IO uint32_t CLKPSC0_1; /*!< [0x0014] PWM Clock Prescale Register 0/1 */ 2184 __IO uint32_t CLKPSC2_3; /*!< [0x0018] PWM Clock Prescale Register 2/3 */ 2185 __IO uint32_t CLKPSC4_5; /*!< [0x001c] PWM Clock Prescale Register 4/5 */ 2186 __IO uint32_t CNTEN; /*!< [0x0020] PWM Counter Enable Register */ 2187 __IO uint32_t CNTCLR; /*!< [0x0024] PWM Clear Counter Register */ 2188 __I uint32_t RESERVE1[2]; 2189 __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] PWM Period Register 0/2/4 */ 2190 __I uint32_t RESERVE2[2]; 2191 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] PWM Comparator Register 0~5 */ 2192 __I uint32_t RESERVE3[2]; 2193 __IO uint32_t DTCTL0_1; /*!< [0x0070] PWM Dead-time Control Register 0/1 */ 2194 __IO uint32_t DTCTL2_3; /*!< [0x0074] PWM Dead-time Control Register 2/3 */ 2195 __IO uint32_t DTCTL4_5; /*!< [0x0078] PWM Dead-time Control Register 4/5 */ 2196 __I uint32_t RESERVE4[5]; 2197 __I uint32_t CNT[6]; /*!< [0x0090~0x00a4] PWM Counter Register 0/2/4 */ 2198 __I uint32_t RESERVE5[2]; 2199 __IO uint32_t WGCTL0; /*!< [0x00b0] PWM Generation Register 0 */ 2200 __IO uint32_t WGCTL1; /*!< [0x00b4] PWM Generation Register 1 */ 2201 __IO uint32_t MSKEN; /*!< [0x00b8] PWM Mask Enable Register */ 2202 __IO uint32_t MSK; /*!< [0x00bc] PWM Mask Data Register */ 2203 __IO uint32_t BNF; /*!< [0x00c0] PWM Brake Noise Filter Register */ 2204 __IO uint32_t FAILBRK; /*!< [0x00c4] PWM System Fail Brake Control Register */ 2205 __IO uint32_t BRKCTL0_1; /*!< [0x00c8] PWM Brake Edge Detect Control Register 0/1 */ 2206 __IO uint32_t BRKCTL2_3; /*!< [0x00cc] PWM Brake Edge Detect Control Register 2/3 */ 2207 __IO uint32_t BRKCTL4_5; /*!< [0x00d0] PWM Brake Edge Detect Control Register 4/5 */ 2208 __IO uint32_t POLCTL; /*!< [0x00d4] PWM Pin Polar Inverse Register */ 2209 __IO uint32_t POEN; /*!< [0x00d8] PWM Output Enable Register */ 2210 __O uint32_t SWBRK; /*!< [0x00dc] PWM Software Brake Control Register */ 2211 __IO uint32_t INTEN0; /*!< [0x00e0] PWM Interrupt Enable Register 0 */ 2212 __IO uint32_t INTEN1; /*!< [0x00e4] PWM Interrupt Enable Register 1 */ 2213 __IO uint32_t INTSTS0; /*!< [0x00e8] PWM Interrupt Flag Register 0 */ 2214 __IO uint32_t INTSTS1; /*!< [0x00ec] PWM Interrupt Flag Register 1 */ 2215 __I uint32_t RESERVE10[1]; 2216 __IO uint32_t DACTRGEN; /*!< [0x00f4] PWM Trigger DAC Enable Register */ 2217 __IO uint32_t EADCTS0; /*!< [0x00f8] PWM Trigger EADC Source Select Register 0 */ 2218 __IO uint32_t EADCTS1; /*!< [0x00fc] PWM Trigger EADC Source Select Register 1 */ 2219 __I uint32_t RESERVE11[4]; 2220 __IO uint32_t SSCTL; /*!< [0x0110] PWM Synchronous Start Control Register */ 2221 __O uint32_t SSTRG; /*!< [0x0114] PWM Synchronous Start Trigger Register */ 2222 __I uint32_t RESERVE12[2]; 2223 __IO uint32_t STATUS; /*!< [0x0120] PWM Status Register */ 2224 __I uint32_t RESERVE13[3]; 2225 __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ 2226 __I uint32_t RESERVE16[2]; 2227 __IO uint32_t AINTSTS; /*!< [0x0150] PWM Accumulator Interrupt Flag Register */ 2228 __IO uint32_t AINTEN; /*!< [0x0154] PWM Accumulator Interrupt Enable Register */ 2229 __IO uint32_t APDMACTL; /*!< [0x0158] PWM Accumulator PDMA Control Register */ 2230 __I uint32_t RESERVE17[41]; 2231 __IO uint32_t CAPINEN; /*!< [0x0200] PWM Capture Input Enable Register */ 2232 __IO uint32_t CAPCTL; /*!< [0x0204] PWM Capture Control Register */ 2233 __I uint32_t CAPSTS; /*!< [0x0208] PWM Capture Status Register */ 2234 __I uint32_t RCAPDAT0; /*!< [0x020c] PWM Rising Capture Data Register 0 */ 2235 __I uint32_t FCAPDAT0; /*!< [0x0210] PWM Falling Capture Data Register 0 */ 2236 __I uint32_t RCAPDAT1; /*!< [0x0214] PWM Rising Capture Data Register 1 */ 2237 __I uint32_t FCAPDAT1; /*!< [0x0218] PWM Falling Capture Data Register 1 */ 2238 __I uint32_t RCAPDAT2; /*!< [0x021c] PWM Rising Capture Data Register 2 */ 2239 __I uint32_t FCAPDAT2; /*!< [0x0220] PWM Falling Capture Data Register 2 */ 2240 __I uint32_t RCAPDAT3; /*!< [0x0224] PWM Rising Capture Data Register 3 */ 2241 __I uint32_t FCAPDAT3; /*!< [0x0228] PWM Falling Capture Data Register 3 */ 2242 __I uint32_t RCAPDAT4; /*!< [0x022c] PWM Rising Capture Data Register 4 */ 2243 __I uint32_t FCAPDAT4; /*!< [0x0230] PWM Falling Capture Data Register 4 */ 2244 __I uint32_t RCAPDAT5; /*!< [0x0234] PWM Rising Capture Data Register 5 */ 2245 __I uint32_t FCAPDAT5; /*!< [0x0238] PWM Falling Capture Data Register 5 */ 2246 __IO uint32_t PDMACTL; /*!< [0x023c] PWM PDMA Control Register */ 2247 __I uint32_t PDMACAP0_1; /*!< [0x0240] PWM Capture Channel 01 PDMA Register */ 2248 __I uint32_t PDMACAP2_3; /*!< [0x0244] PWM Capture Channel 23 PDMA Register */ 2249 __I uint32_t PDMACAP4_5; /*!< [0x0248] PWM Capture Channel 45 PDMA Register */ 2250 __I uint32_t RESERVE18[1]; 2251 __IO uint32_t CAPIEN; /*!< [0x0250] PWM Capture Interrupt Enable Register */ 2252 __IO uint32_t CAPIF; /*!< [0x0254] PWM Capture Interrupt Flag Register */ 2253 __IO uint32_t CAPNF[6]; /*!< [0x0258] PWM Capture Input Noise Filter Register */ 2254 __IO uint32_t EXTETCTL0; /*!< [0x0270] PWM External Event Trigger Control Register 0 */ 2255 __I uint32_t RESERVE19[1]; 2256 __IO uint32_t EXTETCTL2; /*!< [0x0278] PWM External Event Trigger Control Register 2 */ 2257 __I uint32_t RESERVE20[1]; 2258 __IO uint32_t EXTETCTL4; /*!< [0x0280] PWM External Event Trigger Control Register 4 */ 2259 __I uint32_t RESERVE21[1]; 2260 __IO uint32_t SWEOFCTL; /*!< [0x0288] PWM Software Event Output Force Control Register */ 2261 __IO uint32_t SWEOFTRG; /*!< [0x028c] PWM Software Event Output Force Trigger Register */ 2262 __I uint32_t RESERVE22[29]; 2263 __I uint32_t PBUF0; /*!< [0x0304] PWM PERIOD0 Buffer */ 2264 __I uint32_t RESERVE23[1]; 2265 __I uint32_t PBUF2; /*!< [0x030c] PWM PERIOD2 Buffer */ 2266 __I uint32_t RESERVE24[1]; 2267 __I uint32_t PBUF4; /*!< [0x0314] PWM PERIOD4 Buffer */ 2268 __I uint32_t RESERVE25[1]; 2269 __I uint32_t CMPBUF[6]; /*!< [0x031c] PWM CMPDAT0~5 Buffer */ 2270 __I uint32_t RESERVE26[13]; 2271 __I uint32_t IFACNT[6]; /*!< [0x0368] PWM Interrupt Flag Accumulator Counter0~5 */ 2272 2273 } PWM_T; 2274 2275 /** 2276 @addtogroup PWM_CONST PWM Bit Field Definition 2277 Constant Definitions for PWM Controller 2278 @{ */ 2279 2280 #define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */ 2281 #define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */ 2282 2283 #define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */ 2284 #define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */ 2285 2286 #define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */ 2287 #define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */ 2288 2289 #define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */ 2290 #define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */ 2291 2292 #define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */ 2293 #define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */ 2294 2295 #define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */ 2296 #define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */ 2297 2298 #define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */ 2299 #define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */ 2300 2301 #define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */ 2302 #define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */ 2303 2304 #define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */ 2305 #define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */ 2306 2307 #define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */ 2308 #define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */ 2309 2310 #define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */ 2311 #define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */ 2312 2313 #define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */ 2314 #define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */ 2315 2316 #define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */ 2317 #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */ 2318 2319 #define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */ 2320 #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */ 2321 2322 #define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */ 2323 #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */ 2324 2325 #define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */ 2326 #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */ 2327 2328 #define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */ 2329 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */ 2330 #define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */ 2331 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */ 2332 2333 #define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */ 2334 #define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */ 2335 2336 #define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */ 2337 #define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */ 2338 2339 #define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */ 2340 #define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */ 2341 2342 #define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */ 2343 #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */ 2344 2345 #define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */ 2346 #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */ 2347 2348 #define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */ 2349 #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */ 2350 2351 #define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */ 2352 #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */ 2353 2354 #define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */ 2355 #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */ 2356 2357 #define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */ 2358 #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */ 2359 2360 #define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */ 2361 #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */ 2362 2363 #define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */ 2364 #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */ 2365 2366 #define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */ 2367 #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */ 2368 2369 #define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */ 2370 #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */ 2371 2372 #define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */ 2373 #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */ 2374 2375 #define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */ 2376 #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */ 2377 2378 #define PWM_PERIOD0_PERIOD_Pos (0) /*!< PWM_T::PERIOD0: PERIOD Position */ 2379 #define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) /*!< PWM_T::PERIOD0: PERIOD Mask */ 2380 2381 #define PWM_PERIOD2_PERIOD_Pos (0) /*!< PWM_T::PERIOD2: PERIOD Position */ 2382 #define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) /*!< PWM_T::PERIOD2: PERIOD Mask */ 2383 2384 #define PWM_PERIOD4_PERIOD_Pos (0) /*!< PWM_T::PERIOD4: PERIOD Position */ 2385 #define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) /*!< PWM_T::PERIOD4: PERIOD Mask */ 2386 2387 #define PWM_CMPDAT0_CMP_Pos (0) /*!< PWM_T::CMPDAT0: CMP Position */ 2388 #define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) /*!< PWM_T::CMPDAT0: CMP Mask */ 2389 2390 #define PWM_CMPDAT1_CMP_Pos (0) /*!< PWM_T::CMPDAT1: CMP Position */ 2391 #define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) /*!< PWM_T::CMPDAT1: CMP Mask */ 2392 2393 #define PWM_CMPDAT2_CMP_Pos (0) /*!< PWM_T::CMPDAT2: CMP Position */ 2394 #define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) /*!< PWM_T::CMPDAT2: CMP Mask */ 2395 2396 #define PWM_CMPDAT3_CMP_Pos (0) /*!< PWM_T::CMPDAT3: CMP Position */ 2397 #define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) /*!< PWM_T::CMPDAT3: CMP Mask */ 2398 2399 #define PWM_CMPDAT4_CMP_Pos (0) /*!< PWM_T::CMPDAT4: CMP Position */ 2400 #define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) /*!< PWM_T::CMPDAT4: CMP Mask */ 2401 2402 #define PWM_CMPDAT5_CMP_Pos (0) /*!< PWM_T::CMPDAT5: CMP Position */ 2403 #define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) /*!< PWM_T::CMPDAT5: CMP Mask */ 2404 2405 #define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */ 2406 #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */ 2407 2408 #define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */ 2409 #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */ 2410 2411 #define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */ 2412 #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */ 2413 2414 #define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */ 2415 #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */ 2416 2417 #define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */ 2418 #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */ 2419 2420 #define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */ 2421 #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */ 2422 2423 #define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */ 2424 #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */ 2425 2426 #define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */ 2427 #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */ 2428 2429 #define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */ 2430 #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */ 2431 2432 #define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */ 2433 #define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */ 2434 2435 #define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */ 2436 #define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */ 2437 2438 #define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */ 2439 #define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */ 2440 2441 #define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */ 2442 #define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */ 2443 2444 #define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */ 2445 #define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */ 2446 2447 #define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */ 2448 #define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */ 2449 2450 #define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */ 2451 #define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */ 2452 2453 #define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */ 2454 #define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */ 2455 2456 #define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */ 2457 #define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */ 2458 2459 #define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */ 2460 #define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */ 2461 2462 #define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */ 2463 #define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */ 2464 2465 #define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */ 2466 #define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */ 2467 2468 #define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */ 2469 #define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */ 2470 2471 #define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */ 2472 #define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */ 2473 2474 #define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */ 2475 #define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */ 2476 2477 #define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */ 2478 #define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */ 2479 2480 #define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */ 2481 #define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */ 2482 2483 #define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */ 2484 #define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */ 2485 2486 #define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */ 2487 #define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */ 2488 2489 #define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */ 2490 #define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */ 2491 2492 #define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */ 2493 #define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */ 2494 2495 #define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */ 2496 #define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */ 2497 2498 #define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */ 2499 #define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */ 2500 2501 #define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */ 2502 #define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */ 2503 2504 #define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */ 2505 #define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */ 2506 2507 #define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */ 2508 #define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */ 2509 2510 #define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */ 2511 #define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */ 2512 2513 #define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */ 2514 #define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */ 2515 2516 #define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */ 2517 #define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */ 2518 2519 #define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */ 2520 #define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */ 2521 2522 #define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */ 2523 #define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */ 2524 2525 #define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */ 2526 #define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */ 2527 2528 #define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */ 2529 #define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */ 2530 2531 #define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */ 2532 #define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */ 2533 2534 #define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */ 2535 #define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */ 2536 2537 #define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */ 2538 #define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */ 2539 2540 #define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */ 2541 #define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */ 2542 2543 #define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */ 2544 #define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */ 2545 2546 #define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */ 2547 #define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */ 2548 2549 #define PWM_BNF_BRK0FSEL_Pos (1) /*!< PWM_T::BNF: BRK0FSEL Position */ 2550 #define PWM_BNF_BRK0FSEL_Msk (0x7ul << PWM_BNF_BRK0FSEL_Pos) /*!< PWM_T::BNF: BRK0FSEL Mask */ 2551 2552 #define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */ 2553 #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */ 2554 2555 #define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */ 2556 #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */ 2557 2558 #define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */ 2559 #define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */ 2560 2561 #define PWM_BNF_BRK1FSEL_Pos (9) /*!< PWM_T::BNF: BRK1FSEL Position */ 2562 #define PWM_BNF_BRK1FSEL_Msk (0x7ul << PWM_BNF_BRK1FSEL_Pos) /*!< PWM_T::BNF: BRK1FSEL Mask */ 2563 2564 #define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */ 2565 #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */ 2566 2567 #define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */ 2568 #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */ 2569 2570 #define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */ 2571 #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */ 2572 2573 #define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */ 2574 #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */ 2575 2576 #define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */ 2577 #define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */ 2578 2579 #define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */ 2580 #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */ 2581 2582 #define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */ 2583 #define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */ 2584 2585 #define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */ 2586 #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */ 2587 2588 #define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */ 2589 #define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */ 2590 2591 #define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */ 2592 #define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */ 2593 2594 #define PWM_BRKCTL0_1_CPO2EBEN_Pos (2) /*!< PWM_T::BRKCTL0_1: CPO2EBEN Position */ 2595 #define PWM_BRKCTL0_1_CPO2EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO2EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO2EBEN Mask */ 2596 2597 #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */ 2598 #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */ 2599 2600 #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */ 2601 #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */ 2602 2603 #define PWM_BRKCTL0_1_VBSNEBEN_Pos (6) /*!< PWM_T::BRKCTL0_1: VBSNEBEN Position */ 2604 #define PWM_BRKCTL0_1_VBSNEBEN_Msk (0x1ul << PWM_BRKCTL0_1_VBSNEBEN_Pos) /*!< PWM_T::BRKCTL0_1: VBSNEBEN Mask */ 2605 2606 #define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */ 2607 #define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */ 2608 2609 #define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */ 2610 #define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */ 2611 2612 #define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */ 2613 #define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */ 2614 2615 #define PWM_BRKCTL0_1_CPO2LBEN_Pos (10) /*!< PWM_T::BRKCTL0_1: CPO2LBEN Position */ 2616 #define PWM_BRKCTL0_1_CPO2LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO2LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO2LBEN Mask */ 2617 2618 #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */ 2619 #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */ 2620 2621 #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */ 2622 #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */ 2623 2624 #define PWM_BRKCTL0_1_VBSNLBEN_Pos (14) /*!< PWM_T::BRKCTL0_1: VBSNLBEN Position */ 2625 #define PWM_BRKCTL0_1_VBSNLBEN_Msk (0x1ul << PWM_BRKCTL0_1_VBSNLBEN_Pos) /*!< PWM_T::BRKCTL0_1: VBSNLBEN Mask */ 2626 2627 #define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */ 2628 #define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */ 2629 2630 #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */ 2631 #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */ 2632 2633 #define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */ 2634 #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */ 2635 2636 #define PWM_BRKCTL0_1_EADC0EBEN_Pos (20) /*!< PWM_T::BRKCTL0_1: EADC0EBEN Position */ 2637 #define PWM_BRKCTL0_1_EADC0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_EADC0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: EADC0EBEN Mask */ 2638 2639 #define PWM_BRKCTL0_1_VBSREBEN_Pos (23) /*!< PWM_T::BRKCTL0_1: VBSREBEN Position */ 2640 #define PWM_BRKCTL0_1_VBSREBEN_Msk (0x1ul << PWM_BRKCTL0_1_VBSREBEN_Pos) /*!< PWM_T::BRKCTL0_1: VBSREBEN Mask */ 2641 2642 #define PWM_BRKCTL0_1_EADC0LBEN_Pos (28) /*!< PWM_T::BRKCTL0_1: EADC0LBEN Position */ 2643 #define PWM_BRKCTL0_1_EADC0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_EADC0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: EADC0LBEN Mask */ 2644 2645 #define PWM_BRKCTL0_1_VBSRLBEN_Pos (31) /*!< PWM_T::BRKCTL0_1: VBSRLBEN Position */ 2646 #define PWM_BRKCTL0_1_VBSRLBEN_Msk (0x1ul << PWM_BRKCTL0_1_VBSRLBEN_Pos) /*!< PWM_T::BRKCTL0_1: VBSRLBEN Mask */ 2647 2648 #define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */ 2649 #define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */ 2650 2651 #define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */ 2652 #define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */ 2653 2654 #define PWM_BRKCTL2_3_CPO2EBEN_Pos (2) /*!< PWM_T::BRKCTL2_3: CPO2EBEN Position */ 2655 #define PWM_BRKCTL2_3_CPO2EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO2EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO2EBEN Mask */ 2656 2657 #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */ 2658 #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */ 2659 2660 #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */ 2661 #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */ 2662 2663 #define PWM_BRKCTL2_3_VBSNEBEN_Pos (6) /*!< PWM_T::BRKCTL2_3: VBSNEBEN Position */ 2664 #define PWM_BRKCTL2_3_VBSNEBEN_Msk (0x1ul << PWM_BRKCTL2_3_VBSNEBEN_Pos) /*!< PWM_T::BRKCTL2_3: VBSNEBEN Mask */ 2665 2666 #define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */ 2667 #define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */ 2668 2669 #define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */ 2670 #define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */ 2671 2672 #define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */ 2673 #define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */ 2674 2675 #define PWM_BRKCTL2_3_CPO2LBEN_Pos (10) /*!< PWM_T::BRKCTL2_3: CPO2LBEN Position */ 2676 #define PWM_BRKCTL2_3_CPO2LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO2LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO2LBEN Mask */ 2677 2678 #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */ 2679 #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */ 2680 2681 #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */ 2682 #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */ 2683 2684 #define PWM_BRKCTL2_3_VBSNLBEN_Pos (14) /*!< PWM_T::BRKCTL2_3: VBSNLBEN Position */ 2685 #define PWM_BRKCTL2_3_VBSNLBEN_Msk (0x1ul << PWM_BRKCTL2_3_VBSNLBEN_Pos) /*!< PWM_T::BRKCTL2_3: VBSNLBEN Mask */ 2686 2687 #define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */ 2688 #define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */ 2689 2690 #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */ 2691 #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */ 2692 2693 #define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */ 2694 #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */ 2695 2696 #define PWM_BRKCTL2_3_EADC0EBEN_Pos (20) /*!< PWM_T::BRKCTL2_3: EADC0EBEN Position */ 2697 #define PWM_BRKCTL2_3_EADC0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_EADC0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: EADC0EBEN Mask */ 2698 2699 #define PWM_BRKCTL2_3_VBSREBEN_Pos (23) /*!< PWM_T::BRKCTL2_3: VBSREBEN Position */ 2700 #define PWM_BRKCTL2_3_VBSREBEN_Msk (0x1ul << PWM_BRKCTL2_3_VBSREBEN_Pos) /*!< PWM_T::BRKCTL2_3: VBSREBEN Mask */ 2701 2702 #define PWM_BRKCTL2_3_EADC0LBEN_Pos (28) /*!< PWM_T::BRKCTL2_3: EADC0LBEN Position */ 2703 #define PWM_BRKCTL2_3_EADC0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_EADC0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: EADC0LBEN Mask */ 2704 2705 #define PWM_BRKCTL2_3_VBSRLBEN_Pos (31) /*!< PWM_T::BRKCTL2_3: VBSRLBEN Position */ 2706 #define PWM_BRKCTL2_3_VBSRLBEN_Msk (0x1ul << PWM_BRKCTL2_3_VBSRLBEN_Pos) /*!< PWM_T::BRKCTL2_3: VBSRLBEN Mask */ 2707 2708 #define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */ 2709 #define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */ 2710 2711 #define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */ 2712 #define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */ 2713 2714 #define PWM_BRKCTL4_5_CPO2EBEN_Pos (2) /*!< PWM_T::BRKCTL4_5: CPO2EBEN Position */ 2715 #define PWM_BRKCTL4_5_CPO2EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO2EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO2EBEN Mask */ 2716 2717 #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */ 2718 #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */ 2719 2720 #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */ 2721 #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */ 2722 2723 #define PWM_BRKCTL4_5_VBSNEBEN_Pos (6) /*!< PWM_T::BRKCTL4_5: VBSNEBEN Position */ 2724 #define PWM_BRKCTL4_5_VBSNEBEN_Msk (0x1ul << PWM_BRKCTL4_5_VBSNEBEN_Pos) /*!< PWM_T::BRKCTL4_5: VBSNEBEN Mask */ 2725 2726 #define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */ 2727 #define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */ 2728 2729 #define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */ 2730 #define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */ 2731 2732 #define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */ 2733 #define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */ 2734 2735 #define PWM_BRKCTL4_5_CPO2LBEN_Pos (10) /*!< PWM_T::BRKCTL4_5: CPO2LBEN Position */ 2736 #define PWM_BRKCTL4_5_CPO2LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO2LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO2LBEN Mask */ 2737 2738 #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */ 2739 #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */ 2740 2741 #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */ 2742 #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */ 2743 2744 #define PWM_BRKCTL4_5_VBSNLBEN_Pos (14) /*!< PWM_T::BRKCTL4_5: VBSNLBEN Position */ 2745 #define PWM_BRKCTL4_5_VBSNLBEN_Msk (0x1ul << PWM_BRKCTL4_5_VBSNLBEN_Pos) /*!< PWM_T::BRKCTL4_5: VBSNLBEN Mask */ 2746 2747 #define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */ 2748 #define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */ 2749 2750 #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */ 2751 #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */ 2752 2753 #define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */ 2754 #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */ 2755 2756 #define PWM_BRKCTL4_5_EADC0EBEN_Pos (20) /*!< PWM_T::BRKCTL4_5: EADC0EBEN Position */ 2757 #define PWM_BRKCTL4_5_EADC0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_EADC0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: EADC0EBEN Mask */ 2758 2759 #define PWM_BRKCTL4_5_VBSREBEN_Pos (23) /*!< PWM_T::BRKCTL4_5: VBSREBEN Position */ 2760 #define PWM_BRKCTL4_5_VBSREBEN_Msk (0x1ul << PWM_BRKCTL4_5_VBSREBEN_Pos) /*!< PWM_T::BRKCTL4_5: VBSREBEN Mask */ 2761 2762 #define PWM_BRKCTL4_5_EADC0LBEN_Pos (28) /*!< PWM_T::BRKCTL4_5: EADC0LBEN Position */ 2763 #define PWM_BRKCTL4_5_EADC0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_EADC0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: EADC0LBEN Mask */ 2764 2765 #define PWM_BRKCTL4_5_VBSRLBEN_Pos (31) /*!< PWM_T::BRKCTL4_5: VBSRLBEN Position */ 2766 #define PWM_BRKCTL4_5_VBSRLBEN_Msk (0x1ul << PWM_BRKCTL4_5_VBSRLBEN_Pos) /*!< PWM_T::BRKCTL4_5: VBSRLBEN Mask */ 2767 2768 #define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */ 2769 #define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */ 2770 2771 #define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */ 2772 #define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */ 2773 2774 #define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */ 2775 #define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */ 2776 2777 #define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */ 2778 #define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */ 2779 2780 #define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */ 2781 #define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */ 2782 2783 #define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */ 2784 #define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */ 2785 2786 #define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */ 2787 #define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */ 2788 2789 #define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */ 2790 #define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */ 2791 2792 #define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */ 2793 #define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */ 2794 2795 #define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */ 2796 #define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */ 2797 2798 #define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */ 2799 #define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */ 2800 2801 #define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */ 2802 #define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */ 2803 2804 #define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */ 2805 #define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */ 2806 2807 #define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */ 2808 #define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */ 2809 2810 #define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */ 2811 #define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */ 2812 2813 #define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */ 2814 #define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */ 2815 2816 #define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */ 2817 #define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */ 2818 2819 #define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */ 2820 #define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */ 2821 2822 #define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */ 2823 #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */ 2824 2825 #define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */ 2826 #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */ 2827 2828 #define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */ 2829 #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */ 2830 2831 #define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */ 2832 #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */ 2833 2834 #define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */ 2835 #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */ 2836 2837 #define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */ 2838 #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */ 2839 2840 #define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */ 2841 #define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */ 2842 2843 #define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */ 2844 #define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */ 2845 2846 #define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */ 2847 #define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */ 2848 2849 #define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */ 2850 #define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */ 2851 2852 #define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */ 2853 #define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */ 2854 2855 #define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */ 2856 #define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */ 2857 2858 #define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */ 2859 #define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */ 2860 2861 #define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */ 2862 #define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */ 2863 2864 #define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */ 2865 #define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */ 2866 2867 #define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */ 2868 #define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */ 2869 2870 #define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */ 2871 #define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */ 2872 2873 #define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */ 2874 #define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */ 2875 2876 #define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */ 2877 #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */ 2878 2879 #define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */ 2880 #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */ 2881 2882 #define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */ 2883 #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */ 2884 2885 #define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */ 2886 #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */ 2887 2888 #define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */ 2889 #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */ 2890 2891 #define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */ 2892 #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */ 2893 2894 #define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */ 2895 #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */ 2896 2897 #define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */ 2898 #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */ 2899 2900 #define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */ 2901 #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */ 2902 2903 #define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */ 2904 #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */ 2905 2906 #define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */ 2907 #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */ 2908 2909 #define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */ 2910 #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */ 2911 2912 #define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */ 2913 #define PWM_INTSTS0_CMPUIF0_Msk (0x3ful << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */ 2914 2915 #define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */ 2916 #define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */ 2917 2918 #define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */ 2919 #define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */ 2920 2921 #define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */ 2922 #define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */ 2923 2924 #define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */ 2925 #define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */ 2926 2927 #define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */ 2928 #define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */ 2929 2930 #define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */ 2931 #define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */ 2932 2933 #define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */ 2934 #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */ 2935 2936 #define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */ 2937 #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */ 2938 2939 #define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */ 2940 #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */ 2941 2942 #define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */ 2943 #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */ 2944 2945 #define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */ 2946 #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */ 2947 2948 #define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */ 2949 #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */ 2950 2951 #define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */ 2952 #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */ 2953 2954 #define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */ 2955 #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */ 2956 2957 #define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */ 2958 #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */ 2959 2960 #define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */ 2961 #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */ 2962 2963 #define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */ 2964 #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */ 2965 2966 #define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */ 2967 #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */ 2968 2969 #define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */ 2970 #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */ 2971 2972 #define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */ 2973 #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */ 2974 2975 #define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */ 2976 #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */ 2977 2978 #define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */ 2979 #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */ 2980 2981 #define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */ 2982 #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */ 2983 2984 #define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */ 2985 #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */ 2986 2987 #define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */ 2988 #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */ 2989 2990 #define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */ 2991 #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */ 2992 2993 #define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */ 2994 #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */ 2995 2996 #define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */ 2997 #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */ 2998 2999 #define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */ 3000 #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */ 3001 3002 #define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */ 3003 #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */ 3004 3005 #define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */ 3006 #define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */ 3007 3008 #define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */ 3009 #define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */ 3010 3011 #define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */ 3012 #define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */ 3013 3014 #define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */ 3015 #define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */ 3016 3017 #define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */ 3018 #define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */ 3019 3020 #define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */ 3021 #define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */ 3022 3023 #define PWM_DACTRGEN_CUTRGEN0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEN0 Position */ 3024 #define PWM_DACTRGEN_CUTRGEN0_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN0_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN0 Mask */ 3025 3026 #define PWM_DACTRGEN_CUTRGEN1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGEN1 Position */ 3027 #define PWM_DACTRGEN_CUTRGEN1_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN1_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN1 Mask */ 3028 3029 #define PWM_DACTRGEN_CUTRGEN2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGEN2 Position */ 3030 #define PWM_DACTRGEN_CUTRGEN2_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN2_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN2 Mask */ 3031 3032 #define PWM_DACTRGEN_CUTRGEN3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGEN3 Position */ 3033 #define PWM_DACTRGEN_CUTRGEN3_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN3_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN3 Mask */ 3034 3035 #define PWM_DACTRGEN_CUTRGEN4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGEN4 Position */ 3036 #define PWM_DACTRGEN_CUTRGEN4_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN4_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN4 Mask */ 3037 3038 #define PWM_DACTRGEN_CUTRGEN5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGEN5 Position */ 3039 #define PWM_DACTRGEN_CUTRGEN5_Msk (0x1ul << PWM_DACTRGEN_CUTRGEN5_Pos) /*!< PWM_T::DACTRGEN: CUTRGEN5 Mask */ 3040 3041 #define PWM_DACTRGEN_CDTRGEN0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEN0 Position */ 3042 #define PWM_DACTRGEN_CDTRGEN0_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN0_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN0 Mask */ 3043 3044 #define PWM_DACTRGEN_CDTRGEN1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGEN1 Position */ 3045 #define PWM_DACTRGEN_CDTRGEN1_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN1_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN1 Mask */ 3046 3047 #define PWM_DACTRGEN_CDTRGEN2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGEN2 Position */ 3048 #define PWM_DACTRGEN_CDTRGEN2_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN2_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN2 Mask */ 3049 3050 #define PWM_DACTRGEN_CDTRGEN3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGEN3 Position */ 3051 #define PWM_DACTRGEN_CDTRGEN3_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN3_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN3 Mask */ 3052 3053 #define PWM_DACTRGEN_CDTRGEN4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGEN4 Position */ 3054 #define PWM_DACTRGEN_CDTRGEN4_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN4_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN4 Mask */ 3055 3056 #define PWM_DACTRGEN_CDTRGEN5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGEN5 Position */ 3057 #define PWM_DACTRGEN_CDTRGEN5_Msk (0x1ul << PWM_DACTRGEN_CDTRGEN5_Pos) /*!< PWM_T::DACTRGEN: CDTRGEN5 Mask */ 3058 3059 #define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */ 3060 #define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */ 3061 3062 #define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */ 3063 #define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */ 3064 3065 #define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */ 3066 #define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */ 3067 3068 #define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */ 3069 #define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */ 3070 3071 #define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */ 3072 #define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */ 3073 3074 #define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */ 3075 #define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */ 3076 3077 #define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */ 3078 #define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */ 3079 3080 #define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */ 3081 #define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */ 3082 3083 #define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */ 3084 #define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */ 3085 3086 #define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */ 3087 #define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */ 3088 3089 #define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */ 3090 #define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */ 3091 3092 #define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */ 3093 #define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */ 3094 3095 #define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */ 3096 #define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */ 3097 3098 #define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */ 3099 #define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */ 3100 3101 #define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */ 3102 #define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */ 3103 3104 #define PWM_SSCTL_SSRC_Pos (8) /*!< PWM_T::SSCTL: SSRC Position */ 3105 #define PWM_SSCTL_SSRC_Msk (0x3ul << PWM_SSCTL_SSRC_Pos) /*!< PWM_T::SSCTL: SSRC Mask */ 3106 3107 #define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */ 3108 #define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */ 3109 3110 #define PWM_STATUS_CNTMAX0_Pos (0) /*!< PWM_T::STATUS: CNTMAX0 Position */ 3111 #define PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos) /*!< PWM_T::STATUS: CNTMAX0 Mask */ 3112 3113 #define PWM_STATUS_CNTMAX2_Pos (2) /*!< PWM_T::STATUS: CNTMAX2 Position */ 3114 #define PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos) /*!< PWM_T::STATUS: CNTMAX2 Mask */ 3115 3116 #define PWM_STATUS_CNTMAX4_Pos (4) /*!< PWM_T::STATUS: CNTMAX4 Position */ 3117 #define PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos) /*!< PWM_T::STATUS: CNTMAX4 Mask */ 3118 3119 #define PWM_STATUS_EADCTRG0_Pos (16) /*!< PWM_T::STATUS: EADCTRG0 Position */ 3120 #define PWM_STATUS_EADCTRG0_Msk (0x1ul << PWM_STATUS_EADCTRG0_Pos) /*!< PWM_T::STATUS: EADCTRG0 Mask */ 3121 3122 #define PWM_STATUS_EADCTRG1_Pos (17) /*!< PWM_T::STATUS: EADCTRG1 Position */ 3123 #define PWM_STATUS_EADCTRG1_Msk (0x1ul << PWM_STATUS_EADCTRG1_Pos) /*!< PWM_T::STATUS: EADCTRG1 Mask */ 3124 3125 #define PWM_STATUS_EADCTRG2_Pos (18) /*!< PWM_T::STATUS: EADCTRG2 Position */ 3126 #define PWM_STATUS_EADCTRG2_Msk (0x1ul << PWM_STATUS_EADCTRG2_Pos) /*!< PWM_T::STATUS: EADCTRG2 Mask */ 3127 3128 #define PWM_STATUS_EADCTRG3_Pos (19) /*!< PWM_T::STATUS: EADCTRG3 Position */ 3129 #define PWM_STATUS_EADCTRG3_Msk (0x1ul << PWM_STATUS_EADCTRG3_Pos) /*!< PWM_T::STATUS: EADCTRG3 Mask */ 3130 3131 #define PWM_STATUS_EADCTRG4_Pos (20) /*!< PWM_T::STATUS: EADCTRG4 Position */ 3132 #define PWM_STATUS_EADCTRG4_Msk (0x1ul << PWM_STATUS_EADCTRG4_Pos) /*!< PWM_T::STATUS: EADCTRG4 Mask */ 3133 3134 #define PWM_STATUS_EADCTRG5_Pos (21) /*!< PWM_T::STATUS: EADCTRG5 Position */ 3135 #define PWM_STATUS_EADCTRG5_Msk (0x1ul << PWM_STATUS_EADCTRG5_Pos) /*!< PWM_T::STATUS: EADCTRG5 Mask */ 3136 3137 #define PWM_STATUS_LPADCTRG_Pos (23) /*!< PWM_T::STATUS: LPADCTRG Position */ 3138 #define PWM_STATUS_LPADCTRG_Msk (0x1ul << PWM_STATUS_LPADCTRG_Pos) /*!< PWM_T::STATUS: LPADCTRG Mask */ 3139 3140 #define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */ 3141 #define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */ 3142 3143 #define PWM_IFA0_IFACNT_Pos (0) /*!< PWM_T::IFA0: IFACNT Position */ 3144 #define PWM_IFA0_IFACNT_Msk (0xfful << PWM_IFA0_IFACNT_Pos) /*!< PWM_T::IFA0: IFACNT Mask */ 3145 3146 #define PWM_IFA0_STPMOD_Pos (24) /*!< PWM_T::IFA0: STPMOD Position */ 3147 #define PWM_IFA0_STPMOD_Msk (0x1ul << PWM_IFA0_STPMOD_Pos) /*!< PWM_T::IFA0: STPMOD Mask */ 3148 3149 #define PWM_IFA0_IFASEL_Pos (28) /*!< PWM_T::IFA0: IFASEL Position */ 3150 #define PWM_IFA0_IFASEL_Msk (0x3ul << PWM_IFA0_IFASEL_Pos) /*!< PWM_T::IFA0: IFASEL Mask */ 3151 3152 #define PWM_IFA0_IFAEN_Pos (31) /*!< PWM_T::IFA0: IFAEN Position */ 3153 #define PWM_IFA0_IFAEN_Msk (0x1ul << PWM_IFA0_IFAEN_Pos) /*!< PWM_T::IFA0: IFAEN Mask */ 3154 3155 #define PWM_IFA2_IFACNT_Pos (0) /*!< PWM_T::IFA2: IFACNT Position */ 3156 #define PWM_IFA2_IFACNT_Msk (0xfful << PWM_IFA2_IFACNT_Pos) /*!< PWM_T::IFA2: IFACNT Mask */ 3157 3158 #define PWM_IFA2_STPMOD_Pos (24) /*!< PWM_T::IFA2: STPMOD Position */ 3159 #define PWM_IFA2_STPMOD_Msk (0x1ul << PWM_IFA2_STPMOD_Pos) /*!< PWM_T::IFA2: STPMOD Mask */ 3160 3161 #define PWM_IFA2_IFASEL_Pos (28) /*!< PWM_T::IFA2: IFASEL Position */ 3162 #define PWM_IFA2_IFASEL_Msk (0x3ul << PWM_IFA2_IFASEL_Pos) /*!< PWM_T::IFA2: IFASEL Mask */ 3163 3164 #define PWM_IFA2_IFAEN_Pos (31) /*!< PWM_T::IFA2: IFAEN Position */ 3165 #define PWM_IFA2_IFAEN_Msk (0x1ul << PWM_IFA2_IFAEN_Pos) /*!< PWM_T::IFA2: IFAEN Mask */ 3166 3167 #define PWM_IFA4_IFACNT_Pos (0) /*!< PWM_T::IFA4: IFACNT Position */ 3168 #define PWM_IFA4_IFACNT_Msk (0xfful << PWM_IFA4_IFACNT_Pos) /*!< PWM_T::IFA4: IFACNT Mask */ 3169 3170 #define PWM_IFA4_STPMOD_Pos (24) /*!< PWM_T::IFA4: STPMOD Position */ 3171 #define PWM_IFA4_STPMOD_Msk (0x1ul << PWM_IFA4_STPMOD_Pos) /*!< PWM_T::IFA4: STPMOD Mask */ 3172 3173 #define PWM_IFA4_IFASEL_Pos (28) /*!< PWM_T::IFA4: IFASEL Position */ 3174 #define PWM_IFA4_IFASEL_Msk (0x3ul << PWM_IFA4_IFASEL_Pos) /*!< PWM_T::IFA4: IFASEL Mask */ 3175 3176 #define PWM_IFA4_IFAEN_Pos (31) /*!< PWM_T::IFA4: IFAEN Position */ 3177 #define PWM_IFA4_IFAEN_Msk (0x1ul << PWM_IFA4_IFAEN_Pos) /*!< PWM_T::IFA4: IFAEN Mask */ 3178 3179 #define PWM_AINTSTS_IFAIF0_Pos (0) /*!< PWM_T::AINTSTS: IFAIF0 Position */ 3180 #define PWM_AINTSTS_IFAIF0_Msk (0x1ul << PWM_AINTSTS_IFAIF0_Pos) /*!< PWM_T::AINTSTS: IFAIF0 Mask */ 3181 3182 #define PWM_AINTSTS_IFAIF2_Pos (2) /*!< PWM_T::AINTSTS: IFAIF2 Position */ 3183 #define PWM_AINTSTS_IFAIF2_Msk (0x1ul << PWM_AINTSTS_IFAIF2_Pos) /*!< PWM_T::AINTSTS: IFAIF2 Mask */ 3184 3185 #define PWM_AINTSTS_IFAIF4_Pos (4) /*!< PWM_T::AINTSTS: IFAIF4 Position */ 3186 #define PWM_AINTSTS_IFAIF4_Msk (0x1ul << PWM_AINTSTS_IFAIF4_Pos) /*!< PWM_T::AINTSTS: IFAIF4 Mask */ 3187 3188 #define PWM_AINTEN_IFAIEN0_Pos (0) /*!< PWM_T::AINTEN: IFAIEN0 Position */ 3189 #define PWM_AINTEN_IFAIEN0_Msk (0x1ul << PWM_AINTEN_IFAIEN0_Pos) /*!< PWM_T::AINTEN: IFAIEN0 Mask */ 3190 3191 #define PWM_AINTEN_IFAIEN2_Pos (2) /*!< PWM_T::AINTEN: IFAIEN2 Position */ 3192 #define PWM_AINTEN_IFAIEN2_Msk (0x1ul << PWM_AINTEN_IFAIEN2_Pos) /*!< PWM_T::AINTEN: IFAIEN2 Mask */ 3193 3194 #define PWM_AINTEN_IFAIEN4_Pos (4) /*!< PWM_T::AINTEN: IFAIEN4 Position */ 3195 #define PWM_AINTEN_IFAIEN4_Msk (0x1ul << PWM_AINTEN_IFAIEN4_Pos) /*!< PWM_T::AINTEN: IFAIEN4 Mask */ 3196 3197 #define PWM_APDMACTL_APDMAEN0_Pos (0) /*!< PWM_T::APDMACTL: APDMAEN0 Position */ 3198 #define PWM_APDMACTL_APDMAEN0_Msk (0x1ul << PWM_APDMACTL_APDMAEN0_Pos) /*!< PWM_T::APDMACTL: APDMAEN0 Mask */ 3199 3200 #define PWM_APDMACTL_APDMAEN1_Pos (1) /*!< PWM_T::APDMACTL: APDMAEN1 Position */ 3201 #define PWM_APDMACTL_APDMAEN1_Msk (0x1ul << PWM_APDMACTL_APDMAEN1_Pos) /*!< PWM_T::APDMACTL: APDMAEN1 Mask */ 3202 3203 #define PWM_APDMACTL_APDMAEN2_Pos (2) /*!< PWM_T::APDMACTL: APDMAEN2 Position */ 3204 #define PWM_APDMACTL_APDMAEN2_Msk (0x1ul << PWM_APDMACTL_APDMAEN2_Pos) /*!< PWM_T::APDMACTL: APDMAEN2 Mask */ 3205 3206 #define PWM_APDMACTL_APDMAEN3_Pos (3) /*!< PWM_T::APDMACTL: APDMAEN3 Position */ 3207 #define PWM_APDMACTL_APDMAEN3_Msk (0x1ul << PWM_APDMACTL_APDMAEN3_Pos) /*!< PWM_T::APDMACTL: APDMAEN3 Mask */ 3208 3209 #define PWM_APDMACTL_APDMAEN4_Pos (4) /*!< PWM_T::APDMACTL: APDMAEN4 Position */ 3210 #define PWM_APDMACTL_APDMAEN4_Msk (0x1ul << PWM_APDMACTL_APDMAEN4_Pos) /*!< PWM_T::APDMACTL: APDMAEN4 Mask */ 3211 3212 #define PWM_APDMACTL_APDMAEN5_Pos (5) /*!< PWM_T::APDMACTL: APDMAEN5 Position */ 3213 #define PWM_APDMACTL_APDMAEN5_Msk (0x1ul << PWM_APDMACTL_APDMAEN5_Pos) /*!< PWM_T::APDMACTL: APDMAEN5 Mask */ 3214 3215 #define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */ 3216 #define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */ 3217 3218 #define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */ 3219 #define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */ 3220 3221 #define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */ 3222 #define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */ 3223 3224 #define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */ 3225 #define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */ 3226 3227 #define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */ 3228 #define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */ 3229 3230 #define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */ 3231 #define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */ 3232 3233 #define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */ 3234 #define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */ 3235 3236 #define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */ 3237 #define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */ 3238 3239 #define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */ 3240 #define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */ 3241 3242 #define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */ 3243 #define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */ 3244 3245 #define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */ 3246 #define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */ 3247 3248 #define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */ 3249 #define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */ 3250 3251 #define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */ 3252 #define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */ 3253 3254 #define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */ 3255 #define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */ 3256 3257 #define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */ 3258 #define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */ 3259 3260 #define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */ 3261 #define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */ 3262 3263 #define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */ 3264 #define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */ 3265 3266 #define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */ 3267 #define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */ 3268 3269 #define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */ 3270 #define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */ 3271 3272 #define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */ 3273 #define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */ 3274 3275 #define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */ 3276 #define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */ 3277 3278 #define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */ 3279 #define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */ 3280 3281 #define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */ 3282 #define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */ 3283 3284 #define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */ 3285 #define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */ 3286 3287 #define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */ 3288 #define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */ 3289 3290 #define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */ 3291 #define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */ 3292 3293 #define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */ 3294 #define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */ 3295 3296 #define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */ 3297 #define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */ 3298 3299 #define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */ 3300 #define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */ 3301 3302 #define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */ 3303 #define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */ 3304 3305 #define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */ 3306 #define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */ 3307 3308 #define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */ 3309 #define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */ 3310 3311 #define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */ 3312 #define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */ 3313 3314 #define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */ 3315 #define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */ 3316 3317 #define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */ 3318 #define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */ 3319 3320 #define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */ 3321 #define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */ 3322 3323 #define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */ 3324 #define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */ 3325 3326 #define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */ 3327 #define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */ 3328 3329 #define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */ 3330 #define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */ 3331 3332 #define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */ 3333 #define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */ 3334 3335 #define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */ 3336 #define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */ 3337 3338 #define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */ 3339 #define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */ 3340 3341 #define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */ 3342 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */ 3343 3344 #define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */ 3345 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */ 3346 3347 #define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */ 3348 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */ 3349 3350 #define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */ 3351 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */ 3352 3353 #define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */ 3354 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */ 3355 3356 #define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */ 3357 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */ 3358 3359 #define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */ 3360 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */ 3361 3362 #define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */ 3363 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */ 3364 3365 #define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */ 3366 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */ 3367 3368 #define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */ 3369 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */ 3370 3371 #define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */ 3372 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */ 3373 3374 #define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */ 3375 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */ 3376 3377 #define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */ 3378 #define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */ 3379 3380 #define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */ 3381 #define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */ 3382 3383 #define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */ 3384 #define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */ 3385 3386 #define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */ 3387 #define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */ 3388 3389 #define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */ 3390 #define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */ 3391 3392 #define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */ 3393 #define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */ 3394 3395 #define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */ 3396 #define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */ 3397 3398 #define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */ 3399 #define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */ 3400 3401 #define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */ 3402 #define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */ 3403 3404 #define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */ 3405 #define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */ 3406 3407 #define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */ 3408 #define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */ 3409 3410 #define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */ 3411 #define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */ 3412 3413 #define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */ 3414 #define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */ 3415 3416 #define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */ 3417 #define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */ 3418 3419 #define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */ 3420 #define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */ 3421 3422 #define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */ 3423 #define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */ 3424 3425 #define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */ 3426 #define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */ 3427 3428 #define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */ 3429 #define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */ 3430 3431 #define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */ 3432 #define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */ 3433 3434 #define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */ 3435 #define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */ 3436 3437 #define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */ 3438 #define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */ 3439 3440 #define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */ 3441 #define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */ 3442 3443 #define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */ 3444 #define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */ 3445 3446 #define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */ 3447 #define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */ 3448 3449 #define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */ 3450 #define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */ 3451 3452 #define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */ 3453 #define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */ 3454 3455 #define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */ 3456 #define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */ 3457 3458 #define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */ 3459 #define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */ 3460 3461 #define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */ 3462 #define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */ 3463 3464 #define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */ 3465 #define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */ 3466 3467 #define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */ 3468 #define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */ 3469 3470 #define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */ 3471 #define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */ 3472 3473 #define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */ 3474 #define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */ 3475 3476 #define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */ 3477 #define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */ 3478 3479 #define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */ 3480 #define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */ 3481 3482 #define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */ 3483 #define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */ 3484 3485 #define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */ 3486 #define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */ 3487 3488 #define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */ 3489 #define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */ 3490 3491 #define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */ 3492 #define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */ 3493 3494 #define PWM_CAPNF0_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF0: CAPNFEN Position */ 3495 #define PWM_CAPNF0_CAPNFEN_Msk (0x1ul << PWM_CAPNF0_CAPNFEN_Pos) /*!< PWM_T::CAPNF0: CAPNFEN Mask */ 3496 3497 #define PWM_CAPNF0_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF0: CAPNFSEL Position */ 3498 #define PWM_CAPNF0_CAPNFSEL_Msk (0x7ul << PWM_CAPNF0_CAPNFSEL_Pos) /*!< PWM_T::CAPNF0: CAPNFSEL Mask */ 3499 3500 #define PWM_CAPNF0_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF0: CAPNFCNT Position */ 3501 #define PWM_CAPNF0_CAPNFCNT_Msk (0x7ul << PWM_CAPNF0_CAPNFCNT_Pos) /*!< PWM_T::CAPNF0: CAPNFCNT Mask */ 3502 3503 #define PWM_CAPNF1_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF1: CAPNFEN Position */ 3504 #define PWM_CAPNF1_CAPNFEN_Msk (0x1ul << PWM_CAPNF1_CAPNFEN_Pos) /*!< PWM_T::CAPNF1: CAPNFEN Mask */ 3505 3506 #define PWM_CAPNF1_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF1: CAPNFSEL Position */ 3507 #define PWM_CAPNF1_CAPNFSEL_Msk (0x7ul << PWM_CAPNF1_CAPNFSEL_Pos) /*!< PWM_T::CAPNF1: CAPNFSEL Mask */ 3508 3509 #define PWM_CAPNF1_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF1: CAPNFCNT Position */ 3510 #define PWM_CAPNF1_CAPNFCNT_Msk (0x7ul << PWM_CAPNF1_CAPNFCNT_Pos) /*!< PWM_T::CAPNF1: CAPNFCNT Mask */ 3511 3512 #define PWM_CAPNF2_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF2: CAPNFEN Position */ 3513 #define PWM_CAPNF2_CAPNFEN_Msk (0x1ul << PWM_CAPNF2_CAPNFEN_Pos) /*!< PWM_T::CAPNF2: CAPNFEN Mask */ 3514 3515 #define PWM_CAPNF2_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF2: CAPNFSEL Position */ 3516 #define PWM_CAPNF2_CAPNFSEL_Msk (0x7ul << PWM_CAPNF2_CAPNFSEL_Pos) /*!< PWM_T::CAPNF2: CAPNFSEL Mask */ 3517 3518 #define PWM_CAPNF2_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF2: CAPNFCNT Position */ 3519 #define PWM_CAPNF2_CAPNFCNT_Msk (0x7ul << PWM_CAPNF2_CAPNFCNT_Pos) /*!< PWM_T::CAPNF2: CAPNFCNT Mask */ 3520 3521 #define PWM_CAPNF3_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF3: CAPNFEN Position */ 3522 #define PWM_CAPNF3_CAPNFEN_Msk (0x1ul << PWM_CAPNF3_CAPNFEN_Pos) /*!< PWM_T::CAPNF3: CAPNFEN Mask */ 3523 3524 #define PWM_CAPNF3_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF3: CAPNFSEL Position */ 3525 #define PWM_CAPNF3_CAPNFSEL_Msk (0x7ul << PWM_CAPNF3_CAPNFSEL_Pos) /*!< PWM_T::CAPNF3: CAPNFSEL Mask */ 3526 3527 #define PWM_CAPNF3_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF3: CAPNFCNT Position */ 3528 #define PWM_CAPNF3_CAPNFCNT_Msk (0x7ul << PWM_CAPNF3_CAPNFCNT_Pos) /*!< PWM_T::CAPNF3: CAPNFCNT Mask */ 3529 3530 #define PWM_CAPNF4_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF4: CAPNFEN Position */ 3531 #define PWM_CAPNF4_CAPNFEN_Msk (0x1ul << PWM_CAPNF4_CAPNFEN_Pos) /*!< PWM_T::CAPNF4: CAPNFEN Mask */ 3532 3533 #define PWM_CAPNF4_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF4: CAPNFSEL Position */ 3534 #define PWM_CAPNF4_CAPNFSEL_Msk (0x7ul << PWM_CAPNF4_CAPNFSEL_Pos) /*!< PWM_T::CAPNF4: CAPNFSEL Mask */ 3535 3536 #define PWM_CAPNF4_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF4: CAPNFCNT Position */ 3537 #define PWM_CAPNF4_CAPNFCNT_Msk (0x7ul << PWM_CAPNF4_CAPNFCNT_Pos) /*!< PWM_T::CAPNF4: CAPNFCNT Mask */ 3538 3539 #define PWM_CAPNF5_CAPNFEN_Pos (0) /*!< PWM_T::CAPNF5: CAPNFEN Position */ 3540 #define PWM_CAPNF5_CAPNFEN_Msk (0x1ul << PWM_CAPNF5_CAPNFEN_Pos) /*!< PWM_T::CAPNF5: CAPNFEN Mask */ 3541 3542 #define PWM_CAPNF5_CAPNFSEL_Pos (4) /*!< PWM_T::CAPNF5: CAPNFSEL Position */ 3543 #define PWM_CAPNF5_CAPNFSEL_Msk (0x7ul << PWM_CAPNF5_CAPNFSEL_Pos) /*!< PWM_T::CAPNF5: CAPNFSEL Mask */ 3544 3545 #define PWM_CAPNF5_CAPNFCNT_Pos (8) /*!< PWM_T::CAPNF5: CAPNFCNT Position */ 3546 #define PWM_CAPNF5_CAPNFCNT_Msk (0x7ul << PWM_CAPNF5_CAPNFCNT_Pos) /*!< PWM_T::CAPNF5: CAPNFCNT Mask */ 3547 3548 #define PWM_EXTETCTL0_EXTETEN_Pos (0) /*!< PWM_T::EXTETCTL0: EXTETEN Position */ 3549 #define PWM_EXTETCTL0_EXTETEN_Msk (0x1ul << PWM_EXTETCTL0_EXTETEN_Pos) /*!< PWM_T::EXTETCTL0: EXTETEN Mask */ 3550 3551 #define PWM_EXTETCTL0_CNTACTS_Pos (4) /*!< PWM_T::EXTETCTL0: CNTACTS Position */ 3552 #define PWM_EXTETCTL0_CNTACTS_Msk (0x3ul << PWM_EXTETCTL0_CNTACTS_Pos) /*!< PWM_T::EXTETCTL0: CNTACTS Mask */ 3553 3554 #define PWM_EXTETCTL0_EXTTRGS_Pos (8) /*!< PWM_T::EXTETCTL0: EXTTRGS Position */ 3555 #define PWM_EXTETCTL0_EXTTRGS_Msk (0xful << PWM_EXTETCTL0_EXTTRGS_Pos) /*!< PWM_T::EXTETCTL0: EXTTRGS Mask */ 3556 3557 #define PWM_EXTETCTL2_EXTETEN_Pos (0) /*!< PWM_T::EXTETCTL2: EXTETEN Position */ 3558 #define PWM_EXTETCTL2_EXTETEN_Msk (0x1ul << PWM_EXTETCTL2_EXTETEN_Pos) /*!< PWM_T::EXTETCTL2: EXTETEN Mask */ 3559 3560 #define PWM_EXTETCTL2_CNTACTS_Pos (4) /*!< PWM_T::EXTETCTL2: CNTACTS Position */ 3561 #define PWM_EXTETCTL2_CNTACTS_Msk (0x3ul << PWM_EXTETCTL2_CNTACTS_Pos) /*!< PWM_T::EXTETCTL2: CNTACTS Mask */ 3562 3563 #define PWM_EXTETCTL2_EXTTRGS_Pos (8) /*!< PWM_T::EXTETCTL2: EXTTRGS Position */ 3564 #define PWM_EXTETCTL2_EXTTRGS_Msk (0xful << PWM_EXTETCTL2_EXTTRGS_Pos) /*!< PWM_T::EXTETCTL2: EXTTRGS Mask */ 3565 3566 #define PWM_EXTETCTL4_EXTETEN_Pos (0) /*!< PWM_T::EXTETCTL4: EXTETEN Position */ 3567 #define PWM_EXTETCTL4_EXTETEN_Msk (0x1ul << PWM_EXTETCTL4_EXTETEN_Pos) /*!< PWM_T::EXTETCTL4: EXTETEN Mask */ 3568 3569 #define PWM_EXTETCTL4_CNTACTS_Pos (4) /*!< PWM_T::EXTETCTL4: CNTACTS Position */ 3570 #define PWM_EXTETCTL4_CNTACTS_Msk (0x3ul << PWM_EXTETCTL4_CNTACTS_Pos) /*!< PWM_T::EXTETCTL4: CNTACTS Mask */ 3571 3572 #define PWM_EXTETCTL4_EXTTRGS_Pos (8) /*!< PWM_T::EXTETCTL4: EXTTRGS Position */ 3573 #define PWM_EXTETCTL4_EXTTRGS_Msk (0xful << PWM_EXTETCTL4_EXTTRGS_Pos) /*!< PWM_T::EXTETCTL4: EXTTRGS Mask */ 3574 3575 #define PWM_SWEOFCTL_OUTACTS0_Pos (0) /*!< PWM_T::SWEOFCTL: OUTACTS0 Position */ 3576 #define PWM_SWEOFCTL_OUTACTS0_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS0_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS0 Mask */ 3577 3578 #define PWM_SWEOFCTL_OUTACTS1_Pos (2) /*!< PWM_T::SWEOFCTL: OUTACTS1 Position */ 3579 #define PWM_SWEOFCTL_OUTACTS1_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS1_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS1 Mask */ 3580 3581 #define PWM_SWEOFCTL_OUTACTS2_Pos (4) /*!< PWM_T::SWEOFCTL: OUTACTS2 Position */ 3582 #define PWM_SWEOFCTL_OUTACTS2_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS2_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS2 Mask */ 3583 3584 #define PWM_SWEOFCTL_OUTACTS3_Pos (6) /*!< PWM_T::SWEOFCTL: OUTACTS3 Position */ 3585 #define PWM_SWEOFCTL_OUTACTS3_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS3_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS3 Mask */ 3586 3587 #define PWM_SWEOFCTL_OUTACTS4_Pos (8) /*!< PWM_T::SWEOFCTL: OUTACTS4 Position */ 3588 #define PWM_SWEOFCTL_OUTACTS4_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS4_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS4 Mask */ 3589 3590 #define PWM_SWEOFCTL_OUTACTS5_Pos (10) /*!< PWM_T::SWEOFCTL: OUTACTS5 Position */ 3591 #define PWM_SWEOFCTL_OUTACTS5_Msk (0x3ul << PWM_SWEOFCTL_OUTACTS5_Pos) /*!< PWM_T::SWEOFCTL: OUTACTS5 Mask */ 3592 3593 #define PWM_SWEOFTRG_SWETRG0_Pos (0) /*!< PWM_T::SWEOFTRG: SWETRG0 Position */ 3594 #define PWM_SWEOFTRG_SWETRG0_Msk (0x1ul << PWM_SWEOFTRG_SWETRG0_Pos) /*!< PWM_T::SWEOFTRG: SWETRG0 Mask */ 3595 3596 #define PWM_SWEOFTRG_SWETRG1_Pos (1) /*!< PWM_T::SWEOFTRG: SWETRG1 Position */ 3597 #define PWM_SWEOFTRG_SWETRG1_Msk (0x1ul << PWM_SWEOFTRG_SWETRG1_Pos) /*!< PWM_T::SWEOFTRG: SWETRG1 Mask */ 3598 3599 #define PWM_SWEOFTRG_SWETRG2_Pos (2) /*!< PWM_T::SWEOFTRG: SWETRG2 Position */ 3600 #define PWM_SWEOFTRG_SWETRG2_Msk (0x1ul << PWM_SWEOFTRG_SWETRG2_Pos) /*!< PWM_T::SWEOFTRG: SWETRG2 Mask */ 3601 3602 #define PWM_SWEOFTRG_SWETRG3_Pos (3) /*!< PWM_T::SWEOFTRG: SWETRG3 Position */ 3603 #define PWM_SWEOFTRG_SWETRG3_Msk (0x1ul << PWM_SWEOFTRG_SWETRG3_Pos) /*!< PWM_T::SWEOFTRG: SWETRG3 Mask */ 3604 3605 #define PWM_SWEOFTRG_SWETRG4_Pos (4) /*!< PWM_T::SWEOFTRG: SWETRG4 Position */ 3606 #define PWM_SWEOFTRG_SWETRG4_Msk (0x1ul << PWM_SWEOFTRG_SWETRG4_Pos) /*!< PWM_T::SWEOFTRG: SWETRG4 Mask */ 3607 3608 #define PWM_SWEOFTRG_SWETRG5_Pos (5) /*!< PWM_T::SWEOFTRG: SWETRG5 Position */ 3609 #define PWM_SWEOFTRG_SWETRG5_Msk (0x1ul << PWM_SWEOFTRG_SWETRG5_Pos) /*!< PWM_T::SWEOFTRG: SWETRG5 Mask */ 3610 3611 #define PWM_PBUF0_PBUF_Pos (0) /*!< PWM_T::PBUF0: PBUF Position */ 3612 #define PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos) /*!< PWM_T::PBUF0: PBUF Mask */ 3613 3614 #define PWM_PBUF2_PBUF_Pos (0) /*!< PWM_T::PBUF2: PBUF Position */ 3615 #define PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos) /*!< PWM_T::PBUF2: PBUF Mask */ 3616 3617 #define PWM_PBUF4_PBUF_Pos (0) /*!< PWM_T::PBUF4: PBUF Position */ 3618 #define PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos) /*!< PWM_T::PBUF4: PBUF Mask */ 3619 3620 #define PWM_CMPBUF0_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF0: CMPBUF Position */ 3621 #define PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos) /*!< PWM_T::CMPBUF0: CMPBUF Mask */ 3622 3623 #define PWM_CMPBUF1_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF1: CMPBUF Position */ 3624 #define PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos) /*!< PWM_T::CMPBUF1: CMPBUF Mask */ 3625 3626 #define PWM_CMPBUF2_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF2: CMPBUF Position */ 3627 #define PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos) /*!< PWM_T::CMPBUF2: CMPBUF Mask */ 3628 3629 #define PWM_CMPBUF3_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF3: CMPBUF Position */ 3630 #define PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos) /*!< PWM_T::CMPBUF3: CMPBUF Mask */ 3631 3632 #define PWM_CMPBUF4_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF4: CMPBUF Position */ 3633 #define PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos) /*!< PWM_T::CMPBUF4: CMPBUF Mask */ 3634 3635 #define PWM_CMPBUF5_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF5: CMPBUF Position */ 3636 #define PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) /*!< PWM_T::CMPBUF5: CMPBUF Mask */ 3637 3638 #define PWM_IFACNT0_ACUCNT_Pos (0) /*!< PWM_T::IFACNT0: ACUCNT Position */ 3639 #define PWM_IFACNT0_ACUCNT_Msk (0xfffful << PWM_IFACNT0_ACUCNT_Pos) /*!< PWM_T::IFACNT0: ACUCNT Mask */ 3640 3641 #define PWM_IFACNT2_ACUCNT_Pos (0) /*!< PWM_T::IFACNT2: ACUCNT Position */ 3642 #define PWM_IFACNT2_ACUCNT_Msk (0xfffful << PWM_IFACNT2_ACUCNT_Pos) /*!< PWM_T::IFACNT2: ACUCNT Mask */ 3643 3644 #define PWM_IFACNT4_ACUCNT_Pos (0) /*!< PWM_T::IFACNT4: ACUCNT Position */ 3645 #define PWM_IFACNT4_ACUCNT_Msk (0xfffful << PWM_IFACNT4_ACUCNT_Pos) /*!< PWM_T::IFACNT4: ACUCNT Mask */ 3646 3647 /**@}*/ /* PWM_CONST */ 3648 /**@}*/ /* end of PWM register group */ 3649 /**@}*/ /* end of REGISTER group */ 3650 3651 #if defined ( __CC_ARM ) 3652 #pragma no_anon_unions 3653 #endif 3654 3655 #endif /* __PWM_REG_H__ */ 3656
