1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2022 AMD.All rights reserved. 4 * 5 * Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com> 6 * Bala Kishore <balakishore.pati@amd.com> 7 */ 8 9 #ifndef _RMB_OFFSET_HEADER 10 #define _RMB_OFFSET_HEADER 11 12 #define PU_REGISTER_BASE (0x9FD00000 - 0x01240000) 13 #define PU_SCRATCH_REG_BASE (0x9FF00000 - 0x01250000) 14 15 /* Registers from ACP_DMA block */ 16 #define ACP_DMA_CNTL_0 0x1240000 17 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 18 #define ACP_DMA_DSCR_CNT_0 0x1240040 19 #define ACP_DMA_PRIO_0 0x1240060 20 #define ACP_DMA_CUR_DSCR_0 0x1240080 21 #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 22 #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 23 #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 24 #define ACP_DMA_CH_STS 0x12400E8 25 #define ACP_DMA_CH_GROUP 0x12400EC 26 #define ACP_DMA_CH_RST_STS 0x12400F0 27 28 /* Registers from ACP_MISC block */ 29 #define ACP_CLKMUX_SEL 0x124102C 30 #define ACP_DSP0_INTR_CNTL 0x1241800 31 #define ACP_DSP0_INTR_STAT 0x1241804 32 #define ACP_DSP_SW_INTR_CNTL 0x1241808 33 #define ACP_DSP_SW_INTR_STAT 0x124180C 34 #define ACP_SW_INTR_TRIG 0x1241810 35 #define DSP_INTERRUPT_ROUTING_CTRL_0 0x1241814 36 #define DSP_INTERRUPT_ROUTING_CTRL_1 0x1241818 37 #define ACP_FUTURE_REG_ACLK_0 0x1241854 38 #define ACP_AXI2DAGB_SEM_0 0x1241874 39 #define ACP_DSP0_INTR_CNTL1 0x1241920 40 #define ACP_DSP0_INTR_STAT1 0x1241924 41 #define ACP_SRBM_CLIENT_BASE_ADDR 0x12419EC 42 #define ACP_SRBM_CLIENT_RDDATA 0x12419F0 43 #define ACP_SRBM_CYCLE_STS 0x12419F4 44 #define ACP_SRBM_CLIENT_CONFIG 0x12419F8 45 46 /* Registers from ACP_P1_MISC block */ 47 #define ACP_EXTERNAL_INTR_ENB 0x1241A00 48 #define ACP_EXTERNAL_INTR_CNTL 0x1241A04 49 #define ACP_EXTERNAL_INTR_CNTL1 0x1241A08 50 #define ACP_EXTERNAL_INTR_STAT 0x1241A0C 51 #define ACP_EXTERNAL_INTR_STAT1 0x1241A10 52 53 /* Registers from ACP_I2S_TDM block */ 54 #define ACP_I2STDM_IER 0x1242400 55 #define ACP_I2STDM_IRER 0x1242404 56 #define ACP_I2STDM_RXFRMT 0x1242408 57 #define ACP_I2STDM_ITER 0x124240C 58 #define ACP_I2STDM_TXFRMT 0x1242410 59 #define ACP_I2STDM0_MSTRCLKGEN 0x1242414 60 #define ACP_I2STDM1_MSTRCLKGEN 0x1242418 61 #define ACP_I2STDM2_MSTRCLKGEN 0x124241C 62 #define ACP_I2STDM_REFCLKGEN 0x1242420 63 64 /* Registers from ACP_BT_TDM block */ 65 #define ACP_BTTDM_IER 0x1242800 66 #define ACP_BTTDM_IRER 0x1242804 67 #define ACP_BTTDM_RXFRMT 0x1242808 68 #define ACP_BTTDM_ITER 0x124280C 69 #define ACP_BTTDM_TXFRMT 0x1242810 70 #define ACP_HSTDM_IER 0x1242814 71 #define ACP_HSTDM_IRER 0x1242818 72 #define ACP_HSTDM_RXFRMT 0x124281C 73 #define ACP_HSTDM_ITER 0x1242820 74 #define ACP_HSTDM_TXFRMT 0x1242824 75 76 /* Registers from ACP_WOV block */ 77 #define ACP_WOV_PDM_ENABLE 0x1242C04 78 #define ACP_WOV_PDM_DMA_ENABLE 0x1242C08 79 #define ACP_WOV_RX_RINGBUFADDR 0x1242C0C 80 #define ACP_WOV_RX_RINGBUFSIZE 0x1242C10 81 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14 82 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18 83 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C 84 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20 85 #define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24 86 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28 87 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C 88 #define ACP_WOV_PDM_VAD_CTRL 0x1242C30 89 #define ACP_WOV_WAKE 0x1242C54 90 #define ACP_WOV_BUFFER_STATUS 0x1242C58 91 #define ACP_WOV_MISC_CTRL 0x1242C5C 92 #define ACP_WOV_CLK_CTRL 0x1242C60 93 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64 94 #define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68 95 #define ACP_PDM_CLKDIV 0x1242C6C 96 97 /* Registers from ACP_P1_AUDIO_BUFFERS block */ 98 #define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00 99 #define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04 100 #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x1243A08 101 #define ACP_P1_I2S_RX_FIFOADDR 0x1243A0C 102 #define ACP_P1_I2S_RX_FIFOSIZE 0x1243A10 103 #define ACP_P1_I2S_RX_DMA_SIZE 0x1243A14 104 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18 105 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C 106 #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x1243A20 107 #define ACP_P1_I2S_TX_RINGBUFADDR 0x1243A24 108 #define ACP_P1_I2S_TX_RINGBUFSIZE 0x1243A28 109 #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x1243A2C 110 #define ACP_P1_I2S_TX_FIFOADDR 0x1243A30 111 #define ACP_P1_I2S_TX_FIFOSIZE 0x1243A34 112 #define ACP_P1_I2S_TX_DMA_SIZE 0x1243A38 113 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C 114 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 115 #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44 116 #define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48 117 #define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C 118 #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x1243A50 119 #define ACP_P1_BT_RX_FIFOADDR 0x1243A54 120 #define ACP_P1_BT_RX_FIFOSIZE 0x1243A58 121 #define ACP_P1_BT_RX_DMA_SIZE 0x1243A5C 122 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1243A60 123 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x1243A64 124 #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x1243A68 125 #define ACP_P1_BT_TX_RINGBUFADDR 0x1243A6C 126 #define ACP_P1_BT_TX_RINGBUFSIZE 0x1243A70 127 #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x1243A74 128 #define ACP_P1_BT_TX_FIFOADDR 0x1243A78 129 #define ACP_P1_BT_TX_FIFOSIZE 0x1243A7C 130 #define ACP_P1_BT_TX_DMA_SIZE 0x1243A80 131 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1243A84 132 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x1243A88 133 #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x1243A8C 134 #define ACP_P1_HS_RX_RINGBUFADDR 0x1243A90 135 #define ACP_P1_HS_RX_RINGBUFSIZE 0x1243A94 136 #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x1243A98 137 #define ACP_P1_HS_RX_FIFOADDR 0x1243A9C 138 #define ACP_P1_HS_RX_FIFOSIZE 0x1243AA0 139 #define ACP_P1_HS_RX_DMA_SIZE 0x1243AA4 140 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x1243AA8 141 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x1243AAC 142 #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x1243AB0 143 #define ACP_P1_HS_TX_RINGBUFADDR 0x1243AB4 144 #define ACP_P1_HS_TX_RINGBUFSIZE 0x1243AB8 145 #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x1243ABC 146 #define ACP_P1_HS_TX_FIFOADDR 0x1243AC0 147 #define ACP_P1_HS_TX_FIFOSIZE 0x1243AC4 148 #define ACP_P1_HS_TX_DMA_SIZE 0x1243AC8 149 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x1243ACC 150 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0 151 #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4 152 153 #define MP1_SMN_C2PMSG_69 0x58A14 154 #define MP1_SMN_C2PMSG_85 0x58A54 155 #define MP1_SMN_C2PMSG_93 0x58A74 156 157 #define MP0_C2PMSG_73 0x3810A24 158 #define MP0_C2PMSG_114 0x3810AC8 159 #endif 160
