1 /*
2  * Copyright (c) 2019-2020 Cobham Gaisler AB
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
8 #define ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
9 
10 /*
11  * @file
12  * @brief Definitions for the SPARC V8 architecture.
13  */
14 
15 /* Processor State Register */
16 #define PSR_VER_BIT                     24
17 #define PSR_PIL_BIT                      8
18 
19 #define PSR_VER                         (0xf << PSR_VER_BIT)
20 #define PSR_EF                          (1 << 12)
21 #define PSR_S                           (1 <<  7)
22 #define PSR_PS                          (1 <<  6)
23 #define PSR_ET                          (1 <<  5)
24 #define PSR_PIL                         (0xf << PSR_PIL_BIT)
25 #define PSR_CWP                         0x1f
26 
27 
28 /* Trap Base Register */
29 #define TBR_TT_BIT                       4
30 
31 #define TBR_TBA                         0xfffff000
32 #define TBR_TT                          0x00000ff0
33 
34 /* Trap types in TBR.TT */
35 #define TT_RESET                        0x00
36 #define TT_WINDOW_OVERFLOW              0x05
37 #define TT_WINDOW_UNDERFLOW             0x06
38 #define TT_DATA_ACCESS_EXCEPTION        0x09
39 
40 #endif /* ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_ */
41