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Searched defs:PSCCTL1_SET (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1233 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
2719 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
DMIMXRT685S_cm33.h6944 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
8449 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6944 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
8449 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1910 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
4109 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
DMIMXRT595S_cm33.h8148 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10366 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8147 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10365 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8144 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10362 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16932 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
20228 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT735S_hifi1.h10658 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT735S_cm33_core1.h10694 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT735S_cm33_core0.h17487 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h19959 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
21416 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h16932 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
20228 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT798S_hifi1.h10658 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT798S_cm33_core1.h10694 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT798S_hifi4.h17426 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
DMIMXRT798S_cm33_core0.h17487 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h19959 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
21416 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h16932 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member
20228 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT758S_cm33_core1.h10694 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT758S_hifi1.h10658 …__IO uint32_t PSCCTL1_SET; /**< VDD1_SENSE Peripheral Clock Control 1 Set, o… member
DMIMXRT758S_cm33_core0.h17487 …__IO uint32_t PSCCTL1_SET; /**< VDD2_COMP Peripheral Clock Control 1 Set, of… member