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Searched defs:PSCCTL0_SET (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1232 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
2718 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
DMIMXRT685S_cm33.h6943 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
8448 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6943 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
8448 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1909 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
4108 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
DMIMXRT595S_cm33.h8147 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
10365 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8146 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
10364 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8143 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
10361 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16931 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20227 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
21541 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT735S_hifi1.h10657 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
11990 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT735S_cm33_core1.h10693 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
12026 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT735S_cm33_core0.h17486 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20800 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h16931 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20227 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
21541 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT798S_hifi1.h10657 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
11990 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT798S_cm33_core1.h10693 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
12026 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT798S_hifi4.h17425 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20739 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT798S_cm33_core0.h17486 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20800 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h16931 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20227 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
21541 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT758S_cm33_core1.h10693 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
12026 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT758S_hifi1.h10657 …__IO uint32_t PSCCTL0_SET; /**< VDD1_SENSE Peripheral Clock Control 0 Set, o… member
11990 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
DMIMXRT758S_cm33_core0.h17486 …__IO uint32_t PSCCTL0_SET; /**< VDD2_COMP Peripheral Clock Control 0 Set, of… member
20800 …__IO uint32_t PSCCTL0_SET; /**< VDDN_COM Peripheral Clock 0 Set, offset: 0x4… member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h19958 __O uint32_t PSCCTL0_SET; /**< Peripheral clock set 0, offset: 0x40 */ member
21415 __O uint32_t PSCCTL0_SET; /**< Peripheral clock set 0, offset: 0x40 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h19958 __O uint32_t PSCCTL0_SET; /**< Peripheral clock set 0, offset: 0x40 */ member
21415 __O uint32_t PSCCTL0_SET; /**< Peripheral clock set 0, offset: 0x40 */ member