1 /***************************************************************************//** 2 * \file cyip_prot_v2.h 3 * 4 * \brief 5 * PROT IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PROT_V2_H_ 28 #define _CYIP_PROT_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PROT 34 *******************************************************************************/ 35 36 #define PROT_SMPU_SMPU_STRUCT_V2_SECTION_SIZE 0x00000040UL 37 #define PROT_SMPU_V2_SECTION_SIZE 0x00004000UL 38 #define PROT_MPU_MPU_STRUCT_V2_SECTION_SIZE 0x00000020UL 39 #define PROT_MPU_V2_SECTION_SIZE 0x00000400UL 40 #define PROT_V2_SECTION_SIZE 0x00010000UL 41 42 /** 43 * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT) 44 */ 45 typedef struct { 46 __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */ 47 __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */ 48 __IM uint32_t RESERVED[6]; 49 __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */ 50 __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */ 51 __IM uint32_t RESERVED1[6]; 52 } PROT_SMPU_SMPU_STRUCT_V2_Type; /*!< Size = 64 (0x40) */ 53 54 /** 55 * \brief SMPU (PROT_SMPU) 56 */ 57 typedef struct { 58 __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */ 59 __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */ 60 __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */ 61 __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */ 62 __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */ 63 __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */ 64 __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */ 65 __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */ 66 __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */ 67 __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */ 68 __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */ 69 __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */ 70 __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */ 71 __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */ 72 __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */ 73 __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */ 74 __IM uint32_t RESERVED[2032]; 75 PROT_SMPU_SMPU_STRUCT_V2_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */ 76 __IM uint32_t RESERVED1[1536]; 77 } PROT_SMPU_V2_Type; /*!< Size = 16384 (0x4000) */ 78 79 /** 80 * \brief MPU structure (PROT_MPU_MPU_STRUCT) 81 */ 82 typedef struct { 83 __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */ 84 __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */ 85 __IM uint32_t RESERVED[6]; 86 } PROT_MPU_MPU_STRUCT_V2_Type; /*!< Size = 32 (0x20) */ 87 88 /** 89 * \brief MPU (PROT_MPU) 90 */ 91 typedef struct { 92 __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */ 93 __IM uint32_t MS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */ 94 PROT_MPU_MPU_STRUCT_V2_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */ 95 } PROT_MPU_V2_Type; /*!< Size = 1024 (0x400) */ 96 97 /** 98 * \brief Protection (PROT) 99 */ 100 typedef struct { 101 PROT_SMPU_V2_Type SMPU; /*!< 0x00000000 SMPU */ 102 PROT_MPU_V2_Type CYMPU[16]; /*!< 0x00004000 MPU */ 103 } PROT_V2_Type; /*!< Size = 32768 (0x8000) */ 104 105 106 /* PROT_SMPU_SMPU_STRUCT.ADDR0 */ 107 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Pos 0UL 108 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 109 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Pos 8UL 110 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Msk 0xFFFFFF00UL 111 /* PROT_SMPU_SMPU_STRUCT.ATT0 */ 112 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Pos 0UL 113 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Msk 0x1UL 114 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Pos 1UL 115 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Msk 0x2UL 116 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Pos 2UL 117 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Msk 0x4UL 118 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Pos 3UL 119 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Msk 0x8UL 120 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Pos 4UL 121 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Msk 0x10UL 122 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Pos 5UL 123 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Msk 0x20UL 124 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Pos 6UL 125 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Msk 0x40UL 126 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Pos 8UL 127 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Msk 0x100UL 128 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Pos 9UL 129 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 130 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Pos 24UL 131 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Msk 0x1F000000UL 132 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Pos 30UL 133 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Msk 0x40000000UL 134 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Pos 31UL 135 #define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Msk 0x80000000UL 136 /* PROT_SMPU_SMPU_STRUCT.ADDR1 */ 137 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Pos 0UL 138 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 139 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Pos 8UL 140 #define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Msk 0xFFFFFF00UL 141 /* PROT_SMPU_SMPU_STRUCT.ATT1 */ 142 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Pos 0UL 143 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Msk 0x1UL 144 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Pos 1UL 145 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Msk 0x2UL 146 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Pos 2UL 147 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Msk 0x4UL 148 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Pos 3UL 149 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Msk 0x8UL 150 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Pos 4UL 151 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Msk 0x10UL 152 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Pos 5UL 153 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Msk 0x20UL 154 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Pos 6UL 155 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Msk 0x40UL 156 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Pos 8UL 157 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Msk 0x100UL 158 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Pos 9UL 159 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 160 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Pos 24UL 161 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Msk 0x1F000000UL 162 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Pos 30UL 163 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Msk 0x40000000UL 164 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Pos 31UL 165 #define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Msk 0x80000000UL 166 167 168 /* PROT_SMPU.MS0_CTL */ 169 #define PROT_SMPU_V2_MS0_CTL_P_Pos 0UL 170 #define PROT_SMPU_V2_MS0_CTL_P_Msk 0x1UL 171 #define PROT_SMPU_V2_MS0_CTL_NS_Pos 1UL 172 #define PROT_SMPU_V2_MS0_CTL_NS_Msk 0x2UL 173 #define PROT_SMPU_V2_MS0_CTL_PRIO_Pos 8UL 174 #define PROT_SMPU_V2_MS0_CTL_PRIO_Msk 0x300UL 175 #define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Pos 16UL 176 #define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Msk 0x10000UL 177 #define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL 178 #define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 179 /* PROT_SMPU.MS1_CTL */ 180 #define PROT_SMPU_V2_MS1_CTL_P_Pos 0UL 181 #define PROT_SMPU_V2_MS1_CTL_P_Msk 0x1UL 182 #define PROT_SMPU_V2_MS1_CTL_NS_Pos 1UL 183 #define PROT_SMPU_V2_MS1_CTL_NS_Msk 0x2UL 184 #define PROT_SMPU_V2_MS1_CTL_PRIO_Pos 8UL 185 #define PROT_SMPU_V2_MS1_CTL_PRIO_Msk 0x300UL 186 #define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Pos 16UL 187 #define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Msk 0x10000UL 188 #define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL 189 #define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 190 /* PROT_SMPU.MS2_CTL */ 191 #define PROT_SMPU_V2_MS2_CTL_P_Pos 0UL 192 #define PROT_SMPU_V2_MS2_CTL_P_Msk 0x1UL 193 #define PROT_SMPU_V2_MS2_CTL_NS_Pos 1UL 194 #define PROT_SMPU_V2_MS2_CTL_NS_Msk 0x2UL 195 #define PROT_SMPU_V2_MS2_CTL_PRIO_Pos 8UL 196 #define PROT_SMPU_V2_MS2_CTL_PRIO_Msk 0x300UL 197 #define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Pos 16UL 198 #define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Msk 0x10000UL 199 #define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL 200 #define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 201 /* PROT_SMPU.MS3_CTL */ 202 #define PROT_SMPU_V2_MS3_CTL_P_Pos 0UL 203 #define PROT_SMPU_V2_MS3_CTL_P_Msk 0x1UL 204 #define PROT_SMPU_V2_MS3_CTL_NS_Pos 1UL 205 #define PROT_SMPU_V2_MS3_CTL_NS_Msk 0x2UL 206 #define PROT_SMPU_V2_MS3_CTL_PRIO_Pos 8UL 207 #define PROT_SMPU_V2_MS3_CTL_PRIO_Msk 0x300UL 208 #define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Pos 16UL 209 #define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Msk 0x10000UL 210 #define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL 211 #define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 212 /* PROT_SMPU.MS4_CTL */ 213 #define PROT_SMPU_V2_MS4_CTL_P_Pos 0UL 214 #define PROT_SMPU_V2_MS4_CTL_P_Msk 0x1UL 215 #define PROT_SMPU_V2_MS4_CTL_NS_Pos 1UL 216 #define PROT_SMPU_V2_MS4_CTL_NS_Msk 0x2UL 217 #define PROT_SMPU_V2_MS4_CTL_PRIO_Pos 8UL 218 #define PROT_SMPU_V2_MS4_CTL_PRIO_Msk 0x300UL 219 #define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Pos 16UL 220 #define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Msk 0x10000UL 221 #define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL 222 #define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 223 /* PROT_SMPU.MS5_CTL */ 224 #define PROT_SMPU_V2_MS5_CTL_P_Pos 0UL 225 #define PROT_SMPU_V2_MS5_CTL_P_Msk 0x1UL 226 #define PROT_SMPU_V2_MS5_CTL_NS_Pos 1UL 227 #define PROT_SMPU_V2_MS5_CTL_NS_Msk 0x2UL 228 #define PROT_SMPU_V2_MS5_CTL_PRIO_Pos 8UL 229 #define PROT_SMPU_V2_MS5_CTL_PRIO_Msk 0x300UL 230 #define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Pos 16UL 231 #define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Msk 0x10000UL 232 #define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL 233 #define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 234 /* PROT_SMPU.MS6_CTL */ 235 #define PROT_SMPU_V2_MS6_CTL_P_Pos 0UL 236 #define PROT_SMPU_V2_MS6_CTL_P_Msk 0x1UL 237 #define PROT_SMPU_V2_MS6_CTL_NS_Pos 1UL 238 #define PROT_SMPU_V2_MS6_CTL_NS_Msk 0x2UL 239 #define PROT_SMPU_V2_MS6_CTL_PRIO_Pos 8UL 240 #define PROT_SMPU_V2_MS6_CTL_PRIO_Msk 0x300UL 241 #define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Pos 16UL 242 #define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Msk 0x10000UL 243 #define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL 244 #define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 245 /* PROT_SMPU.MS7_CTL */ 246 #define PROT_SMPU_V2_MS7_CTL_P_Pos 0UL 247 #define PROT_SMPU_V2_MS7_CTL_P_Msk 0x1UL 248 #define PROT_SMPU_V2_MS7_CTL_NS_Pos 1UL 249 #define PROT_SMPU_V2_MS7_CTL_NS_Msk 0x2UL 250 #define PROT_SMPU_V2_MS7_CTL_PRIO_Pos 8UL 251 #define PROT_SMPU_V2_MS7_CTL_PRIO_Msk 0x300UL 252 #define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Pos 16UL 253 #define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Msk 0x10000UL 254 #define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL 255 #define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 256 /* PROT_SMPU.MS8_CTL */ 257 #define PROT_SMPU_V2_MS8_CTL_P_Pos 0UL 258 #define PROT_SMPU_V2_MS8_CTL_P_Msk 0x1UL 259 #define PROT_SMPU_V2_MS8_CTL_NS_Pos 1UL 260 #define PROT_SMPU_V2_MS8_CTL_NS_Msk 0x2UL 261 #define PROT_SMPU_V2_MS8_CTL_PRIO_Pos 8UL 262 #define PROT_SMPU_V2_MS8_CTL_PRIO_Msk 0x300UL 263 #define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Pos 16UL 264 #define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Msk 0x10000UL 265 #define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL 266 #define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 267 /* PROT_SMPU.MS9_CTL */ 268 #define PROT_SMPU_V2_MS9_CTL_P_Pos 0UL 269 #define PROT_SMPU_V2_MS9_CTL_P_Msk 0x1UL 270 #define PROT_SMPU_V2_MS9_CTL_NS_Pos 1UL 271 #define PROT_SMPU_V2_MS9_CTL_NS_Msk 0x2UL 272 #define PROT_SMPU_V2_MS9_CTL_PRIO_Pos 8UL 273 #define PROT_SMPU_V2_MS9_CTL_PRIO_Msk 0x300UL 274 #define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Pos 16UL 275 #define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Msk 0x10000UL 276 #define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL 277 #define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 278 /* PROT_SMPU.MS10_CTL */ 279 #define PROT_SMPU_V2_MS10_CTL_P_Pos 0UL 280 #define PROT_SMPU_V2_MS10_CTL_P_Msk 0x1UL 281 #define PROT_SMPU_V2_MS10_CTL_NS_Pos 1UL 282 #define PROT_SMPU_V2_MS10_CTL_NS_Msk 0x2UL 283 #define PROT_SMPU_V2_MS10_CTL_PRIO_Pos 8UL 284 #define PROT_SMPU_V2_MS10_CTL_PRIO_Msk 0x300UL 285 #define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Pos 16UL 286 #define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Msk 0x10000UL 287 #define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL 288 #define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 289 /* PROT_SMPU.MS11_CTL */ 290 #define PROT_SMPU_V2_MS11_CTL_P_Pos 0UL 291 #define PROT_SMPU_V2_MS11_CTL_P_Msk 0x1UL 292 #define PROT_SMPU_V2_MS11_CTL_NS_Pos 1UL 293 #define PROT_SMPU_V2_MS11_CTL_NS_Msk 0x2UL 294 #define PROT_SMPU_V2_MS11_CTL_PRIO_Pos 8UL 295 #define PROT_SMPU_V2_MS11_CTL_PRIO_Msk 0x300UL 296 #define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Pos 16UL 297 #define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Msk 0x10000UL 298 #define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL 299 #define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 300 /* PROT_SMPU.MS12_CTL */ 301 #define PROT_SMPU_V2_MS12_CTL_P_Pos 0UL 302 #define PROT_SMPU_V2_MS12_CTL_P_Msk 0x1UL 303 #define PROT_SMPU_V2_MS12_CTL_NS_Pos 1UL 304 #define PROT_SMPU_V2_MS12_CTL_NS_Msk 0x2UL 305 #define PROT_SMPU_V2_MS12_CTL_PRIO_Pos 8UL 306 #define PROT_SMPU_V2_MS12_CTL_PRIO_Msk 0x300UL 307 #define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Pos 16UL 308 #define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Msk 0x10000UL 309 #define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL 310 #define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 311 /* PROT_SMPU.MS13_CTL */ 312 #define PROT_SMPU_V2_MS13_CTL_P_Pos 0UL 313 #define PROT_SMPU_V2_MS13_CTL_P_Msk 0x1UL 314 #define PROT_SMPU_V2_MS13_CTL_NS_Pos 1UL 315 #define PROT_SMPU_V2_MS13_CTL_NS_Msk 0x2UL 316 #define PROT_SMPU_V2_MS13_CTL_PRIO_Pos 8UL 317 #define PROT_SMPU_V2_MS13_CTL_PRIO_Msk 0x300UL 318 #define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Pos 16UL 319 #define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Msk 0x10000UL 320 #define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL 321 #define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 322 /* PROT_SMPU.MS14_CTL */ 323 #define PROT_SMPU_V2_MS14_CTL_P_Pos 0UL 324 #define PROT_SMPU_V2_MS14_CTL_P_Msk 0x1UL 325 #define PROT_SMPU_V2_MS14_CTL_NS_Pos 1UL 326 #define PROT_SMPU_V2_MS14_CTL_NS_Msk 0x2UL 327 #define PROT_SMPU_V2_MS14_CTL_PRIO_Pos 8UL 328 #define PROT_SMPU_V2_MS14_CTL_PRIO_Msk 0x300UL 329 #define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Pos 16UL 330 #define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Msk 0x10000UL 331 #define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL 332 #define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 333 /* PROT_SMPU.MS15_CTL */ 334 #define PROT_SMPU_V2_MS15_CTL_P_Pos 0UL 335 #define PROT_SMPU_V2_MS15_CTL_P_Msk 0x1UL 336 #define PROT_SMPU_V2_MS15_CTL_NS_Pos 1UL 337 #define PROT_SMPU_V2_MS15_CTL_NS_Msk 0x2UL 338 #define PROT_SMPU_V2_MS15_CTL_PRIO_Pos 8UL 339 #define PROT_SMPU_V2_MS15_CTL_PRIO_Msk 0x300UL 340 #define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Pos 16UL 341 #define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Msk 0x10000UL 342 #define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL 343 #define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 344 345 346 /* PROT_MPU_MPU_STRUCT.ADDR */ 347 #define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Pos 0UL 348 #define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Msk 0xFFUL 349 #define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Pos 8UL 350 #define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Msk 0xFFFFFF00UL 351 /* PROT_MPU_MPU_STRUCT.ATT */ 352 #define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Pos 0UL 353 #define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Msk 0x1UL 354 #define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Pos 1UL 355 #define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Msk 0x2UL 356 #define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Pos 2UL 357 #define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Msk 0x4UL 358 #define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Pos 3UL 359 #define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Msk 0x8UL 360 #define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Pos 4UL 361 #define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Msk 0x10UL 362 #define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Pos 5UL 363 #define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Msk 0x20UL 364 #define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Pos 6UL 365 #define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Msk 0x40UL 366 #define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Pos 24UL 367 #define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Msk 0x1F000000UL 368 #define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Pos 31UL 369 #define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Msk 0x80000000UL 370 371 372 /* PROT_MPU.MS_CTL */ 373 #define PROT_MPU_V2_MS_CTL_PC_Pos 0UL 374 #define PROT_MPU_V2_MS_CTL_PC_Msk 0xFUL 375 #define PROT_MPU_V2_MS_CTL_PC_SAVED_Pos 16UL 376 #define PROT_MPU_V2_MS_CTL_PC_SAVED_Msk 0xF0000UL 377 /* PROT_MPU.MS_CTL_READ_MIR */ 378 #define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Pos 0UL 379 #define PROT_MPU_V2_MS_CTL_READ_MIR_PC_Msk 0xFUL 380 #define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL 381 #define PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL 382 383 384 #endif /* _CYIP_PROT_V2_H_ */ 385 386 387 /* [] END OF FILE */ 388
