1 /***************************************************************************//** 2 * \file cyip_prot.h 3 * 4 * \brief 5 * PROT IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_PROT_H_ 29 #define _CYIP_PROT_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * PROT 35 *******************************************************************************/ 36 37 #define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL 38 #define PROT_SMPU_SECTION_SIZE 0x00004000UL 39 #define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL 40 #define PROT_MPU_SECTION_SIZE 0x00000400UL 41 #define PROT_SECTION_SIZE 0x00010000UL 42 43 /** 44 * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT) 45 */ 46 typedef struct { 47 __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */ 48 __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */ 49 __IM uint32_t RESERVED[6]; 50 __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */ 51 __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */ 52 __IM uint32_t RESERVED1[6]; 53 } PROT_SMPU_SMPU_STRUCT_V1_Type; /*!< Size = 64 (0x40) */ 54 55 /** 56 * \brief SMPU (PROT_SMPU) 57 */ 58 typedef struct { 59 __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */ 60 __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */ 61 __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */ 62 __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */ 63 __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */ 64 __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */ 65 __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */ 66 __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */ 67 __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */ 68 __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */ 69 __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */ 70 __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */ 71 __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */ 72 __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */ 73 __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */ 74 __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */ 75 __IM uint32_t RESERVED[2032]; 76 PROT_SMPU_SMPU_STRUCT_V1_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */ 77 __IM uint32_t RESERVED1[1536]; 78 } PROT_SMPU_V1_Type; /*!< Size = 16384 (0x4000) */ 79 80 /** 81 * \brief MPU structure (PROT_MPU_MPU_STRUCT) 82 */ 83 typedef struct { 84 __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */ 85 __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */ 86 __IM uint32_t RESERVED[6]; 87 } PROT_MPU_MPU_STRUCT_V1_Type; /*!< Size = 32 (0x20) */ 88 89 /** 90 * \brief MPU (PROT_MPU) 91 */ 92 typedef struct { 93 __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */ 94 __IM uint32_t MS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */ 95 PROT_MPU_MPU_STRUCT_V1_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */ 96 } PROT_MPU_V1_Type; /*!< Size = 1024 (0x400) */ 97 98 /** 99 * \brief Protection (PROT) 100 */ 101 typedef struct { 102 PROT_SMPU_V1_Type SMPU; /*!< 0x00000000 SMPU */ 103 PROT_MPU_V1_Type CYMPU[16]; /*!< 0x00004000 MPU */ 104 } PROT_V1_Type; /*!< Size = 32768 (0x8000) */ 105 106 107 /* PROT_SMPU_SMPU_STRUCT.ADDR0 */ 108 #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos 0UL 109 #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 110 #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos 8UL 111 #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk 0xFFFFFF00UL 112 /* PROT_SMPU_SMPU_STRUCT.ATT0 */ 113 #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos 0UL 114 #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk 0x1UL 115 #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos 1UL 116 #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk 0x2UL 117 #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos 2UL 118 #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk 0x4UL 119 #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos 3UL 120 #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk 0x8UL 121 #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos 4UL 122 #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk 0x10UL 123 #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos 5UL 124 #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk 0x20UL 125 #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos 6UL 126 #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk 0x40UL 127 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos 8UL 128 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk 0x100UL 129 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos 9UL 130 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 131 #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos 24UL 132 #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk 0x1F000000UL 133 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos 30UL 134 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk 0x40000000UL 135 #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos 31UL 136 #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk 0x80000000UL 137 /* PROT_SMPU_SMPU_STRUCT.ADDR1 */ 138 #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos 0UL 139 #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 140 #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos 8UL 141 #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk 0xFFFFFF00UL 142 /* PROT_SMPU_SMPU_STRUCT.ATT1 */ 143 #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos 0UL 144 #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk 0x1UL 145 #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos 1UL 146 #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk 0x2UL 147 #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos 2UL 148 #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk 0x4UL 149 #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos 3UL 150 #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk 0x8UL 151 #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos 4UL 152 #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk 0x10UL 153 #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos 5UL 154 #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk 0x20UL 155 #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos 6UL 156 #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk 0x40UL 157 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos 8UL 158 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk 0x100UL 159 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos 9UL 160 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 161 #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos 24UL 162 #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk 0x1F000000UL 163 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos 30UL 164 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk 0x40000000UL 165 #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos 31UL 166 #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk 0x80000000UL 167 168 169 /* PROT_SMPU.MS0_CTL */ 170 #define PROT_SMPU_MS0_CTL_P_Pos 0UL 171 #define PROT_SMPU_MS0_CTL_P_Msk 0x1UL 172 #define PROT_SMPU_MS0_CTL_NS_Pos 1UL 173 #define PROT_SMPU_MS0_CTL_NS_Msk 0x2UL 174 #define PROT_SMPU_MS0_CTL_PRIO_Pos 8UL 175 #define PROT_SMPU_MS0_CTL_PRIO_Msk 0x300UL 176 #define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos 16UL 177 #define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk 0x10000UL 178 #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL 179 #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 180 /* PROT_SMPU.MS1_CTL */ 181 #define PROT_SMPU_MS1_CTL_P_Pos 0UL 182 #define PROT_SMPU_MS1_CTL_P_Msk 0x1UL 183 #define PROT_SMPU_MS1_CTL_NS_Pos 1UL 184 #define PROT_SMPU_MS1_CTL_NS_Msk 0x2UL 185 #define PROT_SMPU_MS1_CTL_PRIO_Pos 8UL 186 #define PROT_SMPU_MS1_CTL_PRIO_Msk 0x300UL 187 #define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos 16UL 188 #define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk 0x10000UL 189 #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL 190 #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 191 /* PROT_SMPU.MS2_CTL */ 192 #define PROT_SMPU_MS2_CTL_P_Pos 0UL 193 #define PROT_SMPU_MS2_CTL_P_Msk 0x1UL 194 #define PROT_SMPU_MS2_CTL_NS_Pos 1UL 195 #define PROT_SMPU_MS2_CTL_NS_Msk 0x2UL 196 #define PROT_SMPU_MS2_CTL_PRIO_Pos 8UL 197 #define PROT_SMPU_MS2_CTL_PRIO_Msk 0x300UL 198 #define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos 16UL 199 #define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk 0x10000UL 200 #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL 201 #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 202 /* PROT_SMPU.MS3_CTL */ 203 #define PROT_SMPU_MS3_CTL_P_Pos 0UL 204 #define PROT_SMPU_MS3_CTL_P_Msk 0x1UL 205 #define PROT_SMPU_MS3_CTL_NS_Pos 1UL 206 #define PROT_SMPU_MS3_CTL_NS_Msk 0x2UL 207 #define PROT_SMPU_MS3_CTL_PRIO_Pos 8UL 208 #define PROT_SMPU_MS3_CTL_PRIO_Msk 0x300UL 209 #define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos 16UL 210 #define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk 0x10000UL 211 #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL 212 #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 213 /* PROT_SMPU.MS4_CTL */ 214 #define PROT_SMPU_MS4_CTL_P_Pos 0UL 215 #define PROT_SMPU_MS4_CTL_P_Msk 0x1UL 216 #define PROT_SMPU_MS4_CTL_NS_Pos 1UL 217 #define PROT_SMPU_MS4_CTL_NS_Msk 0x2UL 218 #define PROT_SMPU_MS4_CTL_PRIO_Pos 8UL 219 #define PROT_SMPU_MS4_CTL_PRIO_Msk 0x300UL 220 #define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos 16UL 221 #define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk 0x10000UL 222 #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL 223 #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 224 /* PROT_SMPU.MS5_CTL */ 225 #define PROT_SMPU_MS5_CTL_P_Pos 0UL 226 #define PROT_SMPU_MS5_CTL_P_Msk 0x1UL 227 #define PROT_SMPU_MS5_CTL_NS_Pos 1UL 228 #define PROT_SMPU_MS5_CTL_NS_Msk 0x2UL 229 #define PROT_SMPU_MS5_CTL_PRIO_Pos 8UL 230 #define PROT_SMPU_MS5_CTL_PRIO_Msk 0x300UL 231 #define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos 16UL 232 #define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk 0x10000UL 233 #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL 234 #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 235 /* PROT_SMPU.MS6_CTL */ 236 #define PROT_SMPU_MS6_CTL_P_Pos 0UL 237 #define PROT_SMPU_MS6_CTL_P_Msk 0x1UL 238 #define PROT_SMPU_MS6_CTL_NS_Pos 1UL 239 #define PROT_SMPU_MS6_CTL_NS_Msk 0x2UL 240 #define PROT_SMPU_MS6_CTL_PRIO_Pos 8UL 241 #define PROT_SMPU_MS6_CTL_PRIO_Msk 0x300UL 242 #define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos 16UL 243 #define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk 0x10000UL 244 #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL 245 #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 246 /* PROT_SMPU.MS7_CTL */ 247 #define PROT_SMPU_MS7_CTL_P_Pos 0UL 248 #define PROT_SMPU_MS7_CTL_P_Msk 0x1UL 249 #define PROT_SMPU_MS7_CTL_NS_Pos 1UL 250 #define PROT_SMPU_MS7_CTL_NS_Msk 0x2UL 251 #define PROT_SMPU_MS7_CTL_PRIO_Pos 8UL 252 #define PROT_SMPU_MS7_CTL_PRIO_Msk 0x300UL 253 #define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos 16UL 254 #define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk 0x10000UL 255 #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL 256 #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 257 /* PROT_SMPU.MS8_CTL */ 258 #define PROT_SMPU_MS8_CTL_P_Pos 0UL 259 #define PROT_SMPU_MS8_CTL_P_Msk 0x1UL 260 #define PROT_SMPU_MS8_CTL_NS_Pos 1UL 261 #define PROT_SMPU_MS8_CTL_NS_Msk 0x2UL 262 #define PROT_SMPU_MS8_CTL_PRIO_Pos 8UL 263 #define PROT_SMPU_MS8_CTL_PRIO_Msk 0x300UL 264 #define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos 16UL 265 #define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk 0x10000UL 266 #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL 267 #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 268 /* PROT_SMPU.MS9_CTL */ 269 #define PROT_SMPU_MS9_CTL_P_Pos 0UL 270 #define PROT_SMPU_MS9_CTL_P_Msk 0x1UL 271 #define PROT_SMPU_MS9_CTL_NS_Pos 1UL 272 #define PROT_SMPU_MS9_CTL_NS_Msk 0x2UL 273 #define PROT_SMPU_MS9_CTL_PRIO_Pos 8UL 274 #define PROT_SMPU_MS9_CTL_PRIO_Msk 0x300UL 275 #define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos 16UL 276 #define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk 0x10000UL 277 #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL 278 #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 279 /* PROT_SMPU.MS10_CTL */ 280 #define PROT_SMPU_MS10_CTL_P_Pos 0UL 281 #define PROT_SMPU_MS10_CTL_P_Msk 0x1UL 282 #define PROT_SMPU_MS10_CTL_NS_Pos 1UL 283 #define PROT_SMPU_MS10_CTL_NS_Msk 0x2UL 284 #define PROT_SMPU_MS10_CTL_PRIO_Pos 8UL 285 #define PROT_SMPU_MS10_CTL_PRIO_Msk 0x300UL 286 #define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos 16UL 287 #define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk 0x10000UL 288 #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL 289 #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 290 /* PROT_SMPU.MS11_CTL */ 291 #define PROT_SMPU_MS11_CTL_P_Pos 0UL 292 #define PROT_SMPU_MS11_CTL_P_Msk 0x1UL 293 #define PROT_SMPU_MS11_CTL_NS_Pos 1UL 294 #define PROT_SMPU_MS11_CTL_NS_Msk 0x2UL 295 #define PROT_SMPU_MS11_CTL_PRIO_Pos 8UL 296 #define PROT_SMPU_MS11_CTL_PRIO_Msk 0x300UL 297 #define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos 16UL 298 #define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk 0x10000UL 299 #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL 300 #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 301 /* PROT_SMPU.MS12_CTL */ 302 #define PROT_SMPU_MS12_CTL_P_Pos 0UL 303 #define PROT_SMPU_MS12_CTL_P_Msk 0x1UL 304 #define PROT_SMPU_MS12_CTL_NS_Pos 1UL 305 #define PROT_SMPU_MS12_CTL_NS_Msk 0x2UL 306 #define PROT_SMPU_MS12_CTL_PRIO_Pos 8UL 307 #define PROT_SMPU_MS12_CTL_PRIO_Msk 0x300UL 308 #define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos 16UL 309 #define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk 0x10000UL 310 #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL 311 #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 312 /* PROT_SMPU.MS13_CTL */ 313 #define PROT_SMPU_MS13_CTL_P_Pos 0UL 314 #define PROT_SMPU_MS13_CTL_P_Msk 0x1UL 315 #define PROT_SMPU_MS13_CTL_NS_Pos 1UL 316 #define PROT_SMPU_MS13_CTL_NS_Msk 0x2UL 317 #define PROT_SMPU_MS13_CTL_PRIO_Pos 8UL 318 #define PROT_SMPU_MS13_CTL_PRIO_Msk 0x300UL 319 #define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos 16UL 320 #define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk 0x10000UL 321 #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL 322 #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 323 /* PROT_SMPU.MS14_CTL */ 324 #define PROT_SMPU_MS14_CTL_P_Pos 0UL 325 #define PROT_SMPU_MS14_CTL_P_Msk 0x1UL 326 #define PROT_SMPU_MS14_CTL_NS_Pos 1UL 327 #define PROT_SMPU_MS14_CTL_NS_Msk 0x2UL 328 #define PROT_SMPU_MS14_CTL_PRIO_Pos 8UL 329 #define PROT_SMPU_MS14_CTL_PRIO_Msk 0x300UL 330 #define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos 16UL 331 #define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk 0x10000UL 332 #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL 333 #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 334 /* PROT_SMPU.MS15_CTL */ 335 #define PROT_SMPU_MS15_CTL_P_Pos 0UL 336 #define PROT_SMPU_MS15_CTL_P_Msk 0x1UL 337 #define PROT_SMPU_MS15_CTL_NS_Pos 1UL 338 #define PROT_SMPU_MS15_CTL_NS_Msk 0x2UL 339 #define PROT_SMPU_MS15_CTL_PRIO_Pos 8UL 340 #define PROT_SMPU_MS15_CTL_PRIO_Msk 0x300UL 341 #define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos 16UL 342 #define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk 0x10000UL 343 #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL 344 #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL 345 346 347 /* PROT_MPU_MPU_STRUCT.ADDR */ 348 #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos 0UL 349 #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk 0xFFUL 350 #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos 8UL 351 #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk 0xFFFFFF00UL 352 /* PROT_MPU_MPU_STRUCT.ATT */ 353 #define PROT_MPU_MPU_STRUCT_ATT_UR_Pos 0UL 354 #define PROT_MPU_MPU_STRUCT_ATT_UR_Msk 0x1UL 355 #define PROT_MPU_MPU_STRUCT_ATT_UW_Pos 1UL 356 #define PROT_MPU_MPU_STRUCT_ATT_UW_Msk 0x2UL 357 #define PROT_MPU_MPU_STRUCT_ATT_UX_Pos 2UL 358 #define PROT_MPU_MPU_STRUCT_ATT_UX_Msk 0x4UL 359 #define PROT_MPU_MPU_STRUCT_ATT_PR_Pos 3UL 360 #define PROT_MPU_MPU_STRUCT_ATT_PR_Msk 0x8UL 361 #define PROT_MPU_MPU_STRUCT_ATT_PW_Pos 4UL 362 #define PROT_MPU_MPU_STRUCT_ATT_PW_Msk 0x10UL 363 #define PROT_MPU_MPU_STRUCT_ATT_PX_Pos 5UL 364 #define PROT_MPU_MPU_STRUCT_ATT_PX_Msk 0x20UL 365 #define PROT_MPU_MPU_STRUCT_ATT_NS_Pos 6UL 366 #define PROT_MPU_MPU_STRUCT_ATT_NS_Msk 0x40UL 367 #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos 24UL 368 #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk 0x1F000000UL 369 #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos 31UL 370 #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk 0x80000000UL 371 372 373 /* PROT_MPU.MS_CTL */ 374 #define PROT_MPU_MS_CTL_PC_Pos 0UL 375 #define PROT_MPU_MS_CTL_PC_Msk 0xFUL 376 #define PROT_MPU_MS_CTL_PC_SAVED_Pos 16UL 377 #define PROT_MPU_MS_CTL_PC_SAVED_Msk 0xF0000UL 378 /* PROT_MPU.MS_CTL_READ_MIR */ 379 #define PROT_MPU_MS_CTL_READ_MIR_PC_Pos 0UL 380 #define PROT_MPU_MS_CTL_READ_MIR_PC_Msk 0xFUL 381 #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL 382 #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL 383 384 385 #endif /* _CYIP_PROT_H_ */ 386 387 388 /* [] END OF FILE */ 389
