1 /***************************************************************************//** 2 * \file ppu_v1.h 3 * \version 1.0 4 * 5 * This file provides the header for ARM PPU driver 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: BSD-3-Clause 13 * 14 * Arm SCP/MCP Software 15 * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. 16 * 17 * SPDX-License-Identifier: BSD-3-Clause 18 *******************************************************************************/ 19 20 21 #ifndef PPU_V1_H 22 #define PPU_V1_H 23 24 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 25 26 /*! 27 * \cond 28 * @{ 29 */ 30 #include <stdbool.h> 31 #include <stdint.h> 32 #include "cy_syslib.h" 33 34 /* 35 * Macro additions by Cypress Semiconductor Corporation 36 */ 37 #define fwk_assert CY_ASSERT 38 #define FWK_SUCCESS CY_RET_SUCCESS 39 40 41 /* 42 * PPU 1.1 register definitions 43 */ 44 struct ppu_v1_reg { 45 __IOM uint32_t PWPR; 46 __IOM uint32_t PMER; 47 __IM uint32_t PWSR; 48 uint32_t RESERVED0; 49 __IM uint32_t DISR; 50 __IM uint32_t MISR; 51 __IM uint32_t STSR; 52 __IOM uint32_t UNLK; 53 __IOM uint32_t PWCR; 54 __IOM uint32_t PTCR; 55 uint32_t RESERVED1[2]; 56 __IOM uint32_t IMR; 57 __IOM uint32_t AIMR; 58 __IOM uint32_t ISR; 59 __IOM uint32_t AISR; 60 __IOM uint32_t IESR; 61 __IOM uint32_t OPSR; 62 uint32_t RESERVED2[2]; 63 __IOM uint32_t FUNRR; 64 __IOM uint32_t FULRR; 65 __IOM uint32_t MEMRR; 66 uint8_t RESERVED3[0x160 - 0x5C]; 67 __IOM uint32_t EDTR0; 68 __IOM uint32_t EDTR1; 69 uint32_t RESERVED4[2]; 70 __IOM uint32_t DCCR0; 71 __IOM uint32_t DCCR1; 72 uint8_t RESERVED5[0xFB0 - 0x178]; 73 __IM uint32_t IDR0; 74 __IM uint32_t IDR1; 75 uint8_t RESERVED6[0xFC8 - 0xFB8]; 76 __IM uint32_t IIDR; 77 __IM uint32_t AIDR; 78 uint8_t RESERVED7[0x1000 - 0xFD0]; 79 }; 80 81 enum ppu_v1_mode { 82 PPU_V1_MODE_OFF = 0, 83 PPU_V1_MODE_OFF_EMU = 1, 84 PPU_V1_MODE_MEM_RET = 2, 85 PPU_V1_MODE_MEM_RET_EMU = 3, 86 PPU_V1_MODE_LOGIC_RET = 4, 87 PPU_V1_MODE_FULL_RET = 5, 88 PPU_V1_MODE_MEM_OFF = 6, 89 PPU_V1_MODE_FUNC_RET = 7, 90 PPU_V1_MODE_ON = 8, 91 PPU_V1_MODE_WARM_RST = 9, 92 PPU_V1_MODE_DBG_RECOV = 10, 93 /* No valid modes after this line */ 94 PPU_V1_MODE_COUNT 95 }; 96 97 enum ppu_v1_opmode { 98 PPU_V1_OPMODE_00, 99 PPU_V1_OPMODE_01, 100 PPU_V1_OPMODE_02, 101 PPU_V1_OPMODE_03, 102 PPU_V1_OPMODE_04, 103 PPU_V1_OPMODE_05, 104 PPU_V1_OPMODE_06, 105 PPU_V1_OPMODE_07, 106 PPU_V1_OPMODE_08, 107 PPU_V1_OPMODE_09, 108 PPU_V1_OPMODE_10, 109 PPU_V1_OPMODE_11, 110 PPU_V1_OPMODE_12, 111 PPU_V1_OPMODE_13, 112 PPU_V1_OPMODE_14, 113 PPU_V1_OPMODE_15, 114 /* No valid operating modes after this line */ 115 PPU_V1_OPMODE_COUNT 116 }; 117 118 enum ppu_v1_op_devactive { 119 PPU_V1_OP_DEVACTIVE_0, 120 PPU_V1_OP_DEVACTIVE_1, 121 PPU_V1_OP_DEVACTIVE_2, 122 PPU_V1_OP_DEVACTIVE_3, 123 PPU_V1_OP_DEVACTIVE_INDEPENDENT_COUNT, 124 PPU_V1_OP_DEVACTIVE_4 = 4, 125 PPU_V1_OP_DEVACTIVE_5, 126 PPU_V1_OP_DEVACTIVE_6, 127 PPU_V1_OP_DEVACTIVE_7, 128 /* No valid operating mode devactive signal number after this line */ 129 PPU_V1_OP_DEVACTIVE_COUNT 130 }; 131 132 /* 133 * Bit definitions for PWPR 134 */ 135 #define PPU_V1_PWPR_PWR_POLICY_POS 0 136 #define PPU_V1_PWPR_OP_POLICY_POS 16 137 138 #define PPU_V1_PWPR_POLICY UINT32_C(0x0000000F) 139 #define PPU_V1_PWPR_DYNAMIC_EN UINT32_C(0x00000100) 140 #define PPU_V1_PWPR_OFF_LOCK_EN UINT32_C(0x00001000) 141 #define PPU_V1_PWPR_OP_POLICY UINT32_C(0x000F0000) 142 #define PPU_V1_PWPR_OP_DYN_EN UINT32_C(0x01000000) 143 144 /* 145 * Bit definitions for PWSR 146 */ 147 #define PPU_V1_PWSR_PWR_STATUS_POS 0 148 #define PPU_V1_PWSR_OP_STATUS_POS 16 149 150 #define PPU_V1_PWSR_PWR_STATUS UINT32_C(0x0000000F) 151 #define PPU_V1_PWSR_PWR_DYN_STATUS UINT32_C(0x00000100) 152 #define PPU_V1_PWSR_OFF_LOCK_STATUS UINT32_C(0x00001000) 153 #define PPU_V1_PWSR_OP_STATUS UINT32_C(0x000F0000) 154 #define PPU_V1_PWSR_OP_DYN_STATUS UINT32_C(0x01000000) 155 156 /* 157 * Bit definitions for DISR 158 */ 159 #define PPU_V1_DISR_PWR_DEVACTIVE_STATUS_POS 0 160 #define PPU_V1_DISR_OP_DEVACTIVE_STATUS_POS 24 161 162 /* 163 * Bit definitions for UNLK 164 */ 165 #define PPU_V1_UNLK_OFF_UNLOCK UINT32_C(0x00000001) 166 167 /* 168 * Bit definitions for PWCR 169 */ 170 #define PPU_V1_PWCR_DEV_REQ_EN UINT32_C(0x000000FF) 171 #define PPU_V1_PWCR_DEV_ACTIVE_EN UINT32_C(0x0007FF00) 172 #define PPU_V1_PWCR_OP_DEV_ACTIVE_EN UINT32_C(0xFF000000) 173 174 /* 175 * Definitions for IESR and OPSR 176 */ 177 enum ppu_v1_edge_sensitivity { 178 PPU_V1_EDGE_SENSITIVITY_MASKED, 179 PPU_V1_EDGE_SENSITIVITY_RISING_EDGE, 180 PPU_V1_EDGE_SENSITIVITY_FALLING_EDGE, 181 PPU_V1_EDGE_SENSITIVITY_BOTH_EDGES, 182 /* No valid edge sensitivity after this line */ 183 PPU_V1_EDGE_SENSITIVITY_COUNT 184 }; 185 186 #define PPU_V1_BITS_PER_EDGE_SENSITIVITY 2 187 #define PPU_V1_EDGE_SENSITIVITY_MASK 0x3 188 189 /* 190 * Bit definitions for IMR 191 */ 192 #define PPU_V1_IMR_MASK UINT32_C(0x0000003F) 193 #define PPU_V1_IMR_STA_POLICY_TRN_IRQ_MASK UINT32_C(0x00000001) 194 #define PPU_V1_IMR_STA_ACCEPT_IRQ_MASK UINT32_C(0x00000002) 195 #define PPU_V1_IMR_STA_DENY_IRQ_MASK UINT32_C(0x00000004) 196 #define PPU_V1_IMR_EMU_ACCEPT_IRQ_MASK UINT32_C(0x00000008) 197 #define PPU_V1_IMR_EMU_DENY_IRQ_MASK UINT32_C(0x00000010) 198 #define PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK UINT32_C(0x00000020) 199 200 /* 201 * Bit definitions for AIMR 202 */ 203 #define PPU_V1_AIMR_MASK UINT32_C(0x0000001F) 204 #define PPU_V1_AIMR_UNSPT_POLICY_IRQ_MASK UINT32_C(0x00000001) 205 #define PPU_V1_AIMR_DYN_ACCEPT_IRQ_MASK UINT32_C(0x00000002) 206 #define PPU_V1_AIMR_DYN_DENY_IRQ_MASK UINT32_C(0x00000004) 207 #define PPU_V1_AIMR_STA_POLICY_PWR_IRQ_MASK UINT32_C(0x00000008) 208 #define PPU_V1_AIMR_STA_POLICY_OP_IRQ_MASK UINT32_C(0x00000010) 209 210 /* 211 * Bit definitions for ISR 212 */ 213 #define PPU_V1_ISR_MASK UINT32_C(0xFF07FFBF) 214 #define PPU_V1_ISR_STA_POLICY_TRN_IRQ UINT32_C(0x00000001) 215 #define PPU_V1_ISR_STA_ACCEPT_IRQ UINT32_C(0x00000002) 216 #define PPU_V1_ISR_STA_DENY_IRQ UINT32_C(0x00000004) 217 #define PPU_V1_ISR_EMU_ACCEPT_IRQ UINT32_C(0x00000008) 218 #define PPU_V1_ISR_EMU_DENY_IRQ UINT32_C(0x00000010) 219 #define PPU_V1_ISR_DYN_POLICY_MIN_IRQ UINT32_C(0x00000020) 220 #define PPU_V1_ISR_OTHER_IRQ UINT32_C(0x00000080) 221 #define PPU_V1_ISR_ACTIVE_EDGE_POS 8 222 #define PPU_V1_ISR_ACTIVE_EDGE_IRQ_MASK UINT32_C(0x0007FF00) 223 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE0_IRQ UINT32_C(0x00000100) 224 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE1_IRQ UINT32_C(0x00000200) 225 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE2_IRQ UINT32_C(0x00000400) 226 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE3_IRQ UINT32_C(0x00000800) 227 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE4_IRQ UINT32_C(0x00001000) 228 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE5_IRQ UINT32_C(0x00002000) 229 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE6_IRQ UINT32_C(0x00004000) 230 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE7_IRQ UINT32_C(0x00008000) 231 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE8_IRQ UINT32_C(0x00010000) 232 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE9_IRQ UINT32_C(0x00020000) 233 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE10_IRQ UINT32_C(0x00040000) 234 #define PPU_V1_ISR_OP_ACTIVE_EDGE_POS 24 235 #define PPU_V1_ISR_OP_ACTIVE_EDGE_IRQ_MASK UINT32_C(0xFF000000) 236 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE0_IRQ UINT32_C(0x01000000) 237 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE1_IRQ UINT32_C(0x02000000) 238 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE2_IRQ UINT32_C(0x04000000) 239 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE3_IRQ UINT32_C(0x08000000) 240 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE4_IRQ UINT32_C(0x10000000) 241 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE5_IRQ UINT32_C(0x20000000) 242 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE6_IRQ UINT32_C(0x40000000) 243 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE7_IRQ UINT32_C(0x80000000) 244 245 /* 246 * Bit definitions for AISR 247 */ 248 #define PPU_V1_AISR_MASK UINT32_C(0x0000001F) 249 #define PPU_V1_AISR_UNSPT_POLICY_IRQ UINT32_C(0x00000001) 250 #define PPU_V1_AISR_DYN_ACCEPT_IRQ UINT32_C(0x00000002) 251 #define PPU_V1_AISR_DYN_DENY_IRQ UINT32_C(0x00000004) 252 #define PPU_V1_AISR_STA_POLICY_PWR_IRQ UINT32_C(0x00000008) 253 #define PPU_V1_AISR_STA_POLICY_OP_IRQ UINT32_C(0x00000010) 254 255 256 /* 257 * Bit definitions for MISR 258 */ 259 #define PPU_V1_MISR_DEVDENY_STATUS_POS 16 260 #define PPU_V1_MISR_DEVDENY_STATUS_MASK UINT32_C(0x00FF0000) 261 262 /* 263 * Bit definitions for AIDR 264 */ 265 #define PPU_V1_AIDR_ARCH_REV_MINOR UINT32_C(0x0000000F) 266 #define PPU_V1_AIDR_ARCH_REV_MAJOR UINT32_C(0x000000F0) 267 268 /* 269 * Definitions for PPU Arch version ID 270 */ 271 #define PPU_V1_ARCH_ID 0x11 272 273 /* 274 * Bit definitions for IDR0 275 */ 276 #define PPU_V1_IDR0_NUM_OPMODE_POS 4 277 #define PPU_V1_IDR0_NUM_OPMODE UINT32_C(0x000000F0) 278 279 /* 280 * Initializes the PPU by masking all interrupts and acknowledging any 281 * previously pending interrupt. 282 */ 283 void ppu_v1_init(struct ppu_v1_reg *ppu); 284 285 /* 286 * Set PPU's power mode and wait for the transition. 287 * Note: This function currently supports only synchronous transitions with 288 * limited error detection. 289 */ 290 int ppu_v1_set_power_mode(struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode); 291 292 /* 293 * Request PPU's power mode and don't wait for the transition. 294 */ 295 int ppu_v1_request_power_mode(struct ppu_v1_reg *ppu, 296 enum ppu_v1_mode ppu_mode); 297 298 /* 299 * Request a change to the PPU's operating mode. 300 */ 301 int ppu_v1_request_operating_mode(struct ppu_v1_reg *ppu, 302 enum ppu_v1_opmode op_mode); 303 304 /* 305 * Enable PPU's dynamic operating mode transitions 306 */ 307 void ppu_v1_opmode_dynamic_enable(struct ppu_v1_reg *ppu, 308 enum ppu_v1_opmode min_dyn_mode); 309 310 /* 311 * Enable PPU's dynamic power mode transitions 312 */ 313 void ppu_v1_dynamic_enable(struct ppu_v1_reg *ppu, 314 enum ppu_v1_mode min_dyn_state); 315 316 /* 317 * Enable the lock in the OFF state 318 */ 319 void ppu_v1_lock_off_enable(struct ppu_v1_reg *ppu); 320 321 /* 322 * Disable the lock in the OFF state 323 */ 324 void ppu_v1_lock_off_disable(struct ppu_v1_reg *ppu); 325 326 /* 327 * Get the current power mode. 328 */ 329 enum ppu_v1_mode ppu_v1_get_power_mode(struct ppu_v1_reg *ppu); 330 331 /* 332 * Get the current programmed power policy mode. 333 */ 334 enum ppu_v1_mode ppu_v1_get_programmed_power_mode(struct ppu_v1_reg *ppu); 335 336 /* 337 * Get the current operating mode. 338 */ 339 enum ppu_v1_opmode ppu_v1_get_operating_mode(struct ppu_v1_reg *ppu); 340 341 /* 342 * Get the current programmed operating mode policy. 343 */ 344 enum ppu_v1_opmode ppu_v1_get_programmed_operating_mode(struct ppu_v1_reg *ppu); 345 346 /* 347 * Check whether the dynamic transitions are enabled or not. 348 */ 349 bool ppu_v1_is_dynamic_enabled(struct ppu_v1_reg *ppu); 350 351 /* 352 * Check whether the locked in the MEM_RET or OFF state. 353 */ 354 bool ppu_v1_is_locked(struct ppu_v1_reg *ppu); 355 356 /* 357 * Check if the DEVACTIVE signal associated to a power mode is high. 358 */ 359 bool ppu_v1_is_power_devactive_high(struct ppu_v1_reg *ppu, 360 enum ppu_v1_mode ppu_mode); 361 362 /* 363 * Check if the DEVACTIVE signal associated to an operating mode is high. 364 */ 365 bool ppu_v1_is_op_devactive_high(struct ppu_v1_reg *ppu, 366 enum ppu_v1_op_devactive op_devactive); 367 368 /* 369 * Unlock the power domain from the OFF power mode. 370 */ 371 void ppu_v1_off_unlock(struct ppu_v1_reg *ppu); 372 373 /* 374 * Disable the check of the DEVACTIVE signals by the PPU logic for state 375 * transition. 376 */ 377 void ppu_v1_disable_devactive(struct ppu_v1_reg *ppu); 378 379 /* 380 * Disable the handshake with the P-channel or the Q-channels 381 */ 382 void ppu_v1_disable_handshake(struct ppu_v1_reg *ppu); 383 384 /* 385 * Set one or more bits of the interrupt mask register. 386 */ 387 void ppu_v1_interrupt_mask(struct ppu_v1_reg *ppu, unsigned int mask); 388 389 /* 390 * Set one or more bits of the additional interrupt mask register. 391 */ 392 void ppu_v1_additional_interrupt_mask(struct ppu_v1_reg *ppu, 393 unsigned int mask); 394 395 /* 396 * Clear one or more bits of the interrupt mask register. 397 */ 398 void ppu_v1_interrupt_unmask(struct ppu_v1_reg *ppu, unsigned int mask); 399 400 /* 401 * Clear one or more bits of the additional interrupt mask register. 402 */ 403 void ppu_v1_additional_interrupt_unmask(struct ppu_v1_reg *ppu, 404 unsigned int mask); 405 406 /* 407 * Check if some additional interrupts are pending. 408 */ 409 bool ppu_v1_is_additional_interrupt_pending(struct ppu_v1_reg *ppu, 410 unsigned int mask); 411 412 /* 413 * Acknowledge one or more interrupts. 414 */ 415 void ppu_v1_ack_interrupt(struct ppu_v1_reg *ppu, unsigned int mask); 416 417 /* 418 * Acknowledge one or more additional interrupts. 419 */ 420 void ppu_v1_ack_additional_interrupt(struct ppu_v1_reg *ppu, unsigned int mask); 421 422 /* 423 * Set input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the 424 * available sensitivities. 425 */ 426 void ppu_v1_set_input_edge_sensitivity(struct ppu_v1_reg *ppu, 427 enum ppu_v1_mode ppu_mode, enum ppu_v1_edge_sensitivity edge_sensitivity); 428 429 /* 430 * Get input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the 431 * available sensitivities. 432 */ 433 enum ppu_v1_edge_sensitivity ppu_v1_get_input_edge_sensitivity( 434 struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode); 435 436 /* 437 * Acknowledge a power active edge interrupt. 438 */ 439 void ppu_v1_ack_power_active_edge_interrupt(struct ppu_v1_reg *ppu, 440 enum ppu_v1_mode ppu_mode); 441 442 /* 443 * Check if a power active edge interrupt is pending. 444 */ 445 bool ppu_v1_is_power_active_edge_interrupt(struct ppu_v1_reg *ppu, 446 enum ppu_v1_mode ppu_mode); 447 448 /* 449 * Set operating mode active edge sensitivity. See 450 * 'enum ppu_v1_edge_sensitivity' for the available sensitivities. 451 */ 452 void ppu_v1_set_op_active_edge_sensitivity(struct ppu_v1_reg *ppu, 453 enum ppu_v1_op_devactive op_devactive, 454 enum ppu_v1_edge_sensitivity edge_sensitivity); 455 456 /* 457 * Get operating mode active edge sensitivity. 458 * See 'enum ppu_v1_edge_sensitivity for the available sensitivities. 459 */ 460 enum ppu_v1_edge_sensitivity ppu_v1_get_op_active_edge_sensitivity( 461 struct ppu_v1_reg *ppu, enum ppu_v1_op_devactive op_devactive); 462 463 /* 464 * Acknowledge operating mode active edge interrupt. 465 */ 466 void ppu_v1_ack_op_active_edge_interrupt(struct ppu_v1_reg *ppu, 467 enum ppu_v1_op_devactive op_devactive); 468 469 /* 470 * Check if an operating mode active edge interrupt is pending. 471 */ 472 bool ppu_v1_is_op_active_edge_interrupt(struct ppu_v1_reg *ppu, 473 enum ppu_v1_op_devactive op_devactive); 474 475 /* 476 * Check if the DYN input edge interrupt is pending. 477 */ 478 bool ppu_v1_is_dyn_policy_min_interrupt(struct ppu_v1_reg *ppu); 479 480 /* 481 * Get the number of operating modes. 482 */ 483 unsigned int ppu_v1_get_num_opmode(struct ppu_v1_reg *ppu); 484 485 /* 486 * Get the PPU architecture ID. 487 */ 488 unsigned int ppu_v1_get_arch_id(struct ppu_v1_reg *ppu); 489 490 /* 491 * Get the ID(s) of device that denied Deepsleep 492 */ 493 unsigned int ppu_v1_get_failure_device_id(struct ppu_v1_reg *ppu); 494 495 /*! 496 * \endcond 497 * @} 498 */ 499 #endif /* CY_IP_MXS40SRSS || CY_IP_MXS40SSRSS*/ 500 501 #endif /* PPU_V1_H */ 502
