1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _ADDRESSMAP_H 9 #define _ADDRESSMAP_H 10 11 /** 12 * \file rp2350/addressmap.h 13 */ 14 15 #include "hardware/platform_defs.h" 16 17 // Register address offsets for atomic RMW aliases 18 #define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) 19 #define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) 20 #define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) 21 #define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) 22 23 #define ROM_BASE _u(0x00000000) 24 #define XIP_BASE _u(0x10000000) 25 #define XIP_SRAM_BASE _u(0x13ffc000) 26 #define XIP_END _u(0x14000000) 27 #define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000) 28 #define XIP_SRAM_END _u(0x14000000) 29 #define XIP_NOCACHE_NOALLOC_END _u(0x18000000) 30 #define XIP_MAINTENANCE_BASE _u(0x18000000) 31 #define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000) 32 #define SRAM0_BASE _u(0x20000000) 33 #define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000) 34 #define SRAM_BASE _u(0x20000000) 35 #define SRAM_STRIPED_BASE _u(0x20000000) 36 #define SRAM4_BASE _u(0x20040000) 37 #define SRAM8_BASE _u(0x20080000) 38 #define SRAM_STRIPED_END _u(0x20080000) 39 #define SRAM_SCRATCH_X_BASE _u(0x20080000) 40 #define SRAM9_BASE _u(0x20081000) 41 #define SRAM_SCRATCH_Y_BASE _u(0x20081000) 42 #define SRAM_END _u(0x20082000) 43 #define SYSINFO_BASE _u(0x40000000) 44 #define SYSCFG_BASE _u(0x40008000) 45 #define CLOCKS_BASE _u(0x40010000) 46 #define PSM_BASE _u(0x40018000) 47 #define RESETS_BASE _u(0x40020000) 48 #define IO_BANK0_BASE _u(0x40028000) 49 #define IO_QSPI_BASE _u(0x40030000) 50 #define PADS_BANK0_BASE _u(0x40038000) 51 #define PADS_QSPI_BASE _u(0x40040000) 52 #define XOSC_BASE _u(0x40048000) 53 #define PLL_SYS_BASE _u(0x40050000) 54 #define PLL_USB_BASE _u(0x40058000) 55 #define ACCESSCTRL_BASE _u(0x40060000) 56 #define BUSCTRL_BASE _u(0x40068000) 57 #define UART0_BASE _u(0x40070000) 58 #define UART1_BASE _u(0x40078000) 59 #define SPI0_BASE _u(0x40080000) 60 #define SPI1_BASE _u(0x40088000) 61 #define I2C0_BASE _u(0x40090000) 62 #define I2C1_BASE _u(0x40098000) 63 #define ADC_BASE _u(0x400a0000) 64 #define PWM_BASE _u(0x400a8000) 65 #define TIMER0_BASE _u(0x400b0000) 66 #define TIMER1_BASE _u(0x400b8000) 67 #define HSTX_CTRL_BASE _u(0x400c0000) 68 #define XIP_CTRL_BASE _u(0x400c8000) 69 #define XIP_QMI_BASE _u(0x400d0000) 70 #define WATCHDOG_BASE _u(0x400d8000) 71 #define BOOTRAM_BASE _u(0x400e0000) 72 #define BOOTRAM_END _u(0x400e0400) 73 #define ROSC_BASE _u(0x400e8000) 74 #define TRNG_BASE _u(0x400f0000) 75 #define SHA256_BASE _u(0x400f8000) 76 #define POWMAN_BASE _u(0x40100000) 77 #define TICKS_BASE _u(0x40108000) 78 #define OTP_BASE _u(0x40120000) 79 #define OTP_DATA_BASE _u(0x40130000) 80 #define OTP_DATA_RAW_BASE _u(0x40134000) 81 #define OTP_DATA_GUARDED_BASE _u(0x40138000) 82 #define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000) 83 #define CORESIGHT_PERIPH_BASE _u(0x40140000) 84 #define CORESIGHT_ROMTABLE_BASE _u(0x40140000) 85 #define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000) 86 #define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000) 87 #define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000) 88 #define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000) 89 #define CORESIGHT_TPIU_BASE _u(0x40148000) 90 #define CORESIGHT_CTI_BASE _u(0x40149000) 91 #define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000) 92 #define DFT_BASE _u(0x40150000) 93 #define GLITCH_DETECTOR_BASE _u(0x40158000) 94 #define TBMAN_BASE _u(0x40160000) 95 #define DMA_BASE _u(0x50000000) 96 #define USBCTRL_BASE _u(0x50100000) 97 #define USBCTRL_DPRAM_BASE _u(0x50100000) 98 #define USBCTRL_REGS_BASE _u(0x50110000) 99 #define PIO0_BASE _u(0x50200000) 100 #define PIO1_BASE _u(0x50300000) 101 #define PIO2_BASE _u(0x50400000) 102 #define XIP_AUX_BASE _u(0x50500000) 103 #define HSTX_FIFO_BASE _u(0x50600000) 104 #define CORESIGHT_TRACE_BASE _u(0x50700000) 105 #define SIO_BASE _u(0xd0000000) 106 #define SIO_NONSEC_BASE _u(0xd0020000) 107 #define PPB_BASE _u(0xe0000000) 108 #define PPB_NONSEC_BASE _u(0xe0020000) 109 #define EPPB_BASE _u(0xe0080000) 110 111 #endif // _ADDRESSMAP_H 112 113
